piixpm.c revision 1.35
1 /* $NetBSD: piixpm.c,v 1.35 2011/02/13 11:20:12 hannken Exp $ */ 2 /* $OpenBSD: piixpm.c,v 1.20 2006/02/27 08:25:02 grange Exp $ */ 3 4 /* 5 * Copyright (c) 2005, 2006 Alexander Yurchenko <grange (at) openbsd.org> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 /* 21 * Intel PIIX and compatible Power Management controller driver. 22 */ 23 24 #include <sys/cdefs.h> 25 __KERNEL_RCSID(0, "$NetBSD: piixpm.c,v 1.35 2011/02/13 11:20:12 hannken Exp $"); 26 27 #include <sys/param.h> 28 #include <sys/systm.h> 29 #include <sys/device.h> 30 #include <sys/kernel.h> 31 #include <sys/rwlock.h> 32 #include <sys/proc.h> 33 34 #include <sys/bus.h> 35 36 #include <dev/pci/pcidevs.h> 37 #include <dev/pci/pcireg.h> 38 #include <dev/pci/pcivar.h> 39 40 #include <dev/pci/piixpmreg.h> 41 42 #include <dev/i2c/i2cvar.h> 43 44 #include <dev/ic/acpipmtimer.h> 45 46 #ifdef PIIXPM_DEBUG 47 #define DPRINTF(x) printf x 48 #else 49 #define DPRINTF(x) 50 #endif 51 52 #define PIIXPM_IS_CSB5(id) \ 53 (PCI_VENDOR((id)) == PCI_VENDOR_SERVERWORKS && \ 54 PCI_PRODUCT((id)) == PCI_PRODUCT_SERVERWORKS_CSB5) 55 #define PIIXPM_DELAY 200 56 #define PIIXPM_TIMEOUT 1 57 58 struct piixpm_softc { 59 device_t sc_dev; 60 61 bus_space_tag_t sc_smb_iot; 62 bus_space_handle_t sc_smb_ioh; 63 void * sc_smb_ih; 64 int sc_poll; 65 66 bus_space_tag_t sc_pm_iot; 67 bus_space_handle_t sc_pm_ioh; 68 69 pci_chipset_tag_t sc_pc; 70 pcitag_t sc_pcitag; 71 pcireg_t sc_id; 72 73 struct i2c_controller sc_i2c_tag; 74 krwlock_t sc_i2c_rwlock; 75 struct { 76 i2c_op_t op; 77 void * buf; 78 size_t len; 79 int flags; 80 volatile int error; 81 } sc_i2c_xfer; 82 83 pcireg_t sc_devact[2]; 84 }; 85 86 static int piixpm_match(device_t, cfdata_t, void *); 87 static void piixpm_attach(device_t, device_t, void *); 88 89 static bool piixpm_suspend(device_t, const pmf_qual_t *); 90 static bool piixpm_resume(device_t, const pmf_qual_t *); 91 92 static void piixpm_csb5_reset(void *); 93 static int piixpm_i2c_acquire_bus(void *, int); 94 static void piixpm_i2c_release_bus(void *, int); 95 static int piixpm_i2c_exec(void *, i2c_op_t, i2c_addr_t, const void *, 96 size_t, void *, size_t, int); 97 98 static int piixpm_intr(void *); 99 100 CFATTACH_DECL_NEW(piixpm, sizeof(struct piixpm_softc), 101 piixpm_match, piixpm_attach, NULL, NULL); 102 103 static int 104 piixpm_match(device_t parent, cfdata_t match, void *aux) 105 { 106 struct pci_attach_args *pa; 107 108 pa = (struct pci_attach_args *)aux; 109 switch (PCI_VENDOR(pa->pa_id)) { 110 case PCI_VENDOR_INTEL: 111 switch (PCI_PRODUCT(pa->pa_id)) { 112 case PCI_PRODUCT_INTEL_82371AB_PMC: 113 case PCI_PRODUCT_INTEL_82440MX_PMC: 114 return 1; 115 } 116 break; 117 case PCI_VENDOR_ATI: 118 switch (PCI_PRODUCT(pa->pa_id)) { 119 case PCI_PRODUCT_ATI_SB200_SMB: 120 case PCI_PRODUCT_ATI_SB300_SMB: 121 case PCI_PRODUCT_ATI_SB400_SMB: 122 case PCI_PRODUCT_ATI_SB600_SMB: /* matches SB600/SB700/SB800 */ 123 return 1; 124 } 125 break; 126 case PCI_VENDOR_SERVERWORKS: 127 switch (PCI_PRODUCT(pa->pa_id)) { 128 case PCI_PRODUCT_SERVERWORKS_OSB4: 129 case PCI_PRODUCT_SERVERWORKS_CSB5: 130 case PCI_PRODUCT_SERVERWORKS_CSB6: 131 case PCI_PRODUCT_SERVERWORKS_HT1000SB: 132 return 1; 133 } 134 } 135 136 return 0; 137 } 138 139 static void 140 piixpm_attach(device_t parent, device_t self, void *aux) 141 { 142 struct piixpm_softc *sc = device_private(self); 143 struct pci_attach_args *pa = aux; 144 struct i2cbus_attach_args iba; 145 pcireg_t base, conf; 146 pcireg_t pmmisc; 147 pci_intr_handle_t ih; 148 char devinfo[256]; 149 const char *intrstr = NULL; 150 151 sc->sc_dev = self; 152 sc->sc_id = pa->pa_id; 153 sc->sc_pc = pa->pa_pc; 154 sc->sc_pcitag = pa->pa_tag; 155 156 aprint_naive("\n"); 157 aprint_normal("\n"); 158 159 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo, sizeof(devinfo)); 160 aprint_normal_dev(self, "%s (rev. 0x%02x)\n", devinfo, 161 PCI_REVISION(pa->pa_class)); 162 163 if (!pmf_device_register(self, piixpm_suspend, piixpm_resume)) 164 aprint_error_dev(self, "couldn't establish power handler\n"); 165 166 /* Read configuration */ 167 conf = pci_conf_read(pa->pa_pc, pa->pa_tag, PIIX_SMB_HOSTC); 168 DPRINTF(("%s: conf 0x%x\n", device_xname(self), conf)); 169 170 if ((PCI_VENDOR(pa->pa_id) != PCI_VENDOR_INTEL) || 171 (PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_INTEL_82371AB_PMC)) 172 goto nopowermanagement; 173 174 /* check whether I/O access to PM regs is enabled */ 175 pmmisc = pci_conf_read(pa->pa_pc, pa->pa_tag, PIIX_PMREGMISC); 176 if (!(pmmisc & 1)) 177 goto nopowermanagement; 178 179 sc->sc_pm_iot = pa->pa_iot; 180 /* Map I/O space */ 181 base = pci_conf_read(pa->pa_pc, pa->pa_tag, PIIX_PM_BASE); 182 if (bus_space_map(sc->sc_pm_iot, PCI_MAPREG_IO_ADDR(base), 183 PIIX_PM_SIZE, 0, &sc->sc_pm_ioh)) { 184 aprint_error_dev(self, "can't map power management I/O space\n"); 185 goto nopowermanagement; 186 } 187 188 /* 189 * Revision 0 and 1 are PIIX4, 2 is PIIX4E, 3 is PIIX4M. 190 * PIIX4 and PIIX4E have a bug in the timer latch, see Errata #20 191 * in the "Specification update" (document #297738). 192 */ 193 acpipmtimer_attach(self, sc->sc_pm_iot, sc->sc_pm_ioh, 194 PIIX_PM_PMTMR, 195 (PCI_REVISION(pa->pa_class) < 3) ? ACPIPMT_BADLATCH : 0 ); 196 197 nopowermanagement: 198 if ((conf & PIIX_SMB_HOSTC_HSTEN) == 0) { 199 aprint_normal_dev(self, "SMBus disabled\n"); 200 return; 201 } 202 203 /* Map I/O space */ 204 sc->sc_smb_iot = pa->pa_iot; 205 base = pci_conf_read(pa->pa_pc, pa->pa_tag, PIIX_SMB_BASE) & 0xffff; 206 if (bus_space_map(sc->sc_smb_iot, PCI_MAPREG_IO_ADDR(base), 207 PIIX_SMB_SIZE, 0, &sc->sc_smb_ioh)) { 208 aprint_error_dev(self, "can't map smbus I/O space\n"); 209 return; 210 } 211 212 sc->sc_poll = 1; 213 aprint_normal_dev(self, ""); 214 if ((conf & PIIX_SMB_HOSTC_INTMASK) == PIIX_SMB_HOSTC_SMI) { 215 /* No PCI IRQ */ 216 aprint_normal("interrupting at SMI, "); 217 } else if ((conf & PIIX_SMB_HOSTC_INTMASK) == PIIX_SMB_HOSTC_IRQ) { 218 /* Install interrupt handler */ 219 if (pci_intr_map(pa, &ih) == 0) { 220 intrstr = pci_intr_string(pa->pa_pc, ih); 221 sc->sc_smb_ih = pci_intr_establish(pa->pa_pc, ih, IPL_BIO, 222 piixpm_intr, sc); 223 if (sc->sc_smb_ih != NULL) { 224 aprint_normal("interrupting at %s", intrstr); 225 sc->sc_poll = 0; 226 } 227 } 228 } 229 if (sc->sc_poll) 230 aprint_normal("polling"); 231 232 aprint_normal("\n"); 233 234 /* Attach I2C bus */ 235 rw_init(&sc->sc_i2c_rwlock); 236 sc->sc_i2c_tag.ic_cookie = sc; 237 sc->sc_i2c_tag.ic_acquire_bus = piixpm_i2c_acquire_bus; 238 sc->sc_i2c_tag.ic_release_bus = piixpm_i2c_release_bus; 239 sc->sc_i2c_tag.ic_exec = piixpm_i2c_exec; 240 241 memset(&iba, 0, sizeof(iba)); 242 iba.iba_type = I2C_TYPE_SMBUS; 243 iba.iba_tag = &sc->sc_i2c_tag; 244 config_found_ia(self, "i2cbus", &iba, iicbus_print); 245 246 return; 247 } 248 249 static bool 250 piixpm_suspend(device_t dv, const pmf_qual_t *qual) 251 { 252 struct piixpm_softc *sc = device_private(dv); 253 254 sc->sc_devact[0] = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 255 PIIX_DEVACTA); 256 sc->sc_devact[1] = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 257 PIIX_DEVACTB); 258 259 return true; 260 } 261 262 static bool 263 piixpm_resume(device_t dv, const pmf_qual_t *qual) 264 { 265 struct piixpm_softc *sc = device_private(dv); 266 267 pci_conf_write(sc->sc_pc, sc->sc_pcitag, PIIX_DEVACTA, 268 sc->sc_devact[0]); 269 pci_conf_write(sc->sc_pc, sc->sc_pcitag, PIIX_DEVACTB, 270 sc->sc_devact[1]); 271 272 return true; 273 } 274 275 static void 276 piixpm_csb5_reset(void *arg) 277 { 278 struct piixpm_softc *sc = arg; 279 pcireg_t base, hostc, pmbase; 280 281 base = pci_conf_read(sc->sc_pc, sc->sc_pcitag, PIIX_SMB_BASE); 282 hostc = pci_conf_read(sc->sc_pc, sc->sc_pcitag, PIIX_SMB_HOSTC); 283 284 pmbase = pci_conf_read(sc->sc_pc, sc->sc_pcitag, PIIX_PM_BASE); 285 pmbase |= PIIX_PM_BASE_CSB5_RESET; 286 pci_conf_write(sc->sc_pc, sc->sc_pcitag, PIIX_PM_BASE, pmbase); 287 pmbase &= ~PIIX_PM_BASE_CSB5_RESET; 288 pci_conf_write(sc->sc_pc, sc->sc_pcitag, PIIX_PM_BASE, pmbase); 289 290 pci_conf_write(sc->sc_pc, sc->sc_pcitag, PIIX_SMB_BASE, base); 291 pci_conf_write(sc->sc_pc, sc->sc_pcitag, PIIX_SMB_HOSTC, hostc); 292 293 (void) tsleep(&sc, PRIBIO, "csb5reset", hz/2); 294 } 295 296 static int 297 piixpm_i2c_acquire_bus(void *cookie, int flags) 298 { 299 struct piixpm_softc *sc = cookie; 300 301 if (cold || sc->sc_poll || (flags & I2C_F_POLL)) 302 return (0); 303 304 rw_enter(&sc->sc_i2c_rwlock, RW_WRITER); 305 return 0; 306 } 307 308 static void 309 piixpm_i2c_release_bus(void *cookie, int flags) 310 { 311 struct piixpm_softc *sc = cookie; 312 313 if (cold || sc->sc_poll || (flags & I2C_F_POLL)) 314 return; 315 316 rw_exit(&sc->sc_i2c_rwlock); 317 } 318 319 static int 320 piixpm_i2c_exec(void *cookie, i2c_op_t op, i2c_addr_t addr, 321 const void *cmdbuf, size_t cmdlen, void *buf, size_t len, int flags) 322 { 323 struct piixpm_softc *sc = cookie; 324 const u_int8_t *b; 325 u_int8_t ctl = 0, st; 326 int retries; 327 328 DPRINTF(("%s: exec: op %d, addr 0x%x, cmdlen %zu, len %zu, flags 0x%x\n", 329 device_xname(sc->sc_dev), op, addr, cmdlen, len, flags)); 330 331 /* Wait for bus to be idle */ 332 for (retries = 100; retries > 0; retries--) { 333 st = bus_space_read_1(sc->sc_smb_iot, sc->sc_smb_ioh, 334 PIIX_SMB_HS); 335 if (!(st & PIIX_SMB_HS_BUSY)) 336 break; 337 DELAY(PIIXPM_DELAY); 338 } 339 DPRINTF(("%s: exec: st 0x%d\n", device_xname(sc->sc_dev), st & 0xff)); 340 if (st & PIIX_SMB_HS_BUSY) 341 return (1); 342 343 if (cold || sc->sc_poll) 344 flags |= I2C_F_POLL; 345 346 if (!I2C_OP_STOP_P(op) || cmdlen > 1 || len > 2 || 347 (cmdlen == 0 && len > 1)) 348 return (1); 349 350 /* Setup transfer */ 351 sc->sc_i2c_xfer.op = op; 352 sc->sc_i2c_xfer.buf = buf; 353 sc->sc_i2c_xfer.len = len; 354 sc->sc_i2c_xfer.flags = flags; 355 sc->sc_i2c_xfer.error = 0; 356 357 /* Set slave address and transfer direction */ 358 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_TXSLVA, 359 PIIX_SMB_TXSLVA_ADDR(addr) | 360 (I2C_OP_READ_P(op) ? PIIX_SMB_TXSLVA_READ : 0)); 361 362 b = cmdbuf; 363 if (cmdlen > 0) 364 /* Set command byte */ 365 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, 366 PIIX_SMB_HCMD, b[0]); 367 368 if (I2C_OP_WRITE_P(op)) { 369 /* Write data */ 370 b = buf; 371 if (cmdlen == 0 && len == 1) 372 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, 373 PIIX_SMB_HCMD, b[0]); 374 else if (len > 0) 375 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, 376 PIIX_SMB_HD0, b[0]); 377 if (len > 1) 378 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, 379 PIIX_SMB_HD1, b[1]); 380 } 381 382 /* Set SMBus command */ 383 if (cmdlen == 0) { 384 if (len == 0) 385 ctl = PIIX_SMB_HC_CMD_QUICK; 386 else 387 ctl = PIIX_SMB_HC_CMD_BYTE; 388 } else if (len == 1) 389 ctl = PIIX_SMB_HC_CMD_BDATA; 390 else if (len == 2) 391 ctl = PIIX_SMB_HC_CMD_WDATA; 392 393 if ((flags & I2C_F_POLL) == 0) 394 ctl |= PIIX_SMB_HC_INTREN; 395 396 /* Start transaction */ 397 ctl |= PIIX_SMB_HC_START; 398 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_HC, ctl); 399 400 if (flags & I2C_F_POLL) { 401 /* Poll for completion */ 402 if (PIIXPM_IS_CSB5(sc->sc_id)) 403 DELAY(2*PIIXPM_DELAY); 404 else 405 DELAY(PIIXPM_DELAY); 406 for (retries = 1000; retries > 0; retries--) { 407 st = bus_space_read_1(sc->sc_smb_iot, sc->sc_smb_ioh, 408 PIIX_SMB_HS); 409 if ((st & PIIX_SMB_HS_BUSY) == 0) 410 break; 411 DELAY(PIIXPM_DELAY); 412 } 413 if (st & PIIX_SMB_HS_BUSY) 414 goto timeout; 415 piixpm_intr(sc); 416 } else { 417 /* Wait for interrupt */ 418 if (tsleep(sc, PRIBIO, "iicexec", PIIXPM_TIMEOUT * hz)) 419 goto timeout; 420 } 421 422 if (sc->sc_i2c_xfer.error) 423 return (1); 424 425 return (0); 426 427 timeout: 428 /* 429 * Transfer timeout. Kill the transaction and clear status bits. 430 */ 431 aprint_error_dev(sc->sc_dev, "timeout, status 0x%x\n", st); 432 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_HC, 433 PIIX_SMB_HC_KILL); 434 DELAY(PIIXPM_DELAY); 435 st = bus_space_read_1(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_HS); 436 if ((st & PIIX_SMB_HS_FAILED) == 0) 437 aprint_error_dev(sc->sc_dev, "transaction abort failed, status 0x%x\n", st); 438 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_HS, st); 439 /* 440 * CSB5 needs hard reset to unlock the smbus after timeout. 441 */ 442 if (PIIXPM_IS_CSB5(sc->sc_id)) 443 piixpm_csb5_reset(sc); 444 return (1); 445 } 446 447 static int 448 piixpm_intr(void *arg) 449 { 450 struct piixpm_softc *sc = arg; 451 u_int8_t st; 452 u_int8_t *b; 453 size_t len; 454 455 /* Read status */ 456 st = bus_space_read_1(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_HS); 457 if ((st & PIIX_SMB_HS_BUSY) != 0 || (st & (PIIX_SMB_HS_INTR | 458 PIIX_SMB_HS_DEVERR | PIIX_SMB_HS_BUSERR | 459 PIIX_SMB_HS_FAILED)) == 0) 460 /* Interrupt was not for us */ 461 return (0); 462 463 DPRINTF(("%s: intr st 0x%d\n", device_xname(sc->sc_dev), st & 0xff)); 464 465 /* Clear status bits */ 466 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_HS, st); 467 468 /* Check for errors */ 469 if (st & (PIIX_SMB_HS_DEVERR | PIIX_SMB_HS_BUSERR | 470 PIIX_SMB_HS_FAILED)) { 471 sc->sc_i2c_xfer.error = 1; 472 goto done; 473 } 474 475 if (st & PIIX_SMB_HS_INTR) { 476 if (I2C_OP_WRITE_P(sc->sc_i2c_xfer.op)) 477 goto done; 478 479 /* Read data */ 480 b = sc->sc_i2c_xfer.buf; 481 len = sc->sc_i2c_xfer.len; 482 if (len > 0) 483 b[0] = bus_space_read_1(sc->sc_smb_iot, sc->sc_smb_ioh, 484 PIIX_SMB_HD0); 485 if (len > 1) 486 b[1] = bus_space_read_1(sc->sc_smb_iot, sc->sc_smb_ioh, 487 PIIX_SMB_HD1); 488 } 489 490 done: 491 if ((sc->sc_i2c_xfer.flags & I2C_F_POLL) == 0) 492 wakeup(sc); 493 return (1); 494 } 495
Indexes created Mon Sep 29 18:09:42 GMT 2025