piixpm.c revision 1.36
1 /* $NetBSD: piixpm.c,v 1.36 2011/10/02 23:25:20 jmcneill Exp $ */ 2 /* $OpenBSD: piixpm.c,v 1.20 2006/02/27 08:25:02 grange Exp $ */ 3 4 /* 5 * Copyright (c) 2005, 2006 Alexander Yurchenko <grange (at) openbsd.org> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 /* 21 * Intel PIIX and compatible Power Management controller driver. 22 */ 23 24 #include <sys/cdefs.h> 25 __KERNEL_RCSID(0, "$NetBSD: piixpm.c,v 1.36 2011/10/02 23:25:20 jmcneill Exp $"); 26 27 #include <sys/param.h> 28 #include <sys/systm.h> 29 #include <sys/device.h> 30 #include <sys/kernel.h> 31 #include <sys/rwlock.h> 32 #include <sys/proc.h> 33 34 #include <sys/bus.h> 35 36 #include <dev/pci/pcidevs.h> 37 #include <dev/pci/pcireg.h> 38 #include <dev/pci/pcivar.h> 39 40 #include <dev/pci/piixpmreg.h> 41 42 #include <dev/i2c/i2cvar.h> 43 44 #include <dev/ic/acpipmtimer.h> 45 46 #ifdef PIIXPM_DEBUG 47 #define DPRINTF(x) printf x 48 #else 49 #define DPRINTF(x) 50 #endif 51 52 #define PIIXPM_IS_CSB5(id) \ 53 (PCI_VENDOR((id)) == PCI_VENDOR_SERVERWORKS && \ 54 PCI_PRODUCT((id)) == PCI_PRODUCT_SERVERWORKS_CSB5) 55 #define PIIXPM_DELAY 200 56 #define PIIXPM_TIMEOUT 1 57 58 #define PIIXPM_INDIRECTIO_BASE 0xcd6 59 #define PIIXPM_INDIRECTIO_SIZE 2 60 #define PIIXPM_INDIRECTIO_INDEX 0 61 #define PIIXPM_INDIRECTIO_DATA 1 62 63 #define SB800_PM_SMBUS0EN_LO 0x2c 64 #define SB800_PM_SMBUS0EN_HI 0x2d 65 66 #define SB800_PM_SMBUS0EN_ENABLE 0x0001 67 #define SB800_PM_SMBUS0EN_BADDR 0xffe0 68 69 struct piixpm_softc { 70 device_t sc_dev; 71 72 bus_space_tag_t sc_smb_iot; 73 bus_space_handle_t sc_smb_ioh; 74 void * sc_smb_ih; 75 int sc_poll; 76 77 bus_space_tag_t sc_pm_iot; 78 bus_space_handle_t sc_pm_ioh; 79 80 pci_chipset_tag_t sc_pc; 81 pcitag_t sc_pcitag; 82 pcireg_t sc_id; 83 84 struct i2c_controller sc_i2c_tag; 85 krwlock_t sc_i2c_rwlock; 86 struct { 87 i2c_op_t op; 88 void * buf; 89 size_t len; 90 int flags; 91 volatile int error; 92 } sc_i2c_xfer; 93 94 pcireg_t sc_devact[2]; 95 }; 96 97 static int piixpm_match(device_t, cfdata_t, void *); 98 static void piixpm_attach(device_t, device_t, void *); 99 100 static bool piixpm_suspend(device_t, const pmf_qual_t *); 101 static bool piixpm_resume(device_t, const pmf_qual_t *); 102 103 static int piixpm_sb800_init(struct piixpm_softc *, 104 struct pci_attach_args *); 105 static void piixpm_csb5_reset(void *); 106 static int piixpm_i2c_acquire_bus(void *, int); 107 static void piixpm_i2c_release_bus(void *, int); 108 static int piixpm_i2c_exec(void *, i2c_op_t, i2c_addr_t, const void *, 109 size_t, void *, size_t, int); 110 111 static int piixpm_intr(void *); 112 113 CFATTACH_DECL_NEW(piixpm, sizeof(struct piixpm_softc), 114 piixpm_match, piixpm_attach, NULL, NULL); 115 116 static int 117 piixpm_match(device_t parent, cfdata_t match, void *aux) 118 { 119 struct pci_attach_args *pa; 120 121 pa = (struct pci_attach_args *)aux; 122 switch (PCI_VENDOR(pa->pa_id)) { 123 case PCI_VENDOR_INTEL: 124 switch (PCI_PRODUCT(pa->pa_id)) { 125 case PCI_PRODUCT_INTEL_82371AB_PMC: 126 case PCI_PRODUCT_INTEL_82440MX_PMC: 127 return 1; 128 } 129 break; 130 case PCI_VENDOR_ATI: 131 switch (PCI_PRODUCT(pa->pa_id)) { 132 case PCI_PRODUCT_ATI_SB200_SMB: 133 case PCI_PRODUCT_ATI_SB300_SMB: 134 case PCI_PRODUCT_ATI_SB400_SMB: 135 case PCI_PRODUCT_ATI_SB600_SMB: /* matches SB600/SB700/SB800 */ 136 return 1; 137 } 138 break; 139 case PCI_VENDOR_SERVERWORKS: 140 switch (PCI_PRODUCT(pa->pa_id)) { 141 case PCI_PRODUCT_SERVERWORKS_OSB4: 142 case PCI_PRODUCT_SERVERWORKS_CSB5: 143 case PCI_PRODUCT_SERVERWORKS_CSB6: 144 case PCI_PRODUCT_SERVERWORKS_HT1000SB: 145 return 1; 146 } 147 } 148 149 return 0; 150 } 151 152 static void 153 piixpm_attach(device_t parent, device_t self, void *aux) 154 { 155 struct piixpm_softc *sc = device_private(self); 156 struct pci_attach_args *pa = aux; 157 struct i2cbus_attach_args iba; 158 pcireg_t base, conf; 159 pcireg_t pmmisc; 160 pci_intr_handle_t ih; 161 char devinfo[256]; 162 const char *intrstr = NULL; 163 164 sc->sc_dev = self; 165 sc->sc_id = pa->pa_id; 166 sc->sc_pc = pa->pa_pc; 167 sc->sc_pcitag = pa->pa_tag; 168 169 aprint_naive("\n"); 170 aprint_normal("\n"); 171 172 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo, sizeof(devinfo)); 173 aprint_normal_dev(self, "%s (rev. 0x%02x)\n", devinfo, 174 PCI_REVISION(pa->pa_class)); 175 176 if (!pmf_device_register(self, piixpm_suspend, piixpm_resume)) 177 aprint_error_dev(self, "couldn't establish power handler\n"); 178 179 /* Read configuration */ 180 conf = pci_conf_read(pa->pa_pc, pa->pa_tag, PIIX_SMB_HOSTC); 181 DPRINTF(("%s: conf 0x%x\n", device_xname(self), conf)); 182 183 if ((PCI_VENDOR(pa->pa_id) != PCI_VENDOR_INTEL) || 184 (PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_INTEL_82371AB_PMC)) 185 goto nopowermanagement; 186 187 /* check whether I/O access to PM regs is enabled */ 188 pmmisc = pci_conf_read(pa->pa_pc, pa->pa_tag, PIIX_PMREGMISC); 189 if (!(pmmisc & 1)) 190 goto nopowermanagement; 191 192 sc->sc_pm_iot = pa->pa_iot; 193 /* Map I/O space */ 194 base = pci_conf_read(pa->pa_pc, pa->pa_tag, PIIX_PM_BASE); 195 if (bus_space_map(sc->sc_pm_iot, PCI_MAPREG_IO_ADDR(base), 196 PIIX_PM_SIZE, 0, &sc->sc_pm_ioh)) { 197 aprint_error_dev(self, "can't map power management I/O space\n"); 198 goto nopowermanagement; 199 } 200 201 /* 202 * Revision 0 and 1 are PIIX4, 2 is PIIX4E, 3 is PIIX4M. 203 * PIIX4 and PIIX4E have a bug in the timer latch, see Errata #20 204 * in the "Specification update" (document #297738). 205 */ 206 acpipmtimer_attach(self, sc->sc_pm_iot, sc->sc_pm_ioh, 207 PIIX_PM_PMTMR, 208 (PCI_REVISION(pa->pa_class) < 3) ? ACPIPMT_BADLATCH : 0 ); 209 210 nopowermanagement: 211 212 /* SB800 rev 0x40+ needs special initialization */ 213 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_ATI && 214 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_ATI_SB600_SMB && 215 PCI_REVISION(pa->pa_class) >= 0x40) { 216 if (piixpm_sb800_init(sc, pa) == 0) 217 goto attach_i2c; 218 aprint_normal_dev(self, "SMBus disabled\n"); 219 return; 220 } 221 222 if ((conf & PIIX_SMB_HOSTC_HSTEN) == 0) { 223 aprint_normal_dev(self, "SMBus disabled\n"); 224 return; 225 } 226 227 /* Map I/O space */ 228 sc->sc_smb_iot = pa->pa_iot; 229 base = pci_conf_read(pa->pa_pc, pa->pa_tag, PIIX_SMB_BASE) & 0xffff; 230 if (bus_space_map(sc->sc_smb_iot, PCI_MAPREG_IO_ADDR(base), 231 PIIX_SMB_SIZE, 0, &sc->sc_smb_ioh)) { 232 aprint_error_dev(self, "can't map smbus I/O space\n"); 233 return; 234 } 235 236 sc->sc_poll = 1; 237 aprint_normal_dev(self, ""); 238 if ((conf & PIIX_SMB_HOSTC_INTMASK) == PIIX_SMB_HOSTC_SMI) { 239 /* No PCI IRQ */ 240 aprint_normal("interrupting at SMI, "); 241 } else if ((conf & PIIX_SMB_HOSTC_INTMASK) == PIIX_SMB_HOSTC_IRQ) { 242 /* Install interrupt handler */ 243 if (pci_intr_map(pa, &ih) == 0) { 244 intrstr = pci_intr_string(pa->pa_pc, ih); 245 sc->sc_smb_ih = pci_intr_establish(pa->pa_pc, ih, IPL_BIO, 246 piixpm_intr, sc); 247 if (sc->sc_smb_ih != NULL) { 248 aprint_normal("interrupting at %s", intrstr); 249 sc->sc_poll = 0; 250 } 251 } 252 } 253 if (sc->sc_poll) 254 aprint_normal("polling"); 255 256 attach_i2c: 257 aprint_normal("\n"); 258 259 /* Attach I2C bus */ 260 rw_init(&sc->sc_i2c_rwlock); 261 sc->sc_i2c_tag.ic_cookie = sc; 262 sc->sc_i2c_tag.ic_acquire_bus = piixpm_i2c_acquire_bus; 263 sc->sc_i2c_tag.ic_release_bus = piixpm_i2c_release_bus; 264 sc->sc_i2c_tag.ic_exec = piixpm_i2c_exec; 265 266 memset(&iba, 0, sizeof(iba)); 267 iba.iba_type = I2C_TYPE_SMBUS; 268 iba.iba_tag = &sc->sc_i2c_tag; 269 config_found_ia(self, "i2cbus", &iba, iicbus_print); 270 271 return; 272 } 273 274 static bool 275 piixpm_suspend(device_t dv, const pmf_qual_t *qual) 276 { 277 struct piixpm_softc *sc = device_private(dv); 278 279 sc->sc_devact[0] = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 280 PIIX_DEVACTA); 281 sc->sc_devact[1] = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 282 PIIX_DEVACTB); 283 284 return true; 285 } 286 287 static bool 288 piixpm_resume(device_t dv, const pmf_qual_t *qual) 289 { 290 struct piixpm_softc *sc = device_private(dv); 291 292 pci_conf_write(sc->sc_pc, sc->sc_pcitag, PIIX_DEVACTA, 293 sc->sc_devact[0]); 294 pci_conf_write(sc->sc_pc, sc->sc_pcitag, PIIX_DEVACTB, 295 sc->sc_devact[1]); 296 297 return true; 298 } 299 300 /* 301 * Extract SMBus base address from SB800 Power Management (PM) registers. 302 * The PM registers can be accessed either through indirect I/O (CD6/CD7) or 303 * direct mapping if AcpiMMioDecodeEn is enabled. Since this function is only 304 * called once it uses indirect I/O for simplicity. 305 */ 306 static int 307 piixpm_sb800_init(struct piixpm_softc *sc, struct pci_attach_args *pa) 308 { 309 bus_space_tag_t iot = pa->pa_iot; 310 bus_space_handle_t ioh; /* indirect I/O handle */ 311 uint16_t val, base_addr; 312 313 /* Fetch SMB base address */ 314 if (bus_space_map(iot, 315 PIIXPM_INDIRECTIO_BASE, PIIXPM_INDIRECTIO_SIZE, 0, &ioh)) { 316 device_printf(sc->sc_dev, "couldn't map indirect I/O space\n"); 317 return EBUSY; 318 } 319 bus_space_write_1(iot, ioh, PIIXPM_INDIRECTIO_INDEX, 320 SB800_PM_SMBUS0EN_LO); 321 val = bus_space_read_1(iot, ioh, PIIXPM_INDIRECTIO_DATA); 322 bus_space_write_1(iot, ioh, PIIXPM_INDIRECTIO_INDEX, 323 SB800_PM_SMBUS0EN_HI); 324 val |= bus_space_read_1(iot, ioh, PIIXPM_INDIRECTIO_DATA) << 8; 325 bus_space_unmap(iot, ioh, 2); 326 327 if ((val & SB800_PM_SMBUS0EN_ENABLE) == 0) 328 return ENOENT; 329 330 base_addr = val & SB800_PM_SMBUS0EN_BADDR; 331 332 aprint_debug_dev(sc->sc_dev, "SMBus @ 0x%04x\n", base_addr); 333 334 sc->sc_smb_iot = iot; 335 if (bus_space_map(sc->sc_smb_iot, PCI_MAPREG_IO_ADDR(base_addr), 336 PIIX_SMB_SIZE, 0, &sc->sc_smb_ioh)) { 337 aprint_error_dev(sc->sc_dev, "can't map smbus I/O space\n"); 338 return EBUSY; 339 } 340 sc->sc_poll = 1; 341 342 return 0; 343 } 344 345 static void 346 piixpm_csb5_reset(void *arg) 347 { 348 struct piixpm_softc *sc = arg; 349 pcireg_t base, hostc, pmbase; 350 351 base = pci_conf_read(sc->sc_pc, sc->sc_pcitag, PIIX_SMB_BASE); 352 hostc = pci_conf_read(sc->sc_pc, sc->sc_pcitag, PIIX_SMB_HOSTC); 353 354 pmbase = pci_conf_read(sc->sc_pc, sc->sc_pcitag, PIIX_PM_BASE); 355 pmbase |= PIIX_PM_BASE_CSB5_RESET; 356 pci_conf_write(sc->sc_pc, sc->sc_pcitag, PIIX_PM_BASE, pmbase); 357 pmbase &= ~PIIX_PM_BASE_CSB5_RESET; 358 pci_conf_write(sc->sc_pc, sc->sc_pcitag, PIIX_PM_BASE, pmbase); 359 360 pci_conf_write(sc->sc_pc, sc->sc_pcitag, PIIX_SMB_BASE, base); 361 pci_conf_write(sc->sc_pc, sc->sc_pcitag, PIIX_SMB_HOSTC, hostc); 362 363 (void) tsleep(&sc, PRIBIO, "csb5reset", hz/2); 364 } 365 366 static int 367 piixpm_i2c_acquire_bus(void *cookie, int flags) 368 { 369 struct piixpm_softc *sc = cookie; 370 371 if (cold || sc->sc_poll || (flags & I2C_F_POLL)) 372 return (0); 373 374 rw_enter(&sc->sc_i2c_rwlock, RW_WRITER); 375 return 0; 376 } 377 378 static void 379 piixpm_i2c_release_bus(void *cookie, int flags) 380 { 381 struct piixpm_softc *sc = cookie; 382 383 if (cold || sc->sc_poll || (flags & I2C_F_POLL)) 384 return; 385 386 rw_exit(&sc->sc_i2c_rwlock); 387 } 388 389 static int 390 piixpm_i2c_exec(void *cookie, i2c_op_t op, i2c_addr_t addr, 391 const void *cmdbuf, size_t cmdlen, void *buf, size_t len, int flags) 392 { 393 struct piixpm_softc *sc = cookie; 394 const u_int8_t *b; 395 u_int8_t ctl = 0, st; 396 int retries; 397 398 DPRINTF(("%s: exec: op %d, addr 0x%x, cmdlen %zu, len %zu, flags 0x%x\n", 399 device_xname(sc->sc_dev), op, addr, cmdlen, len, flags)); 400 401 /* Wait for bus to be idle */ 402 for (retries = 100; retries > 0; retries--) { 403 st = bus_space_read_1(sc->sc_smb_iot, sc->sc_smb_ioh, 404 PIIX_SMB_HS); 405 if (!(st & PIIX_SMB_HS_BUSY)) 406 break; 407 DELAY(PIIXPM_DELAY); 408 } 409 DPRINTF(("%s: exec: st 0x%d\n", device_xname(sc->sc_dev), st & 0xff)); 410 if (st & PIIX_SMB_HS_BUSY) 411 return (1); 412 413 if (cold || sc->sc_poll) 414 flags |= I2C_F_POLL; 415 416 if (!I2C_OP_STOP_P(op) || cmdlen > 1 || len > 2 || 417 (cmdlen == 0 && len > 1)) 418 return (1); 419 420 /* Setup transfer */ 421 sc->sc_i2c_xfer.op = op; 422 sc->sc_i2c_xfer.buf = buf; 423 sc->sc_i2c_xfer.len = len; 424 sc->sc_i2c_xfer.flags = flags; 425 sc->sc_i2c_xfer.error = 0; 426 427 /* Set slave address and transfer direction */ 428 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_TXSLVA, 429 PIIX_SMB_TXSLVA_ADDR(addr) | 430 (I2C_OP_READ_P(op) ? PIIX_SMB_TXSLVA_READ : 0)); 431 432 b = cmdbuf; 433 if (cmdlen > 0) 434 /* Set command byte */ 435 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, 436 PIIX_SMB_HCMD, b[0]); 437 438 if (I2C_OP_WRITE_P(op)) { 439 /* Write data */ 440 b = buf; 441 if (cmdlen == 0 && len == 1) 442 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, 443 PIIX_SMB_HCMD, b[0]); 444 else if (len > 0) 445 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, 446 PIIX_SMB_HD0, b[0]); 447 if (len > 1) 448 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, 449 PIIX_SMB_HD1, b[1]); 450 } 451 452 /* Set SMBus command */ 453 if (cmdlen == 0) { 454 if (len == 0) 455 ctl = PIIX_SMB_HC_CMD_QUICK; 456 else 457 ctl = PIIX_SMB_HC_CMD_BYTE; 458 } else if (len == 1) 459 ctl = PIIX_SMB_HC_CMD_BDATA; 460 else if (len == 2) 461 ctl = PIIX_SMB_HC_CMD_WDATA; 462 463 if ((flags & I2C_F_POLL) == 0) 464 ctl |= PIIX_SMB_HC_INTREN; 465 466 /* Start transaction */ 467 ctl |= PIIX_SMB_HC_START; 468 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_HC, ctl); 469 470 if (flags & I2C_F_POLL) { 471 /* Poll for completion */ 472 if (PIIXPM_IS_CSB5(sc->sc_id)) 473 DELAY(2*PIIXPM_DELAY); 474 else 475 DELAY(PIIXPM_DELAY); 476 for (retries = 1000; retries > 0; retries--) { 477 st = bus_space_read_1(sc->sc_smb_iot, sc->sc_smb_ioh, 478 PIIX_SMB_HS); 479 if ((st & PIIX_SMB_HS_BUSY) == 0) 480 break; 481 DELAY(PIIXPM_DELAY); 482 } 483 if (st & PIIX_SMB_HS_BUSY) 484 goto timeout; 485 piixpm_intr(sc); 486 } else { 487 /* Wait for interrupt */ 488 if (tsleep(sc, PRIBIO, "iicexec", PIIXPM_TIMEOUT * hz)) 489 goto timeout; 490 } 491 492 if (sc->sc_i2c_xfer.error) 493 return (1); 494 495 return (0); 496 497 timeout: 498 /* 499 * Transfer timeout. Kill the transaction and clear status bits. 500 */ 501 aprint_error_dev(sc->sc_dev, "timeout, status 0x%x\n", st); 502 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_HC, 503 PIIX_SMB_HC_KILL); 504 DELAY(PIIXPM_DELAY); 505 st = bus_space_read_1(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_HS); 506 if ((st & PIIX_SMB_HS_FAILED) == 0) 507 aprint_error_dev(sc->sc_dev, "transaction abort failed, status 0x%x\n", st); 508 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_HS, st); 509 /* 510 * CSB5 needs hard reset to unlock the smbus after timeout. 511 */ 512 if (PIIXPM_IS_CSB5(sc->sc_id)) 513 piixpm_csb5_reset(sc); 514 return (1); 515 } 516 517 static int 518 piixpm_intr(void *arg) 519 { 520 struct piixpm_softc *sc = arg; 521 u_int8_t st; 522 u_int8_t *b; 523 size_t len; 524 525 /* Read status */ 526 st = bus_space_read_1(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_HS); 527 if ((st & PIIX_SMB_HS_BUSY) != 0 || (st & (PIIX_SMB_HS_INTR | 528 PIIX_SMB_HS_DEVERR | PIIX_SMB_HS_BUSERR | 529 PIIX_SMB_HS_FAILED)) == 0) 530 /* Interrupt was not for us */ 531 return (0); 532 533 DPRINTF(("%s: intr st 0x%d\n", device_xname(sc->sc_dev), st & 0xff)); 534 535 /* Clear status bits */ 536 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_HS, st); 537 538 /* Check for errors */ 539 if (st & (PIIX_SMB_HS_DEVERR | PIIX_SMB_HS_BUSERR | 540 PIIX_SMB_HS_FAILED)) { 541 sc->sc_i2c_xfer.error = 1; 542 goto done; 543 } 544 545 if (st & PIIX_SMB_HS_INTR) { 546 if (I2C_OP_WRITE_P(sc->sc_i2c_xfer.op)) 547 goto done; 548 549 /* Read data */ 550 b = sc->sc_i2c_xfer.buf; 551 len = sc->sc_i2c_xfer.len; 552 if (len > 0) 553 b[0] = bus_space_read_1(sc->sc_smb_iot, sc->sc_smb_ioh, 554 PIIX_SMB_HD0); 555 if (len > 1) 556 b[1] = bus_space_read_1(sc->sc_smb_iot, sc->sc_smb_ioh, 557 PIIX_SMB_HD1); 558 } 559 560 done: 561 if ((sc->sc_i2c_xfer.flags & I2C_F_POLL) == 0) 562 wakeup(sc); 563 return (1); 564 } 565
Indexes created Mon Sep 29 21:09:56 GMT 2025