piixpm.c revision 1.37.2.1
1 /* $NetBSD: piixpm.c,v 1.37.2.1 2012/04/17 00:07:57 yamt Exp $ */ 2 /* $OpenBSD: piixpm.c,v 1.20 2006/02/27 08:25:02 grange Exp $ */ 3 4 /* 5 * Copyright (c) 2005, 2006 Alexander Yurchenko <grange (at) openbsd.org> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 /* 21 * Intel PIIX and compatible Power Management controller driver. 22 */ 23 24 #include <sys/cdefs.h> 25 __KERNEL_RCSID(0, "$NetBSD: piixpm.c,v 1.37.2.1 2012/04/17 00:07:57 yamt Exp $"); 26 27 #include <sys/param.h> 28 #include <sys/systm.h> 29 #include <sys/device.h> 30 #include <sys/kernel.h> 31 #include <sys/mutex.h> 32 #include <sys/proc.h> 33 34 #include <sys/bus.h> 35 36 #include <dev/pci/pcidevs.h> 37 #include <dev/pci/pcireg.h> 38 #include <dev/pci/pcivar.h> 39 40 #include <dev/pci/piixpmreg.h> 41 42 #include <dev/i2c/i2cvar.h> 43 44 #include <dev/ic/acpipmtimer.h> 45 46 #ifdef PIIXPM_DEBUG 47 #define DPRINTF(x) printf x 48 #else 49 #define DPRINTF(x) 50 #endif 51 52 #define PIIXPM_IS_CSB5(id) \ 53 (PCI_VENDOR((id)) == PCI_VENDOR_SERVERWORKS && \ 54 PCI_PRODUCT((id)) == PCI_PRODUCT_SERVERWORKS_CSB5) 55 #define PIIXPM_DELAY 200 56 #define PIIXPM_TIMEOUT 1 57 58 #define PIIXPM_INDIRECTIO_BASE 0xcd6 59 #define PIIXPM_INDIRECTIO_SIZE 2 60 #define PIIXPM_INDIRECTIO_INDEX 0 61 #define PIIXPM_INDIRECTIO_DATA 1 62 63 #define SB800_PM_SMBUS0EN_LO 0x2c 64 #define SB800_PM_SMBUS0EN_HI 0x2d 65 66 #define SB800_PM_SMBUS0EN_ENABLE 0x0001 67 #define SB800_PM_SMBUS0EN_BADDR 0xffe0 68 69 struct piixpm_softc { 70 device_t sc_dev; 71 72 bus_space_tag_t sc_smb_iot; 73 bus_space_handle_t sc_smb_ioh; 74 void * sc_smb_ih; 75 int sc_poll; 76 77 bus_space_tag_t sc_pm_iot; 78 bus_space_handle_t sc_pm_ioh; 79 80 pci_chipset_tag_t sc_pc; 81 pcitag_t sc_pcitag; 82 pcireg_t sc_id; 83 84 struct i2c_controller sc_i2c_tag; 85 kmutex_t sc_i2c_mutex; 86 struct { 87 i2c_op_t op; 88 void * buf; 89 size_t len; 90 int flags; 91 volatile int error; 92 } sc_i2c_xfer; 93 94 pcireg_t sc_devact[2]; 95 }; 96 97 static int piixpm_match(device_t, cfdata_t, void *); 98 static void piixpm_attach(device_t, device_t, void *); 99 100 static bool piixpm_suspend(device_t, const pmf_qual_t *); 101 static bool piixpm_resume(device_t, const pmf_qual_t *); 102 103 static int piixpm_sb800_init(struct piixpm_softc *, 104 struct pci_attach_args *); 105 static void piixpm_csb5_reset(void *); 106 static int piixpm_i2c_acquire_bus(void *, int); 107 static void piixpm_i2c_release_bus(void *, int); 108 static int piixpm_i2c_exec(void *, i2c_op_t, i2c_addr_t, const void *, 109 size_t, void *, size_t, int); 110 111 static int piixpm_intr(void *); 112 113 CFATTACH_DECL_NEW(piixpm, sizeof(struct piixpm_softc), 114 piixpm_match, piixpm_attach, NULL, NULL); 115 116 static int 117 piixpm_match(device_t parent, cfdata_t match, void *aux) 118 { 119 struct pci_attach_args *pa; 120 121 pa = (struct pci_attach_args *)aux; 122 switch (PCI_VENDOR(pa->pa_id)) { 123 case PCI_VENDOR_INTEL: 124 switch (PCI_PRODUCT(pa->pa_id)) { 125 case PCI_PRODUCT_INTEL_82371AB_PMC: 126 case PCI_PRODUCT_INTEL_82440MX_PMC: 127 return 1; 128 } 129 break; 130 case PCI_VENDOR_ATI: 131 switch (PCI_PRODUCT(pa->pa_id)) { 132 case PCI_PRODUCT_ATI_SB200_SMB: 133 case PCI_PRODUCT_ATI_SB300_SMB: 134 case PCI_PRODUCT_ATI_SB400_SMB: 135 case PCI_PRODUCT_ATI_SB600_SMB: /* matches SB600/SB700/SB800 */ 136 return 1; 137 } 138 break; 139 case PCI_VENDOR_SERVERWORKS: 140 switch (PCI_PRODUCT(pa->pa_id)) { 141 case PCI_PRODUCT_SERVERWORKS_OSB4: 142 case PCI_PRODUCT_SERVERWORKS_CSB5: 143 case PCI_PRODUCT_SERVERWORKS_CSB6: 144 case PCI_PRODUCT_SERVERWORKS_HT1000SB: 145 return 1; 146 } 147 } 148 149 return 0; 150 } 151 152 static void 153 piixpm_attach(device_t parent, device_t self, void *aux) 154 { 155 struct piixpm_softc *sc = device_private(self); 156 struct pci_attach_args *pa = aux; 157 struct i2cbus_attach_args iba; 158 pcireg_t base, conf; 159 pcireg_t pmmisc; 160 pci_intr_handle_t ih; 161 const char *intrstr = NULL; 162 163 sc->sc_dev = self; 164 sc->sc_id = pa->pa_id; 165 sc->sc_pc = pa->pa_pc; 166 sc->sc_pcitag = pa->pa_tag; 167 168 pci_aprint_devinfo(pa, NULL); 169 170 if (!pmf_device_register(self, piixpm_suspend, piixpm_resume)) 171 aprint_error_dev(self, "couldn't establish power handler\n"); 172 173 /* Read configuration */ 174 conf = pci_conf_read(pa->pa_pc, pa->pa_tag, PIIX_SMB_HOSTC); 175 DPRINTF(("%s: conf 0x%x\n", device_xname(self), conf)); 176 177 if ((PCI_VENDOR(pa->pa_id) != PCI_VENDOR_INTEL) || 178 (PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_INTEL_82371AB_PMC)) 179 goto nopowermanagement; 180 181 /* check whether I/O access to PM regs is enabled */ 182 pmmisc = pci_conf_read(pa->pa_pc, pa->pa_tag, PIIX_PMREGMISC); 183 if (!(pmmisc & 1)) 184 goto nopowermanagement; 185 186 sc->sc_pm_iot = pa->pa_iot; 187 /* Map I/O space */ 188 base = pci_conf_read(pa->pa_pc, pa->pa_tag, PIIX_PM_BASE); 189 if (bus_space_map(sc->sc_pm_iot, PCI_MAPREG_IO_ADDR(base), 190 PIIX_PM_SIZE, 0, &sc->sc_pm_ioh)) { 191 aprint_error_dev(self, "can't map power management I/O space\n"); 192 goto nopowermanagement; 193 } 194 195 /* 196 * Revision 0 and 1 are PIIX4, 2 is PIIX4E, 3 is PIIX4M. 197 * PIIX4 and PIIX4E have a bug in the timer latch, see Errata #20 198 * in the "Specification update" (document #297738). 199 */ 200 acpipmtimer_attach(self, sc->sc_pm_iot, sc->sc_pm_ioh, 201 PIIX_PM_PMTMR, 202 (PCI_REVISION(pa->pa_class) < 3) ? ACPIPMT_BADLATCH : 0 ); 203 204 nopowermanagement: 205 206 /* SB800 rev 0x40+ needs special initialization */ 207 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_ATI && 208 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_ATI_SB600_SMB && 209 PCI_REVISION(pa->pa_class) >= 0x40) { 210 if (piixpm_sb800_init(sc, pa) == 0) 211 goto attach_i2c; 212 aprint_normal_dev(self, "SMBus disabled\n"); 213 return; 214 } 215 216 if ((conf & PIIX_SMB_HOSTC_HSTEN) == 0) { 217 aprint_normal_dev(self, "SMBus disabled\n"); 218 return; 219 } 220 221 /* Map I/O space */ 222 sc->sc_smb_iot = pa->pa_iot; 223 base = pci_conf_read(pa->pa_pc, pa->pa_tag, PIIX_SMB_BASE) & 0xffff; 224 if (bus_space_map(sc->sc_smb_iot, PCI_MAPREG_IO_ADDR(base), 225 PIIX_SMB_SIZE, 0, &sc->sc_smb_ioh)) { 226 aprint_error_dev(self, "can't map smbus I/O space\n"); 227 return; 228 } 229 230 sc->sc_poll = 1; 231 aprint_normal_dev(self, ""); 232 if ((conf & PIIX_SMB_HOSTC_INTMASK) == PIIX_SMB_HOSTC_SMI) { 233 /* No PCI IRQ */ 234 aprint_normal("interrupting at SMI, "); 235 } else if ((conf & PIIX_SMB_HOSTC_INTMASK) == PIIX_SMB_HOSTC_IRQ) { 236 /* Install interrupt handler */ 237 if (pci_intr_map(pa, &ih) == 0) { 238 intrstr = pci_intr_string(pa->pa_pc, ih); 239 sc->sc_smb_ih = pci_intr_establish(pa->pa_pc, ih, IPL_BIO, 240 piixpm_intr, sc); 241 if (sc->sc_smb_ih != NULL) { 242 aprint_normal("interrupting at %s", intrstr); 243 sc->sc_poll = 0; 244 } 245 } 246 } 247 if (sc->sc_poll) 248 aprint_normal("polling"); 249 250 aprint_normal("\n"); 251 252 attach_i2c: 253 /* Attach I2C bus */ 254 mutex_init(&sc->sc_i2c_mutex, MUTEX_DEFAULT, IPL_NONE); 255 sc->sc_i2c_tag.ic_cookie = sc; 256 sc->sc_i2c_tag.ic_acquire_bus = piixpm_i2c_acquire_bus; 257 sc->sc_i2c_tag.ic_release_bus = piixpm_i2c_release_bus; 258 sc->sc_i2c_tag.ic_exec = piixpm_i2c_exec; 259 260 memset(&iba, 0, sizeof(iba)); 261 iba.iba_type = I2C_TYPE_SMBUS; 262 iba.iba_tag = &sc->sc_i2c_tag; 263 config_found_ia(self, "i2cbus", &iba, iicbus_print); 264 265 return; 266 } 267 268 static bool 269 piixpm_suspend(device_t dv, const pmf_qual_t *qual) 270 { 271 struct piixpm_softc *sc = device_private(dv); 272 273 sc->sc_devact[0] = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 274 PIIX_DEVACTA); 275 sc->sc_devact[1] = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 276 PIIX_DEVACTB); 277 278 return true; 279 } 280 281 static bool 282 piixpm_resume(device_t dv, const pmf_qual_t *qual) 283 { 284 struct piixpm_softc *sc = device_private(dv); 285 286 pci_conf_write(sc->sc_pc, sc->sc_pcitag, PIIX_DEVACTA, 287 sc->sc_devact[0]); 288 pci_conf_write(sc->sc_pc, sc->sc_pcitag, PIIX_DEVACTB, 289 sc->sc_devact[1]); 290 291 return true; 292 } 293 294 /* 295 * Extract SMBus base address from SB800 Power Management (PM) registers. 296 * The PM registers can be accessed either through indirect I/O (CD6/CD7) or 297 * direct mapping if AcpiMMioDecodeEn is enabled. Since this function is only 298 * called once it uses indirect I/O for simplicity. 299 */ 300 static int 301 piixpm_sb800_init(struct piixpm_softc *sc, struct pci_attach_args *pa) 302 { 303 bus_space_tag_t iot = pa->pa_iot; 304 bus_space_handle_t ioh; /* indirect I/O handle */ 305 uint16_t val, base_addr; 306 307 /* Fetch SMB base address */ 308 if (bus_space_map(iot, 309 PIIXPM_INDIRECTIO_BASE, PIIXPM_INDIRECTIO_SIZE, 0, &ioh)) { 310 device_printf(sc->sc_dev, "couldn't map indirect I/O space\n"); 311 return EBUSY; 312 } 313 bus_space_write_1(iot, ioh, PIIXPM_INDIRECTIO_INDEX, 314 SB800_PM_SMBUS0EN_LO); 315 val = bus_space_read_1(iot, ioh, PIIXPM_INDIRECTIO_DATA); 316 bus_space_write_1(iot, ioh, PIIXPM_INDIRECTIO_INDEX, 317 SB800_PM_SMBUS0EN_HI); 318 val |= bus_space_read_1(iot, ioh, PIIXPM_INDIRECTIO_DATA) << 8; 319 bus_space_unmap(iot, ioh, 2); 320 321 if ((val & SB800_PM_SMBUS0EN_ENABLE) == 0) 322 return ENOENT; 323 324 base_addr = val & SB800_PM_SMBUS0EN_BADDR; 325 326 aprint_debug_dev(sc->sc_dev, "SMBus @ 0x%04x\n", base_addr); 327 328 sc->sc_smb_iot = iot; 329 if (bus_space_map(sc->sc_smb_iot, PCI_MAPREG_IO_ADDR(base_addr), 330 PIIX_SMB_SIZE, 0, &sc->sc_smb_ioh)) { 331 aprint_error_dev(sc->sc_dev, "can't map smbus I/O space\n"); 332 return EBUSY; 333 } 334 aprint_normal_dev(sc->sc_dev, "polling (SB800)\n"); 335 sc->sc_poll = 1; 336 337 return 0; 338 } 339 340 static void 341 piixpm_csb5_reset(void *arg) 342 { 343 struct piixpm_softc *sc = arg; 344 pcireg_t base, hostc, pmbase; 345 346 base = pci_conf_read(sc->sc_pc, sc->sc_pcitag, PIIX_SMB_BASE); 347 hostc = pci_conf_read(sc->sc_pc, sc->sc_pcitag, PIIX_SMB_HOSTC); 348 349 pmbase = pci_conf_read(sc->sc_pc, sc->sc_pcitag, PIIX_PM_BASE); 350 pmbase |= PIIX_PM_BASE_CSB5_RESET; 351 pci_conf_write(sc->sc_pc, sc->sc_pcitag, PIIX_PM_BASE, pmbase); 352 pmbase &= ~PIIX_PM_BASE_CSB5_RESET; 353 pci_conf_write(sc->sc_pc, sc->sc_pcitag, PIIX_PM_BASE, pmbase); 354 355 pci_conf_write(sc->sc_pc, sc->sc_pcitag, PIIX_SMB_BASE, base); 356 pci_conf_write(sc->sc_pc, sc->sc_pcitag, PIIX_SMB_HOSTC, hostc); 357 358 (void) tsleep(&sc, PRIBIO, "csb5reset", hz/2); 359 } 360 361 static int 362 piixpm_i2c_acquire_bus(void *cookie, int flags) 363 { 364 struct piixpm_softc *sc = cookie; 365 366 if (!cold) 367 mutex_enter(&sc->sc_i2c_mutex); 368 369 return 0; 370 } 371 372 static void 373 piixpm_i2c_release_bus(void *cookie, int flags) 374 { 375 struct piixpm_softc *sc = cookie; 376 377 if (!cold) 378 mutex_exit(&sc->sc_i2c_mutex); 379 } 380 381 static int 382 piixpm_i2c_exec(void *cookie, i2c_op_t op, i2c_addr_t addr, 383 const void *cmdbuf, size_t cmdlen, void *buf, size_t len, int flags) 384 { 385 struct piixpm_softc *sc = cookie; 386 const u_int8_t *b; 387 u_int8_t ctl = 0, st; 388 int retries; 389 390 DPRINTF(("%s: exec: op %d, addr 0x%x, cmdlen %zu, len %zu, flags 0x%x\n", 391 device_xname(sc->sc_dev), op, addr, cmdlen, len, flags)); 392 393 /* Wait for bus to be idle */ 394 for (retries = 100; retries > 0; retries--) { 395 st = bus_space_read_1(sc->sc_smb_iot, sc->sc_smb_ioh, 396 PIIX_SMB_HS); 397 if (!(st & PIIX_SMB_HS_BUSY)) 398 break; 399 DELAY(PIIXPM_DELAY); 400 } 401 DPRINTF(("%s: exec: st 0x%d\n", device_xname(sc->sc_dev), st & 0xff)); 402 if (st & PIIX_SMB_HS_BUSY) 403 return (1); 404 405 if (cold || sc->sc_poll) 406 flags |= I2C_F_POLL; 407 408 if (!I2C_OP_STOP_P(op) || cmdlen > 1 || len > 2 || 409 (cmdlen == 0 && len > 1)) 410 return (1); 411 412 /* Setup transfer */ 413 sc->sc_i2c_xfer.op = op; 414 sc->sc_i2c_xfer.buf = buf; 415 sc->sc_i2c_xfer.len = len; 416 sc->sc_i2c_xfer.flags = flags; 417 sc->sc_i2c_xfer.error = 0; 418 419 /* Set slave address and transfer direction */ 420 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_TXSLVA, 421 PIIX_SMB_TXSLVA_ADDR(addr) | 422 (I2C_OP_READ_P(op) ? PIIX_SMB_TXSLVA_READ : 0)); 423 424 b = cmdbuf; 425 if (cmdlen > 0) 426 /* Set command byte */ 427 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, 428 PIIX_SMB_HCMD, b[0]); 429 430 if (I2C_OP_WRITE_P(op)) { 431 /* Write data */ 432 b = buf; 433 if (cmdlen == 0 && len == 1) 434 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, 435 PIIX_SMB_HCMD, b[0]); 436 else if (len > 0) 437 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, 438 PIIX_SMB_HD0, b[0]); 439 if (len > 1) 440 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, 441 PIIX_SMB_HD1, b[1]); 442 } 443 444 /* Set SMBus command */ 445 if (cmdlen == 0) { 446 if (len == 0) 447 ctl = PIIX_SMB_HC_CMD_QUICK; 448 else 449 ctl = PIIX_SMB_HC_CMD_BYTE; 450 } else if (len == 1) 451 ctl = PIIX_SMB_HC_CMD_BDATA; 452 else if (len == 2) 453 ctl = PIIX_SMB_HC_CMD_WDATA; 454 455 if ((flags & I2C_F_POLL) == 0) 456 ctl |= PIIX_SMB_HC_INTREN; 457 458 /* Start transaction */ 459 ctl |= PIIX_SMB_HC_START; 460 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_HC, ctl); 461 462 if (flags & I2C_F_POLL) { 463 /* Poll for completion */ 464 if (PIIXPM_IS_CSB5(sc->sc_id)) 465 DELAY(2*PIIXPM_DELAY); 466 else 467 DELAY(PIIXPM_DELAY); 468 for (retries = 1000; retries > 0; retries--) { 469 st = bus_space_read_1(sc->sc_smb_iot, sc->sc_smb_ioh, 470 PIIX_SMB_HS); 471 if ((st & PIIX_SMB_HS_BUSY) == 0) 472 break; 473 DELAY(PIIXPM_DELAY); 474 } 475 if (st & PIIX_SMB_HS_BUSY) 476 goto timeout; 477 piixpm_intr(sc); 478 } else { 479 /* Wait for interrupt */ 480 if (tsleep(sc, PRIBIO, "iicexec", PIIXPM_TIMEOUT * hz)) 481 goto timeout; 482 } 483 484 if (sc->sc_i2c_xfer.error) 485 return (1); 486 487 return (0); 488 489 timeout: 490 /* 491 * Transfer timeout. Kill the transaction and clear status bits. 492 */ 493 aprint_error_dev(sc->sc_dev, "timeout, status 0x%x\n", st); 494 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_HC, 495 PIIX_SMB_HC_KILL); 496 DELAY(PIIXPM_DELAY); 497 st = bus_space_read_1(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_HS); 498 if ((st & PIIX_SMB_HS_FAILED) == 0) 499 aprint_error_dev(sc->sc_dev, "transaction abort failed, status 0x%x\n", st); 500 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_HS, st); 501 /* 502 * CSB5 needs hard reset to unlock the smbus after timeout. 503 */ 504 if (PIIXPM_IS_CSB5(sc->sc_id)) 505 piixpm_csb5_reset(sc); 506 return (1); 507 } 508 509 static int 510 piixpm_intr(void *arg) 511 { 512 struct piixpm_softc *sc = arg; 513 u_int8_t st; 514 u_int8_t *b; 515 size_t len; 516 517 /* Read status */ 518 st = bus_space_read_1(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_HS); 519 if ((st & PIIX_SMB_HS_BUSY) != 0 || (st & (PIIX_SMB_HS_INTR | 520 PIIX_SMB_HS_DEVERR | PIIX_SMB_HS_BUSERR | 521 PIIX_SMB_HS_FAILED)) == 0) 522 /* Interrupt was not for us */ 523 return (0); 524 525 DPRINTF(("%s: intr st 0x%d\n", device_xname(sc->sc_dev), st & 0xff)); 526 527 /* Clear status bits */ 528 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_HS, st); 529 530 /* Check for errors */ 531 if (st & (PIIX_SMB_HS_DEVERR | PIIX_SMB_HS_BUSERR | 532 PIIX_SMB_HS_FAILED)) { 533 sc->sc_i2c_xfer.error = 1; 534 goto done; 535 } 536 537 if (st & PIIX_SMB_HS_INTR) { 538 if (I2C_OP_WRITE_P(sc->sc_i2c_xfer.op)) 539 goto done; 540 541 /* Read data */ 542 b = sc->sc_i2c_xfer.buf; 543 len = sc->sc_i2c_xfer.len; 544 if (len > 0) 545 b[0] = bus_space_read_1(sc->sc_smb_iot, sc->sc_smb_ioh, 546 PIIX_SMB_HD0); 547 if (len > 1) 548 b[1] = bus_space_read_1(sc->sc_smb_iot, sc->sc_smb_ioh, 549 PIIX_SMB_HD1); 550 } 551 552 done: 553 if ((sc->sc_i2c_xfer.flags & I2C_F_POLL) == 0) 554 wakeup(sc); 555 return (1); 556 } 557
Indexes created Wed Oct 01 19:09:53 GMT 2025