piixpm.c revision 1.38
1 /* $NetBSD: piixpm.c,v 1.38 2012/01/07 15:59:46 pgoyette Exp $ */ 2 /* $OpenBSD: piixpm.c,v 1.20 2006/02/27 08:25:02 grange Exp $ */ 3 4 /* 5 * Copyright (c) 2005, 2006 Alexander Yurchenko <grange (at) openbsd.org> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 /* 21 * Intel PIIX and compatible Power Management controller driver. 22 */ 23 24 #include <sys/cdefs.h> 25 __KERNEL_RCSID(0, "$NetBSD: piixpm.c,v 1.38 2012/01/07 15:59:46 pgoyette Exp $"); 26 27 #include <sys/param.h> 28 #include <sys/systm.h> 29 #include <sys/device.h> 30 #include <sys/kernel.h> 31 #include <sys/rwlock.h> 32 #include <sys/proc.h> 33 34 #include <sys/bus.h> 35 36 #include <dev/pci/pcidevs.h> 37 #include <dev/pci/pcireg.h> 38 #include <dev/pci/pcivar.h> 39 40 #include <dev/pci/piixpmreg.h> 41 42 #include <dev/i2c/i2cvar.h> 43 44 #include <dev/ic/acpipmtimer.h> 45 46 #ifdef PIIXPM_DEBUG 47 #define DPRINTF(x) printf x 48 #else 49 #define DPRINTF(x) 50 #endif 51 52 #define PIIXPM_IS_CSB5(id) \ 53 (PCI_VENDOR((id)) == PCI_VENDOR_SERVERWORKS && \ 54 PCI_PRODUCT((id)) == PCI_PRODUCT_SERVERWORKS_CSB5) 55 #define PIIXPM_DELAY 200 56 #define PIIXPM_TIMEOUT 1 57 58 #define PIIXPM_INDIRECTIO_BASE 0xcd6 59 #define PIIXPM_INDIRECTIO_SIZE 2 60 #define PIIXPM_INDIRECTIO_INDEX 0 61 #define PIIXPM_INDIRECTIO_DATA 1 62 63 #define SB800_PM_SMBUS0EN_LO 0x2c 64 #define SB800_PM_SMBUS0EN_HI 0x2d 65 66 #define SB800_PM_SMBUS0EN_ENABLE 0x0001 67 #define SB800_PM_SMBUS0EN_BADDR 0xffe0 68 69 struct piixpm_softc { 70 device_t sc_dev; 71 72 bus_space_tag_t sc_smb_iot; 73 bus_space_handle_t sc_smb_ioh; 74 void * sc_smb_ih; 75 int sc_poll; 76 77 bus_space_tag_t sc_pm_iot; 78 bus_space_handle_t sc_pm_ioh; 79 80 pci_chipset_tag_t sc_pc; 81 pcitag_t sc_pcitag; 82 pcireg_t sc_id; 83 84 struct i2c_controller sc_i2c_tag; 85 krwlock_t sc_i2c_rwlock; 86 struct { 87 i2c_op_t op; 88 void * buf; 89 size_t len; 90 int flags; 91 volatile int error; 92 } sc_i2c_xfer; 93 94 pcireg_t sc_devact[2]; 95 }; 96 97 static int piixpm_match(device_t, cfdata_t, void *); 98 static void piixpm_attach(device_t, device_t, void *); 99 100 static bool piixpm_suspend(device_t, const pmf_qual_t *); 101 static bool piixpm_resume(device_t, const pmf_qual_t *); 102 103 static int piixpm_sb800_init(struct piixpm_softc *, 104 struct pci_attach_args *); 105 static void piixpm_csb5_reset(void *); 106 static int piixpm_i2c_acquire_bus(void *, int); 107 static void piixpm_i2c_release_bus(void *, int); 108 static int piixpm_i2c_exec(void *, i2c_op_t, i2c_addr_t, const void *, 109 size_t, void *, size_t, int); 110 111 static int piixpm_intr(void *); 112 113 CFATTACH_DECL_NEW(piixpm, sizeof(struct piixpm_softc), 114 piixpm_match, piixpm_attach, NULL, NULL); 115 116 static int 117 piixpm_match(device_t parent, cfdata_t match, void *aux) 118 { 119 struct pci_attach_args *pa; 120 121 pa = (struct pci_attach_args *)aux; 122 switch (PCI_VENDOR(pa->pa_id)) { 123 case PCI_VENDOR_INTEL: 124 switch (PCI_PRODUCT(pa->pa_id)) { 125 case PCI_PRODUCT_INTEL_82371AB_PMC: 126 case PCI_PRODUCT_INTEL_82440MX_PMC: 127 return 1; 128 } 129 break; 130 case PCI_VENDOR_ATI: 131 switch (PCI_PRODUCT(pa->pa_id)) { 132 case PCI_PRODUCT_ATI_SB200_SMB: 133 case PCI_PRODUCT_ATI_SB300_SMB: 134 case PCI_PRODUCT_ATI_SB400_SMB: 135 case PCI_PRODUCT_ATI_SB600_SMB: /* matches SB600/SB700/SB800 */ 136 return 1; 137 } 138 break; 139 case PCI_VENDOR_SERVERWORKS: 140 switch (PCI_PRODUCT(pa->pa_id)) { 141 case PCI_PRODUCT_SERVERWORKS_OSB4: 142 case PCI_PRODUCT_SERVERWORKS_CSB5: 143 case PCI_PRODUCT_SERVERWORKS_CSB6: 144 case PCI_PRODUCT_SERVERWORKS_HT1000SB: 145 return 1; 146 } 147 } 148 149 return 0; 150 } 151 152 static void 153 piixpm_attach(device_t parent, device_t self, void *aux) 154 { 155 struct piixpm_softc *sc = device_private(self); 156 struct pci_attach_args *pa = aux; 157 struct i2cbus_attach_args iba; 158 pcireg_t base, conf; 159 pcireg_t pmmisc; 160 pci_intr_handle_t ih; 161 char devinfo[256]; 162 const char *intrstr = NULL; 163 164 sc->sc_dev = self; 165 sc->sc_id = pa->pa_id; 166 sc->sc_pc = pa->pa_pc; 167 sc->sc_pcitag = pa->pa_tag; 168 169 aprint_naive("\n"); 170 171 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo, sizeof(devinfo)); 172 aprint_normal(": %s (rev. 0x%02x)\n", devinfo, 173 PCI_REVISION(pa->pa_class)); 174 175 if (!pmf_device_register(self, piixpm_suspend, piixpm_resume)) 176 aprint_error_dev(self, "couldn't establish power handler\n"); 177 178 /* Read configuration */ 179 conf = pci_conf_read(pa->pa_pc, pa->pa_tag, PIIX_SMB_HOSTC); 180 DPRINTF(("%s: conf 0x%x\n", device_xname(self), conf)); 181 182 if ((PCI_VENDOR(pa->pa_id) != PCI_VENDOR_INTEL) || 183 (PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_INTEL_82371AB_PMC)) 184 goto nopowermanagement; 185 186 /* check whether I/O access to PM regs is enabled */ 187 pmmisc = pci_conf_read(pa->pa_pc, pa->pa_tag, PIIX_PMREGMISC); 188 if (!(pmmisc & 1)) 189 goto nopowermanagement; 190 191 sc->sc_pm_iot = pa->pa_iot; 192 /* Map I/O space */ 193 base = pci_conf_read(pa->pa_pc, pa->pa_tag, PIIX_PM_BASE); 194 if (bus_space_map(sc->sc_pm_iot, PCI_MAPREG_IO_ADDR(base), 195 PIIX_PM_SIZE, 0, &sc->sc_pm_ioh)) { 196 aprint_error_dev(self, "can't map power management I/O space\n"); 197 goto nopowermanagement; 198 } 199 200 /* 201 * Revision 0 and 1 are PIIX4, 2 is PIIX4E, 3 is PIIX4M. 202 * PIIX4 and PIIX4E have a bug in the timer latch, see Errata #20 203 * in the "Specification update" (document #297738). 204 */ 205 acpipmtimer_attach(self, sc->sc_pm_iot, sc->sc_pm_ioh, 206 PIIX_PM_PMTMR, 207 (PCI_REVISION(pa->pa_class) < 3) ? ACPIPMT_BADLATCH : 0 ); 208 209 nopowermanagement: 210 211 /* SB800 rev 0x40+ needs special initialization */ 212 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_ATI && 213 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_ATI_SB600_SMB && 214 PCI_REVISION(pa->pa_class) >= 0x40) { 215 if (piixpm_sb800_init(sc, pa) == 0) 216 goto attach_i2c; 217 aprint_normal_dev(self, "SMBus disabled\n"); 218 return; 219 } 220 221 if ((conf & PIIX_SMB_HOSTC_HSTEN) == 0) { 222 aprint_normal_dev(self, "SMBus disabled\n"); 223 return; 224 } 225 226 /* Map I/O space */ 227 sc->sc_smb_iot = pa->pa_iot; 228 base = pci_conf_read(pa->pa_pc, pa->pa_tag, PIIX_SMB_BASE) & 0xffff; 229 if (bus_space_map(sc->sc_smb_iot, PCI_MAPREG_IO_ADDR(base), 230 PIIX_SMB_SIZE, 0, &sc->sc_smb_ioh)) { 231 aprint_error_dev(self, "can't map smbus I/O space\n"); 232 return; 233 } 234 235 sc->sc_poll = 1; 236 aprint_normal_dev(self, ""); 237 if ((conf & PIIX_SMB_HOSTC_INTMASK) == PIIX_SMB_HOSTC_SMI) { 238 /* No PCI IRQ */ 239 aprint_normal("interrupting at SMI, "); 240 } else if ((conf & PIIX_SMB_HOSTC_INTMASK) == PIIX_SMB_HOSTC_IRQ) { 241 /* Install interrupt handler */ 242 if (pci_intr_map(pa, &ih) == 0) { 243 intrstr = pci_intr_string(pa->pa_pc, ih); 244 sc->sc_smb_ih = pci_intr_establish(pa->pa_pc, ih, IPL_BIO, 245 piixpm_intr, sc); 246 if (sc->sc_smb_ih != NULL) { 247 aprint_normal("interrupting at %s", intrstr); 248 sc->sc_poll = 0; 249 } 250 } 251 } 252 if (sc->sc_poll) 253 aprint_normal("polling"); 254 255 aprint_normal("\n"); 256 257 attach_i2c: 258 /* Attach I2C bus */ 259 rw_init(&sc->sc_i2c_rwlock); 260 sc->sc_i2c_tag.ic_cookie = sc; 261 sc->sc_i2c_tag.ic_acquire_bus = piixpm_i2c_acquire_bus; 262 sc->sc_i2c_tag.ic_release_bus = piixpm_i2c_release_bus; 263 sc->sc_i2c_tag.ic_exec = piixpm_i2c_exec; 264 265 memset(&iba, 0, sizeof(iba)); 266 iba.iba_type = I2C_TYPE_SMBUS; 267 iba.iba_tag = &sc->sc_i2c_tag; 268 config_found_ia(self, "i2cbus", &iba, iicbus_print); 269 270 return; 271 } 272 273 static bool 274 piixpm_suspend(device_t dv, const pmf_qual_t *qual) 275 { 276 struct piixpm_softc *sc = device_private(dv); 277 278 sc->sc_devact[0] = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 279 PIIX_DEVACTA); 280 sc->sc_devact[1] = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 281 PIIX_DEVACTB); 282 283 return true; 284 } 285 286 static bool 287 piixpm_resume(device_t dv, const pmf_qual_t *qual) 288 { 289 struct piixpm_softc *sc = device_private(dv); 290 291 pci_conf_write(sc->sc_pc, sc->sc_pcitag, PIIX_DEVACTA, 292 sc->sc_devact[0]); 293 pci_conf_write(sc->sc_pc, sc->sc_pcitag, PIIX_DEVACTB, 294 sc->sc_devact[1]); 295 296 return true; 297 } 298 299 /* 300 * Extract SMBus base address from SB800 Power Management (PM) registers. 301 * The PM registers can be accessed either through indirect I/O (CD6/CD7) or 302 * direct mapping if AcpiMMioDecodeEn is enabled. Since this function is only 303 * called once it uses indirect I/O for simplicity. 304 */ 305 static int 306 piixpm_sb800_init(struct piixpm_softc *sc, struct pci_attach_args *pa) 307 { 308 bus_space_tag_t iot = pa->pa_iot; 309 bus_space_handle_t ioh; /* indirect I/O handle */ 310 uint16_t val, base_addr; 311 312 /* Fetch SMB base address */ 313 if (bus_space_map(iot, 314 PIIXPM_INDIRECTIO_BASE, PIIXPM_INDIRECTIO_SIZE, 0, &ioh)) { 315 device_printf(sc->sc_dev, "couldn't map indirect I/O space\n"); 316 return EBUSY; 317 } 318 bus_space_write_1(iot, ioh, PIIXPM_INDIRECTIO_INDEX, 319 SB800_PM_SMBUS0EN_LO); 320 val = bus_space_read_1(iot, ioh, PIIXPM_INDIRECTIO_DATA); 321 bus_space_write_1(iot, ioh, PIIXPM_INDIRECTIO_INDEX, 322 SB800_PM_SMBUS0EN_HI); 323 val |= bus_space_read_1(iot, ioh, PIIXPM_INDIRECTIO_DATA) << 8; 324 bus_space_unmap(iot, ioh, 2); 325 326 if ((val & SB800_PM_SMBUS0EN_ENABLE) == 0) 327 return ENOENT; 328 329 base_addr = val & SB800_PM_SMBUS0EN_BADDR; 330 331 aprint_debug_dev(sc->sc_dev, "SMBus @ 0x%04x\n", base_addr); 332 333 sc->sc_smb_iot = iot; 334 if (bus_space_map(sc->sc_smb_iot, PCI_MAPREG_IO_ADDR(base_addr), 335 PIIX_SMB_SIZE, 0, &sc->sc_smb_ioh)) { 336 aprint_error_dev(sc->sc_dev, "can't map smbus I/O space\n"); 337 return EBUSY; 338 } 339 sc->sc_poll = 1; 340 341 return 0; 342 } 343 344 static void 345 piixpm_csb5_reset(void *arg) 346 { 347 struct piixpm_softc *sc = arg; 348 pcireg_t base, hostc, pmbase; 349 350 base = pci_conf_read(sc->sc_pc, sc->sc_pcitag, PIIX_SMB_BASE); 351 hostc = pci_conf_read(sc->sc_pc, sc->sc_pcitag, PIIX_SMB_HOSTC); 352 353 pmbase = pci_conf_read(sc->sc_pc, sc->sc_pcitag, PIIX_PM_BASE); 354 pmbase |= PIIX_PM_BASE_CSB5_RESET; 355 pci_conf_write(sc->sc_pc, sc->sc_pcitag, PIIX_PM_BASE, pmbase); 356 pmbase &= ~PIIX_PM_BASE_CSB5_RESET; 357 pci_conf_write(sc->sc_pc, sc->sc_pcitag, PIIX_PM_BASE, pmbase); 358 359 pci_conf_write(sc->sc_pc, sc->sc_pcitag, PIIX_SMB_BASE, base); 360 pci_conf_write(sc->sc_pc, sc->sc_pcitag, PIIX_SMB_HOSTC, hostc); 361 362 (void) tsleep(&sc, PRIBIO, "csb5reset", hz/2); 363 } 364 365 static int 366 piixpm_i2c_acquire_bus(void *cookie, int flags) 367 { 368 struct piixpm_softc *sc = cookie; 369 370 if (cold || sc->sc_poll || (flags & I2C_F_POLL)) 371 return (0); 372 373 rw_enter(&sc->sc_i2c_rwlock, RW_WRITER); 374 return 0; 375 } 376 377 static void 378 piixpm_i2c_release_bus(void *cookie, int flags) 379 { 380 struct piixpm_softc *sc = cookie; 381 382 if (cold || sc->sc_poll || (flags & I2C_F_POLL)) 383 return; 384 385 rw_exit(&sc->sc_i2c_rwlock); 386 } 387 388 static int 389 piixpm_i2c_exec(void *cookie, i2c_op_t op, i2c_addr_t addr, 390 const void *cmdbuf, size_t cmdlen, void *buf, size_t len, int flags) 391 { 392 struct piixpm_softc *sc = cookie; 393 const u_int8_t *b; 394 u_int8_t ctl = 0, st; 395 int retries; 396 397 DPRINTF(("%s: exec: op %d, addr 0x%x, cmdlen %zu, len %zu, flags 0x%x\n", 398 device_xname(sc->sc_dev), op, addr, cmdlen, len, flags)); 399 400 /* Wait for bus to be idle */ 401 for (retries = 100; retries > 0; retries--) { 402 st = bus_space_read_1(sc->sc_smb_iot, sc->sc_smb_ioh, 403 PIIX_SMB_HS); 404 if (!(st & PIIX_SMB_HS_BUSY)) 405 break; 406 DELAY(PIIXPM_DELAY); 407 } 408 DPRINTF(("%s: exec: st 0x%d\n", device_xname(sc->sc_dev), st & 0xff)); 409 if (st & PIIX_SMB_HS_BUSY) 410 return (1); 411 412 if (cold || sc->sc_poll) 413 flags |= I2C_F_POLL; 414 415 if (!I2C_OP_STOP_P(op) || cmdlen > 1 || len > 2 || 416 (cmdlen == 0 && len > 1)) 417 return (1); 418 419 /* Setup transfer */ 420 sc->sc_i2c_xfer.op = op; 421 sc->sc_i2c_xfer.buf = buf; 422 sc->sc_i2c_xfer.len = len; 423 sc->sc_i2c_xfer.flags = flags; 424 sc->sc_i2c_xfer.error = 0; 425 426 /* Set slave address and transfer direction */ 427 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_TXSLVA, 428 PIIX_SMB_TXSLVA_ADDR(addr) | 429 (I2C_OP_READ_P(op) ? PIIX_SMB_TXSLVA_READ : 0)); 430 431 b = cmdbuf; 432 if (cmdlen > 0) 433 /* Set command byte */ 434 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, 435 PIIX_SMB_HCMD, b[0]); 436 437 if (I2C_OP_WRITE_P(op)) { 438 /* Write data */ 439 b = buf; 440 if (cmdlen == 0 && len == 1) 441 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, 442 PIIX_SMB_HCMD, b[0]); 443 else if (len > 0) 444 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, 445 PIIX_SMB_HD0, b[0]); 446 if (len > 1) 447 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, 448 PIIX_SMB_HD1, b[1]); 449 } 450 451 /* Set SMBus command */ 452 if (cmdlen == 0) { 453 if (len == 0) 454 ctl = PIIX_SMB_HC_CMD_QUICK; 455 else 456 ctl = PIIX_SMB_HC_CMD_BYTE; 457 } else if (len == 1) 458 ctl = PIIX_SMB_HC_CMD_BDATA; 459 else if (len == 2) 460 ctl = PIIX_SMB_HC_CMD_WDATA; 461 462 if ((flags & I2C_F_POLL) == 0) 463 ctl |= PIIX_SMB_HC_INTREN; 464 465 /* Start transaction */ 466 ctl |= PIIX_SMB_HC_START; 467 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_HC, ctl); 468 469 if (flags & I2C_F_POLL) { 470 /* Poll for completion */ 471 if (PIIXPM_IS_CSB5(sc->sc_id)) 472 DELAY(2*PIIXPM_DELAY); 473 else 474 DELAY(PIIXPM_DELAY); 475 for (retries = 1000; retries > 0; retries--) { 476 st = bus_space_read_1(sc->sc_smb_iot, sc->sc_smb_ioh, 477 PIIX_SMB_HS); 478 if ((st & PIIX_SMB_HS_BUSY) == 0) 479 break; 480 DELAY(PIIXPM_DELAY); 481 } 482 if (st & PIIX_SMB_HS_BUSY) 483 goto timeout; 484 piixpm_intr(sc); 485 } else { 486 /* Wait for interrupt */ 487 if (tsleep(sc, PRIBIO, "iicexec", PIIXPM_TIMEOUT * hz)) 488 goto timeout; 489 } 490 491 if (sc->sc_i2c_xfer.error) 492 return (1); 493 494 return (0); 495 496 timeout: 497 /* 498 * Transfer timeout. Kill the transaction and clear status bits. 499 */ 500 aprint_error_dev(sc->sc_dev, "timeout, status 0x%x\n", st); 501 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_HC, 502 PIIX_SMB_HC_KILL); 503 DELAY(PIIXPM_DELAY); 504 st = bus_space_read_1(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_HS); 505 if ((st & PIIX_SMB_HS_FAILED) == 0) 506 aprint_error_dev(sc->sc_dev, "transaction abort failed, status 0x%x\n", st); 507 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_HS, st); 508 /* 509 * CSB5 needs hard reset to unlock the smbus after timeout. 510 */ 511 if (PIIXPM_IS_CSB5(sc->sc_id)) 512 piixpm_csb5_reset(sc); 513 return (1); 514 } 515 516 static int 517 piixpm_intr(void *arg) 518 { 519 struct piixpm_softc *sc = arg; 520 u_int8_t st; 521 u_int8_t *b; 522 size_t len; 523 524 /* Read status */ 525 st = bus_space_read_1(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_HS); 526 if ((st & PIIX_SMB_HS_BUSY) != 0 || (st & (PIIX_SMB_HS_INTR | 527 PIIX_SMB_HS_DEVERR | PIIX_SMB_HS_BUSERR | 528 PIIX_SMB_HS_FAILED)) == 0) 529 /* Interrupt was not for us */ 530 return (0); 531 532 DPRINTF(("%s: intr st 0x%d\n", device_xname(sc->sc_dev), st & 0xff)); 533 534 /* Clear status bits */ 535 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_HS, st); 536 537 /* Check for errors */ 538 if (st & (PIIX_SMB_HS_DEVERR | PIIX_SMB_HS_BUSERR | 539 PIIX_SMB_HS_FAILED)) { 540 sc->sc_i2c_xfer.error = 1; 541 goto done; 542 } 543 544 if (st & PIIX_SMB_HS_INTR) { 545 if (I2C_OP_WRITE_P(sc->sc_i2c_xfer.op)) 546 goto done; 547 548 /* Read data */ 549 b = sc->sc_i2c_xfer.buf; 550 len = sc->sc_i2c_xfer.len; 551 if (len > 0) 552 b[0] = bus_space_read_1(sc->sc_smb_iot, sc->sc_smb_ioh, 553 PIIX_SMB_HD0); 554 if (len > 1) 555 b[1] = bus_space_read_1(sc->sc_smb_iot, sc->sc_smb_ioh, 556 PIIX_SMB_HD1); 557 } 558 559 done: 560 if ((sc->sc_i2c_xfer.flags & I2C_F_POLL) == 0) 561 wakeup(sc); 562 return (1); 563 } 564
Indexes created Wed Oct 01 19:09:53 GMT 2025