piixpm.c revision 1.4
1 /* $NetBSD: piixpm.c,v 1.4 2006/06/22 16:49:01 jmcneill Exp $ */ 2 /* $OpenBSD: piixpm.c,v 1.20 2006/02/27 08:25:02 grange Exp $ */ 3 4 /* 5 * Copyright (c) 2005, 2006 Alexander Yurchenko <grange (at) openbsd.org> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 /* 21 * Intel PIIX and compatible Power Management controller driver. 22 */ 23 24 #include <sys/param.h> 25 #include <sys/systm.h> 26 #include <sys/device.h> 27 #include <sys/kernel.h> 28 #include <sys/lock.h> 29 #include <sys/proc.h> 30 31 #include <machine/bus.h> 32 33 #include <dev/pci/pcidevs.h> 34 #include <dev/pci/pcireg.h> 35 #include <dev/pci/pcivar.h> 36 37 #include <dev/pci/piixpmreg.h> 38 39 #include <dev/i2c/i2cvar.h> 40 41 #ifdef __HAVE_TIMECOUNTER 42 #include <sys/timetc.h> 43 #include <machine/bus.h> 44 #endif 45 46 #ifdef PIIXPM_DEBUG 47 #define DPRINTF(x) printf x 48 #else 49 #define DPRINTF(x) 50 #endif 51 52 #define PIIXPM_DELAY 200 53 #define PIIXPM_TIMEOUT 1 54 55 struct piixpm_softc { 56 struct device sc_dev; 57 58 bus_space_tag_t sc_smb_iot; 59 bus_space_handle_t sc_smb_ioh; 60 void * sc_smb_ih; 61 int sc_poll; 62 63 bus_space_tag_t sc_pm_iot; 64 bus_space_handle_t sc_pm_ioh; 65 66 pci_chipset_tag_t sc_pc; 67 pcitag_t sc_pcitag; 68 69 struct i2c_controller sc_i2c_tag; 70 struct lock sc_i2c_lock; 71 struct { 72 i2c_op_t op; 73 void * buf; 74 size_t len; 75 int flags; 76 volatile int error; 77 } sc_i2c_xfer; 78 79 void * sc_powerhook; 80 struct pci_conf_state sc_pciconf; 81 pcireg_t sc_devact[2]; 82 }; 83 84 int piixpm_match(struct device *, struct cfdata *, void *); 85 void piixpm_attach(struct device *, struct device *, void *); 86 87 void piixpm_powerhook(int, void *); 88 89 int piixpm_i2c_acquire_bus(void *, int); 90 void piixpm_i2c_release_bus(void *, int); 91 int piixpm_i2c_exec(void *, i2c_op_t, i2c_addr_t, const void *, size_t, 92 void *, size_t, int); 93 94 int piixpm_intr(void *); 95 96 #ifdef __HAVE_TIMECOUNTER 97 uint32_t piixpm_get_timecount(struct timecounter *); 98 99 #ifndef PIIXPM_FREQUENCY 100 #define PIIXPM_FREQUENCY 3579545 /* from PIIX4 datasheet */ 101 #endif 102 103 static struct timecounter piixpm_timecounter = { 104 piixpm_get_timecount, 105 0, 106 0xffffff, 107 PIIXPM_FREQUENCY, 108 "piixpm", 109 1000 110 }; 111 #endif 112 113 CFATTACH_DECL(piixpm, sizeof(struct piixpm_softc), 114 piixpm_match, piixpm_attach, NULL, NULL); 115 116 int 117 piixpm_match(struct device *parent, struct cfdata *match, void *aux) 118 { 119 struct pci_attach_args *pa; 120 121 pa = (struct pci_attach_args *)aux; 122 switch (PCI_VENDOR(pa->pa_id)) { 123 case PCI_VENDOR_INTEL: 124 switch (PCI_PRODUCT(pa->pa_id)) { 125 case PCI_PRODUCT_INTEL_82371AB_PMC: 126 case PCI_PRODUCT_INTEL_82440MX_PMC: 127 return 1; 128 } 129 break; 130 case PCI_VENDOR_ATI: 131 switch (PCI_PRODUCT(pa->pa_id)) { 132 case PCI_PRODUCT_ATI_SB200_SMB: 133 return 1; 134 } 135 break; 136 } 137 138 return 0; 139 } 140 141 void 142 piixpm_attach(struct device *parent, struct device *self, void *aux) 143 { 144 struct piixpm_softc *sc = (struct piixpm_softc *)self; 145 struct pci_attach_args *pa = aux; 146 struct i2cbus_attach_args iba; 147 pcireg_t base, conf; 148 pci_intr_handle_t ih; 149 const char *intrstr = NULL; 150 151 sc->sc_pc = pa->pa_pc; 152 sc->sc_pcitag = pa->pa_tag; 153 154 aprint_naive("\n"); 155 aprint_normal(": Power Management Controller\n"); 156 157 sc->sc_powerhook = powerhook_establish(piixpm_powerhook, sc); 158 if (sc->sc_powerhook == NULL) 159 aprint_error("%s: can't establish powerhook\n", 160 sc->sc_dev.dv_xname); 161 162 /* Read configuration */ 163 conf = pci_conf_read(pa->pa_pc, pa->pa_tag, PIIX_SMB_HOSTC); 164 DPRINTF((": conf 0x%x", conf)); 165 166 #ifdef __HAVE_TIMECOUNTER 167 sc->sc_pm_iot = pa->pa_iot; 168 /* Map I/O space */ 169 base = pci_conf_read(pa->pa_pc, pa->pa_tag, PIIX_PM_BASE) & 0xffff; 170 if (bus_space_map(sc->sc_pm_iot, PCI_MAPREG_IO_ADDR(base), 171 PIIX_PM_SIZE, 0, &sc->sc_pm_ioh)) { 172 aprint_error("%s: can't map power management I/O space\n", 173 sc->sc_dev.dv_xname); 174 goto nopowermanagement; 175 } 176 177 aprint_normal("%s: 24-bit timer at %" PRIu64 "Hz\n", 178 sc->sc_dev.dv_xname, 179 piixpm_timecounter.tc_frequency); 180 piixpm_timecounter.tc_priv = sc; 181 tc_init(&piixpm_timecounter); 182 183 nopowermanagement: 184 #endif 185 186 if ((conf & PIIX_SMB_HOSTC_HSTEN) == 0) { 187 aprint_normal("%s: SMBus disabled\n", sc->sc_dev.dv_xname); 188 return; 189 } 190 191 /* Map I/O space */ 192 sc->sc_smb_iot = pa->pa_iot; 193 base = pci_conf_read(pa->pa_pc, pa->pa_tag, PIIX_SMB_BASE) & 0xffff; 194 if (bus_space_map(sc->sc_smb_iot, PCI_MAPREG_IO_ADDR(base), 195 PIIX_SMB_SIZE, 0, &sc->sc_smb_ioh)) { 196 aprint_error("%s: can't map smbus I/O space\n", 197 sc->sc_dev.dv_xname); 198 return; 199 } 200 201 sc->sc_poll = 1; 202 if ((conf & PIIX_SMB_HOSTC_INTMASK) == PIIX_SMB_HOSTC_SMI) { 203 /* No PCI IRQ */ 204 aprint_normal("%s: interrupting at SMI", sc->sc_dev.dv_xname); 205 } else if ((conf & PIIX_SMB_HOSTC_INTMASK) == PIIX_SMB_HOSTC_IRQ) { 206 /* Install interrupt handler */ 207 if (pci_intr_map(pa, &ih) == 0) { 208 intrstr = pci_intr_string(pa->pa_pc, ih); 209 sc->sc_smb_ih = pci_intr_establish(pa->pa_pc, ih, IPL_BIO, 210 piixpm_intr, sc); 211 if (sc->sc_smb_ih != NULL) { 212 aprint_normal("%s: interrupting at %s", 213 sc->sc_dev.dv_xname, intrstr); 214 sc->sc_poll = 0; 215 } 216 } 217 if (sc->sc_poll) 218 aprint_normal("%s: polling", sc->sc_dev.dv_xname); 219 } 220 221 aprint_normal("\n"); 222 223 /* Attach I2C bus */ 224 lockinit(&sc->sc_i2c_lock, PRIBIO | PCATCH, "iiclk", 0, 0); 225 sc->sc_i2c_tag.ic_cookie = sc; 226 sc->sc_i2c_tag.ic_acquire_bus = piixpm_i2c_acquire_bus; 227 sc->sc_i2c_tag.ic_release_bus = piixpm_i2c_release_bus; 228 sc->sc_i2c_tag.ic_exec = piixpm_i2c_exec; 229 230 bzero(&iba, sizeof(iba)); 231 iba.iba_name = "iic"; 232 iba.iba_tag = &sc->sc_i2c_tag; 233 config_found(self, &iba, iicbus_print); 234 235 return; 236 } 237 238 void 239 piixpm_powerhook(int why, void *cookie) 240 { 241 struct piixpm_softc *sc = cookie; 242 pci_chipset_tag_t pc = sc->sc_pc; 243 pcitag_t tag = sc->sc_pcitag; 244 245 switch (why) { 246 case PWR_SUSPEND: 247 pci_conf_capture(pc, tag, &sc->sc_pciconf); 248 sc->sc_devact[0] = pci_conf_read(pc, tag, PIIX_DEVACTA); 249 sc->sc_devact[1] = pci_conf_read(pc, tag, PIIX_DEVACTB); 250 break; 251 case PWR_RESUME: 252 pci_conf_restore(pc, tag, &sc->sc_pciconf); 253 pci_conf_write(pc, tag, PIIX_DEVACTA, sc->sc_devact[0]); 254 pci_conf_write(pc, tag, PIIX_DEVACTB, sc->sc_devact[1]); 255 break; 256 } 257 258 return; 259 } 260 261 int 262 piixpm_i2c_acquire_bus(void *cookie, int flags) 263 { 264 struct piixpm_softc *sc = cookie; 265 266 if (cold || sc->sc_poll || (flags & I2C_F_POLL)) 267 return (0); 268 269 return (lockmgr(&sc->sc_i2c_lock, LK_EXCLUSIVE, NULL)); 270 } 271 272 void 273 piixpm_i2c_release_bus(void *cookie, int flags) 274 { 275 struct piixpm_softc *sc = cookie; 276 277 if (cold || sc->sc_poll || (flags & I2C_F_POLL)) 278 return; 279 280 lockmgr(&sc->sc_i2c_lock, LK_RELEASE, NULL); 281 } 282 283 int 284 piixpm_i2c_exec(void *cookie, i2c_op_t op, i2c_addr_t addr, 285 const void *cmdbuf, size_t cmdlen, void *buf, size_t len, int flags) 286 { 287 struct piixpm_softc *sc = cookie; 288 const u_int8_t *b; 289 u_int8_t ctl = 0, st; 290 int retries; 291 292 DPRINTF(("%s: exec: op %d, addr 0x%x, cmdlen %d, len %d, flags 0x%x\n", 293 sc->sc_dev.dv_xname, op, addr, cmdlen, len, flags)); 294 295 /* Wait for bus to be idle */ 296 for (retries = 100; retries > 0; retries--) { 297 st = bus_space_read_1(sc->sc_smb_iot, sc->sc_smb_ioh, 298 PIIX_SMB_HS); 299 if (!(st & PIIX_SMB_HS_BUSY)) 300 break; 301 DELAY(PIIXPM_DELAY); 302 } 303 DPRINTF(("%s: exec: st 0x%b\n", sc->sc_dev.dv_xname, st, 304 PIIX_SMB_HS_BITS)); 305 if (st & PIIX_SMB_HS_BUSY) 306 return (1); 307 308 if (cold || sc->sc_poll) 309 flags |= I2C_F_POLL; 310 311 if (!I2C_OP_STOP_P(op) || cmdlen > 1 || len > 2) 312 return (1); 313 314 /* Setup transfer */ 315 sc->sc_i2c_xfer.op = op; 316 sc->sc_i2c_xfer.buf = buf; 317 sc->sc_i2c_xfer.len = len; 318 sc->sc_i2c_xfer.flags = flags; 319 sc->sc_i2c_xfer.error = 0; 320 321 /* Set slave address and transfer direction */ 322 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_TXSLVA, 323 PIIX_SMB_TXSLVA_ADDR(addr) | 324 (I2C_OP_READ_P(op) ? PIIX_SMB_TXSLVA_READ : 0)); 325 326 b = cmdbuf; 327 if (cmdlen > 0) 328 /* Set command byte */ 329 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, 330 PIIX_SMB_HCMD, b[0]); 331 332 if (I2C_OP_WRITE_P(op)) { 333 /* Write data */ 334 b = buf; 335 if (len > 0) 336 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, 337 PIIX_SMB_HD0, b[0]); 338 if (len > 1) 339 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, 340 PIIX_SMB_HD1, b[1]); 341 } 342 343 /* Set SMBus command */ 344 if (len == 0) 345 ctl = PIIX_SMB_HC_CMD_BYTE; 346 else if (len == 1) 347 ctl = PIIX_SMB_HC_CMD_BDATA; 348 else if (len == 2) 349 ctl = PIIX_SMB_HC_CMD_WDATA; 350 351 if ((flags & I2C_F_POLL) == 0) 352 ctl |= PIIX_SMB_HC_INTREN; 353 354 /* Start transaction */ 355 ctl |= PIIX_SMB_HC_START; 356 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_HC, ctl); 357 358 if (flags & I2C_F_POLL) { 359 /* Poll for completion */ 360 DELAY(PIIXPM_DELAY); 361 for (retries = 1000; retries > 0; retries--) { 362 st = bus_space_read_1(sc->sc_smb_iot, sc->sc_smb_ioh, 363 PIIX_SMB_HS); 364 if ((st & PIIX_SMB_HS_BUSY) == 0) 365 break; 366 DELAY(PIIXPM_DELAY); 367 } 368 if (st & PIIX_SMB_HS_BUSY) 369 goto timeout; 370 piixpm_intr(sc); 371 } else { 372 /* Wait for interrupt */ 373 if (tsleep(sc, PRIBIO, "iicexec", PIIXPM_TIMEOUT * hz)) 374 goto timeout; 375 } 376 377 if (sc->sc_i2c_xfer.error) 378 return (1); 379 380 return (0); 381 382 timeout: 383 /* 384 * Transfer timeout. Kill the transaction and clear status bits. 385 */ 386 aprint_error("%s: timeout, status 0x%x\n", sc->sc_dev.dv_xname, st); 387 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_HC, 388 PIIX_SMB_HC_KILL); 389 DELAY(PIIXPM_DELAY); 390 st = bus_space_read_1(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_HS); 391 if ((st & PIIX_SMB_HS_FAILED) == 0) 392 aprint_error("%s: transaction abort failed, status 0x%x\n", 393 sc->sc_dev.dv_xname, st); 394 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_HS, st); 395 return (1); 396 } 397 398 int 399 piixpm_intr(void *arg) 400 { 401 struct piixpm_softc *sc = arg; 402 u_int8_t st; 403 u_int8_t *b; 404 size_t len; 405 406 /* Read status */ 407 st = bus_space_read_1(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_HS); 408 if ((st & PIIX_SMB_HS_BUSY) != 0 || (st & (PIIX_SMB_HS_INTR | 409 PIIX_SMB_HS_DEVERR | PIIX_SMB_HS_BUSERR | 410 PIIX_SMB_HS_FAILED)) == 0) 411 /* Interrupt was not for us */ 412 return (0); 413 414 DPRINTF(("%s: intr st 0x%b\n", sc->sc_dev.dv_xname, st, 415 PIIX_SMB_HS_BITS)); 416 417 /* Clear status bits */ 418 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_HS, st); 419 420 /* Check for errors */ 421 if (st & (PIIX_SMB_HS_DEVERR | PIIX_SMB_HS_BUSERR | 422 PIIX_SMB_HS_FAILED)) { 423 sc->sc_i2c_xfer.error = 1; 424 goto done; 425 } 426 427 if (st & PIIX_SMB_HS_INTR) { 428 if (I2C_OP_WRITE_P(sc->sc_i2c_xfer.op)) 429 goto done; 430 431 /* Read data */ 432 b = sc->sc_i2c_xfer.buf; 433 len = sc->sc_i2c_xfer.len; 434 if (len > 0) 435 b[0] = bus_space_read_1(sc->sc_smb_iot, sc->sc_smb_ioh, 436 PIIX_SMB_HD0); 437 if (len > 1) 438 b[1] = bus_space_read_1(sc->sc_smb_iot, sc->sc_smb_ioh, 439 PIIX_SMB_HD1); 440 } 441 442 done: 443 if ((sc->sc_i2c_xfer.flags & I2C_F_POLL) == 0) 444 wakeup(sc); 445 return (1); 446 } 447 448 #ifdef __HAVE_TIMECOUNTER 449 uint32_t 450 piixpm_get_timecount(struct timecounter *tc) 451 { 452 struct piixpm_softc *sc; 453 454 sc = (struct piixpm_softc *)tc->tc_priv; 455 456 return bus_space_read_4(sc->sc_pm_iot, sc->sc_pm_ioh, PIIX_PM_PMTMR); 457 } 458 #endif 459
Indexes created Mon Sep 29 18:09:42 GMT 2025