piixpm.c revision 1.40.2.1
1 /* $NetBSD: piixpm.c,v 1.40.2.1 2013/09/20 03:49:00 riz Exp $ */ 2 /* $OpenBSD: piixpm.c,v 1.20 2006/02/27 08:25:02 grange Exp $ */ 3 4 /* 5 * Copyright (c) 2005, 2006 Alexander Yurchenko <grange (at) openbsd.org> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 /* 21 * Intel PIIX and compatible Power Management controller driver. 22 */ 23 24 #include <sys/cdefs.h> 25 __KERNEL_RCSID(0, "$NetBSD: piixpm.c,v 1.40.2.1 2013/09/20 03:49:00 riz Exp $"); 26 27 #include <sys/param.h> 28 #include <sys/systm.h> 29 #include <sys/device.h> 30 #include <sys/kernel.h> 31 #include <sys/mutex.h> 32 #include <sys/proc.h> 33 34 #include <sys/bus.h> 35 36 #include <dev/pci/pcidevs.h> 37 #include <dev/pci/pcireg.h> 38 #include <dev/pci/pcivar.h> 39 40 #include <dev/pci/piixpmreg.h> 41 42 #include <dev/i2c/i2cvar.h> 43 44 #include <dev/ic/acpipmtimer.h> 45 46 #ifdef PIIXPM_DEBUG 47 #define DPRINTF(x) printf x 48 #else 49 #define DPRINTF(x) 50 #endif 51 52 #define PIIXPM_IS_CSB5(id) \ 53 (PCI_VENDOR((id)) == PCI_VENDOR_SERVERWORKS && \ 54 PCI_PRODUCT((id)) == PCI_PRODUCT_SERVERWORKS_CSB5) 55 #define PIIXPM_DELAY 200 56 #define PIIXPM_TIMEOUT 1 57 58 struct piixpm_smbus { 59 int sda; 60 struct piixpm_softc *softc; 61 }; 62 63 struct piixpm_softc { 64 device_t sc_dev; 65 66 bus_space_tag_t sc_iot; 67 #define sc_pm_iot sc_iot 68 #define sc_smb_iot sc_iot 69 bus_space_handle_t sc_pm_ioh; 70 bus_space_handle_t sc_sb800_ioh; 71 bus_space_handle_t sc_smb_ioh; 72 void * sc_smb_ih; 73 int sc_poll; 74 75 pci_chipset_tag_t sc_pc; 76 pcitag_t sc_pcitag; 77 pcireg_t sc_id; 78 79 struct piixpm_smbus sc_busses[4]; 80 struct i2c_controller sc_i2c_tags[4]; 81 82 kmutex_t sc_i2c_mutex; 83 struct { 84 i2c_op_t op; 85 void * buf; 86 size_t len; 87 int flags; 88 volatile int error; 89 } sc_i2c_xfer; 90 91 pcireg_t sc_devact[2]; 92 }; 93 94 static int piixpm_match(device_t, cfdata_t, void *); 95 static void piixpm_attach(device_t, device_t, void *); 96 97 static bool piixpm_suspend(device_t, const pmf_qual_t *); 98 static bool piixpm_resume(device_t, const pmf_qual_t *); 99 100 static int piixpm_sb800_init(struct piixpm_softc *); 101 static void piixpm_csb5_reset(void *); 102 static int piixpm_i2c_acquire_bus(void *, int); 103 static void piixpm_i2c_release_bus(void *, int); 104 static int piixpm_i2c_exec(void *, i2c_op_t, i2c_addr_t, const void *, 105 size_t, void *, size_t, int); 106 107 static int piixpm_intr(void *); 108 109 CFATTACH_DECL_NEW(piixpm, sizeof(struct piixpm_softc), 110 piixpm_match, piixpm_attach, NULL, NULL); 111 112 static int 113 piixpm_match(device_t parent, cfdata_t match, void *aux) 114 { 115 struct pci_attach_args *pa; 116 117 pa = (struct pci_attach_args *)aux; 118 switch (PCI_VENDOR(pa->pa_id)) { 119 case PCI_VENDOR_INTEL: 120 switch (PCI_PRODUCT(pa->pa_id)) { 121 case PCI_PRODUCT_INTEL_82371AB_PMC: 122 case PCI_PRODUCT_INTEL_82440MX_PMC: 123 return 1; 124 } 125 break; 126 case PCI_VENDOR_ATI: 127 switch (PCI_PRODUCT(pa->pa_id)) { 128 case PCI_PRODUCT_ATI_SB200_SMB: 129 case PCI_PRODUCT_ATI_SB300_SMB: 130 case PCI_PRODUCT_ATI_SB400_SMB: 131 case PCI_PRODUCT_ATI_SB600_SMB: /* matches SB600/SB700/SB800 */ 132 return 1; 133 } 134 break; 135 case PCI_VENDOR_SERVERWORKS: 136 switch (PCI_PRODUCT(pa->pa_id)) { 137 case PCI_PRODUCT_SERVERWORKS_OSB4: 138 case PCI_PRODUCT_SERVERWORKS_CSB5: 139 case PCI_PRODUCT_SERVERWORKS_CSB6: 140 case PCI_PRODUCT_SERVERWORKS_HT1000SB: 141 return 1; 142 } 143 } 144 145 return 0; 146 } 147 148 static void 149 piixpm_attach(device_t parent, device_t self, void *aux) 150 { 151 struct piixpm_softc *sc = device_private(self); 152 struct pci_attach_args *pa = aux; 153 struct i2cbus_attach_args iba; 154 pcireg_t base, conf; 155 pcireg_t pmmisc; 156 pci_intr_handle_t ih; 157 const char *intrstr = NULL; 158 int i, numbusses = 1; 159 160 sc->sc_dev = self; 161 sc->sc_iot = pa->pa_iot; 162 sc->sc_id = pa->pa_id; 163 sc->sc_pc = pa->pa_pc; 164 sc->sc_pcitag = pa->pa_tag; 165 166 pci_aprint_devinfo(pa, NULL); 167 168 if (!pmf_device_register(self, piixpm_suspend, piixpm_resume)) 169 aprint_error_dev(self, "couldn't establish power handler\n"); 170 171 /* Read configuration */ 172 conf = pci_conf_read(pa->pa_pc, pa->pa_tag, PIIX_SMB_HOSTC); 173 DPRINTF(("%s: conf 0x%x\n", device_xname(self), conf)); 174 175 if ((PCI_VENDOR(pa->pa_id) != PCI_VENDOR_INTEL) || 176 (PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_INTEL_82371AB_PMC)) 177 goto nopowermanagement; 178 179 /* check whether I/O access to PM regs is enabled */ 180 pmmisc = pci_conf_read(pa->pa_pc, pa->pa_tag, PIIX_PMREGMISC); 181 if (!(pmmisc & 1)) 182 goto nopowermanagement; 183 184 /* Map I/O space */ 185 base = pci_conf_read(pa->pa_pc, pa->pa_tag, PIIX_PM_BASE); 186 if (bus_space_map(sc->sc_pm_iot, PCI_MAPREG_IO_ADDR(base), 187 PIIX_PM_SIZE, 0, &sc->sc_pm_ioh)) { 188 aprint_error_dev(self, "can't map power management I/O space\n"); 189 goto nopowermanagement; 190 } 191 192 /* 193 * Revision 0 and 1 are PIIX4, 2 is PIIX4E, 3 is PIIX4M. 194 * PIIX4 and PIIX4E have a bug in the timer latch, see Errata #20 195 * in the "Specification update" (document #297738). 196 */ 197 acpipmtimer_attach(self, sc->sc_pm_iot, sc->sc_pm_ioh, 198 PIIX_PM_PMTMR, 199 (PCI_REVISION(pa->pa_class) < 3) ? ACPIPMT_BADLATCH : 0 ); 200 201 nopowermanagement: 202 203 /* SB800 rev 0x40+ needs special initialization */ 204 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_ATI && 205 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_ATI_SB600_SMB && 206 PCI_REVISION(pa->pa_class) >= 0x40) { 207 if (piixpm_sb800_init(sc) == 0) { 208 numbusses = 4; 209 goto attach_i2c; 210 } 211 aprint_normal_dev(self, "SMBus disabled\n"); 212 return; 213 } 214 215 if ((conf & PIIX_SMB_HOSTC_HSTEN) == 0) { 216 aprint_normal_dev(self, "SMBus disabled\n"); 217 return; 218 } 219 220 /* Map I/O space */ 221 base = pci_conf_read(pa->pa_pc, pa->pa_tag, PIIX_SMB_BASE) & 0xffff; 222 if (bus_space_map(sc->sc_smb_iot, PCI_MAPREG_IO_ADDR(base), 223 PIIX_SMB_SIZE, 0, &sc->sc_smb_ioh)) { 224 aprint_error_dev(self, "can't map smbus I/O space\n"); 225 return; 226 } 227 228 sc->sc_poll = 1; 229 aprint_normal_dev(self, ""); 230 if ((conf & PIIX_SMB_HOSTC_INTMASK) == PIIX_SMB_HOSTC_SMI) { 231 /* No PCI IRQ */ 232 aprint_normal("interrupting at SMI, "); 233 } else if ((conf & PIIX_SMB_HOSTC_INTMASK) == PIIX_SMB_HOSTC_IRQ) { 234 /* Install interrupt handler */ 235 if (pci_intr_map(pa, &ih) == 0) { 236 intrstr = pci_intr_string(pa->pa_pc, ih); 237 sc->sc_smb_ih = pci_intr_establish(pa->pa_pc, ih, IPL_BIO, 238 piixpm_intr, sc); 239 if (sc->sc_smb_ih != NULL) { 240 aprint_normal("interrupting at %s", intrstr); 241 sc->sc_poll = 0; 242 } 243 } 244 } 245 if (sc->sc_poll) 246 aprint_normal("polling"); 247 248 aprint_normal("\n"); 249 250 attach_i2c: 251 /* Attach I2C bus */ 252 mutex_init(&sc->sc_i2c_mutex, MUTEX_DEFAULT, IPL_NONE); 253 254 for (i = 0; i < numbusses; i++) { 255 sc->sc_busses[i].sda = i; 256 sc->sc_busses[i].softc = sc; 257 sc->sc_i2c_tags[i].ic_cookie = &sc->sc_busses[i]; 258 sc->sc_i2c_tags[i].ic_acquire_bus = piixpm_i2c_acquire_bus; 259 sc->sc_i2c_tags[i].ic_release_bus = piixpm_i2c_release_bus; 260 sc->sc_i2c_tags[i].ic_exec = piixpm_i2c_exec; 261 262 memset(&iba, 0, sizeof(iba)); 263 iba.iba_type = I2C_TYPE_SMBUS; 264 iba.iba_tag = &sc->sc_i2c_tags[i]; 265 config_found_ia(self, "i2cbus", &iba, iicbus_print); 266 } 267 } 268 269 static bool 270 piixpm_suspend(device_t dv, const pmf_qual_t *qual) 271 { 272 struct piixpm_softc *sc = device_private(dv); 273 274 sc->sc_devact[0] = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 275 PIIX_DEVACTA); 276 sc->sc_devact[1] = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 277 PIIX_DEVACTB); 278 279 return true; 280 } 281 282 static bool 283 piixpm_resume(device_t dv, const pmf_qual_t *qual) 284 { 285 struct piixpm_softc *sc = device_private(dv); 286 287 pci_conf_write(sc->sc_pc, sc->sc_pcitag, PIIX_DEVACTA, 288 sc->sc_devact[0]); 289 pci_conf_write(sc->sc_pc, sc->sc_pcitag, PIIX_DEVACTB, 290 sc->sc_devact[1]); 291 292 return true; 293 } 294 295 /* 296 * Extract SMBus base address from SB800 Power Management (PM) registers. 297 * The PM registers can be accessed either through indirect I/O (CD6/CD7) or 298 * direct mapping if AcpiMMioDecodeEn is enabled. Since this function is only 299 * called once it uses indirect I/O for simplicity. 300 */ 301 static int 302 piixpm_sb800_init(struct piixpm_softc *sc) 303 { 304 bus_space_tag_t iot = sc->sc_iot; 305 bus_space_handle_t ioh; /* indirect I/O handle */ 306 uint16_t val, base_addr; 307 308 /* Fetch SMB base address */ 309 if (bus_space_map(iot, 310 PIIXPM_INDIRECTIO_BASE, PIIXPM_INDIRECTIO_SIZE, 0, &ioh)) { 311 device_printf(sc->sc_dev, "couldn't map indirect I/O space\n"); 312 return EBUSY; 313 } 314 bus_space_write_1(iot, ioh, PIIXPM_INDIRECTIO_INDEX, 315 SB800_PM_SMBUS0EN_LO); 316 val = bus_space_read_1(iot, ioh, PIIXPM_INDIRECTIO_DATA); 317 bus_space_write_1(iot, ioh, PIIXPM_INDIRECTIO_INDEX, 318 SB800_PM_SMBUS0EN_HI); 319 val |= bus_space_read_1(iot, ioh, PIIXPM_INDIRECTIO_DATA) << 8; 320 sc->sc_sb800_ioh = ioh; 321 322 if ((val & SB800_PM_SMBUS0EN_ENABLE) == 0) 323 return ENOENT; 324 325 base_addr = val & SB800_PM_SMBUS0EN_BADDR; 326 327 aprint_debug_dev(sc->sc_dev, "SMBus @ 0x%04x\n", base_addr); 328 329 bus_space_write_1(iot, ioh, PIIXPM_INDIRECTIO_INDEX, SB800_PM_SMBUS0SELEN); 330 bus_space_write_1(iot, ioh, PIIXPM_INDIRECTIO_DATA, 1); /* SMBUS0SEL */ 331 332 if (bus_space_map(iot, PCI_MAPREG_IO_ADDR(base_addr), 333 PIIX_SMB_SIZE, 0, &sc->sc_smb_ioh)) { 334 aprint_error_dev(sc->sc_dev, "can't map smbus I/O space\n"); 335 return EBUSY; 336 } 337 aprint_normal_dev(sc->sc_dev, "polling (SB800)\n"); 338 sc->sc_poll = 1; 339 340 return 0; 341 } 342 343 static void 344 piixpm_csb5_reset(void *arg) 345 { 346 struct piixpm_softc *sc = arg; 347 pcireg_t base, hostc, pmbase; 348 349 base = pci_conf_read(sc->sc_pc, sc->sc_pcitag, PIIX_SMB_BASE); 350 hostc = pci_conf_read(sc->sc_pc, sc->sc_pcitag, PIIX_SMB_HOSTC); 351 352 pmbase = pci_conf_read(sc->sc_pc, sc->sc_pcitag, PIIX_PM_BASE); 353 pmbase |= PIIX_PM_BASE_CSB5_RESET; 354 pci_conf_write(sc->sc_pc, sc->sc_pcitag, PIIX_PM_BASE, pmbase); 355 pmbase &= ~PIIX_PM_BASE_CSB5_RESET; 356 pci_conf_write(sc->sc_pc, sc->sc_pcitag, PIIX_PM_BASE, pmbase); 357 358 pci_conf_write(sc->sc_pc, sc->sc_pcitag, PIIX_SMB_BASE, base); 359 pci_conf_write(sc->sc_pc, sc->sc_pcitag, PIIX_SMB_HOSTC, hostc); 360 361 (void) tsleep(&sc, PRIBIO, "csb5reset", hz/2); 362 } 363 364 static int 365 piixpm_i2c_acquire_bus(void *cookie, int flags) 366 { 367 struct piixpm_smbus *smbus = cookie; 368 struct piixpm_softc *sc = smbus->softc; 369 370 if (!cold) 371 mutex_enter(&sc->sc_i2c_mutex); 372 373 if (smbus->sda > 0) /* SB800 */ 374 { 375 bus_space_write_1(sc->sc_iot, sc->sc_sb800_ioh, 376 PIIXPM_INDIRECTIO_INDEX, SB800_PM_SMBUS0SEL); 377 bus_space_write_1(sc->sc_iot, sc->sc_sb800_ioh, 378 PIIXPM_INDIRECTIO_DATA, smbus->sda << 1); 379 } 380 381 return 0; 382 } 383 384 static void 385 piixpm_i2c_release_bus(void *cookie, int flags) 386 { 387 struct piixpm_smbus *smbus = cookie; 388 struct piixpm_softc *sc = smbus->softc; 389 390 if (smbus->sda > 0) /* SB800 */ 391 { 392 /* 393 * HP Microserver hangs after reboot if not set to SDA0. 394 * Also add shutdown hook? 395 */ 396 bus_space_write_1(sc->sc_iot, sc->sc_sb800_ioh, 397 PIIXPM_INDIRECTIO_INDEX, SB800_PM_SMBUS0SEL); 398 bus_space_write_1(sc->sc_iot, sc->sc_sb800_ioh, 399 PIIXPM_INDIRECTIO_DATA, 0); 400 } 401 402 if (!cold) 403 mutex_exit(&sc->sc_i2c_mutex); 404 } 405 406 static int 407 piixpm_i2c_exec(void *cookie, i2c_op_t op, i2c_addr_t addr, 408 const void *cmdbuf, size_t cmdlen, void *buf, size_t len, int flags) 409 { 410 struct piixpm_smbus *smbus = cookie; 411 struct piixpm_softc *sc = smbus->softc; 412 const u_int8_t *b; 413 u_int8_t ctl = 0, st; 414 int retries; 415 416 DPRINTF(("%s: exec: op %d, addr 0x%x, cmdlen %zu, len %zu, flags 0x%x\n", 417 device_xname(sc->sc_dev), op, addr, cmdlen, len, flags)); 418 419 /* Wait for bus to be idle */ 420 for (retries = 100; retries > 0; retries--) { 421 st = bus_space_read_1(sc->sc_smb_iot, sc->sc_smb_ioh, 422 PIIX_SMB_HS); 423 if (!(st & PIIX_SMB_HS_BUSY)) 424 break; 425 DELAY(PIIXPM_DELAY); 426 } 427 DPRINTF(("%s: exec: st 0x%d\n", device_xname(sc->sc_dev), st & 0xff)); 428 if (st & PIIX_SMB_HS_BUSY) 429 return (1); 430 431 if (cold || sc->sc_poll) 432 flags |= I2C_F_POLL; 433 434 if (!I2C_OP_STOP_P(op) || cmdlen > 1 || len > 2 || 435 (cmdlen == 0 && len > 1)) 436 return (1); 437 438 /* Setup transfer */ 439 sc->sc_i2c_xfer.op = op; 440 sc->sc_i2c_xfer.buf = buf; 441 sc->sc_i2c_xfer.len = len; 442 sc->sc_i2c_xfer.flags = flags; 443 sc->sc_i2c_xfer.error = 0; 444 445 /* Set slave address and transfer direction */ 446 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_TXSLVA, 447 PIIX_SMB_TXSLVA_ADDR(addr) | 448 (I2C_OP_READ_P(op) ? PIIX_SMB_TXSLVA_READ : 0)); 449 450 b = cmdbuf; 451 if (cmdlen > 0) 452 /* Set command byte */ 453 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, 454 PIIX_SMB_HCMD, b[0]); 455 456 if (I2C_OP_WRITE_P(op)) { 457 /* Write data */ 458 b = buf; 459 if (cmdlen == 0 && len == 1) 460 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, 461 PIIX_SMB_HCMD, b[0]); 462 else if (len > 0) 463 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, 464 PIIX_SMB_HD0, b[0]); 465 if (len > 1) 466 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, 467 PIIX_SMB_HD1, b[1]); 468 } 469 470 /* Set SMBus command */ 471 if (cmdlen == 0) { 472 if (len == 0) 473 ctl = PIIX_SMB_HC_CMD_QUICK; 474 else 475 ctl = PIIX_SMB_HC_CMD_BYTE; 476 } else if (len == 1) 477 ctl = PIIX_SMB_HC_CMD_BDATA; 478 else if (len == 2) 479 ctl = PIIX_SMB_HC_CMD_WDATA; 480 481 if ((flags & I2C_F_POLL) == 0) 482 ctl |= PIIX_SMB_HC_INTREN; 483 484 /* Start transaction */ 485 ctl |= PIIX_SMB_HC_START; 486 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_HC, ctl); 487 488 if (flags & I2C_F_POLL) { 489 /* Poll for completion */ 490 if (PIIXPM_IS_CSB5(sc->sc_id)) 491 DELAY(2*PIIXPM_DELAY); 492 else 493 DELAY(PIIXPM_DELAY); 494 for (retries = 1000; retries > 0; retries--) { 495 st = bus_space_read_1(sc->sc_smb_iot, sc->sc_smb_ioh, 496 PIIX_SMB_HS); 497 if ((st & PIIX_SMB_HS_BUSY) == 0) 498 break; 499 DELAY(PIIXPM_DELAY); 500 } 501 if (st & PIIX_SMB_HS_BUSY) 502 goto timeout; 503 piixpm_intr(smbus); 504 } else { 505 /* Wait for interrupt */ 506 if (tsleep(sc, PRIBIO, "iicexec", PIIXPM_TIMEOUT * hz)) 507 goto timeout; 508 } 509 510 if (sc->sc_i2c_xfer.error) 511 return (1); 512 513 return (0); 514 515 timeout: 516 /* 517 * Transfer timeout. Kill the transaction and clear status bits. 518 */ 519 aprint_error_dev(sc->sc_dev, "timeout, status 0x%x\n", st); 520 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_HC, 521 PIIX_SMB_HC_KILL); 522 DELAY(PIIXPM_DELAY); 523 st = bus_space_read_1(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_HS); 524 if ((st & PIIX_SMB_HS_FAILED) == 0) 525 aprint_error_dev(sc->sc_dev, "transaction abort failed, status 0x%x\n", st); 526 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_HS, st); 527 /* 528 * CSB5 needs hard reset to unlock the smbus after timeout. 529 */ 530 if (PIIXPM_IS_CSB5(sc->sc_id)) 531 piixpm_csb5_reset(sc); 532 return (1); 533 } 534 535 static int 536 piixpm_intr(void *arg) 537 { 538 struct piixpm_smbus *smbus = arg; 539 struct piixpm_softc *sc = smbus->softc; 540 u_int8_t st; 541 u_int8_t *b; 542 size_t len; 543 544 /* Read status */ 545 st = bus_space_read_1(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_HS); 546 if ((st & PIIX_SMB_HS_BUSY) != 0 || (st & (PIIX_SMB_HS_INTR | 547 PIIX_SMB_HS_DEVERR | PIIX_SMB_HS_BUSERR | 548 PIIX_SMB_HS_FAILED)) == 0) 549 /* Interrupt was not for us */ 550 return (0); 551 552 DPRINTF(("%s: intr st 0x%d\n", device_xname(sc->sc_dev), st & 0xff)); 553 554 /* Clear status bits */ 555 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_HS, st); 556 557 /* Check for errors */ 558 if (st & (PIIX_SMB_HS_DEVERR | PIIX_SMB_HS_BUSERR | 559 PIIX_SMB_HS_FAILED)) { 560 sc->sc_i2c_xfer.error = 1; 561 goto done; 562 } 563 564 if (st & PIIX_SMB_HS_INTR) { 565 if (I2C_OP_WRITE_P(sc->sc_i2c_xfer.op)) 566 goto done; 567 568 /* Read data */ 569 b = sc->sc_i2c_xfer.buf; 570 len = sc->sc_i2c_xfer.len; 571 if (len > 0) 572 b[0] = bus_space_read_1(sc->sc_smb_iot, sc->sc_smb_ioh, 573 PIIX_SMB_HD0); 574 if (len > 1) 575 b[1] = bus_space_read_1(sc->sc_smb_iot, sc->sc_smb_ioh, 576 PIIX_SMB_HD1); 577 } 578 579 done: 580 if ((sc->sc_i2c_xfer.flags & I2C_F_POLL) == 0) 581 wakeup(sc); 582 return (1); 583 } 584
Indexes created Wed Oct 01 19:09:53 GMT 2025