piixpm.c revision 1.44
1 /* $NetBSD: piixpm.c,v 1.44 2014/03/29 19:28:25 christos Exp $ */ 2 /* $OpenBSD: piixpm.c,v 1.20 2006/02/27 08:25:02 grange Exp $ */ 3 4 /* 5 * Copyright (c) 2005, 2006 Alexander Yurchenko <grange (at) openbsd.org> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 /* 21 * Intel PIIX and compatible Power Management controller driver. 22 */ 23 24 #include <sys/cdefs.h> 25 __KERNEL_RCSID(0, "$NetBSD: piixpm.c,v 1.44 2014/03/29 19:28:25 christos Exp $"); 26 27 #include <sys/param.h> 28 #include <sys/systm.h> 29 #include <sys/device.h> 30 #include <sys/kernel.h> 31 #include <sys/mutex.h> 32 #include <sys/proc.h> 33 34 #include <sys/bus.h> 35 36 #include <dev/pci/pcidevs.h> 37 #include <dev/pci/pcireg.h> 38 #include <dev/pci/pcivar.h> 39 40 #include <dev/pci/piixpmreg.h> 41 42 #include <dev/i2c/i2cvar.h> 43 44 #include <dev/ic/acpipmtimer.h> 45 46 #ifdef PIIXPM_DEBUG 47 #define DPRINTF(x) printf x 48 #else 49 #define DPRINTF(x) 50 #endif 51 52 #define PIIXPM_IS_CSB5(id) \ 53 (PCI_VENDOR((id)) == PCI_VENDOR_SERVERWORKS && \ 54 PCI_PRODUCT((id)) == PCI_PRODUCT_SERVERWORKS_CSB5) 55 #define PIIXPM_DELAY 200 56 #define PIIXPM_TIMEOUT 1 57 58 struct piixpm_smbus { 59 int sda; 60 struct piixpm_softc *softc; 61 }; 62 63 struct piixpm_softc { 64 device_t sc_dev; 65 66 bus_space_tag_t sc_iot; 67 #define sc_pm_iot sc_iot 68 #define sc_smb_iot sc_iot 69 bus_space_handle_t sc_pm_ioh; 70 bus_space_handle_t sc_sb800_ioh; 71 bus_space_handle_t sc_smb_ioh; 72 void * sc_smb_ih; 73 int sc_poll; 74 75 pci_chipset_tag_t sc_pc; 76 pcitag_t sc_pcitag; 77 pcireg_t sc_id; 78 79 struct piixpm_smbus sc_busses[4]; 80 struct i2c_controller sc_i2c_tags[4]; 81 82 kmutex_t sc_i2c_mutex; 83 struct { 84 i2c_op_t op; 85 void * buf; 86 size_t len; 87 int flags; 88 volatile int error; 89 } sc_i2c_xfer; 90 91 pcireg_t sc_devact[2]; 92 }; 93 94 static int piixpm_match(device_t, cfdata_t, void *); 95 static void piixpm_attach(device_t, device_t, void *); 96 97 static bool piixpm_suspend(device_t, const pmf_qual_t *); 98 static bool piixpm_resume(device_t, const pmf_qual_t *); 99 100 static int piixpm_sb800_init(struct piixpm_softc *); 101 static void piixpm_csb5_reset(void *); 102 static int piixpm_i2c_acquire_bus(void *, int); 103 static void piixpm_i2c_release_bus(void *, int); 104 static int piixpm_i2c_exec(void *, i2c_op_t, i2c_addr_t, const void *, 105 size_t, void *, size_t, int); 106 107 static int piixpm_intr(void *); 108 109 CFATTACH_DECL_NEW(piixpm, sizeof(struct piixpm_softc), 110 piixpm_match, piixpm_attach, NULL, NULL); 111 112 static int 113 piixpm_match(device_t parent, cfdata_t match, void *aux) 114 { 115 struct pci_attach_args *pa; 116 117 pa = (struct pci_attach_args *)aux; 118 switch (PCI_VENDOR(pa->pa_id)) { 119 case PCI_VENDOR_INTEL: 120 switch (PCI_PRODUCT(pa->pa_id)) { 121 case PCI_PRODUCT_INTEL_82371AB_PMC: 122 case PCI_PRODUCT_INTEL_82440MX_PMC: 123 return 1; 124 } 125 break; 126 case PCI_VENDOR_ATI: 127 switch (PCI_PRODUCT(pa->pa_id)) { 128 case PCI_PRODUCT_ATI_SB200_SMB: 129 case PCI_PRODUCT_ATI_SB300_SMB: 130 case PCI_PRODUCT_ATI_SB400_SMB: 131 case PCI_PRODUCT_ATI_SB600_SMB: /* matches SB600/SB700/SB800 */ 132 return 1; 133 } 134 break; 135 case PCI_VENDOR_SERVERWORKS: 136 switch (PCI_PRODUCT(pa->pa_id)) { 137 case PCI_PRODUCT_SERVERWORKS_OSB4: 138 case PCI_PRODUCT_SERVERWORKS_CSB5: 139 case PCI_PRODUCT_SERVERWORKS_CSB6: 140 case PCI_PRODUCT_SERVERWORKS_HT1000SB: 141 return 1; 142 } 143 } 144 145 return 0; 146 } 147 148 static void 149 piixpm_attach(device_t parent, device_t self, void *aux) 150 { 151 struct piixpm_softc *sc = device_private(self); 152 struct pci_attach_args *pa = aux; 153 struct i2cbus_attach_args iba; 154 pcireg_t base, conf; 155 pcireg_t pmmisc; 156 pci_intr_handle_t ih; 157 const char *intrstr = NULL; 158 int i, numbusses = 1; 159 char intrbuf[PCI_INTRSTR_LEN]; 160 161 sc->sc_dev = self; 162 sc->sc_iot = pa->pa_iot; 163 sc->sc_id = pa->pa_id; 164 sc->sc_pc = pa->pa_pc; 165 sc->sc_pcitag = pa->pa_tag; 166 167 pci_aprint_devinfo(pa, NULL); 168 169 if (!pmf_device_register(self, piixpm_suspend, piixpm_resume)) 170 aprint_error_dev(self, "couldn't establish power handler\n"); 171 172 /* Read configuration */ 173 conf = pci_conf_read(pa->pa_pc, pa->pa_tag, PIIX_SMB_HOSTC); 174 DPRINTF(("%s: conf 0x%x\n", device_xname(self), conf)); 175 176 if ((PCI_VENDOR(pa->pa_id) != PCI_VENDOR_INTEL) || 177 (PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_INTEL_82371AB_PMC)) 178 goto nopowermanagement; 179 180 /* check whether I/O access to PM regs is enabled */ 181 pmmisc = pci_conf_read(pa->pa_pc, pa->pa_tag, PIIX_PMREGMISC); 182 if (!(pmmisc & 1)) 183 goto nopowermanagement; 184 185 /* Map I/O space */ 186 base = pci_conf_read(pa->pa_pc, pa->pa_tag, PIIX_PM_BASE); 187 if (bus_space_map(sc->sc_pm_iot, PCI_MAPREG_IO_ADDR(base), 188 PIIX_PM_SIZE, 0, &sc->sc_pm_ioh)) { 189 aprint_error_dev(self, "can't map power management I/O space\n"); 190 goto nopowermanagement; 191 } 192 193 /* 194 * Revision 0 and 1 are PIIX4, 2 is PIIX4E, 3 is PIIX4M. 195 * PIIX4 and PIIX4E have a bug in the timer latch, see Errata #20 196 * in the "Specification update" (document #297738). 197 */ 198 acpipmtimer_attach(self, sc->sc_pm_iot, sc->sc_pm_ioh, 199 PIIX_PM_PMTMR, 200 (PCI_REVISION(pa->pa_class) < 3) ? ACPIPMT_BADLATCH : 0 ); 201 202 nopowermanagement: 203 204 /* SB800 rev 0x40+ needs special initialization */ 205 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_ATI && 206 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_ATI_SB600_SMB && 207 PCI_REVISION(pa->pa_class) >= 0x40) { 208 if (piixpm_sb800_init(sc) == 0) { 209 numbusses = 4; 210 goto attach_i2c; 211 } 212 aprint_normal_dev(self, "SMBus disabled\n"); 213 return; 214 } 215 216 if ((conf & PIIX_SMB_HOSTC_HSTEN) == 0) { 217 aprint_normal_dev(self, "SMBus disabled\n"); 218 return; 219 } 220 221 /* Map I/O space */ 222 base = pci_conf_read(pa->pa_pc, pa->pa_tag, PIIX_SMB_BASE) & 0xffff; 223 if (bus_space_map(sc->sc_smb_iot, PCI_MAPREG_IO_ADDR(base), 224 PIIX_SMB_SIZE, 0, &sc->sc_smb_ioh)) { 225 aprint_error_dev(self, "can't map smbus I/O space\n"); 226 return; 227 } 228 229 sc->sc_poll = 1; 230 aprint_normal_dev(self, ""); 231 if ((conf & PIIX_SMB_HOSTC_INTMASK) == PIIX_SMB_HOSTC_SMI) { 232 /* No PCI IRQ */ 233 aprint_normal("interrupting at SMI, "); 234 } else if ((conf & PIIX_SMB_HOSTC_INTMASK) == PIIX_SMB_HOSTC_IRQ) { 235 /* Install interrupt handler */ 236 if (pci_intr_map(pa, &ih) == 0) { 237 intrstr = pci_intr_string(pa->pa_pc, ih, intrbuf, sizeof(intrbuf)); 238 sc->sc_smb_ih = pci_intr_establish(pa->pa_pc, ih, IPL_BIO, 239 piixpm_intr, sc); 240 if (sc->sc_smb_ih != NULL) { 241 aprint_normal("interrupting at %s", intrstr); 242 sc->sc_poll = 0; 243 } 244 } 245 } 246 if (sc->sc_poll) 247 aprint_normal("polling"); 248 249 aprint_normal("\n"); 250 251 attach_i2c: 252 /* Attach I2C bus */ 253 mutex_init(&sc->sc_i2c_mutex, MUTEX_DEFAULT, IPL_NONE); 254 255 for (i = 0; i < numbusses; i++) { 256 sc->sc_busses[i].sda = i; 257 sc->sc_busses[i].softc = sc; 258 sc->sc_i2c_tags[i].ic_cookie = &sc->sc_busses[i]; 259 sc->sc_i2c_tags[i].ic_acquire_bus = piixpm_i2c_acquire_bus; 260 sc->sc_i2c_tags[i].ic_release_bus = piixpm_i2c_release_bus; 261 sc->sc_i2c_tags[i].ic_exec = piixpm_i2c_exec; 262 263 memset(&iba, 0, sizeof(iba)); 264 iba.iba_type = I2C_TYPE_SMBUS; 265 iba.iba_tag = &sc->sc_i2c_tags[i]; 266 config_found_ia(self, "i2cbus", &iba, iicbus_print); 267 } 268 } 269 270 static bool 271 piixpm_suspend(device_t dv, const pmf_qual_t *qual) 272 { 273 struct piixpm_softc *sc = device_private(dv); 274 275 sc->sc_devact[0] = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 276 PIIX_DEVACTA); 277 sc->sc_devact[1] = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 278 PIIX_DEVACTB); 279 280 return true; 281 } 282 283 static bool 284 piixpm_resume(device_t dv, const pmf_qual_t *qual) 285 { 286 struct piixpm_softc *sc = device_private(dv); 287 288 pci_conf_write(sc->sc_pc, sc->sc_pcitag, PIIX_DEVACTA, 289 sc->sc_devact[0]); 290 pci_conf_write(sc->sc_pc, sc->sc_pcitag, PIIX_DEVACTB, 291 sc->sc_devact[1]); 292 293 return true; 294 } 295 296 /* 297 * Extract SMBus base address from SB800 Power Management (PM) registers. 298 * The PM registers can be accessed either through indirect I/O (CD6/CD7) or 299 * direct mapping if AcpiMMioDecodeEn is enabled. Since this function is only 300 * called once it uses indirect I/O for simplicity. 301 */ 302 static int 303 piixpm_sb800_init(struct piixpm_softc *sc) 304 { 305 bus_space_tag_t iot = sc->sc_iot; 306 bus_space_handle_t ioh; /* indirect I/O handle */ 307 uint16_t val, base_addr; 308 309 /* Fetch SMB base address */ 310 if (bus_space_map(iot, 311 PIIXPM_INDIRECTIO_BASE, PIIXPM_INDIRECTIO_SIZE, 0, &ioh)) { 312 device_printf(sc->sc_dev, "couldn't map indirect I/O space\n"); 313 return EBUSY; 314 } 315 bus_space_write_1(iot, ioh, PIIXPM_INDIRECTIO_INDEX, 316 SB800_PM_SMBUS0EN_LO); 317 val = bus_space_read_1(iot, ioh, PIIXPM_INDIRECTIO_DATA); 318 bus_space_write_1(iot, ioh, PIIXPM_INDIRECTIO_INDEX, 319 SB800_PM_SMBUS0EN_HI); 320 val |= bus_space_read_1(iot, ioh, PIIXPM_INDIRECTIO_DATA) << 8; 321 sc->sc_sb800_ioh = ioh; 322 323 if ((val & SB800_PM_SMBUS0EN_ENABLE) == 0) 324 return ENOENT; 325 326 base_addr = val & SB800_PM_SMBUS0EN_BADDR; 327 328 aprint_debug_dev(sc->sc_dev, "SMBus @ 0x%04x\n", base_addr); 329 330 bus_space_write_1(iot, ioh, PIIXPM_INDIRECTIO_INDEX, SB800_PM_SMBUS0SELEN); 331 bus_space_write_1(iot, ioh, PIIXPM_INDIRECTIO_DATA, 1); /* SMBUS0SEL */ 332 333 if (bus_space_map(iot, PCI_MAPREG_IO_ADDR(base_addr), 334 PIIX_SMB_SIZE, 0, &sc->sc_smb_ioh)) { 335 aprint_error_dev(sc->sc_dev, "can't map smbus I/O space\n"); 336 return EBUSY; 337 } 338 aprint_normal_dev(sc->sc_dev, "polling (SB800)\n"); 339 sc->sc_poll = 1; 340 341 return 0; 342 } 343 344 static void 345 piixpm_csb5_reset(void *arg) 346 { 347 struct piixpm_softc *sc = arg; 348 pcireg_t base, hostc, pmbase; 349 350 base = pci_conf_read(sc->sc_pc, sc->sc_pcitag, PIIX_SMB_BASE); 351 hostc = pci_conf_read(sc->sc_pc, sc->sc_pcitag, PIIX_SMB_HOSTC); 352 353 pmbase = pci_conf_read(sc->sc_pc, sc->sc_pcitag, PIIX_PM_BASE); 354 pmbase |= PIIX_PM_BASE_CSB5_RESET; 355 pci_conf_write(sc->sc_pc, sc->sc_pcitag, PIIX_PM_BASE, pmbase); 356 pmbase &= ~PIIX_PM_BASE_CSB5_RESET; 357 pci_conf_write(sc->sc_pc, sc->sc_pcitag, PIIX_PM_BASE, pmbase); 358 359 pci_conf_write(sc->sc_pc, sc->sc_pcitag, PIIX_SMB_BASE, base); 360 pci_conf_write(sc->sc_pc, sc->sc_pcitag, PIIX_SMB_HOSTC, hostc); 361 362 (void) tsleep(&sc, PRIBIO, "csb5reset", hz/2); 363 } 364 365 static int 366 piixpm_i2c_acquire_bus(void *cookie, int flags) 367 { 368 struct piixpm_smbus *smbus = cookie; 369 struct piixpm_softc *sc = smbus->softc; 370 371 if (!cold) 372 mutex_enter(&sc->sc_i2c_mutex); 373 374 if (smbus->sda > 0) /* SB800 */ 375 { 376 bus_space_write_1(sc->sc_iot, sc->sc_sb800_ioh, 377 PIIXPM_INDIRECTIO_INDEX, SB800_PM_SMBUS0SEL); 378 bus_space_write_1(sc->sc_iot, sc->sc_sb800_ioh, 379 PIIXPM_INDIRECTIO_DATA, smbus->sda << 1); 380 } 381 382 return 0; 383 } 384 385 static void 386 piixpm_i2c_release_bus(void *cookie, int flags) 387 { 388 struct piixpm_smbus *smbus = cookie; 389 struct piixpm_softc *sc = smbus->softc; 390 391 if (smbus->sda > 0) /* SB800 */ 392 { 393 /* 394 * HP Microserver hangs after reboot if not set to SDA0. 395 * Also add shutdown hook? 396 */ 397 bus_space_write_1(sc->sc_iot, sc->sc_sb800_ioh, 398 PIIXPM_INDIRECTIO_INDEX, SB800_PM_SMBUS0SEL); 399 bus_space_write_1(sc->sc_iot, sc->sc_sb800_ioh, 400 PIIXPM_INDIRECTIO_DATA, 0); 401 } 402 403 if (!cold) 404 mutex_exit(&sc->sc_i2c_mutex); 405 } 406 407 static int 408 piixpm_i2c_exec(void *cookie, i2c_op_t op, i2c_addr_t addr, 409 const void *cmdbuf, size_t cmdlen, void *buf, size_t len, int flags) 410 { 411 struct piixpm_smbus *smbus = cookie; 412 struct piixpm_softc *sc = smbus->softc; 413 const u_int8_t *b; 414 u_int8_t ctl = 0, st; 415 int retries; 416 417 DPRINTF(("%s: exec: op %d, addr 0x%x, cmdlen %zu, len %zu, flags 0x%x\n", 418 device_xname(sc->sc_dev), op, addr, cmdlen, len, flags)); 419 420 /* Clear status bits */ 421 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_HS, 422 PIIX_SMB_HS_INTR | PIIX_SMB_HS_DEVERR | 423 PIIX_SMB_HS_BUSERR | PIIX_SMB_HS_FAILED); 424 bus_space_barrier(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_HS, 1, 425 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 426 427 /* Wait for bus to be idle */ 428 for (retries = 100; retries > 0; retries--) { 429 st = bus_space_read_1(sc->sc_smb_iot, sc->sc_smb_ioh, 430 PIIX_SMB_HS); 431 if (!(st & PIIX_SMB_HS_BUSY)) 432 break; 433 DELAY(PIIXPM_DELAY); 434 } 435 DPRINTF(("%s: exec: st 0x%d\n", device_xname(sc->sc_dev), st & 0xff)); 436 if (st & PIIX_SMB_HS_BUSY) 437 return (1); 438 439 if (cold || sc->sc_poll) 440 flags |= I2C_F_POLL; 441 442 if (!I2C_OP_STOP_P(op) || cmdlen > 1 || len > 2 || 443 (cmdlen == 0 && len > 1)) 444 return (1); 445 446 /* Setup transfer */ 447 sc->sc_i2c_xfer.op = op; 448 sc->sc_i2c_xfer.buf = buf; 449 sc->sc_i2c_xfer.len = len; 450 sc->sc_i2c_xfer.flags = flags; 451 sc->sc_i2c_xfer.error = 0; 452 453 /* Set slave address and transfer direction */ 454 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_TXSLVA, 455 PIIX_SMB_TXSLVA_ADDR(addr) | 456 (I2C_OP_READ_P(op) ? PIIX_SMB_TXSLVA_READ : 0)); 457 458 b = cmdbuf; 459 if (cmdlen > 0) 460 /* Set command byte */ 461 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, 462 PIIX_SMB_HCMD, b[0]); 463 464 if (I2C_OP_WRITE_P(op)) { 465 /* Write data */ 466 b = buf; 467 if (cmdlen == 0 && len == 1) 468 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, 469 PIIX_SMB_HCMD, b[0]); 470 else if (len > 0) 471 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, 472 PIIX_SMB_HD0, b[0]); 473 if (len > 1) 474 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, 475 PIIX_SMB_HD1, b[1]); 476 } 477 478 /* Set SMBus command */ 479 if (cmdlen == 0) { 480 if (len == 0) 481 ctl = PIIX_SMB_HC_CMD_QUICK; 482 else 483 ctl = PIIX_SMB_HC_CMD_BYTE; 484 } else if (len == 1) 485 ctl = PIIX_SMB_HC_CMD_BDATA; 486 else if (len == 2) 487 ctl = PIIX_SMB_HC_CMD_WDATA; 488 489 if ((flags & I2C_F_POLL) == 0) 490 ctl |= PIIX_SMB_HC_INTREN; 491 492 /* Start transaction */ 493 ctl |= PIIX_SMB_HC_START; 494 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_HC, ctl); 495 496 if (flags & I2C_F_POLL) { 497 /* Poll for completion */ 498 if (PIIXPM_IS_CSB5(sc->sc_id)) 499 DELAY(2*PIIXPM_DELAY); 500 else 501 DELAY(PIIXPM_DELAY); 502 for (retries = 1000; retries > 0; retries--) { 503 st = bus_space_read_1(sc->sc_smb_iot, sc->sc_smb_ioh, 504 PIIX_SMB_HS); 505 if ((st & PIIX_SMB_HS_BUSY) == 0) 506 break; 507 DELAY(PIIXPM_DELAY); 508 } 509 if (st & PIIX_SMB_HS_BUSY) 510 goto timeout; 511 piixpm_intr(smbus); 512 } else { 513 /* Wait for interrupt */ 514 if (tsleep(sc, PRIBIO, "iicexec", PIIXPM_TIMEOUT * hz)) 515 goto timeout; 516 } 517 518 if (sc->sc_i2c_xfer.error) 519 return (1); 520 521 return (0); 522 523 timeout: 524 /* 525 * Transfer timeout. Kill the transaction and clear status bits. 526 */ 527 aprint_error_dev(sc->sc_dev, "timeout, status 0x%x\n", st); 528 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_HC, 529 PIIX_SMB_HC_KILL); 530 DELAY(PIIXPM_DELAY); 531 st = bus_space_read_1(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_HS); 532 if ((st & PIIX_SMB_HS_FAILED) == 0) 533 aprint_error_dev(sc->sc_dev, "transaction abort failed, status 0x%x\n", st); 534 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_HS, st); 535 /* 536 * CSB5 needs hard reset to unlock the smbus after timeout. 537 */ 538 if (PIIXPM_IS_CSB5(sc->sc_id)) 539 piixpm_csb5_reset(sc); 540 return (1); 541 } 542 543 static int 544 piixpm_intr(void *arg) 545 { 546 struct piixpm_smbus *smbus = arg; 547 struct piixpm_softc *sc = smbus->softc; 548 u_int8_t st; 549 u_int8_t *b; 550 size_t len; 551 552 /* Read status */ 553 st = bus_space_read_1(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_HS); 554 if ((st & PIIX_SMB_HS_BUSY) != 0 || (st & (PIIX_SMB_HS_INTR | 555 PIIX_SMB_HS_DEVERR | PIIX_SMB_HS_BUSERR | 556 PIIX_SMB_HS_FAILED)) == 0) 557 /* Interrupt was not for us */ 558 return (0); 559 560 DPRINTF(("%s: intr st 0x%d\n", device_xname(sc->sc_dev), st & 0xff)); 561 562 /* Clear status bits */ 563 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_HS, st); 564 565 /* Check for errors */ 566 if (st & (PIIX_SMB_HS_DEVERR | PIIX_SMB_HS_BUSERR | 567 PIIX_SMB_HS_FAILED)) { 568 sc->sc_i2c_xfer.error = 1; 569 goto done; 570 } 571 572 if (st & PIIX_SMB_HS_INTR) { 573 if (I2C_OP_WRITE_P(sc->sc_i2c_xfer.op)) 574 goto done; 575 576 /* Read data */ 577 b = sc->sc_i2c_xfer.buf; 578 len = sc->sc_i2c_xfer.len; 579 if (len > 0) 580 b[0] = bus_space_read_1(sc->sc_smb_iot, sc->sc_smb_ioh, 581 PIIX_SMB_HD0); 582 if (len > 1) 583 b[1] = bus_space_read_1(sc->sc_smb_iot, sc->sc_smb_ioh, 584 PIIX_SMB_HD1); 585 } 586 587 done: 588 if ((sc->sc_i2c_xfer.flags & I2C_F_POLL) == 0) 589 wakeup(sc); 590 return (1); 591 } 592
Indexes created Mon Sep 29 21:09:56 GMT 2025