piixpm.c revision 1.47
1 /* $NetBSD: piixpm.c,v 1.47 2015/12/10 05:29:41 pgoyette Exp $ */ 2 /* $OpenBSD: piixpm.c,v 1.20 2006/02/27 08:25:02 grange Exp $ */ 3 4 /* 5 * Copyright (c) 2005, 2006 Alexander Yurchenko <grange (at) openbsd.org> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 /* 21 * Intel PIIX and compatible Power Management controller driver. 22 */ 23 24 #include <sys/cdefs.h> 25 __KERNEL_RCSID(0, "$NetBSD: piixpm.c,v 1.47 2015/12/10 05:29:41 pgoyette Exp $"); 26 27 #include <sys/param.h> 28 #include <sys/systm.h> 29 #include <sys/device.h> 30 #include <sys/kernel.h> 31 #include <sys/mutex.h> 32 #include <sys/proc.h> 33 34 #include <sys/bus.h> 35 36 #include <dev/pci/pcidevs.h> 37 #include <dev/pci/pcireg.h> 38 #include <dev/pci/pcivar.h> 39 40 #include <dev/pci/piixpmreg.h> 41 42 #include <dev/i2c/i2cvar.h> 43 44 #include <dev/ic/acpipmtimer.h> 45 46 #ifdef PIIXPM_DEBUG 47 #define DPRINTF(x) printf x 48 #else 49 #define DPRINTF(x) 50 #endif 51 52 #define PIIXPM_IS_CSB5(id) \ 53 (PCI_VENDOR((id)) == PCI_VENDOR_SERVERWORKS && \ 54 PCI_PRODUCT((id)) == PCI_PRODUCT_SERVERWORKS_CSB5) 55 #define PIIXPM_DELAY 200 56 #define PIIXPM_TIMEOUT 1 57 58 struct piixpm_smbus { 59 int sda; 60 struct piixpm_softc *softc; 61 }; 62 63 struct piixpm_softc { 64 device_t sc_dev; 65 66 bus_space_tag_t sc_iot; 67 #define sc_pm_iot sc_iot 68 #define sc_smb_iot sc_iot 69 bus_space_handle_t sc_pm_ioh; 70 bus_space_handle_t sc_sb800_ioh; 71 bus_space_handle_t sc_smb_ioh; 72 void * sc_smb_ih; 73 int sc_poll; 74 75 pci_chipset_tag_t sc_pc; 76 pcitag_t sc_pcitag; 77 pcireg_t sc_id; 78 79 int sc_numbusses; 80 device_t sc_i2c_device[4]; 81 struct piixpm_smbus sc_busses[4]; 82 struct i2c_controller sc_i2c_tags[4]; 83 84 kmutex_t sc_i2c_mutex; 85 struct { 86 i2c_op_t op; 87 void * buf; 88 size_t len; 89 int flags; 90 volatile int error; 91 } sc_i2c_xfer; 92 93 pcireg_t sc_devact[2]; 94 }; 95 96 static int piixpm_match(device_t, cfdata_t, void *); 97 static void piixpm_attach(device_t, device_t, void *); 98 static int piixpm_rescan(device_t, const char *, const int *); 99 static void piixpm_chdet(device_t, device_t); 100 101 static bool piixpm_suspend(device_t, const pmf_qual_t *); 102 static bool piixpm_resume(device_t, const pmf_qual_t *); 103 104 static int piixpm_sb800_init(struct piixpm_softc *); 105 static void piixpm_csb5_reset(void *); 106 static int piixpm_i2c_acquire_bus(void *, int); 107 static void piixpm_i2c_release_bus(void *, int); 108 static int piixpm_i2c_exec(void *, i2c_op_t, i2c_addr_t, const void *, 109 size_t, void *, size_t, int); 110 111 static int piixpm_intr(void *); 112 113 CFATTACH_DECL3_NEW(piixpm, sizeof(struct piixpm_softc), 114 piixpm_match, piixpm_attach, NULL, NULL, piixpm_rescan, piixpm_chdet, 0); 115 116 static int 117 piixpm_match(device_t parent, cfdata_t match, void *aux) 118 { 119 struct pci_attach_args *pa; 120 121 pa = (struct pci_attach_args *)aux; 122 switch (PCI_VENDOR(pa->pa_id)) { 123 case PCI_VENDOR_INTEL: 124 switch (PCI_PRODUCT(pa->pa_id)) { 125 case PCI_PRODUCT_INTEL_82371AB_PMC: 126 case PCI_PRODUCT_INTEL_82440MX_PMC: 127 return 1; 128 } 129 break; 130 case PCI_VENDOR_ATI: 131 switch (PCI_PRODUCT(pa->pa_id)) { 132 case PCI_PRODUCT_ATI_SB200_SMB: 133 case PCI_PRODUCT_ATI_SB300_SMB: 134 case PCI_PRODUCT_ATI_SB400_SMB: 135 case PCI_PRODUCT_ATI_SB600_SMB: /* matches SB600/SB700/SB800 */ 136 return 1; 137 } 138 break; 139 case PCI_VENDOR_SERVERWORKS: 140 switch (PCI_PRODUCT(pa->pa_id)) { 141 case PCI_PRODUCT_SERVERWORKS_OSB4: 142 case PCI_PRODUCT_SERVERWORKS_CSB5: 143 case PCI_PRODUCT_SERVERWORKS_CSB6: 144 case PCI_PRODUCT_SERVERWORKS_HT1000SB: 145 return 1; 146 } 147 } 148 149 return 0; 150 } 151 152 static void 153 piixpm_attach(device_t parent, device_t self, void *aux) 154 { 155 struct piixpm_softc *sc = device_private(self); 156 struct pci_attach_args *pa = aux; 157 pcireg_t base, conf; 158 pcireg_t pmmisc; 159 pci_intr_handle_t ih; 160 const char *intrstr = NULL; 161 int i, flags; 162 char intrbuf[PCI_INTRSTR_LEN]; 163 164 sc->sc_dev = self; 165 sc->sc_iot = pa->pa_iot; 166 sc->sc_id = pa->pa_id; 167 sc->sc_pc = pa->pa_pc; 168 sc->sc_pcitag = pa->pa_tag; 169 sc->sc_numbusses = 1; 170 171 pci_aprint_devinfo(pa, NULL); 172 173 if (!pmf_device_register(self, piixpm_suspend, piixpm_resume)) 174 aprint_error_dev(self, "couldn't establish power handler\n"); 175 176 /* Read configuration */ 177 conf = pci_conf_read(pa->pa_pc, pa->pa_tag, PIIX_SMB_HOSTC); 178 DPRINTF(("%s: conf 0x%x\n", device_xname(self), conf)); 179 180 if ((PCI_VENDOR(pa->pa_id) != PCI_VENDOR_INTEL) || 181 (PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_INTEL_82371AB_PMC)) 182 goto nopowermanagement; 183 184 /* check whether I/O access to PM regs is enabled */ 185 pmmisc = pci_conf_read(pa->pa_pc, pa->pa_tag, PIIX_PMREGMISC); 186 if (!(pmmisc & 1)) 187 goto nopowermanagement; 188 189 /* Map I/O space */ 190 base = pci_conf_read(pa->pa_pc, pa->pa_tag, PIIX_PM_BASE); 191 if (bus_space_map(sc->sc_pm_iot, PCI_MAPREG_IO_ADDR(base), 192 PIIX_PM_SIZE, 0, &sc->sc_pm_ioh)) { 193 aprint_error_dev(self, "can't map power management I/O space\n"); 194 goto nopowermanagement; 195 } 196 197 /* 198 * Revision 0 and 1 are PIIX4, 2 is PIIX4E, 3 is PIIX4M. 199 * PIIX4 and PIIX4E have a bug in the timer latch, see Errata #20 200 * in the "Specification update" (document #297738). 201 */ 202 acpipmtimer_attach(self, sc->sc_pm_iot, sc->sc_pm_ioh, 203 PIIX_PM_PMTMR, 204 (PCI_REVISION(pa->pa_class) < 3) ? ACPIPMT_BADLATCH : 0 ); 205 206 nopowermanagement: 207 208 /* SB800 rev 0x40+ needs special initialization */ 209 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_ATI && 210 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_ATI_SB600_SMB && 211 PCI_REVISION(pa->pa_class) >= 0x40) { 212 if (piixpm_sb800_init(sc) == 0) { 213 sc->sc_numbusses = 4; 214 goto attach_i2c; 215 } 216 aprint_normal_dev(self, "SMBus disabled\n"); 217 return; 218 } 219 220 if ((conf & PIIX_SMB_HOSTC_HSTEN) == 0) { 221 aprint_normal_dev(self, "SMBus disabled\n"); 222 return; 223 } 224 225 /* Map I/O space */ 226 base = pci_conf_read(pa->pa_pc, pa->pa_tag, PIIX_SMB_BASE) & 0xffff; 227 if (bus_space_map(sc->sc_smb_iot, PCI_MAPREG_IO_ADDR(base), 228 PIIX_SMB_SIZE, 0, &sc->sc_smb_ioh)) { 229 aprint_error_dev(self, "can't map smbus I/O space\n"); 230 return; 231 } 232 233 sc->sc_poll = 1; 234 aprint_normal_dev(self, ""); 235 if ((conf & PIIX_SMB_HOSTC_INTMASK) == PIIX_SMB_HOSTC_SMI) { 236 /* No PCI IRQ */ 237 aprint_normal("interrupting at SMI, "); 238 } else if ((conf & PIIX_SMB_HOSTC_INTMASK) == PIIX_SMB_HOSTC_IRQ) { 239 /* Install interrupt handler */ 240 if (pci_intr_map(pa, &ih) == 0) { 241 intrstr = pci_intr_string(pa->pa_pc, ih, intrbuf, sizeof(intrbuf)); 242 sc->sc_smb_ih = pci_intr_establish(pa->pa_pc, ih, IPL_BIO, 243 piixpm_intr, sc); 244 if (sc->sc_smb_ih != NULL) { 245 aprint_normal("interrupting at %s", intrstr); 246 sc->sc_poll = 0; 247 } 248 } 249 } 250 if (sc->sc_poll) 251 aprint_normal("polling"); 252 253 aprint_normal("\n"); 254 255 attach_i2c: 256 for (i = 0; i < sc->sc_numbusses; i++) 257 sc->sc_i2c_device[i] = NULL; 258 259 flags = 0; 260 mutex_init(&sc->sc_i2c_mutex, MUTEX_DEFAULT, IPL_NONE); 261 piixpm_rescan(self, "i2cbus", &flags); 262 } 263 264 static int 265 piixpm_rescan(device_t self, const char *ifattr, const int *flags) 266 { 267 struct piixpm_softc *sc = device_private(self); 268 struct i2cbus_attach_args iba; 269 int i; 270 271 if (!ifattr_match(ifattr, "i2cbus")) 272 return 0; 273 274 /* Attach I2C bus */ 275 276 for (i = 0; i < sc->sc_numbusses; i++) { 277 if (sc->sc_i2c_device[i]) 278 continue; 279 sc->sc_busses[i].sda = i; 280 sc->sc_busses[i].softc = sc; 281 sc->sc_i2c_tags[i].ic_cookie = &sc->sc_busses[i]; 282 sc->sc_i2c_tags[i].ic_acquire_bus = piixpm_i2c_acquire_bus; 283 sc->sc_i2c_tags[i].ic_release_bus = piixpm_i2c_release_bus; 284 sc->sc_i2c_tags[i].ic_exec = piixpm_i2c_exec; 285 memset(&iba, 0, sizeof(iba)); 286 iba.iba_type = I2C_TYPE_SMBUS; 287 iba.iba_tag = &sc->sc_i2c_tags[i]; 288 sc->sc_i2c_device[i] = config_found_ia(self, ifattr, &iba, 289 iicbus_print); 290 } 291 292 return 0; 293 } 294 295 static void 296 piixpm_chdet(device_t self, device_t child) 297 { 298 struct piixpm_softc *sc = device_private(self); 299 int i; 300 301 for (i = 0; i < sc->sc_numbusses; i++) { 302 if (sc->sc_i2c_device[i] == child) { 303 sc->sc_i2c_device[i] = NULL; 304 break; 305 } 306 } 307 } 308 309 310 static bool 311 piixpm_suspend(device_t dv, const pmf_qual_t *qual) 312 { 313 struct piixpm_softc *sc = device_private(dv); 314 315 sc->sc_devact[0] = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 316 PIIX_DEVACTA); 317 sc->sc_devact[1] = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 318 PIIX_DEVACTB); 319 320 return true; 321 } 322 323 static bool 324 piixpm_resume(device_t dv, const pmf_qual_t *qual) 325 { 326 struct piixpm_softc *sc = device_private(dv); 327 328 pci_conf_write(sc->sc_pc, sc->sc_pcitag, PIIX_DEVACTA, 329 sc->sc_devact[0]); 330 pci_conf_write(sc->sc_pc, sc->sc_pcitag, PIIX_DEVACTB, 331 sc->sc_devact[1]); 332 333 return true; 334 } 335 336 /* 337 * Extract SMBus base address from SB800 Power Management (PM) registers. 338 * The PM registers can be accessed either through indirect I/O (CD6/CD7) or 339 * direct mapping if AcpiMMioDecodeEn is enabled. Since this function is only 340 * called once it uses indirect I/O for simplicity. 341 */ 342 static int 343 piixpm_sb800_init(struct piixpm_softc *sc) 344 { 345 bus_space_tag_t iot = sc->sc_iot; 346 bus_space_handle_t ioh; /* indirect I/O handle */ 347 uint16_t val, base_addr; 348 349 /* Fetch SMB base address */ 350 if (bus_space_map(iot, 351 PIIXPM_INDIRECTIO_BASE, PIIXPM_INDIRECTIO_SIZE, 0, &ioh)) { 352 device_printf(sc->sc_dev, "couldn't map indirect I/O space\n"); 353 return EBUSY; 354 } 355 bus_space_write_1(iot, ioh, PIIXPM_INDIRECTIO_INDEX, 356 SB800_PM_SMBUS0EN_LO); 357 val = bus_space_read_1(iot, ioh, PIIXPM_INDIRECTIO_DATA); 358 bus_space_write_1(iot, ioh, PIIXPM_INDIRECTIO_INDEX, 359 SB800_PM_SMBUS0EN_HI); 360 val |= bus_space_read_1(iot, ioh, PIIXPM_INDIRECTIO_DATA) << 8; 361 sc->sc_sb800_ioh = ioh; 362 363 if ((val & SB800_PM_SMBUS0EN_ENABLE) == 0) 364 return ENOENT; 365 366 base_addr = val & SB800_PM_SMBUS0EN_BADDR; 367 368 aprint_debug_dev(sc->sc_dev, "SMBus @ 0x%04x\n", base_addr); 369 370 bus_space_write_1(iot, ioh, PIIXPM_INDIRECTIO_INDEX, SB800_PM_SMBUS0SELEN); 371 bus_space_write_1(iot, ioh, PIIXPM_INDIRECTIO_DATA, 1); /* SMBUS0SEL */ 372 373 if (bus_space_map(iot, PCI_MAPREG_IO_ADDR(base_addr), 374 PIIX_SMB_SIZE, 0, &sc->sc_smb_ioh)) { 375 aprint_error_dev(sc->sc_dev, "can't map smbus I/O space\n"); 376 return EBUSY; 377 } 378 aprint_normal_dev(sc->sc_dev, "polling (SB800)\n"); 379 sc->sc_poll = 1; 380 381 return 0; 382 } 383 384 static void 385 piixpm_csb5_reset(void *arg) 386 { 387 struct piixpm_softc *sc = arg; 388 pcireg_t base, hostc, pmbase; 389 390 base = pci_conf_read(sc->sc_pc, sc->sc_pcitag, PIIX_SMB_BASE); 391 hostc = pci_conf_read(sc->sc_pc, sc->sc_pcitag, PIIX_SMB_HOSTC); 392 393 pmbase = pci_conf_read(sc->sc_pc, sc->sc_pcitag, PIIX_PM_BASE); 394 pmbase |= PIIX_PM_BASE_CSB5_RESET; 395 pci_conf_write(sc->sc_pc, sc->sc_pcitag, PIIX_PM_BASE, pmbase); 396 pmbase &= ~PIIX_PM_BASE_CSB5_RESET; 397 pci_conf_write(sc->sc_pc, sc->sc_pcitag, PIIX_PM_BASE, pmbase); 398 399 pci_conf_write(sc->sc_pc, sc->sc_pcitag, PIIX_SMB_BASE, base); 400 pci_conf_write(sc->sc_pc, sc->sc_pcitag, PIIX_SMB_HOSTC, hostc); 401 402 (void) tsleep(&sc, PRIBIO, "csb5reset", hz/2); 403 } 404 405 static int 406 piixpm_i2c_acquire_bus(void *cookie, int flags) 407 { 408 struct piixpm_smbus *smbus = cookie; 409 struct piixpm_softc *sc = smbus->softc; 410 411 if (!cold) 412 mutex_enter(&sc->sc_i2c_mutex); 413 414 if (smbus->sda > 0) /* SB800 */ 415 { 416 bus_space_write_1(sc->sc_iot, sc->sc_sb800_ioh, 417 PIIXPM_INDIRECTIO_INDEX, SB800_PM_SMBUS0SEL); 418 bus_space_write_1(sc->sc_iot, sc->sc_sb800_ioh, 419 PIIXPM_INDIRECTIO_DATA, smbus->sda << 1); 420 } 421 422 return 0; 423 } 424 425 static void 426 piixpm_i2c_release_bus(void *cookie, int flags) 427 { 428 struct piixpm_smbus *smbus = cookie; 429 struct piixpm_softc *sc = smbus->softc; 430 431 if (smbus->sda > 0) /* SB800 */ 432 { 433 /* 434 * HP Microserver hangs after reboot if not set to SDA0. 435 * Also add shutdown hook? 436 */ 437 bus_space_write_1(sc->sc_iot, sc->sc_sb800_ioh, 438 PIIXPM_INDIRECTIO_INDEX, SB800_PM_SMBUS0SEL); 439 bus_space_write_1(sc->sc_iot, sc->sc_sb800_ioh, 440 PIIXPM_INDIRECTIO_DATA, 0); 441 } 442 443 if (!cold) 444 mutex_exit(&sc->sc_i2c_mutex); 445 } 446 447 static int 448 piixpm_i2c_exec(void *cookie, i2c_op_t op, i2c_addr_t addr, 449 const void *cmdbuf, size_t cmdlen, void *buf, size_t len, int flags) 450 { 451 struct piixpm_smbus *smbus = cookie; 452 struct piixpm_softc *sc = smbus->softc; 453 const u_int8_t *b; 454 u_int8_t ctl = 0, st; 455 int retries; 456 457 DPRINTF(("%s: exec: op %d, addr 0x%x, cmdlen %zu, len %zu, flags 0x%x\n", 458 device_xname(sc->sc_dev), op, addr, cmdlen, len, flags)); 459 460 /* Clear status bits */ 461 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_HS, 462 PIIX_SMB_HS_INTR | PIIX_SMB_HS_DEVERR | 463 PIIX_SMB_HS_BUSERR | PIIX_SMB_HS_FAILED); 464 bus_space_barrier(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_HS, 1, 465 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 466 467 /* Wait for bus to be idle */ 468 for (retries = 100; retries > 0; retries--) { 469 st = bus_space_read_1(sc->sc_smb_iot, sc->sc_smb_ioh, 470 PIIX_SMB_HS); 471 if (!(st & PIIX_SMB_HS_BUSY)) 472 break; 473 DELAY(PIIXPM_DELAY); 474 } 475 DPRINTF(("%s: exec: st 0x%d\n", device_xname(sc->sc_dev), st & 0xff)); 476 if (st & PIIX_SMB_HS_BUSY) 477 return (1); 478 479 if (cold || sc->sc_poll) 480 flags |= I2C_F_POLL; 481 482 if (!I2C_OP_STOP_P(op) || cmdlen > 1 || len > 2 || 483 (cmdlen == 0 && len > 1)) 484 return (1); 485 486 /* Setup transfer */ 487 sc->sc_i2c_xfer.op = op; 488 sc->sc_i2c_xfer.buf = buf; 489 sc->sc_i2c_xfer.len = len; 490 sc->sc_i2c_xfer.flags = flags; 491 sc->sc_i2c_xfer.error = 0; 492 493 /* Set slave address and transfer direction */ 494 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_TXSLVA, 495 PIIX_SMB_TXSLVA_ADDR(addr) | 496 (I2C_OP_READ_P(op) ? PIIX_SMB_TXSLVA_READ : 0)); 497 498 b = cmdbuf; 499 if (cmdlen > 0) 500 /* Set command byte */ 501 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, 502 PIIX_SMB_HCMD, b[0]); 503 504 if (I2C_OP_WRITE_P(op)) { 505 /* Write data */ 506 b = buf; 507 if (cmdlen == 0 && len == 1) 508 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, 509 PIIX_SMB_HCMD, b[0]); 510 else if (len > 0) 511 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, 512 PIIX_SMB_HD0, b[0]); 513 if (len > 1) 514 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, 515 PIIX_SMB_HD1, b[1]); 516 } 517 518 /* Set SMBus command */ 519 if (cmdlen == 0) { 520 if (len == 0) 521 ctl = PIIX_SMB_HC_CMD_QUICK; 522 else 523 ctl = PIIX_SMB_HC_CMD_BYTE; 524 } else if (len == 1) 525 ctl = PIIX_SMB_HC_CMD_BDATA; 526 else if (len == 2) 527 ctl = PIIX_SMB_HC_CMD_WDATA; 528 529 if ((flags & I2C_F_POLL) == 0) 530 ctl |= PIIX_SMB_HC_INTREN; 531 532 /* Start transaction */ 533 ctl |= PIIX_SMB_HC_START; 534 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_HC, ctl); 535 536 if (flags & I2C_F_POLL) { 537 /* Poll for completion */ 538 if (PIIXPM_IS_CSB5(sc->sc_id)) 539 DELAY(2*PIIXPM_DELAY); 540 else 541 DELAY(PIIXPM_DELAY); 542 for (retries = 1000; retries > 0; retries--) { 543 st = bus_space_read_1(sc->sc_smb_iot, sc->sc_smb_ioh, 544 PIIX_SMB_HS); 545 if ((st & PIIX_SMB_HS_BUSY) == 0) 546 break; 547 DELAY(PIIXPM_DELAY); 548 } 549 if (st & PIIX_SMB_HS_BUSY) 550 goto timeout; 551 piixpm_intr(sc); 552 } else { 553 /* Wait for interrupt */ 554 if (tsleep(sc, PRIBIO, "iicexec", PIIXPM_TIMEOUT * hz)) 555 goto timeout; 556 } 557 558 if (sc->sc_i2c_xfer.error) 559 return (1); 560 561 return (0); 562 563 timeout: 564 /* 565 * Transfer timeout. Kill the transaction and clear status bits. 566 */ 567 aprint_error_dev(sc->sc_dev, "timeout, status 0x%x\n", st); 568 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_HC, 569 PIIX_SMB_HC_KILL); 570 DELAY(PIIXPM_DELAY); 571 st = bus_space_read_1(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_HS); 572 if ((st & PIIX_SMB_HS_FAILED) == 0) 573 aprint_error_dev(sc->sc_dev, "transaction abort failed, status 0x%x\n", st); 574 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_HS, st); 575 /* 576 * CSB5 needs hard reset to unlock the smbus after timeout. 577 */ 578 if (PIIXPM_IS_CSB5(sc->sc_id)) 579 piixpm_csb5_reset(sc); 580 return (1); 581 } 582 583 static int 584 piixpm_intr(void *arg) 585 { 586 struct piixpm_softc *sc = arg; 587 u_int8_t st; 588 u_int8_t *b; 589 size_t len; 590 591 /* Read status */ 592 st = bus_space_read_1(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_HS); 593 if ((st & PIIX_SMB_HS_BUSY) != 0 || (st & (PIIX_SMB_HS_INTR | 594 PIIX_SMB_HS_DEVERR | PIIX_SMB_HS_BUSERR | 595 PIIX_SMB_HS_FAILED)) == 0) 596 /* Interrupt was not for us */ 597 return (0); 598 599 DPRINTF(("%s: intr st 0x%d\n", device_xname(sc->sc_dev), st & 0xff)); 600 601 /* Clear status bits */ 602 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_HS, st); 603 604 /* Check for errors */ 605 if (st & (PIIX_SMB_HS_DEVERR | PIIX_SMB_HS_BUSERR | 606 PIIX_SMB_HS_FAILED)) { 607 sc->sc_i2c_xfer.error = 1; 608 goto done; 609 } 610 611 if (st & PIIX_SMB_HS_INTR) { 612 if (I2C_OP_WRITE_P(sc->sc_i2c_xfer.op)) 613 goto done; 614 615 /* Read data */ 616 b = sc->sc_i2c_xfer.buf; 617 len = sc->sc_i2c_xfer.len; 618 if (len > 0) 619 b[0] = bus_space_read_1(sc->sc_smb_iot, sc->sc_smb_ioh, 620 PIIX_SMB_HD0); 621 if (len > 1) 622 b[1] = bus_space_read_1(sc->sc_smb_iot, sc->sc_smb_ioh, 623 PIIX_SMB_HD1); 624 } 625 626 done: 627 if ((sc->sc_i2c_xfer.flags & I2C_F_POLL) == 0) 628 wakeup(sc); 629 return (1); 630 } 631
Indexes created Mon Sep 29 03:10:08 GMT 2025