piixpm.c revision 1.48
1 /* $NetBSD: piixpm.c,v 1.48 2016/07/10 04:44:47 pgoyette Exp $ */ 2 /* $OpenBSD: piixpm.c,v 1.20 2006/02/27 08:25:02 grange Exp $ */ 3 4 /* 5 * Copyright (c) 2005, 2006 Alexander Yurchenko <grange (at) openbsd.org> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 /* 21 * Intel PIIX and compatible Power Management controller driver. 22 */ 23 24 #include <sys/cdefs.h> 25 __KERNEL_RCSID(0, "$NetBSD: piixpm.c,v 1.48 2016/07/10 04:44:47 pgoyette Exp $"); 26 27 #include <sys/param.h> 28 #include <sys/systm.h> 29 #include <sys/device.h> 30 #include <sys/kernel.h> 31 #include <sys/mutex.h> 32 #include <sys/proc.h> 33 34 #include <sys/bus.h> 35 36 #include <dev/pci/pcidevs.h> 37 #include <dev/pci/pcireg.h> 38 #include <dev/pci/pcivar.h> 39 40 #include <dev/pci/piixpmreg.h> 41 42 #include <dev/i2c/i2cvar.h> 43 44 #include <dev/ic/acpipmtimer.h> 45 46 #ifdef PIIXPM_DEBUG 47 #define DPRINTF(x) printf x 48 #else 49 #define DPRINTF(x) 50 #endif 51 52 #define PIIXPM_IS_CSB5(id) \ 53 (PCI_VENDOR((id)) == PCI_VENDOR_SERVERWORKS && \ 54 PCI_PRODUCT((id)) == PCI_PRODUCT_SERVERWORKS_CSB5) 55 #define PIIXPM_DELAY 200 56 #define PIIXPM_TIMEOUT 1 57 58 struct piixpm_smbus { 59 int sda; 60 struct piixpm_softc *softc; 61 }; 62 63 struct piixpm_softc { 64 device_t sc_dev; 65 66 bus_space_tag_t sc_iot; 67 #define sc_pm_iot sc_iot 68 #define sc_smb_iot sc_iot 69 bus_space_handle_t sc_pm_ioh; 70 bus_space_handle_t sc_sb800_ioh; 71 bus_space_handle_t sc_smb_ioh; 72 void * sc_smb_ih; 73 int sc_poll; 74 75 pci_chipset_tag_t sc_pc; 76 pcitag_t sc_pcitag; 77 pcireg_t sc_id; 78 79 int sc_numbusses; 80 device_t sc_i2c_device[4]; 81 struct piixpm_smbus sc_busses[4]; 82 struct i2c_controller sc_i2c_tags[4]; 83 84 kmutex_t sc_i2c_mutex; 85 struct { 86 i2c_op_t op; 87 void * buf; 88 size_t len; 89 int flags; 90 volatile int error; 91 } sc_i2c_xfer; 92 93 pcireg_t sc_devact[2]; 94 }; 95 96 static int piixpm_match(device_t, cfdata_t, void *); 97 static void piixpm_attach(device_t, device_t, void *); 98 static int piixpm_rescan(device_t, const char *, const int *); 99 static void piixpm_chdet(device_t, device_t); 100 101 static bool piixpm_suspend(device_t, const pmf_qual_t *); 102 static bool piixpm_resume(device_t, const pmf_qual_t *); 103 104 static int piixpm_sb800_init(struct piixpm_softc *); 105 static void piixpm_csb5_reset(void *); 106 static int piixpm_i2c_acquire_bus(void *, int); 107 static void piixpm_i2c_release_bus(void *, int); 108 static int piixpm_i2c_exec(void *, i2c_op_t, i2c_addr_t, const void *, 109 size_t, void *, size_t, int); 110 111 static int piixpm_intr(void *); 112 113 CFATTACH_DECL3_NEW(piixpm, sizeof(struct piixpm_softc), 114 piixpm_match, piixpm_attach, NULL, NULL, piixpm_rescan, piixpm_chdet, 0); 115 116 static int 117 piixpm_match(device_t parent, cfdata_t match, void *aux) 118 { 119 struct pci_attach_args *pa; 120 121 pa = (struct pci_attach_args *)aux; 122 switch (PCI_VENDOR(pa->pa_id)) { 123 case PCI_VENDOR_INTEL: 124 switch (PCI_PRODUCT(pa->pa_id)) { 125 case PCI_PRODUCT_INTEL_82371AB_PMC: 126 case PCI_PRODUCT_INTEL_82440MX_PMC: 127 return 1; 128 } 129 break; 130 case PCI_VENDOR_ATI: 131 switch (PCI_PRODUCT(pa->pa_id)) { 132 case PCI_PRODUCT_ATI_SB200_SMB: 133 case PCI_PRODUCT_ATI_SB300_SMB: 134 case PCI_PRODUCT_ATI_SB400_SMB: 135 case PCI_PRODUCT_ATI_SB600_SMB: /* matches SB600/SB700/SB800 */ 136 return 1; 137 } 138 break; 139 case PCI_VENDOR_SERVERWORKS: 140 switch (PCI_PRODUCT(pa->pa_id)) { 141 case PCI_PRODUCT_SERVERWORKS_OSB4: 142 case PCI_PRODUCT_SERVERWORKS_CSB5: 143 case PCI_PRODUCT_SERVERWORKS_CSB6: 144 case PCI_PRODUCT_SERVERWORKS_HT1000SB: 145 return 1; 146 } 147 case PCI_VENDOR_AMD: 148 switch (PCI_PRODUCT(pa->pa_id)) { 149 case PCI_PRODUCT_AMD_HUDSON_SMB: 150 return 1; 151 } 152 } 153 154 return 0; 155 } 156 157 static void 158 piixpm_attach(device_t parent, device_t self, void *aux) 159 { 160 struct piixpm_softc *sc = device_private(self); 161 struct pci_attach_args *pa = aux; 162 pcireg_t base, conf; 163 pcireg_t pmmisc; 164 pci_intr_handle_t ih; 165 const char *intrstr = NULL; 166 int i, flags; 167 char intrbuf[PCI_INTRSTR_LEN]; 168 169 sc->sc_dev = self; 170 sc->sc_iot = pa->pa_iot; 171 sc->sc_id = pa->pa_id; 172 sc->sc_pc = pa->pa_pc; 173 sc->sc_pcitag = pa->pa_tag; 174 sc->sc_numbusses = 1; 175 176 pci_aprint_devinfo(pa, NULL); 177 178 if (!pmf_device_register(self, piixpm_suspend, piixpm_resume)) 179 aprint_error_dev(self, "couldn't establish power handler\n"); 180 181 /* Read configuration */ 182 conf = pci_conf_read(pa->pa_pc, pa->pa_tag, PIIX_SMB_HOSTC); 183 DPRINTF(("%s: conf 0x%x\n", device_xname(self), conf)); 184 185 if ((PCI_VENDOR(pa->pa_id) != PCI_VENDOR_INTEL) || 186 (PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_INTEL_82371AB_PMC)) 187 goto nopowermanagement; 188 189 /* check whether I/O access to PM regs is enabled */ 190 pmmisc = pci_conf_read(pa->pa_pc, pa->pa_tag, PIIX_PMREGMISC); 191 if (!(pmmisc & 1)) 192 goto nopowermanagement; 193 194 /* Map I/O space */ 195 base = pci_conf_read(pa->pa_pc, pa->pa_tag, PIIX_PM_BASE); 196 if (bus_space_map(sc->sc_pm_iot, PCI_MAPREG_IO_ADDR(base), 197 PIIX_PM_SIZE, 0, &sc->sc_pm_ioh)) { 198 aprint_error_dev(self, "can't map power management I/O space\n"); 199 goto nopowermanagement; 200 } 201 202 /* 203 * Revision 0 and 1 are PIIX4, 2 is PIIX4E, 3 is PIIX4M. 204 * PIIX4 and PIIX4E have a bug in the timer latch, see Errata #20 205 * in the "Specification update" (document #297738). 206 */ 207 acpipmtimer_attach(self, sc->sc_pm_iot, sc->sc_pm_ioh, 208 PIIX_PM_PMTMR, 209 (PCI_REVISION(pa->pa_class) < 3) ? ACPIPMT_BADLATCH : 0 ); 210 211 nopowermanagement: 212 213 /* SB800 rev 0x40+ and AMD HUDSON need special initialization */ 214 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_AMD && 215 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_AMD_HUDSON_SMB) { 216 if (piixpm_sb800_init(sc) == 0) { 217 goto attach_i2c; 218 } 219 aprint_normal_dev(self, "SMBus initialization failed\n"); 220 return; 221 } 222 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_ATI && 223 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_ATI_SB600_SMB && 224 PCI_REVISION(pa->pa_class) >= 0x40) { 225 if (piixpm_sb800_init(sc) == 0) { 226 sc->sc_numbusses = 4; 227 goto attach_i2c; 228 } 229 aprint_normal_dev(self, "SMBus initialization failed\n"); 230 return; 231 } 232 233 if ((conf & PIIX_SMB_HOSTC_HSTEN) == 0) { 234 aprint_normal_dev(self, "SMBus disabled\n"); 235 return; 236 } 237 238 /* Map I/O space */ 239 base = pci_conf_read(pa->pa_pc, pa->pa_tag, PIIX_SMB_BASE) & 0xffff; 240 if (bus_space_map(sc->sc_smb_iot, PCI_MAPREG_IO_ADDR(base), 241 PIIX_SMB_SIZE, 0, &sc->sc_smb_ioh)) { 242 aprint_error_dev(self, "can't map smbus I/O space\n"); 243 return; 244 } 245 246 sc->sc_poll = 1; 247 aprint_normal_dev(self, ""); 248 if ((conf & PIIX_SMB_HOSTC_INTMASK) == PIIX_SMB_HOSTC_SMI) { 249 /* No PCI IRQ */ 250 aprint_normal("interrupting at SMI, "); 251 } else if ((conf & PIIX_SMB_HOSTC_INTMASK) == PIIX_SMB_HOSTC_IRQ) { 252 /* Install interrupt handler */ 253 if (pci_intr_map(pa, &ih) == 0) { 254 intrstr = pci_intr_string(pa->pa_pc, ih, intrbuf, sizeof(intrbuf)); 255 sc->sc_smb_ih = pci_intr_establish(pa->pa_pc, ih, IPL_BIO, 256 piixpm_intr, sc); 257 if (sc->sc_smb_ih != NULL) { 258 aprint_normal("interrupting at %s", intrstr); 259 sc->sc_poll = 0; 260 } 261 } 262 } 263 if (sc->sc_poll) 264 aprint_normal("polling"); 265 266 aprint_normal("\n"); 267 268 attach_i2c: 269 for (i = 0; i < sc->sc_numbusses; i++) 270 sc->sc_i2c_device[i] = NULL; 271 272 flags = 0; 273 mutex_init(&sc->sc_i2c_mutex, MUTEX_DEFAULT, IPL_NONE); 274 piixpm_rescan(self, "i2cbus", &flags); 275 } 276 277 static int 278 piixpm_rescan(device_t self, const char *ifattr, const int *flags) 279 { 280 struct piixpm_softc *sc = device_private(self); 281 struct i2cbus_attach_args iba; 282 int i; 283 284 if (!ifattr_match(ifattr, "i2cbus")) 285 return 0; 286 287 /* Attach I2C bus */ 288 289 for (i = 0; i < sc->sc_numbusses; i++) { 290 if (sc->sc_i2c_device[i]) 291 continue; 292 sc->sc_busses[i].sda = i; 293 sc->sc_busses[i].softc = sc; 294 sc->sc_i2c_tags[i].ic_cookie = &sc->sc_busses[i]; 295 sc->sc_i2c_tags[i].ic_acquire_bus = piixpm_i2c_acquire_bus; 296 sc->sc_i2c_tags[i].ic_release_bus = piixpm_i2c_release_bus; 297 sc->sc_i2c_tags[i].ic_exec = piixpm_i2c_exec; 298 memset(&iba, 0, sizeof(iba)); 299 iba.iba_type = I2C_TYPE_SMBUS; 300 iba.iba_tag = &sc->sc_i2c_tags[i]; 301 sc->sc_i2c_device[i] = config_found_ia(self, ifattr, &iba, 302 iicbus_print); 303 } 304 305 return 0; 306 } 307 308 static void 309 piixpm_chdet(device_t self, device_t child) 310 { 311 struct piixpm_softc *sc = device_private(self); 312 int i; 313 314 for (i = 0; i < sc->sc_numbusses; i++) { 315 if (sc->sc_i2c_device[i] == child) { 316 sc->sc_i2c_device[i] = NULL; 317 break; 318 } 319 } 320 } 321 322 323 static bool 324 piixpm_suspend(device_t dv, const pmf_qual_t *qual) 325 { 326 struct piixpm_softc *sc = device_private(dv); 327 328 sc->sc_devact[0] = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 329 PIIX_DEVACTA); 330 sc->sc_devact[1] = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 331 PIIX_DEVACTB); 332 333 return true; 334 } 335 336 static bool 337 piixpm_resume(device_t dv, const pmf_qual_t *qual) 338 { 339 struct piixpm_softc *sc = device_private(dv); 340 341 pci_conf_write(sc->sc_pc, sc->sc_pcitag, PIIX_DEVACTA, 342 sc->sc_devact[0]); 343 pci_conf_write(sc->sc_pc, sc->sc_pcitag, PIIX_DEVACTB, 344 sc->sc_devact[1]); 345 346 return true; 347 } 348 349 /* 350 * Extract SMBus base address from SB800 Power Management (PM) registers. 351 * The PM registers can be accessed either through indirect I/O (CD6/CD7) or 352 * direct mapping if AcpiMMioDecodeEn is enabled. Since this function is only 353 * called once it uses indirect I/O for simplicity. 354 */ 355 static int 356 piixpm_sb800_init(struct piixpm_softc *sc) 357 { 358 bus_space_tag_t iot = sc->sc_iot; 359 bus_space_handle_t ioh; /* indirect I/O handle */ 360 uint16_t val, base_addr; 361 362 /* Fetch SMB base address */ 363 if (bus_space_map(iot, 364 PIIXPM_INDIRECTIO_BASE, PIIXPM_INDIRECTIO_SIZE, 0, &ioh)) { 365 device_printf(sc->sc_dev, "couldn't map indirect I/O space\n"); 366 return EBUSY; 367 } 368 bus_space_write_1(iot, ioh, PIIXPM_INDIRECTIO_INDEX, 369 SB800_PM_SMBUS0EN_LO); 370 val = bus_space_read_1(iot, ioh, PIIXPM_INDIRECTIO_DATA); 371 bus_space_write_1(iot, ioh, PIIXPM_INDIRECTIO_INDEX, 372 SB800_PM_SMBUS0EN_HI); 373 val |= bus_space_read_1(iot, ioh, PIIXPM_INDIRECTIO_DATA) << 8; 374 sc->sc_sb800_ioh = ioh; 375 376 if ((val & SB800_PM_SMBUS0EN_ENABLE) == 0) 377 return ENOENT; 378 379 base_addr = val & SB800_PM_SMBUS0EN_BADDR; 380 381 aprint_debug_dev(sc->sc_dev, "SMBus @ 0x%04x\n", base_addr); 382 383 bus_space_write_1(iot, ioh, PIIXPM_INDIRECTIO_INDEX, SB800_PM_SMBUS0SELEN); 384 bus_space_write_1(iot, ioh, PIIXPM_INDIRECTIO_DATA, 1); /* SMBUS0SEL */ 385 386 if (bus_space_map(iot, PCI_MAPREG_IO_ADDR(base_addr), 387 PIIX_SMB_SIZE, 0, &sc->sc_smb_ioh)) { 388 aprint_error_dev(sc->sc_dev, "can't map smbus I/O space\n"); 389 return EBUSY; 390 } 391 aprint_normal_dev(sc->sc_dev, "polling (SB800)\n"); 392 sc->sc_poll = 1; 393 394 return 0; 395 } 396 397 static void 398 piixpm_csb5_reset(void *arg) 399 { 400 struct piixpm_softc *sc = arg; 401 pcireg_t base, hostc, pmbase; 402 403 base = pci_conf_read(sc->sc_pc, sc->sc_pcitag, PIIX_SMB_BASE); 404 hostc = pci_conf_read(sc->sc_pc, sc->sc_pcitag, PIIX_SMB_HOSTC); 405 406 pmbase = pci_conf_read(sc->sc_pc, sc->sc_pcitag, PIIX_PM_BASE); 407 pmbase |= PIIX_PM_BASE_CSB5_RESET; 408 pci_conf_write(sc->sc_pc, sc->sc_pcitag, PIIX_PM_BASE, pmbase); 409 pmbase &= ~PIIX_PM_BASE_CSB5_RESET; 410 pci_conf_write(sc->sc_pc, sc->sc_pcitag, PIIX_PM_BASE, pmbase); 411 412 pci_conf_write(sc->sc_pc, sc->sc_pcitag, PIIX_SMB_BASE, base); 413 pci_conf_write(sc->sc_pc, sc->sc_pcitag, PIIX_SMB_HOSTC, hostc); 414 415 (void) tsleep(&sc, PRIBIO, "csb5reset", hz/2); 416 } 417 418 static int 419 piixpm_i2c_acquire_bus(void *cookie, int flags) 420 { 421 struct piixpm_smbus *smbus = cookie; 422 struct piixpm_softc *sc = smbus->softc; 423 424 if (!cold) 425 mutex_enter(&sc->sc_i2c_mutex); 426 427 if (smbus->sda > 0) /* SB800 */ 428 { 429 bus_space_write_1(sc->sc_iot, sc->sc_sb800_ioh, 430 PIIXPM_INDIRECTIO_INDEX, SB800_PM_SMBUS0SEL); 431 bus_space_write_1(sc->sc_iot, sc->sc_sb800_ioh, 432 PIIXPM_INDIRECTIO_DATA, smbus->sda << 1); 433 } 434 435 return 0; 436 } 437 438 static void 439 piixpm_i2c_release_bus(void *cookie, int flags) 440 { 441 struct piixpm_smbus *smbus = cookie; 442 struct piixpm_softc *sc = smbus->softc; 443 444 if (smbus->sda > 0) /* SB800 */ 445 { 446 /* 447 * HP Microserver hangs after reboot if not set to SDA0. 448 * Also add shutdown hook? 449 */ 450 bus_space_write_1(sc->sc_iot, sc->sc_sb800_ioh, 451 PIIXPM_INDIRECTIO_INDEX, SB800_PM_SMBUS0SEL); 452 bus_space_write_1(sc->sc_iot, sc->sc_sb800_ioh, 453 PIIXPM_INDIRECTIO_DATA, 0); 454 } 455 456 if (!cold) 457 mutex_exit(&sc->sc_i2c_mutex); 458 } 459 460 static int 461 piixpm_i2c_exec(void *cookie, i2c_op_t op, i2c_addr_t addr, 462 const void *cmdbuf, size_t cmdlen, void *buf, size_t len, int flags) 463 { 464 struct piixpm_smbus *smbus = cookie; 465 struct piixpm_softc *sc = smbus->softc; 466 const u_int8_t *b; 467 u_int8_t ctl = 0, st; 468 int retries; 469 470 DPRINTF(("%s: exec: op %d, addr 0x%x, cmdlen %zu, len %zu, flags 0x%x\n", 471 device_xname(sc->sc_dev), op, addr, cmdlen, len, flags)); 472 473 /* Clear status bits */ 474 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_HS, 475 PIIX_SMB_HS_INTR | PIIX_SMB_HS_DEVERR | 476 PIIX_SMB_HS_BUSERR | PIIX_SMB_HS_FAILED); 477 bus_space_barrier(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_HS, 1, 478 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 479 480 /* Wait for bus to be idle */ 481 for (retries = 100; retries > 0; retries--) { 482 st = bus_space_read_1(sc->sc_smb_iot, sc->sc_smb_ioh, 483 PIIX_SMB_HS); 484 if (!(st & PIIX_SMB_HS_BUSY)) 485 break; 486 DELAY(PIIXPM_DELAY); 487 } 488 DPRINTF(("%s: exec: st 0x%d\n", device_xname(sc->sc_dev), st & 0xff)); 489 if (st & PIIX_SMB_HS_BUSY) 490 return (1); 491 492 if (cold || sc->sc_poll) 493 flags |= I2C_F_POLL; 494 495 if (!I2C_OP_STOP_P(op) || cmdlen > 1 || len > 2 || 496 (cmdlen == 0 && len > 1)) 497 return (1); 498 499 /* Setup transfer */ 500 sc->sc_i2c_xfer.op = op; 501 sc->sc_i2c_xfer.buf = buf; 502 sc->sc_i2c_xfer.len = len; 503 sc->sc_i2c_xfer.flags = flags; 504 sc->sc_i2c_xfer.error = 0; 505 506 /* Set slave address and transfer direction */ 507 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_TXSLVA, 508 PIIX_SMB_TXSLVA_ADDR(addr) | 509 (I2C_OP_READ_P(op) ? PIIX_SMB_TXSLVA_READ : 0)); 510 511 b = cmdbuf; 512 if (cmdlen > 0) 513 /* Set command byte */ 514 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, 515 PIIX_SMB_HCMD, b[0]); 516 517 if (I2C_OP_WRITE_P(op)) { 518 /* Write data */ 519 b = buf; 520 if (cmdlen == 0 && len == 1) 521 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, 522 PIIX_SMB_HCMD, b[0]); 523 else if (len > 0) 524 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, 525 PIIX_SMB_HD0, b[0]); 526 if (len > 1) 527 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, 528 PIIX_SMB_HD1, b[1]); 529 } 530 531 /* Set SMBus command */ 532 if (cmdlen == 0) { 533 if (len == 0) 534 ctl = PIIX_SMB_HC_CMD_QUICK; 535 else 536 ctl = PIIX_SMB_HC_CMD_BYTE; 537 } else if (len == 1) 538 ctl = PIIX_SMB_HC_CMD_BDATA; 539 else if (len == 2) 540 ctl = PIIX_SMB_HC_CMD_WDATA; 541 542 if ((flags & I2C_F_POLL) == 0) 543 ctl |= PIIX_SMB_HC_INTREN; 544 545 /* Start transaction */ 546 ctl |= PIIX_SMB_HC_START; 547 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_HC, ctl); 548 549 if (flags & I2C_F_POLL) { 550 /* Poll for completion */ 551 if (PIIXPM_IS_CSB5(sc->sc_id)) 552 DELAY(2*PIIXPM_DELAY); 553 else 554 DELAY(PIIXPM_DELAY); 555 for (retries = 1000; retries > 0; retries--) { 556 st = bus_space_read_1(sc->sc_smb_iot, sc->sc_smb_ioh, 557 PIIX_SMB_HS); 558 if ((st & PIIX_SMB_HS_BUSY) == 0) 559 break; 560 DELAY(PIIXPM_DELAY); 561 } 562 if (st & PIIX_SMB_HS_BUSY) 563 goto timeout; 564 piixpm_intr(sc); 565 } else { 566 /* Wait for interrupt */ 567 if (tsleep(sc, PRIBIO, "iicexec", PIIXPM_TIMEOUT * hz)) 568 goto timeout; 569 } 570 571 if (sc->sc_i2c_xfer.error) 572 return (1); 573 574 return (0); 575 576 timeout: 577 /* 578 * Transfer timeout. Kill the transaction and clear status bits. 579 */ 580 aprint_error_dev(sc->sc_dev, "timeout, status 0x%x\n", st); 581 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_HC, 582 PIIX_SMB_HC_KILL); 583 DELAY(PIIXPM_DELAY); 584 st = bus_space_read_1(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_HS); 585 if ((st & PIIX_SMB_HS_FAILED) == 0) 586 aprint_error_dev(sc->sc_dev, "transaction abort failed, status 0x%x\n", st); 587 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_HS, st); 588 /* 589 * CSB5 needs hard reset to unlock the smbus after timeout. 590 */ 591 if (PIIXPM_IS_CSB5(sc->sc_id)) 592 piixpm_csb5_reset(sc); 593 return (1); 594 } 595 596 static int 597 piixpm_intr(void *arg) 598 { 599 struct piixpm_softc *sc = arg; 600 u_int8_t st; 601 u_int8_t *b; 602 size_t len; 603 604 /* Read status */ 605 st = bus_space_read_1(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_HS); 606 if ((st & PIIX_SMB_HS_BUSY) != 0 || (st & (PIIX_SMB_HS_INTR | 607 PIIX_SMB_HS_DEVERR | PIIX_SMB_HS_BUSERR | 608 PIIX_SMB_HS_FAILED)) == 0) 609 /* Interrupt was not for us */ 610 return (0); 611 612 DPRINTF(("%s: intr st 0x%d\n", device_xname(sc->sc_dev), st & 0xff)); 613 614 /* Clear status bits */ 615 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_HS, st); 616 617 /* Check for errors */ 618 if (st & (PIIX_SMB_HS_DEVERR | PIIX_SMB_HS_BUSERR | 619 PIIX_SMB_HS_FAILED)) { 620 sc->sc_i2c_xfer.error = 1; 621 goto done; 622 } 623 624 if (st & PIIX_SMB_HS_INTR) { 625 if (I2C_OP_WRITE_P(sc->sc_i2c_xfer.op)) 626 goto done; 627 628 /* Read data */ 629 b = sc->sc_i2c_xfer.buf; 630 len = sc->sc_i2c_xfer.len; 631 if (len > 0) 632 b[0] = bus_space_read_1(sc->sc_smb_iot, sc->sc_smb_ioh, 633 PIIX_SMB_HD0); 634 if (len > 1) 635 b[1] = bus_space_read_1(sc->sc_smb_iot, sc->sc_smb_ioh, 636 PIIX_SMB_HD1); 637 } 638 639 done: 640 if ((sc->sc_i2c_xfer.flags & I2C_F_POLL) == 0) 641 wakeup(sc); 642 return (1); 643 } 644
Indexes created Sun Sep 28 12:09:53 GMT 2025