piixpm.c revision 1.49
1 /* $NetBSD: piixpm.c,v 1.49 2016/07/11 11:31:51 msaitoh Exp $ */ 2 /* $OpenBSD: piixpm.c,v 1.20 2006/02/27 08:25:02 grange Exp $ */ 3 4 /* 5 * Copyright (c) 2005, 2006 Alexander Yurchenko <grange (at) openbsd.org> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 /* 21 * Intel PIIX and compatible Power Management controller driver. 22 */ 23 24 #include <sys/cdefs.h> 25 __KERNEL_RCSID(0, "$NetBSD: piixpm.c,v 1.49 2016/07/11 11:31:51 msaitoh Exp $"); 26 27 #include <sys/param.h> 28 #include <sys/systm.h> 29 #include <sys/device.h> 30 #include <sys/kernel.h> 31 #include <sys/mutex.h> 32 #include <sys/proc.h> 33 34 #include <sys/bus.h> 35 36 #include <dev/pci/pcidevs.h> 37 #include <dev/pci/pcireg.h> 38 #include <dev/pci/pcivar.h> 39 40 #include <dev/pci/piixpmreg.h> 41 42 #include <dev/i2c/i2cvar.h> 43 44 #include <dev/ic/acpipmtimer.h> 45 46 #ifdef PIIXPM_DEBUG 47 #define DPRINTF(x) printf x 48 #else 49 #define DPRINTF(x) 50 #endif 51 52 #define PIIXPM_IS_CSB5(id) \ 53 (PCI_VENDOR((id)) == PCI_VENDOR_SERVERWORKS && \ 54 PCI_PRODUCT((id)) == PCI_PRODUCT_SERVERWORKS_CSB5) 55 #define PIIXPM_DELAY 200 56 #define PIIXPM_TIMEOUT 1 57 58 struct piixpm_smbus { 59 int sda; 60 struct piixpm_softc *softc; 61 }; 62 63 struct piixpm_softc { 64 device_t sc_dev; 65 66 bus_space_tag_t sc_iot; 67 #define sc_pm_iot sc_iot 68 #define sc_smb_iot sc_iot 69 bus_space_handle_t sc_pm_ioh; 70 bus_space_handle_t sc_sb800_ioh; 71 bus_space_handle_t sc_smb_ioh; 72 void * sc_smb_ih; 73 int sc_poll; 74 75 pci_chipset_tag_t sc_pc; 76 pcitag_t sc_pcitag; 77 pcireg_t sc_id; 78 79 int sc_numbusses; 80 device_t sc_i2c_device[4]; 81 struct piixpm_smbus sc_busses[4]; 82 struct i2c_controller sc_i2c_tags[4]; 83 84 kmutex_t sc_i2c_mutex; 85 struct { 86 i2c_op_t op; 87 void * buf; 88 size_t len; 89 int flags; 90 volatile int error; 91 } sc_i2c_xfer; 92 93 pcireg_t sc_devact[2]; 94 }; 95 96 static int piixpm_match(device_t, cfdata_t, void *); 97 static void piixpm_attach(device_t, device_t, void *); 98 static int piixpm_rescan(device_t, const char *, const int *); 99 static void piixpm_chdet(device_t, device_t); 100 101 static bool piixpm_suspend(device_t, const pmf_qual_t *); 102 static bool piixpm_resume(device_t, const pmf_qual_t *); 103 104 static int piixpm_sb800_init(struct piixpm_softc *); 105 static void piixpm_csb5_reset(void *); 106 static int piixpm_i2c_acquire_bus(void *, int); 107 static void piixpm_i2c_release_bus(void *, int); 108 static int piixpm_i2c_exec(void *, i2c_op_t, i2c_addr_t, const void *, 109 size_t, void *, size_t, int); 110 111 static int piixpm_intr(void *); 112 113 CFATTACH_DECL3_NEW(piixpm, sizeof(struct piixpm_softc), 114 piixpm_match, piixpm_attach, NULL, NULL, piixpm_rescan, piixpm_chdet, 0); 115 116 static int 117 piixpm_match(device_t parent, cfdata_t match, void *aux) 118 { 119 struct pci_attach_args *pa; 120 121 pa = (struct pci_attach_args *)aux; 122 switch (PCI_VENDOR(pa->pa_id)) { 123 case PCI_VENDOR_INTEL: 124 switch (PCI_PRODUCT(pa->pa_id)) { 125 case PCI_PRODUCT_INTEL_82371AB_PMC: 126 case PCI_PRODUCT_INTEL_82440MX_PMC: 127 return 1; 128 } 129 break; 130 case PCI_VENDOR_ATI: 131 switch (PCI_PRODUCT(pa->pa_id)) { 132 case PCI_PRODUCT_ATI_SB200_SMB: 133 case PCI_PRODUCT_ATI_SB300_SMB: 134 case PCI_PRODUCT_ATI_SB400_SMB: 135 case PCI_PRODUCT_ATI_SB600_SMB: /* matches SB600/SB700/SB800 */ 136 return 1; 137 } 138 break; 139 case PCI_VENDOR_SERVERWORKS: 140 switch (PCI_PRODUCT(pa->pa_id)) { 141 case PCI_PRODUCT_SERVERWORKS_OSB4: 142 case PCI_PRODUCT_SERVERWORKS_CSB5: 143 case PCI_PRODUCT_SERVERWORKS_CSB6: 144 case PCI_PRODUCT_SERVERWORKS_HT1000SB: 145 return 1; 146 } 147 case PCI_VENDOR_AMD: 148 switch (PCI_PRODUCT(pa->pa_id)) { 149 case PCI_PRODUCT_AMD_HUDSON_SMB: 150 return 1; 151 } 152 } 153 154 return 0; 155 } 156 157 static void 158 piixpm_attach(device_t parent, device_t self, void *aux) 159 { 160 struct piixpm_softc *sc = device_private(self); 161 struct pci_attach_args *pa = aux; 162 pcireg_t base, conf; 163 pcireg_t pmmisc; 164 pci_intr_handle_t ih; 165 const char *intrstr = NULL; 166 int i, flags; 167 char intrbuf[PCI_INTRSTR_LEN]; 168 169 sc->sc_dev = self; 170 sc->sc_iot = pa->pa_iot; 171 sc->sc_id = pa->pa_id; 172 sc->sc_pc = pa->pa_pc; 173 sc->sc_pcitag = pa->pa_tag; 174 sc->sc_numbusses = 1; 175 176 pci_aprint_devinfo(pa, NULL); 177 178 if (!pmf_device_register(self, piixpm_suspend, piixpm_resume)) 179 aprint_error_dev(self, "couldn't establish power handler\n"); 180 181 /* Read configuration */ 182 conf = pci_conf_read(pa->pa_pc, pa->pa_tag, PIIX_SMB_HOSTC); 183 DPRINTF(("%s: conf 0x%x\n", device_xname(self), conf)); 184 185 if ((PCI_VENDOR(pa->pa_id) != PCI_VENDOR_INTEL) || 186 (PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_INTEL_82371AB_PMC)) 187 goto nopowermanagement; 188 189 /* check whether I/O access to PM regs is enabled */ 190 pmmisc = pci_conf_read(pa->pa_pc, pa->pa_tag, PIIX_PMREGMISC); 191 if (!(pmmisc & 1)) 192 goto nopowermanagement; 193 194 /* Map I/O space */ 195 base = pci_conf_read(pa->pa_pc, pa->pa_tag, PIIX_PM_BASE); 196 if (bus_space_map(sc->sc_pm_iot, PCI_MAPREG_IO_ADDR(base), 197 PIIX_PM_SIZE, 0, &sc->sc_pm_ioh)) { 198 aprint_error_dev(self, 199 "can't map power management I/O space\n"); 200 goto nopowermanagement; 201 } 202 203 /* 204 * Revision 0 and 1 are PIIX4, 2 is PIIX4E, 3 is PIIX4M. 205 * PIIX4 and PIIX4E have a bug in the timer latch, see Errata #20 206 * in the "Specification update" (document #297738). 207 */ 208 acpipmtimer_attach(self, sc->sc_pm_iot, sc->sc_pm_ioh, 209 PIIX_PM_PMTMR, 210 (PCI_REVISION(pa->pa_class) < 3) ? ACPIPMT_BADLATCH : 0 ); 211 212 nopowermanagement: 213 214 /* SB800 rev 0x40+ and AMD HUDSON need special initialization */ 215 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_AMD && 216 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_AMD_HUDSON_SMB) { 217 if (piixpm_sb800_init(sc) == 0) { 218 goto attach_i2c; 219 } 220 aprint_normal_dev(self, "SMBus initialization failed\n"); 221 return; 222 } 223 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_ATI && 224 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_ATI_SB600_SMB && 225 PCI_REVISION(pa->pa_class) >= 0x40) { 226 if (piixpm_sb800_init(sc) == 0) { 227 sc->sc_numbusses = 4; 228 goto attach_i2c; 229 } 230 aprint_normal_dev(self, "SMBus initialization failed\n"); 231 return; 232 } 233 234 if ((conf & PIIX_SMB_HOSTC_HSTEN) == 0) { 235 aprint_normal_dev(self, "SMBus disabled\n"); 236 return; 237 } 238 239 /* Map I/O space */ 240 base = pci_conf_read(pa->pa_pc, pa->pa_tag, PIIX_SMB_BASE) & 0xffff; 241 if (bus_space_map(sc->sc_smb_iot, PCI_MAPREG_IO_ADDR(base), 242 PIIX_SMB_SIZE, 0, &sc->sc_smb_ioh)) { 243 aprint_error_dev(self, "can't map smbus I/O space\n"); 244 return; 245 } 246 247 sc->sc_poll = 1; 248 aprint_normal_dev(self, ""); 249 if ((conf & PIIX_SMB_HOSTC_INTMASK) == PIIX_SMB_HOSTC_SMI) { 250 /* No PCI IRQ */ 251 aprint_normal("interrupting at SMI, "); 252 } else if ((conf & PIIX_SMB_HOSTC_INTMASK) == PIIX_SMB_HOSTC_IRQ) { 253 /* Install interrupt handler */ 254 if (pci_intr_map(pa, &ih) == 0) { 255 intrstr = pci_intr_string(pa->pa_pc, ih, intrbuf, 256 sizeof(intrbuf)); 257 sc->sc_smb_ih = pci_intr_establish(pa->pa_pc, ih, 258 IPL_BIO, piixpm_intr, sc); 259 if (sc->sc_smb_ih != NULL) { 260 aprint_normal("interrupting at %s", intrstr); 261 sc->sc_poll = 0; 262 } 263 } 264 } 265 if (sc->sc_poll) 266 aprint_normal("polling"); 267 268 aprint_normal("\n"); 269 270 attach_i2c: 271 for (i = 0; i < sc->sc_numbusses; i++) 272 sc->sc_i2c_device[i] = NULL; 273 274 flags = 0; 275 mutex_init(&sc->sc_i2c_mutex, MUTEX_DEFAULT, IPL_NONE); 276 piixpm_rescan(self, "i2cbus", &flags); 277 } 278 279 static int 280 piixpm_rescan(device_t self, const char *ifattr, const int *flags) 281 { 282 struct piixpm_softc *sc = device_private(self); 283 struct i2cbus_attach_args iba; 284 int i; 285 286 if (!ifattr_match(ifattr, "i2cbus")) 287 return 0; 288 289 /* Attach I2C bus */ 290 291 for (i = 0; i < sc->sc_numbusses; i++) { 292 if (sc->sc_i2c_device[i]) 293 continue; 294 sc->sc_busses[i].sda = i; 295 sc->sc_busses[i].softc = sc; 296 sc->sc_i2c_tags[i].ic_cookie = &sc->sc_busses[i]; 297 sc->sc_i2c_tags[i].ic_acquire_bus = piixpm_i2c_acquire_bus; 298 sc->sc_i2c_tags[i].ic_release_bus = piixpm_i2c_release_bus; 299 sc->sc_i2c_tags[i].ic_exec = piixpm_i2c_exec; 300 memset(&iba, 0, sizeof(iba)); 301 iba.iba_type = I2C_TYPE_SMBUS; 302 iba.iba_tag = &sc->sc_i2c_tags[i]; 303 sc->sc_i2c_device[i] = config_found_ia(self, ifattr, &iba, 304 iicbus_print); 305 } 306 307 return 0; 308 } 309 310 static void 311 piixpm_chdet(device_t self, device_t child) 312 { 313 struct piixpm_softc *sc = device_private(self); 314 int i; 315 316 for (i = 0; i < sc->sc_numbusses; i++) { 317 if (sc->sc_i2c_device[i] == child) { 318 sc->sc_i2c_device[i] = NULL; 319 break; 320 } 321 } 322 } 323 324 325 static bool 326 piixpm_suspend(device_t dv, const pmf_qual_t *qual) 327 { 328 struct piixpm_softc *sc = device_private(dv); 329 330 sc->sc_devact[0] = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 331 PIIX_DEVACTA); 332 sc->sc_devact[1] = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 333 PIIX_DEVACTB); 334 335 return true; 336 } 337 338 static bool 339 piixpm_resume(device_t dv, const pmf_qual_t *qual) 340 { 341 struct piixpm_softc *sc = device_private(dv); 342 343 pci_conf_write(sc->sc_pc, sc->sc_pcitag, PIIX_DEVACTA, 344 sc->sc_devact[0]); 345 pci_conf_write(sc->sc_pc, sc->sc_pcitag, PIIX_DEVACTB, 346 sc->sc_devact[1]); 347 348 return true; 349 } 350 351 /* 352 * Extract SMBus base address from SB800 Power Management (PM) registers. 353 * The PM registers can be accessed either through indirect I/O (CD6/CD7) or 354 * direct mapping if AcpiMMioDecodeEn is enabled. Since this function is only 355 * called once it uses indirect I/O for simplicity. 356 */ 357 static int 358 piixpm_sb800_init(struct piixpm_softc *sc) 359 { 360 bus_space_tag_t iot = sc->sc_iot; 361 bus_space_handle_t ioh; /* indirect I/O handle */ 362 uint16_t val, base_addr; 363 364 /* Fetch SMB base address */ 365 if (bus_space_map(iot, 366 PIIXPM_INDIRECTIO_BASE, PIIXPM_INDIRECTIO_SIZE, 0, &ioh)) { 367 device_printf(sc->sc_dev, "couldn't map indirect I/O space\n"); 368 return EBUSY; 369 } 370 bus_space_write_1(iot, ioh, PIIXPM_INDIRECTIO_INDEX, 371 SB800_PM_SMBUS0EN_LO); 372 val = bus_space_read_1(iot, ioh, PIIXPM_INDIRECTIO_DATA); 373 bus_space_write_1(iot, ioh, PIIXPM_INDIRECTIO_INDEX, 374 SB800_PM_SMBUS0EN_HI); 375 val |= bus_space_read_1(iot, ioh, PIIXPM_INDIRECTIO_DATA) << 8; 376 sc->sc_sb800_ioh = ioh; 377 378 if ((val & SB800_PM_SMBUS0EN_ENABLE) == 0) 379 return ENOENT; 380 381 base_addr = val & SB800_PM_SMBUS0EN_BADDR; 382 383 aprint_debug_dev(sc->sc_dev, "SMBus @ 0x%04x\n", base_addr); 384 385 bus_space_write_1(iot, ioh, PIIXPM_INDIRECTIO_INDEX, 386 SB800_PM_SMBUS0SELEN); 387 bus_space_write_1(iot, ioh, PIIXPM_INDIRECTIO_DATA, 1); /* SMBUS0SEL */ 388 389 if (bus_space_map(iot, PCI_MAPREG_IO_ADDR(base_addr), 390 PIIX_SMB_SIZE, 0, &sc->sc_smb_ioh)) { 391 aprint_error_dev(sc->sc_dev, "can't map smbus I/O space\n"); 392 return EBUSY; 393 } 394 aprint_normal_dev(sc->sc_dev, "polling (SB800)\n"); 395 sc->sc_poll = 1; 396 397 return 0; 398 } 399 400 static void 401 piixpm_csb5_reset(void *arg) 402 { 403 struct piixpm_softc *sc = arg; 404 pcireg_t base, hostc, pmbase; 405 406 base = pci_conf_read(sc->sc_pc, sc->sc_pcitag, PIIX_SMB_BASE); 407 hostc = pci_conf_read(sc->sc_pc, sc->sc_pcitag, PIIX_SMB_HOSTC); 408 409 pmbase = pci_conf_read(sc->sc_pc, sc->sc_pcitag, PIIX_PM_BASE); 410 pmbase |= PIIX_PM_BASE_CSB5_RESET; 411 pci_conf_write(sc->sc_pc, sc->sc_pcitag, PIIX_PM_BASE, pmbase); 412 pmbase &= ~PIIX_PM_BASE_CSB5_RESET; 413 pci_conf_write(sc->sc_pc, sc->sc_pcitag, PIIX_PM_BASE, pmbase); 414 415 pci_conf_write(sc->sc_pc, sc->sc_pcitag, PIIX_SMB_BASE, base); 416 pci_conf_write(sc->sc_pc, sc->sc_pcitag, PIIX_SMB_HOSTC, hostc); 417 418 (void) tsleep(&sc, PRIBIO, "csb5reset", hz/2); 419 } 420 421 static int 422 piixpm_i2c_acquire_bus(void *cookie, int flags) 423 { 424 struct piixpm_smbus *smbus = cookie; 425 struct piixpm_softc *sc = smbus->softc; 426 427 if (!cold) 428 mutex_enter(&sc->sc_i2c_mutex); 429 430 if (smbus->sda > 0) /* SB800 */ 431 { 432 bus_space_write_1(sc->sc_iot, sc->sc_sb800_ioh, 433 PIIXPM_INDIRECTIO_INDEX, SB800_PM_SMBUS0SEL); 434 bus_space_write_1(sc->sc_iot, sc->sc_sb800_ioh, 435 PIIXPM_INDIRECTIO_DATA, smbus->sda << 1); 436 } 437 438 return 0; 439 } 440 441 static void 442 piixpm_i2c_release_bus(void *cookie, int flags) 443 { 444 struct piixpm_smbus *smbus = cookie; 445 struct piixpm_softc *sc = smbus->softc; 446 447 if (smbus->sda > 0) /* SB800 */ 448 { 449 /* 450 * HP Microserver hangs after reboot if not set to SDA0. 451 * Also add shutdown hook? 452 */ 453 bus_space_write_1(sc->sc_iot, sc->sc_sb800_ioh, 454 PIIXPM_INDIRECTIO_INDEX, SB800_PM_SMBUS0SEL); 455 bus_space_write_1(sc->sc_iot, sc->sc_sb800_ioh, 456 PIIXPM_INDIRECTIO_DATA, 0); 457 } 458 459 if (!cold) 460 mutex_exit(&sc->sc_i2c_mutex); 461 } 462 463 static int 464 piixpm_i2c_exec(void *cookie, i2c_op_t op, i2c_addr_t addr, 465 const void *cmdbuf, size_t cmdlen, void *buf, size_t len, int flags) 466 { 467 struct piixpm_smbus *smbus = cookie; 468 struct piixpm_softc *sc = smbus->softc; 469 const u_int8_t *b; 470 u_int8_t ctl = 0, st; 471 int retries; 472 473 DPRINTF(("%s: exec: op %d, addr 0x%x, cmdlen %zu, len %zu, flags 0x%x\n", 474 device_xname(sc->sc_dev), op, addr, cmdlen, len, flags)); 475 476 /* Clear status bits */ 477 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_HS, 478 PIIX_SMB_HS_INTR | PIIX_SMB_HS_DEVERR | 479 PIIX_SMB_HS_BUSERR | PIIX_SMB_HS_FAILED); 480 bus_space_barrier(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_HS, 1, 481 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 482 483 /* Wait for bus to be idle */ 484 for (retries = 100; retries > 0; retries--) { 485 st = bus_space_read_1(sc->sc_smb_iot, sc->sc_smb_ioh, 486 PIIX_SMB_HS); 487 if (!(st & PIIX_SMB_HS_BUSY)) 488 break; 489 DELAY(PIIXPM_DELAY); 490 } 491 DPRINTF(("%s: exec: st 0x%d\n", device_xname(sc->sc_dev), st & 0xff)); 492 if (st & PIIX_SMB_HS_BUSY) 493 return (1); 494 495 if (cold || sc->sc_poll) 496 flags |= I2C_F_POLL; 497 498 if (!I2C_OP_STOP_P(op) || cmdlen > 1 || len > 2 || 499 (cmdlen == 0 && len > 1)) 500 return (1); 501 502 /* Setup transfer */ 503 sc->sc_i2c_xfer.op = op; 504 sc->sc_i2c_xfer.buf = buf; 505 sc->sc_i2c_xfer.len = len; 506 sc->sc_i2c_xfer.flags = flags; 507 sc->sc_i2c_xfer.error = 0; 508 509 /* Set slave address and transfer direction */ 510 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_TXSLVA, 511 PIIX_SMB_TXSLVA_ADDR(addr) | 512 (I2C_OP_READ_P(op) ? PIIX_SMB_TXSLVA_READ : 0)); 513 514 b = cmdbuf; 515 if (cmdlen > 0) 516 /* Set command byte */ 517 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, 518 PIIX_SMB_HCMD, b[0]); 519 520 if (I2C_OP_WRITE_P(op)) { 521 /* Write data */ 522 b = buf; 523 if (cmdlen == 0 && len == 1) 524 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, 525 PIIX_SMB_HCMD, b[0]); 526 else if (len > 0) 527 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, 528 PIIX_SMB_HD0, b[0]); 529 if (len > 1) 530 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, 531 PIIX_SMB_HD1, b[1]); 532 } 533 534 /* Set SMBus command */ 535 if (cmdlen == 0) { 536 if (len == 0) 537 ctl = PIIX_SMB_HC_CMD_QUICK; 538 else 539 ctl = PIIX_SMB_HC_CMD_BYTE; 540 } else if (len == 1) 541 ctl = PIIX_SMB_HC_CMD_BDATA; 542 else if (len == 2) 543 ctl = PIIX_SMB_HC_CMD_WDATA; 544 545 if ((flags & I2C_F_POLL) == 0) 546 ctl |= PIIX_SMB_HC_INTREN; 547 548 /* Start transaction */ 549 ctl |= PIIX_SMB_HC_START; 550 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_HC, ctl); 551 552 if (flags & I2C_F_POLL) { 553 /* Poll for completion */ 554 if (PIIXPM_IS_CSB5(sc->sc_id)) 555 DELAY(2*PIIXPM_DELAY); 556 else 557 DELAY(PIIXPM_DELAY); 558 for (retries = 1000; retries > 0; retries--) { 559 st = bus_space_read_1(sc->sc_smb_iot, sc->sc_smb_ioh, 560 PIIX_SMB_HS); 561 if ((st & PIIX_SMB_HS_BUSY) == 0) 562 break; 563 DELAY(PIIXPM_DELAY); 564 } 565 if (st & PIIX_SMB_HS_BUSY) 566 goto timeout; 567 piixpm_intr(sc); 568 } else { 569 /* Wait for interrupt */ 570 if (tsleep(sc, PRIBIO, "iicexec", PIIXPM_TIMEOUT * hz)) 571 goto timeout; 572 } 573 574 if (sc->sc_i2c_xfer.error) 575 return (1); 576 577 return (0); 578 579 timeout: 580 /* 581 * Transfer timeout. Kill the transaction and clear status bits. 582 */ 583 aprint_error_dev(sc->sc_dev, "timeout, status 0x%x\n", st); 584 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_HC, 585 PIIX_SMB_HC_KILL); 586 DELAY(PIIXPM_DELAY); 587 st = bus_space_read_1(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_HS); 588 if ((st & PIIX_SMB_HS_FAILED) == 0) 589 aprint_error_dev(sc->sc_dev, 590 "transaction abort failed, status 0x%x\n", st); 591 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_HS, st); 592 /* 593 * CSB5 needs hard reset to unlock the smbus after timeout. 594 */ 595 if (PIIXPM_IS_CSB5(sc->sc_id)) 596 piixpm_csb5_reset(sc); 597 return (1); 598 } 599 600 static int 601 piixpm_intr(void *arg) 602 { 603 struct piixpm_softc *sc = arg; 604 u_int8_t st; 605 u_int8_t *b; 606 size_t len; 607 608 /* Read status */ 609 st = bus_space_read_1(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_HS); 610 if ((st & PIIX_SMB_HS_BUSY) != 0 || (st & (PIIX_SMB_HS_INTR | 611 PIIX_SMB_HS_DEVERR | PIIX_SMB_HS_BUSERR | 612 PIIX_SMB_HS_FAILED)) == 0) 613 /* Interrupt was not for us */ 614 return (0); 615 616 DPRINTF(("%s: intr st 0x%d\n", device_xname(sc->sc_dev), st & 0xff)); 617 618 /* Clear status bits */ 619 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_HS, st); 620 621 /* Check for errors */ 622 if (st & (PIIX_SMB_HS_DEVERR | PIIX_SMB_HS_BUSERR | 623 PIIX_SMB_HS_FAILED)) { 624 sc->sc_i2c_xfer.error = 1; 625 goto done; 626 } 627 628 if (st & PIIX_SMB_HS_INTR) { 629 if (I2C_OP_WRITE_P(sc->sc_i2c_xfer.op)) 630 goto done; 631 632 /* Read data */ 633 b = sc->sc_i2c_xfer.buf; 634 len = sc->sc_i2c_xfer.len; 635 if (len > 0) 636 b[0] = bus_space_read_1(sc->sc_smb_iot, sc->sc_smb_ioh, 637 PIIX_SMB_HD0); 638 if (len > 1) 639 b[1] = bus_space_read_1(sc->sc_smb_iot, sc->sc_smb_ioh, 640 PIIX_SMB_HD1); 641 } 642 643 done: 644 if ((sc->sc_i2c_xfer.flags & I2C_F_POLL) == 0) 645 wakeup(sc); 646 return (1); 647 } 648
Indexes created Mon Sep 29 21:09:56 GMT 2025