piixpm.c revision 1.49.2.3
1 /* $NetBSD: piixpm.c,v 1.49.2.3 2017/04/26 02:53:22 pgoyette Exp $ */ 2 /* $OpenBSD: piixpm.c,v 1.20 2006/02/27 08:25:02 grange Exp $ */ 3 4 /* 5 * Copyright (c) 2005, 2006 Alexander Yurchenko <grange (at) openbsd.org> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 /* 21 * Intel PIIX and compatible Power Management controller driver. 22 */ 23 24 #include <sys/cdefs.h> 25 <<<<<<< piixpm.c 26 __KERNEL_RCSID(0, "$NetBSD: piixpm.c,v 1.49.2.3 2017/04/26 02:53:22 pgoyette Exp $"); 27 ======= 28 __KERNEL_RCSID(0, "$NetBSD: piixpm.c,v 1.49.2.3 2017/04/26 02:53:22 pgoyette Exp $"); 29 >>>>>>> 1.52 30 31 #include <sys/param.h> 32 #include <sys/systm.h> 33 #include <sys/device.h> 34 #include <sys/kernel.h> 35 #include <sys/mutex.h> 36 #include <sys/proc.h> 37 38 #include <sys/bus.h> 39 40 #include <dev/pci/pcidevs.h> 41 #include <dev/pci/pcireg.h> 42 #include <dev/pci/pcivar.h> 43 44 #include <dev/pci/piixpmreg.h> 45 46 #include <dev/i2c/i2cvar.h> 47 48 #include <dev/ic/acpipmtimer.h> 49 50 #ifdef PIIXPM_DEBUG 51 #define DPRINTF(x) printf x 52 #else 53 #define DPRINTF(x) 54 #endif 55 56 #define PIIXPM_IS_CSB5(id) \ 57 (PCI_VENDOR((id)) == PCI_VENDOR_SERVERWORKS && \ 58 PCI_PRODUCT((id)) == PCI_PRODUCT_SERVERWORKS_CSB5) 59 #define PIIXPM_DELAY 200 60 #define PIIXPM_TIMEOUT 1 61 62 struct piixpm_smbus { 63 int sda; 64 struct piixpm_softc *softc; 65 }; 66 67 struct piixpm_softc { 68 device_t sc_dev; 69 70 bus_space_tag_t sc_iot; 71 #define sc_pm_iot sc_iot 72 #define sc_smb_iot sc_iot 73 bus_space_handle_t sc_pm_ioh; 74 bus_space_handle_t sc_sb800_ioh; 75 bus_space_handle_t sc_smb_ioh; 76 void * sc_smb_ih; 77 int sc_poll; 78 79 pci_chipset_tag_t sc_pc; 80 pcitag_t sc_pcitag; 81 pcireg_t sc_id; 82 83 int sc_numbusses; 84 device_t sc_i2c_device[4]; 85 struct piixpm_smbus sc_busses[4]; 86 struct i2c_controller sc_i2c_tags[4]; 87 88 kmutex_t sc_i2c_mutex; 89 struct { 90 i2c_op_t op; 91 void * buf; 92 size_t len; 93 int flags; 94 volatile int error; 95 } sc_i2c_xfer; 96 97 pcireg_t sc_devact[2]; 98 }; 99 100 static int piixpm_match(device_t, cfdata_t, void *); 101 static void piixpm_attach(device_t, device_t, void *); 102 static int piixpm_rescan(device_t, const char *, const int *); 103 static void piixpm_chdet(device_t, device_t); 104 105 static bool piixpm_suspend(device_t, const pmf_qual_t *); 106 static bool piixpm_resume(device_t, const pmf_qual_t *); 107 108 static int piixpm_sb800_init(struct piixpm_softc *); 109 static void piixpm_csb5_reset(void *); 110 static int piixpm_i2c_acquire_bus(void *, int); 111 static void piixpm_i2c_release_bus(void *, int); 112 static int piixpm_i2c_exec(void *, i2c_op_t, i2c_addr_t, const void *, 113 size_t, void *, size_t, int); 114 115 static int piixpm_intr(void *); 116 117 CFATTACH_DECL3_NEW(piixpm, sizeof(struct piixpm_softc), 118 piixpm_match, piixpm_attach, NULL, NULL, piixpm_rescan, piixpm_chdet, 0); 119 120 static int 121 piixpm_match(device_t parent, cfdata_t match, void *aux) 122 { 123 struct pci_attach_args *pa; 124 125 pa = (struct pci_attach_args *)aux; 126 switch (PCI_VENDOR(pa->pa_id)) { 127 case PCI_VENDOR_INTEL: 128 switch (PCI_PRODUCT(pa->pa_id)) { 129 case PCI_PRODUCT_INTEL_82371AB_PMC: 130 case PCI_PRODUCT_INTEL_82440MX_PMC: 131 return 1; 132 } 133 break; 134 case PCI_VENDOR_ATI: 135 switch (PCI_PRODUCT(pa->pa_id)) { 136 case PCI_PRODUCT_ATI_SB200_SMB: 137 case PCI_PRODUCT_ATI_SB300_SMB: 138 case PCI_PRODUCT_ATI_SB400_SMB: 139 case PCI_PRODUCT_ATI_SB600_SMB: /* matches SB600/SB700/SB800 */ 140 return 1; 141 } 142 break; 143 case PCI_VENDOR_SERVERWORKS: 144 switch (PCI_PRODUCT(pa->pa_id)) { 145 case PCI_PRODUCT_SERVERWORKS_OSB4: 146 case PCI_PRODUCT_SERVERWORKS_CSB5: 147 case PCI_PRODUCT_SERVERWORKS_CSB6: 148 case PCI_PRODUCT_SERVERWORKS_HT1000SB: 149 return 1; 150 } 151 break; 152 case PCI_VENDOR_AMD: 153 switch (PCI_PRODUCT(pa->pa_id)) { 154 case PCI_PRODUCT_AMD_HUDSON_SMB: 155 return 1; 156 } 157 break; 158 } 159 160 return 0; 161 } 162 163 static void 164 piixpm_attach(device_t parent, device_t self, void *aux) 165 { 166 struct piixpm_softc *sc = device_private(self); 167 struct pci_attach_args *pa = aux; 168 pcireg_t base, conf; 169 pcireg_t pmmisc; 170 pci_intr_handle_t ih; 171 const char *intrstr = NULL; 172 int i, flags; 173 char intrbuf[PCI_INTRSTR_LEN]; 174 175 sc->sc_dev = self; 176 sc->sc_iot = pa->pa_iot; 177 sc->sc_id = pa->pa_id; 178 sc->sc_pc = pa->pa_pc; 179 sc->sc_pcitag = pa->pa_tag; 180 sc->sc_numbusses = 1; 181 182 pci_aprint_devinfo(pa, NULL); 183 184 if (!pmf_device_register(self, piixpm_suspend, piixpm_resume)) 185 aprint_error_dev(self, "couldn't establish power handler\n"); 186 187 /* Read configuration */ 188 conf = pci_conf_read(pa->pa_pc, pa->pa_tag, PIIX_SMB_HOSTC); 189 DPRINTF(("%s: conf 0x%x\n", device_xname(self), conf)); 190 191 if ((PCI_VENDOR(pa->pa_id) != PCI_VENDOR_INTEL) || 192 (PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_INTEL_82371AB_PMC)) 193 goto nopowermanagement; 194 195 /* check whether I/O access to PM regs is enabled */ 196 pmmisc = pci_conf_read(pa->pa_pc, pa->pa_tag, PIIX_PMREGMISC); 197 if (!(pmmisc & 1)) 198 goto nopowermanagement; 199 200 /* Map I/O space */ 201 base = pci_conf_read(pa->pa_pc, pa->pa_tag, PIIX_PM_BASE); 202 if (bus_space_map(sc->sc_pm_iot, PCI_MAPREG_IO_ADDR(base), 203 PIIX_PM_SIZE, 0, &sc->sc_pm_ioh)) { 204 aprint_error_dev(self, 205 "can't map power management I/O space\n"); 206 goto nopowermanagement; 207 } 208 209 /* 210 * Revision 0 and 1 are PIIX4, 2 is PIIX4E, 3 is PIIX4M. 211 * PIIX4 and PIIX4E have a bug in the timer latch, see Errata #20 212 * in the "Specification update" (document #297738). 213 */ 214 acpipmtimer_attach(self, sc->sc_pm_iot, sc->sc_pm_ioh, 215 PIIX_PM_PMTMR, 216 (PCI_REVISION(pa->pa_class) < 3) ? ACPIPMT_BADLATCH : 0 ); 217 218 nopowermanagement: 219 220 /* SB800 rev 0x40+ and AMD HUDSON need special initialization */ 221 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_AMD && 222 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_AMD_HUDSON_SMB) { 223 if (piixpm_sb800_init(sc) == 0) { 224 goto attach_i2c; 225 } 226 aprint_normal_dev(self, "SMBus initialization failed\n"); 227 return; 228 } 229 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_ATI && 230 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_ATI_SB600_SMB && 231 PCI_REVISION(pa->pa_class) >= 0x40) { 232 if (piixpm_sb800_init(sc) == 0) { 233 sc->sc_numbusses = 4; 234 goto attach_i2c; 235 } 236 aprint_normal_dev(self, "SMBus initialization failed\n"); 237 return; 238 } 239 240 if ((conf & PIIX_SMB_HOSTC_HSTEN) == 0) { 241 aprint_normal_dev(self, "SMBus disabled\n"); 242 return; 243 } 244 245 /* Map I/O space */ 246 base = pci_conf_read(pa->pa_pc, pa->pa_tag, PIIX_SMB_BASE) & 0xffff; 247 if (bus_space_map(sc->sc_smb_iot, PCI_MAPREG_IO_ADDR(base), 248 PIIX_SMB_SIZE, 0, &sc->sc_smb_ioh)) { 249 aprint_error_dev(self, "can't map smbus I/O space\n"); 250 return; 251 } 252 253 sc->sc_poll = 1; 254 aprint_normal_dev(self, ""); 255 if ((conf & PIIX_SMB_HOSTC_INTMASK) == PIIX_SMB_HOSTC_SMI) { 256 /* No PCI IRQ */ 257 aprint_normal("interrupting at SMI, "); 258 } else if ((conf & PIIX_SMB_HOSTC_INTMASK) == PIIX_SMB_HOSTC_IRQ) { 259 /* Install interrupt handler */ 260 if (pci_intr_map(pa, &ih) == 0) { 261 intrstr = pci_intr_string(pa->pa_pc, ih, intrbuf, 262 sizeof(intrbuf)); 263 sc->sc_smb_ih = pci_intr_establish_xname(pa->pa_pc, ih, 264 IPL_BIO, piixpm_intr, sc, device_xname(sc->sc_dev)); 265 if (sc->sc_smb_ih != NULL) { 266 aprint_normal("interrupting at %s", intrstr); 267 sc->sc_poll = 0; 268 } 269 } 270 } 271 if (sc->sc_poll) 272 aprint_normal("polling"); 273 274 aprint_normal("\n"); 275 276 attach_i2c: 277 for (i = 0; i < sc->sc_numbusses; i++) 278 sc->sc_i2c_device[i] = NULL; 279 280 flags = 0; 281 mutex_init(&sc->sc_i2c_mutex, MUTEX_DEFAULT, IPL_NONE); 282 piixpm_rescan(self, "i2cbus", &flags); 283 } 284 285 static int 286 piixpm_rescan(device_t self, const char *ifattr, const int *flags) 287 { 288 struct piixpm_softc *sc = device_private(self); 289 struct i2cbus_attach_args iba; 290 int i; 291 292 if (!ifattr_match(ifattr, "i2cbus")) 293 return 0; 294 295 /* Attach I2C bus */ 296 297 for (i = 0; i < sc->sc_numbusses; i++) { 298 if (sc->sc_i2c_device[i]) 299 continue; 300 sc->sc_busses[i].sda = i; 301 sc->sc_busses[i].softc = sc; 302 sc->sc_i2c_tags[i].ic_cookie = &sc->sc_busses[i]; 303 sc->sc_i2c_tags[i].ic_acquire_bus = piixpm_i2c_acquire_bus; 304 sc->sc_i2c_tags[i].ic_release_bus = piixpm_i2c_release_bus; 305 sc->sc_i2c_tags[i].ic_exec = piixpm_i2c_exec; 306 memset(&iba, 0, sizeof(iba)); 307 iba.iba_type = I2C_TYPE_SMBUS; 308 iba.iba_tag = &sc->sc_i2c_tags[i]; 309 sc->sc_i2c_device[i] = config_found_ia(self, ifattr, &iba, 310 iicbus_print); 311 } 312 313 return 0; 314 } 315 316 static void 317 piixpm_chdet(device_t self, device_t child) 318 { 319 struct piixpm_softc *sc = device_private(self); 320 int i; 321 322 for (i = 0; i < sc->sc_numbusses; i++) { 323 if (sc->sc_i2c_device[i] == child) { 324 sc->sc_i2c_device[i] = NULL; 325 break; 326 } 327 } 328 } 329 330 331 static bool 332 piixpm_suspend(device_t dv, const pmf_qual_t *qual) 333 { 334 struct piixpm_softc *sc = device_private(dv); 335 336 sc->sc_devact[0] = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 337 PIIX_DEVACTA); 338 sc->sc_devact[1] = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 339 PIIX_DEVACTB); 340 341 return true; 342 } 343 344 static bool 345 piixpm_resume(device_t dv, const pmf_qual_t *qual) 346 { 347 struct piixpm_softc *sc = device_private(dv); 348 349 pci_conf_write(sc->sc_pc, sc->sc_pcitag, PIIX_DEVACTA, 350 sc->sc_devact[0]); 351 pci_conf_write(sc->sc_pc, sc->sc_pcitag, PIIX_DEVACTB, 352 sc->sc_devact[1]); 353 354 return true; 355 } 356 357 /* 358 * Extract SMBus base address from SB800 Power Management (PM) registers. 359 * The PM registers can be accessed either through indirect I/O (CD6/CD7) or 360 * direct mapping if AcpiMMioDecodeEn is enabled. Since this function is only 361 * called once it uses indirect I/O for simplicity. 362 */ 363 static int 364 piixpm_sb800_init(struct piixpm_softc *sc) 365 { 366 bus_space_tag_t iot = sc->sc_iot; 367 bus_space_handle_t ioh; /* indirect I/O handle */ 368 uint16_t val, base_addr; 369 370 /* Fetch SMB base address */ 371 if (bus_space_map(iot, 372 PIIXPM_INDIRECTIO_BASE, PIIXPM_INDIRECTIO_SIZE, 0, &ioh)) { 373 device_printf(sc->sc_dev, "couldn't map indirect I/O space\n"); 374 return EBUSY; 375 } 376 bus_space_write_1(iot, ioh, PIIXPM_INDIRECTIO_INDEX, 377 SB800_PM_SMBUS0EN_LO); 378 val = bus_space_read_1(iot, ioh, PIIXPM_INDIRECTIO_DATA); 379 bus_space_write_1(iot, ioh, PIIXPM_INDIRECTIO_INDEX, 380 SB800_PM_SMBUS0EN_HI); 381 val |= bus_space_read_1(iot, ioh, PIIXPM_INDIRECTIO_DATA) << 8; 382 sc->sc_sb800_ioh = ioh; 383 384 if ((val & SB800_PM_SMBUS0EN_ENABLE) == 0) 385 return ENOENT; 386 387 base_addr = val & SB800_PM_SMBUS0EN_BADDR; 388 389 aprint_debug_dev(sc->sc_dev, "SMBus @ 0x%04x\n", base_addr); 390 391 bus_space_write_1(iot, ioh, PIIXPM_INDIRECTIO_INDEX, 392 SB800_PM_SMBUS0SELEN); 393 bus_space_write_1(iot, ioh, PIIXPM_INDIRECTIO_DATA, 1); /* SMBUS0SEL */ 394 395 if (bus_space_map(iot, PCI_MAPREG_IO_ADDR(base_addr), 396 PIIX_SMB_SIZE, 0, &sc->sc_smb_ioh)) { 397 aprint_error_dev(sc->sc_dev, "can't map smbus I/O space\n"); 398 return EBUSY; 399 } 400 aprint_normal_dev(sc->sc_dev, "polling (SB800)\n"); 401 sc->sc_poll = 1; 402 403 return 0; 404 } 405 406 static void 407 piixpm_csb5_reset(void *arg) 408 { 409 struct piixpm_softc *sc = arg; 410 pcireg_t base, hostc, pmbase; 411 412 base = pci_conf_read(sc->sc_pc, sc->sc_pcitag, PIIX_SMB_BASE); 413 hostc = pci_conf_read(sc->sc_pc, sc->sc_pcitag, PIIX_SMB_HOSTC); 414 415 pmbase = pci_conf_read(sc->sc_pc, sc->sc_pcitag, PIIX_PM_BASE); 416 pmbase |= PIIX_PM_BASE_CSB5_RESET; 417 pci_conf_write(sc->sc_pc, sc->sc_pcitag, PIIX_PM_BASE, pmbase); 418 pmbase &= ~PIIX_PM_BASE_CSB5_RESET; 419 pci_conf_write(sc->sc_pc, sc->sc_pcitag, PIIX_PM_BASE, pmbase); 420 421 pci_conf_write(sc->sc_pc, sc->sc_pcitag, PIIX_SMB_BASE, base); 422 pci_conf_write(sc->sc_pc, sc->sc_pcitag, PIIX_SMB_HOSTC, hostc); 423 424 (void) tsleep(&sc, PRIBIO, "csb5reset", hz/2); 425 } 426 427 static int 428 piixpm_i2c_acquire_bus(void *cookie, int flags) 429 { 430 struct piixpm_smbus *smbus = cookie; 431 struct piixpm_softc *sc = smbus->softc; 432 433 if (!cold) 434 mutex_enter(&sc->sc_i2c_mutex); 435 436 if (smbus->sda > 0) /* SB800 */ 437 { 438 bus_space_write_1(sc->sc_iot, sc->sc_sb800_ioh, 439 PIIXPM_INDIRECTIO_INDEX, SB800_PM_SMBUS0SEL); 440 bus_space_write_1(sc->sc_iot, sc->sc_sb800_ioh, 441 PIIXPM_INDIRECTIO_DATA, smbus->sda << 1); 442 } 443 444 return 0; 445 } 446 447 static void 448 piixpm_i2c_release_bus(void *cookie, int flags) 449 { 450 struct piixpm_smbus *smbus = cookie; 451 struct piixpm_softc *sc = smbus->softc; 452 453 if (smbus->sda > 0) /* SB800 */ 454 { 455 /* 456 * HP Microserver hangs after reboot if not set to SDA0. 457 * Also add shutdown hook? 458 */ 459 bus_space_write_1(sc->sc_iot, sc->sc_sb800_ioh, 460 PIIXPM_INDIRECTIO_INDEX, SB800_PM_SMBUS0SEL); 461 bus_space_write_1(sc->sc_iot, sc->sc_sb800_ioh, 462 PIIXPM_INDIRECTIO_DATA, 0); 463 } 464 465 if (!cold) 466 mutex_exit(&sc->sc_i2c_mutex); 467 } 468 469 static int 470 piixpm_i2c_exec(void *cookie, i2c_op_t op, i2c_addr_t addr, 471 const void *cmdbuf, size_t cmdlen, void *buf, size_t len, int flags) 472 { 473 struct piixpm_smbus *smbus = cookie; 474 struct piixpm_softc *sc = smbus->softc; 475 const u_int8_t *b; 476 u_int8_t ctl = 0, st; 477 int retries; 478 479 DPRINTF(("%s: exec: op %d, addr 0x%x, cmdlen %zu, len %zu, flags 0x%x\n", 480 device_xname(sc->sc_dev), op, addr, cmdlen, len, flags)); 481 482 /* Clear status bits */ 483 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_HS, 484 PIIX_SMB_HS_INTR | PIIX_SMB_HS_DEVERR | 485 PIIX_SMB_HS_BUSERR | PIIX_SMB_HS_FAILED); 486 bus_space_barrier(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_HS, 1, 487 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 488 489 /* Wait for bus to be idle */ 490 for (retries = 100; retries > 0; retries--) { 491 st = bus_space_read_1(sc->sc_smb_iot, sc->sc_smb_ioh, 492 PIIX_SMB_HS); 493 if (!(st & PIIX_SMB_HS_BUSY)) 494 break; 495 DELAY(PIIXPM_DELAY); 496 } 497 DPRINTF(("%s: exec: st %#x\n", device_xname(sc->sc_dev), st & 0xff)); 498 if (st & PIIX_SMB_HS_BUSY) 499 return (1); 500 501 if (cold || sc->sc_poll) 502 flags |= I2C_F_POLL; 503 504 if (!I2C_OP_STOP_P(op) || cmdlen > 1 || len > 2 || 505 (cmdlen == 0 && len > 1)) 506 return (1); 507 508 /* Setup transfer */ 509 sc->sc_i2c_xfer.op = op; 510 sc->sc_i2c_xfer.buf = buf; 511 sc->sc_i2c_xfer.len = len; 512 sc->sc_i2c_xfer.flags = flags; 513 sc->sc_i2c_xfer.error = 0; 514 515 /* Set slave address and transfer direction */ 516 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_TXSLVA, 517 PIIX_SMB_TXSLVA_ADDR(addr) | 518 (I2C_OP_READ_P(op) ? PIIX_SMB_TXSLVA_READ : 0)); 519 520 b = cmdbuf; 521 if (cmdlen > 0) 522 /* Set command byte */ 523 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, 524 PIIX_SMB_HCMD, b[0]); 525 526 if (I2C_OP_WRITE_P(op)) { 527 /* Write data */ 528 b = buf; 529 if (cmdlen == 0 && len == 1) 530 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, 531 PIIX_SMB_HCMD, b[0]); 532 else if (len > 0) 533 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, 534 PIIX_SMB_HD0, b[0]); 535 if (len > 1) 536 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, 537 PIIX_SMB_HD1, b[1]); 538 } 539 540 /* Set SMBus command */ 541 if (cmdlen == 0) { 542 if (len == 0) 543 ctl = PIIX_SMB_HC_CMD_QUICK; 544 else 545 ctl = PIIX_SMB_HC_CMD_BYTE; 546 } else if (len == 1) 547 ctl = PIIX_SMB_HC_CMD_BDATA; 548 else if (len == 2) 549 ctl = PIIX_SMB_HC_CMD_WDATA; 550 551 if ((flags & I2C_F_POLL) == 0) 552 ctl |= PIIX_SMB_HC_INTREN; 553 554 /* Start transaction */ 555 ctl |= PIIX_SMB_HC_START; 556 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_HC, ctl); 557 558 if (flags & I2C_F_POLL) { 559 /* Poll for completion */ 560 if (PIIXPM_IS_CSB5(sc->sc_id)) 561 DELAY(2*PIIXPM_DELAY); 562 else 563 DELAY(PIIXPM_DELAY); 564 for (retries = 1000; retries > 0; retries--) { 565 st = bus_space_read_1(sc->sc_smb_iot, sc->sc_smb_ioh, 566 PIIX_SMB_HS); 567 if ((st & PIIX_SMB_HS_BUSY) == 0) 568 break; 569 DELAY(PIIXPM_DELAY); 570 } 571 if (st & PIIX_SMB_HS_BUSY) 572 goto timeout; 573 piixpm_intr(sc); 574 } else { 575 /* Wait for interrupt */ 576 if (tsleep(sc, PRIBIO, "iicexec", PIIXPM_TIMEOUT * hz)) 577 goto timeout; 578 } 579 580 if (sc->sc_i2c_xfer.error) 581 return (1); 582 583 return (0); 584 585 timeout: 586 /* 587 * Transfer timeout. Kill the transaction and clear status bits. 588 */ 589 aprint_error_dev(sc->sc_dev, "timeout, status 0x%x\n", st); 590 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_HC, 591 PIIX_SMB_HC_KILL); 592 DELAY(PIIXPM_DELAY); 593 st = bus_space_read_1(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_HS); 594 if ((st & PIIX_SMB_HS_FAILED) == 0) 595 aprint_error_dev(sc->sc_dev, 596 "transaction abort failed, status 0x%x\n", st); 597 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_HS, st); 598 /* 599 * CSB5 needs hard reset to unlock the smbus after timeout. 600 */ 601 if (PIIXPM_IS_CSB5(sc->sc_id)) 602 piixpm_csb5_reset(sc); 603 return (1); 604 } 605 606 static int 607 piixpm_intr(void *arg) 608 { 609 struct piixpm_softc *sc = arg; 610 u_int8_t st; 611 u_int8_t *b; 612 size_t len; 613 614 /* Read status */ 615 st = bus_space_read_1(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_HS); 616 if ((st & PIIX_SMB_HS_BUSY) != 0 || (st & (PIIX_SMB_HS_INTR | 617 PIIX_SMB_HS_DEVERR | PIIX_SMB_HS_BUSERR | 618 PIIX_SMB_HS_FAILED)) == 0) 619 /* Interrupt was not for us */ 620 return (0); 621 622 DPRINTF(("%s: intr st %#x\n", device_xname(sc->sc_dev), st & 0xff)); 623 624 /* Clear status bits */ 625 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_HS, st); 626 627 /* Check for errors */ 628 if (st & (PIIX_SMB_HS_DEVERR | PIIX_SMB_HS_BUSERR | 629 PIIX_SMB_HS_FAILED)) { 630 sc->sc_i2c_xfer.error = 1; 631 goto done; 632 } 633 634 if (st & PIIX_SMB_HS_INTR) { 635 if (I2C_OP_WRITE_P(sc->sc_i2c_xfer.op)) 636 goto done; 637 638 /* Read data */ 639 b = sc->sc_i2c_xfer.buf; 640 len = sc->sc_i2c_xfer.len; 641 if (len > 0) 642 b[0] = bus_space_read_1(sc->sc_smb_iot, sc->sc_smb_ioh, 643 PIIX_SMB_HD0); 644 if (len > 1) 645 b[1] = bus_space_read_1(sc->sc_smb_iot, sc->sc_smb_ioh, 646 PIIX_SMB_HD1); 647 } 648 649 done: 650 if ((sc->sc_i2c_xfer.flags & I2C_F_POLL) == 0) 651 wakeup(sc); 652 return (1); 653 } 654
Indexes created Wed Oct 01 19:09:53 GMT 2025