piixpm.c revision 1.5
1 /* $NetBSD: piixpm.c,v 1.5 2006/06/26 17:17:20 drochner Exp $ */ 2 /* $OpenBSD: piixpm.c,v 1.20 2006/02/27 08:25:02 grange Exp $ */ 3 4 /* 5 * Copyright (c) 2005, 2006 Alexander Yurchenko <grange (at) openbsd.org> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 /* 21 * Intel PIIX and compatible Power Management controller driver. 22 */ 23 24 #include <sys/param.h> 25 #include <sys/systm.h> 26 #include <sys/device.h> 27 #include <sys/kernel.h> 28 #include <sys/lock.h> 29 #include <sys/proc.h> 30 31 #include <machine/bus.h> 32 33 #include <dev/pci/pcidevs.h> 34 #include <dev/pci/pcireg.h> 35 #include <dev/pci/pcivar.h> 36 37 #include <dev/pci/piixpmreg.h> 38 39 #include <dev/i2c/i2cvar.h> 40 41 #ifdef __HAVE_TIMECOUNTER 42 #include <dev/ic/acpipmtimer.h> 43 #endif 44 45 #ifdef PIIXPM_DEBUG 46 #define DPRINTF(x) printf x 47 #else 48 #define DPRINTF(x) 49 #endif 50 51 #define PIIXPM_DELAY 200 52 #define PIIXPM_TIMEOUT 1 53 54 struct piixpm_softc { 55 struct device sc_dev; 56 57 bus_space_tag_t sc_smb_iot; 58 bus_space_handle_t sc_smb_ioh; 59 void * sc_smb_ih; 60 int sc_poll; 61 62 bus_space_tag_t sc_pm_iot; 63 bus_space_handle_t sc_pm_ioh; 64 65 pci_chipset_tag_t sc_pc; 66 pcitag_t sc_pcitag; 67 68 struct i2c_controller sc_i2c_tag; 69 struct lock sc_i2c_lock; 70 struct { 71 i2c_op_t op; 72 void * buf; 73 size_t len; 74 int flags; 75 volatile int error; 76 } sc_i2c_xfer; 77 78 void * sc_powerhook; 79 struct pci_conf_state sc_pciconf; 80 pcireg_t sc_devact[2]; 81 }; 82 83 int piixpm_match(struct device *, struct cfdata *, void *); 84 void piixpm_attach(struct device *, struct device *, void *); 85 86 void piixpm_powerhook(int, void *); 87 88 int piixpm_i2c_acquire_bus(void *, int); 89 void piixpm_i2c_release_bus(void *, int); 90 int piixpm_i2c_exec(void *, i2c_op_t, i2c_addr_t, const void *, size_t, 91 void *, size_t, int); 92 93 int piixpm_intr(void *); 94 95 CFATTACH_DECL(piixpm, sizeof(struct piixpm_softc), 96 piixpm_match, piixpm_attach, NULL, NULL); 97 98 int 99 piixpm_match(struct device *parent, struct cfdata *match, void *aux) 100 { 101 struct pci_attach_args *pa; 102 103 pa = (struct pci_attach_args *)aux; 104 switch (PCI_VENDOR(pa->pa_id)) { 105 case PCI_VENDOR_INTEL: 106 switch (PCI_PRODUCT(pa->pa_id)) { 107 case PCI_PRODUCT_INTEL_82371AB_PMC: 108 case PCI_PRODUCT_INTEL_82440MX_PMC: 109 return 1; 110 } 111 break; 112 case PCI_VENDOR_ATI: 113 switch (PCI_PRODUCT(pa->pa_id)) { 114 case PCI_PRODUCT_ATI_SB200_SMB: 115 return 1; 116 } 117 break; 118 } 119 120 return 0; 121 } 122 123 void 124 piixpm_attach(struct device *parent, struct device *self, void *aux) 125 { 126 struct piixpm_softc *sc = (struct piixpm_softc *)self; 127 struct pci_attach_args *pa = aux; 128 struct i2cbus_attach_args iba; 129 pcireg_t base, conf; 130 #ifdef __HAVE_TIMECOUNTER 131 pcireg_t pmmisc; 132 #endif 133 pci_intr_handle_t ih; 134 const char *intrstr = NULL; 135 136 sc->sc_pc = pa->pa_pc; 137 sc->sc_pcitag = pa->pa_tag; 138 139 aprint_naive("\n"); 140 aprint_normal(": Power Management Controller\n"); 141 142 sc->sc_powerhook = powerhook_establish(piixpm_powerhook, sc); 143 if (sc->sc_powerhook == NULL) 144 aprint_error("%s: can't establish powerhook\n", 145 sc->sc_dev.dv_xname); 146 147 /* Read configuration */ 148 conf = pci_conf_read(pa->pa_pc, pa->pa_tag, PIIX_SMB_HOSTC); 149 DPRINTF((": conf 0x%x", conf)); 150 151 #ifdef __HAVE_TIMECOUNTER 152 if ((PCI_VENDOR(pa->pa_id) != PCI_VENDOR_INTEL) || 153 (PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_INTEL_82371AB_PMC)) 154 goto nopowermanagement; 155 156 /* check whether I/O access to PM regs is enabled */ 157 pmmisc = pci_conf_read(pa->pa_pc, pa->pa_tag, PIIX_PMREGMISC); 158 if (!(pmmisc & 1)) 159 goto nopowermanagement; 160 161 sc->sc_pm_iot = pa->pa_iot; 162 /* Map I/O space */ 163 base = pci_conf_read(pa->pa_pc, pa->pa_tag, PIIX_PM_BASE); 164 if (bus_space_map(sc->sc_pm_iot, PCI_MAPREG_IO_ADDR(base), 165 PIIX_PM_SIZE, 0, &sc->sc_pm_ioh)) { 166 aprint_error("%s: can't map power management I/O space\n", 167 sc->sc_dev.dv_xname); 168 goto nopowermanagement; 169 } 170 171 /* 172 * Revision 0 and 1 are PIIX4, 2 is PIIX4E, 3 is PIIX4M. 173 * PIIX4 and PIIX4E have a bug in the timer latch, see Errata #20 174 * in the "Specification update" (document #297738). 175 */ 176 acpipmtimer_attach(&sc->sc_dev, sc->sc_pm_iot, sc->sc_pm_ioh, 177 PIIX_PM_PMTMR, 178 (PCI_REVISION(pa->pa_class) < 3) ? ACPIPMT_BADLATCH : 0 ); 179 180 nopowermanagement: 181 #endif 182 183 if ((conf & PIIX_SMB_HOSTC_HSTEN) == 0) { 184 aprint_normal("%s: SMBus disabled\n", sc->sc_dev.dv_xname); 185 return; 186 } 187 188 /* Map I/O space */ 189 sc->sc_smb_iot = pa->pa_iot; 190 base = pci_conf_read(pa->pa_pc, pa->pa_tag, PIIX_SMB_BASE) & 0xffff; 191 if (bus_space_map(sc->sc_smb_iot, PCI_MAPREG_IO_ADDR(base), 192 PIIX_SMB_SIZE, 0, &sc->sc_smb_ioh)) { 193 aprint_error("%s: can't map smbus I/O space\n", 194 sc->sc_dev.dv_xname); 195 return; 196 } 197 198 sc->sc_poll = 1; 199 if ((conf & PIIX_SMB_HOSTC_INTMASK) == PIIX_SMB_HOSTC_SMI) { 200 /* No PCI IRQ */ 201 aprint_normal("%s: interrupting at SMI", sc->sc_dev.dv_xname); 202 } else if ((conf & PIIX_SMB_HOSTC_INTMASK) == PIIX_SMB_HOSTC_IRQ) { 203 /* Install interrupt handler */ 204 if (pci_intr_map(pa, &ih) == 0) { 205 intrstr = pci_intr_string(pa->pa_pc, ih); 206 sc->sc_smb_ih = pci_intr_establish(pa->pa_pc, ih, IPL_BIO, 207 piixpm_intr, sc); 208 if (sc->sc_smb_ih != NULL) { 209 aprint_normal("%s: interrupting at %s", 210 sc->sc_dev.dv_xname, intrstr); 211 sc->sc_poll = 0; 212 } 213 } 214 if (sc->sc_poll) 215 aprint_normal("%s: polling", sc->sc_dev.dv_xname); 216 } 217 218 aprint_normal("\n"); 219 220 /* Attach I2C bus */ 221 lockinit(&sc->sc_i2c_lock, PRIBIO | PCATCH, "iiclk", 0, 0); 222 sc->sc_i2c_tag.ic_cookie = sc; 223 sc->sc_i2c_tag.ic_acquire_bus = piixpm_i2c_acquire_bus; 224 sc->sc_i2c_tag.ic_release_bus = piixpm_i2c_release_bus; 225 sc->sc_i2c_tag.ic_exec = piixpm_i2c_exec; 226 227 bzero(&iba, sizeof(iba)); 228 iba.iba_name = "iic"; 229 iba.iba_tag = &sc->sc_i2c_tag; 230 config_found(self, &iba, iicbus_print); 231 232 return; 233 } 234 235 void 236 piixpm_powerhook(int why, void *cookie) 237 { 238 struct piixpm_softc *sc = cookie; 239 pci_chipset_tag_t pc = sc->sc_pc; 240 pcitag_t tag = sc->sc_pcitag; 241 242 switch (why) { 243 case PWR_SUSPEND: 244 pci_conf_capture(pc, tag, &sc->sc_pciconf); 245 sc->sc_devact[0] = pci_conf_read(pc, tag, PIIX_DEVACTA); 246 sc->sc_devact[1] = pci_conf_read(pc, tag, PIIX_DEVACTB); 247 break; 248 case PWR_RESUME: 249 pci_conf_restore(pc, tag, &sc->sc_pciconf); 250 pci_conf_write(pc, tag, PIIX_DEVACTA, sc->sc_devact[0]); 251 pci_conf_write(pc, tag, PIIX_DEVACTB, sc->sc_devact[1]); 252 break; 253 } 254 255 return; 256 } 257 258 int 259 piixpm_i2c_acquire_bus(void *cookie, int flags) 260 { 261 struct piixpm_softc *sc = cookie; 262 263 if (cold || sc->sc_poll || (flags & I2C_F_POLL)) 264 return (0); 265 266 return (lockmgr(&sc->sc_i2c_lock, LK_EXCLUSIVE, NULL)); 267 } 268 269 void 270 piixpm_i2c_release_bus(void *cookie, int flags) 271 { 272 struct piixpm_softc *sc = cookie; 273 274 if (cold || sc->sc_poll || (flags & I2C_F_POLL)) 275 return; 276 277 lockmgr(&sc->sc_i2c_lock, LK_RELEASE, NULL); 278 } 279 280 int 281 piixpm_i2c_exec(void *cookie, i2c_op_t op, i2c_addr_t addr, 282 const void *cmdbuf, size_t cmdlen, void *buf, size_t len, int flags) 283 { 284 struct piixpm_softc *sc = cookie; 285 const u_int8_t *b; 286 u_int8_t ctl = 0, st; 287 int retries; 288 289 DPRINTF(("%s: exec: op %d, addr 0x%x, cmdlen %d, len %d, flags 0x%x\n", 290 sc->sc_dev.dv_xname, op, addr, cmdlen, len, flags)); 291 292 /* Wait for bus to be idle */ 293 for (retries = 100; retries > 0; retries--) { 294 st = bus_space_read_1(sc->sc_smb_iot, sc->sc_smb_ioh, 295 PIIX_SMB_HS); 296 if (!(st & PIIX_SMB_HS_BUSY)) 297 break; 298 DELAY(PIIXPM_DELAY); 299 } 300 DPRINTF(("%s: exec: st 0x%b\n", sc->sc_dev.dv_xname, st, 301 PIIX_SMB_HS_BITS)); 302 if (st & PIIX_SMB_HS_BUSY) 303 return (1); 304 305 if (cold || sc->sc_poll) 306 flags |= I2C_F_POLL; 307 308 if (!I2C_OP_STOP_P(op) || cmdlen > 1 || len > 2) 309 return (1); 310 311 /* Setup transfer */ 312 sc->sc_i2c_xfer.op = op; 313 sc->sc_i2c_xfer.buf = buf; 314 sc->sc_i2c_xfer.len = len; 315 sc->sc_i2c_xfer.flags = flags; 316 sc->sc_i2c_xfer.error = 0; 317 318 /* Set slave address and transfer direction */ 319 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_TXSLVA, 320 PIIX_SMB_TXSLVA_ADDR(addr) | 321 (I2C_OP_READ_P(op) ? PIIX_SMB_TXSLVA_READ : 0)); 322 323 b = cmdbuf; 324 if (cmdlen > 0) 325 /* Set command byte */ 326 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, 327 PIIX_SMB_HCMD, b[0]); 328 329 if (I2C_OP_WRITE_P(op)) { 330 /* Write data */ 331 b = buf; 332 if (len > 0) 333 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, 334 PIIX_SMB_HD0, b[0]); 335 if (len > 1) 336 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, 337 PIIX_SMB_HD1, b[1]); 338 } 339 340 /* Set SMBus command */ 341 if (len == 0) 342 ctl = PIIX_SMB_HC_CMD_BYTE; 343 else if (len == 1) 344 ctl = PIIX_SMB_HC_CMD_BDATA; 345 else if (len == 2) 346 ctl = PIIX_SMB_HC_CMD_WDATA; 347 348 if ((flags & I2C_F_POLL) == 0) 349 ctl |= PIIX_SMB_HC_INTREN; 350 351 /* Start transaction */ 352 ctl |= PIIX_SMB_HC_START; 353 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_HC, ctl); 354 355 if (flags & I2C_F_POLL) { 356 /* Poll for completion */ 357 DELAY(PIIXPM_DELAY); 358 for (retries = 1000; retries > 0; retries--) { 359 st = bus_space_read_1(sc->sc_smb_iot, sc->sc_smb_ioh, 360 PIIX_SMB_HS); 361 if ((st & PIIX_SMB_HS_BUSY) == 0) 362 break; 363 DELAY(PIIXPM_DELAY); 364 } 365 if (st & PIIX_SMB_HS_BUSY) 366 goto timeout; 367 piixpm_intr(sc); 368 } else { 369 /* Wait for interrupt */ 370 if (tsleep(sc, PRIBIO, "iicexec", PIIXPM_TIMEOUT * hz)) 371 goto timeout; 372 } 373 374 if (sc->sc_i2c_xfer.error) 375 return (1); 376 377 return (0); 378 379 timeout: 380 /* 381 * Transfer timeout. Kill the transaction and clear status bits. 382 */ 383 aprint_error("%s: timeout, status 0x%x\n", sc->sc_dev.dv_xname, st); 384 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_HC, 385 PIIX_SMB_HC_KILL); 386 DELAY(PIIXPM_DELAY); 387 st = bus_space_read_1(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_HS); 388 if ((st & PIIX_SMB_HS_FAILED) == 0) 389 aprint_error("%s: transaction abort failed, status 0x%x\n", 390 sc->sc_dev.dv_xname, st); 391 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_HS, st); 392 return (1); 393 } 394 395 int 396 piixpm_intr(void *arg) 397 { 398 struct piixpm_softc *sc = arg; 399 u_int8_t st; 400 u_int8_t *b; 401 size_t len; 402 403 /* Read status */ 404 st = bus_space_read_1(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_HS); 405 if ((st & PIIX_SMB_HS_BUSY) != 0 || (st & (PIIX_SMB_HS_INTR | 406 PIIX_SMB_HS_DEVERR | PIIX_SMB_HS_BUSERR | 407 PIIX_SMB_HS_FAILED)) == 0) 408 /* Interrupt was not for us */ 409 return (0); 410 411 DPRINTF(("%s: intr st 0x%b\n", sc->sc_dev.dv_xname, st, 412 PIIX_SMB_HS_BITS)); 413 414 /* Clear status bits */ 415 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_HS, st); 416 417 /* Check for errors */ 418 if (st & (PIIX_SMB_HS_DEVERR | PIIX_SMB_HS_BUSERR | 419 PIIX_SMB_HS_FAILED)) { 420 sc->sc_i2c_xfer.error = 1; 421 goto done; 422 } 423 424 if (st & PIIX_SMB_HS_INTR) { 425 if (I2C_OP_WRITE_P(sc->sc_i2c_xfer.op)) 426 goto done; 427 428 /* Read data */ 429 b = sc->sc_i2c_xfer.buf; 430 len = sc->sc_i2c_xfer.len; 431 if (len > 0) 432 b[0] = bus_space_read_1(sc->sc_smb_iot, sc->sc_smb_ioh, 433 PIIX_SMB_HD0); 434 if (len > 1) 435 b[1] = bus_space_read_1(sc->sc_smb_iot, sc->sc_smb_ioh, 436 PIIX_SMB_HD1); 437 } 438 439 done: 440 if ((sc->sc_i2c_xfer.flags & I2C_F_POLL) == 0) 441 wakeup(sc); 442 return (1); 443 } 444
Indexes created Mon Sep 29 21:09:56 GMT 2025