piixpm.c revision 1.53
1 /* $NetBSD: piixpm.c,v 1.53 2019/07/12 03:57:50 msaitoh Exp $ */ 2 /* $OpenBSD: piixpm.c,v 1.35 2011/04/09 04:33:40 deraadt Exp $ */ 3 4 /* 5 * Copyright (c) 2005, 2006 Alexander Yurchenko <grange (at) openbsd.org> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 /* 21 * Intel PIIX and compatible Power Management controller driver. 22 */ 23 24 #include <sys/cdefs.h> 25 __KERNEL_RCSID(0, "$NetBSD: piixpm.c,v 1.53 2019/07/12 03:57:50 msaitoh Exp $"); 26 27 #include <sys/param.h> 28 #include <sys/systm.h> 29 #include <sys/device.h> 30 #include <sys/kernel.h> 31 #include <sys/mutex.h> 32 #include <sys/proc.h> 33 34 #include <sys/bus.h> 35 36 #include <dev/pci/pcidevs.h> 37 #include <dev/pci/pcireg.h> 38 #include <dev/pci/pcivar.h> 39 40 #include <dev/pci/piixpmreg.h> 41 42 #include <dev/i2c/i2cvar.h> 43 44 #include <dev/ic/acpipmtimer.h> 45 46 #ifdef PIIXPM_DEBUG 47 #define DPRINTF(x) printf x 48 #else 49 #define DPRINTF(x) 50 #endif 51 52 #define PIIXPM_IS_CSB5(id) \ 53 (PCI_VENDOR((id)) == PCI_VENDOR_SERVERWORKS && \ 54 PCI_PRODUCT((id)) == PCI_PRODUCT_SERVERWORKS_CSB5) 55 #define PIIXPM_DELAY 200 56 #define PIIXPM_TIMEOUT 1 57 58 struct piixpm_smbus { 59 int sda; 60 struct piixpm_softc *softc; 61 }; 62 63 struct piixpm_softc { 64 device_t sc_dev; 65 66 bus_space_tag_t sc_iot; 67 #define sc_pm_iot sc_iot 68 #define sc_smb_iot sc_iot 69 bus_space_handle_t sc_pm_ioh; 70 bus_space_handle_t sc_sb800_ioh; 71 bus_space_handle_t sc_smb_ioh; 72 void * sc_smb_ih; 73 int sc_poll; 74 75 pci_chipset_tag_t sc_pc; 76 pcitag_t sc_pcitag; 77 pcireg_t sc_id; 78 79 int sc_numbusses; 80 device_t sc_i2c_device[4]; 81 struct piixpm_smbus sc_busses[4]; 82 struct i2c_controller sc_i2c_tags[4]; 83 84 kmutex_t sc_i2c_mutex; 85 struct { 86 i2c_op_t op; 87 void * buf; 88 size_t len; 89 int flags; 90 volatile int error; 91 } sc_i2c_xfer; 92 93 pcireg_t sc_devact[2]; 94 }; 95 96 static int piixpm_match(device_t, cfdata_t, void *); 97 static void piixpm_attach(device_t, device_t, void *); 98 static int piixpm_rescan(device_t, const char *, const int *); 99 static void piixpm_chdet(device_t, device_t); 100 101 static bool piixpm_suspend(device_t, const pmf_qual_t *); 102 static bool piixpm_resume(device_t, const pmf_qual_t *); 103 104 static int piixpm_sb800_init(struct piixpm_softc *); 105 static void piixpm_csb5_reset(void *); 106 static int piixpm_i2c_acquire_bus(void *, int); 107 static void piixpm_i2c_release_bus(void *, int); 108 static int piixpm_i2c_exec(void *, i2c_op_t, i2c_addr_t, const void *, 109 size_t, void *, size_t, int); 110 111 static int piixpm_intr(void *); 112 113 CFATTACH_DECL3_NEW(piixpm, sizeof(struct piixpm_softc), 114 piixpm_match, piixpm_attach, NULL, NULL, piixpm_rescan, piixpm_chdet, 0); 115 116 static int 117 piixpm_match(device_t parent, cfdata_t match, void *aux) 118 { 119 struct pci_attach_args *pa; 120 121 pa = (struct pci_attach_args *)aux; 122 switch (PCI_VENDOR(pa->pa_id)) { 123 case PCI_VENDOR_INTEL: 124 switch (PCI_PRODUCT(pa->pa_id)) { 125 case PCI_PRODUCT_INTEL_82371AB_PMC: 126 case PCI_PRODUCT_INTEL_82440MX_PMC: 127 return 1; 128 } 129 break; 130 case PCI_VENDOR_ATI: 131 switch (PCI_PRODUCT(pa->pa_id)) { 132 case PCI_PRODUCT_ATI_SB200_SMB: 133 case PCI_PRODUCT_ATI_SB300_SMB: 134 case PCI_PRODUCT_ATI_SB400_SMB: 135 case PCI_PRODUCT_ATI_SB600_SMB: /* matches SB600/SB700/SB800 */ 136 return 1; 137 } 138 break; 139 case PCI_VENDOR_SERVERWORKS: 140 switch (PCI_PRODUCT(pa->pa_id)) { 141 case PCI_PRODUCT_SERVERWORKS_OSB4: 142 case PCI_PRODUCT_SERVERWORKS_CSB5: 143 case PCI_PRODUCT_SERVERWORKS_CSB6: 144 case PCI_PRODUCT_SERVERWORKS_HT1000SB: 145 case PCI_PRODUCT_SERVERWORKS_HT1100SB: 146 return 1; 147 } 148 break; 149 case PCI_VENDOR_AMD: 150 switch (PCI_PRODUCT(pa->pa_id)) { 151 case PCI_PRODUCT_AMD_HUDSON_SMB: 152 return 1; 153 } 154 break; 155 } 156 157 return 0; 158 } 159 160 static void 161 piixpm_attach(device_t parent, device_t self, void *aux) 162 { 163 struct piixpm_softc *sc = device_private(self); 164 struct pci_attach_args *pa = aux; 165 pcireg_t base, conf; 166 pcireg_t pmmisc; 167 pci_intr_handle_t ih; 168 const char *intrstr = NULL; 169 int i, flags; 170 char intrbuf[PCI_INTRSTR_LEN]; 171 172 sc->sc_dev = self; 173 sc->sc_iot = pa->pa_iot; 174 sc->sc_id = pa->pa_id; 175 sc->sc_pc = pa->pa_pc; 176 sc->sc_pcitag = pa->pa_tag; 177 sc->sc_numbusses = 1; 178 179 pci_aprint_devinfo(pa, NULL); 180 181 if (!pmf_device_register(self, piixpm_suspend, piixpm_resume)) 182 aprint_error_dev(self, "couldn't establish power handler\n"); 183 184 /* Read configuration */ 185 conf = pci_conf_read(pa->pa_pc, pa->pa_tag, PIIX_SMB_HOSTC); 186 DPRINTF(("%s: conf 0x%x\n", device_xname(self), conf)); 187 188 if ((PCI_VENDOR(pa->pa_id) != PCI_VENDOR_INTEL) || 189 (PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_INTEL_82371AB_PMC)) 190 goto nopowermanagement; 191 192 /* check whether I/O access to PM regs is enabled */ 193 pmmisc = pci_conf_read(pa->pa_pc, pa->pa_tag, PIIX_PMREGMISC); 194 if (!(pmmisc & 1)) 195 goto nopowermanagement; 196 197 /* Map I/O space */ 198 base = pci_conf_read(pa->pa_pc, pa->pa_tag, PIIX_PM_BASE); 199 if (base == 0 || bus_space_map(sc->sc_pm_iot, PCI_MAPREG_IO_ADDR(base), 200 PIIX_PM_SIZE, 0, &sc->sc_pm_ioh)) { 201 aprint_error_dev(self, 202 "can't map power management I/O space\n"); 203 goto nopowermanagement; 204 } 205 206 /* 207 * Revision 0 and 1 are PIIX4, 2 is PIIX4E, 3 is PIIX4M. 208 * PIIX4 and PIIX4E have a bug in the timer latch, see Errata #20 209 * in the "Specification update" (document #297738). 210 */ 211 acpipmtimer_attach(self, sc->sc_pm_iot, sc->sc_pm_ioh, 212 PIIX_PM_PMTMR, 213 (PCI_REVISION(pa->pa_class) < 3) ? ACPIPMT_BADLATCH : 0 ); 214 215 nopowermanagement: 216 217 /* SB800 rev 0x40+ and AMD HUDSON need special initialization */ 218 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_AMD && 219 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_AMD_HUDSON_SMB) { 220 if (piixpm_sb800_init(sc) == 0) { 221 goto attach_i2c; 222 } 223 aprint_normal_dev(self, "SMBus initialization failed\n"); 224 return; 225 } 226 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_ATI && 227 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_ATI_SB600_SMB && 228 PCI_REVISION(pa->pa_class) >= 0x40) { 229 if (piixpm_sb800_init(sc) == 0) { 230 sc->sc_numbusses = 4; 231 goto attach_i2c; 232 } 233 aprint_normal_dev(self, "SMBus initialization failed\n"); 234 return; 235 } 236 237 if ((conf & PIIX_SMB_HOSTC_HSTEN) == 0) { 238 aprint_normal_dev(self, "SMBus disabled\n"); 239 return; 240 } 241 242 /* Map I/O space */ 243 base = pci_conf_read(pa->pa_pc, pa->pa_tag, PIIX_SMB_BASE) & 0xffff; 244 if (bus_space_map(sc->sc_smb_iot, PCI_MAPREG_IO_ADDR(base), 245 PIIX_SMB_SIZE, 0, &sc->sc_smb_ioh)) { 246 aprint_error_dev(self, "can't map smbus I/O space\n"); 247 return; 248 } 249 250 sc->sc_poll = 1; 251 aprint_normal_dev(self, ""); 252 if ((conf & PIIX_SMB_HOSTC_INTMASK) == PIIX_SMB_HOSTC_SMI) { 253 /* No PCI IRQ */ 254 aprint_normal("interrupting at SMI, "); 255 } else { 256 if ((conf & PIIX_SMB_HOSTC_INTMASK) == PIIX_SMB_HOSTC_IRQ) { 257 /* Install interrupt handler */ 258 if (pci_intr_map(pa, &ih) == 0) { 259 intrstr = pci_intr_string(pa->pa_pc, ih, 260 intrbuf, sizeof(intrbuf)); 261 sc->sc_smb_ih = pci_intr_establish_xname( 262 pa->pa_pc, ih, IPL_BIO, piixpm_intr, 263 sc, device_xname(sc->sc_dev)); 264 if (sc->sc_smb_ih != NULL) { 265 aprint_normal("interrupting at %s", 266 intrstr); 267 sc->sc_poll = 0; 268 } 269 } 270 } 271 if (sc->sc_poll) 272 aprint_normal("polling"); 273 } 274 275 aprint_normal("\n"); 276 277 attach_i2c: 278 for (i = 0; i < sc->sc_numbusses; i++) 279 sc->sc_i2c_device[i] = NULL; 280 281 flags = 0; 282 mutex_init(&sc->sc_i2c_mutex, MUTEX_DEFAULT, IPL_NONE); 283 piixpm_rescan(self, "i2cbus", &flags); 284 } 285 286 static int 287 piixpm_rescan(device_t self, const char *ifattr, const int *flags) 288 { 289 struct piixpm_softc *sc = device_private(self); 290 struct i2cbus_attach_args iba; 291 int i; 292 293 if (!ifattr_match(ifattr, "i2cbus")) 294 return 0; 295 296 /* Attach I2C bus */ 297 298 for (i = 0; i < sc->sc_numbusses; i++) { 299 if (sc->sc_i2c_device[i]) 300 continue; 301 sc->sc_busses[i].sda = i; 302 sc->sc_busses[i].softc = sc; 303 sc->sc_i2c_tags[i].ic_cookie = &sc->sc_busses[i]; 304 sc->sc_i2c_tags[i].ic_acquire_bus = piixpm_i2c_acquire_bus; 305 sc->sc_i2c_tags[i].ic_release_bus = piixpm_i2c_release_bus; 306 sc->sc_i2c_tags[i].ic_exec = piixpm_i2c_exec; 307 memset(&iba, 0, sizeof(iba)); 308 iba.iba_type = I2C_TYPE_SMBUS; 309 iba.iba_tag = &sc->sc_i2c_tags[i]; 310 sc->sc_i2c_device[i] = config_found_ia(self, ifattr, &iba, 311 iicbus_print); 312 } 313 314 return 0; 315 } 316 317 static void 318 piixpm_chdet(device_t self, device_t child) 319 { 320 struct piixpm_softc *sc = device_private(self); 321 int i; 322 323 for (i = 0; i < sc->sc_numbusses; i++) { 324 if (sc->sc_i2c_device[i] == child) { 325 sc->sc_i2c_device[i] = NULL; 326 break; 327 } 328 } 329 } 330 331 332 static bool 333 piixpm_suspend(device_t dv, const pmf_qual_t *qual) 334 { 335 struct piixpm_softc *sc = device_private(dv); 336 337 sc->sc_devact[0] = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 338 PIIX_DEVACTA); 339 sc->sc_devact[1] = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 340 PIIX_DEVACTB); 341 342 return true; 343 } 344 345 static bool 346 piixpm_resume(device_t dv, const pmf_qual_t *qual) 347 { 348 struct piixpm_softc *sc = device_private(dv); 349 350 pci_conf_write(sc->sc_pc, sc->sc_pcitag, PIIX_DEVACTA, 351 sc->sc_devact[0]); 352 pci_conf_write(sc->sc_pc, sc->sc_pcitag, PIIX_DEVACTB, 353 sc->sc_devact[1]); 354 355 return true; 356 } 357 358 /* 359 * Extract SMBus base address from SB800 Power Management (PM) registers. 360 * The PM registers can be accessed either through indirect I/O (CD6/CD7) or 361 * direct mapping if AcpiMMioDecodeEn is enabled. Since this function is only 362 * called once it uses indirect I/O for simplicity. 363 */ 364 static int 365 piixpm_sb800_init(struct piixpm_softc *sc) 366 { 367 bus_space_tag_t iot = sc->sc_iot; 368 bus_space_handle_t ioh; /* indirect I/O handle */ 369 uint16_t val, base_addr; 370 371 /* Fetch SMB base address */ 372 if (bus_space_map(iot, 373 PIIXPM_INDIRECTIO_BASE, PIIXPM_INDIRECTIO_SIZE, 0, &ioh)) { 374 device_printf(sc->sc_dev, "couldn't map indirect I/O space\n"); 375 return EBUSY; 376 } 377 bus_space_write_1(iot, ioh, PIIXPM_INDIRECTIO_INDEX, 378 SB800_PM_SMBUS0EN_LO); 379 val = bus_space_read_1(iot, ioh, PIIXPM_INDIRECTIO_DATA); 380 bus_space_write_1(iot, ioh, PIIXPM_INDIRECTIO_INDEX, 381 SB800_PM_SMBUS0EN_HI); 382 val |= bus_space_read_1(iot, ioh, PIIXPM_INDIRECTIO_DATA) << 8; 383 sc->sc_sb800_ioh = ioh; 384 385 if ((val & SB800_PM_SMBUS0EN_ENABLE) == 0) 386 return ENOENT; 387 388 base_addr = val & SB800_PM_SMBUS0EN_BADDR; 389 390 aprint_debug_dev(sc->sc_dev, "SMBus @ 0x%04x\n", base_addr); 391 392 bus_space_write_1(iot, ioh, PIIXPM_INDIRECTIO_INDEX, 393 SB800_PM_SMBUS0SELEN); 394 bus_space_write_1(iot, ioh, PIIXPM_INDIRECTIO_DATA, 1); /* SMBUS0SEL */ 395 396 if (bus_space_map(iot, PCI_MAPREG_IO_ADDR(base_addr), 397 PIIX_SMB_SIZE, 0, &sc->sc_smb_ioh)) { 398 aprint_error_dev(sc->sc_dev, "can't map smbus I/O space\n"); 399 return EBUSY; 400 } 401 aprint_normal_dev(sc->sc_dev, "polling (SB800)\n"); 402 sc->sc_poll = 1; 403 404 return 0; 405 } 406 407 static void 408 piixpm_csb5_reset(void *arg) 409 { 410 struct piixpm_softc *sc = arg; 411 pcireg_t base, hostc, pmbase; 412 413 base = pci_conf_read(sc->sc_pc, sc->sc_pcitag, PIIX_SMB_BASE); 414 hostc = pci_conf_read(sc->sc_pc, sc->sc_pcitag, PIIX_SMB_HOSTC); 415 416 pmbase = pci_conf_read(sc->sc_pc, sc->sc_pcitag, PIIX_PM_BASE); 417 pmbase |= PIIX_PM_BASE_CSB5_RESET; 418 pci_conf_write(sc->sc_pc, sc->sc_pcitag, PIIX_PM_BASE, pmbase); 419 pmbase &= ~PIIX_PM_BASE_CSB5_RESET; 420 pci_conf_write(sc->sc_pc, sc->sc_pcitag, PIIX_PM_BASE, pmbase); 421 422 pci_conf_write(sc->sc_pc, sc->sc_pcitag, PIIX_SMB_BASE, base); 423 pci_conf_write(sc->sc_pc, sc->sc_pcitag, PIIX_SMB_HOSTC, hostc); 424 425 (void) tsleep(&sc, PRIBIO, "csb5reset", hz/2); 426 } 427 428 static int 429 piixpm_i2c_acquire_bus(void *cookie, int flags) 430 { 431 struct piixpm_smbus *smbus = cookie; 432 struct piixpm_softc *sc = smbus->softc; 433 434 if (!cold) 435 mutex_enter(&sc->sc_i2c_mutex); 436 437 if (smbus->sda > 0) /* SB800 */ 438 { 439 bus_space_write_1(sc->sc_iot, sc->sc_sb800_ioh, 440 PIIXPM_INDIRECTIO_INDEX, SB800_PM_SMBUS0SEL); 441 bus_space_write_1(sc->sc_iot, sc->sc_sb800_ioh, 442 PIIXPM_INDIRECTIO_DATA, smbus->sda << 1); 443 } 444 445 return 0; 446 } 447 448 static void 449 piixpm_i2c_release_bus(void *cookie, int flags) 450 { 451 struct piixpm_smbus *smbus = cookie; 452 struct piixpm_softc *sc = smbus->softc; 453 454 if (smbus->sda > 0) /* SB800 */ 455 { 456 /* 457 * HP Microserver hangs after reboot if not set to SDA0. 458 * Also add shutdown hook? 459 */ 460 bus_space_write_1(sc->sc_iot, sc->sc_sb800_ioh, 461 PIIXPM_INDIRECTIO_INDEX, SB800_PM_SMBUS0SEL); 462 bus_space_write_1(sc->sc_iot, sc->sc_sb800_ioh, 463 PIIXPM_INDIRECTIO_DATA, 0); 464 } 465 466 if (!cold) 467 mutex_exit(&sc->sc_i2c_mutex); 468 } 469 470 static int 471 piixpm_i2c_exec(void *cookie, i2c_op_t op, i2c_addr_t addr, 472 const void *cmdbuf, size_t cmdlen, void *buf, size_t len, int flags) 473 { 474 struct piixpm_smbus *smbus = cookie; 475 struct piixpm_softc *sc = smbus->softc; 476 const u_int8_t *b; 477 u_int8_t ctl = 0, st; 478 int retries; 479 480 DPRINTF(("%s: exec: op %d, addr 0x%02x, cmdlen %zu, len %zu, " 481 "flags 0x%x\n", 482 device_xname(sc->sc_dev), op, addr, cmdlen, len, flags)); 483 484 /* Clear status bits */ 485 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_HS, 486 PIIX_SMB_HS_INTR | PIIX_SMB_HS_DEVERR | 487 PIIX_SMB_HS_BUSERR | PIIX_SMB_HS_FAILED); 488 bus_space_barrier(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_HS, 1, 489 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 490 491 /* Wait for bus to be idle */ 492 for (retries = 100; retries > 0; retries--) { 493 st = bus_space_read_1(sc->sc_smb_iot, sc->sc_smb_ioh, 494 PIIX_SMB_HS); 495 if (!(st & PIIX_SMB_HS_BUSY)) 496 break; 497 DELAY(PIIXPM_DELAY); 498 } 499 DPRINTF(("%s: exec: st %#x\n", device_xname(sc->sc_dev), st & 0xff)); 500 if (st & PIIX_SMB_HS_BUSY) 501 return (1); 502 503 if (cold || sc->sc_poll) 504 flags |= I2C_F_POLL; 505 506 if (!I2C_OP_STOP_P(op) || cmdlen > 1 || len > 2 || 507 (cmdlen == 0 && len > 1)) 508 return (1); 509 510 /* Setup transfer */ 511 sc->sc_i2c_xfer.op = op; 512 sc->sc_i2c_xfer.buf = buf; 513 sc->sc_i2c_xfer.len = len; 514 sc->sc_i2c_xfer.flags = flags; 515 sc->sc_i2c_xfer.error = 0; 516 517 /* Set slave address and transfer direction */ 518 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_TXSLVA, 519 PIIX_SMB_TXSLVA_ADDR(addr) | 520 (I2C_OP_READ_P(op) ? PIIX_SMB_TXSLVA_READ : 0)); 521 522 b = cmdbuf; 523 if (cmdlen > 0) 524 /* Set command byte */ 525 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, 526 PIIX_SMB_HCMD, b[0]); 527 528 if (I2C_OP_WRITE_P(op)) { 529 /* Write data */ 530 b = buf; 531 if (cmdlen == 0 && len == 1) 532 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, 533 PIIX_SMB_HCMD, b[0]); 534 else if (len > 0) 535 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, 536 PIIX_SMB_HD0, b[0]); 537 if (len > 1) 538 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, 539 PIIX_SMB_HD1, b[1]); 540 } 541 542 /* Set SMBus command */ 543 if (cmdlen == 0) { 544 if (len == 0) 545 ctl = PIIX_SMB_HC_CMD_QUICK; 546 else 547 ctl = PIIX_SMB_HC_CMD_BYTE; 548 } else if (len == 1) 549 ctl = PIIX_SMB_HC_CMD_BDATA; 550 else if (len == 2) 551 ctl = PIIX_SMB_HC_CMD_WDATA; 552 553 if ((flags & I2C_F_POLL) == 0) 554 ctl |= PIIX_SMB_HC_INTREN; 555 556 /* Start transaction */ 557 ctl |= PIIX_SMB_HC_START; 558 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_HC, ctl); 559 560 if (flags & I2C_F_POLL) { 561 /* Poll for completion */ 562 if (PIIXPM_IS_CSB5(sc->sc_id)) 563 DELAY(2*PIIXPM_DELAY); 564 else 565 DELAY(PIIXPM_DELAY); 566 for (retries = 1000; retries > 0; retries--) { 567 st = bus_space_read_1(sc->sc_smb_iot, sc->sc_smb_ioh, 568 PIIX_SMB_HS); 569 if ((st & PIIX_SMB_HS_BUSY) == 0) 570 break; 571 DELAY(PIIXPM_DELAY); 572 } 573 if (st & PIIX_SMB_HS_BUSY) 574 goto timeout; 575 piixpm_intr(sc); 576 } else { 577 /* Wait for interrupt */ 578 if (tsleep(sc, PRIBIO, "piixpm", PIIXPM_TIMEOUT * hz)) 579 goto timeout; 580 } 581 582 if (sc->sc_i2c_xfer.error) 583 return (1); 584 585 return (0); 586 587 timeout: 588 /* 589 * Transfer timeout. Kill the transaction and clear status bits. 590 */ 591 aprint_error_dev(sc->sc_dev, "timeout, status 0x%x\n", st); 592 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_HC, 593 PIIX_SMB_HC_KILL); 594 DELAY(PIIXPM_DELAY); 595 st = bus_space_read_1(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_HS); 596 if ((st & PIIX_SMB_HS_FAILED) == 0) 597 aprint_error_dev(sc->sc_dev, 598 "transaction abort failed, status 0x%x\n", st); 599 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_HS, st); 600 /* 601 * CSB5 needs hard reset to unlock the smbus after timeout. 602 */ 603 if (PIIXPM_IS_CSB5(sc->sc_id)) 604 piixpm_csb5_reset(sc); 605 return (1); 606 } 607 608 static int 609 piixpm_intr(void *arg) 610 { 611 struct piixpm_softc *sc = arg; 612 u_int8_t st; 613 u_int8_t *b; 614 size_t len; 615 616 /* Read status */ 617 st = bus_space_read_1(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_HS); 618 if ((st & PIIX_SMB_HS_BUSY) != 0 || (st & (PIIX_SMB_HS_INTR | 619 PIIX_SMB_HS_DEVERR | PIIX_SMB_HS_BUSERR | 620 PIIX_SMB_HS_FAILED)) == 0) 621 /* Interrupt was not for us */ 622 return (0); 623 624 DPRINTF(("%s: intr st %#x\n", device_xname(sc->sc_dev), st & 0xff)); 625 626 /* Clear status bits */ 627 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_HS, st); 628 629 /* Check for errors */ 630 if (st & (PIIX_SMB_HS_DEVERR | PIIX_SMB_HS_BUSERR | 631 PIIX_SMB_HS_FAILED)) { 632 sc->sc_i2c_xfer.error = 1; 633 goto done; 634 } 635 636 if (st & PIIX_SMB_HS_INTR) { 637 if (I2C_OP_WRITE_P(sc->sc_i2c_xfer.op)) 638 goto done; 639 640 /* Read data */ 641 b = sc->sc_i2c_xfer.buf; 642 len = sc->sc_i2c_xfer.len; 643 if (len > 0) 644 b[0] = bus_space_read_1(sc->sc_smb_iot, sc->sc_smb_ioh, 645 PIIX_SMB_HD0); 646 if (len > 1) 647 b[1] = bus_space_read_1(sc->sc_smb_iot, sc->sc_smb_ioh, 648 PIIX_SMB_HD1); 649 } 650 651 done: 652 if ((sc->sc_i2c_xfer.flags & I2C_F_POLL) == 0) 653 wakeup(sc); 654 return (1); 655 } 656
Indexes created Mon Sep 29 21:09:56 GMT 2025