piixpm.c revision 1.54.2.2
1 /* $NetBSD: piixpm.c,v 1.54.2.2 2021/11/30 11:44:39 martin Exp $ */ 2 /* $OpenBSD: piixpm.c,v 1.39 2013/10/01 20:06:02 sf Exp $ */ 3 4 /* 5 * Copyright (c) 2005, 2006 Alexander Yurchenko <grange (at) openbsd.org> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 /* 21 * Intel PIIX and compatible Power Management controller driver. 22 */ 23 24 #include <sys/cdefs.h> 25 __KERNEL_RCSID(0, "$NetBSD: piixpm.c,v 1.54.2.2 2021/11/30 11:44:39 martin Exp $"); 26 27 #include <sys/param.h> 28 #include <sys/systm.h> 29 #include <sys/device.h> 30 #include <sys/kernel.h> 31 #include <sys/mutex.h> 32 #include <sys/proc.h> 33 34 #include <sys/bus.h> 35 36 #include <dev/pci/pcidevs.h> 37 #include <dev/pci/pcireg.h> 38 #include <dev/pci/pcivar.h> 39 40 #include <dev/pci/piixpmreg.h> 41 42 #include <dev/i2c/i2cvar.h> 43 44 #include <dev/ic/acpipmtimer.h> 45 46 #ifdef PIIXPM_DEBUG 47 #define DPRINTF(x) printf x 48 #else 49 #define DPRINTF(x) 50 #endif 51 52 #define PIIXPM_IS_CSB5(sc) \ 53 (PCI_VENDOR((sc)->sc_id) == PCI_VENDOR_SERVERWORKS && \ 54 PCI_PRODUCT((sc)->sc_id) == PCI_PRODUCT_SERVERWORKS_CSB5) 55 #define PIIXPM_DELAY 200 56 #define PIIXPM_TIMEOUT 1 57 58 #define PIIXPM_IS_SB800GRP(sc) \ 59 ((PCI_VENDOR((sc)->sc_id) == PCI_VENDOR_ATI) && \ 60 ((PCI_PRODUCT((sc)->sc_id) == PCI_PRODUCT_ATI_SB600_SMB) && \ 61 ((sc)->sc_rev >= 0x40))) 62 63 #define PIIXPM_IS_HUDSON(sc) \ 64 ((PCI_VENDOR((sc)->sc_id) == PCI_VENDOR_AMD) && \ 65 (PCI_PRODUCT((sc)->sc_id) == PCI_PRODUCT_AMD_HUDSON_SMB)) 66 67 #define PIIXPM_IS_KERNCZ(sc) \ 68 ((PCI_VENDOR((sc)->sc_id) == PCI_VENDOR_AMD) && \ 69 (PCI_PRODUCT((sc)->sc_id) == PCI_PRODUCT_AMD_KERNCZ_SMB)) 70 71 #define PIIXPM_IS_FCHGRP(sc) (PIIXPM_IS_HUDSON(sc) || PIIXPM_IS_KERNCZ(sc)) 72 73 #define PIIX_SB800_TIMEOUT 500 74 75 struct piixpm_smbus { 76 int sda; 77 int sda_save; 78 struct piixpm_softc *softc; 79 }; 80 81 struct piixpm_softc { 82 device_t sc_dev; 83 84 bus_space_tag_t sc_iot; 85 #define sc_pm_iot sc_iot 86 #define sc_smb_iot sc_iot 87 bus_space_handle_t sc_pm_ioh; 88 bus_space_handle_t sc_sb800_ioh; 89 bus_space_handle_t sc_smb_ioh; 90 void * sc_smb_ih; 91 int sc_poll; 92 bool sc_sb800_selen; /* Use SMBUS0SEL */ 93 94 pci_chipset_tag_t sc_pc; 95 pcitag_t sc_pcitag; 96 pcireg_t sc_id; 97 pcireg_t sc_rev; 98 99 int sc_numbusses; 100 device_t sc_i2c_device[4]; 101 struct piixpm_smbus sc_busses[4]; 102 struct i2c_controller sc_i2c_tags[4]; 103 104 kmutex_t sc_i2c_mutex; 105 struct { 106 i2c_op_t op; 107 void * buf; 108 size_t len; 109 int flags; 110 volatile int error; 111 } sc_i2c_xfer; 112 113 pcireg_t sc_devact[2]; 114 }; 115 116 static int piixpm_match(device_t, cfdata_t, void *); 117 static void piixpm_attach(device_t, device_t, void *); 118 static int piixpm_rescan(device_t, const char *, const int *); 119 static void piixpm_chdet(device_t, device_t); 120 121 static bool piixpm_suspend(device_t, const pmf_qual_t *); 122 static bool piixpm_resume(device_t, const pmf_qual_t *); 123 124 static int piixpm_sb800_init(struct piixpm_softc *); 125 static void piixpm_csb5_reset(void *); 126 static int piixpm_i2c_sb600_acquire_bus(void *, int); 127 static void piixpm_i2c_sb600_release_bus(void *, int); 128 static int piixpm_i2c_sb800_acquire_bus(void *, int); 129 static void piixpm_i2c_sb800_release_bus(void *, int); 130 static int piixpm_i2c_exec(void *, i2c_op_t, i2c_addr_t, const void *, 131 size_t, void *, size_t, int); 132 133 static int piixpm_intr(void *); 134 135 CFATTACH_DECL3_NEW(piixpm, sizeof(struct piixpm_softc), 136 piixpm_match, piixpm_attach, NULL, NULL, piixpm_rescan, piixpm_chdet, 0); 137 138 static int 139 piixpm_match(device_t parent, cfdata_t match, void *aux) 140 { 141 struct pci_attach_args *pa; 142 143 pa = (struct pci_attach_args *)aux; 144 switch (PCI_VENDOR(pa->pa_id)) { 145 case PCI_VENDOR_INTEL: 146 switch (PCI_PRODUCT(pa->pa_id)) { 147 case PCI_PRODUCT_INTEL_82371AB_PMC: 148 case PCI_PRODUCT_INTEL_82440MX_PMC: 149 return 1; 150 } 151 break; 152 case PCI_VENDOR_ATI: 153 switch (PCI_PRODUCT(pa->pa_id)) { 154 case PCI_PRODUCT_ATI_SB200_SMB: 155 case PCI_PRODUCT_ATI_SB300_SMB: 156 case PCI_PRODUCT_ATI_SB400_SMB: 157 case PCI_PRODUCT_ATI_SB600_SMB: /* matches SB600/SB700/SB800 */ 158 return 1; 159 } 160 break; 161 case PCI_VENDOR_SERVERWORKS: 162 switch (PCI_PRODUCT(pa->pa_id)) { 163 case PCI_PRODUCT_SERVERWORKS_OSB4: 164 case PCI_PRODUCT_SERVERWORKS_CSB5: 165 case PCI_PRODUCT_SERVERWORKS_CSB6: 166 case PCI_PRODUCT_SERVERWORKS_HT1000SB: 167 case PCI_PRODUCT_SERVERWORKS_HT1100SB: 168 return 1; 169 } 170 break; 171 case PCI_VENDOR_AMD: 172 switch (PCI_PRODUCT(pa->pa_id)) { 173 case PCI_PRODUCT_AMD_HUDSON_SMB: 174 case PCI_PRODUCT_AMD_KERNCZ_SMB: 175 return 1; 176 } 177 break; 178 } 179 180 return 0; 181 } 182 183 static void 184 piixpm_attach(device_t parent, device_t self, void *aux) 185 { 186 struct piixpm_softc *sc = device_private(self); 187 struct pci_attach_args *pa = aux; 188 pcireg_t base, conf; 189 pcireg_t pmmisc; 190 pci_intr_handle_t ih; 191 bool usesmi = false; 192 const char *intrstr = NULL; 193 int i, flags; 194 char intrbuf[PCI_INTRSTR_LEN]; 195 196 sc->sc_dev = self; 197 sc->sc_iot = pa->pa_iot; 198 sc->sc_id = pa->pa_id; 199 sc->sc_rev = PCI_REVISION(pa->pa_class); 200 sc->sc_pc = pa->pa_pc; 201 sc->sc_pcitag = pa->pa_tag; 202 sc->sc_numbusses = 1; 203 204 pci_aprint_devinfo(pa, NULL); 205 206 if (!pmf_device_register(self, piixpm_suspend, piixpm_resume)) 207 aprint_error_dev(self, "couldn't establish power handler\n"); 208 209 if ((PCI_VENDOR(pa->pa_id) != PCI_VENDOR_INTEL) || 210 (PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_INTEL_82371AB_PMC)) 211 goto nopowermanagement; 212 213 /* check whether I/O access to PM regs is enabled */ 214 pmmisc = pci_conf_read(pa->pa_pc, pa->pa_tag, PIIX_PMREGMISC); 215 if (!(pmmisc & 1)) 216 goto nopowermanagement; 217 218 /* Map I/O space */ 219 base = pci_conf_read(pa->pa_pc, pa->pa_tag, PIIX_PM_BASE); 220 if (base == 0 || bus_space_map(sc->sc_pm_iot, PCI_MAPREG_IO_ADDR(base), 221 PIIX_PM_SIZE, 0, &sc->sc_pm_ioh)) { 222 aprint_error_dev(self, 223 "can't map power management I/O space\n"); 224 goto nopowermanagement; 225 } 226 227 /* 228 * Revision 0 and 1 are PIIX4, 2 is PIIX4E, 3 is PIIX4M. 229 * PIIX4 and PIIX4E have a bug in the timer latch, see Errata #20 230 * in the "Specification update" (document #297738). 231 */ 232 acpipmtimer_attach(self, sc->sc_pm_iot, sc->sc_pm_ioh, PIIX_PM_PMTMR, 233 (PCI_REVISION(pa->pa_class) < 3) ? ACPIPMT_BADLATCH : 0); 234 235 nopowermanagement: 236 237 /* SB800 rev 0x40+, AMD HUDSON and newer need special initialization */ 238 if (PIIXPM_IS_FCHGRP(sc) || PIIXPM_IS_SB800GRP(sc)) { 239 if (piixpm_sb800_init(sc) == 0) { 240 /* Read configuration */ 241 conf = bus_space_read_1(sc->sc_iot, 242 sc->sc_smb_ioh, SB800_SMB_HOSTC); 243 usesmi = ((conf & SB800_SMB_HOSTC_IRQ) == 0); 244 goto setintr; 245 } 246 aprint_normal_dev(self, "SMBus initialization failed\n"); 247 return; 248 } 249 250 /* Read configuration */ 251 conf = pci_conf_read(pa->pa_pc, pa->pa_tag, PIIX_SMB_HOSTC); 252 DPRINTF(("%s: conf 0x%08x\n", device_xname(self), conf)); 253 254 if ((conf & PIIX_SMB_HOSTC_HSTEN) == 0) { 255 aprint_normal_dev(self, "SMBus disabled\n"); 256 return; 257 } 258 usesmi = (conf & PIIX_SMB_HOSTC_INTMASK) == PIIX_SMB_HOSTC_SMI; 259 260 /* Map I/O space */ 261 base = pci_conf_read(pa->pa_pc, pa->pa_tag, PIIX_SMB_BASE) & 0xffff; 262 if (base == 0 || 263 bus_space_map(sc->sc_smb_iot, PCI_MAPREG_IO_ADDR(base), 264 PIIX_SMB_SIZE, 0, &sc->sc_smb_ioh)) { 265 aprint_error_dev(self, "can't map smbus I/O space\n"); 266 return; 267 } 268 269 setintr: 270 sc->sc_poll = 1; 271 aprint_normal_dev(self, ""); 272 if (usesmi) { 273 /* No PCI IRQ */ 274 aprint_normal("interrupting at SMI, "); 275 } else { 276 if ((conf & PIIX_SMB_HOSTC_INTMASK) == PIIX_SMB_HOSTC_IRQ) { 277 /* Install interrupt handler */ 278 if (pci_intr_map(pa, &ih) == 0) { 279 intrstr = pci_intr_string(pa->pa_pc, ih, 280 intrbuf, sizeof(intrbuf)); 281 sc->sc_smb_ih = pci_intr_establish_xname( 282 pa->pa_pc, ih, IPL_BIO, piixpm_intr, 283 sc, device_xname(sc->sc_dev)); 284 if (sc->sc_smb_ih != NULL) { 285 aprint_normal("interrupting at %s", 286 intrstr); 287 sc->sc_poll = 0; 288 } 289 } 290 } 291 if (sc->sc_poll) 292 aprint_normal("polling"); 293 } 294 295 aprint_normal("\n"); 296 297 for (i = 0; i < sc->sc_numbusses; i++) 298 sc->sc_i2c_device[i] = NULL; 299 300 flags = 0; 301 mutex_init(&sc->sc_i2c_mutex, MUTEX_DEFAULT, IPL_NONE); 302 piixpm_rescan(self, "i2cbus", &flags); 303 } 304 305 static int 306 piixpm_iicbus_print(void *aux, const char *pnp) 307 { 308 struct i2cbus_attach_args *iba = aux; 309 struct i2c_controller *tag = iba->iba_tag; 310 struct piixpm_smbus *bus = tag->ic_cookie; 311 struct piixpm_softc *sc = bus->softc; 312 313 iicbus_print(aux, pnp); 314 if (sc->sc_numbusses != 0) 315 aprint_normal(" port %d", bus->sda); 316 317 return UNCONF; 318 } 319 static int 320 piixpm_rescan(device_t self, const char *ifattr, const int *flags) 321 { 322 struct piixpm_softc *sc = device_private(self); 323 struct i2cbus_attach_args iba; 324 int i; 325 326 if (!ifattr_match(ifattr, "i2cbus")) 327 return 0; 328 329 /* Attach I2C bus */ 330 331 for (i = 0; i < sc->sc_numbusses; i++) { 332 struct i2c_controller *tag = &sc->sc_i2c_tags[i]; 333 334 if (sc->sc_i2c_device[i]) 335 continue; 336 sc->sc_busses[i].sda = i; 337 sc->sc_busses[i].softc = sc; 338 tag->ic_cookie = &sc->sc_busses[i]; 339 if (PIIXPM_IS_SB800GRP(sc) || PIIXPM_IS_FCHGRP(sc)) { 340 tag->ic_acquire_bus = piixpm_i2c_sb800_acquire_bus; 341 tag->ic_release_bus = piixpm_i2c_sb800_release_bus; 342 } else { 343 tag->ic_acquire_bus = piixpm_i2c_sb600_acquire_bus; 344 tag->ic_release_bus = piixpm_i2c_sb600_release_bus; 345 } 346 tag->ic_exec = piixpm_i2c_exec; 347 memset(&iba, 0, sizeof(iba)); 348 iba.iba_type = I2C_TYPE_SMBUS; 349 iba.iba_tag = tag; 350 sc->sc_i2c_device[i] = config_found_ia(self, ifattr, &iba, 351 piixpm_iicbus_print); 352 } 353 354 return 0; 355 } 356 357 static void 358 piixpm_chdet(device_t self, device_t child) 359 { 360 struct piixpm_softc *sc = device_private(self); 361 int i; 362 363 for (i = 0; i < sc->sc_numbusses; i++) { 364 if (sc->sc_i2c_device[i] == child) { 365 sc->sc_i2c_device[i] = NULL; 366 break; 367 } 368 } 369 } 370 371 372 static bool 373 piixpm_suspend(device_t dv, const pmf_qual_t *qual) 374 { 375 struct piixpm_softc *sc = device_private(dv); 376 377 sc->sc_devact[0] = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 378 PIIX_DEVACTA); 379 sc->sc_devact[1] = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 380 PIIX_DEVACTB); 381 382 return true; 383 } 384 385 static bool 386 piixpm_resume(device_t dv, const pmf_qual_t *qual) 387 { 388 struct piixpm_softc *sc = device_private(dv); 389 390 pci_conf_write(sc->sc_pc, sc->sc_pcitag, PIIX_DEVACTA, 391 sc->sc_devact[0]); 392 pci_conf_write(sc->sc_pc, sc->sc_pcitag, PIIX_DEVACTB, 393 sc->sc_devact[1]); 394 395 return true; 396 } 397 398 /* 399 * Extract SMBus base address from SB800 Power Management (PM) registers. 400 * The PM registers can be accessed either through indirect I/O (CD6/CD7) or 401 * direct mapping if AcpiMMioDecodeEn is enabled. Since this function is only 402 * called once it uses indirect I/O for simplicity. 403 */ 404 static int 405 piixpm_sb800_init(struct piixpm_softc *sc) 406 { 407 bus_space_tag_t iot = sc->sc_iot; 408 bus_space_handle_t ioh; /* indirect I/O handle */ 409 uint16_t val, base_addr; 410 bool enabled; 411 412 if (PIIXPM_IS_KERNCZ(sc) || 413 (PIIXPM_IS_HUDSON(sc) && (sc->sc_rev >= 0x1f))) 414 sc->sc_numbusses = 2; 415 else 416 sc->sc_numbusses = 4; 417 418 /* Fetch SMB base address */ 419 if (bus_space_map(iot, 420 SB800_INDIRECTIO_BASE, SB800_INDIRECTIO_SIZE, 0, &ioh)) { 421 device_printf(sc->sc_dev, "couldn't map indirect I/O space\n"); 422 return EBUSY; 423 } 424 if (PIIXPM_IS_FCHGRP(sc)) { 425 bus_space_write_1(iot, ioh, SB800_INDIRECTIO_INDEX, 426 AMDFCH41_PM_DECODE_EN0); 427 val = bus_space_read_1(iot, ioh, SB800_INDIRECTIO_DATA); 428 enabled = val & AMDFCH41_SMBUS_EN; 429 if (!enabled) 430 return ENOENT; 431 432 bus_space_write_1(iot, ioh, SB800_INDIRECTIO_INDEX, 433 AMDFCH41_PM_DECODE_EN1); 434 val = bus_space_read_1(iot, ioh, SB800_INDIRECTIO_DATA) << 8; 435 base_addr = val; 436 } else { 437 uint8_t data; 438 439 bus_space_write_1(iot, ioh, SB800_INDIRECTIO_INDEX, 440 SB800_PM_SMBUS0EN_LO); 441 val = bus_space_read_1(iot, ioh, SB800_INDIRECTIO_DATA); 442 enabled = val & SB800_PM_SMBUS0EN_ENABLE; 443 if (!enabled) 444 return ENOENT; 445 446 bus_space_write_1(iot, ioh, SB800_INDIRECTIO_INDEX, 447 SB800_PM_SMBUS0EN_HI); 448 val |= bus_space_read_1(iot, ioh, SB800_INDIRECTIO_DATA) << 8; 449 base_addr = val & SB800_PM_SMBUS0EN_BADDR; 450 451 bus_space_write_1(iot, ioh, SB800_INDIRECTIO_INDEX, 452 SB800_PM_SMBUS0SELEN); 453 data = bus_space_read_1(iot, ioh, SB800_INDIRECTIO_DATA); 454 if ((data & SB800_PM_USE_SMBUS0SEL) != 0) 455 sc->sc_sb800_selen = true; 456 } 457 458 sc->sc_sb800_ioh = ioh; 459 aprint_debug_dev(sc->sc_dev, "SMBus @ 0x%04x\n", base_addr); 460 461 if (bus_space_map(iot, PCI_MAPREG_IO_ADDR(base_addr), 462 SB800_SMB_SIZE, 0, &sc->sc_smb_ioh)) { 463 aprint_error_dev(sc->sc_dev, "can't map smbus I/O space\n"); 464 return EBUSY; 465 } 466 467 return 0; 468 } 469 470 static void 471 piixpm_csb5_reset(void *arg) 472 { 473 struct piixpm_softc *sc = arg; 474 pcireg_t base, hostc, pmbase; 475 476 base = pci_conf_read(sc->sc_pc, sc->sc_pcitag, PIIX_SMB_BASE); 477 hostc = pci_conf_read(sc->sc_pc, sc->sc_pcitag, PIIX_SMB_HOSTC); 478 479 pmbase = pci_conf_read(sc->sc_pc, sc->sc_pcitag, PIIX_PM_BASE); 480 pmbase |= PIIX_PM_BASE_CSB5_RESET; 481 pci_conf_write(sc->sc_pc, sc->sc_pcitag, PIIX_PM_BASE, pmbase); 482 pmbase &= ~PIIX_PM_BASE_CSB5_RESET; 483 pci_conf_write(sc->sc_pc, sc->sc_pcitag, PIIX_PM_BASE, pmbase); 484 485 pci_conf_write(sc->sc_pc, sc->sc_pcitag, PIIX_SMB_BASE, base); 486 pci_conf_write(sc->sc_pc, sc->sc_pcitag, PIIX_SMB_HOSTC, hostc); 487 488 (void) tsleep(&sc, PRIBIO, "csb5reset", hz/2); 489 } 490 491 static int 492 piixpm_i2c_sb600_acquire_bus(void *cookie, int flags) 493 { 494 struct piixpm_smbus *smbus = cookie; 495 struct piixpm_softc *sc = smbus->softc; 496 497 if (!cold) 498 mutex_enter(&sc->sc_i2c_mutex); 499 500 return 0; 501 } 502 503 static void 504 piixpm_i2c_sb600_release_bus(void *cookie, int flags) 505 { 506 struct piixpm_smbus *smbus = cookie; 507 struct piixpm_softc *sc = smbus->softc; 508 509 if (!cold) 510 mutex_exit(&sc->sc_i2c_mutex); 511 } 512 513 static int 514 piixpm_i2c_sb800_acquire_bus(void *cookie, int flags) 515 { 516 struct piixpm_smbus *smbus = cookie; 517 struct piixpm_softc *sc = smbus->softc; 518 uint8_t sctl, old_sda, index, mask, reg; 519 int i; 520 521 522 if (!cold) 523 mutex_enter(&sc->sc_i2c_mutex); 524 525 sctl = bus_space_read_1(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_SC); 526 for (i = 0; i < PIIX_SB800_TIMEOUT; i++) { 527 /* Try to acquire the host semaphore */ 528 sctl &= ~PIIX_SMB_SC_SEMMASK; 529 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_SC, 530 sctl | PIIX_SMB_SC_HOSTSEM); 531 532 sctl = bus_space_read_1(sc->sc_smb_iot, sc->sc_smb_ioh, 533 PIIX_SMB_SC); 534 if ((sctl & PIIX_SMB_SC_HOSTSEM) != 0) 535 break; 536 537 delay(1000); 538 } 539 if (i >= PIIX_SB800_TIMEOUT) { 540 device_printf(sc->sc_dev, 541 "Failed to acquire the host semaphore\n"); 542 return -1; 543 } 544 545 if (PIIXPM_IS_KERNCZ(sc) || 546 (PIIXPM_IS_HUDSON(sc) && (sc->sc_rev >= 0x1f))) { 547 index = AMDFCH41_PM_PORT_INDEX; 548 mask = AMDFCH41_SMBUS_PORTMASK; 549 } else if (sc->sc_sb800_selen) { 550 index = SB800_PM_SMBUS0SEL; 551 mask = SB800_PM_SMBUS0_MASK_E; 552 } else { 553 index = SB800_PM_SMBUS0EN_LO; 554 mask = SB800_PM_SMBUS0_MASK_C; 555 } 556 557 bus_space_write_1(sc->sc_iot, sc->sc_sb800_ioh, 558 SB800_INDIRECTIO_INDEX, index); 559 reg = bus_space_read_1(sc->sc_iot, sc->sc_sb800_ioh, 560 SB800_INDIRECTIO_DATA); 561 562 old_sda = __SHIFTOUT(reg, mask); 563 if (smbus->sda != old_sda) { 564 reg &= ~mask; 565 reg |= __SHIFTIN(smbus->sda, mask); 566 bus_space_write_1(sc->sc_iot, sc->sc_sb800_ioh, 567 SB800_INDIRECTIO_DATA, reg); 568 } 569 570 /* Save the old port number */ 571 smbus->sda_save = old_sda; 572 573 return 0; 574 } 575 576 static void 577 piixpm_i2c_sb800_release_bus(void *cookie, int flags) 578 { 579 struct piixpm_smbus *smbus = cookie; 580 struct piixpm_softc *sc = smbus->softc; 581 uint8_t sctl, index, mask, reg; 582 583 if (PIIXPM_IS_KERNCZ(sc) || 584 (PIIXPM_IS_HUDSON(sc) && (sc->sc_rev >= 0x1f))) { 585 index = AMDFCH41_PM_PORT_INDEX; 586 mask = AMDFCH41_SMBUS_PORTMASK; 587 } else if (sc->sc_sb800_selen) { 588 index = SB800_PM_SMBUS0SEL; 589 mask = SB800_PM_SMBUS0_MASK_E; 590 } else { 591 index = SB800_PM_SMBUS0EN_LO; 592 mask = SB800_PM_SMBUS0_MASK_C; 593 } 594 595 bus_space_write_1(sc->sc_iot, sc->sc_sb800_ioh, 596 SB800_INDIRECTIO_INDEX, index); 597 if (smbus->sda != smbus->sda_save) { 598 /* Restore the port number */ 599 reg = bus_space_read_1(sc->sc_iot, sc->sc_sb800_ioh, 600 SB800_INDIRECTIO_DATA); 601 reg &= ~mask; 602 reg |= __SHIFTIN(smbus->sda_save, mask); 603 bus_space_write_1(sc->sc_iot, sc->sc_sb800_ioh, 604 SB800_INDIRECTIO_DATA, reg); 605 } 606 607 /* Relase the host semaphore */ 608 sctl = bus_space_read_1(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_SC); 609 sctl &= ~PIIX_SMB_SC_SEMMASK; 610 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_SC, 611 sctl | PIIX_SMB_SC_CLRHOSTSEM); 612 613 if (!cold) 614 mutex_exit(&sc->sc_i2c_mutex); 615 } 616 617 static int 618 piixpm_i2c_exec(void *cookie, i2c_op_t op, i2c_addr_t addr, 619 const void *cmdbuf, size_t cmdlen, void *buf, size_t len, int flags) 620 { 621 struct piixpm_smbus *smbus = cookie; 622 struct piixpm_softc *sc = smbus->softc; 623 const uint8_t *b; 624 uint8_t ctl = 0, st; 625 int retries; 626 627 DPRINTF(("%s: exec: op %d, addr 0x%02x, cmdlen %zu, len %zu, " 628 "flags 0x%x\n", 629 device_xname(sc->sc_dev), op, addr, cmdlen, len, flags)); 630 631 /* Clear status bits */ 632 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_HS, 633 PIIX_SMB_HS_INTR | PIIX_SMB_HS_DEVERR | 634 PIIX_SMB_HS_BUSERR | PIIX_SMB_HS_FAILED); 635 bus_space_barrier(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_HS, 1, 636 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 637 638 /* Wait for bus to be idle */ 639 for (retries = 100; retries > 0; retries--) { 640 st = bus_space_read_1(sc->sc_smb_iot, sc->sc_smb_ioh, 641 PIIX_SMB_HS); 642 if (!(st & PIIX_SMB_HS_BUSY)) 643 break; 644 DELAY(PIIXPM_DELAY); 645 } 646 DPRINTF(("%s: exec: st %#x\n", device_xname(sc->sc_dev), st & 0xff)); 647 if (st & PIIX_SMB_HS_BUSY) 648 return (1); 649 650 if (cold || sc->sc_poll) 651 flags |= I2C_F_POLL; 652 653 if (!I2C_OP_STOP_P(op) || cmdlen > 1 || len > 2 || 654 (cmdlen == 0 && len > 1)) 655 return (1); 656 657 /* Setup transfer */ 658 sc->sc_i2c_xfer.op = op; 659 sc->sc_i2c_xfer.buf = buf; 660 sc->sc_i2c_xfer.len = len; 661 sc->sc_i2c_xfer.flags = flags; 662 sc->sc_i2c_xfer.error = 0; 663 664 /* Set slave address and transfer direction */ 665 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_TXSLVA, 666 PIIX_SMB_TXSLVA_ADDR(addr) | 667 (I2C_OP_READ_P(op) ? PIIX_SMB_TXSLVA_READ : 0)); 668 669 b = cmdbuf; 670 if (cmdlen > 0) 671 /* Set command byte */ 672 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, 673 PIIX_SMB_HCMD, b[0]); 674 675 if (I2C_OP_WRITE_P(op)) { 676 /* Write data */ 677 b = buf; 678 if (cmdlen == 0 && len == 1) 679 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, 680 PIIX_SMB_HCMD, b[0]); 681 else if (len > 0) 682 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, 683 PIIX_SMB_HD0, b[0]); 684 if (len > 1) 685 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, 686 PIIX_SMB_HD1, b[1]); 687 } 688 689 /* Set SMBus command */ 690 if (cmdlen == 0) { 691 if (len == 0) 692 ctl = PIIX_SMB_HC_CMD_QUICK; 693 else 694 ctl = PIIX_SMB_HC_CMD_BYTE; 695 } else if (len == 1) 696 ctl = PIIX_SMB_HC_CMD_BDATA; 697 else if (len == 2) 698 ctl = PIIX_SMB_HC_CMD_WDATA; 699 else 700 panic("%s: unexpected len %zu", __func__, len); 701 702 if ((flags & I2C_F_POLL) == 0) 703 ctl |= PIIX_SMB_HC_INTREN; 704 705 /* Start transaction */ 706 ctl |= PIIX_SMB_HC_START; 707 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_HC, ctl); 708 709 if (flags & I2C_F_POLL) { 710 /* Poll for completion */ 711 if (PIIXPM_IS_CSB5(sc)) 712 DELAY(2*PIIXPM_DELAY); 713 else 714 DELAY(PIIXPM_DELAY); 715 for (retries = 1000; retries > 0; retries--) { 716 st = bus_space_read_1(sc->sc_smb_iot, sc->sc_smb_ioh, 717 PIIX_SMB_HS); 718 if ((st & PIIX_SMB_HS_BUSY) == 0) 719 break; 720 DELAY(PIIXPM_DELAY); 721 } 722 if (st & PIIX_SMB_HS_BUSY) 723 goto timeout; 724 piixpm_intr(sc); 725 } else { 726 /* Wait for interrupt */ 727 if (tsleep(sc, PRIBIO, "piixpm", PIIXPM_TIMEOUT * hz)) 728 goto timeout; 729 } 730 731 if (sc->sc_i2c_xfer.error) 732 return (1); 733 734 return (0); 735 736 timeout: 737 /* 738 * Transfer timeout. Kill the transaction and clear status bits. 739 */ 740 aprint_error_dev(sc->sc_dev, "timeout, status 0x%x\n", st); 741 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_HC, 742 PIIX_SMB_HC_KILL); 743 DELAY(PIIXPM_DELAY); 744 st = bus_space_read_1(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_HS); 745 if ((st & PIIX_SMB_HS_FAILED) == 0) 746 aprint_error_dev(sc->sc_dev, 747 "transaction abort failed, status 0x%x\n", st); 748 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_HS, st); 749 /* 750 * CSB5 needs hard reset to unlock the smbus after timeout. 751 */ 752 if (PIIXPM_IS_CSB5(sc)) 753 piixpm_csb5_reset(sc); 754 return (1); 755 } 756 757 static int 758 piixpm_intr(void *arg) 759 { 760 struct piixpm_softc *sc = arg; 761 uint8_t st; 762 uint8_t *b; 763 size_t len; 764 765 /* Read status */ 766 st = bus_space_read_1(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_HS); 767 if ((st & PIIX_SMB_HS_BUSY) != 0 || (st & (PIIX_SMB_HS_INTR | 768 PIIX_SMB_HS_DEVERR | PIIX_SMB_HS_BUSERR | 769 PIIX_SMB_HS_FAILED)) == 0) 770 /* Interrupt was not for us */ 771 return (0); 772 773 DPRINTF(("%s: intr st %#x\n", device_xname(sc->sc_dev), st & 0xff)); 774 775 /* Clear status bits */ 776 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_HS, st); 777 778 /* Check for errors */ 779 if (st & (PIIX_SMB_HS_DEVERR | PIIX_SMB_HS_BUSERR | 780 PIIX_SMB_HS_FAILED)) { 781 sc->sc_i2c_xfer.error = 1; 782 goto done; 783 } 784 785 if (st & PIIX_SMB_HS_INTR) { 786 if (I2C_OP_WRITE_P(sc->sc_i2c_xfer.op)) 787 goto done; 788 789 /* Read data */ 790 b = sc->sc_i2c_xfer.buf; 791 len = sc->sc_i2c_xfer.len; 792 if (len > 0) 793 b[0] = bus_space_read_1(sc->sc_smb_iot, sc->sc_smb_ioh, 794 PIIX_SMB_HD0); 795 if (len > 1) 796 b[1] = bus_space_read_1(sc->sc_smb_iot, sc->sc_smb_ioh, 797 PIIX_SMB_HD1); 798 } 799 800 done: 801 if ((sc->sc_i2c_xfer.flags & I2C_F_POLL) == 0) 802 wakeup(sc); 803 return (1); 804 } 805
Indexes created Wed Oct 01 19:09:53 GMT 2025