piixpm.c revision 1.55
1 /* $NetBSD: piixpm.c,v 1.55 2019/12/22 23:23:32 thorpej Exp $ */ 2 /* $OpenBSD: piixpm.c,v 1.39 2013/10/01 20:06:02 sf Exp $ */ 3 4 /* 5 * Copyright (c) 2005, 2006 Alexander Yurchenko <grange (at) openbsd.org> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 /* 21 * Intel PIIX and compatible Power Management controller driver. 22 */ 23 24 #include <sys/cdefs.h> 25 __KERNEL_RCSID(0, "$NetBSD: piixpm.c,v 1.55 2019/12/22 23:23:32 thorpej Exp $"); 26 27 #include <sys/param.h> 28 #include <sys/systm.h> 29 #include <sys/device.h> 30 #include <sys/kernel.h> 31 #include <sys/mutex.h> 32 #include <sys/proc.h> 33 34 #include <sys/bus.h> 35 36 #include <dev/pci/pcidevs.h> 37 #include <dev/pci/pcireg.h> 38 #include <dev/pci/pcivar.h> 39 40 #include <dev/pci/piixpmreg.h> 41 42 #include <dev/i2c/i2cvar.h> 43 44 #include <dev/ic/acpipmtimer.h> 45 46 #ifdef PIIXPM_DEBUG 47 #define DPRINTF(x) printf x 48 #else 49 #define DPRINTF(x) 50 #endif 51 52 #define PIIXPM_IS_CSB5(sc) \ 53 (PCI_VENDOR((sc)->sc_id) == PCI_VENDOR_SERVERWORKS && \ 54 PCI_PRODUCT((sc)->sc_id) == PCI_PRODUCT_SERVERWORKS_CSB5) 55 #define PIIXPM_DELAY 200 56 #define PIIXPM_TIMEOUT 1 57 58 #define PIIXPM_IS_SB800GRP(sc) \ 59 ((PCI_VENDOR((sc)->sc_id) == PCI_VENDOR_ATI) && \ 60 ((PCI_PRODUCT((sc)->sc_id) == PCI_PRODUCT_ATI_SB600_SMB) && \ 61 ((sc)->sc_rev >= 0x40))) 62 63 #define PIIXPM_IS_HUDSON(sc) \ 64 ((PCI_VENDOR((sc)->sc_id) == PCI_VENDOR_AMD) && \ 65 (PCI_PRODUCT((sc)->sc_id) == PCI_PRODUCT_AMD_HUDSON_SMB)) 66 67 #define PIIXPM_IS_KERNCZ(sc) \ 68 ((PCI_VENDOR((sc)->sc_id) == PCI_VENDOR_AMD) && \ 69 (PCI_PRODUCT((sc)->sc_id) == PCI_PRODUCT_AMD_KERNCZ_SMB)) 70 71 #define PIIXPM_IS_FCHGRP(sc) (PIIXPM_IS_HUDSON(sc) || PIIXPM_IS_KERNCZ(sc)) 72 73 struct piixpm_smbus { 74 int sda; 75 struct piixpm_softc *softc; 76 }; 77 78 struct piixpm_softc { 79 device_t sc_dev; 80 81 bus_space_tag_t sc_iot; 82 #define sc_pm_iot sc_iot 83 #define sc_smb_iot sc_iot 84 bus_space_handle_t sc_pm_ioh; 85 bus_space_handle_t sc_sb800_ioh; 86 bus_space_handle_t sc_smb_ioh; 87 void * sc_smb_ih; 88 int sc_poll; 89 90 pci_chipset_tag_t sc_pc; 91 pcitag_t sc_pcitag; 92 pcireg_t sc_id; 93 pcireg_t sc_rev; 94 95 int sc_numbusses; 96 device_t sc_i2c_device[4]; 97 struct piixpm_smbus sc_busses[4]; 98 struct i2c_controller sc_i2c_tags[4]; 99 100 struct { 101 i2c_op_t op; 102 void * buf; 103 size_t len; 104 int flags; 105 volatile int error; 106 } sc_i2c_xfer; 107 108 pcireg_t sc_devact[2]; 109 }; 110 111 static int piixpm_match(device_t, cfdata_t, void *); 112 static void piixpm_attach(device_t, device_t, void *); 113 static int piixpm_rescan(device_t, const char *, const int *); 114 static void piixpm_chdet(device_t, device_t); 115 116 static bool piixpm_suspend(device_t, const pmf_qual_t *); 117 static bool piixpm_resume(device_t, const pmf_qual_t *); 118 119 static int piixpm_sb800_init(struct piixpm_softc *); 120 static void piixpm_csb5_reset(void *); 121 static int piixpm_i2c_acquire_bus(void *, int); 122 static void piixpm_i2c_release_bus(void *, int); 123 static int piixpm_i2c_exec(void *, i2c_op_t, i2c_addr_t, const void *, 124 size_t, void *, size_t, int); 125 126 static int piixpm_intr(void *); 127 128 CFATTACH_DECL3_NEW(piixpm, sizeof(struct piixpm_softc), 129 piixpm_match, piixpm_attach, NULL, NULL, piixpm_rescan, piixpm_chdet, 0); 130 131 static int 132 piixpm_match(device_t parent, cfdata_t match, void *aux) 133 { 134 struct pci_attach_args *pa; 135 136 pa = (struct pci_attach_args *)aux; 137 switch (PCI_VENDOR(pa->pa_id)) { 138 case PCI_VENDOR_INTEL: 139 switch (PCI_PRODUCT(pa->pa_id)) { 140 case PCI_PRODUCT_INTEL_82371AB_PMC: 141 case PCI_PRODUCT_INTEL_82440MX_PMC: 142 return 1; 143 } 144 break; 145 case PCI_VENDOR_ATI: 146 switch (PCI_PRODUCT(pa->pa_id)) { 147 case PCI_PRODUCT_ATI_SB200_SMB: 148 case PCI_PRODUCT_ATI_SB300_SMB: 149 case PCI_PRODUCT_ATI_SB400_SMB: 150 case PCI_PRODUCT_ATI_SB600_SMB: /* matches SB600/SB700/SB800 */ 151 return 1; 152 } 153 break; 154 case PCI_VENDOR_SERVERWORKS: 155 switch (PCI_PRODUCT(pa->pa_id)) { 156 case PCI_PRODUCT_SERVERWORKS_OSB4: 157 case PCI_PRODUCT_SERVERWORKS_CSB5: 158 case PCI_PRODUCT_SERVERWORKS_CSB6: 159 case PCI_PRODUCT_SERVERWORKS_HT1000SB: 160 case PCI_PRODUCT_SERVERWORKS_HT1100SB: 161 return 1; 162 } 163 break; 164 case PCI_VENDOR_AMD: 165 switch (PCI_PRODUCT(pa->pa_id)) { 166 case PCI_PRODUCT_AMD_HUDSON_SMB: 167 case PCI_PRODUCT_AMD_KERNCZ_SMB: 168 return 1; 169 } 170 break; 171 } 172 173 return 0; 174 } 175 176 static void 177 piixpm_attach(device_t parent, device_t self, void *aux) 178 { 179 struct piixpm_softc *sc = device_private(self); 180 struct pci_attach_args *pa = aux; 181 pcireg_t base, conf; 182 pcireg_t pmmisc; 183 pci_intr_handle_t ih; 184 bool usesmi = false; 185 const char *intrstr = NULL; 186 int i, flags; 187 char intrbuf[PCI_INTRSTR_LEN]; 188 189 sc->sc_dev = self; 190 sc->sc_iot = pa->pa_iot; 191 sc->sc_id = pa->pa_id; 192 sc->sc_rev = PCI_REVISION(pa->pa_class); 193 sc->sc_pc = pa->pa_pc; 194 sc->sc_pcitag = pa->pa_tag; 195 sc->sc_numbusses = 1; 196 197 pci_aprint_devinfo(pa, NULL); 198 199 if (!pmf_device_register(self, piixpm_suspend, piixpm_resume)) 200 aprint_error_dev(self, "couldn't establish power handler\n"); 201 202 if ((PCI_VENDOR(pa->pa_id) != PCI_VENDOR_INTEL) || 203 (PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_INTEL_82371AB_PMC)) 204 goto nopowermanagement; 205 206 /* check whether I/O access to PM regs is enabled */ 207 pmmisc = pci_conf_read(pa->pa_pc, pa->pa_tag, PIIX_PMREGMISC); 208 if (!(pmmisc & 1)) 209 goto nopowermanagement; 210 211 /* Map I/O space */ 212 base = pci_conf_read(pa->pa_pc, pa->pa_tag, PIIX_PM_BASE); 213 if (base == 0 || bus_space_map(sc->sc_pm_iot, PCI_MAPREG_IO_ADDR(base), 214 PIIX_PM_SIZE, 0, &sc->sc_pm_ioh)) { 215 aprint_error_dev(self, 216 "can't map power management I/O space\n"); 217 goto nopowermanagement; 218 } 219 220 /* 221 * Revision 0 and 1 are PIIX4, 2 is PIIX4E, 3 is PIIX4M. 222 * PIIX4 and PIIX4E have a bug in the timer latch, see Errata #20 223 * in the "Specification update" (document #297738). 224 */ 225 acpipmtimer_attach(self, sc->sc_pm_iot, sc->sc_pm_ioh, PIIX_PM_PMTMR, 226 (PCI_REVISION(pa->pa_class) < 3) ? ACPIPMT_BADLATCH : 0); 227 228 nopowermanagement: 229 230 /* SB800 rev 0x40+, AMD HUDSON and newer need special initialization */ 231 if (PIIXPM_IS_FCHGRP(sc) || PIIXPM_IS_SB800GRP(sc)) { 232 if (piixpm_sb800_init(sc) == 0) { 233 sc->sc_numbusses = 4; 234 235 /* Read configuration */ 236 conf = pci_conf_read(pa->pa_pc, pa->pa_tag, 237 SB800_SMB_HOSTC); 238 DPRINTF(("%s: conf 0x%08x\n", device_xname(self), 239 conf)); 240 241 usesmi = conf & SB800_SMB_HOSTC_SMI; 242 goto setintr; 243 } 244 aprint_normal_dev(self, "SMBus initialization failed\n"); 245 return; 246 } 247 248 /* Read configuration */ 249 conf = pci_conf_read(pa->pa_pc, pa->pa_tag, PIIX_SMB_HOSTC); 250 DPRINTF(("%s: conf 0x%08x\n", device_xname(self), conf)); 251 252 if ((conf & PIIX_SMB_HOSTC_HSTEN) == 0) { 253 aprint_normal_dev(self, "SMBus disabled\n"); 254 return; 255 } 256 usesmi = (conf & PIIX_SMB_HOSTC_INTMASK) == PIIX_SMB_HOSTC_SMI; 257 258 /* Map I/O space */ 259 base = pci_conf_read(pa->pa_pc, pa->pa_tag, PIIX_SMB_BASE) & 0xffff; 260 if (base == 0 || 261 bus_space_map(sc->sc_smb_iot, PCI_MAPREG_IO_ADDR(base), 262 PIIX_SMB_SIZE, 0, &sc->sc_smb_ioh)) { 263 aprint_error_dev(self, "can't map smbus I/O space\n"); 264 return; 265 } 266 267 setintr: 268 sc->sc_poll = 1; 269 aprint_normal_dev(self, ""); 270 if (usesmi) { 271 /* No PCI IRQ */ 272 aprint_normal("interrupting at SMI, "); 273 } else { 274 if ((conf & PIIX_SMB_HOSTC_INTMASK) == PIIX_SMB_HOSTC_IRQ) { 275 /* Install interrupt handler */ 276 if (pci_intr_map(pa, &ih) == 0) { 277 intrstr = pci_intr_string(pa->pa_pc, ih, 278 intrbuf, sizeof(intrbuf)); 279 sc->sc_smb_ih = pci_intr_establish_xname( 280 pa->pa_pc, ih, IPL_BIO, piixpm_intr, 281 sc, device_xname(sc->sc_dev)); 282 if (sc->sc_smb_ih != NULL) { 283 aprint_normal("interrupting at %s", 284 intrstr); 285 sc->sc_poll = 0; 286 } 287 } 288 } 289 if (sc->sc_poll) 290 aprint_normal("polling"); 291 } 292 293 aprint_normal("\n"); 294 295 for (i = 0; i < sc->sc_numbusses; i++) 296 sc->sc_i2c_device[i] = NULL; 297 298 flags = 0; 299 piixpm_rescan(self, "i2cbus", &flags); 300 } 301 302 static int 303 piixpm_iicbus_print(void *aux, const char *pnp) 304 { 305 struct i2cbus_attach_args *iba = aux; 306 struct i2c_controller *tag = iba->iba_tag; 307 struct piixpm_smbus *bus = tag->ic_cookie; 308 struct piixpm_softc *sc = bus->softc; 309 310 iicbus_print(aux, pnp); 311 if (sc->sc_numbusses != 0) 312 aprint_normal(" port %d", bus->sda); 313 314 return UNCONF; 315 } 316 static int 317 piixpm_rescan(device_t self, const char *ifattr, const int *flags) 318 { 319 struct piixpm_softc *sc = device_private(self); 320 struct i2cbus_attach_args iba; 321 int i; 322 323 if (!ifattr_match(ifattr, "i2cbus")) 324 return 0; 325 326 /* Attach I2C bus */ 327 328 for (i = 0; i < sc->sc_numbusses; i++) { 329 if (sc->sc_i2c_device[i]) 330 continue; 331 sc->sc_busses[i].sda = i; 332 sc->sc_busses[i].softc = sc; 333 iic_tag_init(&sc->sc_i2c_tags[i]); 334 sc->sc_i2c_tags[i].ic_cookie = &sc->sc_busses[i]; 335 sc->sc_i2c_tags[i].ic_acquire_bus = piixpm_i2c_acquire_bus; 336 sc->sc_i2c_tags[i].ic_release_bus = piixpm_i2c_release_bus; 337 sc->sc_i2c_tags[i].ic_exec = piixpm_i2c_exec; 338 memset(&iba, 0, sizeof(iba)); 339 iba.iba_tag = &sc->sc_i2c_tags[i]; 340 sc->sc_i2c_device[i] = config_found_ia(self, ifattr, &iba, 341 piixpm_iicbus_print); 342 } 343 344 return 0; 345 } 346 347 static void 348 piixpm_chdet(device_t self, device_t child) 349 { 350 struct piixpm_softc *sc = device_private(self); 351 int i; 352 353 for (i = 0; i < sc->sc_numbusses; i++) { 354 if (sc->sc_i2c_device[i] == child) { 355 sc->sc_i2c_device[i] = NULL; 356 break; 357 } 358 } 359 } 360 361 362 static bool 363 piixpm_suspend(device_t dv, const pmf_qual_t *qual) 364 { 365 struct piixpm_softc *sc = device_private(dv); 366 367 sc->sc_devact[0] = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 368 PIIX_DEVACTA); 369 sc->sc_devact[1] = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 370 PIIX_DEVACTB); 371 372 return true; 373 } 374 375 static bool 376 piixpm_resume(device_t dv, const pmf_qual_t *qual) 377 { 378 struct piixpm_softc *sc = device_private(dv); 379 380 pci_conf_write(sc->sc_pc, sc->sc_pcitag, PIIX_DEVACTA, 381 sc->sc_devact[0]); 382 pci_conf_write(sc->sc_pc, sc->sc_pcitag, PIIX_DEVACTB, 383 sc->sc_devact[1]); 384 385 return true; 386 } 387 388 /* 389 * Extract SMBus base address from SB800 Power Management (PM) registers. 390 * The PM registers can be accessed either through indirect I/O (CD6/CD7) or 391 * direct mapping if AcpiMMioDecodeEn is enabled. Since this function is only 392 * called once it uses indirect I/O for simplicity. 393 */ 394 static int 395 piixpm_sb800_init(struct piixpm_softc *sc) 396 { 397 bus_space_tag_t iot = sc->sc_iot; 398 bus_space_handle_t ioh; /* indirect I/O handle */ 399 uint16_t val, base_addr; 400 bool enabled; 401 402 /* Fetch SMB base address */ 403 if (bus_space_map(iot, 404 SB800_INDIRECTIO_BASE, SB800_INDIRECTIO_SIZE, 0, &ioh)) { 405 device_printf(sc->sc_dev, "couldn't map indirect I/O space\n"); 406 return EBUSY; 407 } 408 if (PIIXPM_IS_FCHGRP(sc)) { 409 bus_space_write_1(iot, ioh, SB800_INDIRECTIO_INDEX, 410 AMDFCH41_PM_DECODE_EN0); 411 val = bus_space_read_1(iot, ioh, SB800_INDIRECTIO_DATA); 412 enabled = val & AMDFCH41_SMBUS_EN; 413 if (!enabled) 414 return ENOENT; 415 416 bus_space_write_1(iot, ioh, SB800_INDIRECTIO_INDEX, 417 AMDFCH41_PM_DECODE_EN1); 418 val = bus_space_read_1(iot, ioh, SB800_INDIRECTIO_DATA) << 8; 419 base_addr = val; 420 } else { 421 bus_space_write_1(iot, ioh, SB800_INDIRECTIO_INDEX, 422 SB800_PM_SMBUS0EN_LO); 423 val = bus_space_read_1(iot, ioh, SB800_INDIRECTIO_DATA); 424 enabled = val & SB800_PM_SMBUS0EN_ENABLE; 425 if (!enabled) 426 return ENOENT; 427 428 bus_space_write_1(iot, ioh, SB800_INDIRECTIO_INDEX, 429 SB800_PM_SMBUS0EN_HI); 430 val |= bus_space_read_1(iot, ioh, SB800_INDIRECTIO_DATA) << 8; 431 base_addr = val & SB800_PM_SMBUS0EN_BADDR; 432 433 bus_space_write_1(iot, ioh, SB800_INDIRECTIO_INDEX, 434 SB800_PM_SMBUS0SELEN); 435 bus_space_write_1(iot, ioh, SB800_INDIRECTIO_DATA, 436 SB800_PM_SMBUS0EN_ENABLE); 437 } 438 439 sc->sc_sb800_ioh = ioh; 440 aprint_debug_dev(sc->sc_dev, "SMBus @ 0x%04x\n", base_addr); 441 442 if (bus_space_map(iot, PCI_MAPREG_IO_ADDR(base_addr), 443 PIIX_SMB_SIZE, 0, &sc->sc_smb_ioh)) { 444 aprint_error_dev(sc->sc_dev, "can't map smbus I/O space\n"); 445 return EBUSY; 446 } 447 448 return 0; 449 } 450 451 static void 452 piixpm_csb5_reset(void *arg) 453 { 454 struct piixpm_softc *sc = arg; 455 pcireg_t base, hostc, pmbase; 456 457 base = pci_conf_read(sc->sc_pc, sc->sc_pcitag, PIIX_SMB_BASE); 458 hostc = pci_conf_read(sc->sc_pc, sc->sc_pcitag, PIIX_SMB_HOSTC); 459 460 pmbase = pci_conf_read(sc->sc_pc, sc->sc_pcitag, PIIX_PM_BASE); 461 pmbase |= PIIX_PM_BASE_CSB5_RESET; 462 pci_conf_write(sc->sc_pc, sc->sc_pcitag, PIIX_PM_BASE, pmbase); 463 pmbase &= ~PIIX_PM_BASE_CSB5_RESET; 464 pci_conf_write(sc->sc_pc, sc->sc_pcitag, PIIX_PM_BASE, pmbase); 465 466 pci_conf_write(sc->sc_pc, sc->sc_pcitag, PIIX_SMB_BASE, base); 467 pci_conf_write(sc->sc_pc, sc->sc_pcitag, PIIX_SMB_HOSTC, hostc); 468 469 (void) tsleep(&sc, PRIBIO, "csb5reset", hz/2); 470 } 471 472 static int 473 piixpm_i2c_acquire_bus(void *cookie, int flags) 474 { 475 struct piixpm_smbus *smbus = cookie; 476 struct piixpm_softc *sc = smbus->softc; 477 478 if (PIIXPM_IS_KERNCZ(sc)) { 479 bus_space_write_1(sc->sc_iot, sc->sc_sb800_ioh, 480 SB800_INDIRECTIO_INDEX, AMDFCH41_PM_PORT_INDEX); 481 bus_space_write_1(sc->sc_iot, sc->sc_sb800_ioh, 482 SB800_INDIRECTIO_DATA, smbus->sda << 3); 483 } else if (PIIXPM_IS_SB800GRP(sc) || PIIXPM_IS_HUDSON(sc)) { 484 bus_space_write_1(sc->sc_iot, sc->sc_sb800_ioh, 485 SB800_INDIRECTIO_INDEX, SB800_PM_SMBUS0SEL); 486 bus_space_write_1(sc->sc_iot, sc->sc_sb800_ioh, 487 SB800_INDIRECTIO_DATA, smbus->sda << 1); 488 } 489 490 return 0; 491 } 492 493 static void 494 piixpm_i2c_release_bus(void *cookie, int flags) 495 { 496 struct piixpm_smbus *smbus = cookie; 497 struct piixpm_softc *sc = smbus->softc; 498 499 if (PIIXPM_IS_KERNCZ(sc)) { 500 bus_space_write_1(sc->sc_iot, sc->sc_sb800_ioh, 501 SB800_INDIRECTIO_INDEX, AMDFCH41_PM_PORT_INDEX); 502 bus_space_write_1(sc->sc_iot, sc->sc_sb800_ioh, 503 SB800_INDIRECTIO_DATA, 0); 504 } else if (PIIXPM_IS_SB800GRP(sc) || PIIXPM_IS_HUDSON(sc)) { 505 /* 506 * HP Microserver hangs after reboot if not set to SDA0. 507 * Also add shutdown hook? 508 */ 509 bus_space_write_1(sc->sc_iot, sc->sc_sb800_ioh, 510 SB800_INDIRECTIO_INDEX, SB800_PM_SMBUS0SEL); 511 bus_space_write_1(sc->sc_iot, sc->sc_sb800_ioh, 512 SB800_INDIRECTIO_DATA, 0); 513 } 514 } 515 516 static int 517 piixpm_i2c_exec(void *cookie, i2c_op_t op, i2c_addr_t addr, 518 const void *cmdbuf, size_t cmdlen, void *buf, size_t len, int flags) 519 { 520 struct piixpm_smbus *smbus = cookie; 521 struct piixpm_softc *sc = smbus->softc; 522 const uint8_t *b; 523 uint8_t ctl = 0, st; 524 int retries; 525 526 DPRINTF(("%s: exec: op %d, addr 0x%02x, cmdlen %zu, len %zu, " 527 "flags 0x%x\n", 528 device_xname(sc->sc_dev), op, addr, cmdlen, len, flags)); 529 530 /* Clear status bits */ 531 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_HS, 532 PIIX_SMB_HS_INTR | PIIX_SMB_HS_DEVERR | 533 PIIX_SMB_HS_BUSERR | PIIX_SMB_HS_FAILED); 534 bus_space_barrier(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_HS, 1, 535 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 536 537 /* Wait for bus to be idle */ 538 for (retries = 100; retries > 0; retries--) { 539 st = bus_space_read_1(sc->sc_smb_iot, sc->sc_smb_ioh, 540 PIIX_SMB_HS); 541 if (!(st & PIIX_SMB_HS_BUSY)) 542 break; 543 DELAY(PIIXPM_DELAY); 544 } 545 DPRINTF(("%s: exec: st %#x\n", device_xname(sc->sc_dev), st & 0xff)); 546 if (st & PIIX_SMB_HS_BUSY) 547 return (1); 548 549 if (cold || sc->sc_poll) 550 flags |= I2C_F_POLL; 551 552 if (!I2C_OP_STOP_P(op) || cmdlen > 1 || len > 2 || 553 (cmdlen == 0 && len > 1)) 554 return (1); 555 556 /* Setup transfer */ 557 sc->sc_i2c_xfer.op = op; 558 sc->sc_i2c_xfer.buf = buf; 559 sc->sc_i2c_xfer.len = len; 560 sc->sc_i2c_xfer.flags = flags; 561 sc->sc_i2c_xfer.error = 0; 562 563 /* Set slave address and transfer direction */ 564 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_TXSLVA, 565 PIIX_SMB_TXSLVA_ADDR(addr) | 566 (I2C_OP_READ_P(op) ? PIIX_SMB_TXSLVA_READ : 0)); 567 568 b = cmdbuf; 569 if (cmdlen > 0) 570 /* Set command byte */ 571 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, 572 PIIX_SMB_HCMD, b[0]); 573 574 if (I2C_OP_WRITE_P(op)) { 575 /* Write data */ 576 b = buf; 577 if (cmdlen == 0 && len == 1) 578 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, 579 PIIX_SMB_HCMD, b[0]); 580 else if (len > 0) 581 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, 582 PIIX_SMB_HD0, b[0]); 583 if (len > 1) 584 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, 585 PIIX_SMB_HD1, b[1]); 586 } 587 588 /* Set SMBus command */ 589 if (cmdlen == 0) { 590 if (len == 0) 591 ctl = PIIX_SMB_HC_CMD_QUICK; 592 else 593 ctl = PIIX_SMB_HC_CMD_BYTE; 594 } else if (len == 1) 595 ctl = PIIX_SMB_HC_CMD_BDATA; 596 else if (len == 2) 597 ctl = PIIX_SMB_HC_CMD_WDATA; 598 else 599 panic("%s: unexpected len %zu", __func__, len); 600 601 if ((flags & I2C_F_POLL) == 0) 602 ctl |= PIIX_SMB_HC_INTREN; 603 604 /* Start transaction */ 605 ctl |= PIIX_SMB_HC_START; 606 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_HC, ctl); 607 608 if (flags & I2C_F_POLL) { 609 /* Poll for completion */ 610 if (PIIXPM_IS_CSB5(sc)) 611 DELAY(2*PIIXPM_DELAY); 612 else 613 DELAY(PIIXPM_DELAY); 614 for (retries = 1000; retries > 0; retries--) { 615 st = bus_space_read_1(sc->sc_smb_iot, sc->sc_smb_ioh, 616 PIIX_SMB_HS); 617 if ((st & PIIX_SMB_HS_BUSY) == 0) 618 break; 619 DELAY(PIIXPM_DELAY); 620 } 621 if (st & PIIX_SMB_HS_BUSY) 622 goto timeout; 623 piixpm_intr(sc); 624 } else { 625 /* Wait for interrupt */ 626 if (tsleep(sc, PRIBIO, "piixpm", PIIXPM_TIMEOUT * hz)) 627 goto timeout; 628 } 629 630 if (sc->sc_i2c_xfer.error) 631 return (1); 632 633 return (0); 634 635 timeout: 636 /* 637 * Transfer timeout. Kill the transaction and clear status bits. 638 */ 639 aprint_error_dev(sc->sc_dev, "timeout, status 0x%x\n", st); 640 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_HC, 641 PIIX_SMB_HC_KILL); 642 DELAY(PIIXPM_DELAY); 643 st = bus_space_read_1(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_HS); 644 if ((st & PIIX_SMB_HS_FAILED) == 0) 645 aprint_error_dev(sc->sc_dev, 646 "transaction abort failed, status 0x%x\n", st); 647 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_HS, st); 648 /* 649 * CSB5 needs hard reset to unlock the smbus after timeout. 650 */ 651 if (PIIXPM_IS_CSB5(sc)) 652 piixpm_csb5_reset(sc); 653 return (1); 654 } 655 656 static int 657 piixpm_intr(void *arg) 658 { 659 struct piixpm_softc *sc = arg; 660 uint8_t st; 661 uint8_t *b; 662 size_t len; 663 664 /* Read status */ 665 st = bus_space_read_1(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_HS); 666 if ((st & PIIX_SMB_HS_BUSY) != 0 || (st & (PIIX_SMB_HS_INTR | 667 PIIX_SMB_HS_DEVERR | PIIX_SMB_HS_BUSERR | 668 PIIX_SMB_HS_FAILED)) == 0) 669 /* Interrupt was not for us */ 670 return (0); 671 672 DPRINTF(("%s: intr st %#x\n", device_xname(sc->sc_dev), st & 0xff)); 673 674 /* Clear status bits */ 675 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_HS, st); 676 677 /* Check for errors */ 678 if (st & (PIIX_SMB_HS_DEVERR | PIIX_SMB_HS_BUSERR | 679 PIIX_SMB_HS_FAILED)) { 680 sc->sc_i2c_xfer.error = 1; 681 goto done; 682 } 683 684 if (st & PIIX_SMB_HS_INTR) { 685 if (I2C_OP_WRITE_P(sc->sc_i2c_xfer.op)) 686 goto done; 687 688 /* Read data */ 689 b = sc->sc_i2c_xfer.buf; 690 len = sc->sc_i2c_xfer.len; 691 if (len > 0) 692 b[0] = bus_space_read_1(sc->sc_smb_iot, sc->sc_smb_ioh, 693 PIIX_SMB_HD0); 694 if (len > 1) 695 b[1] = bus_space_read_1(sc->sc_smb_iot, sc->sc_smb_ioh, 696 PIIX_SMB_HD1); 697 } 698 699 done: 700 if ((sc->sc_i2c_xfer.flags & I2C_F_POLL) == 0) 701 wakeup(sc); 702 return (1); 703 } 704
Indexes created Sun Sep 28 12:09:53 GMT 2025