piixpm.c revision 1.57
1 /* $NetBSD: piixpm.c,v 1.57 2019/12/23 23:31:23 msaitoh Exp $ */ 2 /* $OpenBSD: piixpm.c,v 1.39 2013/10/01 20:06:02 sf Exp $ */ 3 4 /* 5 * Copyright (c) 2005, 2006 Alexander Yurchenko <grange (at) openbsd.org> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 /* 21 * Intel PIIX and compatible Power Management controller driver. 22 */ 23 24 #include <sys/cdefs.h> 25 __KERNEL_RCSID(0, "$NetBSD: piixpm.c,v 1.57 2019/12/23 23:31:23 msaitoh Exp $"); 26 27 #include <sys/param.h> 28 #include <sys/systm.h> 29 #include <sys/device.h> 30 #include <sys/kernel.h> 31 #include <sys/mutex.h> 32 #include <sys/proc.h> 33 34 #include <sys/bus.h> 35 36 #include <dev/pci/pcidevs.h> 37 #include <dev/pci/pcireg.h> 38 #include <dev/pci/pcivar.h> 39 40 #include <dev/pci/piixpmreg.h> 41 42 #include <dev/i2c/i2cvar.h> 43 44 #include <dev/ic/acpipmtimer.h> 45 46 #ifdef PIIXPM_DEBUG 47 #define DPRINTF(x) printf x 48 #else 49 #define DPRINTF(x) 50 #endif 51 52 #define PIIXPM_IS_CSB5(sc) \ 53 (PCI_VENDOR((sc)->sc_id) == PCI_VENDOR_SERVERWORKS && \ 54 PCI_PRODUCT((sc)->sc_id) == PCI_PRODUCT_SERVERWORKS_CSB5) 55 #define PIIXPM_DELAY 200 56 #define PIIXPM_TIMEOUT 1 57 58 #define PIIXPM_IS_SB800GRP(sc) \ 59 ((PCI_VENDOR((sc)->sc_id) == PCI_VENDOR_ATI) && \ 60 ((PCI_PRODUCT((sc)->sc_id) == PCI_PRODUCT_ATI_SB600_SMB) && \ 61 ((sc)->sc_rev >= 0x40))) 62 63 #define PIIXPM_IS_HUDSON(sc) \ 64 ((PCI_VENDOR((sc)->sc_id) == PCI_VENDOR_AMD) && \ 65 (PCI_PRODUCT((sc)->sc_id) == PCI_PRODUCT_AMD_HUDSON_SMB)) 66 67 #define PIIXPM_IS_KERNCZ(sc) \ 68 ((PCI_VENDOR((sc)->sc_id) == PCI_VENDOR_AMD) && \ 69 (PCI_PRODUCT((sc)->sc_id) == PCI_PRODUCT_AMD_KERNCZ_SMB)) 70 71 #define PIIXPM_IS_FCHGRP(sc) (PIIXPM_IS_HUDSON(sc) || PIIXPM_IS_KERNCZ(sc)) 72 73 struct piixpm_smbus { 74 int sda; 75 struct piixpm_softc *softc; 76 }; 77 78 struct piixpm_softc { 79 device_t sc_dev; 80 81 bus_space_tag_t sc_iot; 82 #define sc_pm_iot sc_iot 83 #define sc_smb_iot sc_iot 84 bus_space_handle_t sc_pm_ioh; 85 bus_space_handle_t sc_sb800_ioh; 86 bus_space_handle_t sc_smb_ioh; 87 void * sc_smb_ih; 88 int sc_poll; 89 90 pci_chipset_tag_t sc_pc; 91 pcitag_t sc_pcitag; 92 pcireg_t sc_id; 93 pcireg_t sc_rev; 94 95 int sc_numbusses; 96 device_t sc_i2c_device[4]; 97 struct piixpm_smbus sc_busses[4]; 98 struct i2c_controller sc_i2c_tags[4]; 99 100 struct { 101 i2c_op_t op; 102 void * buf; 103 size_t len; 104 int flags; 105 volatile int error; 106 } sc_i2c_xfer; 107 108 pcireg_t sc_devact[2]; 109 }; 110 111 static int piixpm_match(device_t, cfdata_t, void *); 112 static void piixpm_attach(device_t, device_t, void *); 113 static int piixpm_rescan(device_t, const char *, const int *); 114 static void piixpm_chdet(device_t, device_t); 115 116 static bool piixpm_suspend(device_t, const pmf_qual_t *); 117 static bool piixpm_resume(device_t, const pmf_qual_t *); 118 119 static int piixpm_sb800_init(struct piixpm_softc *); 120 static void piixpm_csb5_reset(void *); 121 static int piixpm_i2c_acquire_bus(void *, int); 122 static void piixpm_i2c_release_bus(void *, int); 123 static int piixpm_i2c_exec(void *, i2c_op_t, i2c_addr_t, const void *, 124 size_t, void *, size_t, int); 125 126 static int piixpm_intr(void *); 127 128 CFATTACH_DECL3_NEW(piixpm, sizeof(struct piixpm_softc), 129 piixpm_match, piixpm_attach, NULL, NULL, piixpm_rescan, piixpm_chdet, 0); 130 131 static int 132 piixpm_match(device_t parent, cfdata_t match, void *aux) 133 { 134 struct pci_attach_args *pa; 135 136 pa = (struct pci_attach_args *)aux; 137 switch (PCI_VENDOR(pa->pa_id)) { 138 case PCI_VENDOR_INTEL: 139 switch (PCI_PRODUCT(pa->pa_id)) { 140 case PCI_PRODUCT_INTEL_82371AB_PMC: 141 case PCI_PRODUCT_INTEL_82440MX_PMC: 142 return 1; 143 } 144 break; 145 case PCI_VENDOR_ATI: 146 switch (PCI_PRODUCT(pa->pa_id)) { 147 case PCI_PRODUCT_ATI_SB200_SMB: 148 case PCI_PRODUCT_ATI_SB300_SMB: 149 case PCI_PRODUCT_ATI_SB400_SMB: 150 case PCI_PRODUCT_ATI_SB600_SMB: /* matches SB600/SB700/SB800 */ 151 return 1; 152 } 153 break; 154 case PCI_VENDOR_SERVERWORKS: 155 switch (PCI_PRODUCT(pa->pa_id)) { 156 case PCI_PRODUCT_SERVERWORKS_OSB4: 157 case PCI_PRODUCT_SERVERWORKS_CSB5: 158 case PCI_PRODUCT_SERVERWORKS_CSB6: 159 case PCI_PRODUCT_SERVERWORKS_HT1000SB: 160 case PCI_PRODUCT_SERVERWORKS_HT1100SB: 161 return 1; 162 } 163 break; 164 case PCI_VENDOR_AMD: 165 switch (PCI_PRODUCT(pa->pa_id)) { 166 case PCI_PRODUCT_AMD_HUDSON_SMB: 167 case PCI_PRODUCT_AMD_KERNCZ_SMB: 168 return 1; 169 } 170 break; 171 } 172 173 return 0; 174 } 175 176 static void 177 piixpm_attach(device_t parent, device_t self, void *aux) 178 { 179 struct piixpm_softc *sc = device_private(self); 180 struct pci_attach_args *pa = aux; 181 pcireg_t base, conf; 182 pcireg_t pmmisc; 183 pci_intr_handle_t ih; 184 bool usesmi = false; 185 const char *intrstr = NULL; 186 int i, flags; 187 char intrbuf[PCI_INTRSTR_LEN]; 188 189 sc->sc_dev = self; 190 sc->sc_iot = pa->pa_iot; 191 sc->sc_id = pa->pa_id; 192 sc->sc_rev = PCI_REVISION(pa->pa_class); 193 sc->sc_pc = pa->pa_pc; 194 sc->sc_pcitag = pa->pa_tag; 195 sc->sc_numbusses = 1; 196 197 pci_aprint_devinfo(pa, NULL); 198 199 if (!pmf_device_register(self, piixpm_suspend, piixpm_resume)) 200 aprint_error_dev(self, "couldn't establish power handler\n"); 201 202 if ((PCI_VENDOR(pa->pa_id) != PCI_VENDOR_INTEL) || 203 (PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_INTEL_82371AB_PMC)) 204 goto nopowermanagement; 205 206 /* check whether I/O access to PM regs is enabled */ 207 pmmisc = pci_conf_read(pa->pa_pc, pa->pa_tag, PIIX_PMREGMISC); 208 if (!(pmmisc & 1)) 209 goto nopowermanagement; 210 211 /* Map I/O space */ 212 base = pci_conf_read(pa->pa_pc, pa->pa_tag, PIIX_PM_BASE); 213 if (base == 0 || bus_space_map(sc->sc_pm_iot, PCI_MAPREG_IO_ADDR(base), 214 PIIX_PM_SIZE, 0, &sc->sc_pm_ioh)) { 215 aprint_error_dev(self, 216 "can't map power management I/O space\n"); 217 goto nopowermanagement; 218 } 219 220 /* 221 * Revision 0 and 1 are PIIX4, 2 is PIIX4E, 3 is PIIX4M. 222 * PIIX4 and PIIX4E have a bug in the timer latch, see Errata #20 223 * in the "Specification update" (document #297738). 224 */ 225 acpipmtimer_attach(self, sc->sc_pm_iot, sc->sc_pm_ioh, PIIX_PM_PMTMR, 226 (PCI_REVISION(pa->pa_class) < 3) ? ACPIPMT_BADLATCH : 0); 227 228 nopowermanagement: 229 230 /* SB800 rev 0x40+, AMD HUDSON and newer need special initialization */ 231 if (PIIXPM_IS_FCHGRP(sc) || PIIXPM_IS_SB800GRP(sc)) { 232 if (piixpm_sb800_init(sc) == 0) { 233 /* Read configuration */ 234 conf = pci_conf_read(pa->pa_pc, pa->pa_tag, 235 SB800_SMB_HOSTC); 236 DPRINTF(("%s: conf 0x%08x\n", device_xname(self), 237 conf)); 238 239 usesmi = conf & SB800_SMB_HOSTC_SMI; 240 goto setintr; 241 } 242 aprint_normal_dev(self, "SMBus initialization failed\n"); 243 return; 244 } 245 246 /* Read configuration */ 247 conf = pci_conf_read(pa->pa_pc, pa->pa_tag, PIIX_SMB_HOSTC); 248 DPRINTF(("%s: conf 0x%08x\n", device_xname(self), conf)); 249 250 if ((conf & PIIX_SMB_HOSTC_HSTEN) == 0) { 251 aprint_normal_dev(self, "SMBus disabled\n"); 252 return; 253 } 254 usesmi = (conf & PIIX_SMB_HOSTC_INTMASK) == PIIX_SMB_HOSTC_SMI; 255 256 /* Map I/O space */ 257 base = pci_conf_read(pa->pa_pc, pa->pa_tag, PIIX_SMB_BASE) & 0xffff; 258 if (base == 0 || 259 bus_space_map(sc->sc_smb_iot, PCI_MAPREG_IO_ADDR(base), 260 PIIX_SMB_SIZE, 0, &sc->sc_smb_ioh)) { 261 aprint_error_dev(self, "can't map smbus I/O space\n"); 262 return; 263 } 264 265 setintr: 266 sc->sc_poll = 1; 267 aprint_normal_dev(self, ""); 268 if (usesmi) { 269 /* No PCI IRQ */ 270 aprint_normal("interrupting at SMI, "); 271 } else { 272 if ((conf & PIIX_SMB_HOSTC_INTMASK) == PIIX_SMB_HOSTC_IRQ) { 273 /* Install interrupt handler */ 274 if (pci_intr_map(pa, &ih) == 0) { 275 intrstr = pci_intr_string(pa->pa_pc, ih, 276 intrbuf, sizeof(intrbuf)); 277 sc->sc_smb_ih = pci_intr_establish_xname( 278 pa->pa_pc, ih, IPL_BIO, piixpm_intr, 279 sc, device_xname(sc->sc_dev)); 280 if (sc->sc_smb_ih != NULL) { 281 aprint_normal("interrupting at %s", 282 intrstr); 283 sc->sc_poll = 0; 284 } 285 } 286 } 287 if (sc->sc_poll) 288 aprint_normal("polling"); 289 } 290 291 aprint_normal("\n"); 292 293 for (i = 0; i < sc->sc_numbusses; i++) 294 sc->sc_i2c_device[i] = NULL; 295 296 flags = 0; 297 piixpm_rescan(self, "i2cbus", &flags); 298 } 299 300 static int 301 piixpm_iicbus_print(void *aux, const char *pnp) 302 { 303 struct i2cbus_attach_args *iba = aux; 304 struct i2c_controller *tag = iba->iba_tag; 305 struct piixpm_smbus *bus = tag->ic_cookie; 306 struct piixpm_softc *sc = bus->softc; 307 308 iicbus_print(aux, pnp); 309 if (sc->sc_numbusses != 0) 310 aprint_normal(" port %d", bus->sda); 311 312 return UNCONF; 313 } 314 static int 315 piixpm_rescan(device_t self, const char *ifattr, const int *flags) 316 { 317 struct piixpm_softc *sc = device_private(self); 318 struct i2cbus_attach_args iba; 319 int i; 320 321 if (!ifattr_match(ifattr, "i2cbus")) 322 return 0; 323 324 /* Attach I2C bus */ 325 326 for (i = 0; i < sc->sc_numbusses; i++) { 327 if (sc->sc_i2c_device[i]) 328 continue; 329 sc->sc_busses[i].sda = i; 330 sc->sc_busses[i].softc = sc; 331 iic_tag_init(&sc->sc_i2c_tags[i]); 332 sc->sc_i2c_tags[i].ic_cookie = &sc->sc_busses[i]; 333 sc->sc_i2c_tags[i].ic_acquire_bus = piixpm_i2c_acquire_bus; 334 sc->sc_i2c_tags[i].ic_release_bus = piixpm_i2c_release_bus; 335 sc->sc_i2c_tags[i].ic_exec = piixpm_i2c_exec; 336 memset(&iba, 0, sizeof(iba)); 337 iba.iba_tag = &sc->sc_i2c_tags[i]; 338 sc->sc_i2c_device[i] = config_found_ia(self, ifattr, &iba, 339 piixpm_iicbus_print); 340 } 341 342 return 0; 343 } 344 345 static void 346 piixpm_chdet(device_t self, device_t child) 347 { 348 struct piixpm_softc *sc = device_private(self); 349 int i; 350 351 for (i = 0; i < sc->sc_numbusses; i++) { 352 if (sc->sc_i2c_device[i] == child) { 353 sc->sc_i2c_device[i] = NULL; 354 break; 355 } 356 } 357 } 358 359 360 static bool 361 piixpm_suspend(device_t dv, const pmf_qual_t *qual) 362 { 363 struct piixpm_softc *sc = device_private(dv); 364 365 sc->sc_devact[0] = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 366 PIIX_DEVACTA); 367 sc->sc_devact[1] = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 368 PIIX_DEVACTB); 369 370 return true; 371 } 372 373 static bool 374 piixpm_resume(device_t dv, const pmf_qual_t *qual) 375 { 376 struct piixpm_softc *sc = device_private(dv); 377 378 pci_conf_write(sc->sc_pc, sc->sc_pcitag, PIIX_DEVACTA, 379 sc->sc_devact[0]); 380 pci_conf_write(sc->sc_pc, sc->sc_pcitag, PIIX_DEVACTB, 381 sc->sc_devact[1]); 382 383 return true; 384 } 385 386 /* 387 * Extract SMBus base address from SB800 Power Management (PM) registers. 388 * The PM registers can be accessed either through indirect I/O (CD6/CD7) or 389 * direct mapping if AcpiMMioDecodeEn is enabled. Since this function is only 390 * called once it uses indirect I/O for simplicity. 391 */ 392 static int 393 piixpm_sb800_init(struct piixpm_softc *sc) 394 { 395 bus_space_tag_t iot = sc->sc_iot; 396 bus_space_handle_t ioh; /* indirect I/O handle */ 397 uint16_t val, base_addr; 398 bool enabled; 399 400 if (PIIXPM_IS_KERNCZ(sc) || 401 (PIIXPM_IS_HUDSON(sc) && (sc->sc_rev >= 0x1f))) 402 sc->sc_numbusses = 2; 403 else 404 sc->sc_numbusses = 4; 405 406 /* Fetch SMB base address */ 407 if (bus_space_map(iot, 408 SB800_INDIRECTIO_BASE, SB800_INDIRECTIO_SIZE, 0, &ioh)) { 409 device_printf(sc->sc_dev, "couldn't map indirect I/O space\n"); 410 return EBUSY; 411 } 412 if (PIIXPM_IS_FCHGRP(sc)) { 413 bus_space_write_1(iot, ioh, SB800_INDIRECTIO_INDEX, 414 AMDFCH41_PM_DECODE_EN0); 415 val = bus_space_read_1(iot, ioh, SB800_INDIRECTIO_DATA); 416 enabled = val & AMDFCH41_SMBUS_EN; 417 if (!enabled) 418 return ENOENT; 419 420 bus_space_write_1(iot, ioh, SB800_INDIRECTIO_INDEX, 421 AMDFCH41_PM_DECODE_EN1); 422 val = bus_space_read_1(iot, ioh, SB800_INDIRECTIO_DATA) << 8; 423 base_addr = val; 424 } else { 425 bus_space_write_1(iot, ioh, SB800_INDIRECTIO_INDEX, 426 SB800_PM_SMBUS0EN_LO); 427 val = bus_space_read_1(iot, ioh, SB800_INDIRECTIO_DATA); 428 enabled = val & SB800_PM_SMBUS0EN_ENABLE; 429 if (!enabled) 430 return ENOENT; 431 432 bus_space_write_1(iot, ioh, SB800_INDIRECTIO_INDEX, 433 SB800_PM_SMBUS0EN_HI); 434 val |= bus_space_read_1(iot, ioh, SB800_INDIRECTIO_DATA) << 8; 435 base_addr = val & SB800_PM_SMBUS0EN_BADDR; 436 437 bus_space_write_1(iot, ioh, SB800_INDIRECTIO_INDEX, 438 SB800_PM_SMBUS0SELEN); 439 bus_space_write_1(iot, ioh, SB800_INDIRECTIO_DATA, 440 SB800_PM_SMBUS0EN_ENABLE); 441 } 442 443 sc->sc_sb800_ioh = ioh; 444 aprint_debug_dev(sc->sc_dev, "SMBus @ 0x%04x\n", base_addr); 445 446 if (bus_space_map(iot, PCI_MAPREG_IO_ADDR(base_addr), 447 PIIX_SMB_SIZE, 0, &sc->sc_smb_ioh)) { 448 aprint_error_dev(sc->sc_dev, "can't map smbus I/O space\n"); 449 return EBUSY; 450 } 451 452 return 0; 453 } 454 455 static void 456 piixpm_csb5_reset(void *arg) 457 { 458 struct piixpm_softc *sc = arg; 459 pcireg_t base, hostc, pmbase; 460 461 base = pci_conf_read(sc->sc_pc, sc->sc_pcitag, PIIX_SMB_BASE); 462 hostc = pci_conf_read(sc->sc_pc, sc->sc_pcitag, PIIX_SMB_HOSTC); 463 464 pmbase = pci_conf_read(sc->sc_pc, sc->sc_pcitag, PIIX_PM_BASE); 465 pmbase |= PIIX_PM_BASE_CSB5_RESET; 466 pci_conf_write(sc->sc_pc, sc->sc_pcitag, PIIX_PM_BASE, pmbase); 467 pmbase &= ~PIIX_PM_BASE_CSB5_RESET; 468 pci_conf_write(sc->sc_pc, sc->sc_pcitag, PIIX_PM_BASE, pmbase); 469 470 pci_conf_write(sc->sc_pc, sc->sc_pcitag, PIIX_SMB_BASE, base); 471 pci_conf_write(sc->sc_pc, sc->sc_pcitag, PIIX_SMB_HOSTC, hostc); 472 473 (void) tsleep(&sc, PRIBIO, "csb5reset", hz/2); 474 } 475 476 static int 477 piixpm_i2c_acquire_bus(void *cookie, int flags) 478 { 479 struct piixpm_smbus *smbus = cookie; 480 struct piixpm_softc *sc = smbus->softc; 481 482 if (PIIXPM_IS_KERNCZ(sc)) { 483 bus_space_write_1(sc->sc_iot, sc->sc_sb800_ioh, 484 SB800_INDIRECTIO_INDEX, AMDFCH41_PM_PORT_INDEX); 485 bus_space_write_1(sc->sc_iot, sc->sc_sb800_ioh, 486 SB800_INDIRECTIO_DATA, smbus->sda << 3); 487 } else if (PIIXPM_IS_SB800GRP(sc) || PIIXPM_IS_HUDSON(sc)) { 488 bus_space_write_1(sc->sc_iot, sc->sc_sb800_ioh, 489 SB800_INDIRECTIO_INDEX, SB800_PM_SMBUS0SEL); 490 bus_space_write_1(sc->sc_iot, sc->sc_sb800_ioh, 491 SB800_INDIRECTIO_DATA, smbus->sda << 1); 492 } 493 494 return 0; 495 } 496 497 static void 498 piixpm_i2c_release_bus(void *cookie, int flags) 499 { 500 struct piixpm_smbus *smbus = cookie; 501 struct piixpm_softc *sc = smbus->softc; 502 503 if (PIIXPM_IS_KERNCZ(sc)) { 504 bus_space_write_1(sc->sc_iot, sc->sc_sb800_ioh, 505 SB800_INDIRECTIO_INDEX, AMDFCH41_PM_PORT_INDEX); 506 bus_space_write_1(sc->sc_iot, sc->sc_sb800_ioh, 507 SB800_INDIRECTIO_DATA, 0); 508 } else if (PIIXPM_IS_SB800GRP(sc) || PIIXPM_IS_HUDSON(sc)) { 509 /* 510 * HP Microserver hangs after reboot if not set to SDA0. 511 * Also add shutdown hook? 512 */ 513 bus_space_write_1(sc->sc_iot, sc->sc_sb800_ioh, 514 SB800_INDIRECTIO_INDEX, SB800_PM_SMBUS0SEL); 515 bus_space_write_1(sc->sc_iot, sc->sc_sb800_ioh, 516 SB800_INDIRECTIO_DATA, 0); 517 } 518 } 519 520 static int 521 piixpm_i2c_exec(void *cookie, i2c_op_t op, i2c_addr_t addr, 522 const void *cmdbuf, size_t cmdlen, void *buf, size_t len, int flags) 523 { 524 struct piixpm_smbus *smbus = cookie; 525 struct piixpm_softc *sc = smbus->softc; 526 const uint8_t *b; 527 uint8_t ctl = 0, st; 528 int retries; 529 530 DPRINTF(("%s: exec: op %d, addr 0x%02x, cmdlen %zu, len %zu, " 531 "flags 0x%x\n", 532 device_xname(sc->sc_dev), op, addr, cmdlen, len, flags)); 533 534 /* Clear status bits */ 535 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_HS, 536 PIIX_SMB_HS_INTR | PIIX_SMB_HS_DEVERR | 537 PIIX_SMB_HS_BUSERR | PIIX_SMB_HS_FAILED); 538 bus_space_barrier(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_HS, 1, 539 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 540 541 /* Wait for bus to be idle */ 542 for (retries = 100; retries > 0; retries--) { 543 st = bus_space_read_1(sc->sc_smb_iot, sc->sc_smb_ioh, 544 PIIX_SMB_HS); 545 if (!(st & PIIX_SMB_HS_BUSY)) 546 break; 547 DELAY(PIIXPM_DELAY); 548 } 549 DPRINTF(("%s: exec: st %#x\n", device_xname(sc->sc_dev), st & 0xff)); 550 if (st & PIIX_SMB_HS_BUSY) 551 return (1); 552 553 if (sc->sc_poll) 554 flags |= I2C_F_POLL; 555 556 if (!I2C_OP_STOP_P(op) || cmdlen > 1 || len > 2 || 557 (cmdlen == 0 && len > 1)) 558 return (1); 559 560 /* Setup transfer */ 561 sc->sc_i2c_xfer.op = op; 562 sc->sc_i2c_xfer.buf = buf; 563 sc->sc_i2c_xfer.len = len; 564 sc->sc_i2c_xfer.flags = flags; 565 sc->sc_i2c_xfer.error = 0; 566 567 /* Set slave address and transfer direction */ 568 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_TXSLVA, 569 PIIX_SMB_TXSLVA_ADDR(addr) | 570 (I2C_OP_READ_P(op) ? PIIX_SMB_TXSLVA_READ : 0)); 571 572 b = cmdbuf; 573 if (cmdlen > 0) 574 /* Set command byte */ 575 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, 576 PIIX_SMB_HCMD, b[0]); 577 578 if (I2C_OP_WRITE_P(op)) { 579 /* Write data */ 580 b = buf; 581 if (cmdlen == 0 && len == 1) 582 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, 583 PIIX_SMB_HCMD, b[0]); 584 else if (len > 0) 585 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, 586 PIIX_SMB_HD0, b[0]); 587 if (len > 1) 588 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, 589 PIIX_SMB_HD1, b[1]); 590 } 591 592 /* Set SMBus command */ 593 if (cmdlen == 0) { 594 if (len == 0) 595 ctl = PIIX_SMB_HC_CMD_QUICK; 596 else 597 ctl = PIIX_SMB_HC_CMD_BYTE; 598 } else if (len == 1) 599 ctl = PIIX_SMB_HC_CMD_BDATA; 600 else if (len == 2) 601 ctl = PIIX_SMB_HC_CMD_WDATA; 602 else 603 panic("%s: unexpected len %zu", __func__, len); 604 605 if ((flags & I2C_F_POLL) == 0) 606 ctl |= PIIX_SMB_HC_INTREN; 607 608 /* Start transaction */ 609 ctl |= PIIX_SMB_HC_START; 610 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_HC, ctl); 611 612 if (flags & I2C_F_POLL) { 613 /* Poll for completion */ 614 if (PIIXPM_IS_CSB5(sc)) 615 DELAY(2*PIIXPM_DELAY); 616 else 617 DELAY(PIIXPM_DELAY); 618 for (retries = 1000; retries > 0; retries--) { 619 st = bus_space_read_1(sc->sc_smb_iot, sc->sc_smb_ioh, 620 PIIX_SMB_HS); 621 if ((st & PIIX_SMB_HS_BUSY) == 0) 622 break; 623 DELAY(PIIXPM_DELAY); 624 } 625 if (st & PIIX_SMB_HS_BUSY) 626 goto timeout; 627 piixpm_intr(sc); 628 } else { 629 /* Wait for interrupt */ 630 if (tsleep(sc, PRIBIO, "piixpm", PIIXPM_TIMEOUT * hz)) 631 goto timeout; 632 } 633 634 if (sc->sc_i2c_xfer.error) 635 return (1); 636 637 return (0); 638 639 timeout: 640 /* 641 * Transfer timeout. Kill the transaction and clear status bits. 642 */ 643 aprint_error_dev(sc->sc_dev, "timeout, status 0x%x\n", st); 644 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_HC, 645 PIIX_SMB_HC_KILL); 646 DELAY(PIIXPM_DELAY); 647 st = bus_space_read_1(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_HS); 648 if ((st & PIIX_SMB_HS_FAILED) == 0) 649 aprint_error_dev(sc->sc_dev, 650 "transaction abort failed, status 0x%x\n", st); 651 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_HS, st); 652 /* 653 * CSB5 needs hard reset to unlock the smbus after timeout. 654 */ 655 if (PIIXPM_IS_CSB5(sc)) 656 piixpm_csb5_reset(sc); 657 return (1); 658 } 659 660 static int 661 piixpm_intr(void *arg) 662 { 663 struct piixpm_softc *sc = arg; 664 uint8_t st; 665 uint8_t *b; 666 size_t len; 667 668 /* Read status */ 669 st = bus_space_read_1(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_HS); 670 if ((st & PIIX_SMB_HS_BUSY) != 0 || (st & (PIIX_SMB_HS_INTR | 671 PIIX_SMB_HS_DEVERR | PIIX_SMB_HS_BUSERR | 672 PIIX_SMB_HS_FAILED)) == 0) 673 /* Interrupt was not for us */ 674 return (0); 675 676 DPRINTF(("%s: intr st %#x\n", device_xname(sc->sc_dev), st & 0xff)); 677 678 /* Clear status bits */ 679 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_HS, st); 680 681 /* Check for errors */ 682 if (st & (PIIX_SMB_HS_DEVERR | PIIX_SMB_HS_BUSERR | 683 PIIX_SMB_HS_FAILED)) { 684 sc->sc_i2c_xfer.error = 1; 685 goto done; 686 } 687 688 if (st & PIIX_SMB_HS_INTR) { 689 if (I2C_OP_WRITE_P(sc->sc_i2c_xfer.op)) 690 goto done; 691 692 /* Read data */ 693 b = sc->sc_i2c_xfer.buf; 694 len = sc->sc_i2c_xfer.len; 695 if (len > 0) 696 b[0] = bus_space_read_1(sc->sc_smb_iot, sc->sc_smb_ioh, 697 PIIX_SMB_HD0); 698 if (len > 1) 699 b[1] = bus_space_read_1(sc->sc_smb_iot, sc->sc_smb_ioh, 700 PIIX_SMB_HD1); 701 } 702 703 done: 704 if ((sc->sc_i2c_xfer.flags & I2C_F_POLL) == 0) 705 wakeup(sc); 706 return (1); 707 } 708
Indexes created Mon Sep 29 21:09:56 GMT 2025