piixpm.c revision 1.58
1 /* $NetBSD: piixpm.c,v 1.58 2019/12/23 23:41:43 msaitoh Exp $ */ 2 /* $OpenBSD: piixpm.c,v 1.39 2013/10/01 20:06:02 sf Exp $ */ 3 4 /* 5 * Copyright (c) 2005, 2006 Alexander Yurchenko <grange (at) openbsd.org> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 /* 21 * Intel PIIX and compatible Power Management controller driver. 22 */ 23 24 #include <sys/cdefs.h> 25 __KERNEL_RCSID(0, "$NetBSD: piixpm.c,v 1.58 2019/12/23 23:41:43 msaitoh Exp $"); 26 27 #include <sys/param.h> 28 #include <sys/systm.h> 29 #include <sys/device.h> 30 #include <sys/kernel.h> 31 #include <sys/mutex.h> 32 #include <sys/proc.h> 33 34 #include <sys/bus.h> 35 36 #include <dev/pci/pcidevs.h> 37 #include <dev/pci/pcireg.h> 38 #include <dev/pci/pcivar.h> 39 40 #include <dev/pci/piixpmreg.h> 41 42 #include <dev/i2c/i2cvar.h> 43 44 #include <dev/ic/acpipmtimer.h> 45 46 #ifdef PIIXPM_DEBUG 47 #define DPRINTF(x) printf x 48 #else 49 #define DPRINTF(x) 50 #endif 51 52 #define PIIXPM_IS_CSB5(sc) \ 53 (PCI_VENDOR((sc)->sc_id) == PCI_VENDOR_SERVERWORKS && \ 54 PCI_PRODUCT((sc)->sc_id) == PCI_PRODUCT_SERVERWORKS_CSB5) 55 #define PIIXPM_DELAY 200 56 #define PIIXPM_TIMEOUT 1 57 58 #define PIIXPM_IS_SB800GRP(sc) \ 59 ((PCI_VENDOR((sc)->sc_id) == PCI_VENDOR_ATI) && \ 60 ((PCI_PRODUCT((sc)->sc_id) == PCI_PRODUCT_ATI_SB600_SMB) && \ 61 ((sc)->sc_rev >= 0x40))) 62 63 #define PIIXPM_IS_HUDSON(sc) \ 64 ((PCI_VENDOR((sc)->sc_id) == PCI_VENDOR_AMD) && \ 65 (PCI_PRODUCT((sc)->sc_id) == PCI_PRODUCT_AMD_HUDSON_SMB)) 66 67 #define PIIXPM_IS_KERNCZ(sc) \ 68 ((PCI_VENDOR((sc)->sc_id) == PCI_VENDOR_AMD) && \ 69 (PCI_PRODUCT((sc)->sc_id) == PCI_PRODUCT_AMD_KERNCZ_SMB)) 70 71 #define PIIXPM_IS_FCHGRP(sc) (PIIXPM_IS_HUDSON(sc) || PIIXPM_IS_KERNCZ(sc)) 72 73 struct piixpm_smbus { 74 int sda; 75 struct piixpm_softc *softc; 76 }; 77 78 struct piixpm_softc { 79 device_t sc_dev; 80 81 bus_space_tag_t sc_iot; 82 #define sc_pm_iot sc_iot 83 #define sc_smb_iot sc_iot 84 bus_space_handle_t sc_pm_ioh; 85 bus_space_handle_t sc_sb800_ioh; 86 bus_space_handle_t sc_smb_ioh; 87 void * sc_smb_ih; 88 int sc_poll; 89 90 pci_chipset_tag_t sc_pc; 91 pcitag_t sc_pcitag; 92 pcireg_t sc_id; 93 pcireg_t sc_rev; 94 95 int sc_numbusses; 96 device_t sc_i2c_device[4]; 97 struct piixpm_smbus sc_busses[4]; 98 struct i2c_controller sc_i2c_tags[4]; 99 100 struct { 101 i2c_op_t op; 102 void * buf; 103 size_t len; 104 int flags; 105 volatile int error; 106 } sc_i2c_xfer; 107 108 pcireg_t sc_devact[2]; 109 }; 110 111 static int piixpm_match(device_t, cfdata_t, void *); 112 static void piixpm_attach(device_t, device_t, void *); 113 static int piixpm_rescan(device_t, const char *, const int *); 114 static void piixpm_chdet(device_t, device_t); 115 116 static bool piixpm_suspend(device_t, const pmf_qual_t *); 117 static bool piixpm_resume(device_t, const pmf_qual_t *); 118 119 static int piixpm_sb800_init(struct piixpm_softc *); 120 static void piixpm_csb5_reset(void *); 121 static int piixpm_i2c_acquire_bus(void *, int); 122 static void piixpm_i2c_release_bus(void *, int); 123 static int piixpm_i2c_exec(void *, i2c_op_t, i2c_addr_t, const void *, 124 size_t, void *, size_t, int); 125 126 static int piixpm_intr(void *); 127 128 CFATTACH_DECL3_NEW(piixpm, sizeof(struct piixpm_softc), 129 piixpm_match, piixpm_attach, NULL, NULL, piixpm_rescan, piixpm_chdet, 0); 130 131 static int 132 piixpm_match(device_t parent, cfdata_t match, void *aux) 133 { 134 struct pci_attach_args *pa; 135 136 pa = (struct pci_attach_args *)aux; 137 switch (PCI_VENDOR(pa->pa_id)) { 138 case PCI_VENDOR_INTEL: 139 switch (PCI_PRODUCT(pa->pa_id)) { 140 case PCI_PRODUCT_INTEL_82371AB_PMC: 141 case PCI_PRODUCT_INTEL_82440MX_PMC: 142 return 1; 143 } 144 break; 145 case PCI_VENDOR_ATI: 146 switch (PCI_PRODUCT(pa->pa_id)) { 147 case PCI_PRODUCT_ATI_SB200_SMB: 148 case PCI_PRODUCT_ATI_SB300_SMB: 149 case PCI_PRODUCT_ATI_SB400_SMB: 150 case PCI_PRODUCT_ATI_SB600_SMB: /* matches SB600/SB700/SB800 */ 151 return 1; 152 } 153 break; 154 case PCI_VENDOR_SERVERWORKS: 155 switch (PCI_PRODUCT(pa->pa_id)) { 156 case PCI_PRODUCT_SERVERWORKS_OSB4: 157 case PCI_PRODUCT_SERVERWORKS_CSB5: 158 case PCI_PRODUCT_SERVERWORKS_CSB6: 159 case PCI_PRODUCT_SERVERWORKS_HT1000SB: 160 case PCI_PRODUCT_SERVERWORKS_HT1100SB: 161 return 1; 162 } 163 break; 164 case PCI_VENDOR_AMD: 165 switch (PCI_PRODUCT(pa->pa_id)) { 166 case PCI_PRODUCT_AMD_HUDSON_SMB: 167 case PCI_PRODUCT_AMD_KERNCZ_SMB: 168 return 1; 169 } 170 break; 171 } 172 173 return 0; 174 } 175 176 static void 177 piixpm_attach(device_t parent, device_t self, void *aux) 178 { 179 struct piixpm_softc *sc = device_private(self); 180 struct pci_attach_args *pa = aux; 181 pcireg_t base, conf; 182 pcireg_t pmmisc; 183 pci_intr_handle_t ih; 184 bool usesmi = false; 185 const char *intrstr = NULL; 186 int i, flags; 187 char intrbuf[PCI_INTRSTR_LEN]; 188 189 sc->sc_dev = self; 190 sc->sc_iot = pa->pa_iot; 191 sc->sc_id = pa->pa_id; 192 sc->sc_rev = PCI_REVISION(pa->pa_class); 193 sc->sc_pc = pa->pa_pc; 194 sc->sc_pcitag = pa->pa_tag; 195 sc->sc_numbusses = 1; 196 197 pci_aprint_devinfo(pa, NULL); 198 199 if (!pmf_device_register(self, piixpm_suspend, piixpm_resume)) 200 aprint_error_dev(self, "couldn't establish power handler\n"); 201 202 if ((PCI_VENDOR(pa->pa_id) != PCI_VENDOR_INTEL) || 203 (PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_INTEL_82371AB_PMC)) 204 goto nopowermanagement; 205 206 /* check whether I/O access to PM regs is enabled */ 207 pmmisc = pci_conf_read(pa->pa_pc, pa->pa_tag, PIIX_PMREGMISC); 208 if (!(pmmisc & 1)) 209 goto nopowermanagement; 210 211 /* Map I/O space */ 212 base = pci_conf_read(pa->pa_pc, pa->pa_tag, PIIX_PM_BASE); 213 if (base == 0 || bus_space_map(sc->sc_pm_iot, PCI_MAPREG_IO_ADDR(base), 214 PIIX_PM_SIZE, 0, &sc->sc_pm_ioh)) { 215 aprint_error_dev(self, 216 "can't map power management I/O space\n"); 217 goto nopowermanagement; 218 } 219 220 /* 221 * Revision 0 and 1 are PIIX4, 2 is PIIX4E, 3 is PIIX4M. 222 * PIIX4 and PIIX4E have a bug in the timer latch, see Errata #20 223 * in the "Specification update" (document #297738). 224 */ 225 acpipmtimer_attach(self, sc->sc_pm_iot, sc->sc_pm_ioh, PIIX_PM_PMTMR, 226 (PCI_REVISION(pa->pa_class) < 3) ? ACPIPMT_BADLATCH : 0); 227 228 nopowermanagement: 229 230 /* SB800 rev 0x40+, AMD HUDSON and newer need special initialization */ 231 if (PIIXPM_IS_FCHGRP(sc) || PIIXPM_IS_SB800GRP(sc)) { 232 if (piixpm_sb800_init(sc) == 0) { 233 /* Read configuration */ 234 conf = bus_space_read_1(sc->sc_iot, 235 sc->sc_smb_ioh, SB800_SMB_HOSTC); 236 usesmi = ((conf & SB800_SMB_HOSTC_IRQ) == 0); 237 goto setintr; 238 } 239 aprint_normal_dev(self, "SMBus initialization failed\n"); 240 return; 241 } 242 243 /* Read configuration */ 244 conf = pci_conf_read(pa->pa_pc, pa->pa_tag, PIIX_SMB_HOSTC); 245 DPRINTF(("%s: conf 0x%08x\n", device_xname(self), conf)); 246 247 if ((conf & PIIX_SMB_HOSTC_HSTEN) == 0) { 248 aprint_normal_dev(self, "SMBus disabled\n"); 249 return; 250 } 251 usesmi = (conf & PIIX_SMB_HOSTC_INTMASK) == PIIX_SMB_HOSTC_SMI; 252 253 /* Map I/O space */ 254 base = pci_conf_read(pa->pa_pc, pa->pa_tag, PIIX_SMB_BASE) & 0xffff; 255 if (base == 0 || 256 bus_space_map(sc->sc_smb_iot, PCI_MAPREG_IO_ADDR(base), 257 PIIX_SMB_SIZE, 0, &sc->sc_smb_ioh)) { 258 aprint_error_dev(self, "can't map smbus I/O space\n"); 259 return; 260 } 261 262 setintr: 263 sc->sc_poll = 1; 264 aprint_normal_dev(self, ""); 265 if (usesmi) { 266 /* No PCI IRQ */ 267 aprint_normal("interrupting at SMI, "); 268 } else { 269 if ((conf & PIIX_SMB_HOSTC_INTMASK) == PIIX_SMB_HOSTC_IRQ) { 270 /* Install interrupt handler */ 271 if (pci_intr_map(pa, &ih) == 0) { 272 intrstr = pci_intr_string(pa->pa_pc, ih, 273 intrbuf, sizeof(intrbuf)); 274 sc->sc_smb_ih = pci_intr_establish_xname( 275 pa->pa_pc, ih, IPL_BIO, piixpm_intr, 276 sc, device_xname(sc->sc_dev)); 277 if (sc->sc_smb_ih != NULL) { 278 aprint_normal("interrupting at %s", 279 intrstr); 280 sc->sc_poll = 0; 281 } 282 } 283 } 284 if (sc->sc_poll) 285 aprint_normal("polling"); 286 } 287 288 aprint_normal("\n"); 289 290 for (i = 0; i < sc->sc_numbusses; i++) 291 sc->sc_i2c_device[i] = NULL; 292 293 flags = 0; 294 piixpm_rescan(self, "i2cbus", &flags); 295 } 296 297 static int 298 piixpm_iicbus_print(void *aux, const char *pnp) 299 { 300 struct i2cbus_attach_args *iba = aux; 301 struct i2c_controller *tag = iba->iba_tag; 302 struct piixpm_smbus *bus = tag->ic_cookie; 303 struct piixpm_softc *sc = bus->softc; 304 305 iicbus_print(aux, pnp); 306 if (sc->sc_numbusses != 0) 307 aprint_normal(" port %d", bus->sda); 308 309 return UNCONF; 310 } 311 static int 312 piixpm_rescan(device_t self, const char *ifattr, const int *flags) 313 { 314 struct piixpm_softc *sc = device_private(self); 315 struct i2cbus_attach_args iba; 316 int i; 317 318 if (!ifattr_match(ifattr, "i2cbus")) 319 return 0; 320 321 /* Attach I2C bus */ 322 323 for (i = 0; i < sc->sc_numbusses; i++) { 324 if (sc->sc_i2c_device[i]) 325 continue; 326 sc->sc_busses[i].sda = i; 327 sc->sc_busses[i].softc = sc; 328 iic_tag_init(&sc->sc_i2c_tags[i]); 329 sc->sc_i2c_tags[i].ic_cookie = &sc->sc_busses[i]; 330 sc->sc_i2c_tags[i].ic_acquire_bus = piixpm_i2c_acquire_bus; 331 sc->sc_i2c_tags[i].ic_release_bus = piixpm_i2c_release_bus; 332 sc->sc_i2c_tags[i].ic_exec = piixpm_i2c_exec; 333 memset(&iba, 0, sizeof(iba)); 334 iba.iba_tag = &sc->sc_i2c_tags[i]; 335 sc->sc_i2c_device[i] = config_found_ia(self, ifattr, &iba, 336 piixpm_iicbus_print); 337 } 338 339 return 0; 340 } 341 342 static void 343 piixpm_chdet(device_t self, device_t child) 344 { 345 struct piixpm_softc *sc = device_private(self); 346 int i; 347 348 for (i = 0; i < sc->sc_numbusses; i++) { 349 if (sc->sc_i2c_device[i] == child) { 350 sc->sc_i2c_device[i] = NULL; 351 break; 352 } 353 } 354 } 355 356 357 static bool 358 piixpm_suspend(device_t dv, const pmf_qual_t *qual) 359 { 360 struct piixpm_softc *sc = device_private(dv); 361 362 sc->sc_devact[0] = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 363 PIIX_DEVACTA); 364 sc->sc_devact[1] = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 365 PIIX_DEVACTB); 366 367 return true; 368 } 369 370 static bool 371 piixpm_resume(device_t dv, const pmf_qual_t *qual) 372 { 373 struct piixpm_softc *sc = device_private(dv); 374 375 pci_conf_write(sc->sc_pc, sc->sc_pcitag, PIIX_DEVACTA, 376 sc->sc_devact[0]); 377 pci_conf_write(sc->sc_pc, sc->sc_pcitag, PIIX_DEVACTB, 378 sc->sc_devact[1]); 379 380 return true; 381 } 382 383 /* 384 * Extract SMBus base address from SB800 Power Management (PM) registers. 385 * The PM registers can be accessed either through indirect I/O (CD6/CD7) or 386 * direct mapping if AcpiMMioDecodeEn is enabled. Since this function is only 387 * called once it uses indirect I/O for simplicity. 388 */ 389 static int 390 piixpm_sb800_init(struct piixpm_softc *sc) 391 { 392 bus_space_tag_t iot = sc->sc_iot; 393 bus_space_handle_t ioh; /* indirect I/O handle */ 394 uint16_t val, base_addr; 395 bool enabled; 396 397 if (PIIXPM_IS_KERNCZ(sc) || 398 (PIIXPM_IS_HUDSON(sc) && (sc->sc_rev >= 0x1f))) 399 sc->sc_numbusses = 2; 400 else 401 sc->sc_numbusses = 4; 402 403 /* Fetch SMB base address */ 404 if (bus_space_map(iot, 405 SB800_INDIRECTIO_BASE, SB800_INDIRECTIO_SIZE, 0, &ioh)) { 406 device_printf(sc->sc_dev, "couldn't map indirect I/O space\n"); 407 return EBUSY; 408 } 409 if (PIIXPM_IS_FCHGRP(sc)) { 410 bus_space_write_1(iot, ioh, SB800_INDIRECTIO_INDEX, 411 AMDFCH41_PM_DECODE_EN0); 412 val = bus_space_read_1(iot, ioh, SB800_INDIRECTIO_DATA); 413 enabled = val & AMDFCH41_SMBUS_EN; 414 if (!enabled) 415 return ENOENT; 416 417 bus_space_write_1(iot, ioh, SB800_INDIRECTIO_INDEX, 418 AMDFCH41_PM_DECODE_EN1); 419 val = bus_space_read_1(iot, ioh, SB800_INDIRECTIO_DATA) << 8; 420 base_addr = val; 421 } else { 422 bus_space_write_1(iot, ioh, SB800_INDIRECTIO_INDEX, 423 SB800_PM_SMBUS0EN_LO); 424 val = bus_space_read_1(iot, ioh, SB800_INDIRECTIO_DATA); 425 enabled = val & SB800_PM_SMBUS0EN_ENABLE; 426 if (!enabled) 427 return ENOENT; 428 429 bus_space_write_1(iot, ioh, SB800_INDIRECTIO_INDEX, 430 SB800_PM_SMBUS0EN_HI); 431 val |= bus_space_read_1(iot, ioh, SB800_INDIRECTIO_DATA) << 8; 432 base_addr = val & SB800_PM_SMBUS0EN_BADDR; 433 434 bus_space_write_1(iot, ioh, SB800_INDIRECTIO_INDEX, 435 SB800_PM_SMBUS0SELEN); 436 bus_space_write_1(iot, ioh, SB800_INDIRECTIO_DATA, 437 SB800_PM_SMBUS0EN_ENABLE); 438 } 439 440 sc->sc_sb800_ioh = ioh; 441 aprint_debug_dev(sc->sc_dev, "SMBus @ 0x%04x\n", base_addr); 442 443 if (bus_space_map(iot, PCI_MAPREG_IO_ADDR(base_addr), 444 SB800_SMB_SIZE, 0, &sc->sc_smb_ioh)) { 445 aprint_error_dev(sc->sc_dev, "can't map smbus I/O space\n"); 446 return EBUSY; 447 } 448 449 return 0; 450 } 451 452 static void 453 piixpm_csb5_reset(void *arg) 454 { 455 struct piixpm_softc *sc = arg; 456 pcireg_t base, hostc, pmbase; 457 458 base = pci_conf_read(sc->sc_pc, sc->sc_pcitag, PIIX_SMB_BASE); 459 hostc = pci_conf_read(sc->sc_pc, sc->sc_pcitag, PIIX_SMB_HOSTC); 460 461 pmbase = pci_conf_read(sc->sc_pc, sc->sc_pcitag, PIIX_PM_BASE); 462 pmbase |= PIIX_PM_BASE_CSB5_RESET; 463 pci_conf_write(sc->sc_pc, sc->sc_pcitag, PIIX_PM_BASE, pmbase); 464 pmbase &= ~PIIX_PM_BASE_CSB5_RESET; 465 pci_conf_write(sc->sc_pc, sc->sc_pcitag, PIIX_PM_BASE, pmbase); 466 467 pci_conf_write(sc->sc_pc, sc->sc_pcitag, PIIX_SMB_BASE, base); 468 pci_conf_write(sc->sc_pc, sc->sc_pcitag, PIIX_SMB_HOSTC, hostc); 469 470 (void) tsleep(&sc, PRIBIO, "csb5reset", hz/2); 471 } 472 473 static int 474 piixpm_i2c_acquire_bus(void *cookie, int flags) 475 { 476 struct piixpm_smbus *smbus = cookie; 477 struct piixpm_softc *sc = smbus->softc; 478 479 if (PIIXPM_IS_KERNCZ(sc)) { 480 bus_space_write_1(sc->sc_iot, sc->sc_sb800_ioh, 481 SB800_INDIRECTIO_INDEX, AMDFCH41_PM_PORT_INDEX); 482 bus_space_write_1(sc->sc_iot, sc->sc_sb800_ioh, 483 SB800_INDIRECTIO_DATA, smbus->sda << 3); 484 } else if (PIIXPM_IS_SB800GRP(sc) || PIIXPM_IS_HUDSON(sc)) { 485 bus_space_write_1(sc->sc_iot, sc->sc_sb800_ioh, 486 SB800_INDIRECTIO_INDEX, SB800_PM_SMBUS0SEL); 487 bus_space_write_1(sc->sc_iot, sc->sc_sb800_ioh, 488 SB800_INDIRECTIO_DATA, smbus->sda << 1); 489 } 490 491 return 0; 492 } 493 494 static void 495 piixpm_i2c_release_bus(void *cookie, int flags) 496 { 497 struct piixpm_smbus *smbus = cookie; 498 struct piixpm_softc *sc = smbus->softc; 499 500 if (PIIXPM_IS_KERNCZ(sc)) { 501 bus_space_write_1(sc->sc_iot, sc->sc_sb800_ioh, 502 SB800_INDIRECTIO_INDEX, AMDFCH41_PM_PORT_INDEX); 503 bus_space_write_1(sc->sc_iot, sc->sc_sb800_ioh, 504 SB800_INDIRECTIO_DATA, 0); 505 } else if (PIIXPM_IS_SB800GRP(sc) || PIIXPM_IS_HUDSON(sc)) { 506 /* 507 * HP Microserver hangs after reboot if not set to SDA0. 508 * Also add shutdown hook? 509 */ 510 bus_space_write_1(sc->sc_iot, sc->sc_sb800_ioh, 511 SB800_INDIRECTIO_INDEX, SB800_PM_SMBUS0SEL); 512 bus_space_write_1(sc->sc_iot, sc->sc_sb800_ioh, 513 SB800_INDIRECTIO_DATA, 0); 514 } 515 } 516 517 static int 518 piixpm_i2c_exec(void *cookie, i2c_op_t op, i2c_addr_t addr, 519 const void *cmdbuf, size_t cmdlen, void *buf, size_t len, int flags) 520 { 521 struct piixpm_smbus *smbus = cookie; 522 struct piixpm_softc *sc = smbus->softc; 523 const uint8_t *b; 524 uint8_t ctl = 0, st; 525 int retries; 526 527 DPRINTF(("%s: exec: op %d, addr 0x%02x, cmdlen %zu, len %zu, " 528 "flags 0x%x\n", 529 device_xname(sc->sc_dev), op, addr, cmdlen, len, flags)); 530 531 /* Clear status bits */ 532 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_HS, 533 PIIX_SMB_HS_INTR | PIIX_SMB_HS_DEVERR | 534 PIIX_SMB_HS_BUSERR | PIIX_SMB_HS_FAILED); 535 bus_space_barrier(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_HS, 1, 536 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 537 538 /* Wait for bus to be idle */ 539 for (retries = 100; retries > 0; retries--) { 540 st = bus_space_read_1(sc->sc_smb_iot, sc->sc_smb_ioh, 541 PIIX_SMB_HS); 542 if (!(st & PIIX_SMB_HS_BUSY)) 543 break; 544 DELAY(PIIXPM_DELAY); 545 } 546 DPRINTF(("%s: exec: st %#x\n", device_xname(sc->sc_dev), st & 0xff)); 547 if (st & PIIX_SMB_HS_BUSY) 548 return (1); 549 550 if (sc->sc_poll) 551 flags |= I2C_F_POLL; 552 553 if (!I2C_OP_STOP_P(op) || cmdlen > 1 || len > 2 || 554 (cmdlen == 0 && len > 1)) 555 return (1); 556 557 /* Setup transfer */ 558 sc->sc_i2c_xfer.op = op; 559 sc->sc_i2c_xfer.buf = buf; 560 sc->sc_i2c_xfer.len = len; 561 sc->sc_i2c_xfer.flags = flags; 562 sc->sc_i2c_xfer.error = 0; 563 564 /* Set slave address and transfer direction */ 565 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_TXSLVA, 566 PIIX_SMB_TXSLVA_ADDR(addr) | 567 (I2C_OP_READ_P(op) ? PIIX_SMB_TXSLVA_READ : 0)); 568 569 b = cmdbuf; 570 if (cmdlen > 0) 571 /* Set command byte */ 572 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, 573 PIIX_SMB_HCMD, b[0]); 574 575 if (I2C_OP_WRITE_P(op)) { 576 /* Write data */ 577 b = buf; 578 if (cmdlen == 0 && len == 1) 579 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, 580 PIIX_SMB_HCMD, b[0]); 581 else if (len > 0) 582 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, 583 PIIX_SMB_HD0, b[0]); 584 if (len > 1) 585 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, 586 PIIX_SMB_HD1, b[1]); 587 } 588 589 /* Set SMBus command */ 590 if (cmdlen == 0) { 591 if (len == 0) 592 ctl = PIIX_SMB_HC_CMD_QUICK; 593 else 594 ctl = PIIX_SMB_HC_CMD_BYTE; 595 } else if (len == 1) 596 ctl = PIIX_SMB_HC_CMD_BDATA; 597 else if (len == 2) 598 ctl = PIIX_SMB_HC_CMD_WDATA; 599 else 600 panic("%s: unexpected len %zu", __func__, len); 601 602 if ((flags & I2C_F_POLL) == 0) 603 ctl |= PIIX_SMB_HC_INTREN; 604 605 /* Start transaction */ 606 ctl |= PIIX_SMB_HC_START; 607 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_HC, ctl); 608 609 if (flags & I2C_F_POLL) { 610 /* Poll for completion */ 611 if (PIIXPM_IS_CSB5(sc)) 612 DELAY(2*PIIXPM_DELAY); 613 else 614 DELAY(PIIXPM_DELAY); 615 for (retries = 1000; retries > 0; retries--) { 616 st = bus_space_read_1(sc->sc_smb_iot, sc->sc_smb_ioh, 617 PIIX_SMB_HS); 618 if ((st & PIIX_SMB_HS_BUSY) == 0) 619 break; 620 DELAY(PIIXPM_DELAY); 621 } 622 if (st & PIIX_SMB_HS_BUSY) 623 goto timeout; 624 piixpm_intr(sc); 625 } else { 626 /* Wait for interrupt */ 627 if (tsleep(sc, PRIBIO, "piixpm", PIIXPM_TIMEOUT * hz)) 628 goto timeout; 629 } 630 631 if (sc->sc_i2c_xfer.error) 632 return (1); 633 634 return (0); 635 636 timeout: 637 /* 638 * Transfer timeout. Kill the transaction and clear status bits. 639 */ 640 aprint_error_dev(sc->sc_dev, "timeout, status 0x%x\n", st); 641 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_HC, 642 PIIX_SMB_HC_KILL); 643 DELAY(PIIXPM_DELAY); 644 st = bus_space_read_1(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_HS); 645 if ((st & PIIX_SMB_HS_FAILED) == 0) 646 aprint_error_dev(sc->sc_dev, 647 "transaction abort failed, status 0x%x\n", st); 648 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_HS, st); 649 /* 650 * CSB5 needs hard reset to unlock the smbus after timeout. 651 */ 652 if (PIIXPM_IS_CSB5(sc)) 653 piixpm_csb5_reset(sc); 654 return (1); 655 } 656 657 static int 658 piixpm_intr(void *arg) 659 { 660 struct piixpm_softc *sc = arg; 661 uint8_t st; 662 uint8_t *b; 663 size_t len; 664 665 /* Read status */ 666 st = bus_space_read_1(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_HS); 667 if ((st & PIIX_SMB_HS_BUSY) != 0 || (st & (PIIX_SMB_HS_INTR | 668 PIIX_SMB_HS_DEVERR | PIIX_SMB_HS_BUSERR | 669 PIIX_SMB_HS_FAILED)) == 0) 670 /* Interrupt was not for us */ 671 return (0); 672 673 DPRINTF(("%s: intr st %#x\n", device_xname(sc->sc_dev), st & 0xff)); 674 675 /* Clear status bits */ 676 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_HS, st); 677 678 /* Check for errors */ 679 if (st & (PIIX_SMB_HS_DEVERR | PIIX_SMB_HS_BUSERR | 680 PIIX_SMB_HS_FAILED)) { 681 sc->sc_i2c_xfer.error = 1; 682 goto done; 683 } 684 685 if (st & PIIX_SMB_HS_INTR) { 686 if (I2C_OP_WRITE_P(sc->sc_i2c_xfer.op)) 687 goto done; 688 689 /* Read data */ 690 b = sc->sc_i2c_xfer.buf; 691 len = sc->sc_i2c_xfer.len; 692 if (len > 0) 693 b[0] = bus_space_read_1(sc->sc_smb_iot, sc->sc_smb_ioh, 694 PIIX_SMB_HD0); 695 if (len > 1) 696 b[1] = bus_space_read_1(sc->sc_smb_iot, sc->sc_smb_ioh, 697 PIIX_SMB_HD1); 698 } 699 700 done: 701 if ((sc->sc_i2c_xfer.flags & I2C_F_POLL) == 0) 702 wakeup(sc); 703 return (1); 704 } 705
Indexes created Mon Sep 29 18:09:42 GMT 2025