piixpm.c revision 1.60
1 /* $NetBSD: piixpm.c,v 1.60 2019/12/24 06:27:17 thorpej Exp $ */ 2 /* $OpenBSD: piixpm.c,v 1.39 2013/10/01 20:06:02 sf Exp $ */ 3 4 /* 5 * Copyright (c) 2005, 2006 Alexander Yurchenko <grange (at) openbsd.org> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 /* 21 * Intel PIIX and compatible Power Management controller driver. 22 */ 23 24 #include <sys/cdefs.h> 25 __KERNEL_RCSID(0, "$NetBSD: piixpm.c,v 1.60 2019/12/24 06:27:17 thorpej Exp $"); 26 27 #include <sys/param.h> 28 #include <sys/systm.h> 29 #include <sys/device.h> 30 #include <sys/kernel.h> 31 #include <sys/mutex.h> 32 #include <sys/condvar.h> 33 #include <sys/proc.h> 34 35 #include <sys/bus.h> 36 37 #include <dev/pci/pcidevs.h> 38 #include <dev/pci/pcireg.h> 39 #include <dev/pci/pcivar.h> 40 41 #include <dev/pci/piixpmreg.h> 42 43 #include <dev/i2c/i2cvar.h> 44 45 #include <dev/ic/acpipmtimer.h> 46 47 #ifdef PIIXPM_DEBUG 48 #define DPRINTF(x) printf x 49 #else 50 #define DPRINTF(x) 51 #endif 52 53 #define PIIXPM_IS_CSB5(sc) \ 54 (PCI_VENDOR((sc)->sc_id) == PCI_VENDOR_SERVERWORKS && \ 55 PCI_PRODUCT((sc)->sc_id) == PCI_PRODUCT_SERVERWORKS_CSB5) 56 #define PIIXPM_DELAY 200 57 #define PIIXPM_TIMEOUT 1 58 59 #define PIIXPM_IS_SB800GRP(sc) \ 60 ((PCI_VENDOR((sc)->sc_id) == PCI_VENDOR_ATI) && \ 61 ((PCI_PRODUCT((sc)->sc_id) == PCI_PRODUCT_ATI_SB600_SMB) && \ 62 ((sc)->sc_rev >= 0x40))) 63 64 #define PIIXPM_IS_HUDSON(sc) \ 65 ((PCI_VENDOR((sc)->sc_id) == PCI_VENDOR_AMD) && \ 66 (PCI_PRODUCT((sc)->sc_id) == PCI_PRODUCT_AMD_HUDSON_SMB)) 67 68 #define PIIXPM_IS_KERNCZ(sc) \ 69 ((PCI_VENDOR((sc)->sc_id) == PCI_VENDOR_AMD) && \ 70 (PCI_PRODUCT((sc)->sc_id) == PCI_PRODUCT_AMD_KERNCZ_SMB)) 71 72 #define PIIXPM_IS_FCHGRP(sc) (PIIXPM_IS_HUDSON(sc) || PIIXPM_IS_KERNCZ(sc)) 73 74 struct piixpm_smbus { 75 int sda; 76 struct piixpm_softc *softc; 77 }; 78 79 struct piixpm_softc { 80 device_t sc_dev; 81 82 bus_space_tag_t sc_iot; 83 #define sc_pm_iot sc_iot 84 #define sc_smb_iot sc_iot 85 bus_space_handle_t sc_pm_ioh; 86 bus_space_handle_t sc_sb800_ioh; 87 bus_space_handle_t sc_smb_ioh; 88 void * sc_smb_ih; 89 int sc_poll; 90 bool sc_sb800_selen; /* Use SMBUS0SEL */ 91 92 pci_chipset_tag_t sc_pc; 93 pcitag_t sc_pcitag; 94 pcireg_t sc_id; 95 pcireg_t sc_rev; 96 97 int sc_numbusses; 98 device_t sc_i2c_device[4]; 99 struct piixpm_smbus sc_busses[4]; 100 struct i2c_controller sc_i2c_tags[4]; 101 102 kmutex_t sc_exec_lock; 103 kcondvar_t sc_exec_wait; 104 105 struct { 106 i2c_op_t op; 107 void * buf; 108 size_t len; 109 int flags; 110 int error; 111 bool done; 112 } sc_i2c_xfer; 113 114 pcireg_t sc_devact[2]; 115 }; 116 117 static int piixpm_match(device_t, cfdata_t, void *); 118 static void piixpm_attach(device_t, device_t, void *); 119 static int piixpm_rescan(device_t, const char *, const int *); 120 static void piixpm_chdet(device_t, device_t); 121 122 static bool piixpm_suspend(device_t, const pmf_qual_t *); 123 static bool piixpm_resume(device_t, const pmf_qual_t *); 124 125 static int piixpm_sb800_init(struct piixpm_softc *); 126 static void piixpm_csb5_reset(void *); 127 static int piixpm_i2c_acquire_bus(void *, int); 128 static void piixpm_i2c_release_bus(void *, int); 129 static int piixpm_i2c_exec(void *, i2c_op_t, i2c_addr_t, const void *, 130 size_t, void *, size_t, int); 131 132 static int piixpm_intr(void *); 133 134 CFATTACH_DECL3_NEW(piixpm, sizeof(struct piixpm_softc), 135 piixpm_match, piixpm_attach, NULL, NULL, piixpm_rescan, piixpm_chdet, 0); 136 137 static int 138 piixpm_match(device_t parent, cfdata_t match, void *aux) 139 { 140 struct pci_attach_args *pa; 141 142 pa = (struct pci_attach_args *)aux; 143 switch (PCI_VENDOR(pa->pa_id)) { 144 case PCI_VENDOR_INTEL: 145 switch (PCI_PRODUCT(pa->pa_id)) { 146 case PCI_PRODUCT_INTEL_82371AB_PMC: 147 case PCI_PRODUCT_INTEL_82440MX_PMC: 148 return 1; 149 } 150 break; 151 case PCI_VENDOR_ATI: 152 switch (PCI_PRODUCT(pa->pa_id)) { 153 case PCI_PRODUCT_ATI_SB200_SMB: 154 case PCI_PRODUCT_ATI_SB300_SMB: 155 case PCI_PRODUCT_ATI_SB400_SMB: 156 case PCI_PRODUCT_ATI_SB600_SMB: /* matches SB600/SB700/SB800 */ 157 return 1; 158 } 159 break; 160 case PCI_VENDOR_SERVERWORKS: 161 switch (PCI_PRODUCT(pa->pa_id)) { 162 case PCI_PRODUCT_SERVERWORKS_OSB4: 163 case PCI_PRODUCT_SERVERWORKS_CSB5: 164 case PCI_PRODUCT_SERVERWORKS_CSB6: 165 case PCI_PRODUCT_SERVERWORKS_HT1000SB: 166 case PCI_PRODUCT_SERVERWORKS_HT1100SB: 167 return 1; 168 } 169 break; 170 case PCI_VENDOR_AMD: 171 switch (PCI_PRODUCT(pa->pa_id)) { 172 case PCI_PRODUCT_AMD_HUDSON_SMB: 173 case PCI_PRODUCT_AMD_KERNCZ_SMB: 174 return 1; 175 } 176 break; 177 } 178 179 return 0; 180 } 181 182 static void 183 piixpm_attach(device_t parent, device_t self, void *aux) 184 { 185 struct piixpm_softc *sc = device_private(self); 186 struct pci_attach_args *pa = aux; 187 pcireg_t base, conf; 188 pcireg_t pmmisc; 189 pci_intr_handle_t ih; 190 bool usesmi = false; 191 const char *intrstr = NULL; 192 int i, flags; 193 char intrbuf[PCI_INTRSTR_LEN]; 194 195 sc->sc_dev = self; 196 sc->sc_iot = pa->pa_iot; 197 sc->sc_id = pa->pa_id; 198 sc->sc_rev = PCI_REVISION(pa->pa_class); 199 sc->sc_pc = pa->pa_pc; 200 sc->sc_pcitag = pa->pa_tag; 201 sc->sc_numbusses = 1; 202 203 pci_aprint_devinfo(pa, NULL); 204 205 mutex_init(&sc->sc_exec_lock, MUTEX_DEFAULT, IPL_BIO); 206 cv_init(&sc->sc_exec_wait, device_xname(self)); 207 208 if (!pmf_device_register(self, piixpm_suspend, piixpm_resume)) 209 aprint_error_dev(self, "couldn't establish power handler\n"); 210 211 if ((PCI_VENDOR(pa->pa_id) != PCI_VENDOR_INTEL) || 212 (PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_INTEL_82371AB_PMC)) 213 goto nopowermanagement; 214 215 /* check whether I/O access to PM regs is enabled */ 216 pmmisc = pci_conf_read(pa->pa_pc, pa->pa_tag, PIIX_PMREGMISC); 217 if (!(pmmisc & 1)) 218 goto nopowermanagement; 219 220 /* Map I/O space */ 221 base = pci_conf_read(pa->pa_pc, pa->pa_tag, PIIX_PM_BASE); 222 if (base == 0 || bus_space_map(sc->sc_pm_iot, PCI_MAPREG_IO_ADDR(base), 223 PIIX_PM_SIZE, 0, &sc->sc_pm_ioh)) { 224 aprint_error_dev(self, 225 "can't map power management I/O space\n"); 226 goto nopowermanagement; 227 } 228 229 /* 230 * Revision 0 and 1 are PIIX4, 2 is PIIX4E, 3 is PIIX4M. 231 * PIIX4 and PIIX4E have a bug in the timer latch, see Errata #20 232 * in the "Specification update" (document #297738). 233 */ 234 acpipmtimer_attach(self, sc->sc_pm_iot, sc->sc_pm_ioh, PIIX_PM_PMTMR, 235 (PCI_REVISION(pa->pa_class) < 3) ? ACPIPMT_BADLATCH : 0); 236 237 nopowermanagement: 238 239 /* SB800 rev 0x40+, AMD HUDSON and newer need special initialization */ 240 if (PIIXPM_IS_FCHGRP(sc) || PIIXPM_IS_SB800GRP(sc)) { 241 if (piixpm_sb800_init(sc) == 0) { 242 /* Read configuration */ 243 conf = bus_space_read_1(sc->sc_iot, 244 sc->sc_smb_ioh, SB800_SMB_HOSTC); 245 usesmi = ((conf & SB800_SMB_HOSTC_IRQ) == 0); 246 goto setintr; 247 } 248 aprint_normal_dev(self, "SMBus initialization failed\n"); 249 return; 250 } 251 252 /* Read configuration */ 253 conf = pci_conf_read(pa->pa_pc, pa->pa_tag, PIIX_SMB_HOSTC); 254 DPRINTF(("%s: conf 0x%08x\n", device_xname(self), conf)); 255 256 if ((conf & PIIX_SMB_HOSTC_HSTEN) == 0) { 257 aprint_normal_dev(self, "SMBus disabled\n"); 258 return; 259 } 260 usesmi = (conf & PIIX_SMB_HOSTC_INTMASK) == PIIX_SMB_HOSTC_SMI; 261 262 /* Map I/O space */ 263 base = pci_conf_read(pa->pa_pc, pa->pa_tag, PIIX_SMB_BASE) & 0xffff; 264 if (base == 0 || 265 bus_space_map(sc->sc_smb_iot, PCI_MAPREG_IO_ADDR(base), 266 PIIX_SMB_SIZE, 0, &sc->sc_smb_ioh)) { 267 aprint_error_dev(self, "can't map smbus I/O space\n"); 268 return; 269 } 270 271 setintr: 272 sc->sc_poll = 1; 273 aprint_normal_dev(self, ""); 274 if (usesmi) { 275 /* No PCI IRQ */ 276 aprint_normal("interrupting at SMI, "); 277 } else { 278 if ((conf & PIIX_SMB_HOSTC_INTMASK) == PIIX_SMB_HOSTC_IRQ) { 279 /* Install interrupt handler */ 280 if (pci_intr_map(pa, &ih) == 0) { 281 intrstr = pci_intr_string(pa->pa_pc, ih, 282 intrbuf, sizeof(intrbuf)); 283 pci_intr_setattr(pa->pa_pc, &ih, 284 PCI_INTR_MPSAFE, true); 285 sc->sc_smb_ih = pci_intr_establish_xname( 286 pa->pa_pc, ih, IPL_BIO, piixpm_intr, 287 sc, device_xname(sc->sc_dev)); 288 if (sc->sc_smb_ih != NULL) { 289 aprint_normal("interrupting at %s", 290 intrstr); 291 sc->sc_poll = 0; 292 } 293 } 294 } 295 if (sc->sc_poll) 296 aprint_normal("polling"); 297 } 298 299 aprint_normal("\n"); 300 301 for (i = 0; i < sc->sc_numbusses; i++) 302 sc->sc_i2c_device[i] = NULL; 303 304 flags = 0; 305 piixpm_rescan(self, "i2cbus", &flags); 306 } 307 308 static int 309 piixpm_iicbus_print(void *aux, const char *pnp) 310 { 311 struct i2cbus_attach_args *iba = aux; 312 struct i2c_controller *tag = iba->iba_tag; 313 struct piixpm_smbus *bus = tag->ic_cookie; 314 struct piixpm_softc *sc = bus->softc; 315 316 iicbus_print(aux, pnp); 317 if (sc->sc_numbusses != 0) 318 aprint_normal(" port %d", bus->sda); 319 320 return UNCONF; 321 } 322 static int 323 piixpm_rescan(device_t self, const char *ifattr, const int *flags) 324 { 325 struct piixpm_softc *sc = device_private(self); 326 struct i2cbus_attach_args iba; 327 int i; 328 329 if (!ifattr_match(ifattr, "i2cbus")) 330 return 0; 331 332 /* Attach I2C bus */ 333 334 for (i = 0; i < sc->sc_numbusses; i++) { 335 if (sc->sc_i2c_device[i]) 336 continue; 337 sc->sc_busses[i].sda = i; 338 sc->sc_busses[i].softc = sc; 339 iic_tag_init(&sc->sc_i2c_tags[i]); 340 sc->sc_i2c_tags[i].ic_cookie = &sc->sc_busses[i]; 341 sc->sc_i2c_tags[i].ic_acquire_bus = piixpm_i2c_acquire_bus; 342 sc->sc_i2c_tags[i].ic_release_bus = piixpm_i2c_release_bus; 343 sc->sc_i2c_tags[i].ic_exec = piixpm_i2c_exec; 344 memset(&iba, 0, sizeof(iba)); 345 iba.iba_tag = &sc->sc_i2c_tags[i]; 346 sc->sc_i2c_device[i] = config_found_ia(self, ifattr, &iba, 347 piixpm_iicbus_print); 348 } 349 350 return 0; 351 } 352 353 static void 354 piixpm_chdet(device_t self, device_t child) 355 { 356 struct piixpm_softc *sc = device_private(self); 357 int i; 358 359 for (i = 0; i < sc->sc_numbusses; i++) { 360 if (sc->sc_i2c_device[i] == child) { 361 sc->sc_i2c_device[i] = NULL; 362 break; 363 } 364 } 365 } 366 367 368 static bool 369 piixpm_suspend(device_t dv, const pmf_qual_t *qual) 370 { 371 struct piixpm_softc *sc = device_private(dv); 372 373 sc->sc_devact[0] = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 374 PIIX_DEVACTA); 375 sc->sc_devact[1] = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 376 PIIX_DEVACTB); 377 378 return true; 379 } 380 381 static bool 382 piixpm_resume(device_t dv, const pmf_qual_t *qual) 383 { 384 struct piixpm_softc *sc = device_private(dv); 385 386 pci_conf_write(sc->sc_pc, sc->sc_pcitag, PIIX_DEVACTA, 387 sc->sc_devact[0]); 388 pci_conf_write(sc->sc_pc, sc->sc_pcitag, PIIX_DEVACTB, 389 sc->sc_devact[1]); 390 391 return true; 392 } 393 394 /* 395 * Extract SMBus base address from SB800 Power Management (PM) registers. 396 * The PM registers can be accessed either through indirect I/O (CD6/CD7) or 397 * direct mapping if AcpiMMioDecodeEn is enabled. Since this function is only 398 * called once it uses indirect I/O for simplicity. 399 */ 400 static int 401 piixpm_sb800_init(struct piixpm_softc *sc) 402 { 403 bus_space_tag_t iot = sc->sc_iot; 404 bus_space_handle_t ioh; /* indirect I/O handle */ 405 uint16_t val, base_addr; 406 bool enabled; 407 408 if (PIIXPM_IS_KERNCZ(sc) || 409 (PIIXPM_IS_HUDSON(sc) && (sc->sc_rev >= 0x1f))) 410 sc->sc_numbusses = 2; 411 else 412 sc->sc_numbusses = 4; 413 414 /* Fetch SMB base address */ 415 if (bus_space_map(iot, 416 SB800_INDIRECTIO_BASE, SB800_INDIRECTIO_SIZE, 0, &ioh)) { 417 device_printf(sc->sc_dev, "couldn't map indirect I/O space\n"); 418 return EBUSY; 419 } 420 if (PIIXPM_IS_FCHGRP(sc)) { 421 bus_space_write_1(iot, ioh, SB800_INDIRECTIO_INDEX, 422 AMDFCH41_PM_DECODE_EN0); 423 val = bus_space_read_1(iot, ioh, SB800_INDIRECTIO_DATA); 424 enabled = val & AMDFCH41_SMBUS_EN; 425 if (!enabled) 426 return ENOENT; 427 428 bus_space_write_1(iot, ioh, SB800_INDIRECTIO_INDEX, 429 AMDFCH41_PM_DECODE_EN1); 430 val = bus_space_read_1(iot, ioh, SB800_INDIRECTIO_DATA) << 8; 431 base_addr = val; 432 } else { 433 uint8_t data; 434 435 bus_space_write_1(iot, ioh, SB800_INDIRECTIO_INDEX, 436 SB800_PM_SMBUS0EN_LO); 437 val = bus_space_read_1(iot, ioh, SB800_INDIRECTIO_DATA); 438 enabled = val & SB800_PM_SMBUS0EN_ENABLE; 439 if (!enabled) 440 return ENOENT; 441 442 bus_space_write_1(iot, ioh, SB800_INDIRECTIO_INDEX, 443 SB800_PM_SMBUS0EN_HI); 444 val |= bus_space_read_1(iot, ioh, SB800_INDIRECTIO_DATA) << 8; 445 base_addr = val & SB800_PM_SMBUS0EN_BADDR; 446 447 bus_space_write_1(iot, ioh, SB800_INDIRECTIO_INDEX, 448 SB800_PM_SMBUS0SELEN); 449 data = bus_space_read_1(iot, ioh, SB800_INDIRECTIO_DATA); 450 if ((data & SB800_PM_USE_SMBUS0SEL) != 0) 451 sc->sc_sb800_selen = true; 452 } 453 454 sc->sc_sb800_ioh = ioh; 455 aprint_debug_dev(sc->sc_dev, "SMBus @ 0x%04x\n", base_addr); 456 457 if (bus_space_map(iot, PCI_MAPREG_IO_ADDR(base_addr), 458 SB800_SMB_SIZE, 0, &sc->sc_smb_ioh)) { 459 aprint_error_dev(sc->sc_dev, "can't map smbus I/O space\n"); 460 return EBUSY; 461 } 462 463 return 0; 464 } 465 466 static void 467 piixpm_csb5_reset(void *arg) 468 { 469 struct piixpm_softc *sc = arg; 470 pcireg_t base, hostc, pmbase; 471 472 base = pci_conf_read(sc->sc_pc, sc->sc_pcitag, PIIX_SMB_BASE); 473 hostc = pci_conf_read(sc->sc_pc, sc->sc_pcitag, PIIX_SMB_HOSTC); 474 475 pmbase = pci_conf_read(sc->sc_pc, sc->sc_pcitag, PIIX_PM_BASE); 476 pmbase |= PIIX_PM_BASE_CSB5_RESET; 477 pci_conf_write(sc->sc_pc, sc->sc_pcitag, PIIX_PM_BASE, pmbase); 478 pmbase &= ~PIIX_PM_BASE_CSB5_RESET; 479 pci_conf_write(sc->sc_pc, sc->sc_pcitag, PIIX_PM_BASE, pmbase); 480 481 pci_conf_write(sc->sc_pc, sc->sc_pcitag, PIIX_SMB_BASE, base); 482 pci_conf_write(sc->sc_pc, sc->sc_pcitag, PIIX_SMB_HOSTC, hostc); 483 484 (void) tsleep(&sc, PRIBIO, "csb5reset", hz/2); 485 } 486 487 static int 488 piixpm_i2c_acquire_bus(void *cookie, int flags) 489 { 490 struct piixpm_smbus *smbus = cookie; 491 struct piixpm_softc *sc = smbus->softc; 492 493 if (PIIXPM_IS_KERNCZ(sc)) { 494 bus_space_write_1(sc->sc_iot, sc->sc_sb800_ioh, 495 SB800_INDIRECTIO_INDEX, AMDFCH41_PM_PORT_INDEX); 496 bus_space_write_1(sc->sc_iot, sc->sc_sb800_ioh, 497 SB800_INDIRECTIO_DATA, smbus->sda << 3); 498 } else if (PIIXPM_IS_SB800GRP(sc) || PIIXPM_IS_HUDSON(sc)) { 499 if (sc->sc_sb800_selen) { 500 bus_space_write_1(sc->sc_iot, sc->sc_sb800_ioh, 501 SB800_INDIRECTIO_INDEX, SB800_PM_SMBUS0SEL); 502 bus_space_write_1(sc->sc_iot, sc->sc_sb800_ioh, 503 SB800_INDIRECTIO_DATA, 504 __SHIFTIN(smbus->sda, SB800_PM_SMBUS0_MASK_E)); 505 } else { 506 uint8_t data; 507 508 bus_space_write_1(sc->sc_iot, sc->sc_sb800_ioh, 509 SB800_INDIRECTIO_INDEX, SB800_PM_SMBUS0EN_LO); 510 data = bus_space_read_1(sc->sc_iot, sc->sc_sb800_ioh, 511 SB800_INDIRECTIO_DATA) & ~SB800_PM_SMBUS0_MASK_C; 512 data |= __SHIFTIN(smbus->sda, SB800_PM_SMBUS0_MASK_C); 513 bus_space_write_1(sc->sc_iot, sc->sc_sb800_ioh, 514 SB800_INDIRECTIO_DATA, data); 515 } 516 } 517 518 return 0; 519 } 520 521 static void 522 piixpm_i2c_release_bus(void *cookie, int flags) 523 { 524 struct piixpm_smbus *smbus = cookie; 525 struct piixpm_softc *sc = smbus->softc; 526 527 if (PIIXPM_IS_KERNCZ(sc)) { 528 bus_space_write_1(sc->sc_iot, sc->sc_sb800_ioh, 529 SB800_INDIRECTIO_INDEX, AMDFCH41_PM_PORT_INDEX); 530 /* Set to port 0 */ 531 bus_space_write_1(sc->sc_iot, sc->sc_sb800_ioh, 532 SB800_INDIRECTIO_DATA, 0); 533 } else if (PIIXPM_IS_SB800GRP(sc) || PIIXPM_IS_HUDSON(sc)) { 534 if (sc->sc_sb800_selen) { 535 bus_space_write_1(sc->sc_iot, sc->sc_sb800_ioh, 536 SB800_INDIRECTIO_INDEX, SB800_PM_SMBUS0SEL); 537 538 /* Set to port 0 */ 539 bus_space_write_1(sc->sc_iot, sc->sc_sb800_ioh, 540 SB800_INDIRECTIO_DATA, 0); 541 } else { 542 uint8_t data; 543 544 bus_space_write_1(sc->sc_iot, sc->sc_sb800_ioh, 545 SB800_INDIRECTIO_INDEX, SB800_PM_SMBUS0EN_LO); 546 547 /* Set to port 0 */ 548 data = bus_space_read_1(sc->sc_iot, sc->sc_sb800_ioh, 549 SB800_INDIRECTIO_DATA) & ~SB800_PM_SMBUS0_MASK_C; 550 bus_space_write_1(sc->sc_iot, sc->sc_sb800_ioh, 551 SB800_INDIRECTIO_DATA, data); 552 } 553 } 554 } 555 556 static int 557 piixpm_i2c_exec(void *cookie, i2c_op_t op, i2c_addr_t addr, 558 const void *cmdbuf, size_t cmdlen, void *buf, size_t len, int flags) 559 { 560 struct piixpm_smbus *smbus = cookie; 561 struct piixpm_softc *sc = smbus->softc; 562 const uint8_t *b; 563 uint8_t ctl = 0, st; 564 int retries; 565 566 DPRINTF(("%s: exec: op %d, addr 0x%02x, cmdlen %zu, len %zu, " 567 "flags 0x%x\n", 568 device_xname(sc->sc_dev), op, addr, cmdlen, len, flags)); 569 570 mutex_enter(&sc->sc_exec_lock); 571 572 /* Clear status bits */ 573 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_HS, 574 PIIX_SMB_HS_INTR | PIIX_SMB_HS_DEVERR | 575 PIIX_SMB_HS_BUSERR | PIIX_SMB_HS_FAILED); 576 bus_space_barrier(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_HS, 1, 577 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 578 579 /* Wait for bus to be idle */ 580 for (retries = 100; retries > 0; retries--) { 581 st = bus_space_read_1(sc->sc_smb_iot, sc->sc_smb_ioh, 582 PIIX_SMB_HS); 583 if (!(st & PIIX_SMB_HS_BUSY)) 584 break; 585 DELAY(PIIXPM_DELAY); 586 } 587 DPRINTF(("%s: exec: st %#x\n", device_xname(sc->sc_dev), st & 0xff)); 588 if (st & PIIX_SMB_HS_BUSY) { 589 mutex_exit(&sc->sc_exec_lock); 590 return (EBUSY); 591 } 592 593 if (sc->sc_poll) 594 flags |= I2C_F_POLL; 595 596 if (!I2C_OP_STOP_P(op) || cmdlen > 1 || len > 2 || 597 (cmdlen == 0 && len > 1)) { 598 mutex_exit(&sc->sc_exec_lock); 599 return (EINVAL); 600 } 601 602 /* Setup transfer */ 603 sc->sc_i2c_xfer.op = op; 604 sc->sc_i2c_xfer.buf = buf; 605 sc->sc_i2c_xfer.len = len; 606 sc->sc_i2c_xfer.flags = flags; 607 sc->sc_i2c_xfer.error = 0; 608 sc->sc_i2c_xfer.done = false; 609 610 /* Set slave address and transfer direction */ 611 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_TXSLVA, 612 PIIX_SMB_TXSLVA_ADDR(addr) | 613 (I2C_OP_READ_P(op) ? PIIX_SMB_TXSLVA_READ : 0)); 614 615 b = cmdbuf; 616 if (cmdlen > 0) 617 /* Set command byte */ 618 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, 619 PIIX_SMB_HCMD, b[0]); 620 621 if (I2C_OP_WRITE_P(op)) { 622 /* Write data */ 623 b = buf; 624 if (cmdlen == 0 && len == 1) 625 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, 626 PIIX_SMB_HCMD, b[0]); 627 else if (len > 0) 628 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, 629 PIIX_SMB_HD0, b[0]); 630 if (len > 1) 631 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, 632 PIIX_SMB_HD1, b[1]); 633 } 634 635 /* Set SMBus command */ 636 if (cmdlen == 0) { 637 if (len == 0) 638 ctl = PIIX_SMB_HC_CMD_QUICK; 639 else 640 ctl = PIIX_SMB_HC_CMD_BYTE; 641 } else if (len == 1) 642 ctl = PIIX_SMB_HC_CMD_BDATA; 643 else if (len == 2) 644 ctl = PIIX_SMB_HC_CMD_WDATA; 645 else 646 panic("%s: unexpected len %zu", __func__, len); 647 648 if ((flags & I2C_F_POLL) == 0) 649 ctl |= PIIX_SMB_HC_INTREN; 650 651 /* Start transaction */ 652 ctl |= PIIX_SMB_HC_START; 653 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_HC, ctl); 654 655 if (flags & I2C_F_POLL) { 656 /* Poll for completion */ 657 if (PIIXPM_IS_CSB5(sc)) 658 DELAY(2*PIIXPM_DELAY); 659 else 660 DELAY(PIIXPM_DELAY); 661 for (retries = 1000; retries > 0; retries--) { 662 st = bus_space_read_1(sc->sc_smb_iot, sc->sc_smb_ioh, 663 PIIX_SMB_HS); 664 if ((st & PIIX_SMB_HS_BUSY) == 0) 665 break; 666 DELAY(PIIXPM_DELAY); 667 } 668 if (st & PIIX_SMB_HS_BUSY) 669 goto timeout; 670 piixpm_intr(sc); 671 } else { 672 /* Wait for interrupt */ 673 while (! sc->sc_i2c_xfer.done) { 674 if (cv_timedwait(&sc->sc_exec_wait, &sc->sc_exec_lock, 675 PIIXPM_TIMEOUT * hz)) 676 goto timeout; 677 } 678 } 679 680 int error = sc->sc_i2c_xfer.error; 681 mutex_exit(&sc->sc_exec_lock); 682 683 return (error); 684 685 timeout: 686 /* 687 * Transfer timeout. Kill the transaction and clear status bits. 688 */ 689 aprint_error_dev(sc->sc_dev, "timeout, status 0x%x\n", st); 690 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_HC, 691 PIIX_SMB_HC_KILL); 692 DELAY(PIIXPM_DELAY); 693 st = bus_space_read_1(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_HS); 694 if ((st & PIIX_SMB_HS_FAILED) == 0) 695 aprint_error_dev(sc->sc_dev, 696 "transaction abort failed, status 0x%x\n", st); 697 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_HS, st); 698 /* 699 * CSB5 needs hard reset to unlock the smbus after timeout. 700 */ 701 if (PIIXPM_IS_CSB5(sc)) 702 piixpm_csb5_reset(sc); 703 mutex_exit(&sc->sc_exec_lock); 704 return (ETIMEDOUT); 705 } 706 707 static int 708 piixpm_intr(void *arg) 709 { 710 struct piixpm_softc *sc = arg; 711 uint8_t st; 712 uint8_t *b; 713 size_t len; 714 715 /* Read status */ 716 st = bus_space_read_1(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_HS); 717 if ((st & PIIX_SMB_HS_BUSY) != 0 || (st & (PIIX_SMB_HS_INTR | 718 PIIX_SMB_HS_DEVERR | PIIX_SMB_HS_BUSERR | 719 PIIX_SMB_HS_FAILED)) == 0) 720 /* Interrupt was not for us */ 721 return (0); 722 723 DPRINTF(("%s: intr st %#x\n", device_xname(sc->sc_dev), st & 0xff)); 724 725 if ((sc->sc_i2c_xfer.flags & I2C_F_POLL) == 0) 726 mutex_enter(&sc->sc_exec_lock); 727 728 /* Clear status bits */ 729 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_HS, st); 730 731 /* Check for errors */ 732 if (st & (PIIX_SMB_HS_DEVERR | PIIX_SMB_HS_BUSERR | 733 PIIX_SMB_HS_FAILED)) { 734 sc->sc_i2c_xfer.error = EIO; 735 goto done; 736 } 737 738 if (st & PIIX_SMB_HS_INTR) { 739 if (I2C_OP_WRITE_P(sc->sc_i2c_xfer.op)) 740 goto done; 741 742 /* Read data */ 743 b = sc->sc_i2c_xfer.buf; 744 len = sc->sc_i2c_xfer.len; 745 if (len > 0) 746 b[0] = bus_space_read_1(sc->sc_smb_iot, sc->sc_smb_ioh, 747 PIIX_SMB_HD0); 748 if (len > 1) 749 b[1] = bus_space_read_1(sc->sc_smb_iot, sc->sc_smb_ioh, 750 PIIX_SMB_HD1); 751 } 752 753 done: 754 sc->sc_i2c_xfer.done = true; 755 if ((sc->sc_i2c_xfer.flags & I2C_F_POLL) == 0) { 756 cv_signal(&sc->sc_exec_wait); 757 mutex_exit(&sc->sc_exec_lock); 758 } 759 return (1); 760 } 761
Indexes created Mon Sep 29 15:09:53 GMT 2025