piixpm.c revision 1.61
1 /* $NetBSD: piixpm.c,v 1.61 2020/01/09 12:49:12 msaitoh Exp $ */ 2 /* $OpenBSD: piixpm.c,v 1.39 2013/10/01 20:06:02 sf Exp $ */ 3 4 /* 5 * Copyright (c) 2005, 2006 Alexander Yurchenko <grange (at) openbsd.org> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 /* 21 * Intel PIIX and compatible Power Management controller driver. 22 */ 23 24 #include <sys/cdefs.h> 25 __KERNEL_RCSID(0, "$NetBSD: piixpm.c,v 1.61 2020/01/09 12:49:12 msaitoh Exp $"); 26 27 #include <sys/param.h> 28 #include <sys/systm.h> 29 #include <sys/device.h> 30 #include <sys/kernel.h> 31 #include <sys/mutex.h> 32 #include <sys/condvar.h> 33 #include <sys/proc.h> 34 35 #include <sys/bus.h> 36 37 #include <dev/pci/pcidevs.h> 38 #include <dev/pci/pcireg.h> 39 #include <dev/pci/pcivar.h> 40 41 #include <dev/pci/piixpmreg.h> 42 43 #include <dev/i2c/i2cvar.h> 44 45 #include <dev/ic/acpipmtimer.h> 46 47 #ifdef PIIXPM_DEBUG 48 #define DPRINTF(x) printf x 49 #else 50 #define DPRINTF(x) 51 #endif 52 53 #define PIIXPM_IS_CSB5(sc) \ 54 (PCI_VENDOR((sc)->sc_id) == PCI_VENDOR_SERVERWORKS && \ 55 PCI_PRODUCT((sc)->sc_id) == PCI_PRODUCT_SERVERWORKS_CSB5) 56 #define PIIXPM_DELAY 200 57 #define PIIXPM_TIMEOUT 1 58 59 #define PIIXPM_IS_SB800GRP(sc) \ 60 ((PCI_VENDOR((sc)->sc_id) == PCI_VENDOR_ATI) && \ 61 ((PCI_PRODUCT((sc)->sc_id) == PCI_PRODUCT_ATI_SB600_SMB) && \ 62 ((sc)->sc_rev >= 0x40))) 63 64 #define PIIXPM_IS_HUDSON(sc) \ 65 ((PCI_VENDOR((sc)->sc_id) == PCI_VENDOR_AMD) && \ 66 (PCI_PRODUCT((sc)->sc_id) == PCI_PRODUCT_AMD_HUDSON_SMB)) 67 68 #define PIIXPM_IS_KERNCZ(sc) \ 69 ((PCI_VENDOR((sc)->sc_id) == PCI_VENDOR_AMD) && \ 70 (PCI_PRODUCT((sc)->sc_id) == PCI_PRODUCT_AMD_KERNCZ_SMB)) 71 72 #define PIIXPM_IS_FCHGRP(sc) (PIIXPM_IS_HUDSON(sc) || PIIXPM_IS_KERNCZ(sc)) 73 74 #define PIIX_SB800_TIMEOUT 500 75 76 struct piixpm_smbus { 77 int sda; 78 struct piixpm_softc *softc; 79 }; 80 81 struct piixpm_softc { 82 device_t sc_dev; 83 84 bus_space_tag_t sc_iot; 85 #define sc_pm_iot sc_iot 86 #define sc_smb_iot sc_iot 87 bus_space_handle_t sc_pm_ioh; 88 bus_space_handle_t sc_sb800_ioh; 89 bus_space_handle_t sc_smb_ioh; 90 void * sc_smb_ih; 91 int sc_poll; 92 bool sc_sb800_selen; /* Use SMBUS0SEL */ 93 94 pci_chipset_tag_t sc_pc; 95 pcitag_t sc_pcitag; 96 pcireg_t sc_id; 97 pcireg_t sc_rev; 98 99 int sc_numbusses; 100 device_t sc_i2c_device[4]; 101 struct piixpm_smbus sc_busses[4]; 102 struct i2c_controller sc_i2c_tags[4]; 103 104 kmutex_t sc_exec_lock; 105 kcondvar_t sc_exec_wait; 106 107 struct { 108 i2c_op_t op; 109 void * buf; 110 size_t len; 111 int flags; 112 int error; 113 bool done; 114 } sc_i2c_xfer; 115 116 pcireg_t sc_devact[2]; 117 }; 118 119 static int piixpm_match(device_t, cfdata_t, void *); 120 static void piixpm_attach(device_t, device_t, void *); 121 static int piixpm_rescan(device_t, const char *, const int *); 122 static void piixpm_chdet(device_t, device_t); 123 124 static bool piixpm_suspend(device_t, const pmf_qual_t *); 125 static bool piixpm_resume(device_t, const pmf_qual_t *); 126 127 static int piixpm_sb800_init(struct piixpm_softc *); 128 static void piixpm_csb5_reset(void *); 129 static int piixpm_i2c_sb800_acquire_bus(void *, int); 130 static void piixpm_i2c_sb800_release_bus(void *, int); 131 static int piixpm_i2c_exec(void *, i2c_op_t, i2c_addr_t, const void *, 132 size_t, void *, size_t, int); 133 134 static int piixpm_intr(void *); 135 136 CFATTACH_DECL3_NEW(piixpm, sizeof(struct piixpm_softc), 137 piixpm_match, piixpm_attach, NULL, NULL, piixpm_rescan, piixpm_chdet, 0); 138 139 static int 140 piixpm_match(device_t parent, cfdata_t match, void *aux) 141 { 142 struct pci_attach_args *pa; 143 144 pa = (struct pci_attach_args *)aux; 145 switch (PCI_VENDOR(pa->pa_id)) { 146 case PCI_VENDOR_INTEL: 147 switch (PCI_PRODUCT(pa->pa_id)) { 148 case PCI_PRODUCT_INTEL_82371AB_PMC: 149 case PCI_PRODUCT_INTEL_82440MX_PMC: 150 return 1; 151 } 152 break; 153 case PCI_VENDOR_ATI: 154 switch (PCI_PRODUCT(pa->pa_id)) { 155 case PCI_PRODUCT_ATI_SB200_SMB: 156 case PCI_PRODUCT_ATI_SB300_SMB: 157 case PCI_PRODUCT_ATI_SB400_SMB: 158 case PCI_PRODUCT_ATI_SB600_SMB: /* matches SB600/SB700/SB800 */ 159 return 1; 160 } 161 break; 162 case PCI_VENDOR_SERVERWORKS: 163 switch (PCI_PRODUCT(pa->pa_id)) { 164 case PCI_PRODUCT_SERVERWORKS_OSB4: 165 case PCI_PRODUCT_SERVERWORKS_CSB5: 166 case PCI_PRODUCT_SERVERWORKS_CSB6: 167 case PCI_PRODUCT_SERVERWORKS_HT1000SB: 168 case PCI_PRODUCT_SERVERWORKS_HT1100SB: 169 return 1; 170 } 171 break; 172 case PCI_VENDOR_AMD: 173 switch (PCI_PRODUCT(pa->pa_id)) { 174 case PCI_PRODUCT_AMD_HUDSON_SMB: 175 case PCI_PRODUCT_AMD_KERNCZ_SMB: 176 return 1; 177 } 178 break; 179 } 180 181 return 0; 182 } 183 184 static void 185 piixpm_attach(device_t parent, device_t self, void *aux) 186 { 187 struct piixpm_softc *sc = device_private(self); 188 struct pci_attach_args *pa = aux; 189 pcireg_t base, conf; 190 pcireg_t pmmisc; 191 pci_intr_handle_t ih; 192 bool usesmi = false; 193 const char *intrstr = NULL; 194 int i, flags; 195 char intrbuf[PCI_INTRSTR_LEN]; 196 197 sc->sc_dev = self; 198 sc->sc_iot = pa->pa_iot; 199 sc->sc_id = pa->pa_id; 200 sc->sc_rev = PCI_REVISION(pa->pa_class); 201 sc->sc_pc = pa->pa_pc; 202 sc->sc_pcitag = pa->pa_tag; 203 sc->sc_numbusses = 1; 204 205 pci_aprint_devinfo(pa, NULL); 206 207 mutex_init(&sc->sc_exec_lock, MUTEX_DEFAULT, IPL_BIO); 208 cv_init(&sc->sc_exec_wait, device_xname(self)); 209 210 if (!pmf_device_register(self, piixpm_suspend, piixpm_resume)) 211 aprint_error_dev(self, "couldn't establish power handler\n"); 212 213 if ((PCI_VENDOR(pa->pa_id) != PCI_VENDOR_INTEL) || 214 (PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_INTEL_82371AB_PMC)) 215 goto nopowermanagement; 216 217 /* check whether I/O access to PM regs is enabled */ 218 pmmisc = pci_conf_read(pa->pa_pc, pa->pa_tag, PIIX_PMREGMISC); 219 if (!(pmmisc & 1)) 220 goto nopowermanagement; 221 222 /* Map I/O space */ 223 base = pci_conf_read(pa->pa_pc, pa->pa_tag, PIIX_PM_BASE); 224 if (base == 0 || bus_space_map(sc->sc_pm_iot, PCI_MAPREG_IO_ADDR(base), 225 PIIX_PM_SIZE, 0, &sc->sc_pm_ioh)) { 226 aprint_error_dev(self, 227 "can't map power management I/O space\n"); 228 goto nopowermanagement; 229 } 230 231 /* 232 * Revision 0 and 1 are PIIX4, 2 is PIIX4E, 3 is PIIX4M. 233 * PIIX4 and PIIX4E have a bug in the timer latch, see Errata #20 234 * in the "Specification update" (document #297738). 235 */ 236 acpipmtimer_attach(self, sc->sc_pm_iot, sc->sc_pm_ioh, PIIX_PM_PMTMR, 237 (PCI_REVISION(pa->pa_class) < 3) ? ACPIPMT_BADLATCH : 0); 238 239 nopowermanagement: 240 241 /* SB800 rev 0x40+, AMD HUDSON and newer need special initialization */ 242 if (PIIXPM_IS_FCHGRP(sc) || PIIXPM_IS_SB800GRP(sc)) { 243 if (piixpm_sb800_init(sc) == 0) { 244 /* Read configuration */ 245 conf = bus_space_read_1(sc->sc_iot, 246 sc->sc_smb_ioh, SB800_SMB_HOSTC); 247 usesmi = ((conf & SB800_SMB_HOSTC_IRQ) == 0); 248 goto setintr; 249 } 250 aprint_normal_dev(self, "SMBus initialization failed\n"); 251 return; 252 } 253 254 /* Read configuration */ 255 conf = pci_conf_read(pa->pa_pc, pa->pa_tag, PIIX_SMB_HOSTC); 256 DPRINTF(("%s: conf 0x%08x\n", device_xname(self), conf)); 257 258 if ((conf & PIIX_SMB_HOSTC_HSTEN) == 0) { 259 aprint_normal_dev(self, "SMBus disabled\n"); 260 return; 261 } 262 usesmi = (conf & PIIX_SMB_HOSTC_INTMASK) == PIIX_SMB_HOSTC_SMI; 263 264 /* Map I/O space */ 265 base = pci_conf_read(pa->pa_pc, pa->pa_tag, PIIX_SMB_BASE) & 0xffff; 266 if (base == 0 || 267 bus_space_map(sc->sc_smb_iot, PCI_MAPREG_IO_ADDR(base), 268 PIIX_SMB_SIZE, 0, &sc->sc_smb_ioh)) { 269 aprint_error_dev(self, "can't map smbus I/O space\n"); 270 return; 271 } 272 273 setintr: 274 sc->sc_poll = 1; 275 aprint_normal_dev(self, ""); 276 if (usesmi) { 277 /* No PCI IRQ */ 278 aprint_normal("interrupting at SMI, "); 279 } else { 280 if ((conf & PIIX_SMB_HOSTC_INTMASK) == PIIX_SMB_HOSTC_IRQ) { 281 /* Install interrupt handler */ 282 if (pci_intr_map(pa, &ih) == 0) { 283 intrstr = pci_intr_string(pa->pa_pc, ih, 284 intrbuf, sizeof(intrbuf)); 285 pci_intr_setattr(pa->pa_pc, &ih, 286 PCI_INTR_MPSAFE, true); 287 sc->sc_smb_ih = pci_intr_establish_xname( 288 pa->pa_pc, ih, IPL_BIO, piixpm_intr, 289 sc, device_xname(sc->sc_dev)); 290 if (sc->sc_smb_ih != NULL) { 291 aprint_normal("interrupting at %s", 292 intrstr); 293 sc->sc_poll = 0; 294 } 295 } 296 } 297 if (sc->sc_poll) 298 aprint_normal("polling"); 299 } 300 301 aprint_normal("\n"); 302 303 for (i = 0; i < sc->sc_numbusses; i++) 304 sc->sc_i2c_device[i] = NULL; 305 306 flags = 0; 307 piixpm_rescan(self, "i2cbus", &flags); 308 } 309 310 static int 311 piixpm_iicbus_print(void *aux, const char *pnp) 312 { 313 struct i2cbus_attach_args *iba = aux; 314 struct i2c_controller *tag = iba->iba_tag; 315 struct piixpm_smbus *bus = tag->ic_cookie; 316 struct piixpm_softc *sc = bus->softc; 317 318 iicbus_print(aux, pnp); 319 if (sc->sc_numbusses != 0) 320 aprint_normal(" port %d", bus->sda); 321 322 return UNCONF; 323 } 324 static int 325 piixpm_rescan(device_t self, const char *ifattr, const int *flags) 326 { 327 struct piixpm_softc *sc = device_private(self); 328 struct i2cbus_attach_args iba; 329 int i; 330 331 if (!ifattr_match(ifattr, "i2cbus")) 332 return 0; 333 334 /* Attach I2C bus */ 335 336 for (i = 0; i < sc->sc_numbusses; i++) { 337 struct i2c_controller *tag = &sc->sc_i2c_tags[i]; 338 339 if (sc->sc_i2c_device[i]) 340 continue; 341 sc->sc_busses[i].sda = i; 342 sc->sc_busses[i].softc = sc; 343 iic_tag_init(tag); 344 tag->ic_cookie = &sc->sc_busses[i]; 345 if (PIIXPM_IS_SB800GRP(sc) || PIIXPM_IS_FCHGRP(sc)) { 346 tag->ic_acquire_bus = piixpm_i2c_sb800_acquire_bus; 347 tag->ic_release_bus = piixpm_i2c_sb800_release_bus; 348 } else { 349 tag->ic_acquire_bus = NULL; 350 tag->ic_release_bus = NULL; 351 } 352 tag->ic_exec = piixpm_i2c_exec; 353 memset(&iba, 0, sizeof(iba)); 354 iba.iba_tag = tag; 355 sc->sc_i2c_device[i] = config_found_ia(self, ifattr, &iba, 356 piixpm_iicbus_print); 357 } 358 359 return 0; 360 } 361 362 static void 363 piixpm_chdet(device_t self, device_t child) 364 { 365 struct piixpm_softc *sc = device_private(self); 366 int i; 367 368 for (i = 0; i < sc->sc_numbusses; i++) { 369 if (sc->sc_i2c_device[i] == child) { 370 sc->sc_i2c_device[i] = NULL; 371 break; 372 } 373 } 374 } 375 376 377 static bool 378 piixpm_suspend(device_t dv, const pmf_qual_t *qual) 379 { 380 struct piixpm_softc *sc = device_private(dv); 381 382 sc->sc_devact[0] = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 383 PIIX_DEVACTA); 384 sc->sc_devact[1] = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 385 PIIX_DEVACTB); 386 387 return true; 388 } 389 390 static bool 391 piixpm_resume(device_t dv, const pmf_qual_t *qual) 392 { 393 struct piixpm_softc *sc = device_private(dv); 394 395 pci_conf_write(sc->sc_pc, sc->sc_pcitag, PIIX_DEVACTA, 396 sc->sc_devact[0]); 397 pci_conf_write(sc->sc_pc, sc->sc_pcitag, PIIX_DEVACTB, 398 sc->sc_devact[1]); 399 400 return true; 401 } 402 403 /* 404 * Extract SMBus base address from SB800 Power Management (PM) registers. 405 * The PM registers can be accessed either through indirect I/O (CD6/CD7) or 406 * direct mapping if AcpiMMioDecodeEn is enabled. Since this function is only 407 * called once it uses indirect I/O for simplicity. 408 */ 409 static int 410 piixpm_sb800_init(struct piixpm_softc *sc) 411 { 412 bus_space_tag_t iot = sc->sc_iot; 413 bus_space_handle_t ioh; /* indirect I/O handle */ 414 uint16_t val, base_addr; 415 bool enabled; 416 417 if (PIIXPM_IS_KERNCZ(sc) || 418 (PIIXPM_IS_HUDSON(sc) && (sc->sc_rev >= 0x1f))) 419 sc->sc_numbusses = 2; 420 else 421 sc->sc_numbusses = 4; 422 423 /* Fetch SMB base address */ 424 if (bus_space_map(iot, 425 SB800_INDIRECTIO_BASE, SB800_INDIRECTIO_SIZE, 0, &ioh)) { 426 device_printf(sc->sc_dev, "couldn't map indirect I/O space\n"); 427 return EBUSY; 428 } 429 if (PIIXPM_IS_FCHGRP(sc)) { 430 bus_space_write_1(iot, ioh, SB800_INDIRECTIO_INDEX, 431 AMDFCH41_PM_DECODE_EN0); 432 val = bus_space_read_1(iot, ioh, SB800_INDIRECTIO_DATA); 433 enabled = val & AMDFCH41_SMBUS_EN; 434 if (!enabled) 435 return ENOENT; 436 437 bus_space_write_1(iot, ioh, SB800_INDIRECTIO_INDEX, 438 AMDFCH41_PM_DECODE_EN1); 439 val = bus_space_read_1(iot, ioh, SB800_INDIRECTIO_DATA) << 8; 440 base_addr = val; 441 } else { 442 uint8_t data; 443 444 bus_space_write_1(iot, ioh, SB800_INDIRECTIO_INDEX, 445 SB800_PM_SMBUS0EN_LO); 446 val = bus_space_read_1(iot, ioh, SB800_INDIRECTIO_DATA); 447 enabled = val & SB800_PM_SMBUS0EN_ENABLE; 448 if (!enabled) 449 return ENOENT; 450 451 bus_space_write_1(iot, ioh, SB800_INDIRECTIO_INDEX, 452 SB800_PM_SMBUS0EN_HI); 453 val |= bus_space_read_1(iot, ioh, SB800_INDIRECTIO_DATA) << 8; 454 base_addr = val & SB800_PM_SMBUS0EN_BADDR; 455 456 bus_space_write_1(iot, ioh, SB800_INDIRECTIO_INDEX, 457 SB800_PM_SMBUS0SELEN); 458 data = bus_space_read_1(iot, ioh, SB800_INDIRECTIO_DATA); 459 if ((data & SB800_PM_USE_SMBUS0SEL) != 0) 460 sc->sc_sb800_selen = true; 461 } 462 463 sc->sc_sb800_ioh = ioh; 464 aprint_debug_dev(sc->sc_dev, "SMBus @ 0x%04x\n", base_addr); 465 466 if (bus_space_map(iot, PCI_MAPREG_IO_ADDR(base_addr), 467 SB800_SMB_SIZE, 0, &sc->sc_smb_ioh)) { 468 aprint_error_dev(sc->sc_dev, "can't map smbus I/O space\n"); 469 return EBUSY; 470 } 471 472 return 0; 473 } 474 475 static void 476 piixpm_csb5_reset(void *arg) 477 { 478 struct piixpm_softc *sc = arg; 479 pcireg_t base, hostc, pmbase; 480 481 base = pci_conf_read(sc->sc_pc, sc->sc_pcitag, PIIX_SMB_BASE); 482 hostc = pci_conf_read(sc->sc_pc, sc->sc_pcitag, PIIX_SMB_HOSTC); 483 484 pmbase = pci_conf_read(sc->sc_pc, sc->sc_pcitag, PIIX_PM_BASE); 485 pmbase |= PIIX_PM_BASE_CSB5_RESET; 486 pci_conf_write(sc->sc_pc, sc->sc_pcitag, PIIX_PM_BASE, pmbase); 487 pmbase &= ~PIIX_PM_BASE_CSB5_RESET; 488 pci_conf_write(sc->sc_pc, sc->sc_pcitag, PIIX_PM_BASE, pmbase); 489 490 pci_conf_write(sc->sc_pc, sc->sc_pcitag, PIIX_SMB_BASE, base); 491 pci_conf_write(sc->sc_pc, sc->sc_pcitag, PIIX_SMB_HOSTC, hostc); 492 493 (void) tsleep(&sc, PRIBIO, "csb5reset", hz/2); 494 } 495 496 static int 497 piixpm_i2c_sb800_acquire_bus(void *cookie, int flags) 498 { 499 struct piixpm_smbus *smbus = cookie; 500 struct piixpm_softc *sc = smbus->softc; 501 uint8_t sctl; 502 int i; 503 504 sctl = bus_space_read_1(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_SC); 505 for (i = 0; i < PIIX_SB800_TIMEOUT; i++) { 506 /* Try to acquire the host semaphore */ 507 sctl &= ~PIIX_SMB_SC_SEMMASK; 508 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_SC, 509 sctl | PIIX_SMB_SC_HOSTSEM); 510 511 sctl = bus_space_read_1(sc->sc_smb_iot, sc->sc_smb_ioh, 512 PIIX_SMB_SC); 513 if ((sctl & PIIX_SMB_SC_HOSTSEM) != 0) 514 break; 515 516 delay(1000); 517 } 518 if (i >= PIIX_SB800_TIMEOUT) { 519 device_printf(sc->sc_dev, 520 "Failed to acquire the host semaphore\n"); 521 return -1; 522 } 523 524 if (PIIXPM_IS_KERNCZ(sc)) { 525 bus_space_write_1(sc->sc_iot, sc->sc_sb800_ioh, 526 SB800_INDIRECTIO_INDEX, AMDFCH41_PM_PORT_INDEX); 527 bus_space_write_1(sc->sc_iot, sc->sc_sb800_ioh, 528 SB800_INDIRECTIO_DATA, smbus->sda << 3); 529 } else { 530 if (sc->sc_sb800_selen) { 531 bus_space_write_1(sc->sc_iot, sc->sc_sb800_ioh, 532 SB800_INDIRECTIO_INDEX, SB800_PM_SMBUS0SEL); 533 bus_space_write_1(sc->sc_iot, sc->sc_sb800_ioh, 534 SB800_INDIRECTIO_DATA, 535 __SHIFTIN(smbus->sda, SB800_PM_SMBUS0_MASK_E)); 536 } else { 537 uint8_t data; 538 539 bus_space_write_1(sc->sc_iot, sc->sc_sb800_ioh, 540 SB800_INDIRECTIO_INDEX, SB800_PM_SMBUS0EN_LO); 541 data = bus_space_read_1(sc->sc_iot, sc->sc_sb800_ioh, 542 SB800_INDIRECTIO_DATA) & ~SB800_PM_SMBUS0_MASK_C; 543 data |= __SHIFTIN(smbus->sda, SB800_PM_SMBUS0_MASK_C); 544 bus_space_write_1(sc->sc_iot, sc->sc_sb800_ioh, 545 SB800_INDIRECTIO_DATA, data); 546 } 547 } 548 549 return 0; 550 } 551 552 static void 553 piixpm_i2c_sb800_release_bus(void *cookie, int flags) 554 { 555 struct piixpm_smbus *smbus = cookie; 556 struct piixpm_softc *sc = smbus->softc; 557 uint8_t sctl; 558 559 if (PIIXPM_IS_KERNCZ(sc)) { 560 bus_space_write_1(sc->sc_iot, sc->sc_sb800_ioh, 561 SB800_INDIRECTIO_INDEX, AMDFCH41_PM_PORT_INDEX); 562 /* Set to port 0 */ 563 bus_space_write_1(sc->sc_iot, sc->sc_sb800_ioh, 564 SB800_INDIRECTIO_DATA, 0); 565 } else { 566 if (sc->sc_sb800_selen) { 567 bus_space_write_1(sc->sc_iot, sc->sc_sb800_ioh, 568 SB800_INDIRECTIO_INDEX, SB800_PM_SMBUS0SEL); 569 570 /* Set to port 0 */ 571 bus_space_write_1(sc->sc_iot, sc->sc_sb800_ioh, 572 SB800_INDIRECTIO_DATA, 0); 573 } else { 574 uint8_t data; 575 576 bus_space_write_1(sc->sc_iot, sc->sc_sb800_ioh, 577 SB800_INDIRECTIO_INDEX, SB800_PM_SMBUS0EN_LO); 578 579 /* Set to port 0 */ 580 data = bus_space_read_1(sc->sc_iot, sc->sc_sb800_ioh, 581 SB800_INDIRECTIO_DATA) & ~SB800_PM_SMBUS0_MASK_C; 582 bus_space_write_1(sc->sc_iot, sc->sc_sb800_ioh, 583 SB800_INDIRECTIO_DATA, data); 584 } 585 } 586 587 /* Relase the host semaphore */ 588 sctl = bus_space_read_1(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_SC); 589 sctl &= ~PIIX_SMB_SC_SEMMASK; 590 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_SC, 591 sctl | PIIX_SMB_SC_CLRHOSTSEM); 592 } 593 594 static int 595 piixpm_i2c_exec(void *cookie, i2c_op_t op, i2c_addr_t addr, 596 const void *cmdbuf, size_t cmdlen, void *buf, size_t len, int flags) 597 { 598 struct piixpm_smbus *smbus = cookie; 599 struct piixpm_softc *sc = smbus->softc; 600 const uint8_t *b; 601 uint8_t ctl = 0, st; 602 int retries; 603 604 DPRINTF(("%s: exec: op %d, addr 0x%02x, cmdlen %zu, len %zu, " 605 "flags 0x%x\n", 606 device_xname(sc->sc_dev), op, addr, cmdlen, len, flags)); 607 608 mutex_enter(&sc->sc_exec_lock); 609 610 /* Clear status bits */ 611 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_HS, 612 PIIX_SMB_HS_INTR | PIIX_SMB_HS_DEVERR | 613 PIIX_SMB_HS_BUSERR | PIIX_SMB_HS_FAILED); 614 bus_space_barrier(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_HS, 1, 615 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 616 617 /* Wait for bus to be idle */ 618 for (retries = 100; retries > 0; retries--) { 619 st = bus_space_read_1(sc->sc_smb_iot, sc->sc_smb_ioh, 620 PIIX_SMB_HS); 621 if (!(st & PIIX_SMB_HS_BUSY)) 622 break; 623 DELAY(PIIXPM_DELAY); 624 } 625 DPRINTF(("%s: exec: st %#x\n", device_xname(sc->sc_dev), st & 0xff)); 626 if (st & PIIX_SMB_HS_BUSY) { 627 mutex_exit(&sc->sc_exec_lock); 628 return (EBUSY); 629 } 630 631 if (sc->sc_poll) 632 flags |= I2C_F_POLL; 633 634 if (!I2C_OP_STOP_P(op) || cmdlen > 1 || len > 2 || 635 (cmdlen == 0 && len > 1)) { 636 mutex_exit(&sc->sc_exec_lock); 637 return (EINVAL); 638 } 639 640 /* Setup transfer */ 641 sc->sc_i2c_xfer.op = op; 642 sc->sc_i2c_xfer.buf = buf; 643 sc->sc_i2c_xfer.len = len; 644 sc->sc_i2c_xfer.flags = flags; 645 sc->sc_i2c_xfer.error = 0; 646 sc->sc_i2c_xfer.done = false; 647 648 /* Set slave address and transfer direction */ 649 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_TXSLVA, 650 PIIX_SMB_TXSLVA_ADDR(addr) | 651 (I2C_OP_READ_P(op) ? PIIX_SMB_TXSLVA_READ : 0)); 652 653 b = cmdbuf; 654 if (cmdlen > 0) 655 /* Set command byte */ 656 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, 657 PIIX_SMB_HCMD, b[0]); 658 659 if (I2C_OP_WRITE_P(op)) { 660 /* Write data */ 661 b = buf; 662 if (cmdlen == 0 && len == 1) 663 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, 664 PIIX_SMB_HCMD, b[0]); 665 else if (len > 0) 666 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, 667 PIIX_SMB_HD0, b[0]); 668 if (len > 1) 669 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, 670 PIIX_SMB_HD1, b[1]); 671 } 672 673 /* Set SMBus command */ 674 if (cmdlen == 0) { 675 if (len == 0) 676 ctl = PIIX_SMB_HC_CMD_QUICK; 677 else 678 ctl = PIIX_SMB_HC_CMD_BYTE; 679 } else if (len == 1) 680 ctl = PIIX_SMB_HC_CMD_BDATA; 681 else if (len == 2) 682 ctl = PIIX_SMB_HC_CMD_WDATA; 683 else 684 panic("%s: unexpected len %zu", __func__, len); 685 686 if ((flags & I2C_F_POLL) == 0) 687 ctl |= PIIX_SMB_HC_INTREN; 688 689 /* Start transaction */ 690 ctl |= PIIX_SMB_HC_START; 691 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_HC, ctl); 692 693 if (flags & I2C_F_POLL) { 694 /* Poll for completion */ 695 if (PIIXPM_IS_CSB5(sc)) 696 DELAY(2*PIIXPM_DELAY); 697 else 698 DELAY(PIIXPM_DELAY); 699 for (retries = 1000; retries > 0; retries--) { 700 st = bus_space_read_1(sc->sc_smb_iot, sc->sc_smb_ioh, 701 PIIX_SMB_HS); 702 if ((st & PIIX_SMB_HS_BUSY) == 0) 703 break; 704 DELAY(PIIXPM_DELAY); 705 } 706 if (st & PIIX_SMB_HS_BUSY) 707 goto timeout; 708 piixpm_intr(sc); 709 } else { 710 /* Wait for interrupt */ 711 while (! sc->sc_i2c_xfer.done) { 712 if (cv_timedwait(&sc->sc_exec_wait, &sc->sc_exec_lock, 713 PIIXPM_TIMEOUT * hz)) 714 goto timeout; 715 } 716 } 717 718 int error = sc->sc_i2c_xfer.error; 719 mutex_exit(&sc->sc_exec_lock); 720 721 return (error); 722 723 timeout: 724 /* 725 * Transfer timeout. Kill the transaction and clear status bits. 726 */ 727 aprint_error_dev(sc->sc_dev, "timeout, status 0x%x\n", st); 728 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_HC, 729 PIIX_SMB_HC_KILL); 730 DELAY(PIIXPM_DELAY); 731 st = bus_space_read_1(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_HS); 732 if ((st & PIIX_SMB_HS_FAILED) == 0) 733 aprint_error_dev(sc->sc_dev, 734 "transaction abort failed, status 0x%x\n", st); 735 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_HS, st); 736 /* 737 * CSB5 needs hard reset to unlock the smbus after timeout. 738 */ 739 if (PIIXPM_IS_CSB5(sc)) 740 piixpm_csb5_reset(sc); 741 mutex_exit(&sc->sc_exec_lock); 742 return (ETIMEDOUT); 743 } 744 745 static int 746 piixpm_intr(void *arg) 747 { 748 struct piixpm_softc *sc = arg; 749 uint8_t st; 750 uint8_t *b; 751 size_t len; 752 753 /* Read status */ 754 st = bus_space_read_1(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_HS); 755 if ((st & PIIX_SMB_HS_BUSY) != 0 || (st & (PIIX_SMB_HS_INTR | 756 PIIX_SMB_HS_DEVERR | PIIX_SMB_HS_BUSERR | 757 PIIX_SMB_HS_FAILED)) == 0) 758 /* Interrupt was not for us */ 759 return (0); 760 761 DPRINTF(("%s: intr st %#x\n", device_xname(sc->sc_dev), st & 0xff)); 762 763 if ((sc->sc_i2c_xfer.flags & I2C_F_POLL) == 0) 764 mutex_enter(&sc->sc_exec_lock); 765 766 /* Clear status bits */ 767 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_HS, st); 768 769 /* Check for errors */ 770 if (st & (PIIX_SMB_HS_DEVERR | PIIX_SMB_HS_BUSERR | 771 PIIX_SMB_HS_FAILED)) { 772 sc->sc_i2c_xfer.error = EIO; 773 goto done; 774 } 775 776 if (st & PIIX_SMB_HS_INTR) { 777 if (I2C_OP_WRITE_P(sc->sc_i2c_xfer.op)) 778 goto done; 779 780 /* Read data */ 781 b = sc->sc_i2c_xfer.buf; 782 len = sc->sc_i2c_xfer.len; 783 if (len > 0) 784 b[0] = bus_space_read_1(sc->sc_smb_iot, sc->sc_smb_ioh, 785 PIIX_SMB_HD0); 786 if (len > 1) 787 b[1] = bus_space_read_1(sc->sc_smb_iot, sc->sc_smb_ioh, 788 PIIX_SMB_HD1); 789 } 790 791 done: 792 sc->sc_i2c_xfer.done = true; 793 if ((sc->sc_i2c_xfer.flags & I2C_F_POLL) == 0) { 794 cv_signal(&sc->sc_exec_wait); 795 mutex_exit(&sc->sc_exec_lock); 796 } 797 return (1); 798 } 799
Indexes created Mon Sep 29 21:09:56 GMT 2025