piixpm.c revision 1.63
1 /* $NetBSD: piixpm.c,v 1.63 2020/01/14 15:42:03 msaitoh Exp $ */ 2 /* $OpenBSD: piixpm.c,v 1.39 2013/10/01 20:06:02 sf Exp $ */ 3 4 /* 5 * Copyright (c) 2005, 2006 Alexander Yurchenko <grange (at) openbsd.org> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 /* 21 * Intel PIIX and compatible Power Management controller driver. 22 */ 23 24 #include <sys/cdefs.h> 25 __KERNEL_RCSID(0, "$NetBSD: piixpm.c,v 1.63 2020/01/14 15:42:03 msaitoh Exp $"); 26 27 #include <sys/param.h> 28 #include <sys/systm.h> 29 #include <sys/device.h> 30 #include <sys/kernel.h> 31 #include <sys/mutex.h> 32 #include <sys/condvar.h> 33 #include <sys/proc.h> 34 35 #include <sys/bus.h> 36 37 #include <dev/pci/pcidevs.h> 38 #include <dev/pci/pcireg.h> 39 #include <dev/pci/pcivar.h> 40 41 #include <dev/pci/piixpmreg.h> 42 43 #include <dev/i2c/i2cvar.h> 44 45 #include <dev/ic/acpipmtimer.h> 46 47 #ifdef PIIXPM_DEBUG 48 #define DPRINTF(x) printf x 49 #else 50 #define DPRINTF(x) 51 #endif 52 53 #define PIIXPM_IS_CSB5(sc) \ 54 (PCI_VENDOR((sc)->sc_id) == PCI_VENDOR_SERVERWORKS && \ 55 PCI_PRODUCT((sc)->sc_id) == PCI_PRODUCT_SERVERWORKS_CSB5) 56 #define PIIXPM_DELAY 200 57 #define PIIXPM_TIMEOUT 1 58 59 #define PIIXPM_IS_SB800GRP(sc) \ 60 ((PCI_VENDOR((sc)->sc_id) == PCI_VENDOR_ATI) && \ 61 ((PCI_PRODUCT((sc)->sc_id) == PCI_PRODUCT_ATI_SB600_SMB) && \ 62 ((sc)->sc_rev >= 0x40))) 63 64 #define PIIXPM_IS_HUDSON(sc) \ 65 ((PCI_VENDOR((sc)->sc_id) == PCI_VENDOR_AMD) && \ 66 (PCI_PRODUCT((sc)->sc_id) == PCI_PRODUCT_AMD_HUDSON_SMB)) 67 68 #define PIIXPM_IS_KERNCZ(sc) \ 69 ((PCI_VENDOR((sc)->sc_id) == PCI_VENDOR_AMD) && \ 70 (PCI_PRODUCT((sc)->sc_id) == PCI_PRODUCT_AMD_KERNCZ_SMB)) 71 72 #define PIIXPM_IS_FCHGRP(sc) (PIIXPM_IS_HUDSON(sc) || PIIXPM_IS_KERNCZ(sc)) 73 74 #define PIIX_SB800_TIMEOUT 500 75 76 struct piixpm_smbus { 77 int sda; 78 int sda_save; 79 struct piixpm_softc *softc; 80 }; 81 82 struct piixpm_softc { 83 device_t sc_dev; 84 85 bus_space_tag_t sc_iot; 86 #define sc_pm_iot sc_iot 87 #define sc_smb_iot sc_iot 88 bus_space_handle_t sc_pm_ioh; 89 bus_space_handle_t sc_sb800_ioh; 90 bus_space_handle_t sc_smb_ioh; 91 void * sc_smb_ih; 92 int sc_poll; 93 bool sc_sb800_selen; /* Use SMBUS0SEL */ 94 95 pci_chipset_tag_t sc_pc; 96 pcitag_t sc_pcitag; 97 pcireg_t sc_id; 98 pcireg_t sc_rev; 99 100 int sc_numbusses; 101 device_t sc_i2c_device[4]; 102 struct piixpm_smbus sc_busses[4]; 103 struct i2c_controller sc_i2c_tags[4]; 104 105 kmutex_t sc_exec_lock; 106 kcondvar_t sc_exec_wait; 107 108 struct { 109 i2c_op_t op; 110 void * buf; 111 size_t len; 112 int flags; 113 int error; 114 bool done; 115 } sc_i2c_xfer; 116 117 pcireg_t sc_devact[2]; 118 }; 119 120 static int piixpm_match(device_t, cfdata_t, void *); 121 static void piixpm_attach(device_t, device_t, void *); 122 static int piixpm_rescan(device_t, const char *, const int *); 123 static void piixpm_chdet(device_t, device_t); 124 125 static bool piixpm_suspend(device_t, const pmf_qual_t *); 126 static bool piixpm_resume(device_t, const pmf_qual_t *); 127 128 static int piixpm_sb800_init(struct piixpm_softc *); 129 static void piixpm_csb5_reset(void *); 130 static int piixpm_i2c_sb800_acquire_bus(void *, int); 131 static void piixpm_i2c_sb800_release_bus(void *, int); 132 static int piixpm_i2c_exec(void *, i2c_op_t, i2c_addr_t, const void *, 133 size_t, void *, size_t, int); 134 135 static int piixpm_intr(void *); 136 137 CFATTACH_DECL3_NEW(piixpm, sizeof(struct piixpm_softc), 138 piixpm_match, piixpm_attach, NULL, NULL, piixpm_rescan, piixpm_chdet, 0); 139 140 static int 141 piixpm_match(device_t parent, cfdata_t match, void *aux) 142 { 143 struct pci_attach_args *pa; 144 145 pa = (struct pci_attach_args *)aux; 146 switch (PCI_VENDOR(pa->pa_id)) { 147 case PCI_VENDOR_INTEL: 148 switch (PCI_PRODUCT(pa->pa_id)) { 149 case PCI_PRODUCT_INTEL_82371AB_PMC: 150 case PCI_PRODUCT_INTEL_82440MX_PMC: 151 return 1; 152 } 153 break; 154 case PCI_VENDOR_ATI: 155 switch (PCI_PRODUCT(pa->pa_id)) { 156 case PCI_PRODUCT_ATI_SB200_SMB: 157 case PCI_PRODUCT_ATI_SB300_SMB: 158 case PCI_PRODUCT_ATI_SB400_SMB: 159 case PCI_PRODUCT_ATI_SB600_SMB: /* matches SB600/SB700/SB800 */ 160 return 1; 161 } 162 break; 163 case PCI_VENDOR_SERVERWORKS: 164 switch (PCI_PRODUCT(pa->pa_id)) { 165 case PCI_PRODUCT_SERVERWORKS_OSB4: 166 case PCI_PRODUCT_SERVERWORKS_CSB5: 167 case PCI_PRODUCT_SERVERWORKS_CSB6: 168 case PCI_PRODUCT_SERVERWORKS_HT1000SB: 169 case PCI_PRODUCT_SERVERWORKS_HT1100SB: 170 return 1; 171 } 172 break; 173 case PCI_VENDOR_AMD: 174 switch (PCI_PRODUCT(pa->pa_id)) { 175 case PCI_PRODUCT_AMD_HUDSON_SMB: 176 case PCI_PRODUCT_AMD_KERNCZ_SMB: 177 return 1; 178 } 179 break; 180 } 181 182 return 0; 183 } 184 185 static void 186 piixpm_attach(device_t parent, device_t self, void *aux) 187 { 188 struct piixpm_softc *sc = device_private(self); 189 struct pci_attach_args *pa = aux; 190 pcireg_t base, conf; 191 pcireg_t pmmisc; 192 pci_intr_handle_t ih; 193 bool usesmi = false; 194 const char *intrstr = NULL; 195 int i, flags; 196 char intrbuf[PCI_INTRSTR_LEN]; 197 198 sc->sc_dev = self; 199 sc->sc_iot = pa->pa_iot; 200 sc->sc_id = pa->pa_id; 201 sc->sc_rev = PCI_REVISION(pa->pa_class); 202 sc->sc_pc = pa->pa_pc; 203 sc->sc_pcitag = pa->pa_tag; 204 sc->sc_numbusses = 1; 205 206 pci_aprint_devinfo(pa, NULL); 207 208 mutex_init(&sc->sc_exec_lock, MUTEX_DEFAULT, IPL_BIO); 209 cv_init(&sc->sc_exec_wait, device_xname(self)); 210 211 if (!pmf_device_register(self, piixpm_suspend, piixpm_resume)) 212 aprint_error_dev(self, "couldn't establish power handler\n"); 213 214 if ((PCI_VENDOR(pa->pa_id) != PCI_VENDOR_INTEL) || 215 (PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_INTEL_82371AB_PMC)) 216 goto nopowermanagement; 217 218 /* check whether I/O access to PM regs is enabled */ 219 pmmisc = pci_conf_read(pa->pa_pc, pa->pa_tag, PIIX_PMREGMISC); 220 if (!(pmmisc & 1)) 221 goto nopowermanagement; 222 223 /* Map I/O space */ 224 base = pci_conf_read(pa->pa_pc, pa->pa_tag, PIIX_PM_BASE); 225 if (base == 0 || bus_space_map(sc->sc_pm_iot, PCI_MAPREG_IO_ADDR(base), 226 PIIX_PM_SIZE, 0, &sc->sc_pm_ioh)) { 227 aprint_error_dev(self, 228 "can't map power management I/O space\n"); 229 goto nopowermanagement; 230 } 231 232 /* 233 * Revision 0 and 1 are PIIX4, 2 is PIIX4E, 3 is PIIX4M. 234 * PIIX4 and PIIX4E have a bug in the timer latch, see Errata #20 235 * in the "Specification update" (document #297738). 236 */ 237 acpipmtimer_attach(self, sc->sc_pm_iot, sc->sc_pm_ioh, PIIX_PM_PMTMR, 238 (PCI_REVISION(pa->pa_class) < 3) ? ACPIPMT_BADLATCH : 0); 239 240 nopowermanagement: 241 242 /* SB800 rev 0x40+, AMD HUDSON and newer need special initialization */ 243 if (PIIXPM_IS_FCHGRP(sc) || PIIXPM_IS_SB800GRP(sc)) { 244 if (piixpm_sb800_init(sc) == 0) { 245 /* Read configuration */ 246 conf = bus_space_read_1(sc->sc_iot, 247 sc->sc_smb_ioh, SB800_SMB_HOSTC); 248 usesmi = ((conf & SB800_SMB_HOSTC_IRQ) == 0); 249 goto setintr; 250 } 251 aprint_normal_dev(self, "SMBus initialization failed\n"); 252 return; 253 } 254 255 /* Read configuration */ 256 conf = pci_conf_read(pa->pa_pc, pa->pa_tag, PIIX_SMB_HOSTC); 257 DPRINTF(("%s: conf 0x%08x\n", device_xname(self), conf)); 258 259 if ((conf & PIIX_SMB_HOSTC_HSTEN) == 0) { 260 aprint_normal_dev(self, "SMBus disabled\n"); 261 return; 262 } 263 usesmi = (conf & PIIX_SMB_HOSTC_INTMASK) == PIIX_SMB_HOSTC_SMI; 264 265 /* Map I/O space */ 266 base = pci_conf_read(pa->pa_pc, pa->pa_tag, PIIX_SMB_BASE) & 0xffff; 267 if (base == 0 || 268 bus_space_map(sc->sc_smb_iot, PCI_MAPREG_IO_ADDR(base), 269 PIIX_SMB_SIZE, 0, &sc->sc_smb_ioh)) { 270 aprint_error_dev(self, "can't map smbus I/O space\n"); 271 return; 272 } 273 274 setintr: 275 sc->sc_poll = 1; 276 aprint_normal_dev(self, ""); 277 if (usesmi) { 278 /* No PCI IRQ */ 279 aprint_normal("interrupting at SMI, "); 280 } else { 281 if ((conf & PIIX_SMB_HOSTC_INTMASK) == PIIX_SMB_HOSTC_IRQ) { 282 /* Install interrupt handler */ 283 if (pci_intr_map(pa, &ih) == 0) { 284 intrstr = pci_intr_string(pa->pa_pc, ih, 285 intrbuf, sizeof(intrbuf)); 286 pci_intr_setattr(pa->pa_pc, &ih, 287 PCI_INTR_MPSAFE, true); 288 sc->sc_smb_ih = pci_intr_establish_xname( 289 pa->pa_pc, ih, IPL_BIO, piixpm_intr, 290 sc, device_xname(sc->sc_dev)); 291 if (sc->sc_smb_ih != NULL) { 292 aprint_normal("interrupting at %s", 293 intrstr); 294 sc->sc_poll = 0; 295 } 296 } 297 } 298 if (sc->sc_poll) 299 aprint_normal("polling"); 300 } 301 302 aprint_normal("\n"); 303 304 for (i = 0; i < sc->sc_numbusses; i++) 305 sc->sc_i2c_device[i] = NULL; 306 307 flags = 0; 308 piixpm_rescan(self, "i2cbus", &flags); 309 } 310 311 static int 312 piixpm_iicbus_print(void *aux, const char *pnp) 313 { 314 struct i2cbus_attach_args *iba = aux; 315 struct i2c_controller *tag = iba->iba_tag; 316 struct piixpm_smbus *bus = tag->ic_cookie; 317 struct piixpm_softc *sc = bus->softc; 318 319 iicbus_print(aux, pnp); 320 if (sc->sc_numbusses != 0) 321 aprint_normal(" port %d", bus->sda); 322 323 return UNCONF; 324 } 325 static int 326 piixpm_rescan(device_t self, const char *ifattr, const int *flags) 327 { 328 struct piixpm_softc *sc = device_private(self); 329 struct i2cbus_attach_args iba; 330 int i; 331 332 if (!ifattr_match(ifattr, "i2cbus")) 333 return 0; 334 335 /* Attach I2C bus */ 336 337 for (i = 0; i < sc->sc_numbusses; i++) { 338 struct i2c_controller *tag = &sc->sc_i2c_tags[i]; 339 340 if (sc->sc_i2c_device[i]) 341 continue; 342 sc->sc_busses[i].sda = i; 343 sc->sc_busses[i].softc = sc; 344 iic_tag_init(tag); 345 tag->ic_cookie = &sc->sc_busses[i]; 346 if (PIIXPM_IS_SB800GRP(sc) || PIIXPM_IS_FCHGRP(sc)) { 347 tag->ic_acquire_bus = piixpm_i2c_sb800_acquire_bus; 348 tag->ic_release_bus = piixpm_i2c_sb800_release_bus; 349 } else { 350 tag->ic_acquire_bus = NULL; 351 tag->ic_release_bus = NULL; 352 } 353 tag->ic_exec = piixpm_i2c_exec; 354 memset(&iba, 0, sizeof(iba)); 355 iba.iba_tag = tag; 356 sc->sc_i2c_device[i] = config_found_ia(self, ifattr, &iba, 357 piixpm_iicbus_print); 358 } 359 360 return 0; 361 } 362 363 static void 364 piixpm_chdet(device_t self, device_t child) 365 { 366 struct piixpm_softc *sc = device_private(self); 367 int i; 368 369 for (i = 0; i < sc->sc_numbusses; i++) { 370 if (sc->sc_i2c_device[i] == child) { 371 sc->sc_i2c_device[i] = NULL; 372 break; 373 } 374 } 375 } 376 377 378 static bool 379 piixpm_suspend(device_t dv, const pmf_qual_t *qual) 380 { 381 struct piixpm_softc *sc = device_private(dv); 382 383 sc->sc_devact[0] = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 384 PIIX_DEVACTA); 385 sc->sc_devact[1] = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 386 PIIX_DEVACTB); 387 388 return true; 389 } 390 391 static bool 392 piixpm_resume(device_t dv, const pmf_qual_t *qual) 393 { 394 struct piixpm_softc *sc = device_private(dv); 395 396 pci_conf_write(sc->sc_pc, sc->sc_pcitag, PIIX_DEVACTA, 397 sc->sc_devact[0]); 398 pci_conf_write(sc->sc_pc, sc->sc_pcitag, PIIX_DEVACTB, 399 sc->sc_devact[1]); 400 401 return true; 402 } 403 404 /* 405 * Extract SMBus base address from SB800 Power Management (PM) registers. 406 * The PM registers can be accessed either through indirect I/O (CD6/CD7) or 407 * direct mapping if AcpiMMioDecodeEn is enabled. Since this function is only 408 * called once it uses indirect I/O for simplicity. 409 */ 410 static int 411 piixpm_sb800_init(struct piixpm_softc *sc) 412 { 413 bus_space_tag_t iot = sc->sc_iot; 414 bus_space_handle_t ioh; /* indirect I/O handle */ 415 uint16_t val, base_addr; 416 bool enabled; 417 418 if (PIIXPM_IS_KERNCZ(sc) || 419 (PIIXPM_IS_HUDSON(sc) && (sc->sc_rev >= 0x1f))) 420 sc->sc_numbusses = 2; 421 else 422 sc->sc_numbusses = 4; 423 424 /* Fetch SMB base address */ 425 if (bus_space_map(iot, 426 SB800_INDIRECTIO_BASE, SB800_INDIRECTIO_SIZE, 0, &ioh)) { 427 device_printf(sc->sc_dev, "couldn't map indirect I/O space\n"); 428 return EBUSY; 429 } 430 if (PIIXPM_IS_FCHGRP(sc)) { 431 bus_space_write_1(iot, ioh, SB800_INDIRECTIO_INDEX, 432 AMDFCH41_PM_DECODE_EN0); 433 val = bus_space_read_1(iot, ioh, SB800_INDIRECTIO_DATA); 434 enabled = val & AMDFCH41_SMBUS_EN; 435 if (!enabled) 436 return ENOENT; 437 438 bus_space_write_1(iot, ioh, SB800_INDIRECTIO_INDEX, 439 AMDFCH41_PM_DECODE_EN1); 440 val = bus_space_read_1(iot, ioh, SB800_INDIRECTIO_DATA) << 8; 441 base_addr = val; 442 } else { 443 uint8_t data; 444 445 bus_space_write_1(iot, ioh, SB800_INDIRECTIO_INDEX, 446 SB800_PM_SMBUS0EN_LO); 447 val = bus_space_read_1(iot, ioh, SB800_INDIRECTIO_DATA); 448 enabled = val & SB800_PM_SMBUS0EN_ENABLE; 449 if (!enabled) 450 return ENOENT; 451 452 bus_space_write_1(iot, ioh, SB800_INDIRECTIO_INDEX, 453 SB800_PM_SMBUS0EN_HI); 454 val |= bus_space_read_1(iot, ioh, SB800_INDIRECTIO_DATA) << 8; 455 base_addr = val & SB800_PM_SMBUS0EN_BADDR; 456 457 bus_space_write_1(iot, ioh, SB800_INDIRECTIO_INDEX, 458 SB800_PM_SMBUS0SELEN); 459 data = bus_space_read_1(iot, ioh, SB800_INDIRECTIO_DATA); 460 if ((data & SB800_PM_USE_SMBUS0SEL) != 0) 461 sc->sc_sb800_selen = true; 462 } 463 464 sc->sc_sb800_ioh = ioh; 465 aprint_debug_dev(sc->sc_dev, "SMBus @ 0x%04x\n", base_addr); 466 467 if (bus_space_map(iot, PCI_MAPREG_IO_ADDR(base_addr), 468 SB800_SMB_SIZE, 0, &sc->sc_smb_ioh)) { 469 aprint_error_dev(sc->sc_dev, "can't map smbus I/O space\n"); 470 return EBUSY; 471 } 472 473 return 0; 474 } 475 476 static void 477 piixpm_csb5_reset(void *arg) 478 { 479 struct piixpm_softc *sc = arg; 480 pcireg_t base, hostc, pmbase; 481 482 base = pci_conf_read(sc->sc_pc, sc->sc_pcitag, PIIX_SMB_BASE); 483 hostc = pci_conf_read(sc->sc_pc, sc->sc_pcitag, PIIX_SMB_HOSTC); 484 485 pmbase = pci_conf_read(sc->sc_pc, sc->sc_pcitag, PIIX_PM_BASE); 486 pmbase |= PIIX_PM_BASE_CSB5_RESET; 487 pci_conf_write(sc->sc_pc, sc->sc_pcitag, PIIX_PM_BASE, pmbase); 488 pmbase &= ~PIIX_PM_BASE_CSB5_RESET; 489 pci_conf_write(sc->sc_pc, sc->sc_pcitag, PIIX_PM_BASE, pmbase); 490 491 pci_conf_write(sc->sc_pc, sc->sc_pcitag, PIIX_SMB_BASE, base); 492 pci_conf_write(sc->sc_pc, sc->sc_pcitag, PIIX_SMB_HOSTC, hostc); 493 494 (void) tsleep(&sc, PRIBIO, "csb5reset", hz/2); 495 } 496 497 static int 498 piixpm_i2c_sb800_acquire_bus(void *cookie, int flags) 499 { 500 struct piixpm_smbus *smbus = cookie; 501 struct piixpm_softc *sc = smbus->softc; 502 uint8_t sctl, old_sda, index, mask, reg; 503 int i; 504 505 sctl = bus_space_read_1(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_SC); 506 for (i = 0; i < PIIX_SB800_TIMEOUT; i++) { 507 /* Try to acquire the host semaphore */ 508 sctl &= ~PIIX_SMB_SC_SEMMASK; 509 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_SC, 510 sctl | PIIX_SMB_SC_HOSTSEM); 511 512 sctl = bus_space_read_1(sc->sc_smb_iot, sc->sc_smb_ioh, 513 PIIX_SMB_SC); 514 if ((sctl & PIIX_SMB_SC_HOSTSEM) != 0) 515 break; 516 517 delay(1000); 518 } 519 if (i >= PIIX_SB800_TIMEOUT) { 520 device_printf(sc->sc_dev, 521 "Failed to acquire the host semaphore\n"); 522 return -1; 523 } 524 525 if (PIIXPM_IS_KERNCZ(sc) || 526 (PIIXPM_IS_HUDSON(sc) && (sc->sc_rev >= 0x1f))) { 527 index = AMDFCH41_PM_PORT_INDEX; 528 mask = AMDFCH41_SMBUS_PORTMASK; 529 } else if (sc->sc_sb800_selen) { 530 index = SB800_PM_SMBUS0SEL; 531 mask = SB800_PM_SMBUS0_MASK_E; 532 } else { 533 index = SB800_PM_SMBUS0EN_LO; 534 mask = SB800_PM_SMBUS0_MASK_C; 535 } 536 537 bus_space_write_1(sc->sc_iot, sc->sc_sb800_ioh, 538 SB800_INDIRECTIO_INDEX, index); 539 reg = bus_space_read_1(sc->sc_iot, sc->sc_sb800_ioh, 540 SB800_INDIRECTIO_DATA); 541 542 old_sda = __SHIFTOUT(reg, mask); 543 if (smbus->sda != old_sda) { 544 reg &= ~mask; 545 reg |= __SHIFTIN(smbus->sda, mask); 546 bus_space_write_1(sc->sc_iot, sc->sc_sb800_ioh, 547 SB800_INDIRECTIO_DATA, reg); 548 } 549 550 /* Save the old port number */ 551 smbus->sda_save = old_sda; 552 553 return 0; 554 } 555 556 static void 557 piixpm_i2c_sb800_release_bus(void *cookie, int flags) 558 { 559 struct piixpm_smbus *smbus = cookie; 560 struct piixpm_softc *sc = smbus->softc; 561 uint8_t sctl, index, mask, reg; 562 563 if (PIIXPM_IS_KERNCZ(sc) || 564 (PIIXPM_IS_HUDSON(sc) && (sc->sc_rev >= 0x1f))) { 565 index = AMDFCH41_PM_PORT_INDEX; 566 mask = AMDFCH41_SMBUS_PORTMASK; 567 } else if (sc->sc_sb800_selen) { 568 index = SB800_PM_SMBUS0SEL; 569 mask = SB800_PM_SMBUS0_MASK_E; 570 } else { 571 index = SB800_PM_SMBUS0EN_LO; 572 mask = SB800_PM_SMBUS0_MASK_C; 573 } 574 575 bus_space_write_1(sc->sc_iot, sc->sc_sb800_ioh, 576 SB800_INDIRECTIO_INDEX, index); 577 if (smbus->sda != smbus->sda_save) { 578 /* Restore the port number */ 579 reg = bus_space_read_1(sc->sc_iot, sc->sc_sb800_ioh, 580 SB800_INDIRECTIO_DATA); 581 reg &= ~mask; 582 reg |= __SHIFTIN(smbus->sda_save, mask); 583 bus_space_write_1(sc->sc_iot, sc->sc_sb800_ioh, 584 SB800_INDIRECTIO_DATA, reg); 585 } 586 587 /* Relase the host semaphore */ 588 sctl = bus_space_read_1(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_SC); 589 sctl &= ~PIIX_SMB_SC_SEMMASK; 590 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_SC, 591 sctl | PIIX_SMB_SC_CLRHOSTSEM); 592 } 593 594 static int 595 piixpm_i2c_exec(void *cookie, i2c_op_t op, i2c_addr_t addr, 596 const void *cmdbuf, size_t cmdlen, void *buf, size_t len, int flags) 597 { 598 struct piixpm_smbus *smbus = cookie; 599 struct piixpm_softc *sc = smbus->softc; 600 const uint8_t *b; 601 uint8_t ctl = 0, st; 602 int retries; 603 604 DPRINTF(("%s: exec: op %d, addr 0x%02x, cmdlen %zu, len %zu, " 605 "flags 0x%x\n", 606 device_xname(sc->sc_dev), op, addr, cmdlen, len, flags)); 607 608 mutex_enter(&sc->sc_exec_lock); 609 610 /* Clear status bits */ 611 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_HS, 612 PIIX_SMB_HS_INTR | PIIX_SMB_HS_DEVERR | 613 PIIX_SMB_HS_BUSERR | PIIX_SMB_HS_FAILED); 614 bus_space_barrier(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_HS, 1, 615 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 616 617 /* Wait for bus to be idle */ 618 for (retries = 100; retries > 0; retries--) { 619 st = bus_space_read_1(sc->sc_smb_iot, sc->sc_smb_ioh, 620 PIIX_SMB_HS); 621 if (!(st & PIIX_SMB_HS_BUSY)) 622 break; 623 DELAY(PIIXPM_DELAY); 624 } 625 DPRINTF(("%s: exec: st %#x\n", device_xname(sc->sc_dev), st & 0xff)); 626 if (st & PIIX_SMB_HS_BUSY) { 627 mutex_exit(&sc->sc_exec_lock); 628 return (EBUSY); 629 } 630 631 if (sc->sc_poll) 632 flags |= I2C_F_POLL; 633 634 if (!I2C_OP_STOP_P(op) || cmdlen > 1 || len > 2 || 635 (cmdlen == 0 && len > 1)) { 636 mutex_exit(&sc->sc_exec_lock); 637 return (EINVAL); 638 } 639 640 /* Setup transfer */ 641 sc->sc_i2c_xfer.op = op; 642 sc->sc_i2c_xfer.buf = buf; 643 sc->sc_i2c_xfer.len = len; 644 sc->sc_i2c_xfer.flags = flags; 645 sc->sc_i2c_xfer.error = 0; 646 sc->sc_i2c_xfer.done = false; 647 648 /* Set slave address and transfer direction */ 649 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_TXSLVA, 650 PIIX_SMB_TXSLVA_ADDR(addr) | 651 (I2C_OP_READ_P(op) ? PIIX_SMB_TXSLVA_READ : 0)); 652 653 b = cmdbuf; 654 if (cmdlen > 0) 655 /* Set command byte */ 656 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, 657 PIIX_SMB_HCMD, b[0]); 658 659 if (I2C_OP_WRITE_P(op)) { 660 /* Write data */ 661 b = buf; 662 if (cmdlen == 0 && len == 1) 663 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, 664 PIIX_SMB_HCMD, b[0]); 665 else if (len > 0) 666 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, 667 PIIX_SMB_HD0, b[0]); 668 if (len > 1) 669 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, 670 PIIX_SMB_HD1, b[1]); 671 } 672 673 /* Set SMBus command */ 674 if (cmdlen == 0) { 675 if (len == 0) 676 ctl = PIIX_SMB_HC_CMD_QUICK; 677 else 678 ctl = PIIX_SMB_HC_CMD_BYTE; 679 } else if (len == 1) 680 ctl = PIIX_SMB_HC_CMD_BDATA; 681 else if (len == 2) 682 ctl = PIIX_SMB_HC_CMD_WDATA; 683 else 684 panic("%s: unexpected len %zu", __func__, len); 685 686 if ((flags & I2C_F_POLL) == 0) 687 ctl |= PIIX_SMB_HC_INTREN; 688 689 /* Start transaction */ 690 ctl |= PIIX_SMB_HC_START; 691 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_HC, ctl); 692 693 if (flags & I2C_F_POLL) { 694 /* Poll for completion */ 695 if (PIIXPM_IS_CSB5(sc)) 696 DELAY(2*PIIXPM_DELAY); 697 else 698 DELAY(PIIXPM_DELAY); 699 for (retries = 1000; retries > 0; retries--) { 700 st = bus_space_read_1(sc->sc_smb_iot, sc->sc_smb_ioh, 701 PIIX_SMB_HS); 702 if ((st & PIIX_SMB_HS_BUSY) == 0) 703 break; 704 DELAY(PIIXPM_DELAY); 705 } 706 if (st & PIIX_SMB_HS_BUSY) 707 goto timeout; 708 piixpm_intr(sc); 709 } else { 710 /* Wait for interrupt */ 711 while (! sc->sc_i2c_xfer.done) { 712 if (cv_timedwait(&sc->sc_exec_wait, &sc->sc_exec_lock, 713 PIIXPM_TIMEOUT * hz)) 714 goto timeout; 715 } 716 } 717 718 int error = sc->sc_i2c_xfer.error; 719 mutex_exit(&sc->sc_exec_lock); 720 721 return (error); 722 723 timeout: 724 /* 725 * Transfer timeout. Kill the transaction and clear status bits. 726 */ 727 aprint_error_dev(sc->sc_dev, "timeout, status 0x%x\n", st); 728 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_HC, 729 PIIX_SMB_HC_KILL); 730 DELAY(PIIXPM_DELAY); 731 st = bus_space_read_1(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_HS); 732 if ((st & PIIX_SMB_HS_FAILED) == 0) 733 aprint_error_dev(sc->sc_dev, 734 "transaction abort failed, status 0x%x\n", st); 735 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_HS, st); 736 /* 737 * CSB5 needs hard reset to unlock the smbus after timeout. 738 */ 739 if (PIIXPM_IS_CSB5(sc)) 740 piixpm_csb5_reset(sc); 741 mutex_exit(&sc->sc_exec_lock); 742 return (ETIMEDOUT); 743 } 744 745 static int 746 piixpm_intr(void *arg) 747 { 748 struct piixpm_softc *sc = arg; 749 uint8_t st; 750 uint8_t *b; 751 size_t len; 752 753 /* Read status */ 754 st = bus_space_read_1(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_HS); 755 if ((st & PIIX_SMB_HS_BUSY) != 0 || (st & (PIIX_SMB_HS_INTR | 756 PIIX_SMB_HS_DEVERR | PIIX_SMB_HS_BUSERR | 757 PIIX_SMB_HS_FAILED)) == 0) 758 /* Interrupt was not for us */ 759 return (0); 760 761 DPRINTF(("%s: intr st %#x\n", device_xname(sc->sc_dev), st & 0xff)); 762 763 if ((sc->sc_i2c_xfer.flags & I2C_F_POLL) == 0) 764 mutex_enter(&sc->sc_exec_lock); 765 766 /* Clear status bits */ 767 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_HS, st); 768 769 /* Check for errors */ 770 if (st & (PIIX_SMB_HS_DEVERR | PIIX_SMB_HS_BUSERR | 771 PIIX_SMB_HS_FAILED)) { 772 sc->sc_i2c_xfer.error = EIO; 773 goto done; 774 } 775 776 if (st & PIIX_SMB_HS_INTR) { 777 if (I2C_OP_WRITE_P(sc->sc_i2c_xfer.op)) 778 goto done; 779 780 /* Read data */ 781 b = sc->sc_i2c_xfer.buf; 782 len = sc->sc_i2c_xfer.len; 783 if (len > 0) 784 b[0] = bus_space_read_1(sc->sc_smb_iot, sc->sc_smb_ioh, 785 PIIX_SMB_HD0); 786 if (len > 1) 787 b[1] = bus_space_read_1(sc->sc_smb_iot, sc->sc_smb_ioh, 788 PIIX_SMB_HD1); 789 } 790 791 done: 792 sc->sc_i2c_xfer.done = true; 793 if ((sc->sc_i2c_xfer.flags & I2C_F_POLL) == 0) { 794 cv_signal(&sc->sc_exec_wait); 795 mutex_exit(&sc->sc_exec_lock); 796 } 797 return (1); 798 } 799
Indexes created Sun Sep 28 16:09:52 GMT 2025