piixpm.c revision 1.65
1 /* $NetBSD: piixpm.c,v 1.65 2021/08/07 16:19:14 thorpej Exp $ */ 2 /* $OpenBSD: piixpm.c,v 1.39 2013/10/01 20:06:02 sf Exp $ */ 3 4 /* 5 * Copyright (c) 2005, 2006 Alexander Yurchenko <grange (at) openbsd.org> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 /* 21 * Intel PIIX and compatible Power Management controller driver. 22 */ 23 24 #include <sys/cdefs.h> 25 __KERNEL_RCSID(0, "$NetBSD: piixpm.c,v 1.65 2021/08/07 16:19:14 thorpej Exp $"); 26 27 #include <sys/param.h> 28 #include <sys/systm.h> 29 #include <sys/device.h> 30 #include <sys/kernel.h> 31 #include <sys/mutex.h> 32 #include <sys/condvar.h> 33 #include <sys/proc.h> 34 35 #include <sys/bus.h> 36 37 #include <dev/pci/pcidevs.h> 38 #include <dev/pci/pcireg.h> 39 #include <dev/pci/pcivar.h> 40 41 #include <dev/pci/piixpmreg.h> 42 43 #include <dev/i2c/i2cvar.h> 44 45 #include <dev/ic/acpipmtimer.h> 46 47 #ifdef PIIXPM_DEBUG 48 #define DPRINTF(x) printf x 49 #else 50 #define DPRINTF(x) 51 #endif 52 53 #define PIIXPM_IS_CSB5(sc) \ 54 (PCI_VENDOR((sc)->sc_id) == PCI_VENDOR_SERVERWORKS && \ 55 PCI_PRODUCT((sc)->sc_id) == PCI_PRODUCT_SERVERWORKS_CSB5) 56 #define PIIXPM_DELAY 200 57 #define PIIXPM_TIMEOUT 1 58 59 #define PIIXPM_IS_SB800GRP(sc) \ 60 ((PCI_VENDOR((sc)->sc_id) == PCI_VENDOR_ATI) && \ 61 ((PCI_PRODUCT((sc)->sc_id) == PCI_PRODUCT_ATI_SB600_SMB) && \ 62 ((sc)->sc_rev >= 0x40))) 63 64 #define PIIXPM_IS_HUDSON(sc) \ 65 ((PCI_VENDOR((sc)->sc_id) == PCI_VENDOR_AMD) && \ 66 (PCI_PRODUCT((sc)->sc_id) == PCI_PRODUCT_AMD_HUDSON_SMB)) 67 68 #define PIIXPM_IS_KERNCZ(sc) \ 69 ((PCI_VENDOR((sc)->sc_id) == PCI_VENDOR_AMD) && \ 70 (PCI_PRODUCT((sc)->sc_id) == PCI_PRODUCT_AMD_KERNCZ_SMB)) 71 72 #define PIIXPM_IS_FCHGRP(sc) (PIIXPM_IS_HUDSON(sc) || PIIXPM_IS_KERNCZ(sc)) 73 74 #define PIIX_SB800_TIMEOUT 500 75 76 struct piixpm_smbus { 77 int sda; 78 int sda_save; 79 struct piixpm_softc *softc; 80 }; 81 82 struct piixpm_softc { 83 device_t sc_dev; 84 85 bus_space_tag_t sc_iot; 86 #define sc_pm_iot sc_iot 87 #define sc_smb_iot sc_iot 88 bus_space_handle_t sc_pm_ioh; 89 bus_space_handle_t sc_sb800_ioh; 90 bus_space_handle_t sc_smb_ioh; 91 void * sc_smb_ih; 92 int sc_poll; 93 bool sc_sb800_selen; /* Use SMBUS0SEL */ 94 95 pci_chipset_tag_t sc_pc; 96 pcitag_t sc_pcitag; 97 pcireg_t sc_id; 98 pcireg_t sc_rev; 99 100 int sc_numbusses; 101 device_t sc_i2c_device[4]; 102 struct piixpm_smbus sc_busses[4]; 103 struct i2c_controller sc_i2c_tags[4]; 104 105 kmutex_t sc_exec_lock; 106 kcondvar_t sc_exec_wait; 107 108 struct { 109 i2c_op_t op; 110 void * buf; 111 size_t len; 112 int flags; 113 int error; 114 bool done; 115 } sc_i2c_xfer; 116 117 pcireg_t sc_devact[2]; 118 }; 119 120 static int piixpm_match(device_t, cfdata_t, void *); 121 static void piixpm_attach(device_t, device_t, void *); 122 static int piixpm_rescan(device_t, const char *, const int *); 123 static void piixpm_chdet(device_t, device_t); 124 125 static bool piixpm_suspend(device_t, const pmf_qual_t *); 126 static bool piixpm_resume(device_t, const pmf_qual_t *); 127 128 static int piixpm_sb800_init(struct piixpm_softc *); 129 static void piixpm_csb5_reset(void *); 130 static int piixpm_i2c_sb800_acquire_bus(void *, int); 131 static void piixpm_i2c_sb800_release_bus(void *, int); 132 static int piixpm_i2c_exec(void *, i2c_op_t, i2c_addr_t, const void *, 133 size_t, void *, size_t, int); 134 135 static int piixpm_intr(void *); 136 137 CFATTACH_DECL3_NEW(piixpm, sizeof(struct piixpm_softc), 138 piixpm_match, piixpm_attach, NULL, NULL, piixpm_rescan, piixpm_chdet, 0); 139 140 static int 141 piixpm_match(device_t parent, cfdata_t match, void *aux) 142 { 143 struct pci_attach_args *pa; 144 145 pa = (struct pci_attach_args *)aux; 146 switch (PCI_VENDOR(pa->pa_id)) { 147 case PCI_VENDOR_INTEL: 148 switch (PCI_PRODUCT(pa->pa_id)) { 149 case PCI_PRODUCT_INTEL_82371AB_PMC: 150 case PCI_PRODUCT_INTEL_82440MX_PMC: 151 return 1; 152 } 153 break; 154 case PCI_VENDOR_ATI: 155 switch (PCI_PRODUCT(pa->pa_id)) { 156 case PCI_PRODUCT_ATI_SB200_SMB: 157 case PCI_PRODUCT_ATI_SB300_SMB: 158 case PCI_PRODUCT_ATI_SB400_SMB: 159 case PCI_PRODUCT_ATI_SB600_SMB: /* matches SB600/SB700/SB800 */ 160 return 1; 161 } 162 break; 163 case PCI_VENDOR_SERVERWORKS: 164 switch (PCI_PRODUCT(pa->pa_id)) { 165 case PCI_PRODUCT_SERVERWORKS_OSB4: 166 case PCI_PRODUCT_SERVERWORKS_CSB5: 167 case PCI_PRODUCT_SERVERWORKS_CSB6: 168 case PCI_PRODUCT_SERVERWORKS_HT1000SB: 169 case PCI_PRODUCT_SERVERWORKS_HT1100SB: 170 return 1; 171 } 172 break; 173 case PCI_VENDOR_AMD: 174 switch (PCI_PRODUCT(pa->pa_id)) { 175 case PCI_PRODUCT_AMD_HUDSON_SMB: 176 case PCI_PRODUCT_AMD_KERNCZ_SMB: 177 return 1; 178 } 179 break; 180 } 181 182 return 0; 183 } 184 185 static void 186 piixpm_attach(device_t parent, device_t self, void *aux) 187 { 188 struct piixpm_softc *sc = device_private(self); 189 struct pci_attach_args *pa = aux; 190 pcireg_t base, conf; 191 pcireg_t pmmisc; 192 pci_intr_handle_t ih; 193 bool usesmi = false; 194 const char *intrstr = NULL; 195 int i; 196 char intrbuf[PCI_INTRSTR_LEN]; 197 198 sc->sc_dev = self; 199 sc->sc_iot = pa->pa_iot; 200 sc->sc_id = pa->pa_id; 201 sc->sc_rev = PCI_REVISION(pa->pa_class); 202 sc->sc_pc = pa->pa_pc; 203 sc->sc_pcitag = pa->pa_tag; 204 sc->sc_numbusses = 1; 205 206 pci_aprint_devinfo(pa, NULL); 207 208 mutex_init(&sc->sc_exec_lock, MUTEX_DEFAULT, IPL_BIO); 209 cv_init(&sc->sc_exec_wait, device_xname(self)); 210 211 if (!pmf_device_register(self, piixpm_suspend, piixpm_resume)) 212 aprint_error_dev(self, "couldn't establish power handler\n"); 213 214 if ((PCI_VENDOR(pa->pa_id) != PCI_VENDOR_INTEL) || 215 (PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_INTEL_82371AB_PMC)) 216 goto nopowermanagement; 217 218 /* check whether I/O access to PM regs is enabled */ 219 pmmisc = pci_conf_read(pa->pa_pc, pa->pa_tag, PIIX_PMREGMISC); 220 if (!(pmmisc & 1)) 221 goto nopowermanagement; 222 223 /* Map I/O space */ 224 base = pci_conf_read(pa->pa_pc, pa->pa_tag, PIIX_PM_BASE); 225 if (base == 0 || bus_space_map(sc->sc_pm_iot, PCI_MAPREG_IO_ADDR(base), 226 PIIX_PM_SIZE, 0, &sc->sc_pm_ioh)) { 227 aprint_error_dev(self, 228 "can't map power management I/O space\n"); 229 goto nopowermanagement; 230 } 231 232 /* 233 * Revision 0 and 1 are PIIX4, 2 is PIIX4E, 3 is PIIX4M. 234 * PIIX4 and PIIX4E have a bug in the timer latch, see Errata #20 235 * in the "Specification update" (document #297738). 236 */ 237 acpipmtimer_attach(self, sc->sc_pm_iot, sc->sc_pm_ioh, PIIX_PM_PMTMR, 238 (PCI_REVISION(pa->pa_class) < 3) ? ACPIPMT_BADLATCH : 0); 239 240 nopowermanagement: 241 242 /* SB800 rev 0x40+, AMD HUDSON and newer need special initialization */ 243 if (PIIXPM_IS_FCHGRP(sc) || PIIXPM_IS_SB800GRP(sc)) { 244 if (piixpm_sb800_init(sc) == 0) { 245 /* Read configuration */ 246 conf = bus_space_read_1(sc->sc_iot, 247 sc->sc_smb_ioh, SB800_SMB_HOSTC); 248 usesmi = ((conf & SB800_SMB_HOSTC_IRQ) == 0); 249 goto setintr; 250 } 251 aprint_normal_dev(self, "SMBus initialization failed\n"); 252 return; 253 } 254 255 /* Read configuration */ 256 conf = pci_conf_read(pa->pa_pc, pa->pa_tag, PIIX_SMB_HOSTC); 257 DPRINTF(("%s: conf 0x%08x\n", device_xname(self), conf)); 258 259 if ((conf & PIIX_SMB_HOSTC_HSTEN) == 0) { 260 aprint_normal_dev(self, "SMBus disabled\n"); 261 return; 262 } 263 usesmi = (conf & PIIX_SMB_HOSTC_INTMASK) == PIIX_SMB_HOSTC_SMI; 264 265 /* Map I/O space */ 266 base = pci_conf_read(pa->pa_pc, pa->pa_tag, PIIX_SMB_BASE) & 0xffff; 267 if (base == 0 || 268 bus_space_map(sc->sc_smb_iot, PCI_MAPREG_IO_ADDR(base), 269 PIIX_SMB_SIZE, 0, &sc->sc_smb_ioh)) { 270 aprint_error_dev(self, "can't map smbus I/O space\n"); 271 return; 272 } 273 274 setintr: 275 sc->sc_poll = 1; 276 aprint_normal_dev(self, ""); 277 if (usesmi) { 278 /* No PCI IRQ */ 279 aprint_normal("interrupting at SMI, "); 280 } else { 281 if ((conf & PIIX_SMB_HOSTC_INTMASK) == PIIX_SMB_HOSTC_IRQ) { 282 /* Install interrupt handler */ 283 if (pci_intr_map(pa, &ih) == 0) { 284 intrstr = pci_intr_string(pa->pa_pc, ih, 285 intrbuf, sizeof(intrbuf)); 286 pci_intr_setattr(pa->pa_pc, &ih, 287 PCI_INTR_MPSAFE, true); 288 sc->sc_smb_ih = pci_intr_establish_xname( 289 pa->pa_pc, ih, IPL_BIO, piixpm_intr, 290 sc, device_xname(sc->sc_dev)); 291 if (sc->sc_smb_ih != NULL) { 292 aprint_normal("interrupting at %s", 293 intrstr); 294 sc->sc_poll = 0; 295 } 296 } 297 } 298 if (sc->sc_poll) 299 aprint_normal("polling"); 300 } 301 302 aprint_normal("\n"); 303 304 for (i = 0; i < sc->sc_numbusses; i++) 305 sc->sc_i2c_device[i] = NULL; 306 307 piixpm_rescan(self, NULL, NULL); 308 } 309 310 static int 311 piixpm_iicbus_print(void *aux, const char *pnp) 312 { 313 struct i2cbus_attach_args *iba = aux; 314 struct i2c_controller *tag = iba->iba_tag; 315 struct piixpm_smbus *bus = tag->ic_cookie; 316 struct piixpm_softc *sc = bus->softc; 317 318 iicbus_print(aux, pnp); 319 if (sc->sc_numbusses != 0) 320 aprint_normal(" port %d", bus->sda); 321 322 return UNCONF; 323 } 324 325 static int 326 piixpm_rescan(device_t self, const char *ifattr, const int *locators) 327 { 328 struct piixpm_softc *sc = device_private(self); 329 struct i2cbus_attach_args iba; 330 int i; 331 332 /* Attach I2C bus */ 333 334 for (i = 0; i < sc->sc_numbusses; i++) { 335 struct i2c_controller *tag = &sc->sc_i2c_tags[i]; 336 337 if (sc->sc_i2c_device[i] != NULL) 338 continue; 339 sc->sc_busses[i].sda = i; 340 sc->sc_busses[i].softc = sc; 341 iic_tag_init(tag); 342 tag->ic_cookie = &sc->sc_busses[i]; 343 if (PIIXPM_IS_SB800GRP(sc) || PIIXPM_IS_FCHGRP(sc)) { 344 tag->ic_acquire_bus = piixpm_i2c_sb800_acquire_bus; 345 tag->ic_release_bus = piixpm_i2c_sb800_release_bus; 346 } else { 347 tag->ic_acquire_bus = NULL; 348 tag->ic_release_bus = NULL; 349 } 350 tag->ic_exec = piixpm_i2c_exec; 351 memset(&iba, 0, sizeof(iba)); 352 iba.iba_tag = tag; 353 sc->sc_i2c_device[i] = 354 config_found(self, &iba, piixpm_iicbus_print, CFARGS_NONE); 355 } 356 357 return 0; 358 } 359 360 static void 361 piixpm_chdet(device_t self, device_t child) 362 { 363 struct piixpm_softc *sc = device_private(self); 364 int i; 365 366 for (i = 0; i < sc->sc_numbusses; i++) { 367 if (sc->sc_i2c_device[i] == child) { 368 sc->sc_i2c_device[i] = NULL; 369 break; 370 } 371 } 372 } 373 374 375 static bool 376 piixpm_suspend(device_t dv, const pmf_qual_t *qual) 377 { 378 struct piixpm_softc *sc = device_private(dv); 379 380 sc->sc_devact[0] = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 381 PIIX_DEVACTA); 382 sc->sc_devact[1] = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 383 PIIX_DEVACTB); 384 385 return true; 386 } 387 388 static bool 389 piixpm_resume(device_t dv, const pmf_qual_t *qual) 390 { 391 struct piixpm_softc *sc = device_private(dv); 392 393 pci_conf_write(sc->sc_pc, sc->sc_pcitag, PIIX_DEVACTA, 394 sc->sc_devact[0]); 395 pci_conf_write(sc->sc_pc, sc->sc_pcitag, PIIX_DEVACTB, 396 sc->sc_devact[1]); 397 398 return true; 399 } 400 401 /* 402 * Extract SMBus base address from SB800 Power Management (PM) registers. 403 * The PM registers can be accessed either through indirect I/O (CD6/CD7) or 404 * direct mapping if AcpiMMioDecodeEn is enabled. Since this function is only 405 * called once it uses indirect I/O for simplicity. 406 */ 407 static int 408 piixpm_sb800_init(struct piixpm_softc *sc) 409 { 410 bus_space_tag_t iot = sc->sc_iot; 411 bus_space_handle_t ioh; /* indirect I/O handle */ 412 uint16_t val, base_addr; 413 bool enabled; 414 415 if (PIIXPM_IS_KERNCZ(sc) || 416 (PIIXPM_IS_HUDSON(sc) && (sc->sc_rev >= 0x1f))) 417 sc->sc_numbusses = 2; 418 else 419 sc->sc_numbusses = 4; 420 421 /* Fetch SMB base address */ 422 if (bus_space_map(iot, 423 SB800_INDIRECTIO_BASE, SB800_INDIRECTIO_SIZE, 0, &ioh)) { 424 device_printf(sc->sc_dev, "couldn't map indirect I/O space\n"); 425 return EBUSY; 426 } 427 if (PIIXPM_IS_FCHGRP(sc)) { 428 bus_space_write_1(iot, ioh, SB800_INDIRECTIO_INDEX, 429 AMDFCH41_PM_DECODE_EN0); 430 val = bus_space_read_1(iot, ioh, SB800_INDIRECTIO_DATA); 431 enabled = val & AMDFCH41_SMBUS_EN; 432 if (!enabled) 433 return ENOENT; 434 435 bus_space_write_1(iot, ioh, SB800_INDIRECTIO_INDEX, 436 AMDFCH41_PM_DECODE_EN1); 437 val = bus_space_read_1(iot, ioh, SB800_INDIRECTIO_DATA) << 8; 438 base_addr = val; 439 } else { 440 uint8_t data; 441 442 bus_space_write_1(iot, ioh, SB800_INDIRECTIO_INDEX, 443 SB800_PM_SMBUS0EN_LO); 444 val = bus_space_read_1(iot, ioh, SB800_INDIRECTIO_DATA); 445 enabled = val & SB800_PM_SMBUS0EN_ENABLE; 446 if (!enabled) 447 return ENOENT; 448 449 bus_space_write_1(iot, ioh, SB800_INDIRECTIO_INDEX, 450 SB800_PM_SMBUS0EN_HI); 451 val |= bus_space_read_1(iot, ioh, SB800_INDIRECTIO_DATA) << 8; 452 base_addr = val & SB800_PM_SMBUS0EN_BADDR; 453 454 bus_space_write_1(iot, ioh, SB800_INDIRECTIO_INDEX, 455 SB800_PM_SMBUS0SELEN); 456 data = bus_space_read_1(iot, ioh, SB800_INDIRECTIO_DATA); 457 if ((data & SB800_PM_USE_SMBUS0SEL) != 0) 458 sc->sc_sb800_selen = true; 459 } 460 461 sc->sc_sb800_ioh = ioh; 462 aprint_debug_dev(sc->sc_dev, "SMBus @ 0x%04x\n", base_addr); 463 464 if (bus_space_map(iot, PCI_MAPREG_IO_ADDR(base_addr), 465 SB800_SMB_SIZE, 0, &sc->sc_smb_ioh)) { 466 aprint_error_dev(sc->sc_dev, "can't map smbus I/O space\n"); 467 return EBUSY; 468 } 469 470 return 0; 471 } 472 473 static void 474 piixpm_csb5_reset(void *arg) 475 { 476 struct piixpm_softc *sc = arg; 477 pcireg_t base, hostc, pmbase; 478 479 base = pci_conf_read(sc->sc_pc, sc->sc_pcitag, PIIX_SMB_BASE); 480 hostc = pci_conf_read(sc->sc_pc, sc->sc_pcitag, PIIX_SMB_HOSTC); 481 482 pmbase = pci_conf_read(sc->sc_pc, sc->sc_pcitag, PIIX_PM_BASE); 483 pmbase |= PIIX_PM_BASE_CSB5_RESET; 484 pci_conf_write(sc->sc_pc, sc->sc_pcitag, PIIX_PM_BASE, pmbase); 485 pmbase &= ~PIIX_PM_BASE_CSB5_RESET; 486 pci_conf_write(sc->sc_pc, sc->sc_pcitag, PIIX_PM_BASE, pmbase); 487 488 pci_conf_write(sc->sc_pc, sc->sc_pcitag, PIIX_SMB_BASE, base); 489 pci_conf_write(sc->sc_pc, sc->sc_pcitag, PIIX_SMB_HOSTC, hostc); 490 491 (void) tsleep(&sc, PRIBIO, "csb5reset", hz/2); 492 } 493 494 static int 495 piixpm_i2c_sb800_acquire_bus(void *cookie, int flags) 496 { 497 struct piixpm_smbus *smbus = cookie; 498 struct piixpm_softc *sc = smbus->softc; 499 uint8_t sctl, old_sda, index, mask, reg; 500 int i; 501 502 sctl = bus_space_read_1(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_SC); 503 for (i = 0; i < PIIX_SB800_TIMEOUT; i++) { 504 /* Try to acquire the host semaphore */ 505 sctl &= ~PIIX_SMB_SC_SEMMASK; 506 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_SC, 507 sctl | PIIX_SMB_SC_HOSTSEM); 508 509 sctl = bus_space_read_1(sc->sc_smb_iot, sc->sc_smb_ioh, 510 PIIX_SMB_SC); 511 if ((sctl & PIIX_SMB_SC_HOSTSEM) != 0) 512 break; 513 514 delay(1000); 515 } 516 if (i >= PIIX_SB800_TIMEOUT) { 517 device_printf(sc->sc_dev, 518 "Failed to acquire the host semaphore\n"); 519 return -1; 520 } 521 522 if (PIIXPM_IS_KERNCZ(sc) || 523 (PIIXPM_IS_HUDSON(sc) && (sc->sc_rev >= 0x1f))) { 524 index = AMDFCH41_PM_PORT_INDEX; 525 mask = AMDFCH41_SMBUS_PORTMASK; 526 } else if (sc->sc_sb800_selen) { 527 index = SB800_PM_SMBUS0SEL; 528 mask = SB800_PM_SMBUS0_MASK_E; 529 } else { 530 index = SB800_PM_SMBUS0EN_LO; 531 mask = SB800_PM_SMBUS0_MASK_C; 532 } 533 534 bus_space_write_1(sc->sc_iot, sc->sc_sb800_ioh, 535 SB800_INDIRECTIO_INDEX, index); 536 reg = bus_space_read_1(sc->sc_iot, sc->sc_sb800_ioh, 537 SB800_INDIRECTIO_DATA); 538 539 old_sda = __SHIFTOUT(reg, mask); 540 if (smbus->sda != old_sda) { 541 reg &= ~mask; 542 reg |= __SHIFTIN(smbus->sda, mask); 543 bus_space_write_1(sc->sc_iot, sc->sc_sb800_ioh, 544 SB800_INDIRECTIO_DATA, reg); 545 } 546 547 /* Save the old port number */ 548 smbus->sda_save = old_sda; 549 550 return 0; 551 } 552 553 static void 554 piixpm_i2c_sb800_release_bus(void *cookie, int flags) 555 { 556 struct piixpm_smbus *smbus = cookie; 557 struct piixpm_softc *sc = smbus->softc; 558 uint8_t sctl, index, mask, reg; 559 560 if (PIIXPM_IS_KERNCZ(sc) || 561 (PIIXPM_IS_HUDSON(sc) && (sc->sc_rev >= 0x1f))) { 562 index = AMDFCH41_PM_PORT_INDEX; 563 mask = AMDFCH41_SMBUS_PORTMASK; 564 } else if (sc->sc_sb800_selen) { 565 index = SB800_PM_SMBUS0SEL; 566 mask = SB800_PM_SMBUS0_MASK_E; 567 } else { 568 index = SB800_PM_SMBUS0EN_LO; 569 mask = SB800_PM_SMBUS0_MASK_C; 570 } 571 572 bus_space_write_1(sc->sc_iot, sc->sc_sb800_ioh, 573 SB800_INDIRECTIO_INDEX, index); 574 if (smbus->sda != smbus->sda_save) { 575 /* Restore the port number */ 576 reg = bus_space_read_1(sc->sc_iot, sc->sc_sb800_ioh, 577 SB800_INDIRECTIO_DATA); 578 reg &= ~mask; 579 reg |= __SHIFTIN(smbus->sda_save, mask); 580 bus_space_write_1(sc->sc_iot, sc->sc_sb800_ioh, 581 SB800_INDIRECTIO_DATA, reg); 582 } 583 584 /* Relase the host semaphore */ 585 sctl = bus_space_read_1(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_SC); 586 sctl &= ~PIIX_SMB_SC_SEMMASK; 587 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_SC, 588 sctl | PIIX_SMB_SC_CLRHOSTSEM); 589 } 590 591 static int 592 piixpm_i2c_exec(void *cookie, i2c_op_t op, i2c_addr_t addr, 593 const void *cmdbuf, size_t cmdlen, void *buf, size_t len, int flags) 594 { 595 struct piixpm_smbus *smbus = cookie; 596 struct piixpm_softc *sc = smbus->softc; 597 const uint8_t *b; 598 uint8_t ctl = 0, st; 599 int retries; 600 601 DPRINTF(("%s: exec: op %d, addr 0x%02x, cmdlen %zu, len %zu, " 602 "flags 0x%x\n", 603 device_xname(sc->sc_dev), op, addr, cmdlen, len, flags)); 604 605 mutex_enter(&sc->sc_exec_lock); 606 607 /* Clear status bits */ 608 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_HS, 609 PIIX_SMB_HS_INTR | PIIX_SMB_HS_DEVERR | 610 PIIX_SMB_HS_BUSERR | PIIX_SMB_HS_FAILED); 611 bus_space_barrier(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_HS, 1, 612 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 613 614 /* Wait for bus to be idle */ 615 for (retries = 100; retries > 0; retries--) { 616 st = bus_space_read_1(sc->sc_smb_iot, sc->sc_smb_ioh, 617 PIIX_SMB_HS); 618 if (!(st & PIIX_SMB_HS_BUSY)) 619 break; 620 DELAY(PIIXPM_DELAY); 621 } 622 DPRINTF(("%s: exec: st %#x\n", device_xname(sc->sc_dev), st & 0xff)); 623 if (st & PIIX_SMB_HS_BUSY) { 624 mutex_exit(&sc->sc_exec_lock); 625 return (EBUSY); 626 } 627 628 if (sc->sc_poll) 629 flags |= I2C_F_POLL; 630 631 if (!I2C_OP_STOP_P(op) || cmdlen > 1 || len > 2 || 632 (cmdlen == 0 && len > 1)) { 633 mutex_exit(&sc->sc_exec_lock); 634 return (EINVAL); 635 } 636 637 /* Setup transfer */ 638 sc->sc_i2c_xfer.op = op; 639 sc->sc_i2c_xfer.buf = buf; 640 sc->sc_i2c_xfer.len = len; 641 sc->sc_i2c_xfer.flags = flags; 642 sc->sc_i2c_xfer.error = 0; 643 sc->sc_i2c_xfer.done = false; 644 645 /* Set slave address and transfer direction */ 646 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_TXSLVA, 647 PIIX_SMB_TXSLVA_ADDR(addr) | 648 (I2C_OP_READ_P(op) ? PIIX_SMB_TXSLVA_READ : 0)); 649 650 b = cmdbuf; 651 if (cmdlen > 0) 652 /* Set command byte */ 653 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, 654 PIIX_SMB_HCMD, b[0]); 655 656 if (I2C_OP_WRITE_P(op)) { 657 /* Write data */ 658 b = buf; 659 if (cmdlen == 0 && len == 1) 660 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, 661 PIIX_SMB_HCMD, b[0]); 662 else if (len > 0) 663 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, 664 PIIX_SMB_HD0, b[0]); 665 if (len > 1) 666 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, 667 PIIX_SMB_HD1, b[1]); 668 } 669 670 /* Set SMBus command */ 671 if (cmdlen == 0) { 672 if (len == 0) 673 ctl = PIIX_SMB_HC_CMD_QUICK; 674 else 675 ctl = PIIX_SMB_HC_CMD_BYTE; 676 } else if (len == 1) 677 ctl = PIIX_SMB_HC_CMD_BDATA; 678 else if (len == 2) 679 ctl = PIIX_SMB_HC_CMD_WDATA; 680 else 681 panic("%s: unexpected len %zu", __func__, len); 682 683 if ((flags & I2C_F_POLL) == 0) 684 ctl |= PIIX_SMB_HC_INTREN; 685 686 /* Start transaction */ 687 ctl |= PIIX_SMB_HC_START; 688 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_HC, ctl); 689 690 if (flags & I2C_F_POLL) { 691 /* Poll for completion */ 692 if (PIIXPM_IS_CSB5(sc)) 693 DELAY(2*PIIXPM_DELAY); 694 else 695 DELAY(PIIXPM_DELAY); 696 for (retries = 1000; retries > 0; retries--) { 697 st = bus_space_read_1(sc->sc_smb_iot, sc->sc_smb_ioh, 698 PIIX_SMB_HS); 699 if ((st & PIIX_SMB_HS_BUSY) == 0) 700 break; 701 DELAY(PIIXPM_DELAY); 702 } 703 if (st & PIIX_SMB_HS_BUSY) 704 goto timeout; 705 piixpm_intr(sc); 706 } else { 707 /* Wait for interrupt */ 708 while (! sc->sc_i2c_xfer.done) { 709 if (cv_timedwait(&sc->sc_exec_wait, &sc->sc_exec_lock, 710 PIIXPM_TIMEOUT * hz)) 711 goto timeout; 712 } 713 } 714 715 int error = sc->sc_i2c_xfer.error; 716 mutex_exit(&sc->sc_exec_lock); 717 718 return (error); 719 720 timeout: 721 /* 722 * Transfer timeout. Kill the transaction and clear status bits. 723 */ 724 aprint_error_dev(sc->sc_dev, "timeout, status 0x%x\n", st); 725 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_HC, 726 PIIX_SMB_HC_KILL); 727 DELAY(PIIXPM_DELAY); 728 st = bus_space_read_1(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_HS); 729 if ((st & PIIX_SMB_HS_FAILED) == 0) 730 aprint_error_dev(sc->sc_dev, 731 "transaction abort failed, status 0x%x\n", st); 732 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_HS, st); 733 /* 734 * CSB5 needs hard reset to unlock the smbus after timeout. 735 */ 736 if (PIIXPM_IS_CSB5(sc)) 737 piixpm_csb5_reset(sc); 738 mutex_exit(&sc->sc_exec_lock); 739 return (ETIMEDOUT); 740 } 741 742 static int 743 piixpm_intr(void *arg) 744 { 745 struct piixpm_softc *sc = arg; 746 uint8_t st; 747 uint8_t *b; 748 size_t len; 749 750 /* Read status */ 751 st = bus_space_read_1(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_HS); 752 if ((st & PIIX_SMB_HS_BUSY) != 0 || (st & (PIIX_SMB_HS_INTR | 753 PIIX_SMB_HS_DEVERR | PIIX_SMB_HS_BUSERR | 754 PIIX_SMB_HS_FAILED)) == 0) 755 /* Interrupt was not for us */ 756 return (0); 757 758 DPRINTF(("%s: intr st %#x\n", device_xname(sc->sc_dev), st & 0xff)); 759 760 if ((sc->sc_i2c_xfer.flags & I2C_F_POLL) == 0) 761 mutex_enter(&sc->sc_exec_lock); 762 763 /* Clear status bits */ 764 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_HS, st); 765 766 /* Check for errors */ 767 if (st & (PIIX_SMB_HS_DEVERR | PIIX_SMB_HS_BUSERR | 768 PIIX_SMB_HS_FAILED)) { 769 sc->sc_i2c_xfer.error = EIO; 770 goto done; 771 } 772 773 if (st & PIIX_SMB_HS_INTR) { 774 if (I2C_OP_WRITE_P(sc->sc_i2c_xfer.op)) 775 goto done; 776 777 /* Read data */ 778 b = sc->sc_i2c_xfer.buf; 779 len = sc->sc_i2c_xfer.len; 780 if (len > 0) 781 b[0] = bus_space_read_1(sc->sc_smb_iot, sc->sc_smb_ioh, 782 PIIX_SMB_HD0); 783 if (len > 1) 784 b[1] = bus_space_read_1(sc->sc_smb_iot, sc->sc_smb_ioh, 785 PIIX_SMB_HD1); 786 } 787 788 done: 789 sc->sc_i2c_xfer.done = true; 790 if ((sc->sc_i2c_xfer.flags & I2C_F_POLL) == 0) { 791 cv_signal(&sc->sc_exec_wait); 792 mutex_exit(&sc->sc_exec_lock); 793 } 794 return (1); 795 } 796
Indexes created Sun Sep 28 12:09:53 GMT 2025