piixpm.c revision 1.9
1 /* $NetBSD: piixpm.c,v 1.9 2006/10/12 01:31:33 christos Exp $ */ 2 /* $OpenBSD: piixpm.c,v 1.20 2006/02/27 08:25:02 grange Exp $ */ 3 4 /* 5 * Copyright (c) 2005, 2006 Alexander Yurchenko <grange (at) openbsd.org> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 /* 21 * Intel PIIX and compatible Power Management controller driver. 22 */ 23 24 #include <sys/param.h> 25 #include <sys/systm.h> 26 #include <sys/device.h> 27 #include <sys/kernel.h> 28 #include <sys/lock.h> 29 #include <sys/proc.h> 30 31 #include <machine/bus.h> 32 33 #include <dev/pci/pcidevs.h> 34 #include <dev/pci/pcireg.h> 35 #include <dev/pci/pcivar.h> 36 37 #include <dev/pci/piixpmreg.h> 38 39 #include <dev/i2c/i2cvar.h> 40 41 #ifdef __HAVE_TIMECOUNTER 42 #include <dev/ic/acpipmtimer.h> 43 #endif 44 45 #ifdef PIIXPM_DEBUG 46 #define DPRINTF(x) printf x 47 #else 48 #define DPRINTF(x) 49 #endif 50 51 #define PIIXPM_DELAY 200 52 #define PIIXPM_TIMEOUT 1 53 54 struct piixpm_softc { 55 struct device sc_dev; 56 57 bus_space_tag_t sc_smb_iot; 58 bus_space_handle_t sc_smb_ioh; 59 void * sc_smb_ih; 60 int sc_poll; 61 62 bus_space_tag_t sc_pm_iot; 63 bus_space_handle_t sc_pm_ioh; 64 65 pci_chipset_tag_t sc_pc; 66 pcitag_t sc_pcitag; 67 68 struct i2c_controller sc_i2c_tag; 69 struct lock sc_i2c_lock; 70 struct { 71 i2c_op_t op; 72 void * buf; 73 size_t len; 74 int flags; 75 volatile int error; 76 } sc_i2c_xfer; 77 78 void * sc_powerhook; 79 struct pci_conf_state sc_pciconf; 80 pcireg_t sc_devact[2]; 81 }; 82 83 int piixpm_match(struct device *, struct cfdata *, void *); 84 void piixpm_attach(struct device *, struct device *, void *); 85 86 void piixpm_powerhook(int, void *); 87 88 int piixpm_i2c_acquire_bus(void *, int); 89 void piixpm_i2c_release_bus(void *, int); 90 int piixpm_i2c_exec(void *, i2c_op_t, i2c_addr_t, const void *, size_t, 91 void *, size_t, int); 92 93 int piixpm_intr(void *); 94 95 CFATTACH_DECL(piixpm, sizeof(struct piixpm_softc), 96 piixpm_match, piixpm_attach, NULL, NULL); 97 98 int 99 piixpm_match(struct device *parent __unused, struct cfdata *match __unused, 100 void *aux) 101 { 102 struct pci_attach_args *pa; 103 104 pa = (struct pci_attach_args *)aux; 105 switch (PCI_VENDOR(pa->pa_id)) { 106 case PCI_VENDOR_INTEL: 107 switch (PCI_PRODUCT(pa->pa_id)) { 108 case PCI_PRODUCT_INTEL_82371AB_PMC: 109 case PCI_PRODUCT_INTEL_82440MX_PMC: 110 return 1; 111 } 112 break; 113 case PCI_VENDOR_ATI: 114 switch (PCI_PRODUCT(pa->pa_id)) { 115 case PCI_PRODUCT_ATI_SB200_SMB: 116 return 1; 117 } 118 break; 119 } 120 121 return 0; 122 } 123 124 void 125 piixpm_attach(struct device *parent __unused, struct device *self, void *aux) 126 { 127 struct piixpm_softc *sc = (struct piixpm_softc *)self; 128 struct pci_attach_args *pa = aux; 129 struct i2cbus_attach_args iba; 130 pcireg_t base, conf; 131 #ifdef __HAVE_TIMECOUNTER 132 pcireg_t pmmisc; 133 #endif 134 pci_intr_handle_t ih; 135 const char *intrstr = NULL; 136 137 sc->sc_pc = pa->pa_pc; 138 sc->sc_pcitag = pa->pa_tag; 139 140 aprint_naive("\n"); 141 aprint_normal(": Power Management Controller\n"); 142 143 sc->sc_powerhook = powerhook_establish(sc->sc_dev.dv_xname, 144 piixpm_powerhook, sc); 145 if (sc->sc_powerhook == NULL) 146 aprint_error("%s: can't establish powerhook\n", 147 sc->sc_dev.dv_xname); 148 149 /* Read configuration */ 150 conf = pci_conf_read(pa->pa_pc, pa->pa_tag, PIIX_SMB_HOSTC); 151 DPRINTF((": conf 0x%x", conf)); 152 153 #ifdef __HAVE_TIMECOUNTER 154 if ((PCI_VENDOR(pa->pa_id) != PCI_VENDOR_INTEL) || 155 (PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_INTEL_82371AB_PMC)) 156 goto nopowermanagement; 157 158 /* check whether I/O access to PM regs is enabled */ 159 pmmisc = pci_conf_read(pa->pa_pc, pa->pa_tag, PIIX_PMREGMISC); 160 if (!(pmmisc & 1)) 161 goto nopowermanagement; 162 163 sc->sc_pm_iot = pa->pa_iot; 164 /* Map I/O space */ 165 base = pci_conf_read(pa->pa_pc, pa->pa_tag, PIIX_PM_BASE); 166 if (bus_space_map(sc->sc_pm_iot, PCI_MAPREG_IO_ADDR(base), 167 PIIX_PM_SIZE, 0, &sc->sc_pm_ioh)) { 168 aprint_error("%s: can't map power management I/O space\n", 169 sc->sc_dev.dv_xname); 170 goto nopowermanagement; 171 } 172 173 /* 174 * Revision 0 and 1 are PIIX4, 2 is PIIX4E, 3 is PIIX4M. 175 * PIIX4 and PIIX4E have a bug in the timer latch, see Errata #20 176 * in the "Specification update" (document #297738). 177 */ 178 acpipmtimer_attach(&sc->sc_dev, sc->sc_pm_iot, sc->sc_pm_ioh, 179 PIIX_PM_PMTMR, 180 (PCI_REVISION(pa->pa_class) < 3) ? ACPIPMT_BADLATCH : 0 ); 181 182 nopowermanagement: 183 #endif 184 185 if ((conf & PIIX_SMB_HOSTC_HSTEN) == 0) { 186 aprint_normal("%s: SMBus disabled\n", sc->sc_dev.dv_xname); 187 return; 188 } 189 190 /* Map I/O space */ 191 sc->sc_smb_iot = pa->pa_iot; 192 base = pci_conf_read(pa->pa_pc, pa->pa_tag, PIIX_SMB_BASE) & 0xffff; 193 if (bus_space_map(sc->sc_smb_iot, PCI_MAPREG_IO_ADDR(base), 194 PIIX_SMB_SIZE, 0, &sc->sc_smb_ioh)) { 195 aprint_error("%s: can't map smbus I/O space\n", 196 sc->sc_dev.dv_xname); 197 return; 198 } 199 200 sc->sc_poll = 1; 201 if ((conf & PIIX_SMB_HOSTC_INTMASK) == PIIX_SMB_HOSTC_SMI) { 202 /* No PCI IRQ */ 203 aprint_normal("%s: interrupting at SMI", sc->sc_dev.dv_xname); 204 } else if ((conf & PIIX_SMB_HOSTC_INTMASK) == PIIX_SMB_HOSTC_IRQ) { 205 /* Install interrupt handler */ 206 if (pci_intr_map(pa, &ih) == 0) { 207 intrstr = pci_intr_string(pa->pa_pc, ih); 208 sc->sc_smb_ih = pci_intr_establish(pa->pa_pc, ih, IPL_BIO, 209 piixpm_intr, sc); 210 if (sc->sc_smb_ih != NULL) { 211 aprint_normal("%s: interrupting at %s", 212 sc->sc_dev.dv_xname, intrstr); 213 sc->sc_poll = 0; 214 } 215 } 216 if (sc->sc_poll) 217 aprint_normal("%s: polling", sc->sc_dev.dv_xname); 218 } 219 220 aprint_normal("\n"); 221 222 /* Attach I2C bus */ 223 lockinit(&sc->sc_i2c_lock, PRIBIO | PCATCH, "iiclk", 0, 0); 224 sc->sc_i2c_tag.ic_cookie = sc; 225 sc->sc_i2c_tag.ic_acquire_bus = piixpm_i2c_acquire_bus; 226 sc->sc_i2c_tag.ic_release_bus = piixpm_i2c_release_bus; 227 sc->sc_i2c_tag.ic_exec = piixpm_i2c_exec; 228 229 bzero(&iba, sizeof(iba)); 230 iba.iba_tag = &sc->sc_i2c_tag; 231 config_found_ia(self, "i2cbus", &iba, iicbus_print); 232 233 return; 234 } 235 236 void 237 piixpm_powerhook(int why, void *cookie) 238 { 239 struct piixpm_softc *sc = cookie; 240 pci_chipset_tag_t pc = sc->sc_pc; 241 pcitag_t tag = sc->sc_pcitag; 242 243 switch (why) { 244 case PWR_SUSPEND: 245 pci_conf_capture(pc, tag, &sc->sc_pciconf); 246 sc->sc_devact[0] = pci_conf_read(pc, tag, PIIX_DEVACTA); 247 sc->sc_devact[1] = pci_conf_read(pc, tag, PIIX_DEVACTB); 248 break; 249 case PWR_RESUME: 250 pci_conf_restore(pc, tag, &sc->sc_pciconf); 251 pci_conf_write(pc, tag, PIIX_DEVACTA, sc->sc_devact[0]); 252 pci_conf_write(pc, tag, PIIX_DEVACTB, sc->sc_devact[1]); 253 break; 254 } 255 256 return; 257 } 258 259 int 260 piixpm_i2c_acquire_bus(void *cookie, int flags) 261 { 262 struct piixpm_softc *sc = cookie; 263 264 if (cold || sc->sc_poll || (flags & I2C_F_POLL)) 265 return (0); 266 267 return (lockmgr(&sc->sc_i2c_lock, LK_EXCLUSIVE, NULL)); 268 } 269 270 void 271 piixpm_i2c_release_bus(void *cookie, int flags) 272 { 273 struct piixpm_softc *sc = cookie; 274 275 if (cold || sc->sc_poll || (flags & I2C_F_POLL)) 276 return; 277 278 lockmgr(&sc->sc_i2c_lock, LK_RELEASE, NULL); 279 } 280 281 int 282 piixpm_i2c_exec(void *cookie, i2c_op_t op, i2c_addr_t addr, 283 const void *cmdbuf, size_t cmdlen, void *buf, size_t len, int flags) 284 { 285 struct piixpm_softc *sc = cookie; 286 const u_int8_t *b; 287 u_int8_t ctl = 0, st; 288 int retries; 289 290 DPRINTF(("%s: exec: op %d, addr 0x%x, cmdlen %d, len %d, flags 0x%x\n", 291 sc->sc_dev.dv_xname, op, addr, cmdlen, len, flags)); 292 293 /* Wait for bus to be idle */ 294 for (retries = 100; retries > 0; retries--) { 295 st = bus_space_read_1(sc->sc_smb_iot, sc->sc_smb_ioh, 296 PIIX_SMB_HS); 297 if (!(st & PIIX_SMB_HS_BUSY)) 298 break; 299 DELAY(PIIXPM_DELAY); 300 } 301 DPRINTF(("%s: exec: st 0x%d\n", sc->sc_dev.dv_xname, st & 0xff)); 302 if (st & PIIX_SMB_HS_BUSY) 303 return (1); 304 305 if (cold || sc->sc_poll) 306 flags |= I2C_F_POLL; 307 308 if (!I2C_OP_STOP_P(op) || cmdlen > 1 || len > 2) 309 return (1); 310 311 /* Setup transfer */ 312 sc->sc_i2c_xfer.op = op; 313 sc->sc_i2c_xfer.buf = buf; 314 sc->sc_i2c_xfer.len = len; 315 sc->sc_i2c_xfer.flags = flags; 316 sc->sc_i2c_xfer.error = 0; 317 318 /* Set slave address and transfer direction */ 319 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_TXSLVA, 320 PIIX_SMB_TXSLVA_ADDR(addr) | 321 (I2C_OP_READ_P(op) ? PIIX_SMB_TXSLVA_READ : 0)); 322 323 b = cmdbuf; 324 if (cmdlen > 0) 325 /* Set command byte */ 326 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, 327 PIIX_SMB_HCMD, b[0]); 328 329 if (I2C_OP_WRITE_P(op)) { 330 /* Write data */ 331 b = buf; 332 if (len > 0) 333 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, 334 PIIX_SMB_HD0, b[0]); 335 if (len > 1) 336 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, 337 PIIX_SMB_HD1, b[1]); 338 } 339 340 /* Set SMBus command */ 341 if (len == 0) 342 ctl = PIIX_SMB_HC_CMD_BYTE; 343 else if (len == 1) 344 ctl = PIIX_SMB_HC_CMD_BDATA; 345 else if (len == 2) 346 ctl = PIIX_SMB_HC_CMD_WDATA; 347 348 if ((flags & I2C_F_POLL) == 0) 349 ctl |= PIIX_SMB_HC_INTREN; 350 351 /* Start transaction */ 352 ctl |= PIIX_SMB_HC_START; 353 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_HC, ctl); 354 355 if (flags & I2C_F_POLL) { 356 /* Poll for completion */ 357 DELAY(PIIXPM_DELAY); 358 for (retries = 1000; retries > 0; retries--) { 359 st = bus_space_read_1(sc->sc_smb_iot, sc->sc_smb_ioh, 360 PIIX_SMB_HS); 361 if ((st & PIIX_SMB_HS_BUSY) == 0) 362 break; 363 DELAY(PIIXPM_DELAY); 364 } 365 if (st & PIIX_SMB_HS_BUSY) 366 goto timeout; 367 piixpm_intr(sc); 368 } else { 369 /* Wait for interrupt */ 370 if (tsleep(sc, PRIBIO, "iicexec", PIIXPM_TIMEOUT * hz)) 371 goto timeout; 372 } 373 374 if (sc->sc_i2c_xfer.error) 375 return (1); 376 377 return (0); 378 379 timeout: 380 /* 381 * Transfer timeout. Kill the transaction and clear status bits. 382 */ 383 aprint_error("%s: timeout, status 0x%x\n", sc->sc_dev.dv_xname, st); 384 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_HC, 385 PIIX_SMB_HC_KILL); 386 DELAY(PIIXPM_DELAY); 387 st = bus_space_read_1(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_HS); 388 if ((st & PIIX_SMB_HS_FAILED) == 0) 389 aprint_error("%s: transaction abort failed, status 0x%x\n", 390 sc->sc_dev.dv_xname, st); 391 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_HS, st); 392 return (1); 393 } 394 395 int 396 piixpm_intr(void *arg) 397 { 398 struct piixpm_softc *sc = arg; 399 u_int8_t st; 400 u_int8_t *b; 401 size_t len; 402 403 /* Read status */ 404 st = bus_space_read_1(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_HS); 405 if ((st & PIIX_SMB_HS_BUSY) != 0 || (st & (PIIX_SMB_HS_INTR | 406 PIIX_SMB_HS_DEVERR | PIIX_SMB_HS_BUSERR | 407 PIIX_SMB_HS_FAILED)) == 0) 408 /* Interrupt was not for us */ 409 return (0); 410 411 DPRINTF(("%s: intr st 0x%d\n", sc->sc_dev.dv_xname, st & 0xff)); 412 413 /* Clear status bits */ 414 bus_space_write_1(sc->sc_smb_iot, sc->sc_smb_ioh, PIIX_SMB_HS, st); 415 416 /* Check for errors */ 417 if (st & (PIIX_SMB_HS_DEVERR | PIIX_SMB_HS_BUSERR | 418 PIIX_SMB_HS_FAILED)) { 419 sc->sc_i2c_xfer.error = 1; 420 goto done; 421 } 422 423 if (st & PIIX_SMB_HS_INTR) { 424 if (I2C_OP_WRITE_P(sc->sc_i2c_xfer.op)) 425 goto done; 426 427 /* Read data */ 428 b = sc->sc_i2c_xfer.buf; 429 len = sc->sc_i2c_xfer.len; 430 if (len > 0) 431 b[0] = bus_space_read_1(sc->sc_smb_iot, sc->sc_smb_ioh, 432 PIIX_SMB_HD0); 433 if (len > 1) 434 b[1] = bus_space_read_1(sc->sc_smb_iot, sc->sc_smb_ioh, 435 PIIX_SMB_HD1); 436 } 437 438 done: 439 if ((sc->sc_i2c_xfer.flags & I2C_F_POLL) == 0) 440 wakeup(sc); 441 return (1); 442 } 443
Indexes created Sun Sep 28 16:09:52 GMT 2025