pm3fb.c revision 1.10
1 /* $NetBSD: pm3fb.c,v 1.10 2024/08/14 12:11:48 macallan Exp $ */ 2 3 /* 4 * Copyright (c) 2015 Naruaki Etomi 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 21 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 22 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 23 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 25 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 /* 29 * A console driver for Permedia 3 graphics controllers 30 * most of the following was adapted from the xf86-video-glint driver's 31 * pm3_accel.c, pm3_dac.c and pm2fb framebuffer console driver 32 */ 33 34 #include <sys/cdefs.h> 35 __KERNEL_RCSID(0, "$NetBSD: pm3fb.c,v 1.10 2024/08/14 12:11:48 macallan Exp $"); 36 37 #include <sys/param.h> 38 #include <sys/systm.h> 39 #include <sys/kernel.h> 40 #include <sys/device.h> 41 #include <sys/lwp.h> 42 #include <sys/kauth.h> 43 #include <sys/atomic.h> 44 45 #include <dev/videomode/videomode.h> 46 47 #include <dev/pci/pcivar.h> 48 #include <dev/pci/pcireg.h> 49 #include <dev/pci/pcidevs.h> 50 #include <dev/pci/pciio.h> 51 #include <dev/pci/pm3reg.h> 52 53 #include <dev/wscons/wsdisplayvar.h> 54 #include <dev/wscons/wsconsio.h> 55 #include <dev/wsfont/wsfont.h> 56 #include <dev/rasops/rasops.h> 57 #include <dev/wscons/wsdisplay_vconsvar.h> 58 #include <dev/pci/wsdisplay_pci.h> 59 60 #include <dev/i2c/i2cvar.h> 61 #include <dev/i2c/i2c_bitbang.h> 62 #include <dev/i2c/ddcvar.h> 63 #include <dev/videomode/videomode.h> 64 #include <dev/videomode/edidvar.h> 65 #include <dev/videomode/edidreg.h> 66 67 struct pm3fb_softc { 68 device_t sc_dev; 69 70 pci_chipset_tag_t sc_pc; 71 pcitag_t sc_pcitag; 72 73 bus_space_tag_t sc_memt; 74 bus_space_tag_t sc_iot; 75 76 bus_space_handle_t sc_regh; 77 bus_addr_t sc_fb, sc_reg; 78 bus_size_t sc_fbsize, sc_regsize; 79 80 int sc_width, sc_height, sc_depth, sc_stride; 81 int sc_locked; 82 struct vcons_screen sc_console_screen; 83 struct wsscreen_descr sc_defaultscreen_descr; 84 const struct wsscreen_descr *sc_screens[1]; 85 struct wsscreen_list sc_screenlist; 86 struct vcons_data vd; 87 int sc_mode; 88 u_char sc_cmap_red[256]; 89 u_char sc_cmap_green[256]; 90 u_char sc_cmap_blue[256]; 91 /* i2c stuff */ 92 struct i2c_controller sc_i2c; 93 uint8_t sc_edid_data[128]; 94 struct edid_info sc_ei; 95 const struct videomode *sc_videomode; 96 }; 97 98 static int pm3fb_match(device_t, cfdata_t, void *); 99 static void pm3fb_attach(device_t, device_t, void *); 100 101 CFATTACH_DECL_NEW(pm3fb, sizeof(struct pm3fb_softc), 102 pm3fb_match, pm3fb_attach, NULL, NULL); 103 104 extern const u_char rasops_cmap[768]; 105 106 static int pm3fb_ioctl(void *, void *, u_long, void *, int, struct lwp *); 107 static paddr_t pm3fb_mmap(void *, void *, off_t, int); 108 static void pm3fb_init_screen(void *, struct vcons_screen *, int, long *); 109 110 static int pm3fb_putcmap(struct pm3fb_softc *, struct wsdisplay_cmap *); 111 static int pm3fb_getcmap(struct pm3fb_softc *, struct wsdisplay_cmap *); 112 static void pm3fb_init_palette(struct pm3fb_softc *); 113 static int pm3fb_putpalreg(struct pm3fb_softc *, uint8_t, uint8_t, uint8_t, uint8_t); 114 115 static void pm3fb_init(struct pm3fb_softc *); 116 static inline void pm3fb_wait(struct pm3fb_softc *, int); 117 static void pm3fb_flush_engine(struct pm3fb_softc *); 118 static void pm3fb_rectfill(struct pm3fb_softc *, int, int, int, int, uint32_t); 119 static void pm3fb_bitblt(void *, int, int, int, int, int, int, int); 120 121 static void pm3fb_cursor(void *, int, int, int); 122 static void pm3fb_putchar(void *, int, int, u_int, long); 123 static void pm3fb_copycols(void *, int, int, int, int); 124 static void pm3fb_erasecols(void *, int, int, int, long); 125 static void pm3fb_copyrows(void *, int, int, int); 126 static void pm3fb_eraserows(void *, int, int, long); 127 128 struct wsdisplay_accessops pm3fb_accessops = { 129 pm3fb_ioctl, 130 pm3fb_mmap, 131 NULL, /* alloc_screen */ 132 NULL, /* free_screen */ 133 NULL, /* show_screen */ 134 NULL, /* load_font */ 135 NULL, /* pollc */ 136 NULL /* scroll */ 137 }; 138 139 /* I2C glue */ 140 static int pm3fb_i2c_send_start(void *, int); 141 static int pm3fb_i2c_send_stop(void *, int); 142 static int pm3fb_i2c_initiate_xfer(void *, i2c_addr_t, int); 143 static int pm3fb_i2c_read_byte(void *, uint8_t *, int); 144 static int pm3fb_i2c_write_byte(void *, uint8_t, int); 145 146 /* I2C bitbang glue */ 147 static void pm3fb_i2cbb_set_bits(void *, uint32_t); 148 static void pm3fb_i2cbb_set_dir(void *, uint32_t); 149 static uint32_t pm3fb_i2cbb_read(void *); 150 151 static void pm3_setup_i2c(struct pm3fb_softc *); 152 153 static const struct i2c_bitbang_ops pm3fb_i2cbb_ops = { 154 pm3fb_i2cbb_set_bits, 155 pm3fb_i2cbb_set_dir, 156 pm3fb_i2cbb_read, 157 { 158 PM3_DD_SDA_IN, 159 PM3_DD_SCL_IN, 160 0, 161 0 162 } 163 }; 164 165 /* mode setting stuff */ 166 static int pm3fb_set_pll(struct pm3fb_softc *, int); 167 static void pm3fb_write_dac(struct pm3fb_softc *, int, uint8_t); 168 static void pm3fb_set_mode(struct pm3fb_softc *, const struct videomode *); 169 170 static inline void 171 pm3fb_wait(struct pm3fb_softc *sc, int slots) 172 { 173 uint32_t reg; 174 175 do { 176 reg = bus_space_read_4(sc->sc_memt, sc->sc_regh, 177 PM3_INPUT_FIFO_SPACE); 178 } while (reg <= slots); 179 } 180 181 static void 182 pm3fb_flush_engine(struct pm3fb_softc *sc) 183 { 184 185 pm3fb_wait(sc, 2); 186 bus_space_write_4(sc->sc_memt, sc->sc_regh, PM3_FILTER_MODE, PM3_FM_PASS_SYNC); 187 bus_space_write_4(sc->sc_memt, sc->sc_regh, PM3_SYNC, 0); 188 189 do { 190 while (bus_space_read_4(sc->sc_memt, sc->sc_regh, PM3_OUTPUT_FIFO_WORDS) == 0); 191 } while (bus_space_read_4(sc->sc_memt, sc->sc_regh, PM3_OUTPUT_FIFO) != 192 PM3_SYNC_TAG); 193 } 194 195 static int 196 pm3fb_match(device_t parent, cfdata_t match, void *aux) 197 { 198 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 199 200 if (PCI_CLASS(pa->pa_class) != PCI_CLASS_DISPLAY) 201 return 0; 202 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_3DLABS) 203 return 0; 204 205 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_3DLABS_PERMEDIA3) 206 return 100; 207 return (0); 208 } 209 210 static void 211 pm3fb_attach(device_t parent, device_t self, void *aux) 212 { 213 struct pm3fb_softc *sc = device_private(self); 214 struct pci_attach_args *pa = aux; 215 struct rasops_info *ri; 216 struct wsemuldisplaydev_attach_args aa; 217 prop_dictionary_t dict; 218 unsigned long defattr; 219 bool is_console; 220 uint32_t flags; 221 222 sc->sc_pc = pa->pa_pc; 223 sc->sc_pcitag = pa->pa_tag; 224 sc->sc_memt = pa->pa_memt; 225 sc->sc_iot = pa->pa_iot; 226 sc->sc_dev = self; 227 228 pci_aprint_devinfo(pa, NULL); 229 230 /* 231 * fill in parameters from properties 232 * if we can't get a usable mode via DDC2 we'll use this to pick one, 233 * which is why we fill them in with some conservative values that 234 * hopefully work as a last resort 235 */ 236 dict = device_properties(self); 237 if (!prop_dictionary_get_uint32(dict, "width", &sc->sc_width)) { 238 aprint_error("%s: no width property\n", device_xname(self)); 239 sc->sc_width = 1280; 240 } 241 if (!prop_dictionary_get_uint32(dict, "height", &sc->sc_height)) { 242 aprint_error("%s: no height property\n", device_xname(self)); 243 sc->sc_height = 1024; 244 } 245 if (!prop_dictionary_get_uint32(dict, "depth", &sc->sc_depth)) { 246 aprint_error("%s: no depth property\n", device_xname(self)); 247 sc->sc_depth = 8; 248 } 249 250 sc->sc_stride = sc->sc_width * (sc->sc_depth >> 3); 251 252 prop_dictionary_get_bool(dict, "is_console", &is_console); 253 254 pci_mapreg_info(pa->pa_pc, pa->pa_tag, 0x14, PCI_MAPREG_TYPE_MEM, 255 &sc->sc_fb, &sc->sc_fbsize, &flags); 256 257 if (pci_mapreg_map(pa, 0x10, PCI_MAPREG_TYPE_MEM, 0, 258 &sc->sc_memt, &sc->sc_regh, &sc->sc_reg, &sc->sc_regsize)) { 259 aprint_error("%s: failed to map registers.\n", 260 device_xname(sc->sc_dev)); 261 } 262 263 /* 264 * Permedia 3 always return 64MB fbsize 265 * 16 MB should be enough -- more just wastes map entries 266 */ 267 if (sc->sc_fbsize != 0) 268 sc->sc_fbsize = (16 << 20); 269 270 /* 271 * Some Power Mac G4 model could not initialize these registers, 272 * Power Mac G4 (Mirrored Drive Doors), for example 273 */ 274 #if defined(__powerpc__) 275 bus_space_write_4(sc->sc_memt, sc->sc_regh, PM3_LOCALMEMCAPS, 0x02e311B8); 276 bus_space_write_4(sc->sc_memt, sc->sc_regh, PM3_LOCALMEMTIMINGS, 0x07424905); 277 bus_space_write_4(sc->sc_memt, sc->sc_regh, PM3_LOCALMEMCONTROL, 0x0c000003); 278 #endif 279 280 aprint_normal("%s: %d MB aperture at 0x%08x\n", device_xname(self), 281 (int)(sc->sc_fbsize >> 20), (uint32_t)sc->sc_fb); 282 283 sc->sc_defaultscreen_descr = (struct wsscreen_descr){ 284 "default", 285 0, 0, 286 NULL, 287 8, 16, 288 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 289 NULL 290 }; 291 292 sc->sc_screens[0] = &sc->sc_defaultscreen_descr; 293 sc->sc_screenlist = (struct wsscreen_list){1, sc->sc_screens}; 294 sc->sc_mode = WSDISPLAYIO_MODE_EMUL; 295 sc->sc_locked = 0; 296 297 pm3_setup_i2c(sc); 298 299 vcons_init(&sc->vd, sc, &sc->sc_defaultscreen_descr, 300 &pm3fb_accessops); 301 302 sc->vd.init_screen = pm3fb_init_screen; 303 304 /* init engine here */ 305 pm3fb_init(sc); 306 307 ri = &sc->sc_console_screen.scr_ri; 308 309 vcons_init_screen(&sc->vd, &sc->sc_console_screen, 1, &defattr); 310 sc->sc_console_screen.scr_flags |= VCONS_SCREEN_IS_STATIC; 311 312 pm3fb_rectfill(sc, 0, 0, sc->sc_width, sc->sc_height, 313 ri->ri_devcmap[(defattr >> 16) & 0xff]); 314 pm3fb_init_palette(sc); 315 316 sc->sc_defaultscreen_descr.textops = &ri->ri_ops; 317 sc->sc_defaultscreen_descr.capabilities = ri->ri_caps; 318 sc->sc_defaultscreen_descr.nrows = ri->ri_rows; 319 sc->sc_defaultscreen_descr.ncols = ri->ri_cols; 320 321 if (is_console) { 322 323 wsdisplay_cnattach(&sc->sc_defaultscreen_descr, ri, 0, 0, 324 defattr); 325 vcons_replay_msgbuf(&sc->sc_console_screen); 326 } 327 328 329 aa.console = is_console; 330 aa.scrdata = &sc->sc_screenlist; 331 aa.accessops = &pm3fb_accessops; 332 aa.accesscookie = &sc->vd; 333 334 config_found(sc->sc_dev, &aa, wsemuldisplaydevprint, CFARGS_NONE); 335 } 336 337 static int 338 pm3fb_ioctl(void *v, void *vs, u_long cmd, void *data, int flag, 339 struct lwp *l) 340 { 341 struct vcons_data *vd = v; 342 struct pm3fb_softc *sc = vd->cookie; 343 struct wsdisplay_fbinfo *wdf; 344 struct vcons_screen *ms = vd->active; 345 346 switch (cmd) { 347 case WSDISPLAYIO_GTYPE: 348 *(u_int *)data = WSDISPLAY_TYPE_PCIMISC; 349 return 0; 350 351 /* PCI config read/write passthrough. */ 352 case PCI_IOC_CFGREAD: 353 case PCI_IOC_CFGWRITE: 354 return pci_devioctl(sc->sc_pc, sc->sc_pcitag, 355 cmd, data, flag, l); 356 357 case WSDISPLAYIO_GET_BUSID: 358 return wsdisplayio_busid_pci(sc->sc_dev, sc->sc_pc, 359 sc->sc_pcitag, data); 360 361 case WSDISPLAYIO_GINFO: 362 if (ms == NULL) 363 return ENODEV; 364 wdf = (void *)data; 365 wdf->height = ms->scr_ri.ri_height; 366 wdf->width = ms->scr_ri.ri_width; 367 wdf->depth = ms->scr_ri.ri_depth; 368 wdf->cmsize = 256; 369 return 0; 370 371 case WSDISPLAYIO_GETCMAP: 372 return pm3fb_getcmap(sc, 373 (struct wsdisplay_cmap *)data); 374 375 case WSDISPLAYIO_PUTCMAP: 376 return pm3fb_putcmap(sc, 377 (struct wsdisplay_cmap *)data); 378 379 case WSDISPLAYIO_LINEBYTES: 380 *(u_int *)data = sc->sc_stride; 381 return 0; 382 383 case WSDISPLAYIO_SMODE: { 384 int new_mode = *(int*)data; 385 if (new_mode != sc->sc_mode) { 386 sc->sc_mode = new_mode; 387 if(new_mode == WSDISPLAYIO_MODE_EMUL) { 388 /* first set the video mode */ 389 if (sc->sc_videomode != NULL) { 390 pm3fb_set_mode(sc, sc->sc_videomode); 391 } 392 /* then initialize the drawing engine */ 393 pm3fb_init(sc); 394 pm3fb_init_palette(sc); 395 vcons_redraw_screen(ms); 396 } else 397 pm3fb_flush_engine(sc); 398 } 399 } 400 return 0; 401 case WSDISPLAYIO_GET_EDID: { 402 struct wsdisplayio_edid_info *d = data; 403 d->data_size = 128; 404 if (d->buffer_size < 128) 405 return EAGAIN; 406 return copyout(sc->sc_edid_data, d->edid_data, 128); 407 } 408 409 case WSDISPLAYIO_GET_FBINFO: { 410 struct wsdisplayio_fbinfo *fbi = data; 411 return wsdisplayio_get_fbinfo(&ms->scr_ri, fbi); 412 } 413 } 414 return EPASSTHROUGH; 415 } 416 417 static paddr_t 418 pm3fb_mmap(void *v, void *vs, off_t offset, int prot) 419 { 420 struct vcons_data *vd = v; 421 struct pm3fb_softc *sc = vd->cookie; 422 paddr_t pa; 423 424 /* 'regular' framebuffer mmap()ing */ 425 if (offset < sc->sc_fbsize) { 426 pa = bus_space_mmap(sc->sc_memt, sc->sc_fb + offset, 0, prot, 427 BUS_SPACE_MAP_LINEAR | BUS_SPACE_MAP_PREFETCHABLE); 428 return pa; 429 } 430 431 /* 432 * restrict all other mappings to processes with superuser privileges 433 * or the kernel itself 434 */ 435 if (kauth_authorize_machdep(kauth_cred_get(), 436 KAUTH_MACHDEP_UNMANAGEDMEM, 437 NULL, NULL, NULL, NULL) != 0) { 438 aprint_normal("%s: mmap() rejected.\n", 439 device_xname(sc->sc_dev)); 440 return -1; 441 } 442 443 if ((offset >= sc->sc_fb) && (offset < (sc->sc_fb + sc->sc_fbsize))) { 444 pa = bus_space_mmap(sc->sc_memt, offset, 0, prot, 445 BUS_SPACE_MAP_LINEAR | BUS_SPACE_MAP_PREFETCHABLE); 446 return pa; 447 } 448 449 if ((offset >= sc->sc_reg) && 450 (offset < (sc->sc_reg + sc->sc_regsize))) { 451 pa = bus_space_mmap(sc->sc_memt, offset, 0, prot, 452 BUS_SPACE_MAP_LINEAR); 453 return pa; 454 } 455 456 #ifdef PCI_MAGIC_IO_RANGE 457 /* allow mapping of IO space */ 458 if ((offset >= PCI_MAGIC_IO_RANGE) && 459 (offset < PCI_MAGIC_IO_RANGE + 0x10000)) { 460 pa = bus_space_mmap(sc->sc_iot, offset - PCI_MAGIC_IO_RANGE, 461 0, prot, BUS_SPACE_MAP_LINEAR); 462 return pa; 463 } 464 #endif 465 return -1; 466 } 467 468 static void 469 pm3fb_init_screen(void *cookie, struct vcons_screen *scr, 470 int existing, long *defattr) 471 { 472 struct pm3fb_softc *sc = cookie; 473 struct rasops_info *ri = &scr->scr_ri; 474 475 ri->ri_depth = sc->sc_depth; 476 ri->ri_width = sc->sc_width; 477 ri->ri_height = sc->sc_height; 478 ri->ri_stride = sc->sc_stride; 479 ri->ri_flg = RI_CENTER; 480 if (sc->sc_depth == 8) 481 ri->ri_flg |= RI_8BIT_IS_RGB; 482 483 rasops_init(ri, 0, 0); 484 ri->ri_caps = WSSCREEN_WSCOLORS | WSSCREEN_UNDERLINE; 485 486 rasops_reconfig(ri, sc->sc_height / ri->ri_font->fontheight, 487 sc->sc_width / ri->ri_font->fontwidth); 488 489 ri->ri_hw = scr; 490 ri->ri_ops.copyrows = pm3fb_copyrows; 491 ri->ri_ops.copycols = pm3fb_copycols; 492 ri->ri_ops.cursor = pm3fb_cursor; 493 ri->ri_ops.eraserows = pm3fb_eraserows; 494 ri->ri_ops.erasecols = pm3fb_erasecols; 495 ri->ri_ops.putchar = pm3fb_putchar; 496 } 497 498 static int 499 pm3fb_putcmap(struct pm3fb_softc *sc, struct wsdisplay_cmap *cm) 500 { 501 u_char *r, *g, *b; 502 u_int index = cm->index; 503 u_int count = cm->count; 504 int i, error; 505 u_char rbuf[256], gbuf[256], bbuf[256]; 506 507 if (cm->index >= 256 || cm->count > 256 || 508 (cm->index + cm->count) > 256) 509 return EINVAL; 510 error = copyin(cm->red, &rbuf[index], count); 511 if (error) 512 return error; 513 error = copyin(cm->green, &gbuf[index], count); 514 if (error) 515 return error; 516 error = copyin(cm->blue, &bbuf[index], count); 517 if (error) 518 return error; 519 520 memcpy(&sc->sc_cmap_red[index], &rbuf[index], count); 521 memcpy(&sc->sc_cmap_green[index], &gbuf[index], count); 522 memcpy(&sc->sc_cmap_blue[index], &bbuf[index], count); 523 524 r = &sc->sc_cmap_red[index]; 525 g = &sc->sc_cmap_green[index]; 526 b = &sc->sc_cmap_blue[index]; 527 528 for (i = 0; i < count; i++) { 529 pm3fb_putpalreg(sc, index, *r, *g, *b); 530 index++; 531 r++, g++, b++; 532 } 533 return 0; 534 } 535 536 static int 537 pm3fb_getcmap(struct pm3fb_softc *sc, struct wsdisplay_cmap *cm) 538 { 539 u_int index = cm->index; 540 u_int count = cm->count; 541 int error; 542 543 if (index >= 255 || count > 256 || index + count > 256) 544 return EINVAL; 545 546 error = copyout(&sc->sc_cmap_red[index], cm->red, count); 547 if (error) 548 return error; 549 error = copyout(&sc->sc_cmap_green[index], cm->green, count); 550 if (error) 551 return error; 552 error = copyout(&sc->sc_cmap_blue[index], cm->blue, count); 553 if (error) 554 return error; 555 556 return 0; 557 } 558 559 static void 560 pm3fb_init_palette(struct pm3fb_softc *sc) 561 { 562 struct rasops_info *ri = &sc->sc_console_screen.scr_ri; 563 int i, j = 0; 564 uint8_t cmap[768]; 565 566 rasops_get_cmap(ri, cmap, sizeof(cmap)); 567 568 for (i = 0; i < 256; i++) { 569 sc->sc_cmap_red[i] = cmap[j]; 570 sc->sc_cmap_green[i] = cmap[j + 1]; 571 sc->sc_cmap_blue[i] = cmap[j + 2]; 572 pm3fb_putpalreg(sc, i, cmap[j], cmap[j + 1], cmap[j + 2]); 573 j += 3; 574 } 575 } 576 577 static int 578 pm3fb_putpalreg(struct pm3fb_softc *sc, uint8_t idx, uint8_t r, uint8_t g, uint8_t b) 579 { 580 581 pm3fb_wait(sc, 4); 582 bus_space_write_1(sc->sc_memt, sc->sc_regh, PM3_DAC_PAL_WRITE_IDX, idx); 583 bus_space_write_1(sc->sc_memt, sc->sc_regh, PM3_DAC_PAL_DATA, r); 584 bus_space_write_1(sc->sc_memt, sc->sc_regh, PM3_DAC_PAL_DATA, g); 585 bus_space_write_1(sc->sc_memt, sc->sc_regh, PM3_DAC_PAL_DATA, b); 586 return 0; 587 } 588 589 static void 590 pm3fb_write_dac(struct pm3fb_softc *sc, int reg, uint8_t data) 591 { 592 593 pm3fb_wait(sc, 3); 594 bus_space_write_1(sc->sc_memt, sc->sc_regh, PM3_DAC_INDEX_LOW, reg & 0xff); 595 bus_space_write_1(sc->sc_memt, sc->sc_regh, PM3_DAC_INDEX_HIGH, (reg >> 8) & 0xff); 596 bus_space_write_1(sc->sc_memt, sc->sc_regh, PM3_DAC_INDEX_DATA, data); 597 } 598 599 static void 600 pm3fb_init(struct pm3fb_softc *sc) 601 { 602 603 pm3fb_wait(sc, 16); 604 bus_space_write_4(sc->sc_memt, sc->sc_regh, PM3_LB_DESTREAD_MODE, 0); 605 bus_space_write_4(sc->sc_memt, sc->sc_regh, PM3_LB_DESTREAD_ENABLES, 0); 606 bus_space_write_4(sc->sc_memt, sc->sc_regh, PM3_LB_SOURCEREAD_MODE, 0); 607 bus_space_write_4(sc->sc_memt, sc->sc_regh, PM3_LB_WRITE_MODE, 0); 608 bus_space_write_4(sc->sc_memt, sc->sc_regh, PM3_FILTER_MODE, PM3_FM_PASS_SYNC); 609 bus_space_write_4(sc->sc_memt, sc->sc_regh, PM3_STATISTIC_MODE, 0); 610 bus_space_write_4(sc->sc_memt, sc->sc_regh, PM3_DELTA_MODE, 0); 611 bus_space_write_4(sc->sc_memt, sc->sc_regh, PM3_RASTERIZER_MODE, 0); 612 bus_space_write_4(sc->sc_memt, sc->sc_regh, PM3_SCISSOR_MODE, 0); 613 bus_space_write_4(sc->sc_memt, sc->sc_regh, PM3_LINESTIPPLE_MODE, 0); 614 bus_space_write_4(sc->sc_memt, sc->sc_regh, PM3_AREASTIPPLE_MODE, 0); 615 bus_space_write_4(sc->sc_memt, sc->sc_regh, PM3_GID_MODE, 0); 616 bus_space_write_4(sc->sc_memt, sc->sc_regh, PM3_DEPTH_MODE, 0); 617 bus_space_write_4(sc->sc_memt, sc->sc_regh, PM3_STENCIL_MODE, 0); 618 bus_space_write_4(sc->sc_memt, sc->sc_regh, PM3_STENCIL_DATA, 0); 619 bus_space_write_4(sc->sc_memt, sc->sc_regh, PM3_COLORDDA_MODE, 0); 620 621 pm3fb_wait(sc, 16); 622 bus_space_write_4(sc->sc_memt, sc->sc_regh, PM3_TEXTUREADDRESS_MODE, 0); 623 bus_space_write_4(sc->sc_memt, sc->sc_regh, PM3_TEXTUREINDEX_MODE0, 0); 624 bus_space_write_4(sc->sc_memt, sc->sc_regh, PM3_TEXTUREINDEX_MODE1, 0); 625 bus_space_write_4(sc->sc_memt, sc->sc_regh, PM3_TEXTUREREAD_MODE, 0); 626 bus_space_write_4(sc->sc_memt, sc->sc_regh, PM3_TEXELLUT_MODE, 0); 627 bus_space_write_4(sc->sc_memt, sc->sc_regh, PM3_TEXTUREFILTER_MODE, 0); 628 bus_space_write_4(sc->sc_memt, sc->sc_regh, PM3_TEXTURECOMPOSITE_MODE, 0); 629 bus_space_write_4(sc->sc_memt, sc->sc_regh, PM3_TEXTURECOLOR_MODE, 0); 630 bus_space_write_4(sc->sc_memt, sc->sc_regh, PM3_TEXTURECOMPOSITECOLOR_MODE1, 0); 631 bus_space_write_4(sc->sc_memt, sc->sc_regh, PM3_TEXTURECOMPOSITEALPHA_MODE1, 0); 632 bus_space_write_4(sc->sc_memt, sc->sc_regh, PM3_TEXTURECOMPOSITECOLOR_MODE0, 0); 633 bus_space_write_4(sc->sc_memt, sc->sc_regh, PM3_TEXTURECOMPOSITEALPHA_MODE0, 0); 634 bus_space_write_4(sc->sc_memt, sc->sc_regh, PM3_FOG_MODE, 0); 635 bus_space_write_4(sc->sc_memt, sc->sc_regh, PM3_CHROMATEST_MODE, 0); 636 bus_space_write_4(sc->sc_memt, sc->sc_regh, PM3_ALPHATEST_MODE, 0); 637 bus_space_write_4(sc->sc_memt, sc->sc_regh, PM3_ANTIALIAS_MODE, 0); 638 639 pm3fb_wait(sc, 16); 640 bus_space_write_4(sc->sc_memt, sc->sc_regh, PM3_YUV_MODE, 0); 641 bus_space_write_4(sc->sc_memt, sc->sc_regh, PM3_ALPHABLENDCOLOR_MODE, 0); 642 bus_space_write_4(sc->sc_memt, sc->sc_regh, PM3_ALPHABLENDALPHA_MODE, 0); 643 bus_space_write_4(sc->sc_memt, sc->sc_regh, PM3_DITHER_MODE, 0); 644 bus_space_write_4(sc->sc_memt, sc->sc_regh, PM3_LOGICALOP_MODE, 0); 645 bus_space_write_4(sc->sc_memt, sc->sc_regh, PM3_ROUTER_MODE, 0); 646 bus_space_write_4(sc->sc_memt, sc->sc_regh, PM3_WINDOW, 0); 647 bus_space_write_4(sc->sc_memt, sc->sc_regh, PM3_CONFIG2D, 0); 648 bus_space_write_4(sc->sc_memt, sc->sc_regh, PM3_SPANCOLORMASK, 0xffffffff); 649 bus_space_write_4(sc->sc_memt, sc->sc_regh, PM3_XBIAS, 0); 650 bus_space_write_4(sc->sc_memt, sc->sc_regh, PM3_YBIAS, 0); 651 bus_space_write_4(sc->sc_memt, sc->sc_regh, PM3_DELTACONTROL, 0); 652 bus_space_write_4(sc->sc_memt, sc->sc_regh, PM3_BITMASKPATTERN, 0xffffffff); 653 bus_space_write_4(sc->sc_memt, sc->sc_regh, PM3_FBDESTREAD_ENABLE, 654 PM3_FBDESTREAD_SET(0xff, 0xff, 0xff)); 655 bus_space_write_4(sc->sc_memt, sc->sc_regh, PM3_FBDESTREAD_BUFFERADDRESS0, 0); 656 657 pm3fb_wait(sc, 16); 658 bus_space_write_4(sc->sc_memt, sc->sc_regh, PM3_FBDESTREAD_BUFFEROFFSET0, 0); 659 bus_space_write_4(sc->sc_memt, sc->sc_regh, PM3_FBDESTREAD_BUFFERWIDTH0, 660 PM3_FBDESTREAD_BUFFERWIDTH_WIDTH(sc->sc_stride)); 661 bus_space_write_4(sc->sc_memt, sc->sc_regh, PM3_FB_DESTREAD_MODE, 662 PM3_FBDRM_ENABLE | PM3_FBDRM_ENABLE0); 663 bus_space_write_4(sc->sc_memt, sc->sc_regh, PM3_FBSOURCEREAD_BUFFERADDRESS, 0); 664 bus_space_write_4(sc->sc_memt, sc->sc_regh, PM3_FBSOURCEREAD_BUFFEROFFSET, 0); 665 bus_space_write_4(sc->sc_memt, sc->sc_regh, PM3_FBSOURCEREAD_BUFFERWIDTH, 666 PM3_FBSOURCEREAD_BUFFERWIDTH_WIDTH(sc->sc_stride)); 667 bus_space_write_4(sc->sc_memt, sc->sc_regh, PM3_FBSOURCEREAD_MODE, 668 PM3_FBSOURCEREAD_MODE_BLOCKING | PM3_FBSOURCEREAD_MODE_ENABLE); 669 bus_space_write_4(sc->sc_memt, sc->sc_regh, PM3_PIXEL_SIZE, PM3_PS_8BIT); 670 bus_space_write_4(sc->sc_memt, sc->sc_regh, PM3_FBSOFTWAREWRITEMASK, 0xffffffff); 671 bus_space_write_4(sc->sc_memt, sc->sc_regh, PM3_FBHARDWAREWRITEMASK, 0xffffffff); 672 bus_space_write_4(sc->sc_memt, sc->sc_regh, PM3_FBWRITE_MODE, 673 PM3_FBWRITEMODE_WRITEENABLE | PM3_FBWRITEMODE_OPAQUESPAN | PM3_FBWRITEMODE_ENABLE0); 674 bus_space_write_4(sc->sc_memt, sc->sc_regh, PM3_FBWRITEBUFFERADDRESS0, 0); 675 bus_space_write_4(sc->sc_memt, sc->sc_regh, PM3_FBWRITEBUFFEROFFSET0, 0); 676 bus_space_write_4(sc->sc_memt, sc->sc_regh, PM3_FBWRITEBUFFERWIDTH0, 677 PM3_FBWRITEBUFFERWIDTH_WIDTH(sc->sc_stride)); 678 bus_space_write_4(sc->sc_memt, sc->sc_regh, PM3_SIZEOF_FRAMEBUFFER, 4095); 679 bus_space_write_4(sc->sc_memt, sc->sc_regh, PM3_DITHER_MODE, PM3_CF_TO_DIM_CF(4)); 680 bus_space_write_4(sc->sc_memt, sc->sc_regh, PM3_DXDOM, 0); 681 682 pm3fb_wait(sc, 6); 683 bus_space_write_4(sc->sc_memt, sc->sc_regh, PM3_DXSUB, 0); 684 bus_space_write_4(sc->sc_memt, sc->sc_regh, PM3_DY, 1 << 16); 685 bus_space_write_4(sc->sc_memt, sc->sc_regh, PM3_STARTXDOM, 0); 686 bus_space_write_4(sc->sc_memt, sc->sc_regh, PM3_STARTXSUB, 0); 687 bus_space_write_4(sc->sc_memt, sc->sc_regh, PM3_STARTY, 0); 688 bus_space_write_4(sc->sc_memt, sc->sc_regh, PM3_COUNT, 0); 689 } 690 691 static void 692 pm3fb_rectfill(struct pm3fb_softc *sc, int x, int y, int wi, int he, 693 uint32_t colour) 694 { 695 pm3fb_wait(sc, 4); 696 697 bus_space_write_4(sc->sc_memt, sc->sc_regh, PM3_CONFIG2D, 698 PM3_CONFIG2D_USECONSTANTSOURCE | PM3_CONFIG2D_FOREGROUNDROP_ENABLE | 699 (PM3_CONFIG2D_FOREGROUNDROP(0x3)) | PM3_CONFIG2D_FBWRITE_ENABLE); 700 701 bus_space_write_4(sc->sc_memt, sc->sc_regh, PM3_FOREGROUNDCOLOR, colour); 702 703 bus_space_write_4(sc->sc_memt, sc->sc_regh, PM3_RECTANGLEPOSITION, 704 (((y) & 0xffff) << 16) | ((x) & 0xffff) ); 705 706 bus_space_write_4(sc->sc_memt, sc->sc_regh, PM3_RENDER2D, 707 PM3_RENDER2D_XPOSITIVE | PM3_RENDER2D_YPOSITIVE | 708 PM3_RENDER2D_OPERATION_NORMAL | PM3_RENDER2D_SPANOPERATION | 709 (((he) & 0x0fff) << 16) | ((wi) & 0x0fff)); 710 711 #ifdef PM3FB_DEBUG 712 pm3fb_flush_engine(sc); 713 #endif 714 } 715 716 static void 717 pm3fb_bitblt(void *cookie, int srcx, int srcy, int dstx, int dsty, 718 int width, int height, int rop) 719 { 720 struct pm3fb_softc *sc = cookie; 721 int x_align, offset_x, offset_y; 722 uint32_t dir = 0; 723 724 offset_x = srcx - dstx; 725 offset_y = srcy - dsty; 726 727 if (dsty <= srcy) { 728 dir |= PM3_RENDER2D_YPOSITIVE; 729 } 730 731 if (dstx <= srcx) { 732 dir |= PM3_RENDER2D_XPOSITIVE; 733 } 734 735 x_align = (srcx & 0x1f); 736 737 pm3fb_wait(sc, 6); 738 739 if (rop == 3){ 740 bus_space_write_4(sc->sc_memt, sc->sc_regh, PM3_CONFIG2D, 741 PM3_CONFIG2D_USERSCISSOR_ENABLE | PM3_CONFIG2D_FOREGROUNDROP_ENABLE | PM3_CONFIG2D_BLOCKING | 742 PM3_CONFIG2D_FOREGROUNDROP(rop) | PM3_CONFIG2D_FBWRITE_ENABLE); 743 } else { 744 bus_space_write_4(sc->sc_memt, sc->sc_regh, PM3_CONFIG2D, 745 PM3_CONFIG2D_USERSCISSOR_ENABLE | PM3_CONFIG2D_FOREGROUNDROP_ENABLE | PM3_CONFIG2D_BLOCKING | 746 PM3_CONFIG2D_FOREGROUNDROP(rop) | PM3_CONFIG2D_FBWRITE_ENABLE | PM3_CONFIG2D_FBDESTREAD_ENABLE); 747 } 748 749 bus_space_write_4(sc->sc_memt, sc->sc_regh, PM3_SCISSORMINXY, 750 ((dsty & 0x0fff) << 16) | (dstx & 0x0fff)); 751 752 bus_space_write_4(sc->sc_memt, sc->sc_regh, PM3_SCISSORMAXXY, 753 (((dsty + height) & 0x0fff) << 16) | ((dstx + width) & 0x0fff)); 754 755 bus_space_write_4(sc->sc_memt, sc->sc_regh, PM3_FBSOURCEREAD_BUFFEROFFSET, 756 (((offset_y) & 0xffff) << 16) | ((offset_x) & 0xffff)); 757 758 bus_space_write_4(sc->sc_memt, sc->sc_regh, PM3_RECTANGLEPOSITION, 759 (((dsty) & 0xffff) << 16) | ((dstx - x_align) & 0xffff)); 760 761 bus_space_write_4(sc->sc_memt, sc->sc_regh, PM3_RENDER2D, 762 dir | 763 PM3_RENDER2D_OPERATION_NORMAL | PM3_RENDER2D_SPANOPERATION | PM3_RENDER2D_FBSOURCEREADENABLE | 764 (((height) & 0x0fff) << 16) | ((width + x_align) & 0x0fff)); 765 766 #ifdef PM3FB_DEBUG 767 pm3fb_flush_engine(sc); 768 #endif 769 } 770 771 static void 772 pm3fb_cursor(void *cookie, int on, int row, int col) 773 { 774 struct rasops_info *ri = cookie; 775 struct vcons_screen *scr = ri->ri_hw; 776 struct pm3fb_softc *sc = scr->scr_cookie; 777 int x, y, wi, he; 778 779 wi = ri->ri_font->fontwidth; 780 he = ri->ri_font->fontheight; 781 782 if (sc->sc_mode == WSDISPLAYIO_MODE_EMUL) { 783 x = ri->ri_ccol * wi + ri->ri_xorigin; 784 y = ri->ri_crow * he + ri->ri_yorigin; 785 if (ri->ri_flg & RI_CURSOR) { 786 pm3fb_bitblt(sc, x, y, x, y, wi, he, 12); 787 ri->ri_flg &= ~RI_CURSOR; 788 } 789 ri->ri_crow = row; 790 ri->ri_ccol = col; 791 if (on) { 792 x = ri->ri_ccol * wi + ri->ri_xorigin; 793 y = ri->ri_crow * he + ri->ri_yorigin; 794 pm3fb_bitblt(sc, x, y, x, y, wi, he, 12); 795 ri->ri_flg |= RI_CURSOR; 796 } 797 } else { 798 scr->scr_ri.ri_crow = row; 799 scr->scr_ri.ri_ccol = col; 800 scr->scr_ri.ri_flg &= ~RI_CURSOR; 801 } 802 } 803 804 static void 805 pm3fb_putchar(void *cookie, int row, int col, u_int c, long attr) 806 { 807 struct rasops_info *ri = cookie; 808 struct wsdisplay_font *font = PICK_FONT(ri, c); 809 struct vcons_screen *scr = ri->ri_hw; 810 struct pm3fb_softc *sc = scr->scr_cookie; 811 uint32_t mode; 812 813 if (sc->sc_mode == WSDISPLAYIO_MODE_EMUL) { 814 void *data; 815 uint32_t fg, bg; 816 int uc, i; 817 int x, y, wi, he; 818 819 wi = font->fontwidth; 820 he = font->fontheight; 821 822 if (!CHAR_IN_FONT(c, font)) 823 return; 824 825 bg = ri->ri_devcmap[(attr >> 16) & 0xf]; 826 fg = ri->ri_devcmap[(attr >> 24) & 0xf]; 827 x = ri->ri_xorigin + col * wi; 828 y = ri->ri_yorigin + row * he; 829 if (c == 0x20) { 830 pm3fb_rectfill(sc, x, y, wi, he, bg); 831 } else { 832 uc = c - font->firstchar; 833 data = (uint8_t *)font->data + uc * ri->ri_fontscale; 834 mode = PM3_RM_MASK_MIRROR; 835 836 #if BYTE_ORDER == LITTLE_ENDIAN 837 switch (ri->ri_font->stride) { 838 case 1: 839 mode |= 4 << 7; 840 break; 841 case 2: 842 mode |= 3 << 7; 843 break; 844 } 845 #else 846 switch (ri->ri_font->stride) { 847 case 1: 848 mode |= 3 << 7; 849 break; 850 case 2: 851 mode |= 2 << 7; 852 break; 853 } 854 #endif 855 pm3fb_wait(sc, 8); 856 bus_space_write_4(sc->sc_memt, sc->sc_regh, 857 PM3_FOREGROUNDCOLOR, fg); 858 bus_space_write_4(sc->sc_memt, sc->sc_regh, 859 PM3_BACKGROUNDCOLOR, bg); 860 861 bus_space_write_4(sc->sc_memt, sc->sc_regh, PM3_RASTERIZER_MODE, mode); 862 863 bus_space_write_4(sc->sc_memt, sc->sc_regh, 864 PM3_CONFIG2D, 865 PM3_CONFIG2D_USERSCISSOR_ENABLE | 866 PM3_CONFIG2D_USECONSTANTSOURCE | 867 PM3_CONFIG2D_FOREGROUNDROP_ENABLE | 868 PM3_CONFIG2D_FOREGROUNDROP(0x03) | 869 PM3_CONFIG2D_OPAQUESPAN | 870 PM3_CONFIG2D_FBWRITE_ENABLE); 871 872 bus_space_write_4(sc->sc_memt, sc->sc_regh, 873 PM3_SCISSORMINXY, ((y & 0x0fff) << 16) | (x & 0x0fff)); 874 875 bus_space_write_4(sc->sc_memt, sc->sc_regh, 876 PM3_SCISSORMAXXY, (((y + he) & 0x0fff) << 16) | ((x + wi) & 0x0fff)); 877 878 bus_space_write_4(sc->sc_memt, sc->sc_regh, 879 PM3_RECTANGLEPOSITION, (((y) & 0xffff)<<16) | ((x) & 0xffff)); 880 881 bus_space_write_4(sc->sc_memt, sc->sc_regh, 882 PM3_RENDER2D, 883 PM3_RENDER2D_XPOSITIVE | 884 PM3_RENDER2D_YPOSITIVE | 885 PM3_RENDER2D_OPERATION_SYNCONBITMASK | 886 PM3_RENDER2D_SPANOPERATION | 887 ((wi) & 0x0fff) | (((he) & 0x0fff) << 16)); 888 889 pm3fb_wait(sc, he); 890 891 switch (ri->ri_font->stride) { 892 case 1: { 893 uint8_t *data8 = data; 894 uint32_t reg; 895 for (i = 0; i < he; i++) { 896 reg = *data8; 897 bus_space_write_4(sc->sc_memt, 898 sc->sc_regh, 899 PM3_BITMASKPATTERN, reg); 900 data8++; 901 } 902 break; 903 } 904 case 2: { 905 uint16_t *data16 = data; 906 uint32_t reg; 907 for (i = 0; i < he; i++) { 908 reg = *data16; 909 bus_space_write_4(sc->sc_memt, 910 sc->sc_regh, 911 PM3_BITMASKPATTERN, reg); 912 data16++; 913 } 914 break; 915 } 916 } 917 } 918 } 919 } 920 921 static void 922 pm3fb_copycols(void *cookie, int row, int srccol, int dstcol, int ncols) 923 { 924 struct rasops_info *ri = cookie; 925 struct vcons_screen *scr = ri->ri_hw; 926 struct pm3fb_softc *sc = scr->scr_cookie; 927 int32_t xs, xd, y, width, height; 928 929 if ((sc->sc_locked == 0) && (sc->sc_mode == WSDISPLAYIO_MODE_EMUL)) { 930 xs = ri->ri_xorigin + ri->ri_font->fontwidth * srccol; 931 xd = ri->ri_xorigin + ri->ri_font->fontwidth * dstcol; 932 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 933 width = ri->ri_font->fontwidth * ncols; 934 height = ri->ri_font->fontheight; 935 pm3fb_bitblt(sc, xs, y, xd, y, width, height, 3); 936 } 937 } 938 939 static void 940 pm3fb_erasecols(void *cookie, int row, int startcol, int ncols, long fillattr) 941 { 942 struct rasops_info *ri = cookie; 943 struct vcons_screen *scr = ri->ri_hw; 944 struct pm3fb_softc *sc = scr->scr_cookie; 945 int32_t x, y, width, height, fg, bg, ul; 946 947 if ((sc->sc_locked == 0) && (sc->sc_mode == WSDISPLAYIO_MODE_EMUL)) { 948 x = ri->ri_xorigin + ri->ri_font->fontwidth * startcol; 949 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 950 width = ri->ri_font->fontwidth * ncols; 951 height = ri->ri_font->fontheight; 952 rasops_unpack_attr(fillattr, &fg, &bg, &ul); 953 954 pm3fb_rectfill(sc, x, y, width, height, ri->ri_devcmap[bg]); 955 } 956 } 957 958 static void 959 pm3fb_copyrows(void *cookie, int srcrow, int dstrow, int nrows) 960 { 961 struct rasops_info *ri = cookie; 962 struct vcons_screen *scr = ri->ri_hw; 963 struct pm3fb_softc *sc = scr->scr_cookie; 964 int32_t x, ys, yd, width, height; 965 966 if ((sc->sc_locked == 0) && (sc->sc_mode == WSDISPLAYIO_MODE_EMUL)) { 967 x = ri->ri_xorigin; 968 ys = ri->ri_yorigin + ri->ri_font->fontheight * srcrow; 969 yd = ri->ri_yorigin + ri->ri_font->fontheight * dstrow; 970 width = ri->ri_emuwidth; 971 height = ri->ri_font->fontheight*nrows; 972 pm3fb_bitblt(sc, x, ys, x, yd, width, height, 3); 973 } 974 } 975 976 static void 977 pm3fb_eraserows(void *cookie, int row, int nrows, long fillattr) 978 { 979 struct rasops_info *ri = cookie; 980 struct vcons_screen *scr = ri->ri_hw; 981 struct pm3fb_softc *sc = scr->scr_cookie; 982 int32_t x, y, width, height, fg, bg, ul; 983 984 if ((sc->sc_locked == 0) && (sc->sc_mode == WSDISPLAYIO_MODE_EMUL)) { 985 x = ri->ri_xorigin; 986 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 987 width = ri->ri_emuwidth; 988 height = ri->ri_font->fontheight * nrows; 989 rasops_unpack_attr(fillattr, &fg, &bg, &ul); 990 991 pm3fb_rectfill(sc, x, y, width, height, ri->ri_devcmap[bg]); 992 } 993 } 994 995 /* should be enough */ 996 #define MODE_IS_VALID(m) (((m)->hdisplay < 2048)) 997 998 static void 999 pm3_setup_i2c(struct pm3fb_softc *sc) 1000 { 1001 int i; 1002 1003 /* Fill in the i2c tag */ 1004 iic_tag_init(&sc->sc_i2c); 1005 sc->sc_i2c.ic_cookie = sc; 1006 sc->sc_i2c.ic_send_start = pm3fb_i2c_send_start; 1007 sc->sc_i2c.ic_send_stop = pm3fb_i2c_send_stop; 1008 sc->sc_i2c.ic_initiate_xfer = pm3fb_i2c_initiate_xfer; 1009 sc->sc_i2c.ic_read_byte = pm3fb_i2c_read_byte; 1010 sc->sc_i2c.ic_write_byte = pm3fb_i2c_write_byte; 1011 sc->sc_i2c.ic_exec = NULL; 1012 1013 bus_space_write_4(sc->sc_memt, sc->sc_regh, PM3_DISPLAY_DATA, 0); 1014 1015 /* zero out the EDID buffer */ 1016 memset(sc->sc_edid_data, 0, 128); 1017 1018 /* Some monitors don't respond first time */ 1019 i = 0; 1020 while (sc->sc_edid_data[1] == 0 && i < 10) { 1021 ddc_read_edid(&sc->sc_i2c, sc->sc_edid_data, 128); 1022 i++; 1023 } 1024 1025 if (edid_parse(&sc->sc_edid_data[0], &sc->sc_ei) != -1) { 1026 /* 1027 * Now pick a mode. 1028 */ 1029 if ((sc->sc_ei.edid_preferred_mode != NULL)) { 1030 struct videomode *m = sc->sc_ei.edid_preferred_mode; 1031 if (MODE_IS_VALID(m)) { 1032 sc->sc_videomode = m; 1033 } else { 1034 aprint_error_dev(sc->sc_dev, 1035 "unable to use preferred mode\n"); 1036 } 1037 } 1038 /* 1039 * if we can't use the preferred mode go look for the 1040 * best one we can support 1041 */ 1042 if (sc->sc_videomode == NULL) { 1043 struct videomode *m = sc->sc_ei.edid_modes; 1044 1045 sort_modes(sc->sc_ei.edid_modes, 1046 &sc->sc_ei.edid_preferred_mode, 1047 sc->sc_ei.edid_nmodes); 1048 if (sc->sc_videomode == NULL) 1049 for (int n = 0; n < sc->sc_ei.edid_nmodes; n++) 1050 if (MODE_IS_VALID(&m[n])) { 1051 sc->sc_videomode = &m[n]; 1052 break; 1053 } 1054 } 1055 } 1056 if (sc->sc_videomode == NULL) { 1057 /* no EDID data? */ 1058 sc->sc_videomode = pick_mode_by_ref(sc->sc_width, 1059 sc->sc_height, 60); 1060 } 1061 if (sc->sc_videomode != NULL) { 1062 pm3fb_set_mode(sc, sc->sc_videomode); 1063 } 1064 } 1065 1066 /* I2C bitbanging */ 1067 static void pm3fb_i2cbb_set_bits(void *cookie, uint32_t bits) 1068 { 1069 struct pm3fb_softc *sc = cookie; 1070 uint32_t out; 1071 1072 out = bits << 2; /* bitmasks match the IN bits */ 1073 1074 bus_space_write_4(sc->sc_memt, sc->sc_regh, PM3_DISPLAY_DATA, out); 1075 delay(100); 1076 } 1077 1078 static void pm3fb_i2cbb_set_dir(void *cookie, uint32_t dir) 1079 { 1080 /* Nothing to do */ 1081 } 1082 1083 static uint32_t pm3fb_i2cbb_read(void *cookie) 1084 { 1085 struct pm3fb_softc *sc = cookie; 1086 uint32_t bits; 1087 1088 bits = bus_space_read_4(sc->sc_memt, sc->sc_regh, PM3_DISPLAY_DATA); 1089 return bits; 1090 } 1091 1092 /* higher level I2C stuff */ 1093 static int 1094 pm3fb_i2c_send_start(void *cookie, int flags) 1095 { 1096 1097 return (i2c_bitbang_send_start(cookie, flags, &pm3fb_i2cbb_ops)); 1098 } 1099 1100 static int 1101 pm3fb_i2c_send_stop(void *cookie, int flags) 1102 { 1103 1104 return (i2c_bitbang_send_stop(cookie, flags, &pm3fb_i2cbb_ops)); 1105 } 1106 1107 static int 1108 pm3fb_i2c_initiate_xfer(void *cookie, i2c_addr_t addr, int flags) 1109 { 1110 1111 return (i2c_bitbang_initiate_xfer(cookie, addr, flags, 1112 &pm3fb_i2cbb_ops)); 1113 } 1114 1115 static int 1116 pm3fb_i2c_read_byte(void *cookie, uint8_t *valp, int flags) 1117 { 1118 1119 return (i2c_bitbang_read_byte(cookie, valp, flags, &pm3fb_i2cbb_ops)); 1120 } 1121 1122 static int 1123 pm3fb_i2c_write_byte(void *cookie, uint8_t val, int flags) 1124 { 1125 return (i2c_bitbang_write_byte(cookie, val, flags, &pm3fb_i2cbb_ops)); 1126 } 1127 1128 static int 1129 pm3fb_set_pll(struct pm3fb_softc *sc, int freq) 1130 { 1131 uint8_t bf = 0, bpre = 0, bpost = 0; 1132 int count; 1133 unsigned long feedback, prescale, postscale, IntRef, VCO, out_freq, diff, VCOlow, VCOhigh, bdiff = 1000000; 1134 1135 freq *= 10; /* convert into 100Hz units */ 1136 1137 for (postscale = 0; postscale <= 5; postscale++) { 1138 /* 1139 * It is pointless going through the main loop if all values of 1140 * prescale produce an VCO outside the acceptable range 1141 */ 1142 prescale = 1; 1143 feedback = (prescale * (1UL << postscale) * freq) / (2 * PM3_EXT_CLOCK_FREQ); 1144 VCOlow = (2 * PM3_EXT_CLOCK_FREQ * feedback) / prescale; 1145 if (VCOlow > PM3_VCO_FREQ_MAX) 1146 continue; 1147 1148 prescale = 255; 1149 feedback = (prescale * (1UL << postscale) * freq) / (2 * PM3_EXT_CLOCK_FREQ); 1150 VCOhigh = (2 * PM3_EXT_CLOCK_FREQ * feedback) / prescale; 1151 if (VCOhigh < PM3_VCO_FREQ_MIN) 1152 continue; 1153 1154 for (prescale = 1; prescale <= 255; prescale++) { 1155 IntRef = PM3_EXT_CLOCK_FREQ / prescale; 1156 if (IntRef < PM3_INTREF_MIN || IntRef > PM3_INTREF_MAX) { 1157 if (IntRef > PM3_INTREF_MAX) { 1158 /* 1159 * Hopefully we will get into range as the prescale 1160 * value increases 1161 */ 1162 continue; 1163 } else { 1164 /* 1165 * already below minimum and it will only get worse 1166 * move to the next postscale value 1167 */ 1168 break; 1169 } 1170 } 1171 1172 feedback = (prescale * (1UL << postscale) * freq) / (2 * PM3_EXT_CLOCK_FREQ); 1173 1174 if (feedback > 255) { 1175 /* 1176 * prescale, feedbackscale & postscale registers 1177 * are only 8 bits wide 1178 */ 1179 break; 1180 } else if (feedback == 255) { 1181 count = 1; 1182 } else { 1183 count = 2; 1184 } 1185 1186 do { 1187 VCO = (2 * PM3_EXT_CLOCK_FREQ * feedback) / prescale; 1188 if (VCO >= PM3_VCO_FREQ_MIN && VCO <= PM3_VCO_FREQ_MAX) { 1189 out_freq = VCO / (1UL << postscale); 1190 diff = abs(out_freq - freq); 1191 if (diff < bdiff) { 1192 bdiff = diff; 1193 bf = feedback; 1194 bpre = prescale; 1195 bpost = postscale; 1196 if (diff == 0) 1197 goto out; 1198 } 1199 } 1200 feedback++; 1201 } while (--count >= 0); 1202 } 1203 } 1204 out: 1205 pm3fb_write_dac(sc, PM3_RAMDAC_CMD_CLOCK0_PRE_SCALE, bpre); 1206 pm3fb_write_dac(sc, PM3_RAMDAC_CMD_CLOCK0_FEEDBACK_SCALE, bf); 1207 pm3fb_write_dac(sc, PM3_RAMDAC_CMD_CLOCK0_POST_SCALE, bpost); 1208 return 0; 1209 } 1210 1211 static void 1212 pm3fb_set_mode(struct pm3fb_softc *sc, const struct videomode *mode) 1213 { 1214 int t1, t2, t3, t4, stride; 1215 uint32_t vclk, tmp1; 1216 uint8_t sync = 0; 1217 1218 bus_space_write_4(sc->sc_memt, sc->sc_regh, PM3_BYPASS_MASK, 0xffffffff); 1219 bus_space_write_4(sc->sc_memt, sc->sc_regh, PM3_APERTURE1_CONTROL, 0x00000000); 1220 bus_space_write_4(sc->sc_memt, sc->sc_regh, PM3_APERTURE2_CONTROL, 0x00000000); 1221 bus_space_write_4(sc->sc_memt, sc->sc_regh, PM3_FIFODISCONNECT, 0x00000007); 1222 1223 t1 = mode->hsync_start - mode->hdisplay; 1224 t2 = mode->vsync_start - mode->vdisplay; 1225 t3 = mode->hsync_end - mode->hsync_start; 1226 t4 = mode->vsync_end - mode->vsync_start; 1227 stride = (mode->hdisplay + 31) & ~31; 1228 1229 bus_space_write_4(sc->sc_memt, sc->sc_regh, PM3_HORIZ_TOTAL, 1230 ((mode->htotal - 1) >> 4)); 1231 bus_space_write_4(sc->sc_memt, sc->sc_regh, PM3_HORIZ_SYNC_END, 1232 (t1 + t3) >> 4); 1233 bus_space_write_4(sc->sc_memt, sc->sc_regh, PM3_HORIZ_SYNC_START, 1234 (t1 >> 4)); 1235 bus_space_write_4(sc->sc_memt, sc->sc_regh, PM3_HORIZ_BLANK_END, 1236 (mode->htotal - mode->hdisplay) >> 4); 1237 bus_space_write_4(sc->sc_memt, sc->sc_regh, PM3_HORIZ_GATE_END, 1238 (mode->htotal - mode->hdisplay) >> 4); 1239 bus_space_write_4(sc->sc_memt, sc->sc_regh, PM3_SCREEN_STRIDE, 1240 (stride >> 4)); 1241 1242 bus_space_write_4(sc->sc_memt, sc->sc_regh, 1243 PM3_VERT_TOTAL, mode->vtotal - 1); 1244 bus_space_write_4(sc->sc_memt, sc->sc_regh, 1245 PM3_VERT_SYNC_END, t2 + t4 - 1); 1246 bus_space_write_4(sc->sc_memt, sc->sc_regh, 1247 PM3_VERT_SYNC_START, t2 - 1); 1248 bus_space_write_4(sc->sc_memt, sc->sc_regh, 1249 PM3_VERT_BLANK_END, mode->vtotal - mode->vdisplay); 1250 1251 /*8bpp*/ 1252 bus_space_write_4(sc->sc_memt, sc->sc_regh, 1253 PM3_BYAPERTURE1MODE, PM3_BYAPERTUREMODE_PIXELSIZE_8BIT); 1254 bus_space_write_4(sc->sc_memt, sc->sc_regh, 1255 PM3_BYAPERTURE2MODE, PM3_BYAPERTUREMODE_PIXELSIZE_8BIT); 1256 bus_space_write_4(sc->sc_memt, sc->sc_regh, PM3_VIDEO_CONTROL, 1257 (PM3_VC_ENABLE | PM3_VC_HSC_ACTIVE_HIGH | PM3_VC_VSC_ACTIVE_HIGH | PM3_VC_PIXELSIZE_8BIT)); 1258 1259 vclk = bus_space_read_4(sc->sc_memt, sc->sc_regh, PM3_V_CLOCK_CTL); 1260 bus_space_write_4(sc->sc_memt, sc->sc_regh, PM3_V_CLOCK_CTL, (vclk & 0xFFFFFFFC)); 1261 bus_space_write_4(sc->sc_memt, sc->sc_regh, PM3_SCREEN_BASE, 0x0); 1262 1263 tmp1 = bus_space_read_4(sc->sc_memt, sc->sc_regh, PM3_CHIP_CONFIG); 1264 bus_space_write_4(sc->sc_memt, sc->sc_regh, PM3_CHIP_CONFIG, tmp1 & 0xFFFFFFFD); 1265 1266 pm3fb_set_pll(sc, mode->dot_clock); 1267 1268 if (mode->flags & VID_PHSYNC) 1269 sync |= PM3_SC_HSYNC_ACTIVE_HIGH; 1270 if (mode->flags & VID_PVSYNC) 1271 sync |= PM3_SC_VSYNC_ACTIVE_HIGH; 1272 1273 bus_space_write_4(sc->sc_memt, sc->sc_regh, 1274 PM3_RD_PM3_INDEX_CONTROL, PM3_INCREMENT_DISABLE); 1275 pm3fb_write_dac(sc, PM3_RAMDAC_CMD_SYNC_CONTROL, sync); 1276 pm3fb_write_dac(sc, PM3_RAMDAC_CMD_DAC_CONTROL, 0x00); 1277 1278 pm3fb_write_dac(sc, PM3_RAMDAC_CMD_PIXEL_SIZE, PM3_DACPS_8BIT); 1279 pm3fb_write_dac(sc, PM3_RAMDAC_CMD_COLOR_FORMAT, 1280 (PM3_CF_ORDER_BGR | PM3_CF_VISUAL_256_COLOR)); 1281 pm3fb_write_dac(sc, PM3_RAMDAC_CMD_MISC_CONTROL, PM3_MC_DAC_SIZE_8BIT); 1282 1283 bus_space_write_4(sc->sc_memt, sc->sc_regh, PM3_FIFOCONTROL, 0x00000905); 1284 1285 sc->sc_width = mode->hdisplay; 1286 sc->sc_height = mode->vdisplay; 1287 sc->sc_depth = 8; 1288 sc->sc_stride = stride; 1289 aprint_normal_dev(sc->sc_dev, "pm3 using %d x %d in 8 bit, stride %d\n", 1290 sc->sc_width, sc->sc_height, stride); 1291 } 1292
Indexes created Mon Sep 29 21:09:56 GMT 2025