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r128fbreg.h revision 1.3.12.1
      1  1.3.12.1       mrg /*	$NetBSD: r128fbreg.h,v 1.3.12.1 2012/02/18 07:34:51 mrg Exp $	*/
      2       1.1  macallan 
      3       1.1  macallan /*
      4       1.1  macallan  * Copyright 1999, 2000 ATI Technologies Inc., Markham, Ontario,
      5       1.1  macallan  *                      Precision Insight, Inc., Cedar Park, Texas, and
      6       1.1  macallan  *                      VA Linux Systems Inc., Fremont, California.
      7       1.1  macallan  *
      8       1.1  macallan  * All Rights Reserved.
      9       1.1  macallan  *
     10       1.1  macallan  * Permission is hereby granted, free of charge, to any person obtaining
     11       1.1  macallan  * a copy of this software and associated documentation files (the
     12       1.1  macallan  * "Software"), to deal in the Software without restriction, including
     13       1.1  macallan  * without limitation on the rights to use, copy, modify, merge,
     14       1.1  macallan  * publish, distribute, sublicense, and/or sell copies of the Software,
     15       1.1  macallan  * and to permit persons to whom the Software is furnished to do so,
     16       1.1  macallan  * subject to the following conditions:
     17       1.1  macallan  *
     18       1.1  macallan  * The above copyright notice and this permission notice (including the
     19       1.1  macallan  * next paragraph) shall be included in all copies or substantial
     20       1.1  macallan  * portions of the Software.
     21       1.1  macallan  *
     22       1.1  macallan  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
     23       1.1  macallan  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
     24       1.1  macallan  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
     25       1.1  macallan  * NON-INFRINGEMENT.  IN NO EVENT SHALL ATI, PRECISION INSIGHT, VA LINUX
     26       1.1  macallan  * SYSTEMS AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
     27       1.1  macallan  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
     28       1.1  macallan  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
     29       1.1  macallan  * OTHER DEALINGS IN THE SOFTWARE.
     30       1.1  macallan  */
     31       1.1  macallan 
     32       1.1  macallan /*
     33       1.1  macallan  * Authors:
     34       1.1  macallan  *   Rickard E. Faith <faith (at) valinux.com>
     35       1.1  macallan  *   Kevin E. Martin <martin (at) valinux.com>
     36       1.1  macallan  *   Gareth Hughes <gareth (at) valinux.com>
     37       1.1  macallan  *
     38       1.1  macallan  * References:
     39       1.1  macallan  *
     40       1.1  macallan  *   RAGE 128 VR/ RAGE 128 GL Register Reference Manual (Technical
     41       1.1  macallan  *   Reference Manual P/N RRG-G04100-C Rev. 0.04), ATI Technologies: April
     42       1.1  macallan  *   1999.
     43       1.1  macallan  *
     44       1.1  macallan  *   RAGE 128 Software Development Manual (Technical Reference Manual P/N
     45       1.1  macallan  *   SDK-G04000 Rev. 0.01), ATI Technologies: June 1999.
     46       1.1  macallan  *
     47       1.1  macallan  */
     48       1.1  macallan 
     49       1.1  macallan /*
     50       1.1  macallan  * register definitions for ATI Rage 128 graphics controllers
     51       1.1  macallan  * mostly from XFree86's ati driver
     52       1.1  macallan  */
     53       1.1  macallan 
     54       1.1  macallan 
     55       1.1  macallan #ifndef R128FB_REG_H
     56       1.1  macallan #define R128FB_REG_H
     57       1.1  macallan 
     58       1.2  macallan /* RAMDAC */
     59       1.2  macallan #define R128_PALETTE_DATA		0x00b4
     60       1.2  macallan #define R128_PALETTE_INDEX		0x00b0
     61       1.2  macallan 
     62       1.2  macallan /* flat panel registers */
     63       1.2  macallan #define R128_FP_PANEL_CNTL		0x0288
     64       1.2  macallan 	#define FPCNT_DIGON		  0x00000001	/* FP dig. voltage */
     65       1.2  macallan 	#define FPCNT_BACKLIGHT_ON	  0x00000002
     66       1.2  macallan 	#define FPCNT_BL_MODULATION_ON	  0x00000004
     67       1.2  macallan 	#define FPCNT_BL_CLK_SEL	  0x00000008	/* 1 - divide by 3 */
     68       1.2  macallan 	#define FPCNT_MONID_EN		  0x00000010	/* use MONID pins for
     69       1.2  macallan 							   backlight control */
     70       1.2  macallan 	#define FPCNT_FPENABLE_POL	  0x00000020	/* 1 - active low */
     71       1.2  macallan 	#define FPCNT_LEVEL_MASK	  0x0000ff00
     72       1.2  macallan 	#define FPCNT_LEVEL_SHIFT	  8
     73       1.2  macallan 
     74       1.2  macallan #define R128_LVDS_GEN_CNTL                0x02d0
     75       1.2  macallan #       define R128_LVDS_ON               (1   <<  0)
     76       1.2  macallan #       define R128_LVDS_DISPLAY_DIS      (1   <<  1)
     77       1.2  macallan #       define R128_LVDS_EN               (1   <<  7)
     78       1.2  macallan #       define R128_LVDS_DIGON            (1   << 18)
     79       1.2  macallan #       define R128_LVDS_BLON             (1   << 19)
     80       1.2  macallan #       define R128_LVDS_SEL_CRTC2        (1   << 23)
     81       1.2  macallan #       define R128_HSYNC_DELAY_SHIFT     28
     82       1.2  macallan #       define R128_HSYNC_DELAY_MASK      (0xf << 28)
     83       1.2  macallan #	define R128_LEVEL_MASK	          0x0000ff00
     84       1.2  macallan #	define R128_LEVEL_SHIFT	          8
     85       1.1  macallan 
     86       1.2  macallan /* drawing engine */
     87       1.1  macallan #define R128_PC_NGUI_CTLSTAT              0x0184
     88       1.1  macallan #       define R128_PC_FLUSH_GUI          (3 << 0)
     89       1.1  macallan #       define R128_PC_RI_GUI             (1 << 2)
     90       1.1  macallan #       define R128_PC_FLUSH_ALL          0x00ff
     91       1.1  macallan #       define R128_PC_BUSY               (1 << 31)
     92       1.1  macallan 
     93       1.1  macallan #define R128_CRTC_OFFSET                  0x0224
     94       1.1  macallan 
     95       1.1  macallan #define R128_DST_OFFSET                   0x1404
     96       1.1  macallan #define R128_DST_PITCH                    0x1408
     97       1.1  macallan 
     98       1.1  macallan #define R128_DP_GUI_MASTER_CNTL           0x146c
     99       1.1  macallan #       define R128_GMC_SRC_PITCH_OFFSET_CNTL (1    <<  0)
    100       1.1  macallan #       define R128_GMC_DST_PITCH_OFFSET_CNTL (1    <<  1)
    101       1.1  macallan #       define R128_GMC_SRC_CLIPPING          (1    <<  2)
    102       1.1  macallan #       define R128_GMC_DST_CLIPPING          (1    <<  3)
    103       1.1  macallan #       define R128_GMC_BRUSH_DATATYPE_MASK   (0x0f <<  4)
    104       1.1  macallan #       define R128_GMC_BRUSH_8X8_MONO_FG_BG  (0    <<  4)
    105       1.1  macallan #       define R128_GMC_BRUSH_8X8_MONO_FG_LA  (1    <<  4)
    106       1.1  macallan #       define R128_GMC_BRUSH_1X8_MONO_FG_BG  (4    <<  4)
    107       1.1  macallan #       define R128_GMC_BRUSH_1X8_MONO_FG_LA  (5    <<  4)
    108       1.1  macallan #       define R128_GMC_BRUSH_32x1_MONO_FG_BG (6    <<  4)
    109       1.1  macallan #       define R128_GMC_BRUSH_32x1_MONO_FG_LA (7    <<  4)
    110       1.1  macallan #       define R128_GMC_BRUSH_32x32_MONO_FG_BG (8    <<  4)
    111       1.1  macallan #       define R128_GMC_BRUSH_32x32_MONO_FG_LA (9    <<  4)
    112       1.1  macallan #       define R128_GMC_BRUSH_8x8_COLOR       (10   <<  4)
    113       1.1  macallan #       define R128_GMC_BRUSH_1X8_COLOR       (12   <<  4)
    114       1.1  macallan #       define R128_GMC_BRUSH_SOLID_COLOR     (13   <<  4)
    115       1.1  macallan #       define R128_GMC_BRUSH_NONE            (15   <<  4)
    116       1.1  macallan #       define R128_GMC_DST_8BPP_CI           (2    <<  8)
    117       1.1  macallan #       define R128_GMC_DST_15BPP             (3    <<  8)
    118       1.1  macallan #       define R128_GMC_DST_16BPP             (4    <<  8)
    119       1.1  macallan #       define R128_GMC_DST_24BPP             (5    <<  8)
    120       1.1  macallan #       define R128_GMC_DST_32BPP             (6    <<  8)
    121       1.1  macallan #       define R128_GMC_DST_8BPP_RGB          (7    <<  8)
    122       1.1  macallan #       define R128_GMC_DST_Y8                (8    <<  8)
    123       1.1  macallan #       define R128_GMC_DST_RGB8              (9    <<  8)
    124       1.1  macallan #       define R128_GMC_DST_VYUY              (11   <<  8)
    125       1.1  macallan #       define R128_GMC_DST_YVYU              (12   <<  8)
    126       1.1  macallan #       define R128_GMC_DST_AYUV444           (14   <<  8)
    127       1.1  macallan #       define R128_GMC_DST_ARGB4444          (15   <<  8)
    128       1.1  macallan #       define R128_GMC_DST_DATATYPE_MASK     (0x0f <<  8)
    129       1.1  macallan #       define R128_GMC_DST_DATATYPE_SHIFT    8
    130       1.1  macallan #       define R128_GMC_SRC_DATATYPE_MASK       (3    << 12)
    131       1.1  macallan #       define R128_GMC_SRC_DATATYPE_MONO_FG_BG (0    << 12)
    132       1.1  macallan #       define R128_GMC_SRC_DATATYPE_MONO_FG_LA (1    << 12)
    133       1.1  macallan #       define R128_GMC_SRC_DATATYPE_COLOR      (3    << 12)
    134       1.1  macallan #       define R128_GMC_BYTE_PIX_ORDER        (1    << 14)
    135       1.1  macallan #       define R128_GMC_BYTE_MSB_TO_LSB       (0    << 14)
    136       1.1  macallan #       define R128_GMC_BYTE_LSB_TO_MSB       (1    << 14)
    137       1.1  macallan #       define R128_GMC_CONVERSION_TEMP       (1    << 15)
    138       1.1  macallan #       define R128_GMC_CONVERSION_TEMP_6500  (0    << 15)
    139       1.1  macallan #       define R128_GMC_CONVERSION_TEMP_9300  (1    << 15)
    140       1.1  macallan #       define R128_GMC_ROP3_MASK             (0xff << 16)
    141       1.1  macallan #       define R128_DP_SRC_SOURCE_MASK        (7    << 24)
    142       1.1  macallan #       define R128_DP_SRC_SOURCE_MEMORY      (2    << 24)
    143       1.1  macallan #       define R128_DP_SRC_SOURCE_HOST_DATA   (3    << 24)
    144       1.3  macallan #       define R128_DP_SRC_SOURCE_HOST_ALIGN  (4    << 24)
    145       1.1  macallan #       define R128_GMC_3D_FCN_EN             (1    << 27)
    146       1.1  macallan #       define R128_GMC_CLR_CMP_CNTL_DIS      (1    << 28)
    147       1.1  macallan #       define R128_GMC_AUX_CLIP_DIS          (1    << 29)
    148       1.1  macallan #       define R128_GMC_WR_MSK_DIS            (1    << 30)
    149       1.1  macallan #       define R128_GMC_LD_BRUSH_Y_X          (1    << 31)
    150       1.1  macallan #       define R128_ROP3_ZERO             0x00000000
    151       1.1  macallan #       define R128_ROP3_DSa              0x00880000
    152       1.1  macallan #       define R128_ROP3_SDna             0x00440000
    153       1.1  macallan #       define R128_ROP3_S                0x00cc0000
    154       1.1  macallan #       define R128_ROP3_DSna             0x00220000
    155       1.1  macallan #       define R128_ROP3_D                0x00aa0000
    156       1.1  macallan #       define R128_ROP3_DSx              0x00660000
    157       1.1  macallan #       define R128_ROP3_DSo              0x00ee0000
    158       1.1  macallan #       define R128_ROP3_DSon             0x00110000
    159       1.1  macallan #       define R128_ROP3_DSxn             0x00990000
    160       1.1  macallan #       define R128_ROP3_Dn               0x00550000
    161       1.1  macallan #       define R128_ROP3_SDno             0x00dd0000
    162       1.1  macallan #       define R128_ROP3_Sn               0x00330000
    163       1.1  macallan #       define R128_ROP3_DSno             0x00bb0000
    164       1.1  macallan #       define R128_ROP3_DSan             0x00770000
    165       1.1  macallan #       define R128_ROP3_ONE              0x00ff0000
    166       1.1  macallan #       define R128_ROP3_DPa              0x00a00000
    167       1.1  macallan #       define R128_ROP3_PDna             0x00500000
    168       1.1  macallan #       define R128_ROP3_P                0x00f00000
    169       1.1  macallan #       define R128_ROP3_DPna             0x000a0000
    170       1.1  macallan #       define R128_ROP3_D                0x00aa0000
    171       1.1  macallan #       define R128_ROP3_DPx              0x005a0000
    172       1.1  macallan #       define R128_ROP3_DPo              0x00fa0000
    173       1.1  macallan #       define R128_ROP3_DPon             0x00050000
    174       1.1  macallan #       define R128_ROP3_PDxn             0x00a50000
    175       1.1  macallan #       define R128_ROP3_PDno             0x00f50000
    176       1.1  macallan #       define R128_ROP3_Pn               0x000f0000
    177       1.1  macallan #       define R128_ROP3_DPno             0x00af0000
    178       1.1  macallan #       define R128_ROP3_DPan             0x005f0000
    179       1.1  macallan 
    180       1.1  macallan #define R128_DP_BRUSH_BKGD_CLR            0x1478
    181       1.1  macallan #define R128_DP_BRUSH_FRGD_CLR            0x147c
    182       1.1  macallan #define R128_SRC_X_Y                      0x1590
    183       1.1  macallan #define R128_DST_X_Y                      0x1594
    184       1.1  macallan #define R128_DST_WIDTH_HEIGHT             0x1598
    185       1.1  macallan 
    186       1.1  macallan #define R128_SRC_OFFSET                   0x15ac
    187       1.1  macallan #define R128_SRC_PITCH                    0x15b0
    188       1.1  macallan 
    189       1.1  macallan #define R128_AUX_SC_CNTL                  0x1660
    190       1.1  macallan #       define R128_AUX1_SC_EN            (1 << 0)
    191       1.1  macallan #       define R128_AUX1_SC_MODE_OR       (0 << 1)
    192       1.1  macallan #       define R128_AUX1_SC_MODE_NAND     (1 << 1)
    193       1.1  macallan #       define R128_AUX2_SC_EN            (1 << 2)
    194       1.1  macallan #       define R128_AUX2_SC_MODE_OR       (0 << 3)
    195       1.1  macallan #       define R128_AUX2_SC_MODE_NAND     (1 << 3)
    196       1.1  macallan #       define R128_AUX3_SC_EN            (1 << 4)
    197       1.1  macallan #       define R128_AUX3_SC_MODE_OR       (0 << 5)
    198       1.1  macallan #       define R128_AUX3_SC_MODE_NAND     (1 << 5)
    199       1.1  macallan 
    200       1.1  macallan #define R128_DP_CNTL                      0x16c0
    201       1.1  macallan #       define R128_DST_X_LEFT_TO_RIGHT   (1 <<  0)
    202       1.1  macallan #       define R128_DST_Y_TOP_TO_BOTTOM   (1 <<  1)
    203       1.1  macallan 
    204       1.1  macallan #define R128_DP_DATATYPE                  0x16c4
    205       1.1  macallan #       define R128_HOST_BIG_ENDIAN_EN    (1 << 29)
    206       1.1  macallan 
    207       1.3  macallan #define R128_DP_MIX                       0x16c8
    208       1.3  macallan #	define R128_MIX_SRC_VRAM		  (2 << 8)
    209       1.3  macallan #	define R128_MIX_SRC_HOSTDATA		  (3 << 8)
    210       1.3  macallan #	define R128_MIX_SRC_HOST_BYTEALIGN	  (4 << 8)
    211       1.3  macallan #	define R128_MIX_SRC_ROP3_MASK		  (0xff << 16)
    212       1.3  macallan 
    213       1.1  macallan #define R128_DP_WRITE_MASK                0x16cc
    214       1.3  macallan #define R128_DP_SRC_BKGD_CLR              0x15dc
    215       1.3  macallan #define R128_DP_SRC_FRGD_CLR              0x15d8
    216       1.1  macallan 
    217       1.1  macallan #define R128_DP_CNTL_XDIR_YDIR_YMAJOR     0x16d0
    218       1.1  macallan #       define R128_DST_Y_MAJOR             (1 <<  2)
    219       1.1  macallan #       define R128_DST_Y_DIR_TOP_TO_BOTTOM (1 << 15)
    220       1.1  macallan #       define R128_DST_X_DIR_LEFT_TO_RIGHT (1 << 31)
    221       1.1  macallan 
    222       1.1  macallan #define R128_DEFAULT_OFFSET               0x16e0
    223       1.1  macallan #define R128_DEFAULT_PITCH                0x16e4
    224       1.1  macallan #define R128_DEFAULT_SC_BOTTOM_RIGHT      0x16e8
    225       1.1  macallan #       define R128_DEFAULT_SC_RIGHT_MAX  (0x1fff <<  0)
    226       1.1  macallan #       define R128_DEFAULT_SC_BOTTOM_MAX (0x1fff << 16)
    227       1.1  macallan 
    228       1.3  macallan /* scissor registers */
    229       1.3  macallan #define R128_SC_BOTTOM                    0x164c
    230       1.3  macallan #define R128_SC_BOTTOM_RIGHT              0x16f0
    231       1.3  macallan #define R128_SC_BOTTOM_RIGHT_C            0x1c8c
    232       1.3  macallan #define R128_SC_LEFT                      0x1640
    233       1.3  macallan #define R128_SC_RIGHT                     0x1644
    234       1.3  macallan #define R128_SC_TOP                       0x1648
    235       1.1  macallan #define R128_SC_TOP_LEFT                  0x16ec
    236       1.3  macallan #define R128_SC_TOP_LEFT_C                0x1c88
    237       1.1  macallan 
    238       1.1  macallan #define R128_GUI_STAT                     0x1740
    239       1.1  macallan #       define R128_GUI_FIFOCNT_MASK      0x0fff
    240       1.1  macallan #       define R128_GUI_ACTIVE            (1 << 31)
    241       1.1  macallan 
    242       1.3  macallan #define R128_HOST_DATA0                   0x17c0
    243       1.3  macallan #define R128_HOST_DATA1                   0x17c4
    244       1.3  macallan #define R128_HOST_DATA2                   0x17c8
    245       1.3  macallan #define R128_HOST_DATA3                   0x17cc
    246       1.3  macallan #define R128_HOST_DATA4                   0x17d0
    247       1.3  macallan #define R128_HOST_DATA5                   0x17d4
    248       1.3  macallan #define R128_HOST_DATA6                   0x17d8
    249       1.3  macallan #define R128_HOST_DATA7                   0x17dc
    250       1.3  macallan 
    251  1.3.12.1       mrg /* Information the firmware is supposed to leave for us */
    252  1.3.12.1       mrg #define R128_BIOS_5_SCRATCH               0x0024
    253  1.3.12.1       mrg #       define R128_BIOS_DISPLAY_FP       (1 << 0)
    254  1.3.12.1       mrg #       define R128_BIOS_DISPLAY_CRT      (2 << 0)
    255  1.3.12.1       mrg #       define R128_BIOS_DISPLAY_FP_CRT   (3 << 0)
    256  1.3.12.1       mrg 
    257  1.3.12.1       mrg /* Clock stuff */
    258  1.3.12.1       mrg #define R128_CLOCK_CNTL_INDEX             0x0008
    259  1.3.12.1       mrg #       define R128_PLL_WR_EN             (1 << 7)
    260  1.3.12.1       mrg #       define R128_PLL_DIV_SEL           (3 << 8)
    261  1.3.12.1       mrg #       define R128_PLL2_DIV_SEL_MASK     ~(3 << 8)
    262  1.3.12.1       mrg #define R128_CLOCK_CNTL_DATA              0x000c
    263  1.3.12.1       mrg 
    264  1.3.12.1       mrg #define R128_CLK_PIN_CNTL                 0x0001 /* PLL */
    265  1.3.12.1       mrg #define R128_PPLL_CNTL                    0x0002 /* PLL */
    266  1.3.12.1       mrg #       define R128_PPLL_RESET                (1 <<  0)
    267  1.3.12.1       mrg #       define R128_PPLL_SLEEP                (1 <<  1)
    268  1.3.12.1       mrg #       define R128_PPLL_ATOMIC_UPDATE_EN     (1 << 16)
    269  1.3.12.1       mrg #       define R128_PPLL_VGA_ATOMIC_UPDATE_EN (1 << 17)
    270  1.3.12.1       mrg #define R128_PPLL_REF_DIV                 0x0003 /* PLL */
    271  1.3.12.1       mrg #       define R128_PPLL_REF_DIV_MASK     0x03ff
    272  1.3.12.1       mrg #       define R128_PPLL_ATOMIC_UPDATE_R  (1 << 15) /* same as _W */
    273  1.3.12.1       mrg #       define R128_PPLL_ATOMIC_UPDATE_W  (1 << 15) /* same as _R */
    274  1.3.12.1       mrg #define R128_PPLL_DIV_0                   0x0004 /* PLL */
    275  1.3.12.1       mrg #define R128_PPLL_DIV_1                   0x0005 /* PLL */
    276  1.3.12.1       mrg #define R128_PPLL_DIV_2                   0x0006 /* PLL */
    277  1.3.12.1       mrg #define R128_PPLL_DIV_3                   0x0007 /* PLL */
    278  1.3.12.1       mrg #       define R128_PPLL_FB3_DIV_MASK     0x07ff
    279  1.3.12.1       mrg #       define R128_PPLL_POST3_DIV_MASK   0x00070000
    280  1.3.12.1       mrg #define R128_VCLK_ECP_CNTL                0x0008 /* PLL */
    281  1.3.12.1       mrg #       define R128_VCLK_SRC_SEL_MASK     0x03
    282  1.3.12.1       mrg #       define R128_VCLK_SRC_SEL_CPUCLK   0x00
    283  1.3.12.1       mrg #       define R128_VCLK_SRC_SEL_PPLLCLK  0x03
    284  1.3.12.1       mrg #       define R128_ECP_DIV_MASK          (3 << 8)
    285  1.3.12.1       mrg #define R128_HTOTAL_CNTL                  0x0009 /* PLL */
    286  1.3.12.1       mrg #define R128_X_MPLL_REF_FB_DIV            0x000a /* PLL */
    287  1.3.12.1       mrg #define R128_XPLL_CNTL                    0x000b /* PLL */
    288  1.3.12.1       mrg #define R128_XDLL_CNTL                    0x000c /* PLL */
    289  1.3.12.1       mrg #define R128_XCLK_CNTL                    0x000d /* PLL */
    290  1.3.12.1       mrg #define R128_FCP_CNTL                     0x0012 /* PLL */
    291  1.3.12.1       mrg 
    292  1.3.12.1       mrg #define R128_P2PLL_CNTL                    0x002a /* P2PLL */
    293  1.3.12.1       mrg #       define R128_P2PLL_RESET               (1 <<  0)
    294  1.3.12.1       mrg #       define R128_P2PLL_SLEEP               (1 <<  1)
    295  1.3.12.1       mrg #       define R128_P2PLL_ATOMIC_UPDATE_EN    (1 << 16)
    296  1.3.12.1       mrg #       define R128_P2PLL_VGA_ATOMIC_UPDATE_EN (1 << 17)
    297  1.3.12.1       mrg #       define R128_P2PLL_ATOMIC_UPDATE_VSYNC  (1 << 18)
    298  1.3.12.1       mrg #define R128_P2PLL_REF_DIV                 0x002B /* PLL */
    299  1.3.12.1       mrg #       define R128_P2PLL_REF_DIV_MASK     0x03ff
    300  1.3.12.1       mrg #       define R128_P2PLL_ATOMIC_UPDATE_R  (1 << 15) /* same as _W */
    301  1.3.12.1       mrg #       define R128_P2PLL_ATOMIC_UPDATE_W  (1 << 15) /* same as _R */
    302  1.3.12.1       mrg #define R128_P2PLL_DIV_0                   0x002c
    303  1.3.12.1       mrg #       define R128_P2PLL_FB0_DIV_MASK     0x07ff
    304  1.3.12.1       mrg #       define R128_P2PLL_POST0_DIV_MASK   0x00070000
    305  1.3.12.1       mrg #define R128_V2CLK_VCLKTV_CNTL            0x002d /* PLL */
    306  1.3.12.1       mrg #       define R128_V2CLK_SRC_SEL_MASK    0x03
    307  1.3.12.1       mrg #       define R128_V2CLK_SRC_SEL_CPUCLK  0x00
    308  1.3.12.1       mrg #       define R128_V2CLK_SRC_SEL_P2PLLCLK 0x03
    309  1.3.12.1       mrg #define R128_HTOTAL2_CNTL                 0x002e /* PLL */
    310  1.3.12.1       mrg 
    311  1.3.12.1       mrg /* CTRCs */
    312  1.3.12.1       mrg #define R128_CRTC_GEN_CNTL                0x0050
    313  1.3.12.1       mrg #       define R128_CRTC_DBL_SCAN_EN      (1 <<  0)
    314  1.3.12.1       mrg #       define R128_CRTC_INTERLACE_EN     (1 <<  1)
    315  1.3.12.1       mrg #       define R128_CRTC_CSYNC_EN         (1 <<  4)
    316  1.3.12.1       mrg #	define R128_CRTC_PIX_WIDTH	  (7 <<  8)
    317  1.3.12.1       mrg #	define R128_CRTC_COLOR_8BIT	  (2 <<  8)
    318  1.3.12.1       mrg #	define R128_CRTC_COLOR_15BIT	  (3 <<  8)
    319  1.3.12.1       mrg #	define R128_CRTC_COLOR_16BIT	  (4 <<  8)
    320  1.3.12.1       mrg #	define R128_CRTC_COLOR_24BIT	  (5 <<  8)
    321  1.3.12.1       mrg #	define R128_CRTC_COLOR_32BIT	  (6 <<  8)
    322  1.3.12.1       mrg #       define R128_CRTC_CUR_EN           (1 << 16)
    323  1.3.12.1       mrg #       define R128_CRTC_CUR_MODE_MASK    (7 << 17)
    324  1.3.12.1       mrg #       define R128_CRTC_ICON_EN          (1 << 20)
    325  1.3.12.1       mrg #       define R128_CRTC_EXT_DISP_EN      (1 << 24)
    326  1.3.12.1       mrg #       define R128_CRTC_EN               (1 << 25)
    327  1.3.12.1       mrg #       define R128_CRTC_DISP_REQ_EN_B    (1 << 26)
    328  1.3.12.1       mrg #define R128_CRTC_EXT_CNTL                0x0054
    329  1.3.12.1       mrg #       define R128_CRTC_VGA_XOVERSCAN    (1 <<  0)
    330  1.3.12.1       mrg #       define R128_VGA_ATI_LINEAR        (1 <<  3)
    331  1.3.12.1       mrg #       define R128_XCRT_CNT_EN           (1 <<  6)
    332  1.3.12.1       mrg #       define R128_CRTC_HSYNC_DIS        (1 <<  8)
    333  1.3.12.1       mrg #       define R128_CRTC_VSYNC_DIS        (1 <<  9)
    334  1.3.12.1       mrg #       define R128_CRTC_DISPLAY_DIS      (1 << 10)
    335  1.3.12.1       mrg #       define R128_CRTC_CRT_ON           (1 << 15)
    336  1.3.12.1       mrg #       define R128_FP_OUT_EN             (1 << 22)
    337  1.3.12.1       mrg #       define R128_FP_ACTIVE             (1 << 23)
    338  1.3.12.1       mrg #define R128_CRTC_EXT_CNTL_DPMS_BYTE      0x0055
    339  1.3.12.1       mrg #       define R128_CRTC_HSYNC_DIS_BYTE   (1 <<  0)
    340  1.3.12.1       mrg #       define R128_CRTC_VSYNC_DIS_BYTE   (1 <<  1)
    341  1.3.12.1       mrg #       define R128_CRTC_DISPLAY_DIS_BYTE (1 <<  2)
    342  1.3.12.1       mrg #define R128_CRTC_STATUS                  0x005c
    343  1.3.12.1       mrg #       define R128_CRTC_VBLANK_SAVE      (1 <<  1)
    344  1.3.12.1       mrg 
    345  1.3.12.1       mrg #define R128_CRTC_H_TOTAL_DISP            0x0200
    346  1.3.12.1       mrg #       define R128_CRTC_H_TOTAL          (0x01ff << 0)
    347  1.3.12.1       mrg #       define R128_CRTC_H_TOTAL_SHIFT    0
    348  1.3.12.1       mrg #       define R128_CRTC_H_DISP           (0x00ff << 16)
    349  1.3.12.1       mrg #       define R128_CRTC_H_DISP_SHIFT     16
    350  1.3.12.1       mrg #define R128_CRTC_H_SYNC_STRT_WID         0x0204
    351  1.3.12.1       mrg #       define R128_CRTC_H_SYNC_STRT_PIX        (0x07  <<  0)
    352  1.3.12.1       mrg #       define R128_CRTC_H_SYNC_STRT_CHAR       (0x1ff <<  3)
    353  1.3.12.1       mrg #       define R128_CRTC_H_SYNC_STRT_CHAR_SHIFT 3
    354  1.3.12.1       mrg #       define R128_CRTC_H_SYNC_WID             (0x3f  << 16)
    355  1.3.12.1       mrg #       define R128_CRTC_H_SYNC_WID_SHIFT       16
    356  1.3.12.1       mrg #       define R128_CRTC_H_SYNC_POL             (1     << 23)
    357  1.3.12.1       mrg #define R128_CRTC_V_TOTAL_DISP            0x0208
    358  1.3.12.1       mrg #       define R128_CRTC_V_TOTAL          (0x07ff << 0)
    359  1.3.12.1       mrg #       define R128_CRTC_V_TOTAL_SHIFT    0
    360  1.3.12.1       mrg #       define R128_CRTC_V_DISP           (0x07ff << 16)
    361  1.3.12.1       mrg #       define R128_CRTC_V_DISP_SHIFT     16
    362  1.3.12.1       mrg #define R128_CRTC_V_SYNC_STRT_WID         0x020c
    363  1.3.12.1       mrg #       define R128_CRTC_V_SYNC_STRT       (0x7ff <<  0)
    364  1.3.12.1       mrg #       define R128_CRTC_V_SYNC_STRT_SHIFT 0
    365  1.3.12.1       mrg #       define R128_CRTC_V_SYNC_WID        (0x1f  << 16)
    366  1.3.12.1       mrg #       define R128_CRTC_V_SYNC_WID_SHIFT  16
    367  1.3.12.1       mrg #       define R128_CRTC_V_SYNC_POL        (1     << 23)
    368  1.3.12.1       mrg #define R128_CRTC_VLINE_CRNT_VLINE        0x0210
    369  1.3.12.1       mrg #       define R128_CRTC_CRNT_VLINE_MASK  (0x7ff << 16)
    370  1.3.12.1       mrg #define R128_CRTC_CRNT_FRAME              0x0214
    371  1.3.12.1       mrg #define R128_CRTC_GUI_TRIG_VLINE          0x0218
    372  1.3.12.1       mrg #define R128_CRTC_DEBUG                   0x021c
    373  1.3.12.1       mrg #define R128_CRTC_OFFSET                  0x0224
    374  1.3.12.1       mrg #define R128_CRTC_OFFSET_CNTL             0x0228
    375  1.3.12.1       mrg #define R128_CRTC_PITCH                   0x022c
    376  1.3.12.1       mrg 
    377  1.3.12.1       mrg #define R128_CRTC2_H_TOTAL_DISP           0x0300
    378  1.3.12.1       mrg #       define R128_CRTC2_H_TOTAL          (0x01ff << 0)
    379  1.3.12.1       mrg #       define R128_CRTC2_H_TOTAL_SHIFT    0
    380  1.3.12.1       mrg #       define R128_CRTC2_H_DISP           (0x00ff << 16)
    381  1.3.12.1       mrg #       define R128_CRTC2_H_DISP_SHIFT     16
    382  1.3.12.1       mrg #define R128_CRTC2_H_SYNC_STRT_WID        0x0304
    383  1.3.12.1       mrg #       define R128_CRTC2_H_SYNC_STRT_PIX        (0x07  <<  0)
    384  1.3.12.1       mrg #       define R128_CRTC2_H_SYNC_STRT_CHAR       (0x1ff <<  3)
    385  1.3.12.1       mrg #       define R128_CRTC2_H_SYNC_STRT_CHAR_SHIFT 3
    386  1.3.12.1       mrg #       define R128_CRTC2_H_SYNC_WID             (0x3f  << 16)
    387  1.3.12.1       mrg #       define R128_CRTC2_H_SYNC_WID_SHIFT       16
    388  1.3.12.1       mrg #       define R128_CRTC2_H_SYNC_POL             (1     << 23)
    389  1.3.12.1       mrg #define R128_CRTC2_V_TOTAL_DISP           0x0308
    390  1.3.12.1       mrg #       define R128_CRTC2_V_TOTAL          (0x07ff << 0)
    391  1.3.12.1       mrg #       define R128_CRTC2_V_TOTAL_SHIFT    0
    392  1.3.12.1       mrg #       define R128_CRTC2_V_DISP           (0x07ff << 16)
    393  1.3.12.1       mrg #       define R128_CRTC2_V_DISP_SHIFT     16
    394  1.3.12.1       mrg #define R128_CRTC2_V_SYNC_STRT_WID        0x030c
    395  1.3.12.1       mrg #       define R128_CRTC2_V_SYNC_STRT       (0x7ff <<  0)
    396  1.3.12.1       mrg #       define R128_CRTC2_V_SYNC_STRT_SHIFT 0
    397  1.3.12.1       mrg #       define R128_CRTC2_V_SYNC_WID        (0x1f  << 16)
    398  1.3.12.1       mrg #       define R128_CRTC2_V_SYNC_WID_SHIFT  16
    399  1.3.12.1       mrg #       define R128_CRTC2_V_SYNC_POL        (1     << 23)
    400  1.3.12.1       mrg #define R128_CRTC2_VLINE_CRNT_VLINE       0x0310
    401  1.3.12.1       mrg #define R128_CRTC2_CRNT_FRAME             0x0314
    402  1.3.12.1       mrg #define R128_CRTC2_GUI_TRIG_VLINE         0x0318
    403  1.3.12.1       mrg #define R128_CRTC2_DEBUG                  0x031c
    404  1.3.12.1       mrg #define R128_CRTC2_OFFSET                 0x0324
    405  1.3.12.1       mrg #define R128_CRTC2_OFFSET_CNTL            0x0328
    406  1.3.12.1       mrg #	define R128_CRTC2_TILE_EN         (1 << 15)
    407  1.3.12.1       mrg #define R128_CRTC2_PITCH                  0x032c
    408  1.3.12.1       mrg #define R128_CRTC2_GEN_CNTL               0x03f8
    409  1.3.12.1       mrg #       define R128_CRTC2_DBL_SCAN_EN      (1 <<  0)
    410  1.3.12.1       mrg #       define R128_CRTC2_CUR_EN           (1 << 16)
    411  1.3.12.1       mrg #       define R128_CRTC2_ICON_EN          (1 << 20)
    412  1.3.12.1       mrg #       define R128_CRTC2_DISP_DIS         (1 << 23)
    413  1.3.12.1       mrg #       define R128_CRTC2_EN               (1 << 25)
    414  1.3.12.1       mrg #       define R128_CRTC2_DISP_REQ_EN_B    (1 << 26)
    415  1.3.12.1       mrg #define R128_CRTC2_STATUS                 0x03fc
    416  1.3.12.1       mrg 
    417       1.1  macallan #endif /* R128FB_REG_H */
    418