radeonfb.c revision 1.17.2.4
1 1.17.2.4 joerg /* $NetBSD: radeonfb.c,v 1.17.2.4 2007/11/27 19:37:19 joerg Exp $ */ 2 1.17.2.2 jmcneill 3 1.17.2.2 jmcneill /*- 4 1.17.2.2 jmcneill * Copyright (c) 2006 Itronix Inc. 5 1.17.2.2 jmcneill * All rights reserved. 6 1.17.2.2 jmcneill * 7 1.17.2.2 jmcneill * Written by Garrett D'Amore for Itronix Inc. 8 1.17.2.2 jmcneill * 9 1.17.2.2 jmcneill * Redistribution and use in source and binary forms, with or without 10 1.17.2.2 jmcneill * modification, are permitted provided that the following conditions 11 1.17.2.2 jmcneill * are met: 12 1.17.2.2 jmcneill * 1. Redistributions of source code must retain the above copyright 13 1.17.2.2 jmcneill * notice, this list of conditions and the following disclaimer. 14 1.17.2.2 jmcneill * 2. Redistributions in binary form must reproduce the above copyright 15 1.17.2.2 jmcneill * notice, this list of conditions and the following disclaimer in the 16 1.17.2.2 jmcneill * documentation and/or other materials provided with the distribution. 17 1.17.2.2 jmcneill * 3. The name of Itronix Inc. may not be used to endorse 18 1.17.2.2 jmcneill * or promote products derived from this software without specific 19 1.17.2.2 jmcneill * prior written permission. 20 1.17.2.2 jmcneill * 21 1.17.2.2 jmcneill * THIS SOFTWARE IS PROVIDED BY ITRONIX INC. ``AS IS'' AND ANY EXPRESS 22 1.17.2.2 jmcneill * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 23 1.17.2.2 jmcneill * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 1.17.2.2 jmcneill * ARE DISCLAIMED. IN NO EVENT SHALL ITRONIX INC. BE LIABLE FOR ANY 25 1.17.2.2 jmcneill * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 26 1.17.2.2 jmcneill * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE 27 1.17.2.2 jmcneill * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 1.17.2.2 jmcneill * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 29 1.17.2.2 jmcneill * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 30 1.17.2.2 jmcneill * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 31 1.17.2.2 jmcneill * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 1.17.2.2 jmcneill */ 33 1.17.2.2 jmcneill 34 1.17.2.2 jmcneill /* 35 1.17.2.2 jmcneill * ATI Technologies Inc. ("ATI") has not assisted in the creation of, and 36 1.17.2.2 jmcneill * does not endorse, this software. ATI will not be responsible or liable 37 1.17.2.2 jmcneill * for any actual or alleged damage or loss caused by or in connection with 38 1.17.2.2 jmcneill * the use of or reliance on this software. 39 1.17.2.2 jmcneill */ 40 1.17.2.2 jmcneill 41 1.17.2.2 jmcneill /* 42 1.17.2.2 jmcneill * Portions of this code were taken from XFree86's Radeon driver, which bears 43 1.17.2.2 jmcneill * this notice: 44 1.17.2.2 jmcneill * 45 1.17.2.2 jmcneill * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and 46 1.17.2.2 jmcneill * VA Linux Systems Inc., Fremont, California. 47 1.17.2.2 jmcneill * 48 1.17.2.2 jmcneill * All Rights Reserved. 49 1.17.2.2 jmcneill * 50 1.17.2.2 jmcneill * Permission is hereby granted, free of charge, to any person obtaining 51 1.17.2.2 jmcneill * a copy of this software and associated documentation files (the 52 1.17.2.2 jmcneill * "Software"), to deal in the Software without restriction, including 53 1.17.2.2 jmcneill * without limitation on the rights to use, copy, modify, merge, 54 1.17.2.2 jmcneill * publish, distribute, sublicense, and/or sell copies of the Software, 55 1.17.2.2 jmcneill * and to permit persons to whom the Software is furnished to do so, 56 1.17.2.2 jmcneill * subject to the following conditions: 57 1.17.2.2 jmcneill * 58 1.17.2.2 jmcneill * The above copyright notice and this permission notice (including the 59 1.17.2.2 jmcneill * next paragraph) shall be included in all copies or substantial 60 1.17.2.2 jmcneill * portions of the Software. 61 1.17.2.2 jmcneill * 62 1.17.2.2 jmcneill * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 63 1.17.2.2 jmcneill * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 64 1.17.2.2 jmcneill * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 65 1.17.2.2 jmcneill * NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR 66 1.17.2.2 jmcneill * THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 67 1.17.2.2 jmcneill * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 68 1.17.2.2 jmcneill * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 69 1.17.2.2 jmcneill * DEALINGS IN THE SOFTWARE. 70 1.17.2.2 jmcneill */ 71 1.17.2.2 jmcneill 72 1.17.2.2 jmcneill #include <sys/cdefs.h> 73 1.17.2.4 joerg __KERNEL_RCSID(0, "$NetBSD: radeonfb.c,v 1.17.2.4 2007/11/27 19:37:19 joerg Exp $"); 74 1.17.2.2 jmcneill 75 1.17.2.2 jmcneill #define RADEONFB_DEFAULT_DEPTH 32 76 1.17.2.2 jmcneill 77 1.17.2.2 jmcneill #include <sys/param.h> 78 1.17.2.2 jmcneill #include <sys/systm.h> 79 1.17.2.2 jmcneill #include <sys/device.h> 80 1.17.2.2 jmcneill #include <sys/malloc.h> 81 1.17.2.3 joerg #include <sys/bus.h> 82 1.17.2.2 jmcneill #include <sys/kernel.h> 83 1.17.2.2 jmcneill #include <sys/lwp.h> 84 1.17.2.2 jmcneill #include <sys/kauth.h> 85 1.17.2.2 jmcneill 86 1.17.2.2 jmcneill #include <dev/wscons/wsdisplayvar.h> 87 1.17.2.2 jmcneill #include <dev/wscons/wsconsio.h> 88 1.17.2.2 jmcneill #include <dev/wsfont/wsfont.h> 89 1.17.2.2 jmcneill #include <dev/rasops/rasops.h> 90 1.17.2.2 jmcneill #include <dev/videomode/videomode.h> 91 1.17.2.2 jmcneill #include <dev/videomode/edidvar.h> 92 1.17.2.2 jmcneill #include <dev/wscons/wsdisplay_vconsvar.h> 93 1.17.2.2 jmcneill 94 1.17.2.2 jmcneill #include <dev/pci/pcidevs.h> 95 1.17.2.2 jmcneill #include <dev/pci/pcireg.h> 96 1.17.2.2 jmcneill #include <dev/pci/pcivar.h> 97 1.17.2.2 jmcneill #include <dev/pci/radeonfbreg.h> 98 1.17.2.2 jmcneill #include <dev/pci/radeonfbvar.h> 99 1.17.2.2 jmcneill #include "opt_radeonfb.h" 100 1.17.2.2 jmcneill 101 1.17.2.2 jmcneill static int radeonfb_match(struct device *, struct cfdata *, void *); 102 1.17.2.2 jmcneill static void radeonfb_attach(struct device *, struct device *, void *); 103 1.17.2.2 jmcneill static int radeonfb_ioctl(void *, void *, unsigned long, void *, int, 104 1.17.2.2 jmcneill struct lwp *); 105 1.17.2.2 jmcneill static paddr_t radeonfb_mmap(void *, void *, off_t, int); 106 1.17.2.2 jmcneill static int radeonfb_scratch_test(struct radeonfb_softc *, int, uint32_t); 107 1.17.2.2 jmcneill static void radeonfb_loadbios(struct radeonfb_softc *, 108 1.17.2.2 jmcneill struct pci_attach_args *); 109 1.17.2.2 jmcneill 110 1.17.2.2 jmcneill static uintmax_t radeonfb_getprop_num(struct radeonfb_softc *, const char *, 111 1.17.2.2 jmcneill uintmax_t); 112 1.17.2.2 jmcneill static int radeonfb_getclocks(struct radeonfb_softc *); 113 1.17.2.2 jmcneill static int radeonfb_gettmds(struct radeonfb_softc *); 114 1.17.2.2 jmcneill static int radeonfb_calc_dividers(struct radeonfb_softc *, uint32_t, 115 1.17.2.2 jmcneill uint32_t *, uint32_t *); 116 1.17.2.2 jmcneill static int radeonfb_getconnectors(struct radeonfb_softc *); 117 1.17.2.2 jmcneill static const struct videomode *radeonfb_modelookup(const char *); 118 1.17.2.2 jmcneill static void radeonfb_init_screen(void *, struct vcons_screen *, int, long *); 119 1.17.2.2 jmcneill static void radeonfb_pllwriteupdate(struct radeonfb_softc *, int); 120 1.17.2.2 jmcneill static void radeonfb_pllwaitatomicread(struct radeonfb_softc *, int); 121 1.17.2.2 jmcneill static void radeonfb_program_vclk(struct radeonfb_softc *, int, int); 122 1.17.2.2 jmcneill static void radeonfb_modeswitch(struct radeonfb_display *); 123 1.17.2.2 jmcneill static void radeonfb_setcrtc(struct radeonfb_display *, int); 124 1.17.2.2 jmcneill static void radeonfb_init_misc(struct radeonfb_softc *); 125 1.17.2.2 jmcneill static void radeonfb_set_fbloc(struct radeonfb_softc *); 126 1.17.2.2 jmcneill static void radeonfb_init_palette(struct radeonfb_softc *, int); 127 1.17.2.2 jmcneill static void radeonfb_r300cg_workaround(struct radeonfb_softc *); 128 1.17.2.2 jmcneill 129 1.17.2.2 jmcneill static int radeonfb_isblank(struct radeonfb_display *); 130 1.17.2.2 jmcneill static void radeonfb_blank(struct radeonfb_display *, int); 131 1.17.2.2 jmcneill static int radeonfb_set_cursor(struct radeonfb_display *, 132 1.17.2.2 jmcneill struct wsdisplay_cursor *); 133 1.17.2.2 jmcneill static int radeonfb_set_curpos(struct radeonfb_display *, 134 1.17.2.2 jmcneill struct wsdisplay_curpos *); 135 1.17.2.2 jmcneill 136 1.17.2.2 jmcneill /* acceleration support */ 137 1.17.2.2 jmcneill static void radeonfb_rectfill(struct radeonfb_display *, int dstx, int dsty, 138 1.17.2.2 jmcneill int width, int height, uint32_t color); 139 1.17.2.2 jmcneill static void radeonfb_bitblt(struct radeonfb_display *, int srcx, int srcy, 140 1.17.2.2 jmcneill int dstx, int dsty, int width, int height, int rop, uint32_t mask); 141 1.17.2.2 jmcneill static void radeonfb_feed_bytes(struct radeonfb_display *, int, uint8_t *); 142 1.17.2.2 jmcneill static void radeonfb_setup_mono(struct radeonfb_display *, int, int, int, 143 1.17.2.2 jmcneill int, uint32_t, uint32_t); 144 1.17.2.2 jmcneill 145 1.17.2.2 jmcneill /* hw cursor support */ 146 1.17.2.2 jmcneill static void radeonfb_cursor_cmap(struct radeonfb_display *); 147 1.17.2.2 jmcneill static void radeonfb_cursor_shape(struct radeonfb_display *); 148 1.17.2.2 jmcneill static void radeonfb_cursor_position(struct radeonfb_display *); 149 1.17.2.2 jmcneill static void radeonfb_cursor_visible(struct radeonfb_display *); 150 1.17.2.2 jmcneill static void radeonfb_cursor_update(struct radeonfb_display *, unsigned); 151 1.17.2.2 jmcneill 152 1.17.2.2 jmcneill static void radeonfb_wait_fifo(struct radeonfb_softc *, int); 153 1.17.2.2 jmcneill static void radeonfb_engine_idle(struct radeonfb_softc *); 154 1.17.2.2 jmcneill static void radeonfb_engine_flush(struct radeonfb_softc *); 155 1.17.2.2 jmcneill static void radeonfb_engine_reset(struct radeonfb_softc *); 156 1.17.2.2 jmcneill static void radeonfb_engine_init(struct radeonfb_display *); 157 1.17.2.2 jmcneill static inline void radeonfb_unclip(struct radeonfb_softc *); 158 1.17.2.2 jmcneill 159 1.17.2.2 jmcneill static void radeonfb_eraserows(void *, int, int, long); 160 1.17.2.2 jmcneill static void radeonfb_erasecols(void *, int, int, int, long); 161 1.17.2.2 jmcneill static void radeonfb_copyrows(void *, int, int, int); 162 1.17.2.2 jmcneill static void radeonfb_copycols(void *, int, int, int, int); 163 1.17.2.2 jmcneill static void radeonfb_cursor(void *, int, int, int); 164 1.17.2.2 jmcneill static void radeonfb_putchar(void *, int, int, unsigned, long); 165 1.17.2.2 jmcneill static int radeonfb_allocattr(void *, int, int, int, long *); 166 1.17.2.2 jmcneill 167 1.17.2.2 jmcneill static int radeonfb_get_backlight(struct radeonfb_display *); 168 1.17.2.2 jmcneill static int radeonfb_set_backlight(struct radeonfb_display *, int); 169 1.17.2.2 jmcneill static void radeonfb_lvds_callout(void *); 170 1.17.2.2 jmcneill 171 1.17.2.2 jmcneill static struct videomode *radeonfb_best_refresh(struct videomode *, 172 1.17.2.2 jmcneill struct videomode *); 173 1.17.2.2 jmcneill static void radeonfb_pickres(struct radeonfb_display *, uint16_t *, 174 1.17.2.2 jmcneill uint16_t *, int); 175 1.17.2.2 jmcneill static const struct videomode *radeonfb_port_mode(struct radeonfb_softc *, 176 1.17.2.2 jmcneill struct radeonfb_port *, int, int); 177 1.17.2.2 jmcneill 178 1.17.2.2 jmcneill static int radeonfb_drm_print(void *, const char *); 179 1.17.2.2 jmcneill 180 1.17.2.2 jmcneill #ifdef RADEON_DEBUG 181 1.17.2.2 jmcneill int radeon_debug = 1; 182 1.17.2.2 jmcneill #define DPRINTF(x) \ 183 1.17.2.2 jmcneill if (radeon_debug) printf x 184 1.17.2.2 jmcneill #define PRINTREG(r) DPRINTF((#r " = %08x\n", GET32(sc, r))) 185 1.17.2.2 jmcneill #define PRINTPLL(r) DPRINTF((#r " = %08x\n", GETPLL(sc, r))) 186 1.17.2.2 jmcneill #else 187 1.17.2.2 jmcneill #define DPRINTF(x) 188 1.17.2.2 jmcneill #define PRINTREG(r) 189 1.17.2.2 jmcneill #define PRINTPLL(r) 190 1.17.2.2 jmcneill #endif 191 1.17.2.2 jmcneill 192 1.17.2.2 jmcneill #define ROUNDUP(x,y) (((x) + ((y) - 1)) & ~((y) - 1)) 193 1.17.2.2 jmcneill 194 1.17.2.2 jmcneill #ifndef RADEON_DEFAULT_MODE 195 1.17.2.2 jmcneill /* any reasonably modern display should handle this */ 196 1.17.2.2 jmcneill #define RADEON_DEFAULT_MODE "1024x768x60" 197 1.17.2.2 jmcneill #endif 198 1.17.2.2 jmcneill 199 1.17.2.2 jmcneill const char *radeonfb_default_mode = RADEON_DEFAULT_MODE; 200 1.17.2.2 jmcneill 201 1.17.2.2 jmcneill static struct { 202 1.17.2.2 jmcneill int size; /* minimum memory size (MB) */ 203 1.17.2.2 jmcneill int maxx; /* maximum x dimension */ 204 1.17.2.2 jmcneill int maxy; /* maximum y dimension */ 205 1.17.2.2 jmcneill int maxbpp; /* maximum bpp */ 206 1.17.2.2 jmcneill int maxdisp; /* maximum logical display count */ 207 1.17.2.2 jmcneill } radeonfb_limits[] = { 208 1.17.2.2 jmcneill { 32, 2048, 1536, 32, 2 }, 209 1.17.2.2 jmcneill { 16, 1600, 1200, 32, 2 }, 210 1.17.2.2 jmcneill { 8, 1600, 1200, 32, 1 }, 211 1.17.2.2 jmcneill { 0, 0, 0, 0, 0 }, 212 1.17.2.2 jmcneill }; 213 1.17.2.2 jmcneill 214 1.17.2.2 jmcneill static struct wsscreen_descr radeonfb_stdscreen = { 215 1.17.2.2 jmcneill "fb", /* name */ 216 1.17.2.2 jmcneill 0, 0, /* ncols, nrows */ 217 1.17.2.2 jmcneill NULL, /* textops */ 218 1.17.2.2 jmcneill 8, 16, /* fontwidth, fontheight */ 219 1.17.2.2 jmcneill WSSCREEN_WSCOLORS, /* capabilities */ 220 1.17.2.2 jmcneill 0, /* modecookie */ 221 1.17.2.2 jmcneill }; 222 1.17.2.2 jmcneill 223 1.17.2.2 jmcneill struct wsdisplay_accessops radeonfb_accessops = { 224 1.17.2.2 jmcneill radeonfb_ioctl, 225 1.17.2.2 jmcneill radeonfb_mmap, 226 1.17.2.2 jmcneill NULL, /* vcons_alloc_screen */ 227 1.17.2.2 jmcneill NULL, /* vcons_free_screen */ 228 1.17.2.2 jmcneill NULL, /* vcons_show_screen */ 229 1.17.2.2 jmcneill NULL, /* load_font */ 230 1.17.2.2 jmcneill NULL, /* pollc */ 231 1.17.2.2 jmcneill NULL, /* scroll */ 232 1.17.2.2 jmcneill }; 233 1.17.2.2 jmcneill 234 1.17.2.2 jmcneill static struct { 235 1.17.2.2 jmcneill uint16_t devid; 236 1.17.2.2 jmcneill uint16_t family; 237 1.17.2.2 jmcneill uint16_t flags; 238 1.17.2.2 jmcneill } radeonfb_devices[] = 239 1.17.2.2 jmcneill { 240 1.17.2.2 jmcneill /* R100 family */ 241 1.17.2.2 jmcneill { PCI_PRODUCT_ATI_RADEON_R100_QD, RADEON_R100, 0 }, 242 1.17.2.2 jmcneill { PCI_PRODUCT_ATI_RADEON_R100_QE, RADEON_R100, 0 }, 243 1.17.2.2 jmcneill { PCI_PRODUCT_ATI_RADEON_R100_QF, RADEON_R100, 0 }, 244 1.17.2.2 jmcneill { PCI_PRODUCT_ATI_RADEON_R100_QG, RADEON_R100, 0 }, 245 1.17.2.2 jmcneill 246 1.17.2.2 jmcneill /* RV100 family */ 247 1.17.2.2 jmcneill { PCI_PRODUCT_ATI_RADEON_RV100_LY, RADEON_RV100, RFB_MOB }, 248 1.17.2.2 jmcneill { PCI_PRODUCT_ATI_RADEON_RV100_LZ, RADEON_RV100, RFB_MOB }, 249 1.17.2.2 jmcneill { PCI_PRODUCT_ATI_RADEON_RV100_QY, RADEON_RV100, 0 }, 250 1.17.2.2 jmcneill { PCI_PRODUCT_ATI_RADEON_RV100_QZ, RADEON_RV100, 0 }, 251 1.17.2.2 jmcneill 252 1.17.2.2 jmcneill /* RS100 family */ 253 1.17.2.2 jmcneill { PCI_PRODUCT_ATI_RADEON_RS100_4136, RADEON_RS100, 0 }, 254 1.17.2.2 jmcneill { PCI_PRODUCT_ATI_RADEON_RS100_4336, RADEON_RS100, RFB_MOB }, 255 1.17.2.2 jmcneill 256 1.17.2.2 jmcneill /* RS200/RS250 family */ 257 1.17.2.2 jmcneill { PCI_PRODUCT_ATI_RADEON_RS200_4337, RADEON_RS200, RFB_MOB }, 258 1.17.2.2 jmcneill { PCI_PRODUCT_ATI_RADEON_RS200_A7, RADEON_RS200, 0 }, 259 1.17.2.2 jmcneill { PCI_PRODUCT_ATI_RADEON_RS250_B7, RADEON_RS200, RFB_MOB }, 260 1.17.2.2 jmcneill { PCI_PRODUCT_ATI_RADEON_RS250_D7, RADEON_RS200, 0 }, 261 1.17.2.2 jmcneill 262 1.17.2.2 jmcneill /* R200 family */ 263 1.17.2.2 jmcneill /* add more R200 products? , 5148 */ 264 1.17.2.2 jmcneill { PCI_PRODUCT_ATI_RADEON_R200_BB, RADEON_R200, 0 }, 265 1.17.2.2 jmcneill { PCI_PRODUCT_ATI_RADEON_R200_BC, RADEON_R200, 0 }, 266 1.17.2.2 jmcneill { PCI_PRODUCT_ATI_RADEON_R200_QH, RADEON_R200, 0 }, 267 1.17.2.2 jmcneill { PCI_PRODUCT_ATI_RADEON_R200_QL, RADEON_R200, 0 }, 268 1.17.2.2 jmcneill { PCI_PRODUCT_ATI_RADEON_R200_QM, RADEON_R200, 0 }, 269 1.17.2.2 jmcneill 270 1.17.2.2 jmcneill /* RV200 family */ 271 1.17.2.2 jmcneill { PCI_PRODUCT_ATI_RADEON_RV200_LW, RADEON_RV200, RFB_MOB }, 272 1.17.2.2 jmcneill { PCI_PRODUCT_ATI_RADEON_RV200_LX, RADEON_RV200, RFB_MOB }, 273 1.17.2.2 jmcneill { PCI_PRODUCT_ATI_RADEON_RV200_QW, RADEON_RV200, 0 }, 274 1.17.2.2 jmcneill { PCI_PRODUCT_ATI_RADEON_RV200_QX, RADEON_RV200, 0 }, 275 1.17.2.2 jmcneill 276 1.17.2.2 jmcneill /* RV250 family */ 277 1.17.2.2 jmcneill { PCI_PRODUCT_ATI_RADEON_RV250_4966, RADEON_RV250, 0 }, 278 1.17.2.2 jmcneill { PCI_PRODUCT_ATI_RADEON_RV250_4967, RADEON_RV250, 0 }, 279 1.17.2.2 jmcneill { PCI_PRODUCT_ATI_RADEON_RV250_4C64, RADEON_RV250, RFB_MOB }, 280 1.17.2.2 jmcneill { PCI_PRODUCT_ATI_RADEON_RV250_4C66, RADEON_RV250, RFB_MOB }, 281 1.17.2.2 jmcneill { PCI_PRODUCT_ATI_RADEON_RV250_4C67, RADEON_RV250, RFB_MOB }, 282 1.17.2.2 jmcneill 283 1.17.2.2 jmcneill /* RS300 family */ 284 1.17.2.2 jmcneill { PCI_PRODUCT_ATI_RADEON_RS300_X5, RADEON_RS300, 0 }, 285 1.17.2.2 jmcneill { PCI_PRODUCT_ATI_RADEON_RS300_X4, RADEON_RS300, 0 }, 286 1.17.2.2 jmcneill { PCI_PRODUCT_ATI_RADEON_RS300_7834, RADEON_RS300, 0 }, 287 1.17.2.2 jmcneill { PCI_PRODUCT_ATI_RADEON_RS300_7835, RADEON_RS300, RFB_MOB }, 288 1.17.2.2 jmcneill 289 1.17.2.2 jmcneill /* RV280 family */ 290 1.17.2.2 jmcneill { PCI_PRODUCT_ATI_RADEON_RV280_5960, RADEON_RV280, 0 }, 291 1.17.2.2 jmcneill { PCI_PRODUCT_ATI_RADEON_RV280_5961, RADEON_RV280, 0 }, 292 1.17.2.2 jmcneill { PCI_PRODUCT_ATI_RADEON_RV280_5962, RADEON_RV280, 0 }, 293 1.17.2.2 jmcneill { PCI_PRODUCT_ATI_RADEON_RV280_5963, RADEON_RV280, 0 }, 294 1.17.2.2 jmcneill { PCI_PRODUCT_ATI_RADEON_RV280_5964, RADEON_RV280, 0 }, 295 1.17.2.2 jmcneill { PCI_PRODUCT_ATI_RADEON_RV280_5C61, RADEON_RV280, RFB_MOB }, 296 1.17.2.2 jmcneill { PCI_PRODUCT_ATI_RADEON_RV280_5C63, RADEON_RV280, RFB_MOB }, 297 1.17.2.2 jmcneill 298 1.17.2.2 jmcneill /* R300 family */ 299 1.17.2.2 jmcneill { PCI_PRODUCT_ATI_RADEON_R300_AD, RADEON_R300, 0 }, 300 1.17.2.2 jmcneill { PCI_PRODUCT_ATI_RADEON_R300_AE, RADEON_R300, 0 }, 301 1.17.2.2 jmcneill { PCI_PRODUCT_ATI_RADEON_R300_AF, RADEON_R300, 0 }, 302 1.17.2.2 jmcneill { PCI_PRODUCT_ATI_RADEON_R300_AG, RADEON_R300, 0 }, 303 1.17.2.2 jmcneill { PCI_PRODUCT_ATI_RADEON_R300_ND, RADEON_R300, 0 }, 304 1.17.2.2 jmcneill { PCI_PRODUCT_ATI_RADEON_R300_NE, RADEON_R300, 0 }, 305 1.17.2.2 jmcneill { PCI_PRODUCT_ATI_RADEON_R300_NF, RADEON_R300, 0 }, 306 1.17.2.2 jmcneill { PCI_PRODUCT_ATI_RADEON_R300_NG, RADEON_R300, 0 }, 307 1.17.2.2 jmcneill 308 1.17.2.2 jmcneill /* RV350/RV360 family */ 309 1.17.2.2 jmcneill { PCI_PRODUCT_ATI_RADEON_RV350_AP, RADEON_RV350, 0 }, 310 1.17.2.2 jmcneill { PCI_PRODUCT_ATI_RADEON_RV350_AQ, RADEON_RV350, 0 }, 311 1.17.2.2 jmcneill { PCI_PRODUCT_ATI_RADEON_RV360_AR, RADEON_RV350, 0 }, 312 1.17.2.2 jmcneill { PCI_PRODUCT_ATI_RADEON_RV350_AS, RADEON_RV350, 0 }, 313 1.17.2.2 jmcneill { PCI_PRODUCT_ATI_RADEON_RV350_AT, RADEON_RV350, 0 }, 314 1.17.2.2 jmcneill { PCI_PRODUCT_ATI_RADEON_RV350_AV, RADEON_RV350, 0 }, 315 1.17.2.2 jmcneill { PCI_PRODUCT_ATI_RADEON_RV350_NP, RADEON_RV350, RFB_MOB }, 316 1.17.2.2 jmcneill { PCI_PRODUCT_ATI_RADEON_RV350_NQ, RADEON_RV350, RFB_MOB }, 317 1.17.2.2 jmcneill { PCI_PRODUCT_ATI_RADEON_RV350_NR, RADEON_RV350, RFB_MOB }, 318 1.17.2.2 jmcneill { PCI_PRODUCT_ATI_RADEON_RV350_NS, RADEON_RV350, RFB_MOB }, 319 1.17.2.2 jmcneill { PCI_PRODUCT_ATI_RADEON_RV350_NT, RADEON_RV350, RFB_MOB }, 320 1.17.2.2 jmcneill { PCI_PRODUCT_ATI_RADEON_RV350_NV, RADEON_RV350, RFB_MOB }, 321 1.17.2.2 jmcneill 322 1.17.2.2 jmcneill /* R350/R360 family */ 323 1.17.2.2 jmcneill { PCI_PRODUCT_ATI_RADEON_R350_AH, RADEON_R350, 0 }, 324 1.17.2.2 jmcneill { PCI_PRODUCT_ATI_RADEON_R350_AI, RADEON_R350, 0 }, 325 1.17.2.2 jmcneill { PCI_PRODUCT_ATI_RADEON_R350_AJ, RADEON_R350, 0 }, 326 1.17.2.2 jmcneill { PCI_PRODUCT_ATI_RADEON_R350_AK, RADEON_R350, 0 }, 327 1.17.2.2 jmcneill { PCI_PRODUCT_ATI_RADEON_R350_NH, RADEON_R350, 0 }, 328 1.17.2.2 jmcneill { PCI_PRODUCT_ATI_RADEON_R350_NI, RADEON_R350, 0 }, 329 1.17.2.2 jmcneill { PCI_PRODUCT_ATI_RADEON_R350_NK, RADEON_R350, 0 }, 330 1.17.2.2 jmcneill { PCI_PRODUCT_ATI_RADEON_R360_NJ, RADEON_R350, 0 }, 331 1.17.2.2 jmcneill 332 1.17.2.2 jmcneill /* RV380/RV370 family */ 333 1.17.2.2 jmcneill { PCI_PRODUCT_ATI_RADEON_RV380_3150, RADEON_RV380, RFB_MOB }, 334 1.17.2.2 jmcneill { PCI_PRODUCT_ATI_RADEON_RV380_3154, RADEON_RV380, RFB_MOB }, 335 1.17.2.2 jmcneill { PCI_PRODUCT_ATI_RADEON_RV380_3E50, RADEON_RV380, 0 }, 336 1.17.2.2 jmcneill { PCI_PRODUCT_ATI_RADEON_RV380_3E54, RADEON_RV380, 0 }, 337 1.17.2.2 jmcneill { PCI_PRODUCT_ATI_RADEON_RV370_5460, RADEON_RV380, RFB_MOB }, 338 1.17.2.2 jmcneill { PCI_PRODUCT_ATI_RADEON_RV370_5464, RADEON_RV380, RFB_MOB }, 339 1.17.2.2 jmcneill { PCI_PRODUCT_ATI_RADEON_RV370_5B60, RADEON_RV380, 0 }, 340 1.17.2.2 jmcneill { PCI_PRODUCT_ATI_RADEON_RV370_5B64, RADEON_RV380, 0 }, 341 1.17.2.2 jmcneill { PCI_PRODUCT_ATI_RADEON_RV370_5B65, RADEON_RV380, 0 }, 342 1.17.2.2 jmcneill 343 1.17.2.2 jmcneill /* R420/R423 family */ 344 1.17.2.2 jmcneill { PCI_PRODUCT_ATI_RADEON_R420_JH, RADEON_R420, 0 }, 345 1.17.2.2 jmcneill { PCI_PRODUCT_ATI_RADEON_R420_JI, RADEON_R420, 0 }, 346 1.17.2.2 jmcneill { PCI_PRODUCT_ATI_RADEON_R420_JJ, RADEON_R420, 0 }, 347 1.17.2.2 jmcneill { PCI_PRODUCT_ATI_RADEON_R420_JK, RADEON_R420, 0 }, 348 1.17.2.2 jmcneill { PCI_PRODUCT_ATI_RADEON_R420_JL, RADEON_R420, 0 }, 349 1.17.2.2 jmcneill { PCI_PRODUCT_ATI_RADEON_R420_JM, RADEON_R420, 0 }, 350 1.17.2.2 jmcneill { PCI_PRODUCT_ATI_RADEON_R420_JN, RADEON_R420, RFB_MOB }, 351 1.17.2.2 jmcneill { PCI_PRODUCT_ATI_RADEON_R420_JP, RADEON_R420, 0 }, 352 1.17.2.2 jmcneill { PCI_PRODUCT_ATI_RADEON_R423_UH, RADEON_R420, 0 }, 353 1.17.2.2 jmcneill { PCI_PRODUCT_ATI_RADEON_R423_UI, RADEON_R420, 0 }, 354 1.17.2.2 jmcneill { PCI_PRODUCT_ATI_RADEON_R423_UJ, RADEON_R420, 0 }, 355 1.17.2.2 jmcneill { PCI_PRODUCT_ATI_RADEON_R423_UK, RADEON_R420, 0 }, 356 1.17.2.2 jmcneill { PCI_PRODUCT_ATI_RADEON_R423_UQ, RADEON_R420, 0 }, 357 1.17.2.2 jmcneill { PCI_PRODUCT_ATI_RADEON_R423_UR, RADEON_R420, 0 }, 358 1.17.2.2 jmcneill { PCI_PRODUCT_ATI_RADEON_R423_UT, RADEON_R420, 0 }, 359 1.17.2.2 jmcneill { PCI_PRODUCT_ATI_RADEON_R423_5D57, RADEON_R420, 0 }, 360 1.17.2.4 joerg { PCI_PRODUCT_ATI_RADEON_R430_554F, RADEON_R420, 0 }, 361 1.17.2.2 jmcneill 362 1.17.2.2 jmcneill { 0, 0, 0 } 363 1.17.2.2 jmcneill }; 364 1.17.2.2 jmcneill 365 1.17.2.2 jmcneill static struct { 366 1.17.2.2 jmcneill int divider; 367 1.17.2.2 jmcneill int mask; 368 1.17.2.2 jmcneill } radeonfb_dividers[] = { 369 1.17.2.2 jmcneill { 1, 0 }, 370 1.17.2.2 jmcneill { 2, 1 }, 371 1.17.2.2 jmcneill { 3, 4 }, 372 1.17.2.2 jmcneill { 4, 2 }, 373 1.17.2.2 jmcneill { 6, 6 }, 374 1.17.2.2 jmcneill { 8, 3 }, 375 1.17.2.2 jmcneill { 12, 7 }, 376 1.17.2.2 jmcneill { 0, 0 } 377 1.17.2.2 jmcneill }; 378 1.17.2.2 jmcneill 379 1.17.2.2 jmcneill /* 380 1.17.2.2 jmcneill * This table taken from X11. 381 1.17.2.2 jmcneill */ 382 1.17.2.2 jmcneill static const struct { 383 1.17.2.2 jmcneill int family; 384 1.17.2.2 jmcneill struct radeon_tmds_pll plls[4]; 385 1.17.2.2 jmcneill } radeonfb_tmds_pll[] = { 386 1.17.2.2 jmcneill { RADEON_R100, {{12000, 0xa1b}, {-1, 0xa3f}}}, 387 1.17.2.2 jmcneill { RADEON_RV100, {{12000, 0xa1b}, {-1, 0xa3f}}}, 388 1.17.2.2 jmcneill { RADEON_RS100, {{0, 0}}}, 389 1.17.2.2 jmcneill { RADEON_RV200, {{15000, 0xa1b}, {-1, 0xa3f}}}, 390 1.17.2.2 jmcneill { RADEON_RS200, {{15000, 0xa1b}, {-1, 0xa3f}}}, 391 1.17.2.2 jmcneill { RADEON_R200, {{15000, 0xa1b}, {-1, 0xa3f}}}, 392 1.17.2.2 jmcneill { RADEON_RV250, {{15500, 0x81b}, {-1, 0x83f}}}, 393 1.17.2.2 jmcneill { RADEON_RS300, {{0, 0}}}, 394 1.17.2.2 jmcneill { RADEON_RV280, {{13000, 0x400f4}, {15000, 0x400f7}}}, 395 1.17.2.2 jmcneill { RADEON_R300, {{-1, 0xb01cb}}}, 396 1.17.2.2 jmcneill { RADEON_R350, {{-1, 0xb01cb}}}, 397 1.17.2.2 jmcneill { RADEON_RV350, {{15000, 0xb0155}, {-1, 0xb01cb}}}, 398 1.17.2.2 jmcneill { RADEON_RV380, {{15000, 0xb0155}, {-1, 0xb01cb}}}, 399 1.17.2.2 jmcneill { RADEON_R420, {{-1, 0xb01cb}}}, 400 1.17.2.2 jmcneill }; 401 1.17.2.2 jmcneill 402 1.17.2.2 jmcneill #define RADEONFB_BACKLIGHT_MAX 255 /* Maximum backlight level. */ 403 1.17.2.2 jmcneill 404 1.17.2.2 jmcneill 405 1.17.2.2 jmcneill CFATTACH_DECL(radeonfb, sizeof (struct radeonfb_softc), 406 1.17.2.2 jmcneill radeonfb_match, radeonfb_attach, NULL, NULL); 407 1.17.2.2 jmcneill 408 1.17.2.2 jmcneill static int 409 1.17.2.2 jmcneill radeonfb_match(struct device *parent, struct cfdata *match, void *aux) 410 1.17.2.2 jmcneill { 411 1.17.2.2 jmcneill struct pci_attach_args *pa = aux; 412 1.17.2.2 jmcneill int i; 413 1.17.2.2 jmcneill 414 1.17.2.2 jmcneill if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_ATI) 415 1.17.2.2 jmcneill return 0; 416 1.17.2.2 jmcneill 417 1.17.2.2 jmcneill for (i = 0; radeonfb_devices[i].devid; i++) { 418 1.17.2.2 jmcneill if (PCI_PRODUCT(pa->pa_id) == radeonfb_devices[i].devid) 419 1.17.2.2 jmcneill return 100; /* high to defeat VGA/VESA */ 420 1.17.2.2 jmcneill } 421 1.17.2.2 jmcneill 422 1.17.2.2 jmcneill return 0; 423 1.17.2.2 jmcneill } 424 1.17.2.2 jmcneill 425 1.17.2.2 jmcneill static void 426 1.17.2.2 jmcneill radeonfb_attach(struct device *parent, struct device *dev, void *aux) 427 1.17.2.2 jmcneill { 428 1.17.2.2 jmcneill struct radeonfb_softc *sc = (struct radeonfb_softc *)dev; 429 1.17.2.2 jmcneill struct pci_attach_args *pa = aux; 430 1.17.2.2 jmcneill const char *mptr; 431 1.17.2.2 jmcneill bus_size_t bsz; 432 1.17.2.2 jmcneill pcireg_t screg; 433 1.17.2.2 jmcneill int i, j, fg, bg, ul; 434 1.17.2.2 jmcneill uint32_t v; 435 1.17.2.2 jmcneill 436 1.17.2.2 jmcneill sc->sc_id = pa->pa_id; 437 1.17.2.2 jmcneill for (i = 0; radeonfb_devices[i].devid; i++) { 438 1.17.2.2 jmcneill if (PCI_PRODUCT(sc->sc_id) == radeonfb_devices[i].devid) 439 1.17.2.2 jmcneill break; 440 1.17.2.2 jmcneill } 441 1.17.2.2 jmcneill 442 1.17.2.2 jmcneill pci_devinfo(sc->sc_id, pa->pa_class, 0, sc->sc_devinfo, 443 1.17.2.2 jmcneill sizeof(sc->sc_devinfo)); 444 1.17.2.2 jmcneill 445 1.17.2.2 jmcneill aprint_naive("\n"); 446 1.17.2.2 jmcneill aprint_normal(": %s\n", sc->sc_devinfo); 447 1.17.2.2 jmcneill 448 1.17.2.2 jmcneill DPRINTF((prop_dictionary_externalize(device_properties(dev)))); 449 1.17.2.2 jmcneill 450 1.17.2.2 jmcneill KASSERT(radeonfb_devices[i].devid != 0); 451 1.17.2.2 jmcneill sc->sc_pt = pa->pa_tag; 452 1.17.2.2 jmcneill sc->sc_iot = pa->pa_iot; 453 1.17.2.2 jmcneill sc->sc_pc = pa->pa_pc; 454 1.17.2.2 jmcneill sc->sc_family = radeonfb_devices[i].family; 455 1.17.2.2 jmcneill sc->sc_flags = radeonfb_devices[i].flags; 456 1.17.2.2 jmcneill 457 1.17.2.2 jmcneill /* enable memory and IO access */ 458 1.17.2.2 jmcneill screg = pci_conf_read(sc->sc_pc, sc->sc_pt, PCI_COMMAND_STATUS_REG); 459 1.17.2.2 jmcneill screg |= PCI_FLAGS_IO_ENABLED | PCI_FLAGS_MEM_ENABLED; 460 1.17.2.2 jmcneill pci_conf_write(sc->sc_pc, sc->sc_pt, PCI_COMMAND_STATUS_REG, screg); 461 1.17.2.2 jmcneill 462 1.17.2.2 jmcneill /* 463 1.17.2.2 jmcneill * Some flags are general to entire chip families, and rather 464 1.17.2.2 jmcneill * than clutter up the table with them, we go ahead and set 465 1.17.2.2 jmcneill * them here. 466 1.17.2.2 jmcneill */ 467 1.17.2.2 jmcneill switch (sc->sc_family) { 468 1.17.2.2 jmcneill case RADEON_RS100: 469 1.17.2.2 jmcneill case RADEON_RS200: 470 1.17.2.2 jmcneill sc->sc_flags |= RFB_IGP | RFB_RV100; 471 1.17.2.2 jmcneill break; 472 1.17.2.2 jmcneill 473 1.17.2.2 jmcneill case RADEON_RV100: 474 1.17.2.2 jmcneill case RADEON_RV200: 475 1.17.2.2 jmcneill case RADEON_RV250: 476 1.17.2.2 jmcneill case RADEON_RV280: 477 1.17.2.2 jmcneill sc->sc_flags |= RFB_RV100; 478 1.17.2.2 jmcneill break; 479 1.17.2.2 jmcneill 480 1.17.2.2 jmcneill case RADEON_RS300: 481 1.17.2.2 jmcneill sc->sc_flags |= RFB_SDAC | RFB_IGP | RFB_RV100; 482 1.17.2.2 jmcneill break; 483 1.17.2.2 jmcneill 484 1.17.2.2 jmcneill case RADEON_R300: 485 1.17.2.2 jmcneill case RADEON_RV350: 486 1.17.2.2 jmcneill case RADEON_R350: 487 1.17.2.2 jmcneill case RADEON_RV380: 488 1.17.2.2 jmcneill case RADEON_R420: 489 1.17.2.2 jmcneill /* newer chips */ 490 1.17.2.2 jmcneill sc->sc_flags |= RFB_R300; 491 1.17.2.2 jmcneill break; 492 1.17.2.2 jmcneill 493 1.17.2.2 jmcneill case RADEON_R100: 494 1.17.2.2 jmcneill sc->sc_flags |= RFB_NCRTC2; 495 1.17.2.2 jmcneill break; 496 1.17.2.2 jmcneill } 497 1.17.2.2 jmcneill 498 1.17.2.2 jmcneill if ((sc->sc_family == RADEON_RV200) || 499 1.17.2.2 jmcneill (sc->sc_family == RADEON_RV250) || 500 1.17.2.2 jmcneill (sc->sc_family == RADEON_RV280) || 501 1.17.2.2 jmcneill (sc->sc_family == RADEON_RV350)) { 502 1.17.2.2 jmcneill bool inverted = 0; 503 1.17.2.2 jmcneill /* backlight level is linear */ 504 1.17.2.2 jmcneill DPRINTF(("found RV* chip, backlight is supposedly linear\n")); 505 1.17.2.2 jmcneill prop_dictionary_get_bool(device_properties(&sc->sc_dev), 506 1.17.2.2 jmcneill "backlight_level_reverted", &inverted); 507 1.17.2.2 jmcneill if (inverted) { 508 1.17.2.2 jmcneill DPRINTF(("nope, it's inverted\n")); 509 1.17.2.2 jmcneill sc->sc_flags |= RFB_INV_BLIGHT; 510 1.17.2.2 jmcneill } 511 1.17.2.2 jmcneill } else 512 1.17.2.2 jmcneill sc->sc_flags |= RFB_INV_BLIGHT; 513 1.17.2.2 jmcneill 514 1.17.2.2 jmcneill /* 515 1.17.2.2 jmcneill * XXX: to support true multihead, this must change. 516 1.17.2.2 jmcneill */ 517 1.17.2.2 jmcneill sc->sc_ndisplays = 1; 518 1.17.2.2 jmcneill 519 1.17.2.2 jmcneill /* XXX: */ 520 1.17.2.2 jmcneill if (!HAS_CRTC2(sc)) { 521 1.17.2.2 jmcneill sc->sc_ndisplays = 1; 522 1.17.2.2 jmcneill } 523 1.17.2.2 jmcneill 524 1.17.2.2 jmcneill if (pci_mapreg_map(pa, RADEON_MAPREG_MMIO, PCI_MAPREG_TYPE_MEM, 0, 525 1.17.2.2 jmcneill &sc->sc_regt, &sc->sc_regh, &sc->sc_regaddr, 526 1.17.2.2 jmcneill &sc->sc_regsz) != 0) { 527 1.17.2.2 jmcneill aprint_error("%s: unable to map registers!\n", XNAME(sc)); 528 1.17.2.2 jmcneill goto error; 529 1.17.2.2 jmcneill } 530 1.17.2.2 jmcneill 531 1.17.2.2 jmcneill /* scratch register test... */ 532 1.17.2.2 jmcneill if (radeonfb_scratch_test(sc, RADEON_BIOS_0_SCRATCH, 0x55555555) || 533 1.17.2.2 jmcneill radeonfb_scratch_test(sc, RADEON_BIOS_0_SCRATCH, 0xaaaaaaaa)) { 534 1.17.2.2 jmcneill aprint_error("%s: scratch register test failed!\n", XNAME(sc)); 535 1.17.2.2 jmcneill goto error; 536 1.17.2.2 jmcneill } 537 1.17.2.2 jmcneill 538 1.17.2.2 jmcneill PRINTREG(RADEON_BIOS_4_SCRATCH); 539 1.17.2.2 jmcneill PRINTREG(RADEON_FP_GEN_CNTL); 540 1.17.2.2 jmcneill PRINTREG(RADEON_FP2_GEN_CNTL); 541 1.17.2.2 jmcneill PRINTREG(RADEON_TMDS_CNTL); 542 1.17.2.2 jmcneill PRINTREG(RADEON_TMDS_TRANSMITTER_CNTL); 543 1.17.2.2 jmcneill PRINTREG(RADEON_TMDS_PLL_CNTL); 544 1.17.2.2 jmcneill PRINTREG(RADEON_LVDS_GEN_CNTL); 545 1.17.2.2 jmcneill PRINTREG(RADEON_FP_HORZ_STRETCH); 546 1.17.2.2 jmcneill PRINTREG(RADEON_FP_VERT_STRETCH); 547 1.17.2.2 jmcneill 548 1.17.2.2 jmcneill /* XXX: RV100 specific */ 549 1.17.2.2 jmcneill PUT32(sc, RADEON_TMDS_PLL_CNTL, 0xa27); 550 1.17.2.2 jmcneill 551 1.17.2.2 jmcneill PATCH32(sc, RADEON_TMDS_TRANSMITTER_CNTL, 552 1.17.2.2 jmcneill RADEON_TMDS_TRANSMITTER_PLLEN, 553 1.17.2.2 jmcneill RADEON_TMDS_TRANSMITTER_PLLEN | RADEON_TMDS_TRANSMITTER_PLLRST); 554 1.17.2.2 jmcneill 555 1.17.2.2 jmcneill radeonfb_i2c_init(sc); 556 1.17.2.2 jmcneill 557 1.17.2.2 jmcneill radeonfb_loadbios(sc, pa); 558 1.17.2.2 jmcneill 559 1.17.2.2 jmcneill #ifdef RADEON_BIOS_INIT 560 1.17.2.2 jmcneill if (radeonfb_bios_init(sc)) { 561 1.17.2.2 jmcneill aprint_error("%s: BIOS inititialization failed\n", XNAME(sc)); 562 1.17.2.2 jmcneill goto error; 563 1.17.2.2 jmcneill } 564 1.17.2.2 jmcneill #endif 565 1.17.2.2 jmcneill 566 1.17.2.2 jmcneill if (radeonfb_getclocks(sc)) { 567 1.17.2.2 jmcneill aprint_error("%s: Unable to get reference clocks from BIOS\n", 568 1.17.2.2 jmcneill XNAME(sc)); 569 1.17.2.2 jmcneill goto error; 570 1.17.2.2 jmcneill } 571 1.17.2.2 jmcneill 572 1.17.2.2 jmcneill if (radeonfb_gettmds(sc)) { 573 1.17.2.2 jmcneill aprint_error("%s: Unable to identify TMDS PLL settings\n", 574 1.17.2.2 jmcneill XNAME(sc)); 575 1.17.2.2 jmcneill goto error; 576 1.17.2.2 jmcneill } 577 1.17.2.2 jmcneill 578 1.17.2.2 jmcneill aprint_verbose("%s: refclk = %d.%03d MHz, refdiv = %d " 579 1.17.2.2 jmcneill "minpll = %d, maxpll = %d\n", XNAME(sc), 580 1.17.2.2 jmcneill (int)sc->sc_refclk / 1000, (int)sc->sc_refclk % 1000, 581 1.17.2.2 jmcneill (int)sc->sc_refdiv, (int)sc->sc_minpll, (int)sc->sc_maxpll); 582 1.17.2.2 jmcneill 583 1.17.2.2 jmcneill radeonfb_getconnectors(sc); 584 1.17.2.2 jmcneill 585 1.17.2.2 jmcneill radeonfb_set_fbloc(sc); 586 1.17.2.2 jmcneill 587 1.17.2.2 jmcneill for (i = 0; radeonfb_limits[i].size; i++) { 588 1.17.2.2 jmcneill if (sc->sc_memsz >= radeonfb_limits[i].size) { 589 1.17.2.2 jmcneill sc->sc_maxx = radeonfb_limits[i].maxx; 590 1.17.2.2 jmcneill sc->sc_maxy = radeonfb_limits[i].maxy; 591 1.17.2.2 jmcneill sc->sc_maxbpp = radeonfb_limits[i].maxbpp; 592 1.17.2.2 jmcneill /* framebuffer offset, start at a 4K page */ 593 1.17.2.2 jmcneill sc->sc_fboffset = sc->sc_memsz / 594 1.17.2.2 jmcneill radeonfb_limits[i].maxdisp; 595 1.17.2.2 jmcneill /* 596 1.17.2.2 jmcneill * we use the fbsize to figure out where we can store 597 1.17.2.2 jmcneill * things like cursor data. 598 1.17.2.2 jmcneill */ 599 1.17.2.2 jmcneill sc->sc_fbsize = 600 1.17.2.2 jmcneill ROUNDUP(ROUNDUP(sc->sc_maxx * sc->sc_maxbpp / 8 , 601 1.17.2.2 jmcneill RADEON_STRIDEALIGN) * sc->sc_maxy, 602 1.17.2.2 jmcneill 4096); 603 1.17.2.2 jmcneill break; 604 1.17.2.2 jmcneill } 605 1.17.2.2 jmcneill } 606 1.17.2.2 jmcneill 607 1.17.2.2 jmcneill 608 1.17.2.2 jmcneill radeonfb_init_misc(sc); 609 1.17.2.2 jmcneill radeonfb_init_palette(sc, 0); 610 1.17.2.2 jmcneill if (HAS_CRTC2(sc)) 611 1.17.2.2 jmcneill radeonfb_init_palette(sc, 1); 612 1.17.2.2 jmcneill 613 1.17.2.2 jmcneill /* program the DAC wirings */ 614 1.17.2.2 jmcneill for (i = 0; i < (HAS_CRTC2(sc) ? 2 : 1); i++) { 615 1.17.2.2 jmcneill switch (sc->sc_ports[i].rp_dac_type) { 616 1.17.2.2 jmcneill case RADEON_DAC_PRIMARY: 617 1.17.2.2 jmcneill PATCH32(sc, RADEON_DAC_CNTL2, 618 1.17.2.2 jmcneill i ? RADEON_DAC2_DAC_CLK_SEL : 0, 619 1.17.2.2 jmcneill ~RADEON_DAC2_DAC_CLK_SEL); 620 1.17.2.2 jmcneill break; 621 1.17.2.2 jmcneill case RADEON_DAC_TVDAC: 622 1.17.2.2 jmcneill /* we always use the TVDAC to drive a secondary analog 623 1.17.2.2 jmcneill * CRT for now. if we ever support TV-out this will 624 1.17.2.2 jmcneill * have to change. 625 1.17.2.2 jmcneill */ 626 1.17.2.2 jmcneill SET32(sc, RADEON_DAC_CNTL2, 627 1.17.2.2 jmcneill RADEON_DAC2_DAC2_CLK_SEL); 628 1.17.2.2 jmcneill PATCH32(sc, RADEON_DISP_HW_DEBUG, 629 1.17.2.2 jmcneill i ? 0 : RADEON_CRT2_DISP1_SEL, 630 1.17.2.2 jmcneill ~RADEON_CRT2_DISP1_SEL); 631 1.17.2.2 jmcneill break; 632 1.17.2.2 jmcneill } 633 1.17.2.2 jmcneill } 634 1.17.2.2 jmcneill PRINTREG(RADEON_DAC_CNTL2); 635 1.17.2.2 jmcneill PRINTREG(RADEON_DISP_HW_DEBUG); 636 1.17.2.2 jmcneill 637 1.17.2.2 jmcneill /* other DAC programming */ 638 1.17.2.2 jmcneill v = GET32(sc, RADEON_DAC_CNTL); 639 1.17.2.2 jmcneill v &= (RADEON_DAC_RANGE_CNTL_MASK | RADEON_DAC_BLANKING); 640 1.17.2.2 jmcneill v |= RADEON_DAC_MASK_ALL | RADEON_DAC_8BIT_EN; 641 1.17.2.2 jmcneill PUT32(sc, RADEON_DAC_CNTL, v); 642 1.17.2.2 jmcneill PRINTREG(RADEON_DAC_CNTL); 643 1.17.2.2 jmcneill 644 1.17.2.2 jmcneill /* XXX: this may need more investigation */ 645 1.17.2.2 jmcneill PUT32(sc, RADEON_TV_DAC_CNTL, 0x00280203); 646 1.17.2.2 jmcneill PRINTREG(RADEON_TV_DAC_CNTL); 647 1.17.2.2 jmcneill 648 1.17.2.2 jmcneill /* enable TMDS */ 649 1.17.2.2 jmcneill SET32(sc, RADEON_FP_GEN_CNTL, 650 1.17.2.2 jmcneill RADEON_FP_TMDS_EN | 651 1.17.2.2 jmcneill RADEON_FP_CRTC_DONT_SHADOW_VPAR | 652 1.17.2.2 jmcneill RADEON_FP_CRTC_DONT_SHADOW_HEND); 653 1.17.2.2 jmcneill CLR32(sc, RADEON_FP_GEN_CNTL, RADEON_FP_SEL_CRTC2); 654 1.17.2.2 jmcneill if (HAS_CRTC2(sc)) 655 1.17.2.2 jmcneill SET32(sc, RADEON_FP2_GEN_CNTL, RADEON_FP2_SRC_SEL_CRTC2); 656 1.17.2.2 jmcneill 657 1.17.2.2 jmcneill /* 658 1.17.2.2 jmcneill * we use bus_space_map instead of pci_mapreg, because we don't 659 1.17.2.2 jmcneill * need the full aperature space. no point in wasting virtual 660 1.17.2.2 jmcneill * address space we don't intend to use, right? 661 1.17.2.2 jmcneill */ 662 1.17.2.2 jmcneill if ((sc->sc_memsz < (4096 * 1024)) || 663 1.17.2.2 jmcneill (pci_mapreg_info(sc->sc_pc, sc->sc_pt, RADEON_MAPREG_VRAM, 664 1.17.2.2 jmcneill PCI_MAPREG_TYPE_MEM, &sc->sc_memaddr, &bsz, NULL) != 0) || 665 1.17.2.2 jmcneill (bsz < sc->sc_memsz)) { 666 1.17.2.2 jmcneill sc->sc_memsz = 0; 667 1.17.2.2 jmcneill aprint_error("%s: Bad frame buffer configuration\n", 668 1.17.2.2 jmcneill XNAME(sc)); 669 1.17.2.2 jmcneill goto error; 670 1.17.2.2 jmcneill } 671 1.17.2.2 jmcneill 672 1.17.2.2 jmcneill /* 64 MB should be enough -- more just wastes map entries */ 673 1.17.2.2 jmcneill if (sc->sc_memsz > (64 << 20)) 674 1.17.2.2 jmcneill sc->sc_memsz = (64 << 20); 675 1.17.2.2 jmcneill 676 1.17.2.2 jmcneill sc->sc_memt = pa->pa_memt; 677 1.17.2.2 jmcneill if (bus_space_map(sc->sc_memt, sc->sc_memaddr, sc->sc_memsz, 678 1.17.2.2 jmcneill BUS_SPACE_MAP_LINEAR, &sc->sc_memh) != 0) { 679 1.17.2.2 jmcneill sc->sc_memsz = 0; 680 1.17.2.2 jmcneill aprint_error("%s: Unable to map frame buffer\n", XNAME(sc)); 681 1.17.2.2 jmcneill goto error; 682 1.17.2.2 jmcneill } 683 1.17.2.2 jmcneill 684 1.17.2.2 jmcneill aprint_normal("%s: %d MB aperture at 0x%08x, " 685 1.17.2.2 jmcneill "%d KB registers at 0x%08x\n", XNAME(sc), 686 1.17.2.2 jmcneill (int)sc->sc_memsz >> 20, (unsigned)sc->sc_memaddr, 687 1.17.2.2 jmcneill (int)sc->sc_regsz >> 10, (unsigned)sc->sc_regaddr); 688 1.17.2.2 jmcneill 689 1.17.2.2 jmcneill /* setup default video mode from devprop (allows PROM override) */ 690 1.17.2.2 jmcneill sc->sc_defaultmode = radeonfb_default_mode; 691 1.17.2.2 jmcneill if (prop_dictionary_get_cstring_nocopy(device_properties(&sc->sc_dev), 692 1.17.2.2 jmcneill "videomode", &mptr)) { 693 1.17.2.2 jmcneill 694 1.17.2.2 jmcneill strncpy(sc->sc_modebuf, mptr, sizeof(sc->sc_modebuf)); 695 1.17.2.2 jmcneill sc->sc_defaultmode = sc->sc_modebuf; 696 1.17.2.2 jmcneill } 697 1.17.2.2 jmcneill 698 1.17.2.2 jmcneill /* initialize some basic display parameters */ 699 1.17.2.2 jmcneill for (i = 0; i < sc->sc_ndisplays; i++) { 700 1.17.2.2 jmcneill struct radeonfb_display *dp = &sc->sc_displays[i]; 701 1.17.2.2 jmcneill struct rasops_info *ri; 702 1.17.2.2 jmcneill long defattr; 703 1.17.2.2 jmcneill struct wsemuldisplaydev_attach_args aa; 704 1.17.2.2 jmcneill 705 1.17.2.2 jmcneill /* 706 1.17.2.2 jmcneill * Figure out how many "displays" (desktops) we are going to 707 1.17.2.2 jmcneill * support. If more than one, then each CRTC gets its own 708 1.17.2.2 jmcneill * programming. 709 1.17.2.2 jmcneill * 710 1.17.2.2 jmcneill * XXX: this code needs to change to support mergedfb. 711 1.17.2.2 jmcneill * XXX: would be nice to allow this to be overridden 712 1.17.2.2 jmcneill */ 713 1.17.2.2 jmcneill if (HAS_CRTC2(sc) && (sc->sc_ndisplays == 1)) { 714 1.17.2.2 jmcneill DPRINTF(("dual crtcs!\n")); 715 1.17.2.2 jmcneill dp->rd_ncrtcs = 2; 716 1.17.2.2 jmcneill dp->rd_crtcs[0].rc_number = 0; 717 1.17.2.2 jmcneill dp->rd_crtcs[1].rc_number = 1; 718 1.17.2.2 jmcneill } else { 719 1.17.2.2 jmcneill dp->rd_ncrtcs = 1; 720 1.17.2.2 jmcneill dp->rd_crtcs[0].rc_number = i; 721 1.17.2.2 jmcneill } 722 1.17.2.2 jmcneill 723 1.17.2.2 jmcneill /* set up port pointer */ 724 1.17.2.2 jmcneill for (j = 0; j < dp->rd_ncrtcs; j++) { 725 1.17.2.2 jmcneill dp->rd_crtcs[j].rc_port = 726 1.17.2.2 jmcneill &sc->sc_ports[dp->rd_crtcs[j].rc_number]; 727 1.17.2.2 jmcneill } 728 1.17.2.2 jmcneill 729 1.17.2.2 jmcneill dp->rd_softc = sc; 730 1.17.2.2 jmcneill dp->rd_wsmode = WSDISPLAYIO_MODE_EMUL; 731 1.17.2.2 jmcneill dp->rd_bg = WS_DEFAULT_BG; 732 1.17.2.2 jmcneill #if 0 733 1.17.2.2 jmcneill dp->rd_bpp = sc->sc_maxbpp; /* XXX: for now */ 734 1.17.2.2 jmcneill #else 735 1.17.2.2 jmcneill dp->rd_bpp = RADEONFB_DEFAULT_DEPTH; /* XXX */ 736 1.17.2.2 jmcneill #endif 737 1.17.2.2 jmcneill /* for text mode, we pick a resolution that won't 738 1.17.2.2 jmcneill * require panning */ 739 1.17.2.2 jmcneill radeonfb_pickres(dp, &dp->rd_virtx, &dp->rd_virty, 0); 740 1.17.2.2 jmcneill 741 1.17.2.2 jmcneill aprint_normal("%s: display %d: " 742 1.17.2.2 jmcneill "initial virtual resolution %dx%d at %d bpp\n", 743 1.17.2.2 jmcneill XNAME(sc), i, dp->rd_virtx, dp->rd_virty, dp->rd_bpp); 744 1.17.2.2 jmcneill 745 1.17.2.2 jmcneill /* now select the *video mode* that we will use */ 746 1.17.2.2 jmcneill for (j = 0; j < dp->rd_ncrtcs; j++) { 747 1.17.2.2 jmcneill const struct videomode *vmp; 748 1.17.2.2 jmcneill vmp = radeonfb_port_mode(sc, dp->rd_crtcs[j].rc_port, 749 1.17.2.2 jmcneill dp->rd_virtx, dp->rd_virty); 750 1.17.2.2 jmcneill 751 1.17.2.2 jmcneill /* 752 1.17.2.2 jmcneill * virtual resolution should be at least as high as 753 1.17.2.2 jmcneill * physical 754 1.17.2.2 jmcneill */ 755 1.17.2.2 jmcneill if (dp->rd_virtx < vmp->hdisplay || 756 1.17.2.2 jmcneill dp->rd_virty < vmp->vdisplay) { 757 1.17.2.2 jmcneill dp->rd_virtx = vmp->hdisplay; 758 1.17.2.2 jmcneill dp->rd_virty = vmp->vdisplay; 759 1.17.2.2 jmcneill } 760 1.17.2.2 jmcneill 761 1.17.2.2 jmcneill dp->rd_crtcs[j].rc_videomode = *vmp; 762 1.17.2.2 jmcneill printf("%s: port %d: physical %dx%d %dHz\n", 763 1.17.2.2 jmcneill XNAME(sc), j, vmp->hdisplay, vmp->vdisplay, 764 1.17.2.2 jmcneill DIVIDE(DIVIDE(vmp->dot_clock * 1000, 765 1.17.2.2 jmcneill vmp->htotal), vmp->vtotal)); 766 1.17.2.2 jmcneill } 767 1.17.2.2 jmcneill 768 1.17.2.2 jmcneill /* N.B.: radeon wants 64-byte aligned stride */ 769 1.17.2.2 jmcneill dp->rd_stride = dp->rd_virtx * dp->rd_bpp / 8; 770 1.17.2.2 jmcneill dp->rd_stride = ROUNDUP(dp->rd_stride, RADEON_STRIDEALIGN); 771 1.17.2.2 jmcneill 772 1.17.2.2 jmcneill dp->rd_offset = sc->sc_fboffset * i; 773 1.17.2.2 jmcneill dp->rd_fbptr = (vaddr_t)bus_space_vaddr(sc->sc_memt, 774 1.17.2.2 jmcneill sc->sc_memh) + dp->rd_offset; 775 1.17.2.2 jmcneill dp->rd_curoff = sc->sc_fbsize; 776 1.17.2.2 jmcneill dp->rd_curptr = dp->rd_fbptr + dp->rd_curoff; 777 1.17.2.2 jmcneill 778 1.17.2.2 jmcneill DPRINTF(("fpbtr = %p\n", (void *)dp->rd_fbptr)); 779 1.17.2.2 jmcneill 780 1.17.2.2 jmcneill switch (dp->rd_bpp) { 781 1.17.2.2 jmcneill case 8: 782 1.17.2.2 jmcneill dp->rd_format = 2; 783 1.17.2.2 jmcneill break; 784 1.17.2.2 jmcneill case 32: 785 1.17.2.2 jmcneill dp->rd_format = 6; 786 1.17.2.2 jmcneill break; 787 1.17.2.2 jmcneill default: 788 1.17.2.2 jmcneill aprint_error("%s: bad depth %d\n", XNAME(sc), 789 1.17.2.2 jmcneill dp->rd_bpp); 790 1.17.2.2 jmcneill goto error; 791 1.17.2.2 jmcneill } 792 1.17.2.2 jmcneill 793 1.17.2.2 jmcneill printf("init engine\n"); 794 1.17.2.2 jmcneill /* XXX: this seems suspicious - per display engine 795 1.17.2.2 jmcneill initialization? */ 796 1.17.2.2 jmcneill radeonfb_engine_init(dp); 797 1.17.2.2 jmcneill 798 1.17.2.2 jmcneill /* copy the template into place */ 799 1.17.2.2 jmcneill dp->rd_wsscreens_storage[0] = radeonfb_stdscreen; 800 1.17.2.2 jmcneill dp->rd_wsscreens = dp->rd_wsscreens_storage; 801 1.17.2.2 jmcneill 802 1.17.2.2 jmcneill /* and make up the list */ 803 1.17.2.2 jmcneill dp->rd_wsscreenlist.nscreens = 1; 804 1.17.2.2 jmcneill dp->rd_wsscreenlist.screens = 805 1.17.2.2 jmcneill (const struct wsscreen_descr **)&dp->rd_wsscreens; 806 1.17.2.2 jmcneill 807 1.17.2.2 jmcneill vcons_init(&dp->rd_vd, dp, dp->rd_wsscreens, 808 1.17.2.2 jmcneill &radeonfb_accessops); 809 1.17.2.2 jmcneill 810 1.17.2.2 jmcneill dp->rd_vd.init_screen = radeonfb_init_screen; 811 1.17.2.2 jmcneill 812 1.17.2.2 jmcneill dp->rd_console = 1; 813 1.17.2.2 jmcneill 814 1.17.2.2 jmcneill dp->rd_vscreen.scr_flags |= VCONS_SCREEN_IS_STATIC; 815 1.17.2.2 jmcneill 816 1.17.2.2 jmcneill 817 1.17.2.2 jmcneill vcons_init_screen(&dp->rd_vd, &dp->rd_vscreen, 818 1.17.2.2 jmcneill dp->rd_console, &defattr); 819 1.17.2.2 jmcneill 820 1.17.2.2 jmcneill ri = &dp->rd_vscreen.scr_ri; 821 1.17.2.2 jmcneill 822 1.17.2.2 jmcneill /* clear the screen */ 823 1.17.2.2 jmcneill rasops_unpack_attr(defattr, &fg, &bg, &ul); 824 1.17.2.2 jmcneill radeonfb_rectfill(dp, 0, 0, ri->ri_width, ri->ri_height, 825 1.17.2.2 jmcneill ri->ri_devcmap[bg & 0xf]); 826 1.17.2.2 jmcneill 827 1.17.2.2 jmcneill dp->rd_wsscreens->textops = &ri->ri_ops; 828 1.17.2.2 jmcneill dp->rd_wsscreens->capabilities = ri->ri_caps; 829 1.17.2.2 jmcneill dp->rd_wsscreens->nrows = ri->ri_rows; 830 1.17.2.2 jmcneill dp->rd_wsscreens->ncols = ri->ri_cols; 831 1.17.2.2 jmcneill 832 1.17.2.2 jmcneill #ifdef SPLASHSCREEN 833 1.17.2.2 jmcneill dp->rd_splash.si_depth = ri->ri_depth; 834 1.17.2.2 jmcneill dp->rd_splash.si_bits = ri->ri_bits; 835 1.17.2.2 jmcneill dp->rd_splash.si_hwbits = ri->ri_hwbits; 836 1.17.2.2 jmcneill dp->rd_splash.si_width = ri->ri_width; 837 1.17.2.2 jmcneill dp->rd_splash.si_height = ri->ri_height; 838 1.17.2.2 jmcneill dp->rd_splash.si_stride = ri->ri_stride; 839 1.17.2.2 jmcneill dp->rd_splash.si_fillrect = NULL; 840 1.17.2.2 jmcneill #endif 841 1.17.2.2 jmcneill if (dp->rd_console) { 842 1.17.2.2 jmcneill 843 1.17.2.2 jmcneill wsdisplay_cnattach(dp->rd_wsscreens, ri, 0, 0, 844 1.17.2.2 jmcneill defattr); 845 1.17.2.2 jmcneill #ifdef SPLASHSCREEN 846 1.17.2.2 jmcneill splash_render(&dp->rd_splash, 847 1.17.2.2 jmcneill SPLASH_F_CENTER|SPLASH_F_FILL); 848 1.17.2.2 jmcneill #endif 849 1.17.2.2 jmcneill 850 1.17.2.2 jmcneill #ifdef SPLASHSCREEN_PROGRESS 851 1.17.2.2 jmcneill dp->rd_progress.sp_top = (dp->rd_virty / 8) * 7; 852 1.17.2.2 jmcneill dp->rd_progress.sp_width = (dp->rd_virtx / 4) * 3; 853 1.17.2.2 jmcneill dp->rd_progress.sp_left = (dp->rd_virtx - 854 1.17.2.2 jmcneill dp->rd_progress.sp_width) / 2; 855 1.17.2.2 jmcneill dp->rd_progress.sp_height = 20; 856 1.17.2.2 jmcneill dp->rd_progress.sp_state = -1; 857 1.17.2.2 jmcneill dp->rd_progress.sp_si = &dp->rd_splash; 858 1.17.2.2 jmcneill splash_progress_init(&dp->rd_progress); 859 1.17.2.2 jmcneill SCREEN_DISABLE_DRAWING(&dp->rd_vscreen); 860 1.17.2.2 jmcneill #endif 861 1.17.2.2 jmcneill 862 1.17.2.2 jmcneill } else { 863 1.17.2.2 jmcneill 864 1.17.2.2 jmcneill /* 865 1.17.2.2 jmcneill * since we're not the console we can postpone 866 1.17.2.2 jmcneill * the rest until someone actually allocates a 867 1.17.2.2 jmcneill * screen for us. but we do clear the screen 868 1.17.2.2 jmcneill * at least. 869 1.17.2.2 jmcneill */ 870 1.17.2.2 jmcneill memset(ri->ri_bits, 0, 1024); 871 1.17.2.2 jmcneill 872 1.17.2.2 jmcneill radeonfb_modeswitch(dp); 873 1.17.2.2 jmcneill #ifdef SPLASHSCREEN 874 1.17.2.2 jmcneill splash_render(&dp->rd_splash, 875 1.17.2.2 jmcneill SPLASH_F_CENTER|SPLASH_F_FILL); 876 1.17.2.2 jmcneill SCREEN_DISABLE_DRAWING(&dp->rd_vscreen); 877 1.17.2.2 jmcneill #endif 878 1.17.2.2 jmcneill } 879 1.17.2.2 jmcneill 880 1.17.2.2 jmcneill aa.console = dp->rd_console; 881 1.17.2.2 jmcneill aa.scrdata = &dp->rd_wsscreenlist; 882 1.17.2.2 jmcneill aa.accessops = &radeonfb_accessops; 883 1.17.2.2 jmcneill aa.accesscookie = &dp->rd_vd; 884 1.17.2.2 jmcneill 885 1.17.2.2 jmcneill config_found(&sc->sc_dev, &aa, wsemuldisplaydevprint); 886 1.17.2.2 jmcneill radeonfb_blank(dp, 0); 887 1.17.2.2 jmcneill 888 1.17.2.2 jmcneill /* Initialise delayed lvds operations for backlight. */ 889 1.17.2.2 jmcneill callout_init(&dp->rd_bl_lvds_co, 0); 890 1.17.2.2 jmcneill callout_setfunc(&dp->rd_bl_lvds_co, 891 1.17.2.2 jmcneill radeonfb_lvds_callout, dp); 892 1.17.2.2 jmcneill } 893 1.17.2.2 jmcneill 894 1.17.2.2 jmcneill config_found_ia(dev, "drm", aux, radeonfb_drm_print); 895 1.17.2.2 jmcneill 896 1.17.2.2 jmcneill return; 897 1.17.2.2 jmcneill 898 1.17.2.2 jmcneill error: 899 1.17.2.2 jmcneill if (sc->sc_biossz) 900 1.17.2.2 jmcneill free(sc->sc_bios, M_DEVBUF); 901 1.17.2.2 jmcneill 902 1.17.2.2 jmcneill if (sc->sc_regsz) 903 1.17.2.2 jmcneill bus_space_unmap(sc->sc_regt, sc->sc_regh, sc->sc_regsz); 904 1.17.2.2 jmcneill 905 1.17.2.2 jmcneill if (sc->sc_memsz) 906 1.17.2.2 jmcneill bus_space_unmap(sc->sc_memt, sc->sc_memh, sc->sc_memsz); 907 1.17.2.2 jmcneill } 908 1.17.2.2 jmcneill 909 1.17.2.2 jmcneill static int 910 1.17.2.2 jmcneill radeonfb_drm_print(void *aux, const char *pnp) 911 1.17.2.2 jmcneill { 912 1.17.2.2 jmcneill if (pnp) 913 1.17.2.2 jmcneill aprint_normal("direct rendering for %s", pnp); 914 1.17.2.2 jmcneill return (UNSUPP); 915 1.17.2.2 jmcneill } 916 1.17.2.2 jmcneill 917 1.17.2.2 jmcneill int 918 1.17.2.2 jmcneill radeonfb_ioctl(void *v, void *vs, 919 1.17.2.2 jmcneill unsigned long cmd, void *d, int flag, struct lwp *l) 920 1.17.2.2 jmcneill { 921 1.17.2.2 jmcneill struct vcons_data *vd; 922 1.17.2.2 jmcneill struct radeonfb_display *dp; 923 1.17.2.2 jmcneill struct radeonfb_softc *sc; 924 1.17.2.2 jmcneill struct wsdisplay_param *param; 925 1.17.2.2 jmcneill 926 1.17.2.2 jmcneill vd = (struct vcons_data *)v; 927 1.17.2.2 jmcneill dp = (struct radeonfb_display *)vd->cookie; 928 1.17.2.2 jmcneill sc = dp->rd_softc; 929 1.17.2.2 jmcneill 930 1.17.2.2 jmcneill switch (cmd) { 931 1.17.2.2 jmcneill case WSDISPLAYIO_GTYPE: 932 1.17.2.2 jmcneill *(unsigned *)d = WSDISPLAY_TYPE_PCIMISC; 933 1.17.2.2 jmcneill return 0; 934 1.17.2.2 jmcneill 935 1.17.2.2 jmcneill case WSDISPLAYIO_GINFO: 936 1.17.2.2 jmcneill if (vd->active != NULL) { 937 1.17.2.2 jmcneill struct wsdisplay_fbinfo *fb; 938 1.17.2.2 jmcneill fb = (struct wsdisplay_fbinfo *)d; 939 1.17.2.2 jmcneill fb->width = dp->rd_virtx; 940 1.17.2.2 jmcneill fb->height = dp->rd_virty; 941 1.17.2.2 jmcneill fb->depth = dp->rd_bpp; 942 1.17.2.2 jmcneill fb->cmsize = 256; 943 1.17.2.2 jmcneill return 0; 944 1.17.2.2 jmcneill } else 945 1.17.2.2 jmcneill return ENODEV; 946 1.17.2.2 jmcneill case WSDISPLAYIO_GVIDEO: 947 1.17.2.2 jmcneill if (radeonfb_isblank(dp)) 948 1.17.2.2 jmcneill *(unsigned *)d = WSDISPLAYIO_VIDEO_OFF; 949 1.17.2.2 jmcneill else 950 1.17.2.2 jmcneill *(unsigned *)d = WSDISPLAYIO_VIDEO_ON; 951 1.17.2.2 jmcneill return 0; 952 1.17.2.2 jmcneill 953 1.17.2.2 jmcneill case WSDISPLAYIO_SVIDEO: 954 1.17.2.2 jmcneill radeonfb_blank(dp, 955 1.17.2.2 jmcneill (*(unsigned int *)d == WSDISPLAYIO_VIDEO_OFF)); 956 1.17.2.2 jmcneill return 0; 957 1.17.2.2 jmcneill 958 1.17.2.2 jmcneill case WSDISPLAYIO_GETCMAP: 959 1.17.2.2 jmcneill #if 0 960 1.17.2.2 jmcneill if (dp->rd_bpp == 8) 961 1.17.2.2 jmcneill return radeonfb_getcmap(sc, 962 1.17.2.2 jmcneill (struct wsdisplay_cmap *)d); 963 1.17.2.2 jmcneill #endif 964 1.17.2.2 jmcneill return EINVAL; 965 1.17.2.2 jmcneill 966 1.17.2.2 jmcneill case WSDISPLAYIO_PUTCMAP: 967 1.17.2.2 jmcneill #if 0 968 1.17.2.2 jmcneill if (dp->rd_bpp == 8) 969 1.17.2.2 jmcneill return radeonfb_putcmap(sc, 970 1.17.2.2 jmcneill (struct wsdisplay_cmap *)d); 971 1.17.2.2 jmcneill #endif 972 1.17.2.2 jmcneill return EINVAL; 973 1.17.2.2 jmcneill 974 1.17.2.2 jmcneill case WSDISPLAYIO_LINEBYTES: 975 1.17.2.2 jmcneill *(unsigned *)d = dp->rd_stride; 976 1.17.2.2 jmcneill return 0; 977 1.17.2.2 jmcneill 978 1.17.2.2 jmcneill case WSDISPLAYIO_SMODE: 979 1.17.2.2 jmcneill if (*(int *)d != dp->rd_wsmode) { 980 1.17.2.2 jmcneill dp->rd_wsmode = *(int *)d; 981 1.17.2.2 jmcneill if ((dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) && 982 1.17.2.2 jmcneill (dp->rd_vd.active)) { 983 1.17.2.2 jmcneill radeonfb_engine_init(dp); 984 1.17.2.2 jmcneill radeonfb_modeswitch(dp); 985 1.17.2.2 jmcneill vcons_redraw_screen(dp->rd_vd.active); 986 1.17.2.2 jmcneill } 987 1.17.2.2 jmcneill } 988 1.17.2.2 jmcneill return 0; 989 1.17.2.2 jmcneill 990 1.17.2.2 jmcneill case WSDISPLAYIO_GCURMAX: 991 1.17.2.2 jmcneill ((struct wsdisplay_curpos *)d)->x = RADEON_CURSORMAXX; 992 1.17.2.2 jmcneill ((struct wsdisplay_curpos *)d)->y = RADEON_CURSORMAXY; 993 1.17.2.2 jmcneill return 0; 994 1.17.2.2 jmcneill 995 1.17.2.2 jmcneill case WSDISPLAYIO_SCURSOR: 996 1.17.2.2 jmcneill return radeonfb_set_cursor(dp, (struct wsdisplay_cursor *)d); 997 1.17.2.2 jmcneill 998 1.17.2.2 jmcneill case WSDISPLAYIO_GCURSOR: 999 1.17.2.2 jmcneill return EPASSTHROUGH; 1000 1.17.2.2 jmcneill 1001 1.17.2.2 jmcneill case WSDISPLAYIO_GCURPOS: 1002 1.17.2.2 jmcneill ((struct wsdisplay_curpos *)d)->x = dp->rd_cursor.rc_pos.x; 1003 1.17.2.2 jmcneill ((struct wsdisplay_curpos *)d)->y = dp->rd_cursor.rc_pos.y; 1004 1.17.2.2 jmcneill return 0; 1005 1.17.2.2 jmcneill 1006 1.17.2.2 jmcneill case WSDISPLAYIO_SCURPOS: 1007 1.17.2.2 jmcneill return radeonfb_set_curpos(dp, (struct wsdisplay_curpos *)d); 1008 1.17.2.2 jmcneill 1009 1.17.2.2 jmcneill case WSDISPLAYIO_SSPLASH: 1010 1.17.2.2 jmcneill #if defined(SPLASHSCREEN) 1011 1.17.2.2 jmcneill if (*(int *)d == 1) { 1012 1.17.2.2 jmcneill SCREEN_DISABLE_DRAWING(&dp->rd_vscreen); 1013 1.17.2.2 jmcneill splash_render(&dp->rd_splash, 1014 1.17.2.2 jmcneill SPLASH_F_CENTER|SPLASH_F_FILL); 1015 1.17.2.2 jmcneill } else 1016 1.17.2.2 jmcneill SCREEN_ENABLE_DRAWING(&dp->rd_vscreen); 1017 1.17.2.2 jmcneill return 0; 1018 1.17.2.2 jmcneill #else 1019 1.17.2.2 jmcneill return ENODEV; 1020 1.17.2.2 jmcneill #endif 1021 1.17.2.2 jmcneill case WSDISPLAYIO_SPROGRESS: 1022 1.17.2.2 jmcneill #if defined(SPLASHSCREEN) && defined(SPLASHSCREEN_PROGRESS) 1023 1.17.2.2 jmcneill dp->rd_progress.sp_force = 1; 1024 1.17.2.2 jmcneill splash_progress_update(&dp->rd_progress); 1025 1.17.2.2 jmcneill dp->rd_progress.sp_force = 0; 1026 1.17.2.2 jmcneill return 0; 1027 1.17.2.2 jmcneill #else 1028 1.17.2.2 jmcneill return ENODEV; 1029 1.17.2.2 jmcneill #endif 1030 1.17.2.2 jmcneill case WSDISPLAYIO_GETPARAM: 1031 1.17.2.2 jmcneill param = (struct wsdisplay_param *)d; 1032 1.17.2.2 jmcneill if (param->param == WSDISPLAYIO_PARAM_BACKLIGHT) { 1033 1.17.2.2 jmcneill param->min = 0; 1034 1.17.2.2 jmcneill param->max = RADEONFB_BACKLIGHT_MAX; 1035 1.17.2.2 jmcneill param->curval = radeonfb_get_backlight(dp); 1036 1.17.2.2 jmcneill return 0; 1037 1.17.2.2 jmcneill } 1038 1.17.2.2 jmcneill return EPASSTHROUGH; 1039 1.17.2.2 jmcneill 1040 1.17.2.2 jmcneill case WSDISPLAYIO_SETPARAM: 1041 1.17.2.2 jmcneill param = (struct wsdisplay_param *)d; 1042 1.17.2.2 jmcneill if (param->param == WSDISPLAYIO_PARAM_BACKLIGHT) { 1043 1.17.2.2 jmcneill return radeonfb_set_backlight(dp, param->curval); 1044 1.17.2.2 jmcneill } 1045 1.17.2.2 jmcneill return EPASSTHROUGH; 1046 1.17.2.2 jmcneill 1047 1.17.2.2 jmcneill default: 1048 1.17.2.2 jmcneill return EPASSTHROUGH; 1049 1.17.2.2 jmcneill } 1050 1.17.2.2 jmcneill } 1051 1.17.2.2 jmcneill 1052 1.17.2.2 jmcneill paddr_t 1053 1.17.2.2 jmcneill radeonfb_mmap(void *v, void *vs, off_t offset, int prot) 1054 1.17.2.2 jmcneill { 1055 1.17.2.2 jmcneill struct vcons_data *vd; 1056 1.17.2.2 jmcneill struct radeonfb_display *dp; 1057 1.17.2.2 jmcneill struct radeonfb_softc *sc; 1058 1.17.2.2 jmcneill #ifdef RADEONFB_MMAP_BARS 1059 1.17.2.2 jmcneill struct lwp *me; 1060 1.17.2.2 jmcneill #endif 1061 1.17.2.2 jmcneill paddr_t pa; 1062 1.17.2.2 jmcneill 1063 1.17.2.2 jmcneill vd = (struct vcons_data *)v; 1064 1.17.2.2 jmcneill dp = (struct radeonfb_display *)vd->cookie; 1065 1.17.2.2 jmcneill sc = dp->rd_softc; 1066 1.17.2.2 jmcneill 1067 1.17.2.2 jmcneill /* XXX: note that we don't allow mapping of registers right now */ 1068 1.17.2.2 jmcneill /* XXX: this means that the XFree86 radeon driver won't work */ 1069 1.17.2.2 jmcneill 1070 1.17.2.2 jmcneill if ((offset >= 0) && (offset < (dp->rd_virty * dp->rd_stride))) { 1071 1.17.2.2 jmcneill pa = bus_space_mmap(sc->sc_memt, 1072 1.17.2.2 jmcneill sc->sc_memaddr + dp->rd_offset + offset, 0, 1073 1.17.2.2 jmcneill prot, BUS_SPACE_MAP_LINEAR); 1074 1.17.2.2 jmcneill return pa; 1075 1.17.2.2 jmcneill } 1076 1.17.2.2 jmcneill 1077 1.17.2.2 jmcneill #ifdef RADEONFB_MMAP_BARS 1078 1.17.2.2 jmcneill /* 1079 1.17.2.2 jmcneill * restrict all other mappings to processes with superuser privileges 1080 1.17.2.2 jmcneill * or the kernel itself 1081 1.17.2.2 jmcneill */ 1082 1.17.2.2 jmcneill me = curlwp; 1083 1.17.2.2 jmcneill if (me != NULL) { 1084 1.17.2.2 jmcneill if (kauth_authorize_generic(me->l_cred, KAUTH_GENERIC_ISSUSER, 1085 1.17.2.2 jmcneill NULL) != 0) { 1086 1.17.2.2 jmcneill printf("%s: mmap() rejected.\n", sc->sc_dev.dv_xname); 1087 1.17.2.2 jmcneill return -1; 1088 1.17.2.2 jmcneill } 1089 1.17.2.2 jmcneill } 1090 1.17.2.2 jmcneill 1091 1.17.2.2 jmcneill if ((offset >= sc->sc_regaddr) && 1092 1.17.2.2 jmcneill (offset < sc->sc_regaddr + sc->sc_regsz)) { 1093 1.17.2.2 jmcneill return bus_space_mmap(sc->sc_regt, offset, 0, prot, 1094 1.17.2.2 jmcneill BUS_SPACE_MAP_LINEAR); 1095 1.17.2.2 jmcneill } 1096 1.17.2.2 jmcneill 1097 1.17.2.2 jmcneill if ((offset >= sc->sc_memaddr) && 1098 1.17.2.2 jmcneill (offset < sc->sc_memaddr + sc->sc_memsz)) { 1099 1.17.2.2 jmcneill return bus_space_mmap(sc->sc_memt, offset, 0, prot, 1100 1.17.2.2 jmcneill BUS_SPACE_MAP_LINEAR); 1101 1.17.2.2 jmcneill } 1102 1.17.2.2 jmcneill 1103 1.17.2.2 jmcneill #ifdef macppc 1104 1.17.2.2 jmcneill /* allow mapping of IO space */ 1105 1.17.2.2 jmcneill if ((offset >= 0xf2000000) && (offset < 0xf2800000)) { 1106 1.17.2.2 jmcneill pa = bus_space_mmap(sc->sc_iot, offset - 0xf2000000, 0, prot, 1107 1.17.2.2 jmcneill 0); 1108 1.17.2.2 jmcneill return pa; 1109 1.17.2.2 jmcneill } 1110 1.17.2.2 jmcneill #endif /* macppc */ 1111 1.17.2.2 jmcneill 1112 1.17.2.2 jmcneill #endif /* RADEONFB_MMAP_BARS */ 1113 1.17.2.2 jmcneill 1114 1.17.2.2 jmcneill return -1; 1115 1.17.2.2 jmcneill } 1116 1.17.2.2 jmcneill 1117 1.17.2.2 jmcneill static void 1118 1.17.2.2 jmcneill radeonfb_loadbios(struct radeonfb_softc *sc, struct pci_attach_args *pa) 1119 1.17.2.2 jmcneill { 1120 1.17.2.2 jmcneill bus_space_tag_t romt; 1121 1.17.2.2 jmcneill bus_space_handle_t romh, biosh; 1122 1.17.2.2 jmcneill bus_size_t romsz; 1123 1.17.2.2 jmcneill bus_addr_t ptr; 1124 1.17.2.2 jmcneill 1125 1.17.2.2 jmcneill if (pci_mapreg_map(pa, PCI_MAPREG_ROM, PCI_MAPREG_TYPE_ROM, 1126 1.17.2.2 jmcneill BUS_SPACE_MAP_PREFETCHABLE, &romt, &romh, NULL, &romsz) != 0) { 1127 1.17.2.2 jmcneill aprint_verbose("%s: unable to map BIOS!\n", XNAME(sc)); 1128 1.17.2.2 jmcneill return; 1129 1.17.2.2 jmcneill } 1130 1.17.2.2 jmcneill 1131 1.17.2.2 jmcneill pci_find_rom(pa, romt, romh, PCI_ROM_CODE_TYPE_X86, &biosh, 1132 1.17.2.2 jmcneill &sc->sc_biossz); 1133 1.17.2.2 jmcneill if (sc->sc_biossz == 0) { 1134 1.17.2.2 jmcneill aprint_verbose("%s: Video BIOS not present\n", XNAME(sc)); 1135 1.17.2.2 jmcneill return; 1136 1.17.2.2 jmcneill } 1137 1.17.2.2 jmcneill 1138 1.17.2.2 jmcneill sc->sc_bios = malloc(sc->sc_biossz, M_DEVBUF, M_WAITOK); 1139 1.17.2.2 jmcneill bus_space_read_region_1(romt, biosh, 0, sc->sc_bios, sc->sc_biossz); 1140 1.17.2.2 jmcneill 1141 1.17.2.2 jmcneill /* unmap the PCI expansion rom */ 1142 1.17.2.2 jmcneill bus_space_unmap(romt, romh, romsz); 1143 1.17.2.2 jmcneill 1144 1.17.2.2 jmcneill /* turn off rom decoder now */ 1145 1.17.2.2 jmcneill pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM, 1146 1.17.2.2 jmcneill pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM) & 1147 1.17.2.2 jmcneill ~PCI_MAPREG_ROM_ENABLE); 1148 1.17.2.2 jmcneill 1149 1.17.2.2 jmcneill ptr = GETBIOS16(sc, 0x48); 1150 1.17.2.2 jmcneill if ((GETBIOS32(sc, ptr + 4) == 0x41544f4d /* "ATOM" */) || 1151 1.17.2.2 jmcneill (GETBIOS32(sc, ptr + 4) == 0x4d4f5441 /* "MOTA" */)) { 1152 1.17.2.2 jmcneill sc->sc_flags |= RFB_ATOM; 1153 1.17.2.2 jmcneill } 1154 1.17.2.2 jmcneill 1155 1.17.2.2 jmcneill aprint_verbose("%s: Found %d KB %s BIOS\n", XNAME(sc), 1156 1.17.2.2 jmcneill (unsigned)sc->sc_biossz >> 10, IS_ATOM(sc) ? "ATOM" : "Legacy"); 1157 1.17.2.2 jmcneill } 1158 1.17.2.2 jmcneill 1159 1.17.2.2 jmcneill 1160 1.17.2.2 jmcneill uint32_t 1161 1.17.2.2 jmcneill radeonfb_get32(struct radeonfb_softc *sc, uint32_t reg) 1162 1.17.2.2 jmcneill { 1163 1.17.2.2 jmcneill 1164 1.17.2.2 jmcneill return bus_space_read_4(sc->sc_regt, sc->sc_regh, reg); 1165 1.17.2.2 jmcneill } 1166 1.17.2.2 jmcneill 1167 1.17.2.2 jmcneill void 1168 1.17.2.2 jmcneill radeonfb_put32(struct radeonfb_softc *sc, uint32_t reg, uint32_t val) 1169 1.17.2.2 jmcneill { 1170 1.17.2.2 jmcneill 1171 1.17.2.2 jmcneill bus_space_write_4(sc->sc_regt, sc->sc_regh, reg, val); 1172 1.17.2.2 jmcneill } 1173 1.17.2.2 jmcneill 1174 1.17.2.2 jmcneill void 1175 1.17.2.2 jmcneill radeonfb_mask32(struct radeonfb_softc *sc, uint32_t reg, 1176 1.17.2.2 jmcneill uint32_t andmask, uint32_t ormask) 1177 1.17.2.2 jmcneill { 1178 1.17.2.2 jmcneill int s; 1179 1.17.2.2 jmcneill uint32_t val; 1180 1.17.2.2 jmcneill 1181 1.17.2.2 jmcneill s = splhigh(); 1182 1.17.2.2 jmcneill val = radeonfb_get32(sc, reg); 1183 1.17.2.2 jmcneill val = (val & andmask) | ormask; 1184 1.17.2.2 jmcneill radeonfb_put32(sc, reg, val); 1185 1.17.2.2 jmcneill splx(s); 1186 1.17.2.2 jmcneill } 1187 1.17.2.2 jmcneill 1188 1.17.2.2 jmcneill uint32_t 1189 1.17.2.2 jmcneill radeonfb_getindex(struct radeonfb_softc *sc, uint32_t idx) 1190 1.17.2.2 jmcneill { 1191 1.17.2.2 jmcneill int s; 1192 1.17.2.2 jmcneill uint32_t val; 1193 1.17.2.2 jmcneill 1194 1.17.2.2 jmcneill s = splhigh(); 1195 1.17.2.2 jmcneill radeonfb_put32(sc, RADEON_MM_INDEX, idx); 1196 1.17.2.2 jmcneill val = radeonfb_get32(sc, RADEON_MM_DATA); 1197 1.17.2.2 jmcneill splx(s); 1198 1.17.2.2 jmcneill 1199 1.17.2.2 jmcneill return (val); 1200 1.17.2.2 jmcneill } 1201 1.17.2.2 jmcneill 1202 1.17.2.2 jmcneill void 1203 1.17.2.2 jmcneill radeonfb_putindex(struct radeonfb_softc *sc, uint32_t idx, uint32_t val) 1204 1.17.2.2 jmcneill { 1205 1.17.2.2 jmcneill int s; 1206 1.17.2.2 jmcneill 1207 1.17.2.2 jmcneill s = splhigh(); 1208 1.17.2.2 jmcneill radeonfb_put32(sc, RADEON_MM_INDEX, idx); 1209 1.17.2.2 jmcneill radeonfb_put32(sc, RADEON_MM_DATA, val); 1210 1.17.2.2 jmcneill splx(s); 1211 1.17.2.2 jmcneill } 1212 1.17.2.2 jmcneill 1213 1.17.2.2 jmcneill void 1214 1.17.2.2 jmcneill radeonfb_maskindex(struct radeonfb_softc *sc, uint32_t idx, 1215 1.17.2.2 jmcneill uint32_t andmask, uint32_t ormask) 1216 1.17.2.2 jmcneill { 1217 1.17.2.2 jmcneill int s; 1218 1.17.2.2 jmcneill uint32_t val; 1219 1.17.2.2 jmcneill 1220 1.17.2.2 jmcneill s = splhigh(); 1221 1.17.2.2 jmcneill radeonfb_put32(sc, RADEON_MM_INDEX, idx); 1222 1.17.2.2 jmcneill val = radeonfb_get32(sc, RADEON_MM_DATA); 1223 1.17.2.2 jmcneill val = (val & andmask) | ormask; 1224 1.17.2.2 jmcneill radeonfb_put32(sc, RADEON_MM_DATA, val); 1225 1.17.2.2 jmcneill splx(s); 1226 1.17.2.2 jmcneill } 1227 1.17.2.2 jmcneill 1228 1.17.2.2 jmcneill uint32_t 1229 1.17.2.2 jmcneill radeonfb_getpll(struct radeonfb_softc *sc, uint32_t idx) 1230 1.17.2.2 jmcneill { 1231 1.17.2.2 jmcneill int s; 1232 1.17.2.2 jmcneill uint32_t val; 1233 1.17.2.2 jmcneill 1234 1.17.2.2 jmcneill s = splhigh(); 1235 1.17.2.2 jmcneill radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, idx & 0x3f); 1236 1.17.2.2 jmcneill val = radeonfb_get32(sc, RADEON_CLOCK_CNTL_DATA); 1237 1.17.2.2 jmcneill if (HAS_R300CG(sc)) 1238 1.17.2.2 jmcneill radeonfb_r300cg_workaround(sc); 1239 1.17.2.2 jmcneill splx(s); 1240 1.17.2.2 jmcneill 1241 1.17.2.2 jmcneill return (val); 1242 1.17.2.2 jmcneill } 1243 1.17.2.2 jmcneill 1244 1.17.2.2 jmcneill void 1245 1.17.2.2 jmcneill radeonfb_putpll(struct radeonfb_softc *sc, uint32_t idx, uint32_t val) 1246 1.17.2.2 jmcneill { 1247 1.17.2.2 jmcneill int s; 1248 1.17.2.2 jmcneill 1249 1.17.2.2 jmcneill s = splhigh(); 1250 1.17.2.2 jmcneill radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, (idx & 0x3f) | 1251 1.17.2.2 jmcneill RADEON_PLL_WR_EN); 1252 1.17.2.2 jmcneill radeonfb_put32(sc, RADEON_CLOCK_CNTL_DATA, val); 1253 1.17.2.2 jmcneill radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, 0); 1254 1.17.2.2 jmcneill splx(s); 1255 1.17.2.2 jmcneill } 1256 1.17.2.2 jmcneill 1257 1.17.2.2 jmcneill void 1258 1.17.2.2 jmcneill radeonfb_maskpll(struct radeonfb_softc *sc, uint32_t idx, 1259 1.17.2.2 jmcneill uint32_t andmask, uint32_t ormask) 1260 1.17.2.2 jmcneill { 1261 1.17.2.2 jmcneill int s; 1262 1.17.2.2 jmcneill uint32_t val; 1263 1.17.2.2 jmcneill 1264 1.17.2.2 jmcneill s = splhigh(); 1265 1.17.2.2 jmcneill radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, (idx & 0x3f) | 1266 1.17.2.2 jmcneill RADEON_PLL_WR_EN); 1267 1.17.2.2 jmcneill val = radeonfb_get32(sc, RADEON_CLOCK_CNTL_DATA); 1268 1.17.2.2 jmcneill val = (val & andmask) | ormask; 1269 1.17.2.2 jmcneill radeonfb_put32(sc, RADEON_CLOCK_CNTL_DATA, val); 1270 1.17.2.2 jmcneill radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, 0); 1271 1.17.2.2 jmcneill splx(s); 1272 1.17.2.2 jmcneill } 1273 1.17.2.2 jmcneill 1274 1.17.2.2 jmcneill int 1275 1.17.2.2 jmcneill radeonfb_scratch_test(struct radeonfb_softc *sc, int reg, uint32_t v) 1276 1.17.2.2 jmcneill { 1277 1.17.2.2 jmcneill uint32_t saved; 1278 1.17.2.2 jmcneill 1279 1.17.2.2 jmcneill saved = GET32(sc, reg); 1280 1.17.2.2 jmcneill PUT32(sc, reg, v); 1281 1.17.2.2 jmcneill if (GET32(sc, reg) != v) { 1282 1.17.2.2 jmcneill return -1; 1283 1.17.2.2 jmcneill } 1284 1.17.2.2 jmcneill PUT32(sc, reg, saved); 1285 1.17.2.2 jmcneill return 0; 1286 1.17.2.2 jmcneill } 1287 1.17.2.2 jmcneill 1288 1.17.2.2 jmcneill uintmax_t 1289 1.17.2.2 jmcneill radeonfb_getprop_num(struct radeonfb_softc *sc, const char *name, 1290 1.17.2.2 jmcneill uintmax_t defval) 1291 1.17.2.2 jmcneill { 1292 1.17.2.2 jmcneill prop_number_t pn; 1293 1.17.2.2 jmcneill pn = prop_dictionary_get(device_properties(&sc->sc_dev), name); 1294 1.17.2.2 jmcneill if (pn == NULL) { 1295 1.17.2.2 jmcneill return defval; 1296 1.17.2.2 jmcneill } 1297 1.17.2.2 jmcneill KASSERT(prop_object_type(pn) == PROP_TYPE_NUMBER); 1298 1.17.2.2 jmcneill return (prop_number_integer_value(pn)); 1299 1.17.2.2 jmcneill } 1300 1.17.2.2 jmcneill 1301 1.17.2.2 jmcneill int 1302 1.17.2.2 jmcneill radeonfb_getclocks(struct radeonfb_softc *sc) 1303 1.17.2.2 jmcneill { 1304 1.17.2.2 jmcneill bus_addr_t ptr; 1305 1.17.2.2 jmcneill int refclk = 0; 1306 1.17.2.2 jmcneill int refdiv = 0; 1307 1.17.2.2 jmcneill int minpll = 0; 1308 1.17.2.2 jmcneill int maxpll = 0; 1309 1.17.2.2 jmcneill 1310 1.17.2.2 jmcneill /* load initial property values if port/board provides them */ 1311 1.17.2.2 jmcneill refclk = radeonfb_getprop_num(sc, "refclk", 0) & 0xffff; 1312 1.17.2.2 jmcneill refdiv = radeonfb_getprop_num(sc, "refdiv", 0) & 0xffff; 1313 1.17.2.2 jmcneill minpll = radeonfb_getprop_num(sc, "minpll", 0) & 0xffffffffU; 1314 1.17.2.2 jmcneill maxpll = radeonfb_getprop_num(sc, "maxpll", 0) & 0xffffffffU; 1315 1.17.2.2 jmcneill 1316 1.17.2.2 jmcneill if (refclk && refdiv && minpll && maxpll) 1317 1.17.2.2 jmcneill goto dontprobe; 1318 1.17.2.2 jmcneill 1319 1.17.2.2 jmcneill if (!sc->sc_biossz) { 1320 1.17.2.2 jmcneill /* no BIOS */ 1321 1.17.2.2 jmcneill aprint_verbose("%s: No video BIOS, using default clocks\n", 1322 1.17.2.2 jmcneill XNAME(sc)); 1323 1.17.2.2 jmcneill if (IS_IGP(sc)) 1324 1.17.2.2 jmcneill refclk = refclk ? refclk : 1432; 1325 1.17.2.2 jmcneill else 1326 1.17.2.2 jmcneill refclk = refclk ? refclk : 2700; 1327 1.17.2.2 jmcneill refdiv = refdiv ? refdiv : 12; 1328 1.17.2.2 jmcneill minpll = minpll ? minpll : 12500; 1329 1.17.2.2 jmcneill maxpll = maxpll ? maxpll : 35000; 1330 1.17.2.2 jmcneill } else if (IS_ATOM(sc)) { 1331 1.17.2.2 jmcneill /* ATOM BIOS */ 1332 1.17.2.2 jmcneill ptr = GETBIOS16(sc, 0x48); 1333 1.17.2.2 jmcneill ptr = GETBIOS16(sc, ptr + 32); /* aka MasterDataStart */ 1334 1.17.2.2 jmcneill ptr = GETBIOS16(sc, ptr + 12); /* pll info block */ 1335 1.17.2.2 jmcneill refclk = refclk ? refclk : GETBIOS16(sc, ptr + 82); 1336 1.17.2.2 jmcneill minpll = minpll ? minpll : GETBIOS16(sc, ptr + 78); 1337 1.17.2.2 jmcneill maxpll = maxpll ? maxpll : GETBIOS16(sc, ptr + 32); 1338 1.17.2.2 jmcneill /* 1339 1.17.2.2 jmcneill * ATOM BIOS doesn't supply a reference divider, so we 1340 1.17.2.2 jmcneill * have to probe for it. 1341 1.17.2.2 jmcneill */ 1342 1.17.2.2 jmcneill if (refdiv < 2) 1343 1.17.2.2 jmcneill refdiv = GETPLL(sc, RADEON_PPLL_REF_DIV) & 1344 1.17.2.2 jmcneill RADEON_PPLL_REF_DIV_MASK; 1345 1.17.2.2 jmcneill /* 1346 1.17.2.2 jmcneill * if probe is zero, just assume one that should work 1347 1.17.2.2 jmcneill * for most parts 1348 1.17.2.2 jmcneill */ 1349 1.17.2.2 jmcneill if (refdiv < 2) 1350 1.17.2.2 jmcneill refdiv = 12; 1351 1.17.2.2 jmcneill 1352 1.17.2.2 jmcneill } else { 1353 1.17.2.2 jmcneill /* Legacy BIOS */ 1354 1.17.2.2 jmcneill ptr = GETBIOS16(sc, 0x48); 1355 1.17.2.2 jmcneill ptr = GETBIOS16(sc, ptr + 0x30); 1356 1.17.2.2 jmcneill refclk = refclk ? refclk : GETBIOS16(sc, ptr + 0x0E); 1357 1.17.2.2 jmcneill refdiv = refdiv ? refdiv : GETBIOS16(sc, ptr + 0x10); 1358 1.17.2.2 jmcneill minpll = minpll ? minpll : GETBIOS32(sc, ptr + 0x12); 1359 1.17.2.2 jmcneill maxpll = maxpll ? maxpll : GETBIOS32(sc, ptr + 0x16); 1360 1.17.2.2 jmcneill } 1361 1.17.2.2 jmcneill 1362 1.17.2.2 jmcneill 1363 1.17.2.2 jmcneill dontprobe: 1364 1.17.2.2 jmcneill sc->sc_refclk = refclk * 10; 1365 1.17.2.2 jmcneill sc->sc_refdiv = refdiv; 1366 1.17.2.2 jmcneill sc->sc_minpll = minpll * 10; 1367 1.17.2.2 jmcneill sc->sc_maxpll = maxpll * 10; 1368 1.17.2.2 jmcneill return 0; 1369 1.17.2.2 jmcneill } 1370 1.17.2.2 jmcneill 1371 1.17.2.2 jmcneill int 1372 1.17.2.2 jmcneill radeonfb_calc_dividers(struct radeonfb_softc *sc, uint32_t dotclock, 1373 1.17.2.2 jmcneill uint32_t *postdivbit, uint32_t *feedbackdiv) 1374 1.17.2.2 jmcneill { 1375 1.17.2.2 jmcneill int i; 1376 1.17.2.2 jmcneill uint32_t outfreq; 1377 1.17.2.2 jmcneill int div; 1378 1.17.2.2 jmcneill 1379 1.17.2.2 jmcneill DPRINTF(("dot clock: %u\n", dotclock)); 1380 1.17.2.2 jmcneill for (i = 0; (div = radeonfb_dividers[i].divider) != 0; i++) { 1381 1.17.2.2 jmcneill outfreq = div * dotclock; 1382 1.17.2.2 jmcneill if ((outfreq >= sc->sc_minpll) && 1383 1.17.2.2 jmcneill (outfreq <= sc->sc_maxpll)) { 1384 1.17.2.2 jmcneill DPRINTF(("outfreq: %u\n", outfreq)); 1385 1.17.2.2 jmcneill *postdivbit = 1386 1.17.2.2 jmcneill ((uint32_t)radeonfb_dividers[i].mask << 16); 1387 1.17.2.2 jmcneill DPRINTF(("post divider: %d (mask %x)\n", div, 1388 1.17.2.2 jmcneill *postdivbit)); 1389 1.17.2.2 jmcneill break; 1390 1.17.2.2 jmcneill } 1391 1.17.2.2 jmcneill } 1392 1.17.2.2 jmcneill 1393 1.17.2.2 jmcneill if (div == 0) 1394 1.17.2.2 jmcneill return 1; 1395 1.17.2.2 jmcneill 1396 1.17.2.2 jmcneill *feedbackdiv = DIVIDE(sc->sc_refdiv * outfreq, sc->sc_refclk); 1397 1.17.2.2 jmcneill DPRINTF(("feedback divider: %d\n", *feedbackdiv)); 1398 1.17.2.2 jmcneill return 0; 1399 1.17.2.2 jmcneill } 1400 1.17.2.2 jmcneill 1401 1.17.2.2 jmcneill #if 0 1402 1.17.2.2 jmcneill #ifdef RADEON_DEBUG 1403 1.17.2.2 jmcneill static void 1404 1.17.2.2 jmcneill dump_buffer(const char *pfx, void *buffer, unsigned int size) 1405 1.17.2.2 jmcneill { 1406 1.17.2.2 jmcneill char asc[17]; 1407 1.17.2.2 jmcneill unsigned ptr = (unsigned)buffer; 1408 1.17.2.2 jmcneill char *start = (char *)(ptr & ~0xf); 1409 1.17.2.2 jmcneill char *end = (char *)(ptr + size); 1410 1.17.2.2 jmcneill 1411 1.17.2.2 jmcneill end = (char *)(((unsigned)end + 0xf) & ~0xf); 1412 1.17.2.2 jmcneill 1413 1.17.2.2 jmcneill if (pfx == NULL) { 1414 1.17.2.2 jmcneill pfx = ""; 1415 1.17.2.2 jmcneill } 1416 1.17.2.2 jmcneill 1417 1.17.2.2 jmcneill while (start < end) { 1418 1.17.2.2 jmcneill unsigned offset = (unsigned)start & 0xf; 1419 1.17.2.2 jmcneill if (offset == 0) { 1420 1.17.2.2 jmcneill printf("%s%x: ", pfx, (unsigned)start); 1421 1.17.2.2 jmcneill } 1422 1.17.2.2 jmcneill if (((unsigned)start < ptr) || 1423 1.17.2.2 jmcneill ((unsigned)start >= (ptr + size))) { 1424 1.17.2.2 jmcneill printf(" "); 1425 1.17.2.2 jmcneill asc[offset] = ' '; 1426 1.17.2.2 jmcneill } else { 1427 1.17.2.2 jmcneill printf("%02x", *(unsigned char *)start); 1428 1.17.2.2 jmcneill if ((*start >= ' ') && (*start <= '~')) { 1429 1.17.2.2 jmcneill asc[offset] = *start; 1430 1.17.2.2 jmcneill } else { 1431 1.17.2.2 jmcneill asc[offset] = '.'; 1432 1.17.2.2 jmcneill } 1433 1.17.2.2 jmcneill } 1434 1.17.2.2 jmcneill asc[offset + 1] = 0; 1435 1.17.2.2 jmcneill if (offset % 2) { 1436 1.17.2.2 jmcneill printf(" "); 1437 1.17.2.2 jmcneill } 1438 1.17.2.2 jmcneill if (offset == 15) { 1439 1.17.2.2 jmcneill printf(" %s\n", asc); 1440 1.17.2.2 jmcneill } 1441 1.17.2.2 jmcneill start++; 1442 1.17.2.2 jmcneill } 1443 1.17.2.2 jmcneill } 1444 1.17.2.2 jmcneill #endif 1445 1.17.2.2 jmcneill #endif 1446 1.17.2.2 jmcneill 1447 1.17.2.2 jmcneill int 1448 1.17.2.2 jmcneill radeonfb_getconnectors(struct radeonfb_softc *sc) 1449 1.17.2.2 jmcneill { 1450 1.17.2.2 jmcneill int i; 1451 1.17.2.2 jmcneill int found = 0; 1452 1.17.2.2 jmcneill 1453 1.17.2.2 jmcneill for (i = 0; i < 2; i++) { 1454 1.17.2.2 jmcneill sc->sc_ports[i].rp_mon_type = RADEON_MT_UNKNOWN; 1455 1.17.2.2 jmcneill sc->sc_ports[i].rp_ddc_type = RADEON_DDC_NONE; 1456 1.17.2.2 jmcneill sc->sc_ports[i].rp_dac_type = RADEON_DAC_UNKNOWN; 1457 1.17.2.2 jmcneill sc->sc_ports[i].rp_conn_type = RADEON_CONN_NONE; 1458 1.17.2.2 jmcneill sc->sc_ports[i].rp_tmds_type = RADEON_TMDS_UNKNOWN; 1459 1.17.2.2 jmcneill } 1460 1.17.2.2 jmcneill 1461 1.17.2.2 jmcneill /* 1462 1.17.2.2 jmcneill * This logic is borrowed from Xorg's radeon driver. 1463 1.17.2.2 jmcneill */ 1464 1.17.2.2 jmcneill if (!sc->sc_biossz) 1465 1.17.2.2 jmcneill goto nobios; 1466 1.17.2.2 jmcneill 1467 1.17.2.2 jmcneill if (IS_ATOM(sc)) { 1468 1.17.2.2 jmcneill /* not done yet */ 1469 1.17.2.2 jmcneill } else { 1470 1.17.2.2 jmcneill uint16_t ptr; 1471 1.17.2.2 jmcneill int port = 0; 1472 1.17.2.2 jmcneill 1473 1.17.2.2 jmcneill ptr = GETBIOS16(sc, 0x48); 1474 1.17.2.2 jmcneill ptr = GETBIOS16(sc, ptr + 0x50); 1475 1.17.2.2 jmcneill for (i = 1; i < 4; i++) { 1476 1.17.2.2 jmcneill uint16_t entry; 1477 1.17.2.2 jmcneill uint8_t conn, ddc, dac, tmds; 1478 1.17.2.2 jmcneill 1479 1.17.2.2 jmcneill /* 1480 1.17.2.2 jmcneill * Parse the connector table. From reading the code, 1481 1.17.2.2 jmcneill * it appears to made up of 16-bit entries for each 1482 1.17.2.2 jmcneill * connector. The 16-bits are defined as: 1483 1.17.2.2 jmcneill * 1484 1.17.2.2 jmcneill * bits 12-15 - connector type (0 == end of table) 1485 1.17.2.2 jmcneill * bits 8-11 - DDC type 1486 1.17.2.2 jmcneill * bits 5-7 - ??? 1487 1.17.2.2 jmcneill * bit 4 - TMDS type (1 = EXT, 0 = INT) 1488 1.17.2.2 jmcneill * bits 1-3 - ??? 1489 1.17.2.2 jmcneill * bit 0 - DAC, 1 = TVDAC, 0 = primary 1490 1.17.2.2 jmcneill */ 1491 1.17.2.2 jmcneill if (!GETBIOS8(sc, ptr + i * 2) && i > 1) 1492 1.17.2.2 jmcneill break; 1493 1.17.2.2 jmcneill entry = GETBIOS16(sc, ptr + i * 2); 1494 1.17.2.2 jmcneill 1495 1.17.2.2 jmcneill conn = (entry >> 12) & 0xf; 1496 1.17.2.2 jmcneill ddc = (entry >> 8) & 0xf; 1497 1.17.2.2 jmcneill dac = (entry & 0x1) ? RADEON_DAC_TVDAC : 1498 1.17.2.2 jmcneill RADEON_DAC_PRIMARY; 1499 1.17.2.2 jmcneill tmds = ((entry >> 4) & 0x1) ? RADEON_TMDS_EXT : 1500 1.17.2.2 jmcneill RADEON_TMDS_INT; 1501 1.17.2.2 jmcneill 1502 1.17.2.2 jmcneill if (conn == RADEON_CONN_NONE) 1503 1.17.2.2 jmcneill continue; /* no connector */ 1504 1.17.2.2 jmcneill 1505 1.17.2.2 jmcneill if ((found > 0) && 1506 1.17.2.2 jmcneill (sc->sc_ports[port].rp_ddc_type == ddc)) { 1507 1.17.2.2 jmcneill /* duplicate entry for same connector */ 1508 1.17.2.2 jmcneill continue; 1509 1.17.2.2 jmcneill } 1510 1.17.2.2 jmcneill 1511 1.17.2.2 jmcneill /* internal DDC_DVI port gets priority */ 1512 1.17.2.2 jmcneill if ((ddc == RADEON_DDC_DVI) || (port == 1)) 1513 1.17.2.2 jmcneill port = 0; 1514 1.17.2.2 jmcneill else 1515 1.17.2.2 jmcneill port = 1; 1516 1.17.2.2 jmcneill 1517 1.17.2.2 jmcneill sc->sc_ports[port].rp_ddc_type = 1518 1.17.2.2 jmcneill ddc > RADEON_DDC_CRT2 ? RADEON_DDC_NONE : ddc; 1519 1.17.2.2 jmcneill sc->sc_ports[port].rp_dac_type = dac; 1520 1.17.2.2 jmcneill sc->sc_ports[port].rp_conn_type = 1521 1.17.2.2 jmcneill min(conn, RADEON_CONN_UNSUPPORTED) ; 1522 1.17.2.2 jmcneill 1523 1.17.2.2 jmcneill sc->sc_ports[port].rp_tmds_type = tmds; 1524 1.17.2.2 jmcneill 1525 1.17.2.2 jmcneill if ((conn != RADEON_CONN_DVI_I) && 1526 1.17.2.2 jmcneill (conn != RADEON_CONN_DVI_D) && 1527 1.17.2.2 jmcneill (tmds == RADEON_TMDS_INT)) 1528 1.17.2.2 jmcneill sc->sc_ports[port].rp_tmds_type = 1529 1.17.2.2 jmcneill RADEON_TMDS_UNKNOWN; 1530 1.17.2.2 jmcneill 1531 1.17.2.2 jmcneill found += (port + 1); 1532 1.17.2.2 jmcneill } 1533 1.17.2.2 jmcneill } 1534 1.17.2.2 jmcneill 1535 1.17.2.2 jmcneill nobios: 1536 1.17.2.2 jmcneill if (!found) { 1537 1.17.2.2 jmcneill DPRINTF(("No connector info in BIOS!\n")); 1538 1.17.2.2 jmcneill /* default, port 0 = internal TMDS, port 1 = CRT */ 1539 1.17.2.2 jmcneill sc->sc_ports[0].rp_mon_type = RADEON_MT_UNKNOWN; 1540 1.17.2.2 jmcneill sc->sc_ports[0].rp_ddc_type = RADEON_DDC_DVI; 1541 1.17.2.2 jmcneill sc->sc_ports[0].rp_dac_type = RADEON_DAC_TVDAC; 1542 1.17.2.2 jmcneill sc->sc_ports[0].rp_conn_type = RADEON_CONN_DVI_D; 1543 1.17.2.2 jmcneill sc->sc_ports[0].rp_tmds_type = RADEON_TMDS_INT; 1544 1.17.2.2 jmcneill 1545 1.17.2.2 jmcneill sc->sc_ports[1].rp_mon_type = RADEON_MT_UNKNOWN; 1546 1.17.2.2 jmcneill sc->sc_ports[1].rp_ddc_type = RADEON_DDC_VGA; 1547 1.17.2.2 jmcneill sc->sc_ports[1].rp_dac_type = RADEON_DAC_PRIMARY; 1548 1.17.2.2 jmcneill sc->sc_ports[1].rp_conn_type = RADEON_CONN_CRT; 1549 1.17.2.2 jmcneill sc->sc_ports[1].rp_tmds_type = RADEON_TMDS_EXT; 1550 1.17.2.2 jmcneill } 1551 1.17.2.2 jmcneill 1552 1.17.2.2 jmcneill /* 1553 1.17.2.2 jmcneill * Fixup for RS300/RS350/RS400 chips, that lack a primary DAC. 1554 1.17.2.2 jmcneill * these chips should use TVDAC for the VGA port. 1555 1.17.2.2 jmcneill */ 1556 1.17.2.2 jmcneill if (HAS_SDAC(sc)) { 1557 1.17.2.2 jmcneill if (sc->sc_ports[0].rp_conn_type == RADEON_CONN_CRT) { 1558 1.17.2.2 jmcneill sc->sc_ports[0].rp_dac_type = RADEON_DAC_TVDAC; 1559 1.17.2.2 jmcneill sc->sc_ports[1].rp_dac_type = RADEON_DAC_PRIMARY; 1560 1.17.2.2 jmcneill } else { 1561 1.17.2.2 jmcneill sc->sc_ports[1].rp_dac_type = RADEON_DAC_TVDAC; 1562 1.17.2.2 jmcneill sc->sc_ports[0].rp_dac_type = RADEON_DAC_PRIMARY; 1563 1.17.2.2 jmcneill } 1564 1.17.2.2 jmcneill } else if (!HAS_CRTC2(sc)) { 1565 1.17.2.2 jmcneill sc->sc_ports[0].rp_dac_type = RADEON_DAC_PRIMARY; 1566 1.17.2.2 jmcneill } 1567 1.17.2.2 jmcneill 1568 1.17.2.2 jmcneill for (i = 0; i < 2; i++) { 1569 1.17.2.2 jmcneill char edid[128]; 1570 1.17.2.2 jmcneill uint8_t ddc; 1571 1.17.2.2 jmcneill struct edid_info *eip = &sc->sc_ports[i].rp_edid; 1572 1.17.2.2 jmcneill prop_data_t edid_data; 1573 1.17.2.2 jmcneill 1574 1.17.2.2 jmcneill DPRINTF(("Port #%d:\n", i)); 1575 1.17.2.2 jmcneill DPRINTF((" conn = %d\n", sc->sc_ports[i].rp_conn_type)); 1576 1.17.2.2 jmcneill DPRINTF((" ddc = %d\n", sc->sc_ports[i].rp_ddc_type)); 1577 1.17.2.2 jmcneill DPRINTF((" dac = %d\n", sc->sc_ports[i].rp_dac_type)); 1578 1.17.2.2 jmcneill DPRINTF((" tmds = %d\n", sc->sc_ports[i].rp_tmds_type)); 1579 1.17.2.2 jmcneill 1580 1.17.2.2 jmcneill sc->sc_ports[i].rp_edid_valid = 0; 1581 1.17.2.2 jmcneill /* first look for static EDID data */ 1582 1.17.2.2 jmcneill if ((edid_data = prop_dictionary_get(device_properties( 1583 1.17.2.2 jmcneill &sc->sc_dev), "EDID")) != NULL) { 1584 1.17.2.2 jmcneill 1585 1.17.2.2 jmcneill aprint_normal("%s: using static EDID\n", 1586 1.17.2.2 jmcneill sc->sc_dev.dv_xname); 1587 1.17.2.2 jmcneill memcpy(edid, prop_data_data_nocopy(edid_data), 128); 1588 1.17.2.2 jmcneill if (edid_parse(edid, eip) == 0) { 1589 1.17.2.2 jmcneill 1590 1.17.2.2 jmcneill sc->sc_ports[i].rp_edid_valid = 1; 1591 1.17.2.2 jmcneill edid_print(eip); 1592 1.17.2.2 jmcneill } 1593 1.17.2.2 jmcneill } 1594 1.17.2.2 jmcneill /* if we didn't find any we'll try to talk to the monitor */ 1595 1.17.2.2 jmcneill if (sc->sc_ports[i].rp_edid_valid != 1) { 1596 1.17.2.2 jmcneill 1597 1.17.2.2 jmcneill ddc = sc->sc_ports[i].rp_ddc_type; 1598 1.17.2.2 jmcneill if (ddc != RADEON_DDC_NONE) { 1599 1.17.2.2 jmcneill if ((radeonfb_i2c_read_edid(sc, ddc, edid) 1600 1.17.2.2 jmcneill == 0) && (edid_parse(edid, eip) == 0)) { 1601 1.17.2.2 jmcneill 1602 1.17.2.2 jmcneill sc->sc_ports[i].rp_edid_valid = 1; 1603 1.17.2.2 jmcneill edid_print(eip); 1604 1.17.2.2 jmcneill } 1605 1.17.2.2 jmcneill } 1606 1.17.2.2 jmcneill } 1607 1.17.2.2 jmcneill } 1608 1.17.2.2 jmcneill 1609 1.17.2.2 jmcneill return found; 1610 1.17.2.2 jmcneill } 1611 1.17.2.2 jmcneill 1612 1.17.2.2 jmcneill int 1613 1.17.2.2 jmcneill radeonfb_gettmds(struct radeonfb_softc *sc) 1614 1.17.2.2 jmcneill { 1615 1.17.2.2 jmcneill int i; 1616 1.17.2.2 jmcneill 1617 1.17.2.2 jmcneill if (!sc->sc_biossz) { 1618 1.17.2.2 jmcneill goto nobios; 1619 1.17.2.2 jmcneill } 1620 1.17.2.2 jmcneill 1621 1.17.2.2 jmcneill if (IS_ATOM(sc)) { 1622 1.17.2.2 jmcneill /* XXX: not done yet */ 1623 1.17.2.2 jmcneill } else { 1624 1.17.2.2 jmcneill uint16_t ptr; 1625 1.17.2.2 jmcneill int n; 1626 1.17.2.2 jmcneill 1627 1.17.2.2 jmcneill ptr = GETBIOS16(sc, 0x48); 1628 1.17.2.2 jmcneill ptr = GETBIOS16(sc, ptr + 0x34); 1629 1.17.2.2 jmcneill DPRINTF(("DFP table revision %d\n", GETBIOS8(sc, ptr))); 1630 1.17.2.2 jmcneill if (GETBIOS8(sc, ptr) == 3) { 1631 1.17.2.2 jmcneill /* revision three table */ 1632 1.17.2.2 jmcneill n = GETBIOS8(sc, ptr + 5) + 1; 1633 1.17.2.2 jmcneill n = min(n, 4); 1634 1.17.2.2 jmcneill 1635 1.17.2.2 jmcneill memset(sc->sc_tmds_pll, 0, sizeof (sc->sc_tmds_pll)); 1636 1.17.2.2 jmcneill for (i = 0; i < n; i++) { 1637 1.17.2.2 jmcneill sc->sc_tmds_pll[i].rtp_pll = GETBIOS32(sc, 1638 1.17.2.2 jmcneill ptr + i * 10 + 8); 1639 1.17.2.2 jmcneill sc->sc_tmds_pll[i].rtp_freq = GETBIOS16(sc, 1640 1.17.2.2 jmcneill ptr + i * 10 + 0x10); 1641 1.17.2.2 jmcneill DPRINTF(("TMDS_PLL dot clock %d pll %x\n", 1642 1.17.2.2 jmcneill sc->sc_tmds_pll[i].rtp_freq, 1643 1.17.2.2 jmcneill sc->sc_tmds_pll[i].rtp_pll)); 1644 1.17.2.2 jmcneill } 1645 1.17.2.2 jmcneill return 0; 1646 1.17.2.2 jmcneill } 1647 1.17.2.2 jmcneill } 1648 1.17.2.2 jmcneill 1649 1.17.2.2 jmcneill nobios: 1650 1.17.2.2 jmcneill DPRINTF(("no suitable DFP table present\n")); 1651 1.17.2.2 jmcneill for (i = 0; 1652 1.17.2.2 jmcneill i < sizeof (radeonfb_tmds_pll) / sizeof (radeonfb_tmds_pll[0]); 1653 1.17.2.2 jmcneill i++) { 1654 1.17.2.2 jmcneill int j; 1655 1.17.2.2 jmcneill 1656 1.17.2.2 jmcneill if (radeonfb_tmds_pll[i].family != sc->sc_family) 1657 1.17.2.2 jmcneill continue; 1658 1.17.2.2 jmcneill 1659 1.17.2.2 jmcneill for (j = 0; j < 4; j++) { 1660 1.17.2.2 jmcneill sc->sc_tmds_pll[j] = radeonfb_tmds_pll[i].plls[j]; 1661 1.17.2.2 jmcneill DPRINTF(("TMDS_PLL dot clock %d pll %x\n", 1662 1.17.2.2 jmcneill sc->sc_tmds_pll[j].rtp_freq, 1663 1.17.2.2 jmcneill sc->sc_tmds_pll[j].rtp_pll)); 1664 1.17.2.2 jmcneill } 1665 1.17.2.2 jmcneill return 0; 1666 1.17.2.2 jmcneill } 1667 1.17.2.2 jmcneill 1668 1.17.2.2 jmcneill return -1; 1669 1.17.2.2 jmcneill } 1670 1.17.2.2 jmcneill 1671 1.17.2.2 jmcneill const struct videomode * 1672 1.17.2.2 jmcneill radeonfb_modelookup(const char *name) 1673 1.17.2.2 jmcneill { 1674 1.17.2.2 jmcneill int i; 1675 1.17.2.2 jmcneill 1676 1.17.2.2 jmcneill for (i = 0; i < videomode_count; i++) 1677 1.17.2.2 jmcneill if (!strcmp(name, videomode_list[i].name)) 1678 1.17.2.2 jmcneill return &videomode_list[i]; 1679 1.17.2.2 jmcneill 1680 1.17.2.2 jmcneill return NULL; 1681 1.17.2.2 jmcneill } 1682 1.17.2.2 jmcneill 1683 1.17.2.2 jmcneill void 1684 1.17.2.2 jmcneill radeonfb_pllwriteupdate(struct radeonfb_softc *sc, int crtc) 1685 1.17.2.2 jmcneill { 1686 1.17.2.2 jmcneill if (crtc) { 1687 1.17.2.2 jmcneill while (GETPLL(sc, RADEON_P2PLL_REF_DIV) & 1688 1.17.2.2 jmcneill RADEON_P2PLL_ATOMIC_UPDATE_R); 1689 1.17.2.2 jmcneill SETPLL(sc, RADEON_P2PLL_REF_DIV, RADEON_P2PLL_ATOMIC_UPDATE_W); 1690 1.17.2.2 jmcneill } else { 1691 1.17.2.2 jmcneill while (GETPLL(sc, RADEON_PPLL_REF_DIV) & 1692 1.17.2.2 jmcneill RADEON_PPLL_ATOMIC_UPDATE_R); 1693 1.17.2.2 jmcneill SETPLL(sc, RADEON_PPLL_REF_DIV, RADEON_PPLL_ATOMIC_UPDATE_W); 1694 1.17.2.2 jmcneill } 1695 1.17.2.2 jmcneill } 1696 1.17.2.2 jmcneill 1697 1.17.2.2 jmcneill void 1698 1.17.2.2 jmcneill radeonfb_pllwaitatomicread(struct radeonfb_softc *sc, int crtc) 1699 1.17.2.2 jmcneill { 1700 1.17.2.2 jmcneill int i; 1701 1.17.2.2 jmcneill 1702 1.17.2.2 jmcneill for (i = 10000; i; i--) { 1703 1.17.2.2 jmcneill if (crtc) { 1704 1.17.2.2 jmcneill if (GETPLL(sc, RADEON_P2PLL_REF_DIV) & 1705 1.17.2.2 jmcneill RADEON_P2PLL_ATOMIC_UPDATE_R) 1706 1.17.2.2 jmcneill break; 1707 1.17.2.2 jmcneill } else { 1708 1.17.2.2 jmcneill if (GETPLL(sc, RADEON_PPLL_REF_DIV) & 1709 1.17.2.2 jmcneill RADEON_PPLL_ATOMIC_UPDATE_R) 1710 1.17.2.2 jmcneill break; 1711 1.17.2.2 jmcneill } 1712 1.17.2.2 jmcneill } 1713 1.17.2.2 jmcneill } 1714 1.17.2.2 jmcneill 1715 1.17.2.2 jmcneill void 1716 1.17.2.2 jmcneill radeonfb_program_vclk(struct radeonfb_softc *sc, int dotclock, int crtc) 1717 1.17.2.2 jmcneill { 1718 1.17.2.2 jmcneill uint32_t pbit = 0; 1719 1.17.2.2 jmcneill uint32_t feed = 0; 1720 1.17.2.2 jmcneill uint32_t data; 1721 1.17.2.2 jmcneill #if 1 1722 1.17.2.2 jmcneill int i; 1723 1.17.2.2 jmcneill #endif 1724 1.17.2.2 jmcneill 1725 1.17.2.2 jmcneill radeonfb_calc_dividers(sc, dotclock, &pbit, &feed); 1726 1.17.2.2 jmcneill 1727 1.17.2.2 jmcneill if (crtc == 0) { 1728 1.17.2.2 jmcneill 1729 1.17.2.2 jmcneill /* XXXX: mobility workaround missing */ 1730 1.17.2.2 jmcneill /* XXXX: R300 stuff missing */ 1731 1.17.2.2 jmcneill 1732 1.17.2.2 jmcneill PATCHPLL(sc, RADEON_VCLK_ECP_CNTL, 1733 1.17.2.2 jmcneill RADEON_VCLK_SRC_SEL_CPUCLK, 1734 1.17.2.2 jmcneill ~RADEON_VCLK_SRC_SEL_MASK); 1735 1.17.2.2 jmcneill 1736 1.17.2.2 jmcneill /* put vclk into reset, use atomic updates */ 1737 1.17.2.2 jmcneill SETPLL(sc, RADEON_PPLL_CNTL, 1738 1.17.2.2 jmcneill RADEON_PPLL_REFCLK_SEL | 1739 1.17.2.2 jmcneill RADEON_PPLL_FBCLK_SEL | 1740 1.17.2.2 jmcneill RADEON_PPLL_RESET | 1741 1.17.2.2 jmcneill RADEON_PPLL_ATOMIC_UPDATE_EN | 1742 1.17.2.2 jmcneill RADEON_PPLL_VGA_ATOMIC_UPDATE_EN); 1743 1.17.2.2 jmcneill 1744 1.17.2.2 jmcneill /* select clock 3 */ 1745 1.17.2.2 jmcneill #if 0 1746 1.17.2.2 jmcneill PATCH32(sc, RADEON_CLOCK_CNTL_INDEX, RADEON_PLL_DIV_SEL, 1747 1.17.2.2 jmcneill ~RADEON_PLL_DIV_SEL); 1748 1.17.2.2 jmcneill #else 1749 1.17.2.2 jmcneill PATCH32(sc, RADEON_CLOCK_CNTL_INDEX, 0, 1750 1.17.2.2 jmcneill ~RADEON_PLL_DIV_SEL); 1751 1.17.2.2 jmcneill #endif 1752 1.17.2.2 jmcneill 1753 1.17.2.2 jmcneill /* XXX: R300 family -- program divider differently? */ 1754 1.17.2.2 jmcneill 1755 1.17.2.2 jmcneill /* program reference divider */ 1756 1.17.2.2 jmcneill PATCHPLL(sc, RADEON_PPLL_REF_DIV, sc->sc_refdiv, 1757 1.17.2.2 jmcneill ~RADEON_PPLL_REF_DIV_MASK); 1758 1.17.2.2 jmcneill PRINTPLL(RADEON_PPLL_REF_DIV); 1759 1.17.2.2 jmcneill 1760 1.17.2.2 jmcneill #if 0 1761 1.17.2.2 jmcneill data = GETPLL(sc, RADEON_PPLL_DIV_3); 1762 1.17.2.2 jmcneill data &= ~(RADEON_PPLL_FB3_DIV_MASK | 1763 1.17.2.2 jmcneill RADEON_PPLL_POST3_DIV_MASK); 1764 1.17.2.2 jmcneill data |= pbit; 1765 1.17.2.2 jmcneill data |= (feed & RADEON_PPLL_FB3_DIV_MASK); 1766 1.17.2.2 jmcneill PUTPLL(sc, RADEON_PPLL_DIV_3, data); 1767 1.17.2.2 jmcneill #else 1768 1.17.2.2 jmcneill for (i = 0; i < 4; i++) { 1769 1.17.2.2 jmcneill } 1770 1.17.2.2 jmcneill #endif 1771 1.17.2.2 jmcneill 1772 1.17.2.2 jmcneill /* use the atomic update */ 1773 1.17.2.2 jmcneill radeonfb_pllwriteupdate(sc, crtc); 1774 1.17.2.2 jmcneill 1775 1.17.2.2 jmcneill /* and wait for it to complete */ 1776 1.17.2.2 jmcneill radeonfb_pllwaitatomicread(sc, crtc); 1777 1.17.2.2 jmcneill 1778 1.17.2.2 jmcneill /* program HTOTAL (why?) */ 1779 1.17.2.2 jmcneill PUTPLL(sc, RADEON_HTOTAL_CNTL, 0); 1780 1.17.2.2 jmcneill 1781 1.17.2.2 jmcneill /* drop reset */ 1782 1.17.2.2 jmcneill CLRPLL(sc, RADEON_PPLL_CNTL, 1783 1.17.2.2 jmcneill RADEON_PPLL_RESET | RADEON_PPLL_SLEEP | 1784 1.17.2.2 jmcneill RADEON_PPLL_ATOMIC_UPDATE_EN | 1785 1.17.2.2 jmcneill RADEON_PPLL_VGA_ATOMIC_UPDATE_EN); 1786 1.17.2.2 jmcneill 1787 1.17.2.2 jmcneill PRINTPLL(RADEON_PPLL_CNTL); 1788 1.17.2.2 jmcneill 1789 1.17.2.2 jmcneill /* give clock time to lock */ 1790 1.17.2.2 jmcneill delay(50000); 1791 1.17.2.2 jmcneill 1792 1.17.2.2 jmcneill PATCHPLL(sc, RADEON_VCLK_ECP_CNTL, 1793 1.17.2.2 jmcneill RADEON_VCLK_SRC_SEL_PPLLCLK, 1794 1.17.2.2 jmcneill ~RADEON_VCLK_SRC_SEL_MASK); 1795 1.17.2.2 jmcneill 1796 1.17.2.2 jmcneill } else { 1797 1.17.2.2 jmcneill 1798 1.17.2.2 jmcneill PATCHPLL(sc, RADEON_PIXCLKS_CNTL, 1799 1.17.2.2 jmcneill RADEON_PIX2CLK_SRC_SEL_CPUCLK, 1800 1.17.2.2 jmcneill ~RADEON_PIX2CLK_SRC_SEL_MASK); 1801 1.17.2.2 jmcneill 1802 1.17.2.2 jmcneill /* put vclk into reset, use atomic updates */ 1803 1.17.2.2 jmcneill SETPLL(sc, RADEON_P2PLL_CNTL, 1804 1.17.2.2 jmcneill RADEON_P2PLL_RESET | 1805 1.17.2.2 jmcneill RADEON_P2PLL_ATOMIC_UPDATE_EN | 1806 1.17.2.2 jmcneill RADEON_P2PLL_VGA_ATOMIC_UPDATE_EN); 1807 1.17.2.2 jmcneill 1808 1.17.2.2 jmcneill /* XXX: R300 family -- program divider differently? */ 1809 1.17.2.2 jmcneill 1810 1.17.2.2 jmcneill /* program reference divider */ 1811 1.17.2.2 jmcneill PATCHPLL(sc, RADEON_P2PLL_REF_DIV, sc->sc_refdiv, 1812 1.17.2.2 jmcneill ~RADEON_P2PLL_REF_DIV_MASK); 1813 1.17.2.2 jmcneill 1814 1.17.2.2 jmcneill /* program feedback and post dividers */ 1815 1.17.2.2 jmcneill data = GETPLL(sc, RADEON_P2PLL_DIV_0); 1816 1.17.2.2 jmcneill data &= ~(RADEON_P2PLL_FB0_DIV_MASK | 1817 1.17.2.2 jmcneill RADEON_P2PLL_POST0_DIV_MASK); 1818 1.17.2.2 jmcneill data |= pbit; 1819 1.17.2.2 jmcneill data |= (feed & RADEON_P2PLL_FB0_DIV_MASK); 1820 1.17.2.2 jmcneill PUTPLL(sc, RADEON_P2PLL_DIV_0, data); 1821 1.17.2.2 jmcneill 1822 1.17.2.2 jmcneill /* use the atomic update */ 1823 1.17.2.2 jmcneill radeonfb_pllwriteupdate(sc, crtc); 1824 1.17.2.2 jmcneill 1825 1.17.2.2 jmcneill /* and wait for it to complete */ 1826 1.17.2.2 jmcneill radeonfb_pllwaitatomicread(sc, crtc); 1827 1.17.2.2 jmcneill 1828 1.17.2.2 jmcneill /* program HTOTAL (why?) */ 1829 1.17.2.2 jmcneill PUTPLL(sc, RADEON_HTOTAL2_CNTL, 0); 1830 1.17.2.2 jmcneill 1831 1.17.2.2 jmcneill /* drop reset */ 1832 1.17.2.2 jmcneill CLRPLL(sc, RADEON_P2PLL_CNTL, 1833 1.17.2.2 jmcneill RADEON_P2PLL_RESET | RADEON_P2PLL_SLEEP | 1834 1.17.2.2 jmcneill RADEON_P2PLL_ATOMIC_UPDATE_EN | 1835 1.17.2.2 jmcneill RADEON_P2PLL_VGA_ATOMIC_UPDATE_EN); 1836 1.17.2.2 jmcneill 1837 1.17.2.2 jmcneill /* allow time for clock to lock */ 1838 1.17.2.2 jmcneill delay(50000); 1839 1.17.2.2 jmcneill 1840 1.17.2.2 jmcneill PATCHPLL(sc, RADEON_PIXCLKS_CNTL, 1841 1.17.2.2 jmcneill RADEON_PIX2CLK_SRC_SEL_P2PLLCLK, 1842 1.17.2.2 jmcneill ~RADEON_PIX2CLK_SRC_SEL_MASK); 1843 1.17.2.2 jmcneill } 1844 1.17.2.2 jmcneill PRINTREG(RADEON_CRTC_MORE_CNTL); 1845 1.17.2.2 jmcneill } 1846 1.17.2.2 jmcneill 1847 1.17.2.2 jmcneill void 1848 1.17.2.2 jmcneill radeonfb_modeswitch(struct radeonfb_display *dp) 1849 1.17.2.2 jmcneill { 1850 1.17.2.2 jmcneill struct radeonfb_softc *sc = dp->rd_softc; 1851 1.17.2.2 jmcneill int i; 1852 1.17.2.2 jmcneill 1853 1.17.2.2 jmcneill /* blank the display while we switch modes */ 1854 1.17.2.2 jmcneill //radeonfb_blank(dp, 1); 1855 1.17.2.2 jmcneill 1856 1.17.2.2 jmcneill #if 0 1857 1.17.2.2 jmcneill SET32(sc, RADEON_CRTC_EXT_CNTL, 1858 1.17.2.2 jmcneill RADEON_CRTC_VSYNC_DIS | RADEON_CRTC_HSYNC_DIS | 1859 1.17.2.2 jmcneill RADEON_CRTC_DISPLAY_DIS /* | RADEON_CRTC_DISP_REQ_EN_B */); 1860 1.17.2.2 jmcneill #endif 1861 1.17.2.2 jmcneill 1862 1.17.2.2 jmcneill /* these registers might get in the way... */ 1863 1.17.2.2 jmcneill PUT32(sc, RADEON_OVR_CLR, 0); 1864 1.17.2.2 jmcneill PUT32(sc, RADEON_OVR_WID_LEFT_RIGHT, 0); 1865 1.17.2.2 jmcneill PUT32(sc, RADEON_OVR_WID_TOP_BOTTOM, 0); 1866 1.17.2.2 jmcneill PUT32(sc, RADEON_OV0_SCALE_CNTL, 0); 1867 1.17.2.2 jmcneill PUT32(sc, RADEON_SUBPIC_CNTL, 0); 1868 1.17.2.2 jmcneill PUT32(sc, RADEON_VIPH_CONTROL, 0); 1869 1.17.2.2 jmcneill PUT32(sc, RADEON_I2C_CNTL_1, 0); 1870 1.17.2.2 jmcneill PUT32(sc, RADEON_GEN_INT_CNTL, 0); 1871 1.17.2.2 jmcneill PUT32(sc, RADEON_CAP0_TRIG_CNTL, 0); 1872 1.17.2.2 jmcneill PUT32(sc, RADEON_CAP1_TRIG_CNTL, 0); 1873 1.17.2.2 jmcneill PUT32(sc, RADEON_SURFACE_CNTL, 0); 1874 1.17.2.2 jmcneill 1875 1.17.2.2 jmcneill for (i = 0; i < dp->rd_ncrtcs; i++) 1876 1.17.2.2 jmcneill radeonfb_setcrtc(dp, i); 1877 1.17.2.2 jmcneill 1878 1.17.2.2 jmcneill /* activate the display */ 1879 1.17.2.2 jmcneill //radeonfb_blank(dp, 0); 1880 1.17.2.2 jmcneill } 1881 1.17.2.2 jmcneill 1882 1.17.2.2 jmcneill void 1883 1.17.2.2 jmcneill radeonfb_setcrtc(struct radeonfb_display *dp, int index) 1884 1.17.2.2 jmcneill { 1885 1.17.2.2 jmcneill int crtc; 1886 1.17.2.2 jmcneill struct videomode *mode; 1887 1.17.2.2 jmcneill struct radeonfb_softc *sc; 1888 1.17.2.2 jmcneill struct radeonfb_crtc *cp; 1889 1.17.2.2 jmcneill uint32_t v; 1890 1.17.2.2 jmcneill uint32_t gencntl; 1891 1.17.2.2 jmcneill uint32_t htotaldisp; 1892 1.17.2.2 jmcneill uint32_t hsyncstrt; 1893 1.17.2.2 jmcneill uint32_t vtotaldisp; 1894 1.17.2.2 jmcneill uint32_t vsyncstrt; 1895 1.17.2.2 jmcneill uint32_t fphsyncstrt; 1896 1.17.2.2 jmcneill uint32_t fpvsyncstrt; 1897 1.17.2.2 jmcneill uint32_t fphtotaldisp; 1898 1.17.2.2 jmcneill uint32_t fpvtotaldisp; 1899 1.17.2.2 jmcneill uint32_t pitch; 1900 1.17.2.2 jmcneill 1901 1.17.2.2 jmcneill sc = dp->rd_softc; 1902 1.17.2.2 jmcneill cp = &dp->rd_crtcs[index]; 1903 1.17.2.2 jmcneill crtc = cp->rc_number; 1904 1.17.2.2 jmcneill mode = &cp->rc_videomode; 1905 1.17.2.2 jmcneill 1906 1.17.2.2 jmcneill #if 1 1907 1.17.2.2 jmcneill pitch = (((dp->rd_virtx * dp->rd_bpp) + ((dp->rd_bpp * 8) - 1)) / 1908 1.17.2.2 jmcneill (dp->rd_bpp * 8)); 1909 1.17.2.2 jmcneill #else 1910 1.17.2.2 jmcneill pitch = (((sc->sc_maxx * sc->sc_maxbpp) + ((sc->sc_maxbpp * 8) - 1)) / 1911 1.17.2.2 jmcneill (sc->sc_maxbpp * 8)); 1912 1.17.2.2 jmcneill #endif 1913 1.17.2.2 jmcneill //pitch = pitch | (pitch << 16); 1914 1.17.2.2 jmcneill 1915 1.17.2.2 jmcneill switch (crtc) { 1916 1.17.2.2 jmcneill case 0: 1917 1.17.2.2 jmcneill gencntl = RADEON_CRTC_GEN_CNTL; 1918 1.17.2.2 jmcneill htotaldisp = RADEON_CRTC_H_TOTAL_DISP; 1919 1.17.2.2 jmcneill hsyncstrt = RADEON_CRTC_H_SYNC_STRT_WID; 1920 1.17.2.2 jmcneill vtotaldisp = RADEON_CRTC_V_TOTAL_DISP; 1921 1.17.2.2 jmcneill vsyncstrt = RADEON_CRTC_V_SYNC_STRT_WID; 1922 1.17.2.2 jmcneill fpvsyncstrt = RADEON_FP_V_SYNC_STRT_WID; 1923 1.17.2.2 jmcneill fphsyncstrt = RADEON_FP_H_SYNC_STRT_WID; 1924 1.17.2.2 jmcneill fpvtotaldisp = RADEON_FP_CRTC_V_TOTAL_DISP; 1925 1.17.2.2 jmcneill fphtotaldisp = RADEON_FP_CRTC_H_TOTAL_DISP; 1926 1.17.2.2 jmcneill break; 1927 1.17.2.2 jmcneill case 1: 1928 1.17.2.2 jmcneill gencntl = RADEON_CRTC2_GEN_CNTL; 1929 1.17.2.2 jmcneill htotaldisp = RADEON_CRTC2_H_TOTAL_DISP; 1930 1.17.2.2 jmcneill hsyncstrt = RADEON_CRTC2_H_SYNC_STRT_WID; 1931 1.17.2.2 jmcneill vtotaldisp = RADEON_CRTC2_V_TOTAL_DISP; 1932 1.17.2.2 jmcneill vsyncstrt = RADEON_CRTC2_V_SYNC_STRT_WID; 1933 1.17.2.2 jmcneill fpvsyncstrt = RADEON_FP_V2_SYNC_STRT_WID; 1934 1.17.2.2 jmcneill fphsyncstrt = RADEON_FP_H2_SYNC_STRT_WID; 1935 1.17.2.2 jmcneill fpvtotaldisp = RADEON_FP_CRTC2_V_TOTAL_DISP; 1936 1.17.2.2 jmcneill fphtotaldisp = RADEON_FP_CRTC2_H_TOTAL_DISP; 1937 1.17.2.2 jmcneill break; 1938 1.17.2.2 jmcneill default: 1939 1.17.2.2 jmcneill panic("Bad CRTC!"); 1940 1.17.2.2 jmcneill break; 1941 1.17.2.2 jmcneill } 1942 1.17.2.2 jmcneill 1943 1.17.2.2 jmcneill /* 1944 1.17.2.2 jmcneill * CRTC_GEN_CNTL - depth, accelerator mode, etc. 1945 1.17.2.2 jmcneill */ 1946 1.17.2.2 jmcneill /* only bother with 32bpp and 8bpp */ 1947 1.17.2.2 jmcneill v = dp->rd_format << RADEON_CRTC_PIX_WIDTH_SHIFT; 1948 1.17.2.2 jmcneill 1949 1.17.2.2 jmcneill if (crtc == 1) { 1950 1.17.2.2 jmcneill v |= RADEON_CRTC2_CRT2_ON | RADEON_CRTC2_EN; 1951 1.17.2.2 jmcneill } else { 1952 1.17.2.2 jmcneill v |= RADEON_CRTC_EXT_DISP_EN | RADEON_CRTC_EN; 1953 1.17.2.2 jmcneill } 1954 1.17.2.2 jmcneill 1955 1.17.2.2 jmcneill if (mode->flags & VID_DBLSCAN) 1956 1.17.2.2 jmcneill v |= RADEON_CRTC2_DBL_SCAN_EN; 1957 1.17.2.2 jmcneill 1958 1.17.2.2 jmcneill if (mode->flags & VID_INTERLACE) 1959 1.17.2.2 jmcneill v |= RADEON_CRTC2_INTERLACE_EN; 1960 1.17.2.2 jmcneill 1961 1.17.2.2 jmcneill if (mode->flags & VID_CSYNC) { 1962 1.17.2.2 jmcneill v |= RADEON_CRTC2_CSYNC_EN; 1963 1.17.2.2 jmcneill if (crtc == 1) 1964 1.17.2.2 jmcneill v |= RADEON_CRTC2_VSYNC_TRISTAT; 1965 1.17.2.2 jmcneill } 1966 1.17.2.2 jmcneill 1967 1.17.2.2 jmcneill PUT32(sc, gencntl, v); 1968 1.17.2.2 jmcneill DPRINTF(("CRTC%s_GEN_CNTL = %08x\n", crtc ? "2" : "", v)); 1969 1.17.2.2 jmcneill 1970 1.17.2.2 jmcneill /* 1971 1.17.2.2 jmcneill * CRTC_EXT_CNTL - preserve disable flags, set ATI linear and EXT_CNT 1972 1.17.2.2 jmcneill */ 1973 1.17.2.2 jmcneill v = GET32(sc, RADEON_CRTC_EXT_CNTL); 1974 1.17.2.2 jmcneill if (crtc == 0) { 1975 1.17.2.2 jmcneill v &= (RADEON_CRTC_VSYNC_DIS | RADEON_CRTC_HSYNC_DIS | 1976 1.17.2.2 jmcneill RADEON_CRTC_DISPLAY_DIS); 1977 1.17.2.2 jmcneill v |= RADEON_XCRT_CNT_EN | RADEON_VGA_ATI_LINEAR; 1978 1.17.2.2 jmcneill if (mode->flags & VID_CSYNC) 1979 1.17.2.2 jmcneill v |= RADEON_CRTC_VSYNC_TRISTAT; 1980 1.17.2.2 jmcneill } 1981 1.17.2.2 jmcneill /* unconditional turn on CRT, in case first CRTC is DFP */ 1982 1.17.2.2 jmcneill v |= RADEON_CRTC_CRT_ON; 1983 1.17.2.2 jmcneill PUT32(sc, RADEON_CRTC_EXT_CNTL, v); 1984 1.17.2.2 jmcneill PRINTREG(RADEON_CRTC_EXT_CNTL); 1985 1.17.2.2 jmcneill 1986 1.17.2.2 jmcneill /* 1987 1.17.2.2 jmcneill * H_TOTAL_DISP 1988 1.17.2.2 jmcneill */ 1989 1.17.2.2 jmcneill v = ((mode->hdisplay / 8) - 1) << 16; 1990 1.17.2.2 jmcneill v |= (mode->htotal / 8) - 1; 1991 1.17.2.2 jmcneill PUT32(sc, htotaldisp, v); 1992 1.17.2.2 jmcneill DPRINTF(("CRTC%s_H_TOTAL_DISP = %08x\n", crtc ? "2" : "", v)); 1993 1.17.2.2 jmcneill PUT32(sc, fphtotaldisp, v); 1994 1.17.2.2 jmcneill DPRINTF(("FP_H%s_TOTAL_DISP = %08x\n", crtc ? "2" : "", v)); 1995 1.17.2.2 jmcneill 1996 1.17.2.2 jmcneill /* 1997 1.17.2.2 jmcneill * H_SYNC_STRT_WID 1998 1.17.2.2 jmcneill */ 1999 1.17.2.2 jmcneill v = (((mode->hsync_end - mode->hsync_start) / 8) << 16); 2000 1.17.2.2 jmcneill v |= mode->hsync_start; 2001 1.17.2.2 jmcneill if (mode->flags & VID_NHSYNC) 2002 1.17.2.2 jmcneill v |= RADEON_CRTC_H_SYNC_POL; 2003 1.17.2.2 jmcneill PUT32(sc, hsyncstrt, v); 2004 1.17.2.2 jmcneill DPRINTF(("CRTC%s_H_SYNC_STRT_WID = %08x\n", crtc ? "2" : "", v)); 2005 1.17.2.2 jmcneill PUT32(sc, fphsyncstrt, v); 2006 1.17.2.2 jmcneill DPRINTF(("FP_H%s_SYNC_STRT_WID = %08x\n", crtc ? "2" : "", v)); 2007 1.17.2.2 jmcneill 2008 1.17.2.2 jmcneill /* 2009 1.17.2.2 jmcneill * V_TOTAL_DISP 2010 1.17.2.2 jmcneill */ 2011 1.17.2.2 jmcneill v = ((mode->vdisplay - 1) << 16); 2012 1.17.2.2 jmcneill v |= (mode->vtotal - 1); 2013 1.17.2.2 jmcneill PUT32(sc, vtotaldisp, v); 2014 1.17.2.2 jmcneill DPRINTF(("CRTC%s_V_TOTAL_DISP = %08x\n", crtc ? "2" : "", v)); 2015 1.17.2.2 jmcneill PUT32(sc, fpvtotaldisp, v); 2016 1.17.2.2 jmcneill DPRINTF(("FP_V%s_TOTAL_DISP = %08x\n", crtc ? "2" : "", v)); 2017 1.17.2.2 jmcneill 2018 1.17.2.2 jmcneill /* 2019 1.17.2.2 jmcneill * V_SYNC_STRT_WID 2020 1.17.2.2 jmcneill */ 2021 1.17.2.2 jmcneill v = ((mode->vsync_end - mode->vsync_start) << 16); 2022 1.17.2.2 jmcneill v |= (mode->vsync_start - 1); 2023 1.17.2.2 jmcneill if (mode->flags & VID_NVSYNC) 2024 1.17.2.2 jmcneill v |= RADEON_CRTC_V_SYNC_POL; 2025 1.17.2.2 jmcneill PUT32(sc, vsyncstrt, v); 2026 1.17.2.2 jmcneill DPRINTF(("CRTC%s_V_SYNC_STRT_WID = %08x\n", crtc ? "2" : "", v)); 2027 1.17.2.2 jmcneill PUT32(sc, fpvsyncstrt, v); 2028 1.17.2.2 jmcneill DPRINTF(("FP_V%s_SYNC_STRT_WID = %08x\n", crtc ? "2" : "", v)); 2029 1.17.2.2 jmcneill 2030 1.17.2.2 jmcneill radeonfb_program_vclk(sc, mode->dot_clock, crtc); 2031 1.17.2.2 jmcneill 2032 1.17.2.2 jmcneill switch (crtc) { 2033 1.17.2.2 jmcneill case 0: 2034 1.17.2.2 jmcneill PUT32(sc, RADEON_CRTC_OFFSET, 0); 2035 1.17.2.2 jmcneill PUT32(sc, RADEON_CRTC_OFFSET_CNTL, 0); 2036 1.17.2.2 jmcneill PUT32(sc, RADEON_CRTC_PITCH, pitch); 2037 1.17.2.2 jmcneill CLR32(sc, RADEON_DISP_MERGE_CNTL, RADEON_DISP_RGB_OFFSET_EN); 2038 1.17.2.2 jmcneill 2039 1.17.2.2 jmcneill CLR32(sc, RADEON_CRTC_EXT_CNTL, 2040 1.17.2.2 jmcneill RADEON_CRTC_VSYNC_DIS | RADEON_CRTC_HSYNC_DIS | 2041 1.17.2.2 jmcneill RADEON_CRTC_DISPLAY_DIS /* | RADEON_CRTC_DISP_REQ_EN_B */); 2042 1.17.2.2 jmcneill CLR32(sc, RADEON_CRTC_GEN_CNTL, RADEON_CRTC_DISP_REQ_EN_B); 2043 1.17.2.2 jmcneill PRINTREG(RADEON_CRTC_EXT_CNTL); 2044 1.17.2.2 jmcneill PRINTREG(RADEON_CRTC_GEN_CNTL); 2045 1.17.2.2 jmcneill PRINTREG(RADEON_CLOCK_CNTL_INDEX); 2046 1.17.2.2 jmcneill break; 2047 1.17.2.2 jmcneill 2048 1.17.2.2 jmcneill case 1: 2049 1.17.2.2 jmcneill PUT32(sc, RADEON_CRTC2_OFFSET, 0); 2050 1.17.2.2 jmcneill PUT32(sc, RADEON_CRTC2_OFFSET_CNTL, 0); 2051 1.17.2.2 jmcneill PUT32(sc, RADEON_CRTC2_PITCH, pitch); 2052 1.17.2.2 jmcneill CLR32(sc, RADEON_DISP2_MERGE_CNTL, RADEON_DISP2_RGB_OFFSET_EN); 2053 1.17.2.2 jmcneill CLR32(sc, RADEON_CRTC2_GEN_CNTL, 2054 1.17.2.2 jmcneill RADEON_CRTC2_VSYNC_DIS | 2055 1.17.2.2 jmcneill RADEON_CRTC2_HSYNC_DIS | 2056 1.17.2.2 jmcneill RADEON_CRTC2_DISP_DIS | RADEON_CRTC2_DISP_REQ_EN_B); 2057 1.17.2.2 jmcneill PRINTREG(RADEON_CRTC2_GEN_CNTL); 2058 1.17.2.2 jmcneill break; 2059 1.17.2.2 jmcneill } 2060 1.17.2.2 jmcneill } 2061 1.17.2.2 jmcneill 2062 1.17.2.2 jmcneill int 2063 1.17.2.2 jmcneill radeonfb_isblank(struct radeonfb_display *dp) 2064 1.17.2.2 jmcneill { 2065 1.17.2.2 jmcneill uint32_t reg, mask; 2066 1.17.2.2 jmcneill 2067 1.17.2.2 jmcneill if (dp->rd_crtcs[0].rc_number) { 2068 1.17.2.2 jmcneill reg = RADEON_CRTC2_GEN_CNTL; 2069 1.17.2.2 jmcneill mask = RADEON_CRTC2_DISP_DIS; 2070 1.17.2.2 jmcneill } else { 2071 1.17.2.2 jmcneill reg = RADEON_CRTC_EXT_CNTL; 2072 1.17.2.2 jmcneill mask = RADEON_CRTC_DISPLAY_DIS; 2073 1.17.2.2 jmcneill } 2074 1.17.2.2 jmcneill return ((GET32(dp->rd_softc, reg) & mask) ? 1 : 0); 2075 1.17.2.2 jmcneill } 2076 1.17.2.2 jmcneill 2077 1.17.2.2 jmcneill void 2078 1.17.2.2 jmcneill radeonfb_blank(struct radeonfb_display *dp, int blank) 2079 1.17.2.2 jmcneill { 2080 1.17.2.2 jmcneill struct radeonfb_softc *sc = dp->rd_softc; 2081 1.17.2.2 jmcneill uint32_t reg, mask; 2082 1.17.2.2 jmcneill uint32_t fpreg, fpval; 2083 1.17.2.2 jmcneill int i; 2084 1.17.2.2 jmcneill 2085 1.17.2.2 jmcneill for (i = 0; i < dp->rd_ncrtcs; i++) { 2086 1.17.2.2 jmcneill 2087 1.17.2.2 jmcneill if (dp->rd_crtcs[i].rc_number) { 2088 1.17.2.2 jmcneill reg = RADEON_CRTC2_GEN_CNTL; 2089 1.17.2.2 jmcneill mask = RADEON_CRTC2_DISP_DIS; 2090 1.17.2.2 jmcneill fpreg = RADEON_FP2_GEN_CNTL; 2091 1.17.2.2 jmcneill fpval = RADEON_FP2_ON; 2092 1.17.2.2 jmcneill } else { 2093 1.17.2.2 jmcneill reg = RADEON_CRTC_EXT_CNTL; 2094 1.17.2.2 jmcneill mask = RADEON_CRTC_DISPLAY_DIS; 2095 1.17.2.2 jmcneill fpreg = RADEON_FP_GEN_CNTL; 2096 1.17.2.2 jmcneill fpval = RADEON_FP_FPON; 2097 1.17.2.2 jmcneill } 2098 1.17.2.2 jmcneill 2099 1.17.2.2 jmcneill if (blank) { 2100 1.17.2.2 jmcneill SET32(sc, reg, mask); 2101 1.17.2.2 jmcneill CLR32(sc, fpreg, fpval); 2102 1.17.2.2 jmcneill } else { 2103 1.17.2.2 jmcneill CLR32(sc, reg, mask); 2104 1.17.2.2 jmcneill SET32(sc, fpreg, fpval); 2105 1.17.2.2 jmcneill } 2106 1.17.2.2 jmcneill } 2107 1.17.2.2 jmcneill PRINTREG(RADEON_FP_GEN_CNTL); 2108 1.17.2.2 jmcneill PRINTREG(RADEON_FP2_GEN_CNTL); 2109 1.17.2.2 jmcneill } 2110 1.17.2.2 jmcneill 2111 1.17.2.2 jmcneill void 2112 1.17.2.2 jmcneill radeonfb_init_screen(void *cookie, struct vcons_screen *scr, int existing, 2113 1.17.2.2 jmcneill long *defattr) 2114 1.17.2.2 jmcneill { 2115 1.17.2.2 jmcneill struct radeonfb_display *dp = cookie; 2116 1.17.2.2 jmcneill struct rasops_info *ri = &scr->scr_ri; 2117 1.17.2.2 jmcneill 2118 1.17.2.2 jmcneill /* initialize font subsystem */ 2119 1.17.2.2 jmcneill wsfont_init(); 2120 1.17.2.2 jmcneill 2121 1.17.2.2 jmcneill DPRINTF(("init screen called, existing %d\n", existing)); 2122 1.17.2.2 jmcneill 2123 1.17.2.2 jmcneill ri->ri_depth = dp->rd_bpp; 2124 1.17.2.2 jmcneill ri->ri_width = dp->rd_virtx; 2125 1.17.2.2 jmcneill ri->ri_height = dp->rd_virty; 2126 1.17.2.2 jmcneill ri->ri_stride = dp->rd_stride; 2127 1.17.2.2 jmcneill ri->ri_flg = RI_CENTER; 2128 1.17.2.2 jmcneill ri->ri_bits = (void *)dp->rd_fbptr; 2129 1.17.2.2 jmcneill 2130 1.17.2.2 jmcneill /* XXX: 32 bpp only */ 2131 1.17.2.2 jmcneill /* this is rgb in "big-endian order..." */ 2132 1.17.2.2 jmcneill ri->ri_rnum = 8; 2133 1.17.2.2 jmcneill ri->ri_gnum = 8; 2134 1.17.2.2 jmcneill ri->ri_bnum = 8; 2135 1.17.2.2 jmcneill ri->ri_rpos = 16; 2136 1.17.2.2 jmcneill ri->ri_gpos = 8; 2137 1.17.2.2 jmcneill ri->ri_bpos = 0; 2138 1.17.2.2 jmcneill 2139 1.17.2.2 jmcneill if (existing) { 2140 1.17.2.2 jmcneill ri->ri_flg |= RI_CLEAR; 2141 1.17.2.2 jmcneill 2142 1.17.2.2 jmcneill /* start a modeswitch now */ 2143 1.17.2.2 jmcneill radeonfb_modeswitch(dp); 2144 1.17.2.2 jmcneill } 2145 1.17.2.2 jmcneill 2146 1.17.2.2 jmcneill /* 2147 1.17.2.2 jmcneill * XXX: font selection should be based on properties, with some 2148 1.17.2.2 jmcneill * normal/reasonable default. 2149 1.17.2.2 jmcneill */ 2150 1.17.2.2 jmcneill ri->ri_caps = WSSCREEN_WSCOLORS; 2151 1.17.2.2 jmcneill 2152 1.17.2.2 jmcneill /* initialize and look for an initial font */ 2153 1.17.2.2 jmcneill rasops_init(ri, dp->rd_virty/8, dp->rd_virtx/8); 2154 1.17.2.2 jmcneill 2155 1.17.2.2 jmcneill rasops_reconfig(ri, dp->rd_virty / ri->ri_font->fontheight, 2156 1.17.2.2 jmcneill dp->rd_virtx / ri->ri_font->fontwidth); 2157 1.17.2.2 jmcneill 2158 1.17.2.2 jmcneill /* enable acceleration */ 2159 1.17.2.2 jmcneill ri->ri_ops.copyrows = radeonfb_copyrows; 2160 1.17.2.2 jmcneill ri->ri_ops.copycols = radeonfb_copycols; 2161 1.17.2.2 jmcneill ri->ri_ops.eraserows = radeonfb_eraserows; 2162 1.17.2.2 jmcneill ri->ri_ops.erasecols = radeonfb_erasecols; 2163 1.17.2.2 jmcneill ri->ri_ops.allocattr = radeonfb_allocattr; 2164 1.17.2.2 jmcneill if (!IS_R300(dp->rd_softc)) { 2165 1.17.2.2 jmcneill ri->ri_ops.putchar = radeonfb_putchar; 2166 1.17.2.2 jmcneill } 2167 1.17.2.2 jmcneill ri->ri_ops.cursor = radeonfb_cursor; 2168 1.17.2.2 jmcneill } 2169 1.17.2.2 jmcneill 2170 1.17.2.2 jmcneill void 2171 1.17.2.2 jmcneill radeonfb_set_fbloc(struct radeonfb_softc *sc) 2172 1.17.2.2 jmcneill { 2173 1.17.2.2 jmcneill uint32_t gen, ext, gen2 = 0; 2174 1.17.2.2 jmcneill uint32_t agploc, aperbase, apersize, mcfbloc; 2175 1.17.2.2 jmcneill 2176 1.17.2.2 jmcneill gen = GET32(sc, RADEON_CRTC_GEN_CNTL); 2177 1.17.2.2 jmcneill ext = GET32(sc, RADEON_CRTC_EXT_CNTL); 2178 1.17.2.2 jmcneill agploc = GET32(sc, RADEON_MC_AGP_LOCATION); 2179 1.17.2.2 jmcneill aperbase = GET32(sc, RADEON_CONFIG_APER_0_BASE); 2180 1.17.2.2 jmcneill apersize = GET32(sc, RADEON_CONFIG_APER_SIZE); 2181 1.17.2.2 jmcneill 2182 1.17.2.2 jmcneill PUT32(sc, RADEON_CRTC_GEN_CNTL, gen | RADEON_CRTC_DISP_REQ_EN_B); 2183 1.17.2.2 jmcneill PUT32(sc, RADEON_CRTC_EXT_CNTL, ext | RADEON_CRTC_DISPLAY_DIS); 2184 1.17.2.2 jmcneill //PUT32(sc, RADEON_CRTC_GEN_CNTL, gen | RADEON_CRTC_DISPLAY_DIS); 2185 1.17.2.2 jmcneill //PUT32(sc, RADEON_CRTC_EXT_CNTL, ext | RADEON_CRTC_DISP_REQ_EN_B); 2186 1.17.2.2 jmcneill 2187 1.17.2.2 jmcneill if (HAS_CRTC2(sc)) { 2188 1.17.2.2 jmcneill gen2 = GET32(sc, RADEON_CRTC2_GEN_CNTL); 2189 1.17.2.2 jmcneill PUT32(sc, RADEON_CRTC2_GEN_CNTL, 2190 1.17.2.2 jmcneill gen2 | RADEON_CRTC2_DISP_REQ_EN_B); 2191 1.17.2.2 jmcneill } 2192 1.17.2.2 jmcneill 2193 1.17.2.2 jmcneill delay(100000); 2194 1.17.2.2 jmcneill 2195 1.17.2.2 jmcneill mcfbloc = (aperbase >> 16) | 2196 1.17.2.2 jmcneill ((aperbase + (apersize - 1)) & 0xffff0000); 2197 1.17.2.2 jmcneill 2198 1.17.2.2 jmcneill sc->sc_aperbase = (mcfbloc & 0xffff) << 16; 2199 1.17.2.2 jmcneill sc->sc_memsz = apersize; 2200 1.17.2.2 jmcneill 2201 1.17.2.2 jmcneill if (((agploc & 0xffff) << 16) != 2202 1.17.2.2 jmcneill ((mcfbloc & 0xffff0000U) + 0x10000)) { 2203 1.17.2.2 jmcneill agploc = mcfbloc & 0xffff0000U; 2204 1.17.2.2 jmcneill agploc |= ((agploc + 0x10000) >> 16); 2205 1.17.2.2 jmcneill } 2206 1.17.2.2 jmcneill 2207 1.17.2.2 jmcneill PUT32(sc, RADEON_HOST_PATH_CNTL, 0); 2208 1.17.2.2 jmcneill 2209 1.17.2.2 jmcneill PUT32(sc, RADEON_MC_FB_LOCATION, mcfbloc); 2210 1.17.2.2 jmcneill PUT32(sc, RADEON_MC_AGP_LOCATION, agploc); 2211 1.17.2.2 jmcneill 2212 1.17.2.2 jmcneill DPRINTF(("aperbase = %u\n", aperbase)); 2213 1.17.2.2 jmcneill PRINTREG(RADEON_MC_FB_LOCATION); 2214 1.17.2.2 jmcneill PRINTREG(RADEON_MC_AGP_LOCATION); 2215 1.17.2.2 jmcneill 2216 1.17.2.2 jmcneill PUT32(sc, RADEON_DISPLAY_BASE_ADDR, sc->sc_aperbase); 2217 1.17.2.2 jmcneill 2218 1.17.2.2 jmcneill if (HAS_CRTC2(sc)) 2219 1.17.2.2 jmcneill PUT32(sc, RADEON_DISPLAY2_BASE_ADDR, sc->sc_aperbase); 2220 1.17.2.2 jmcneill 2221 1.17.2.2 jmcneill PUT32(sc, RADEON_OV0_BASE_ADDR, sc->sc_aperbase); 2222 1.17.2.2 jmcneill 2223 1.17.2.2 jmcneill #if 0 2224 1.17.2.2 jmcneill /* XXX: what is this AGP garbage? :-) */ 2225 1.17.2.2 jmcneill PUT32(sc, RADEON_AGP_CNTL, 0x00100000); 2226 1.17.2.2 jmcneill #endif 2227 1.17.2.2 jmcneill 2228 1.17.2.2 jmcneill delay(100000); 2229 1.17.2.2 jmcneill 2230 1.17.2.2 jmcneill PUT32(sc, RADEON_CRTC_GEN_CNTL, gen); 2231 1.17.2.2 jmcneill PUT32(sc, RADEON_CRTC_EXT_CNTL, ext); 2232 1.17.2.2 jmcneill 2233 1.17.2.2 jmcneill if (HAS_CRTC2(sc)) 2234 1.17.2.2 jmcneill PUT32(sc, RADEON_CRTC2_GEN_CNTL, gen2); 2235 1.17.2.2 jmcneill } 2236 1.17.2.2 jmcneill 2237 1.17.2.2 jmcneill void 2238 1.17.2.2 jmcneill radeonfb_init_misc(struct radeonfb_softc *sc) 2239 1.17.2.2 jmcneill { 2240 1.17.2.2 jmcneill PUT32(sc, RADEON_BUS_CNTL, 2241 1.17.2.2 jmcneill RADEON_BUS_MASTER_DIS | 2242 1.17.2.2 jmcneill RADEON_BUS_PREFETCH_MODE_ACT | 2243 1.17.2.2 jmcneill RADEON_BUS_PCI_READ_RETRY_EN | 2244 1.17.2.2 jmcneill RADEON_BUS_PCI_WRT_RETRY_EN | 2245 1.17.2.2 jmcneill (3 << RADEON_BUS_RETRY_WS_SHIFT) | 2246 1.17.2.2 jmcneill RADEON_BUS_MSTR_RD_MULT | 2247 1.17.2.2 jmcneill RADEON_BUS_MSTR_RD_LINE | 2248 1.17.2.2 jmcneill RADEON_BUS_RD_DISCARD_EN | 2249 1.17.2.2 jmcneill RADEON_BUS_MSTR_DISCONNECT_EN | 2250 1.17.2.2 jmcneill RADEON_BUS_READ_BURST); 2251 1.17.2.2 jmcneill 2252 1.17.2.2 jmcneill PUT32(sc, RADEON_BUS_CNTL1, 0xf0); 2253 1.17.2.2 jmcneill /* PUT32(sc, RADEON_SEPROM_CNTL1, 0x09ff0000); */ 2254 1.17.2.2 jmcneill PUT32(sc, RADEON_FCP_CNTL, RADEON_FCP0_SRC_GND); 2255 1.17.2.2 jmcneill PUT32(sc, RADEON_RBBM_CNTL, 2256 1.17.2.2 jmcneill (3 << RADEON_RB_SETTLE_SHIFT) | 2257 1.17.2.2 jmcneill (4 << RADEON_ABORTCLKS_HI_SHIFT) | 2258 1.17.2.2 jmcneill (4 << RADEON_ABORTCLKS_CP_SHIFT) | 2259 1.17.2.2 jmcneill (4 << RADEON_ABORTCLKS_CFIFO_SHIFT)); 2260 1.17.2.2 jmcneill 2261 1.17.2.2 jmcneill /* XXX: figure out what these mean! */ 2262 1.17.2.2 jmcneill PUT32(sc, RADEON_AGP_CNTL, 0x00100000); 2263 1.17.2.2 jmcneill PUT32(sc, RADEON_HOST_PATH_CNTL, 0); 2264 1.17.2.2 jmcneill //PUT32(sc, RADEON_DISP_MISC_CNTL, 0x5bb00400); 2265 1.17.2.2 jmcneill 2266 1.17.2.2 jmcneill PUT32(sc, RADEON_GEN_INT_CNTL, 0); 2267 1.17.2.2 jmcneill PUT32(sc, RADEON_GEN_INT_STATUS, GET32(sc, RADEON_GEN_INT_STATUS)); 2268 1.17.2.2 jmcneill } 2269 1.17.2.2 jmcneill 2270 1.17.2.2 jmcneill /* 2271 1.17.2.2 jmcneill * This loads a linear color map for true color. 2272 1.17.2.2 jmcneill */ 2273 1.17.2.2 jmcneill void 2274 1.17.2.2 jmcneill radeonfb_init_palette(struct radeonfb_softc *sc, int crtc) 2275 1.17.2.2 jmcneill { 2276 1.17.2.2 jmcneill int i; 2277 1.17.2.2 jmcneill uint32_t vclk; 2278 1.17.2.2 jmcneill 2279 1.17.2.2 jmcneill #define DAC_WIDTH ((1 << 10) - 1) 2280 1.17.2.2 jmcneill #define CLUT_WIDTH ((1 << 8) - 1) 2281 1.17.2.2 jmcneill #define CLUT_COLOR(i) ((i * DAC_WIDTH * 2 / CLUT_WIDTH + 1) / 2) 2282 1.17.2.2 jmcneill 2283 1.17.2.2 jmcneill vclk = GETPLL(sc, RADEON_VCLK_ECP_CNTL); 2284 1.17.2.2 jmcneill PUTPLL(sc, RADEON_VCLK_ECP_CNTL, vclk & ~RADEON_PIXCLK_DAC_ALWAYS_ONb); 2285 1.17.2.2 jmcneill 2286 1.17.2.2 jmcneill if (crtc) 2287 1.17.2.2 jmcneill SET32(sc, RADEON_DAC_CNTL2, RADEON_DAC2_PALETTE_ACC_CTL); 2288 1.17.2.2 jmcneill else 2289 1.17.2.2 jmcneill CLR32(sc, RADEON_DAC_CNTL2, RADEON_DAC2_PALETTE_ACC_CTL); 2290 1.17.2.2 jmcneill 2291 1.17.2.2 jmcneill PUT32(sc, RADEON_PALETTE_INDEX, 0); 2292 1.17.2.2 jmcneill for (i = 0; i <= CLUT_WIDTH; ++i) { 2293 1.17.2.2 jmcneill PUT32(sc, RADEON_PALETTE_30_DATA, 2294 1.17.2.2 jmcneill (CLUT_COLOR(i) << 10) | 2295 1.17.2.2 jmcneill (CLUT_COLOR(i) << 20) | 2296 1.17.2.2 jmcneill (CLUT_COLOR(i))); 2297 1.17.2.2 jmcneill } 2298 1.17.2.2 jmcneill 2299 1.17.2.2 jmcneill CLR32(sc, RADEON_DAC_CNTL2, RADEON_DAC2_PALETTE_ACC_CTL); 2300 1.17.2.2 jmcneill PRINTREG(RADEON_DAC_CNTL2); 2301 1.17.2.2 jmcneill 2302 1.17.2.2 jmcneill PUTPLL(sc, RADEON_VCLK_ECP_CNTL, vclk); 2303 1.17.2.2 jmcneill } 2304 1.17.2.2 jmcneill 2305 1.17.2.2 jmcneill /* 2306 1.17.2.2 jmcneill * Bugs in some R300 hardware requires this when accessing CLOCK_CNTL_INDEX. 2307 1.17.2.2 jmcneill */ 2308 1.17.2.2 jmcneill void 2309 1.17.2.2 jmcneill radeonfb_r300cg_workaround(struct radeonfb_softc *sc) 2310 1.17.2.2 jmcneill { 2311 1.17.2.2 jmcneill uint32_t tmp, save; 2312 1.17.2.2 jmcneill 2313 1.17.2.2 jmcneill save = GET32(sc, RADEON_CLOCK_CNTL_INDEX); 2314 1.17.2.2 jmcneill tmp = save & ~(0x3f | RADEON_PLL_WR_EN); 2315 1.17.2.2 jmcneill PUT32(sc, RADEON_CLOCK_CNTL_INDEX, tmp); 2316 1.17.2.2 jmcneill tmp = GET32(sc, RADEON_CLOCK_CNTL_DATA); 2317 1.17.2.2 jmcneill PUT32(sc, RADEON_CLOCK_CNTL_INDEX, save); 2318 1.17.2.2 jmcneill } 2319 1.17.2.2 jmcneill 2320 1.17.2.2 jmcneill /* 2321 1.17.2.2 jmcneill * Acceleration entry points. 2322 1.17.2.2 jmcneill */ 2323 1.17.2.2 jmcneill static void 2324 1.17.2.2 jmcneill radeonfb_putchar(void *cookie, int row, int col, u_int c, long attr) 2325 1.17.2.2 jmcneill { 2326 1.17.2.2 jmcneill struct rasops_info *ri = cookie; 2327 1.17.2.2 jmcneill struct vcons_screen *scr = ri->ri_hw; 2328 1.17.2.2 jmcneill struct radeonfb_display *dp = scr->scr_cookie; 2329 1.17.2.2 jmcneill uint32_t x, y, w, h; 2330 1.17.2.2 jmcneill uint32_t bg, fg; 2331 1.17.2.2 jmcneill uint8_t *data; 2332 1.17.2.2 jmcneill 2333 1.17.2.2 jmcneill if (dp->rd_wsmode != WSDISPLAYIO_MODE_EMUL) 2334 1.17.2.2 jmcneill return; 2335 1.17.2.2 jmcneill 2336 1.17.2.2 jmcneill if (!CHAR_IN_FONT(c, ri->ri_font)) 2337 1.17.2.2 jmcneill return; 2338 1.17.2.2 jmcneill 2339 1.17.2.2 jmcneill w = ri->ri_font->fontwidth; 2340 1.17.2.2 jmcneill h = ri->ri_font->fontheight; 2341 1.17.2.2 jmcneill 2342 1.17.2.2 jmcneill bg = ri->ri_devcmap[(attr >> 16) & 0xf]; 2343 1.17.2.2 jmcneill fg = ri->ri_devcmap[(attr >> 24) & 0xf]; 2344 1.17.2.2 jmcneill 2345 1.17.2.2 jmcneill x = ri->ri_xorigin + col * w; 2346 1.17.2.2 jmcneill y = ri->ri_yorigin + row * h; 2347 1.17.2.2 jmcneill 2348 1.17.2.2 jmcneill if (c == 0x20) { 2349 1.17.2.2 jmcneill radeonfb_rectfill(dp, x, y, w, h, bg); 2350 1.17.2.2 jmcneill } else { 2351 1.17.2.2 jmcneill data = (uint8_t *)ri->ri_font->data + 2352 1.17.2.2 jmcneill (c - ri->ri_font->firstchar) * ri->ri_fontscale; 2353 1.17.2.2 jmcneill 2354 1.17.2.2 jmcneill radeonfb_setup_mono(dp, x, y, w, h, fg, bg); 2355 1.17.2.2 jmcneill radeonfb_feed_bytes(dp, ri->ri_fontscale, data); 2356 1.17.2.2 jmcneill } 2357 1.17.2.2 jmcneill } 2358 1.17.2.2 jmcneill 2359 1.17.2.2 jmcneill static void 2360 1.17.2.2 jmcneill radeonfb_eraserows(void *cookie, int row, int nrows, long fillattr) 2361 1.17.2.2 jmcneill { 2362 1.17.2.2 jmcneill struct rasops_info *ri = cookie; 2363 1.17.2.2 jmcneill struct vcons_screen *scr = ri->ri_hw; 2364 1.17.2.2 jmcneill struct radeonfb_display *dp = scr->scr_cookie; 2365 1.17.2.2 jmcneill uint32_t x, y, w, h, fg, bg, ul; 2366 1.17.2.2 jmcneill 2367 1.17.2.2 jmcneill /* XXX: check for full emulation mode? */ 2368 1.17.2.2 jmcneill if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 2369 1.17.2.2 jmcneill x = ri->ri_xorigin; 2370 1.17.2.2 jmcneill y = ri->ri_yorigin + ri->ri_font->fontheight * row; 2371 1.17.2.2 jmcneill w = ri->ri_emuwidth; 2372 1.17.2.2 jmcneill h = ri->ri_font->fontheight * nrows; 2373 1.17.2.2 jmcneill 2374 1.17.2.2 jmcneill rasops_unpack_attr(fillattr, &fg, &bg, &ul); 2375 1.17.2.2 jmcneill radeonfb_rectfill(dp, x, y, w, h, ri->ri_devcmap[bg & 0xf]); 2376 1.17.2.2 jmcneill } 2377 1.17.2.2 jmcneill } 2378 1.17.2.2 jmcneill 2379 1.17.2.2 jmcneill static void 2380 1.17.2.2 jmcneill radeonfb_copyrows(void *cookie, int srcrow, int dstrow, int nrows) 2381 1.17.2.2 jmcneill { 2382 1.17.2.2 jmcneill struct rasops_info *ri = cookie; 2383 1.17.2.2 jmcneill struct vcons_screen *scr = ri->ri_hw; 2384 1.17.2.2 jmcneill struct radeonfb_display *dp = scr->scr_cookie; 2385 1.17.2.2 jmcneill uint32_t x, ys, yd, w, h; 2386 1.17.2.2 jmcneill 2387 1.17.2.2 jmcneill if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 2388 1.17.2.2 jmcneill x = ri->ri_xorigin; 2389 1.17.2.2 jmcneill ys = ri->ri_yorigin + ri->ri_font->fontheight * srcrow; 2390 1.17.2.2 jmcneill yd = ri->ri_yorigin + ri->ri_font->fontheight * dstrow; 2391 1.17.2.2 jmcneill w = ri->ri_emuwidth; 2392 1.17.2.2 jmcneill h = ri->ri_font->fontheight * nrows; 2393 1.17.2.2 jmcneill radeonfb_bitblt(dp, x, ys, x, yd, w, h, 2394 1.17.2.2 jmcneill RADEON_ROP3_S, 0xffffffff); 2395 1.17.2.2 jmcneill } 2396 1.17.2.2 jmcneill } 2397 1.17.2.2 jmcneill 2398 1.17.2.2 jmcneill static void 2399 1.17.2.2 jmcneill radeonfb_copycols(void *cookie, int row, int srccol, int dstcol, int ncols) 2400 1.17.2.2 jmcneill { 2401 1.17.2.2 jmcneill struct rasops_info *ri = cookie; 2402 1.17.2.2 jmcneill struct vcons_screen *scr = ri->ri_hw; 2403 1.17.2.2 jmcneill struct radeonfb_display *dp = scr->scr_cookie; 2404 1.17.2.2 jmcneill uint32_t xs, xd, y, w, h; 2405 1.17.2.2 jmcneill 2406 1.17.2.2 jmcneill if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 2407 1.17.2.2 jmcneill xs = ri->ri_xorigin + ri->ri_font->fontwidth * srccol; 2408 1.17.2.2 jmcneill xd = ri->ri_xorigin + ri->ri_font->fontwidth * dstcol; 2409 1.17.2.2 jmcneill y = ri->ri_yorigin + ri->ri_font->fontheight * row; 2410 1.17.2.2 jmcneill w = ri->ri_font->fontwidth * ncols; 2411 1.17.2.2 jmcneill h = ri->ri_font->fontheight; 2412 1.17.2.2 jmcneill radeonfb_bitblt(dp, xs, y, xd, y, w, h, 2413 1.17.2.2 jmcneill RADEON_ROP3_S, 0xffffffff); 2414 1.17.2.2 jmcneill } 2415 1.17.2.2 jmcneill } 2416 1.17.2.2 jmcneill 2417 1.17.2.2 jmcneill static void 2418 1.17.2.2 jmcneill radeonfb_erasecols(void *cookie, int row, int startcol, int ncols, 2419 1.17.2.2 jmcneill long fillattr) 2420 1.17.2.2 jmcneill { 2421 1.17.2.2 jmcneill struct rasops_info *ri = cookie; 2422 1.17.2.2 jmcneill struct vcons_screen *scr = ri->ri_hw; 2423 1.17.2.2 jmcneill struct radeonfb_display *dp = scr->scr_cookie; 2424 1.17.2.2 jmcneill uint32_t x, y, w, h, fg, bg, ul; 2425 1.17.2.2 jmcneill 2426 1.17.2.2 jmcneill if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 2427 1.17.2.2 jmcneill x = ri->ri_xorigin + ri->ri_font->fontwidth * startcol; 2428 1.17.2.2 jmcneill y = ri->ri_yorigin + ri->ri_font->fontheight * row; 2429 1.17.2.2 jmcneill w = ri->ri_font->fontwidth * ncols; 2430 1.17.2.2 jmcneill h = ri->ri_font->fontheight; 2431 1.17.2.2 jmcneill 2432 1.17.2.2 jmcneill rasops_unpack_attr(fillattr, &fg, &bg, &ul); 2433 1.17.2.2 jmcneill radeonfb_rectfill(dp, x, y, w, h, ri->ri_devcmap[bg & 0xf]); 2434 1.17.2.2 jmcneill } 2435 1.17.2.2 jmcneill } 2436 1.17.2.2 jmcneill 2437 1.17.2.2 jmcneill static void 2438 1.17.2.2 jmcneill radeonfb_cursor(void *cookie, int on, int row, int col) 2439 1.17.2.2 jmcneill { 2440 1.17.2.2 jmcneill struct rasops_info *ri = cookie; 2441 1.17.2.2 jmcneill struct vcons_screen *scr = ri->ri_hw; 2442 1.17.2.2 jmcneill struct radeonfb_display *dp = scr->scr_cookie; 2443 1.17.2.2 jmcneill int x, y, wi, he; 2444 1.17.2.2 jmcneill 2445 1.17.2.2 jmcneill wi = ri->ri_font->fontwidth; 2446 1.17.2.2 jmcneill he = ri->ri_font->fontheight; 2447 1.17.2.2 jmcneill 2448 1.17.2.2 jmcneill if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 2449 1.17.2.2 jmcneill x = ri->ri_ccol * wi + ri->ri_xorigin; 2450 1.17.2.2 jmcneill y = ri->ri_crow * he + ri->ri_yorigin; 2451 1.17.2.2 jmcneill /* first turn off the old cursor */ 2452 1.17.2.2 jmcneill if (ri->ri_flg & RI_CURSOR) { 2453 1.17.2.2 jmcneill radeonfb_bitblt(dp, x, y, x, y, wi, he, 2454 1.17.2.2 jmcneill RADEON_ROP3_Dn, 0xffffffff); 2455 1.17.2.2 jmcneill ri->ri_flg &= ~RI_CURSOR; 2456 1.17.2.2 jmcneill } 2457 1.17.2.2 jmcneill ri->ri_crow = row; 2458 1.17.2.2 jmcneill ri->ri_ccol = col; 2459 1.17.2.2 jmcneill /* then (possibly) turn on the new one */ 2460 1.17.2.2 jmcneill if (on) { 2461 1.17.2.2 jmcneill x = ri->ri_ccol * wi + ri->ri_xorigin; 2462 1.17.2.2 jmcneill y = ri->ri_crow * he + ri->ri_yorigin; 2463 1.17.2.2 jmcneill radeonfb_bitblt(dp, x, y, x, y, wi, he, 2464 1.17.2.2 jmcneill RADEON_ROP3_Dn, 0xffffffff); 2465 1.17.2.2 jmcneill ri->ri_flg |= RI_CURSOR; 2466 1.17.2.2 jmcneill } 2467 1.17.2.2 jmcneill } else { 2468 1.17.2.2 jmcneill scr->scr_ri.ri_crow = row; 2469 1.17.2.2 jmcneill scr->scr_ri.ri_ccol = col; 2470 1.17.2.2 jmcneill scr->scr_ri.ri_flg &= ~RI_CURSOR; 2471 1.17.2.2 jmcneill } 2472 1.17.2.2 jmcneill } 2473 1.17.2.2 jmcneill 2474 1.17.2.2 jmcneill static int 2475 1.17.2.2 jmcneill radeonfb_allocattr(void *cookie, int fg, int bg, int flags, long *attrp) 2476 1.17.2.2 jmcneill { 2477 1.17.2.2 jmcneill if ((fg == 0) && (bg == 0)) { 2478 1.17.2.2 jmcneill fg = WS_DEFAULT_FG; 2479 1.17.2.2 jmcneill bg = WS_DEFAULT_BG; 2480 1.17.2.2 jmcneill } 2481 1.17.2.2 jmcneill *attrp = ((fg & 0xf) << 24) | ((bg & 0xf) << 16) | (flags & 0xff) << 8; 2482 1.17.2.2 jmcneill return 0; 2483 1.17.2.2 jmcneill } 2484 1.17.2.2 jmcneill 2485 1.17.2.2 jmcneill /* 2486 1.17.2.2 jmcneill * Underlying acceleration support. 2487 1.17.2.2 jmcneill */ 2488 1.17.2.2 jmcneill static void 2489 1.17.2.2 jmcneill radeonfb_setup_mono(struct radeonfb_display *dp, int xd, int yd, int width, 2490 1.17.2.2 jmcneill int height, uint32_t fg, uint32_t bg) 2491 1.17.2.2 jmcneill { 2492 1.17.2.2 jmcneill struct radeonfb_softc *sc = dp->rd_softc; 2493 1.17.2.2 jmcneill uint32_t gmc; 2494 1.17.2.2 jmcneill uint32_t padded_width = (width+7) & 0xfff8; 2495 1.17.2.2 jmcneill uint32_t topleft, bottomright; 2496 1.17.2.2 jmcneill 2497 1.17.2.2 jmcneill gmc = dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT; 2498 1.17.2.2 jmcneill 2499 1.17.2.2 jmcneill if (width != padded_width) { 2500 1.17.2.2 jmcneill 2501 1.17.2.2 jmcneill radeonfb_wait_fifo(sc, 2); 2502 1.17.2.2 jmcneill topleft = ((yd << 16) & 0x1fff0000) | (xd & 0x1fff); 2503 1.17.2.2 jmcneill bottomright = (((yd + height) << 16) & 0x1fff0000) | 2504 1.17.2.2 jmcneill ((xd + width) & 0x1fff); 2505 1.17.2.2 jmcneill PUT32(sc, RADEON_SC_TOP_LEFT, topleft); 2506 1.17.2.2 jmcneill PUT32(sc, RADEON_SC_BOTTOM_RIGHT, bottomright); 2507 1.17.2.2 jmcneill } 2508 1.17.2.2 jmcneill 2509 1.17.2.2 jmcneill radeonfb_wait_fifo(sc, 5); 2510 1.17.2.2 jmcneill 2511 1.17.2.2 jmcneill PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 2512 1.17.2.2 jmcneill RADEON_GMC_BRUSH_NONE | 2513 1.17.2.2 jmcneill RADEON_GMC_SRC_DATATYPE_MONO_FG_BG | 2514 1.17.2.2 jmcneill //RADEON_GMC_BYTE_LSB_TO_MSB | 2515 1.17.2.2 jmcneill RADEON_GMC_DST_CLIPPING | 2516 1.17.2.2 jmcneill RADEON_ROP3_S | 2517 1.17.2.2 jmcneill RADEON_DP_SRC_SOURCE_HOST_DATA | 2518 1.17.2.2 jmcneill RADEON_GMC_CLR_CMP_CNTL_DIS | 2519 1.17.2.2 jmcneill RADEON_GMC_WR_MSK_DIS | 2520 1.17.2.2 jmcneill gmc); 2521 1.17.2.2 jmcneill 2522 1.17.2.2 jmcneill PUT32(sc, RADEON_DP_SRC_FRGD_CLR, fg); 2523 1.17.2.2 jmcneill PUT32(sc, RADEON_DP_SRC_BKGD_CLR, bg); 2524 1.17.2.2 jmcneill 2525 1.17.2.2 jmcneill PUT32(sc, RADEON_DST_X_Y, (xd << 16) | yd); 2526 1.17.2.2 jmcneill PUT32(sc, RADEON_DST_WIDTH_HEIGHT, (padded_width << 16) | height); 2527 1.17.2.2 jmcneill 2528 1.17.2.2 jmcneill } 2529 1.17.2.2 jmcneill 2530 1.17.2.2 jmcneill static void 2531 1.17.2.2 jmcneill radeonfb_feed_bytes(struct radeonfb_display *dp, int count, uint8_t *data) 2532 1.17.2.2 jmcneill { 2533 1.17.2.2 jmcneill struct radeonfb_softc *sc = dp->rd_softc; 2534 1.17.2.2 jmcneill int i; 2535 1.17.2.2 jmcneill uint32_t latch = 0; 2536 1.17.2.2 jmcneill int shift = 0; 2537 1.17.2.2 jmcneill 2538 1.17.2.2 jmcneill for (i = 0; i < count; i++) { 2539 1.17.2.2 jmcneill latch |= (data[i] << shift); 2540 1.17.2.2 jmcneill if (shift == 24) { 2541 1.17.2.2 jmcneill radeonfb_wait_fifo(sc, 1); 2542 1.17.2.2 jmcneill PUT32(sc, RADEON_HOST_DATA0, latch); 2543 1.17.2.2 jmcneill latch = 0; 2544 1.17.2.2 jmcneill shift = 0; 2545 1.17.2.2 jmcneill } else 2546 1.17.2.2 jmcneill shift += 8; 2547 1.17.2.2 jmcneill } 2548 1.17.2.2 jmcneill if (shift != 0) { 2549 1.17.2.2 jmcneill radeonfb_wait_fifo(sc, 1); 2550 1.17.2.2 jmcneill PUT32(sc, RADEON_HOST_DATA0, latch); 2551 1.17.2.2 jmcneill } 2552 1.17.2.2 jmcneill radeonfb_unclip(sc); 2553 1.17.2.2 jmcneill } 2554 1.17.2.2 jmcneill 2555 1.17.2.2 jmcneill static void 2556 1.17.2.2 jmcneill radeonfb_rectfill(struct radeonfb_display *dp, int dstx, int dsty, 2557 1.17.2.2 jmcneill int width, int height, uint32_t color) 2558 1.17.2.2 jmcneill { 2559 1.17.2.2 jmcneill struct radeonfb_softc *sc = dp->rd_softc; 2560 1.17.2.2 jmcneill uint32_t gmc; 2561 1.17.2.2 jmcneill 2562 1.17.2.2 jmcneill gmc = dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT; 2563 1.17.2.2 jmcneill 2564 1.17.2.2 jmcneill radeonfb_wait_fifo(sc, 6); 2565 1.17.2.2 jmcneill 2566 1.17.2.2 jmcneill PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 2567 1.17.2.2 jmcneill RADEON_GMC_BRUSH_SOLID_COLOR | 2568 1.17.2.2 jmcneill RADEON_GMC_SRC_DATATYPE_COLOR | 2569 1.17.2.2 jmcneill RADEON_GMC_CLR_CMP_CNTL_DIS | 2570 1.17.2.2 jmcneill RADEON_ROP3_P | gmc); 2571 1.17.2.2 jmcneill 2572 1.17.2.2 jmcneill PUT32(sc, RADEON_DP_BRUSH_FRGD_CLR, color); 2573 1.17.2.2 jmcneill PUT32(sc, RADEON_DP_WRITE_MASK, 0xffffffff); 2574 1.17.2.2 jmcneill PUT32(sc, RADEON_DP_CNTL, 2575 1.17.2.2 jmcneill RADEON_DST_X_LEFT_TO_RIGHT | 2576 1.17.2.2 jmcneill RADEON_DST_Y_TOP_TO_BOTTOM); 2577 1.17.2.2 jmcneill PUT32(sc, RADEON_DST_Y_X, (dsty << 16) | dstx); 2578 1.17.2.2 jmcneill PUT32(sc, RADEON_DST_WIDTH_HEIGHT, (width << 16) | (height)); 2579 1.17.2.2 jmcneill 2580 1.17.2.2 jmcneill /* 2581 1.17.2.2 jmcneill * XXX: we don't wait for the fifo to empty -- that would slow 2582 1.17.2.2 jmcneill * things down! The linux radeonfb driver waits, but xfree doesn't 2583 1.17.2.2 jmcneill */ 2584 1.17.2.2 jmcneill /* XXX: for now we do, to make it safe for direct drawing */ 2585 1.17.2.2 jmcneill radeonfb_engine_idle(sc); 2586 1.17.2.2 jmcneill } 2587 1.17.2.2 jmcneill 2588 1.17.2.2 jmcneill static void 2589 1.17.2.2 jmcneill radeonfb_bitblt(struct radeonfb_display *dp, int srcx, int srcy, 2590 1.17.2.2 jmcneill int dstx, int dsty, int width, int height, int rop, uint32_t mask) 2591 1.17.2.2 jmcneill { 2592 1.17.2.2 jmcneill struct radeonfb_softc *sc = dp->rd_softc; 2593 1.17.2.2 jmcneill uint32_t gmc; 2594 1.17.2.2 jmcneill uint32_t dir; 2595 1.17.2.2 jmcneill 2596 1.17.2.2 jmcneill if (dsty < srcy) { 2597 1.17.2.2 jmcneill dir = RADEON_DST_Y_TOP_TO_BOTTOM; 2598 1.17.2.2 jmcneill } else { 2599 1.17.2.2 jmcneill srcy += height - 1; 2600 1.17.2.2 jmcneill dsty += height - 1; 2601 1.17.2.2 jmcneill dir = 0; 2602 1.17.2.2 jmcneill } 2603 1.17.2.2 jmcneill if (dstx < srcx) { 2604 1.17.2.2 jmcneill dir |= RADEON_DST_X_LEFT_TO_RIGHT; 2605 1.17.2.2 jmcneill } else { 2606 1.17.2.2 jmcneill srcx += width - 1; 2607 1.17.2.2 jmcneill dstx += width - 1; 2608 1.17.2.2 jmcneill } 2609 1.17.2.2 jmcneill 2610 1.17.2.2 jmcneill gmc = dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT; 2611 1.17.2.2 jmcneill 2612 1.17.2.2 jmcneill radeonfb_wait_fifo(sc, 6); 2613 1.17.2.2 jmcneill 2614 1.17.2.2 jmcneill PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 2615 1.17.2.2 jmcneill //RADEON_GMC_SRC_CLIPPING | 2616 1.17.2.2 jmcneill RADEON_GMC_BRUSH_SOLID_COLOR | 2617 1.17.2.2 jmcneill RADEON_GMC_SRC_DATATYPE_COLOR | 2618 1.17.2.2 jmcneill RADEON_GMC_CLR_CMP_CNTL_DIS | 2619 1.17.2.2 jmcneill RADEON_DP_SRC_SOURCE_MEMORY | 2620 1.17.2.2 jmcneill rop | gmc); 2621 1.17.2.2 jmcneill 2622 1.17.2.2 jmcneill PUT32(sc, RADEON_DP_WRITE_MASK, mask); 2623 1.17.2.2 jmcneill PUT32(sc, RADEON_DP_CNTL, dir); 2624 1.17.2.2 jmcneill PUT32(sc, RADEON_SRC_Y_X, (srcy << 16) | srcx); 2625 1.17.2.2 jmcneill PUT32(sc, RADEON_DST_Y_X, (dsty << 16) | dstx); 2626 1.17.2.2 jmcneill PUT32(sc, RADEON_DST_WIDTH_HEIGHT, (width << 16) | (height)); 2627 1.17.2.2 jmcneill 2628 1.17.2.2 jmcneill /* 2629 1.17.2.2 jmcneill * XXX: we don't wait for the fifo to empty -- that would slow 2630 1.17.2.2 jmcneill * things down! The linux radeonfb driver waits, but xfree doesn't 2631 1.17.2.2 jmcneill */ 2632 1.17.2.2 jmcneill /* XXX: for now we do, to make it safe for direct drawing */ 2633 1.17.2.2 jmcneill radeonfb_engine_idle(sc); 2634 1.17.2.2 jmcneill } 2635 1.17.2.2 jmcneill 2636 1.17.2.2 jmcneill static void 2637 1.17.2.2 jmcneill radeonfb_engine_idle(struct radeonfb_softc *sc) 2638 1.17.2.2 jmcneill { 2639 1.17.2.2 jmcneill int i; 2640 1.17.2.2 jmcneill 2641 1.17.2.2 jmcneill radeonfb_wait_fifo(sc, 64); 2642 1.17.2.2 jmcneill for (i = RADEON_TIMEOUT; i; i--) { 2643 1.17.2.2 jmcneill if ((GET32(sc, RADEON_RBBM_STATUS) & 2644 1.17.2.2 jmcneill RADEON_RBBM_ACTIVE) == 0) { 2645 1.17.2.2 jmcneill radeonfb_engine_flush(sc); 2646 1.17.2.2 jmcneill break; 2647 1.17.2.2 jmcneill } 2648 1.17.2.2 jmcneill } 2649 1.17.2.2 jmcneill } 2650 1.17.2.2 jmcneill 2651 1.17.2.2 jmcneill static void 2652 1.17.2.2 jmcneill radeonfb_wait_fifo(struct radeonfb_softc *sc, int n) 2653 1.17.2.2 jmcneill { 2654 1.17.2.2 jmcneill int i; 2655 1.17.2.2 jmcneill 2656 1.17.2.2 jmcneill for (i = RADEON_TIMEOUT; i; i--) { 2657 1.17.2.2 jmcneill if ((GET32(sc, RADEON_RBBM_STATUS) & 2658 1.17.2.2 jmcneill RADEON_RBBM_FIFOCNT_MASK) >= n) 2659 1.17.2.2 jmcneill return; 2660 1.17.2.2 jmcneill } 2661 1.17.2.2 jmcneill #ifdef DIAGNOSTIC 2662 1.17.2.2 jmcneill if (!i) 2663 1.17.2.2 jmcneill printf("%s: timed out waiting for fifo (%x)\n", 2664 1.17.2.2 jmcneill XNAME(sc), GET32(sc, RADEON_RBBM_STATUS)); 2665 1.17.2.2 jmcneill #endif 2666 1.17.2.2 jmcneill } 2667 1.17.2.2 jmcneill 2668 1.17.2.2 jmcneill static void 2669 1.17.2.2 jmcneill radeonfb_engine_flush(struct radeonfb_softc *sc) 2670 1.17.2.2 jmcneill { 2671 1.17.2.2 jmcneill int i; 2672 1.17.2.2 jmcneill SET32(sc, RADEON_RB2D_DSTCACHE_CTLSTAT, RADEON_RB2D_DC_FLUSH_ALL); 2673 1.17.2.2 jmcneill for (i = RADEON_TIMEOUT; i; i--) { 2674 1.17.2.2 jmcneill if ((GET32(sc, RADEON_RB2D_DSTCACHE_CTLSTAT) & 2675 1.17.2.2 jmcneill RADEON_RB2D_DC_BUSY) == 0) 2676 1.17.2.2 jmcneill break; 2677 1.17.2.2 jmcneill } 2678 1.17.2.2 jmcneill #ifdef DIAGNOSTIC 2679 1.17.2.2 jmcneill if (!i) 2680 1.17.2.2 jmcneill printf("%s: engine flush timed out!\n", XNAME(sc)); 2681 1.17.2.2 jmcneill #endif 2682 1.17.2.2 jmcneill } 2683 1.17.2.2 jmcneill 2684 1.17.2.2 jmcneill static inline void 2685 1.17.2.2 jmcneill radeonfb_unclip(struct radeonfb_softc *sc) 2686 1.17.2.2 jmcneill { 2687 1.17.2.2 jmcneill 2688 1.17.2.2 jmcneill radeonfb_wait_fifo(sc, 2); 2689 1.17.2.2 jmcneill PUT32(sc, RADEON_SC_TOP_LEFT, 0); 2690 1.17.2.2 jmcneill PUT32(sc, RADEON_SC_BOTTOM_RIGHT, 0x1fff1fff); 2691 1.17.2.2 jmcneill } 2692 1.17.2.2 jmcneill 2693 1.17.2.2 jmcneill static void 2694 1.17.2.2 jmcneill radeonfb_engine_init(struct radeonfb_display *dp) 2695 1.17.2.2 jmcneill { 2696 1.17.2.2 jmcneill struct radeonfb_softc *sc = dp->rd_softc; 2697 1.17.2.2 jmcneill uint32_t pitch; 2698 1.17.2.2 jmcneill 2699 1.17.2.2 jmcneill /* no 3D */ 2700 1.17.2.2 jmcneill PUT32(sc, RADEON_RB3D_CNTL, 0); 2701 1.17.2.2 jmcneill 2702 1.17.2.2 jmcneill radeonfb_engine_reset(sc); 2703 1.17.2.2 jmcneill pitch = ((dp->rd_virtx * (dp->rd_bpp / 8) + 0x3f)) >> 6; 2704 1.17.2.2 jmcneill //pitch = ((sc->sc_maxx * (sc->sc_maxbpp / 8) + 0x3f)) >> 6; 2705 1.17.2.2 jmcneill 2706 1.17.2.2 jmcneill radeonfb_wait_fifo(sc, 1); 2707 1.17.2.2 jmcneill if (!IS_R300(sc)) 2708 1.17.2.2 jmcneill PUT32(sc, RADEON_RB2D_DSTCACHE_MODE, 0); 2709 1.17.2.2 jmcneill 2710 1.17.2.2 jmcneill radeonfb_wait_fifo(sc, 3); 2711 1.17.2.2 jmcneill PUT32(sc, RADEON_DEFAULT_PITCH_OFFSET, 2712 1.17.2.2 jmcneill (pitch << 22) | (sc->sc_aperbase >> 10)); 2713 1.17.2.2 jmcneill 2714 1.17.2.2 jmcneill 2715 1.17.2.2 jmcneill PUT32(sc, RADEON_DST_PITCH_OFFSET, 2716 1.17.2.2 jmcneill (pitch << 22) | (sc->sc_aperbase >> 10)); 2717 1.17.2.2 jmcneill PUT32(sc, RADEON_SRC_PITCH_OFFSET, 2718 1.17.2.2 jmcneill (pitch << 22) | (sc->sc_aperbase >> 10)); 2719 1.17.2.2 jmcneill 2720 1.17.2.2 jmcneill radeonfb_wait_fifo(sc, 1); 2721 1.17.2.2 jmcneill #if _BYTE_ORDER == _BIG_ENDIAN 2722 1.17.2.2 jmcneill SET32(sc, RADEON_DP_DATATYPE, RADEON_HOST_BIG_ENDIAN_EN); 2723 1.17.2.2 jmcneill #else 2724 1.17.2.2 jmcneill CLR32(sc, RADEON_DP_DATATYPE, RADEON_HOST_BIG_ENDIAN_EN); 2725 1.17.2.2 jmcneill #endif 2726 1.17.2.2 jmcneill 2727 1.17.2.2 jmcneill /* default scissors -- no clipping */ 2728 1.17.2.2 jmcneill radeonfb_wait_fifo(sc, 1); 2729 1.17.2.2 jmcneill PUT32(sc, RADEON_DEFAULT_SC_BOTTOM_RIGHT, 2730 1.17.2.2 jmcneill RADEON_DEFAULT_SC_RIGHT_MAX | RADEON_DEFAULT_SC_BOTTOM_MAX); 2731 1.17.2.2 jmcneill 2732 1.17.2.2 jmcneill radeonfb_wait_fifo(sc, 1); 2733 1.17.2.2 jmcneill PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 2734 1.17.2.2 jmcneill (dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT) | 2735 1.17.2.2 jmcneill RADEON_GMC_CLR_CMP_CNTL_DIS | 2736 1.17.2.2 jmcneill RADEON_GMC_BRUSH_SOLID_COLOR | 2737 1.17.2.2 jmcneill RADEON_GMC_SRC_DATATYPE_COLOR); 2738 1.17.2.2 jmcneill 2739 1.17.2.2 jmcneill radeonfb_wait_fifo(sc, 7); 2740 1.17.2.2 jmcneill PUT32(sc, RADEON_DST_LINE_START, 0); 2741 1.17.2.2 jmcneill PUT32(sc, RADEON_DST_LINE_END, 0); 2742 1.17.2.2 jmcneill PUT32(sc, RADEON_DP_BRUSH_FRGD_CLR, 0xffffffff); 2743 1.17.2.2 jmcneill PUT32(sc, RADEON_DP_BRUSH_BKGD_CLR, 0); 2744 1.17.2.2 jmcneill PUT32(sc, RADEON_DP_SRC_FRGD_CLR, 0xffffffff); 2745 1.17.2.2 jmcneill PUT32(sc, RADEON_DP_SRC_BKGD_CLR, 0); 2746 1.17.2.2 jmcneill PUT32(sc, RADEON_DP_WRITE_MASK, 0xffffffff); 2747 1.17.2.2 jmcneill 2748 1.17.2.2 jmcneill radeonfb_engine_idle(sc); 2749 1.17.2.2 jmcneill } 2750 1.17.2.2 jmcneill 2751 1.17.2.2 jmcneill static void 2752 1.17.2.2 jmcneill radeonfb_engine_reset(struct radeonfb_softc *sc) 2753 1.17.2.2 jmcneill { 2754 1.17.2.2 jmcneill uint32_t hpc, rbbm, mclkcntl, clkindex; 2755 1.17.2.2 jmcneill 2756 1.17.2.2 jmcneill radeonfb_engine_flush(sc); 2757 1.17.2.2 jmcneill 2758 1.17.2.2 jmcneill clkindex = GET32(sc, RADEON_CLOCK_CNTL_INDEX); 2759 1.17.2.2 jmcneill if (HAS_R300CG(sc)) 2760 1.17.2.2 jmcneill radeonfb_r300cg_workaround(sc); 2761 1.17.2.2 jmcneill mclkcntl = GETPLL(sc, RADEON_MCLK_CNTL); 2762 1.17.2.2 jmcneill 2763 1.17.2.2 jmcneill /* 2764 1.17.2.2 jmcneill * According to comments in XFree code, resetting the HDP via 2765 1.17.2.2 jmcneill * the RBBM_SOFT_RESET can cause bad behavior on some systems. 2766 1.17.2.2 jmcneill * So we use HOST_PATH_CNTL instead. 2767 1.17.2.2 jmcneill */ 2768 1.17.2.2 jmcneill 2769 1.17.2.2 jmcneill hpc = GET32(sc, RADEON_HOST_PATH_CNTL); 2770 1.17.2.2 jmcneill rbbm = GET32(sc, RADEON_RBBM_SOFT_RESET); 2771 1.17.2.2 jmcneill if (IS_R300(sc)) { 2772 1.17.2.2 jmcneill PUT32(sc, RADEON_RBBM_SOFT_RESET, rbbm | 2773 1.17.2.2 jmcneill RADEON_SOFT_RESET_CP | 2774 1.17.2.2 jmcneill RADEON_SOFT_RESET_HI | 2775 1.17.2.2 jmcneill RADEON_SOFT_RESET_E2); 2776 1.17.2.2 jmcneill GET32(sc, RADEON_RBBM_SOFT_RESET); 2777 1.17.2.2 jmcneill PUT32(sc, RADEON_RBBM_SOFT_RESET, 0); 2778 1.17.2.2 jmcneill /* 2779 1.17.2.2 jmcneill * XXX: this bit is not defined in any ATI docs I have, 2780 1.17.2.2 jmcneill * nor in the XFree code, but XFree does it. Why? 2781 1.17.2.2 jmcneill */ 2782 1.17.2.2 jmcneill SET32(sc, RADEON_RB2D_DSTCACHE_MODE, (1<<17)); 2783 1.17.2.2 jmcneill } else { 2784 1.17.2.2 jmcneill PUT32(sc, RADEON_RBBM_SOFT_RESET, rbbm | 2785 1.17.2.2 jmcneill RADEON_SOFT_RESET_CP | 2786 1.17.2.2 jmcneill RADEON_SOFT_RESET_SE | 2787 1.17.2.2 jmcneill RADEON_SOFT_RESET_RE | 2788 1.17.2.2 jmcneill RADEON_SOFT_RESET_PP | 2789 1.17.2.2 jmcneill RADEON_SOFT_RESET_E2 | 2790 1.17.2.2 jmcneill RADEON_SOFT_RESET_RB); 2791 1.17.2.2 jmcneill GET32(sc, RADEON_RBBM_SOFT_RESET); 2792 1.17.2.2 jmcneill PUT32(sc, RADEON_RBBM_SOFT_RESET, rbbm & 2793 1.17.2.2 jmcneill ~(RADEON_SOFT_RESET_CP | 2794 1.17.2.2 jmcneill RADEON_SOFT_RESET_SE | 2795 1.17.2.2 jmcneill RADEON_SOFT_RESET_RE | 2796 1.17.2.2 jmcneill RADEON_SOFT_RESET_PP | 2797 1.17.2.2 jmcneill RADEON_SOFT_RESET_E2 | 2798 1.17.2.2 jmcneill RADEON_SOFT_RESET_RB)); 2799 1.17.2.2 jmcneill GET32(sc, RADEON_RBBM_SOFT_RESET); 2800 1.17.2.2 jmcneill } 2801 1.17.2.2 jmcneill 2802 1.17.2.2 jmcneill PUT32(sc, RADEON_HOST_PATH_CNTL, hpc | RADEON_HDP_SOFT_RESET); 2803 1.17.2.2 jmcneill GET32(sc, RADEON_HOST_PATH_CNTL); 2804 1.17.2.2 jmcneill PUT32(sc, RADEON_HOST_PATH_CNTL, hpc); 2805 1.17.2.2 jmcneill 2806 1.17.2.2 jmcneill if (IS_R300(sc)) 2807 1.17.2.2 jmcneill PUT32(sc, RADEON_RBBM_SOFT_RESET, rbbm); 2808 1.17.2.2 jmcneill 2809 1.17.2.2 jmcneill PUT32(sc, RADEON_CLOCK_CNTL_INDEX, clkindex); 2810 1.17.2.2 jmcneill PUTPLL(sc, RADEON_MCLK_CNTL, mclkcntl); 2811 1.17.2.2 jmcneill 2812 1.17.2.2 jmcneill if (HAS_R300CG(sc)) 2813 1.17.2.2 jmcneill radeonfb_r300cg_workaround(sc); 2814 1.17.2.2 jmcneill } 2815 1.17.2.2 jmcneill 2816 1.17.2.2 jmcneill static int 2817 1.17.2.2 jmcneill radeonfb_set_curpos(struct radeonfb_display *dp, struct wsdisplay_curpos *pos) 2818 1.17.2.2 jmcneill { 2819 1.17.2.2 jmcneill int x, y; 2820 1.17.2.2 jmcneill 2821 1.17.2.2 jmcneill x = pos->x; 2822 1.17.2.2 jmcneill y = pos->y; 2823 1.17.2.2 jmcneill 2824 1.17.2.2 jmcneill /* 2825 1.17.2.2 jmcneill * This doesn't let a cursor move off the screen. I'm not 2826 1.17.2.2 jmcneill * sure if this will have negative effects for e.g. Xinerama. 2827 1.17.2.2 jmcneill * I'd guess Xinerama handles it by changing the cursor shape, 2828 1.17.2.2 jmcneill * but that needs verification. 2829 1.17.2.2 jmcneill */ 2830 1.17.2.2 jmcneill if (x >= dp->rd_virtx) 2831 1.17.2.2 jmcneill x = dp->rd_virtx - 1; 2832 1.17.2.2 jmcneill if (x < 0) 2833 1.17.2.2 jmcneill x = 0; 2834 1.17.2.2 jmcneill if (y >= dp->rd_virty) 2835 1.17.2.2 jmcneill y = dp->rd_virty - 1; 2836 1.17.2.2 jmcneill if (y < 0) 2837 1.17.2.2 jmcneill y = 0; 2838 1.17.2.2 jmcneill 2839 1.17.2.2 jmcneill dp->rd_cursor.rc_pos.x = x; 2840 1.17.2.2 jmcneill dp->rd_cursor.rc_pos.y = y; 2841 1.17.2.2 jmcneill 2842 1.17.2.2 jmcneill radeonfb_cursor_position(dp); 2843 1.17.2.2 jmcneill return 0; 2844 1.17.2.2 jmcneill } 2845 1.17.2.2 jmcneill 2846 1.17.2.2 jmcneill static int 2847 1.17.2.2 jmcneill radeonfb_set_cursor(struct radeonfb_display *dp, struct wsdisplay_cursor *wc) 2848 1.17.2.2 jmcneill { 2849 1.17.2.2 jmcneill unsigned flags; 2850 1.17.2.2 jmcneill 2851 1.17.2.2 jmcneill uint8_t r[2], g[2], b[2]; 2852 1.17.2.2 jmcneill unsigned index, count; 2853 1.17.2.2 jmcneill int i, err; 2854 1.17.2.2 jmcneill int pitch, size; 2855 1.17.2.2 jmcneill struct radeonfb_cursor nc; 2856 1.17.2.2 jmcneill 2857 1.17.2.2 jmcneill flags = wc->which; 2858 1.17.2.2 jmcneill 2859 1.17.2.2 jmcneill /* copy old values */ 2860 1.17.2.2 jmcneill nc = dp->rd_cursor; 2861 1.17.2.2 jmcneill 2862 1.17.2.2 jmcneill if (flags & WSDISPLAY_CURSOR_DOCMAP) { 2863 1.17.2.2 jmcneill index = wc->cmap.index; 2864 1.17.2.2 jmcneill count = wc->cmap.count; 2865 1.17.2.2 jmcneill 2866 1.17.2.2 jmcneill if (index >= 2 || (index + count) > 2) 2867 1.17.2.2 jmcneill return EINVAL; 2868 1.17.2.2 jmcneill 2869 1.17.2.2 jmcneill err = copyin(wc->cmap.red, &r[index], count); 2870 1.17.2.2 jmcneill if (err) 2871 1.17.2.2 jmcneill return err; 2872 1.17.2.2 jmcneill err = copyin(wc->cmap.green, &g[index], count); 2873 1.17.2.2 jmcneill if (err) 2874 1.17.2.2 jmcneill return err; 2875 1.17.2.2 jmcneill err = copyin(wc->cmap.blue, &b[index], count); 2876 1.17.2.2 jmcneill if (err) 2877 1.17.2.2 jmcneill return err; 2878 1.17.2.2 jmcneill 2879 1.17.2.2 jmcneill for (i = index; i < index + count; i++) { 2880 1.17.2.2 jmcneill nc.rc_cmap[i] = 2881 1.17.2.2 jmcneill (r[i] << 16) + (g[i] << 8) + (b[i] << 0); 2882 1.17.2.2 jmcneill } 2883 1.17.2.2 jmcneill } 2884 1.17.2.2 jmcneill 2885 1.17.2.2 jmcneill if (flags & WSDISPLAY_CURSOR_DOSHAPE) { 2886 1.17.2.2 jmcneill if ((wc->size.x > RADEON_CURSORMAXX) || 2887 1.17.2.2 jmcneill (wc->size.y > RADEON_CURSORMAXY)) 2888 1.17.2.2 jmcneill return EINVAL; 2889 1.17.2.2 jmcneill 2890 1.17.2.2 jmcneill /* figure bytes per line */ 2891 1.17.2.2 jmcneill pitch = (wc->size.x + 7) / 8; 2892 1.17.2.2 jmcneill size = pitch * wc->size.y; 2893 1.17.2.2 jmcneill 2894 1.17.2.2 jmcneill /* clear the old cursor and mask */ 2895 1.17.2.2 jmcneill memset(nc.rc_image, 0, 512); 2896 1.17.2.2 jmcneill memset(nc.rc_mask, 0, 512); 2897 1.17.2.2 jmcneill 2898 1.17.2.2 jmcneill nc.rc_size = wc->size; 2899 1.17.2.2 jmcneill 2900 1.17.2.2 jmcneill if ((err = copyin(wc->image, nc.rc_image, size)) != 0) 2901 1.17.2.2 jmcneill return err; 2902 1.17.2.2 jmcneill 2903 1.17.2.2 jmcneill if ((err = copyin(wc->mask, nc.rc_mask, size)) != 0) 2904 1.17.2.2 jmcneill return err; 2905 1.17.2.2 jmcneill } 2906 1.17.2.2 jmcneill 2907 1.17.2.2 jmcneill if (flags & WSDISPLAY_CURSOR_DOHOT) { 2908 1.17.2.2 jmcneill nc.rc_hot = wc->hot; 2909 1.17.2.2 jmcneill if (nc.rc_hot.x >= nc.rc_size.x) 2910 1.17.2.2 jmcneill nc.rc_hot.x = nc.rc_size.x - 1; 2911 1.17.2.2 jmcneill if (nc.rc_hot.y >= nc.rc_size.y) 2912 1.17.2.2 jmcneill nc.rc_hot.y = nc.rc_size.y - 1; 2913 1.17.2.2 jmcneill } 2914 1.17.2.2 jmcneill 2915 1.17.2.2 jmcneill if (flags & WSDISPLAY_CURSOR_DOPOS) { 2916 1.17.2.2 jmcneill nc.rc_pos = wc->pos; 2917 1.17.2.2 jmcneill if (nc.rc_pos.x >= dp->rd_virtx) 2918 1.17.2.2 jmcneill nc.rc_pos.x = dp->rd_virtx - 1; 2919 1.17.2.2 jmcneill #if 0 2920 1.17.2.2 jmcneill if (nc.rc_pos.x < 0) 2921 1.17.2.2 jmcneill nc.rc_pos.x = 0; 2922 1.17.2.2 jmcneill #endif 2923 1.17.2.2 jmcneill if (nc.rc_pos.y >= dp->rd_virty) 2924 1.17.2.2 jmcneill nc.rc_pos.y = dp->rd_virty - 1; 2925 1.17.2.2 jmcneill #if 0 2926 1.17.2.2 jmcneill if (nc.rc_pos.y < 0) 2927 1.17.2.2 jmcneill nc.rc_pos.y = 0; 2928 1.17.2.2 jmcneill #endif 2929 1.17.2.2 jmcneill } 2930 1.17.2.2 jmcneill if (flags & WSDISPLAY_CURSOR_DOCUR) { 2931 1.17.2.2 jmcneill nc.rc_visible = wc->enable; 2932 1.17.2.2 jmcneill } 2933 1.17.2.2 jmcneill 2934 1.17.2.2 jmcneill dp->rd_cursor = nc; 2935 1.17.2.2 jmcneill radeonfb_cursor_update(dp, wc->which); 2936 1.17.2.2 jmcneill 2937 1.17.2.2 jmcneill return 0; 2938 1.17.2.2 jmcneill } 2939 1.17.2.2 jmcneill 2940 1.17.2.2 jmcneill /* 2941 1.17.2.2 jmcneill * Change the cursor shape. Call this with the cursor locked to avoid 2942 1.17.2.2 jmcneill * flickering/tearing. 2943 1.17.2.2 jmcneill */ 2944 1.17.2.2 jmcneill static void 2945 1.17.2.2 jmcneill radeonfb_cursor_shape(struct radeonfb_display *dp) 2946 1.17.2.2 jmcneill { 2947 1.17.2.2 jmcneill uint8_t and[512], xor[512]; 2948 1.17.2.2 jmcneill int i, j, src, dst, pitch; 2949 1.17.2.2 jmcneill const uint8_t *msk = dp->rd_cursor.rc_mask; 2950 1.17.2.2 jmcneill const uint8_t *img = dp->rd_cursor.rc_image; 2951 1.17.2.2 jmcneill 2952 1.17.2.2 jmcneill /* 2953 1.17.2.2 jmcneill * Radeon cursor data interleaves one line of AND data followed 2954 1.17.2.2 jmcneill * by a line of XOR data. (Each line corresponds to a whole hardware 2955 1.17.2.2 jmcneill * pitch - i.e. 64 pixels or 8 bytes.) 2956 1.17.2.2 jmcneill * 2957 1.17.2.2 jmcneill * The cursor is displayed using the following table: 2958 1.17.2.2 jmcneill * 2959 1.17.2.2 jmcneill * AND XOR Result 2960 1.17.2.2 jmcneill * ---------------------- 2961 1.17.2.2 jmcneill * 0 0 Cursor color 0 2962 1.17.2.2 jmcneill * 0 1 Cursor color 1 2963 1.17.2.2 jmcneill * 1 0 Transparent 2964 1.17.2.2 jmcneill * 1 1 Complement of background 2965 1.17.2.2 jmcneill * 2966 1.17.2.2 jmcneill * Our masks are therefore different from what we were passed. 2967 1.17.2.2 jmcneill * Passed in, I'm assuming the data represents either color 0 or 1, 2968 1.17.2.2 jmcneill * and a mask, so the passed in table looks like: 2969 1.17.2.2 jmcneill * 2970 1.17.2.2 jmcneill * IMG Mask Result 2971 1.17.2.2 jmcneill * ----------------------- 2972 1.17.2.2 jmcneill * 0 0 Transparent 2973 1.17.2.2 jmcneill * 0 1 Cursor color 0 2974 1.17.2.2 jmcneill * 1 0 Transparent 2975 1.17.2.2 jmcneill * 1 1 Cursor color 1 2976 1.17.2.2 jmcneill * 2977 1.17.2.2 jmcneill * IF mask bit == 1, AND = 0, XOR = color. 2978 1.17.2.2 jmcneill * IF mask bit == 0, AND = 1, XOR = 0. 2979 1.17.2.2 jmcneill * 2980 1.17.2.2 jmcneill * hence: AND = ~(mask); XOR = color & ~(mask); 2981 1.17.2.2 jmcneill */ 2982 1.17.2.2 jmcneill 2983 1.17.2.2 jmcneill pitch = ((dp->rd_cursor.rc_size.x + 7) / 8); 2984 1.17.2.2 jmcneill 2985 1.17.2.2 jmcneill /* start by assuming all bits are transparent */ 2986 1.17.2.2 jmcneill memset(and, 0xff, 512); 2987 1.17.2.2 jmcneill memset(xor, 0x00, 512); 2988 1.17.2.2 jmcneill 2989 1.17.2.2 jmcneill src = 0; 2990 1.17.2.2 jmcneill dst = 0; 2991 1.17.2.2 jmcneill for (i = 0; i < 64; i++) { 2992 1.17.2.2 jmcneill for (j = 0; j < 64; j += 8) { 2993 1.17.2.2 jmcneill if ((i < dp->rd_cursor.rc_size.y) && 2994 1.17.2.2 jmcneill (j < dp->rd_cursor.rc_size.x)) { 2995 1.17.2.2 jmcneill 2996 1.17.2.2 jmcneill /* take care to leave odd bits alone */ 2997 1.17.2.2 jmcneill and[dst] &= ~(msk[src]); 2998 1.17.2.2 jmcneill xor[dst] = img[src] & msk[src]; 2999 1.17.2.2 jmcneill src++; 3000 1.17.2.2 jmcneill } 3001 1.17.2.2 jmcneill dst++; 3002 1.17.2.2 jmcneill } 3003 1.17.2.2 jmcneill } 3004 1.17.2.2 jmcneill 3005 1.17.2.2 jmcneill /* copy the image into place */ 3006 1.17.2.2 jmcneill for (i = 0; i < 64; i++) { 3007 1.17.2.2 jmcneill memcpy((uint8_t *)dp->rd_curptr + (i * 16), 3008 1.17.2.2 jmcneill &and[i * 8], 8); 3009 1.17.2.2 jmcneill memcpy((uint8_t *)dp->rd_curptr + (i * 16) + 8, 3010 1.17.2.2 jmcneill &xor[i * 8], 8); 3011 1.17.2.2 jmcneill } 3012 1.17.2.2 jmcneill } 3013 1.17.2.2 jmcneill 3014 1.17.2.2 jmcneill static void 3015 1.17.2.2 jmcneill radeonfb_cursor_position(struct radeonfb_display *dp) 3016 1.17.2.2 jmcneill { 3017 1.17.2.2 jmcneill struct radeonfb_softc *sc = dp->rd_softc; 3018 1.17.2.2 jmcneill uint32_t offset, hvoff, hvpos; /* registers */ 3019 1.17.2.2 jmcneill uint32_t coff; /* cursor offset */ 3020 1.17.2.2 jmcneill int i, x, y, xoff, yoff, crtcoff; 3021 1.17.2.2 jmcneill 3022 1.17.2.2 jmcneill /* 3023 1.17.2.2 jmcneill * XXX: this also needs to handle pan/scan 3024 1.17.2.2 jmcneill */ 3025 1.17.2.2 jmcneill for (i = 0; i < dp->rd_ncrtcs; i++) { 3026 1.17.2.2 jmcneill 3027 1.17.2.2 jmcneill struct radeonfb_crtc *rcp = &dp->rd_crtcs[i]; 3028 1.17.2.2 jmcneill 3029 1.17.2.2 jmcneill if (rcp->rc_number) { 3030 1.17.2.2 jmcneill offset = RADEON_CUR2_OFFSET; 3031 1.17.2.2 jmcneill hvoff = RADEON_CUR2_HORZ_VERT_OFF; 3032 1.17.2.2 jmcneill hvpos = RADEON_CUR2_HORZ_VERT_POSN; 3033 1.17.2.2 jmcneill crtcoff = RADEON_CRTC2_OFFSET; 3034 1.17.2.2 jmcneill } else { 3035 1.17.2.2 jmcneill offset = RADEON_CUR_OFFSET; 3036 1.17.2.2 jmcneill hvoff = RADEON_CUR_HORZ_VERT_OFF; 3037 1.17.2.2 jmcneill hvpos = RADEON_CUR_HORZ_VERT_POSN; 3038 1.17.2.2 jmcneill crtcoff = RADEON_CRTC_OFFSET; 3039 1.17.2.2 jmcneill } 3040 1.17.2.2 jmcneill 3041 1.17.2.2 jmcneill x = dp->rd_cursor.rc_pos.x; 3042 1.17.2.2 jmcneill y = dp->rd_cursor.rc_pos.y; 3043 1.17.2.2 jmcneill 3044 1.17.2.2 jmcneill while (y < rcp->rc_yoffset) { 3045 1.17.2.2 jmcneill rcp->rc_yoffset -= RADEON_PANINCREMENT; 3046 1.17.2.2 jmcneill } 3047 1.17.2.2 jmcneill while (y >= (rcp->rc_yoffset + rcp->rc_videomode.vdisplay)) { 3048 1.17.2.2 jmcneill rcp->rc_yoffset += RADEON_PANINCREMENT; 3049 1.17.2.2 jmcneill } 3050 1.17.2.2 jmcneill while (x < rcp->rc_xoffset) { 3051 1.17.2.2 jmcneill rcp->rc_xoffset -= RADEON_PANINCREMENT; 3052 1.17.2.2 jmcneill } 3053 1.17.2.2 jmcneill while (x >= (rcp->rc_xoffset + rcp->rc_videomode.hdisplay)) { 3054 1.17.2.2 jmcneill rcp->rc_xoffset += RADEON_PANINCREMENT; 3055 1.17.2.2 jmcneill } 3056 1.17.2.2 jmcneill 3057 1.17.2.2 jmcneill /* adjust for the cursor's hotspot */ 3058 1.17.2.2 jmcneill x -= dp->rd_cursor.rc_hot.x; 3059 1.17.2.2 jmcneill y -= dp->rd_cursor.rc_hot.y; 3060 1.17.2.2 jmcneill xoff = yoff = 0; 3061 1.17.2.2 jmcneill 3062 1.17.2.2 jmcneill if (x >= dp->rd_virtx) 3063 1.17.2.2 jmcneill x = dp->rd_virtx - 1; 3064 1.17.2.2 jmcneill if (y >= dp->rd_virty) 3065 1.17.2.2 jmcneill y = dp->rd_virty - 1; 3066 1.17.2.2 jmcneill 3067 1.17.2.2 jmcneill /* now adjust cursor so it is relative to viewport */ 3068 1.17.2.2 jmcneill x -= rcp->rc_xoffset; 3069 1.17.2.2 jmcneill y -= rcp->rc_yoffset; 3070 1.17.2.2 jmcneill 3071 1.17.2.2 jmcneill /* 3072 1.17.2.2 jmcneill * no need to check for fall off, because we should 3073 1.17.2.2 jmcneill * never move off the screen entirely! 3074 1.17.2.2 jmcneill */ 3075 1.17.2.2 jmcneill coff = 0; 3076 1.17.2.2 jmcneill if (x < 0) { 3077 1.17.2.2 jmcneill xoff = -x; 3078 1.17.2.2 jmcneill x = 0; 3079 1.17.2.2 jmcneill } 3080 1.17.2.2 jmcneill if (y < 0) { 3081 1.17.2.2 jmcneill yoff = -y; 3082 1.17.2.2 jmcneill y = 0; 3083 1.17.2.2 jmcneill coff = (yoff * 2) * 8; 3084 1.17.2.2 jmcneill } 3085 1.17.2.2 jmcneill 3086 1.17.2.2 jmcneill /* pan the display */ 3087 1.17.2.2 jmcneill PUT32(sc, crtcoff, (rcp->rc_yoffset * dp->rd_stride) + 3088 1.17.2.2 jmcneill rcp->rc_xoffset); 3089 1.17.2.2 jmcneill 3090 1.17.2.2 jmcneill PUT32(sc, offset, (dp->rd_curoff + coff) | RADEON_CUR_LOCK); 3091 1.17.2.2 jmcneill PUT32(sc, hvoff, (xoff << 16) | (yoff) | RADEON_CUR_LOCK); 3092 1.17.2.2 jmcneill /* NB: this unlocks the cursor */ 3093 1.17.2.2 jmcneill PUT32(sc, hvpos, (x << 16) | y); 3094 1.17.2.2 jmcneill } 3095 1.17.2.2 jmcneill } 3096 1.17.2.2 jmcneill 3097 1.17.2.2 jmcneill static void 3098 1.17.2.2 jmcneill radeonfb_cursor_visible(struct radeonfb_display *dp) 3099 1.17.2.2 jmcneill { 3100 1.17.2.2 jmcneill int i; 3101 1.17.2.2 jmcneill uint32_t gencntl, bit; 3102 1.17.2.2 jmcneill 3103 1.17.2.2 jmcneill for (i = 0; i < dp->rd_ncrtcs; i++) { 3104 1.17.2.2 jmcneill if (dp->rd_crtcs[i].rc_number) { 3105 1.17.2.2 jmcneill gencntl = RADEON_CRTC2_GEN_CNTL; 3106 1.17.2.2 jmcneill bit = RADEON_CRTC2_CUR_EN; 3107 1.17.2.2 jmcneill } else { 3108 1.17.2.2 jmcneill gencntl = RADEON_CRTC_GEN_CNTL; 3109 1.17.2.2 jmcneill bit = RADEON_CRTC_CUR_EN; 3110 1.17.2.2 jmcneill } 3111 1.17.2.2 jmcneill 3112 1.17.2.2 jmcneill if (dp->rd_cursor.rc_visible) 3113 1.17.2.2 jmcneill SET32(dp->rd_softc, gencntl, bit); 3114 1.17.2.2 jmcneill else 3115 1.17.2.2 jmcneill CLR32(dp->rd_softc, gencntl, bit); 3116 1.17.2.2 jmcneill } 3117 1.17.2.2 jmcneill } 3118 1.17.2.2 jmcneill 3119 1.17.2.2 jmcneill static void 3120 1.17.2.2 jmcneill radeonfb_cursor_cmap(struct radeonfb_display *dp) 3121 1.17.2.2 jmcneill { 3122 1.17.2.2 jmcneill int i; 3123 1.17.2.2 jmcneill uint32_t c0reg, c1reg; 3124 1.17.2.2 jmcneill struct radeonfb_softc *sc = dp->rd_softc; 3125 1.17.2.2 jmcneill 3126 1.17.2.2 jmcneill for (i = 0; i < dp->rd_ncrtcs; i++) { 3127 1.17.2.2 jmcneill if (dp->rd_crtcs[i].rc_number) { 3128 1.17.2.2 jmcneill c0reg = RADEON_CUR2_CLR0; 3129 1.17.2.2 jmcneill c1reg = RADEON_CUR2_CLR1; 3130 1.17.2.2 jmcneill } else { 3131 1.17.2.2 jmcneill c0reg = RADEON_CUR_CLR0; 3132 1.17.2.2 jmcneill c1reg = RADEON_CUR_CLR1; 3133 1.17.2.2 jmcneill } 3134 1.17.2.2 jmcneill 3135 1.17.2.2 jmcneill PUT32(sc, c0reg, dp->rd_cursor.rc_cmap[0]); 3136 1.17.2.2 jmcneill PUT32(sc, c1reg, dp->rd_cursor.rc_cmap[1]); 3137 1.17.2.2 jmcneill } 3138 1.17.2.2 jmcneill } 3139 1.17.2.2 jmcneill 3140 1.17.2.2 jmcneill static void 3141 1.17.2.2 jmcneill radeonfb_cursor_update(struct radeonfb_display *dp, unsigned which) 3142 1.17.2.2 jmcneill { 3143 1.17.2.2 jmcneill struct radeonfb_softc *sc; 3144 1.17.2.2 jmcneill int i; 3145 1.17.2.2 jmcneill 3146 1.17.2.2 jmcneill sc = dp->rd_softc; 3147 1.17.2.2 jmcneill for (i = 0; i < dp->rd_ncrtcs; i++) { 3148 1.17.2.2 jmcneill if (dp->rd_crtcs[i].rc_number) { 3149 1.17.2.2 jmcneill SET32(sc, RADEON_CUR2_OFFSET, RADEON_CUR_LOCK); 3150 1.17.2.2 jmcneill } else { 3151 1.17.2.2 jmcneill SET32(sc, RADEON_CUR_OFFSET,RADEON_CUR_LOCK); 3152 1.17.2.2 jmcneill } 3153 1.17.2.2 jmcneill } 3154 1.17.2.2 jmcneill 3155 1.17.2.2 jmcneill if (which & WSDISPLAY_CURSOR_DOCMAP) 3156 1.17.2.2 jmcneill radeonfb_cursor_cmap(dp); 3157 1.17.2.2 jmcneill 3158 1.17.2.2 jmcneill if (which & WSDISPLAY_CURSOR_DOSHAPE) 3159 1.17.2.2 jmcneill radeonfb_cursor_shape(dp); 3160 1.17.2.2 jmcneill 3161 1.17.2.2 jmcneill if (which & WSDISPLAY_CURSOR_DOCUR) 3162 1.17.2.2 jmcneill radeonfb_cursor_visible(dp); 3163 1.17.2.2 jmcneill 3164 1.17.2.2 jmcneill /* this one is unconditional, because it updates other stuff */ 3165 1.17.2.2 jmcneill radeonfb_cursor_position(dp); 3166 1.17.2.2 jmcneill } 3167 1.17.2.2 jmcneill 3168 1.17.2.2 jmcneill static struct videomode * 3169 1.17.2.2 jmcneill radeonfb_best_refresh(struct videomode *m1, struct videomode *m2) 3170 1.17.2.2 jmcneill { 3171 1.17.2.2 jmcneill int r1, r2; 3172 1.17.2.2 jmcneill 3173 1.17.2.2 jmcneill /* otherwise pick the higher refresh rate */ 3174 1.17.2.2 jmcneill r1 = DIVIDE(DIVIDE(m1->dot_clock, m1->htotal), m1->vtotal); 3175 1.17.2.2 jmcneill r2 = DIVIDE(DIVIDE(m2->dot_clock, m2->htotal), m2->vtotal); 3176 1.17.2.2 jmcneill 3177 1.17.2.2 jmcneill return (r1 < r2 ? m2 : m1); 3178 1.17.2.2 jmcneill } 3179 1.17.2.2 jmcneill 3180 1.17.2.2 jmcneill static const struct videomode * 3181 1.17.2.2 jmcneill radeonfb_port_mode(struct radeonfb_softc *sc, struct radeonfb_port *rp, 3182 1.17.2.2 jmcneill int x, int y) 3183 1.17.2.2 jmcneill { 3184 1.17.2.2 jmcneill struct edid_info *ep = &rp->rp_edid; 3185 1.17.2.2 jmcneill struct videomode *vmp = NULL; 3186 1.17.2.2 jmcneill int i; 3187 1.17.2.2 jmcneill 3188 1.17.2.2 jmcneill if (!rp->rp_edid_valid) { 3189 1.17.2.2 jmcneill /* fallback to safe mode */ 3190 1.17.2.2 jmcneill return radeonfb_modelookup(sc->sc_defaultmode); 3191 1.17.2.2 jmcneill } 3192 1.17.2.2 jmcneill 3193 1.17.2.2 jmcneill /* always choose the preferred mode first! */ 3194 1.17.2.2 jmcneill if (ep->edid_preferred_mode) { 3195 1.17.2.2 jmcneill 3196 1.17.2.2 jmcneill /* XXX: add auto-stretching support for native mode */ 3197 1.17.2.2 jmcneill 3198 1.17.2.2 jmcneill /* this may want panning to occur, btw */ 3199 1.17.2.2 jmcneill if ((ep->edid_preferred_mode->hdisplay <= x) && 3200 1.17.2.2 jmcneill (ep->edid_preferred_mode->vdisplay <= y)) 3201 1.17.2.2 jmcneill return ep->edid_preferred_mode; 3202 1.17.2.2 jmcneill } 3203 1.17.2.2 jmcneill 3204 1.17.2.2 jmcneill for (i = 0; i < ep->edid_nmodes; i++) { 3205 1.17.2.2 jmcneill /* 3206 1.17.2.2 jmcneill * We elect to pick a resolution that is too large for 3207 1.17.2.2 jmcneill * the monitor than one that is too small. This means 3208 1.17.2.2 jmcneill * that we will prefer to pan rather than to try to 3209 1.17.2.2 jmcneill * center a smaller display on a larger screen. In 3210 1.17.2.2 jmcneill * practice, this shouldn't matter because if a 3211 1.17.2.2 jmcneill * monitor can support a larger resolution, it can 3212 1.17.2.2 jmcneill * probably also support the smaller. A specific 3213 1.17.2.2 jmcneill * exception is fixed format panels, but hopefully 3214 1.17.2.2 jmcneill * they are properly dealt with by the "autostretch" 3215 1.17.2.2 jmcneill * logic above. 3216 1.17.2.2 jmcneill */ 3217 1.17.2.2 jmcneill if ((ep->edid_modes[i].hdisplay > x) || 3218 1.17.2.2 jmcneill (ep->edid_modes[i].vdisplay > y)) { 3219 1.17.2.2 jmcneill continue; 3220 1.17.2.2 jmcneill } 3221 1.17.2.2 jmcneill 3222 1.17.2.2 jmcneill /* 3223 1.17.2.2 jmcneill * at this point, the display mode is no larger than 3224 1.17.2.2 jmcneill * what we've requested. 3225 1.17.2.2 jmcneill */ 3226 1.17.2.2 jmcneill if (vmp == NULL) 3227 1.17.2.2 jmcneill vmp = &ep->edid_modes[i]; 3228 1.17.2.2 jmcneill 3229 1.17.2.2 jmcneill /* eliminate smaller modes */ 3230 1.17.2.2 jmcneill if ((vmp->hdisplay >= ep->edid_modes[i].hdisplay) || 3231 1.17.2.2 jmcneill (vmp->vdisplay >= ep->edid_modes[i].vdisplay)) 3232 1.17.2.2 jmcneill continue; 3233 1.17.2.2 jmcneill 3234 1.17.2.2 jmcneill if ((vmp->hdisplay < ep->edid_modes[i].hdisplay) || 3235 1.17.2.2 jmcneill (vmp->vdisplay < ep->edid_modes[i].vdisplay)) { 3236 1.17.2.2 jmcneill vmp = &ep->edid_modes[i]; 3237 1.17.2.2 jmcneill continue; 3238 1.17.2.2 jmcneill } 3239 1.17.2.2 jmcneill 3240 1.17.2.2 jmcneill KASSERT(vmp->hdisplay == ep->edid_modes[i].hdisplay); 3241 1.17.2.2 jmcneill KASSERT(vmp->vdisplay == ep->edid_modes[i].vdisplay); 3242 1.17.2.2 jmcneill 3243 1.17.2.2 jmcneill vmp = radeonfb_best_refresh(vmp, &ep->edid_modes[i]); 3244 1.17.2.2 jmcneill } 3245 1.17.2.2 jmcneill 3246 1.17.2.2 jmcneill return (vmp ? vmp : radeonfb_modelookup(sc->sc_defaultmode)); 3247 1.17.2.2 jmcneill } 3248 1.17.2.2 jmcneill 3249 1.17.2.2 jmcneill static int 3250 1.17.2.2 jmcneill radeonfb_hasres(struct videomode *list, int nlist, int x, int y) 3251 1.17.2.2 jmcneill { 3252 1.17.2.2 jmcneill int i; 3253 1.17.2.2 jmcneill 3254 1.17.2.2 jmcneill for (i = 0; i < nlist; i++) { 3255 1.17.2.2 jmcneill if ((x == list[i].hdisplay) && 3256 1.17.2.2 jmcneill (y == list[i].vdisplay)) { 3257 1.17.2.2 jmcneill return 1; 3258 1.17.2.2 jmcneill } 3259 1.17.2.2 jmcneill } 3260 1.17.2.2 jmcneill return 0; 3261 1.17.2.2 jmcneill } 3262 1.17.2.2 jmcneill 3263 1.17.2.2 jmcneill static void 3264 1.17.2.2 jmcneill radeonfb_pickres(struct radeonfb_display *dp, uint16_t *x, uint16_t *y, 3265 1.17.2.2 jmcneill int pan) 3266 1.17.2.2 jmcneill { 3267 1.17.2.2 jmcneill struct radeonfb_port *rp; 3268 1.17.2.2 jmcneill struct edid_info *ep; 3269 1.17.2.2 jmcneill int i, j; 3270 1.17.2.2 jmcneill 3271 1.17.2.2 jmcneill *x = 0; 3272 1.17.2.2 jmcneill *y = 0; 3273 1.17.2.2 jmcneill 3274 1.17.2.2 jmcneill if (pan) { 3275 1.17.2.2 jmcneill for (i = 0; i < dp->rd_ncrtcs; i++) { 3276 1.17.2.2 jmcneill rp = dp->rd_crtcs[i].rc_port; 3277 1.17.2.2 jmcneill ep = &rp->rp_edid; 3278 1.17.2.2 jmcneill if (!rp->rp_edid_valid) { 3279 1.17.2.2 jmcneill /* monitor not present */ 3280 1.17.2.2 jmcneill continue; 3281 1.17.2.2 jmcneill } 3282 1.17.2.2 jmcneill 3283 1.17.2.2 jmcneill /* 3284 1.17.2.2 jmcneill * For now we are ignoring "conflict" that 3285 1.17.2.2 jmcneill * could occur when mixing some modes like 3286 1.17.2.2 jmcneill * 1280x1024 and 1400x800. It isn't clear 3287 1.17.2.2 jmcneill * which is better, so the first one wins. 3288 1.17.2.2 jmcneill */ 3289 1.17.2.2 jmcneill for (j = 0; j < ep->edid_nmodes; j++) { 3290 1.17.2.2 jmcneill /* 3291 1.17.2.2 jmcneill * ignore resolutions that are too big for 3292 1.17.2.2 jmcneill * the radeon 3293 1.17.2.2 jmcneill */ 3294 1.17.2.2 jmcneill if (ep->edid_modes[j].hdisplay > 3295 1.17.2.2 jmcneill dp->rd_softc->sc_maxx) 3296 1.17.2.2 jmcneill continue; 3297 1.17.2.2 jmcneill if (ep->edid_modes[j].vdisplay > 3298 1.17.2.2 jmcneill dp->rd_softc->sc_maxy) 3299 1.17.2.2 jmcneill continue; 3300 1.17.2.2 jmcneill 3301 1.17.2.2 jmcneill /* 3302 1.17.2.2 jmcneill * pick largest resolution, the 3303 1.17.2.2 jmcneill * smaller monitor will pan 3304 1.17.2.2 jmcneill */ 3305 1.17.2.2 jmcneill if ((ep->edid_modes[j].hdisplay >= *x) && 3306 1.17.2.2 jmcneill (ep->edid_modes[j].vdisplay >= *y)) { 3307 1.17.2.2 jmcneill *x = ep->edid_modes[j].hdisplay; 3308 1.17.2.2 jmcneill *y = ep->edid_modes[j].vdisplay; 3309 1.17.2.2 jmcneill } 3310 1.17.2.2 jmcneill } 3311 1.17.2.2 jmcneill } 3312 1.17.2.2 jmcneill 3313 1.17.2.2 jmcneill } else { 3314 1.17.2.2 jmcneill struct videomode modes[64]; 3315 1.17.2.2 jmcneill int nmodes = 0; 3316 1.17.2.2 jmcneill int valid = 0; 3317 1.17.2.2 jmcneill 3318 1.17.2.2 jmcneill for (i = 0; i < dp->rd_ncrtcs; i++) { 3319 1.17.2.2 jmcneill /* 3320 1.17.2.2 jmcneill * pick the largest resolution in common. 3321 1.17.2.2 jmcneill */ 3322 1.17.2.2 jmcneill rp = dp->rd_crtcs[i].rc_port; 3323 1.17.2.2 jmcneill ep = &rp->rp_edid; 3324 1.17.2.2 jmcneill 3325 1.17.2.2 jmcneill if (!rp->rp_edid_valid) 3326 1.17.2.2 jmcneill continue; 3327 1.17.2.2 jmcneill 3328 1.17.2.2 jmcneill if (!valid) { 3329 1.17.2.2 jmcneill /* initialize starting list */ 3330 1.17.2.2 jmcneill for (j = 0; j < ep->edid_nmodes; j++) { 3331 1.17.2.2 jmcneill /* 3332 1.17.2.2 jmcneill * ignore resolutions that are 3333 1.17.2.2 jmcneill * too big for the radeon 3334 1.17.2.2 jmcneill */ 3335 1.17.2.2 jmcneill if (ep->edid_modes[j].hdisplay > 3336 1.17.2.2 jmcneill dp->rd_softc->sc_maxx) 3337 1.17.2.2 jmcneill continue; 3338 1.17.2.2 jmcneill if (ep->edid_modes[j].vdisplay > 3339 1.17.2.2 jmcneill dp->rd_softc->sc_maxy) 3340 1.17.2.2 jmcneill continue; 3341 1.17.2.2 jmcneill 3342 1.17.2.2 jmcneill modes[nmodes] = ep->edid_modes[j]; 3343 1.17.2.2 jmcneill nmodes++; 3344 1.17.2.2 jmcneill } 3345 1.17.2.2 jmcneill valid = 1; 3346 1.17.2.2 jmcneill } else { 3347 1.17.2.2 jmcneill /* merge into preexisting list */ 3348 1.17.2.2 jmcneill for (j = 0; j < nmodes; j++) { 3349 1.17.2.2 jmcneill if (!radeonfb_hasres(ep->edid_modes, 3350 1.17.2.2 jmcneill ep->edid_nmodes, 3351 1.17.2.2 jmcneill modes[j].hdisplay, 3352 1.17.2.2 jmcneill modes[j].vdisplay)) { 3353 1.17.2.2 jmcneill modes[j] = modes[nmodes]; 3354 1.17.2.2 jmcneill j--; 3355 1.17.2.2 jmcneill nmodes--; 3356 1.17.2.2 jmcneill } 3357 1.17.2.2 jmcneill } 3358 1.17.2.2 jmcneill } 3359 1.17.2.2 jmcneill } 3360 1.17.2.2 jmcneill 3361 1.17.2.2 jmcneill /* now we have to pick from the merged list */ 3362 1.17.2.2 jmcneill for (i = 0; i < nmodes; i++) { 3363 1.17.2.2 jmcneill if ((modes[i].hdisplay >= *x) && 3364 1.17.2.2 jmcneill (modes[i].vdisplay >= *y)) { 3365 1.17.2.2 jmcneill *x = modes[i].hdisplay; 3366 1.17.2.2 jmcneill *y = modes[i].vdisplay; 3367 1.17.2.2 jmcneill } 3368 1.17.2.2 jmcneill } 3369 1.17.2.2 jmcneill } 3370 1.17.2.2 jmcneill 3371 1.17.2.2 jmcneill if ((*x == 0) || (*y == 0)) { 3372 1.17.2.2 jmcneill /* fallback to safe mode */ 3373 1.17.2.2 jmcneill *x = 640; 3374 1.17.2.2 jmcneill *y = 480; 3375 1.17.2.2 jmcneill } 3376 1.17.2.2 jmcneill } 3377 1.17.2.2 jmcneill 3378 1.17.2.2 jmcneill /* 3379 1.17.2.2 jmcneill * backlight levels are linear on: 3380 1.17.2.2 jmcneill * - RV200, RV250, RV280, RV350 3381 1.17.2.2 jmcneill * - but NOT on PowerBook4,3 6,3 6,5 3382 1.17.2.2 jmcneill * according to Linux' radeonfb 3383 1.17.2.2 jmcneill */ 3384 1.17.2.2 jmcneill 3385 1.17.2.2 jmcneill /* Get the current backlight level for the display. */ 3386 1.17.2.2 jmcneill 3387 1.17.2.2 jmcneill static int 3388 1.17.2.2 jmcneill radeonfb_get_backlight(struct radeonfb_display *dp) 3389 1.17.2.2 jmcneill { 3390 1.17.2.2 jmcneill int s; 3391 1.17.2.2 jmcneill uint32_t level; 3392 1.17.2.2 jmcneill 3393 1.17.2.2 jmcneill s = spltty(); 3394 1.17.2.2 jmcneill 3395 1.17.2.2 jmcneill level = radeonfb_get32(dp->rd_softc, RADEON_LVDS_GEN_CNTL); 3396 1.17.2.2 jmcneill level &= RADEON_LVDS_BL_MOD_LEV_MASK; 3397 1.17.2.2 jmcneill level >>= RADEON_LVDS_BL_MOD_LEV_SHIFT; 3398 1.17.2.2 jmcneill 3399 1.17.2.2 jmcneill /* 3400 1.17.2.2 jmcneill * On some chips, we should negate the backlight level. 3401 1.17.2.2 jmcneill * XXX Find out on which chips. 3402 1.17.2.2 jmcneill */ 3403 1.17.2.2 jmcneill if (dp->rd_softc->sc_flags & RFB_INV_BLIGHT) 3404 1.17.2.2 jmcneill level = RADEONFB_BACKLIGHT_MAX - level; 3405 1.17.2.2 jmcneill 3406 1.17.2.2 jmcneill splx(s); 3407 1.17.2.2 jmcneill 3408 1.17.2.2 jmcneill return level; 3409 1.17.2.2 jmcneill } 3410 1.17.2.2 jmcneill 3411 1.17.2.2 jmcneill /* Set the backlight to the given level for the display. */ 3412 1.17.2.2 jmcneill 3413 1.17.2.2 jmcneill static int 3414 1.17.2.2 jmcneill radeonfb_set_backlight(struct radeonfb_display *dp, int level) 3415 1.17.2.2 jmcneill { 3416 1.17.2.2 jmcneill struct radeonfb_softc *sc; 3417 1.17.2.2 jmcneill int rlevel, s; 3418 1.17.2.2 jmcneill uint32_t lvds; 3419 1.17.2.2 jmcneill 3420 1.17.2.2 jmcneill s = spltty(); 3421 1.17.2.2 jmcneill 3422 1.17.2.2 jmcneill if (level < 0) 3423 1.17.2.2 jmcneill level = 0; 3424 1.17.2.2 jmcneill else if (level >= RADEONFB_BACKLIGHT_MAX) 3425 1.17.2.2 jmcneill level = RADEONFB_BACKLIGHT_MAX; 3426 1.17.2.2 jmcneill 3427 1.17.2.2 jmcneill sc = dp->rd_softc; 3428 1.17.2.2 jmcneill 3429 1.17.2.2 jmcneill /* On some chips, we should negate the backlight level. */ 3430 1.17.2.2 jmcneill if (dp->rd_softc->sc_flags & RFB_INV_BLIGHT) { 3431 1.17.2.2 jmcneill rlevel = RADEONFB_BACKLIGHT_MAX - level; 3432 1.17.2.2 jmcneill } else 3433 1.17.2.2 jmcneill rlevel = level; 3434 1.17.2.2 jmcneill 3435 1.17.2.2 jmcneill callout_stop(&dp->rd_bl_lvds_co); 3436 1.17.2.2 jmcneill radeonfb_engine_idle(sc); 3437 1.17.2.2 jmcneill 3438 1.17.2.2 jmcneill /* 3439 1.17.2.2 jmcneill * Turn off the display if the backlight is set to 0, since the 3440 1.17.2.2 jmcneill * display is useless without backlight anyway. 3441 1.17.2.2 jmcneill */ 3442 1.17.2.2 jmcneill if (level == 0) 3443 1.17.2.2 jmcneill radeonfb_blank(dp, 1); 3444 1.17.2.2 jmcneill else if (radeonfb_get_backlight(dp) == 0) 3445 1.17.2.2 jmcneill radeonfb_blank(dp, 0); 3446 1.17.2.2 jmcneill 3447 1.17.2.2 jmcneill lvds = radeonfb_get32(sc, RADEON_LVDS_GEN_CNTL); 3448 1.17.2.2 jmcneill lvds &= ~RADEON_LVDS_DISPLAY_DIS; 3449 1.17.2.2 jmcneill if (!(lvds & RADEON_LVDS_BLON) || !(lvds & RADEON_LVDS_ON)) { 3450 1.17.2.2 jmcneill lvds |= dp->rd_bl_lvds_val & RADEON_LVDS_DIGON; 3451 1.17.2.2 jmcneill lvds |= RADEON_LVDS_BLON | RADEON_LVDS_EN; 3452 1.17.2.2 jmcneill radeonfb_put32(sc, RADEON_LVDS_GEN_CNTL, lvds); 3453 1.17.2.2 jmcneill lvds &= ~RADEON_LVDS_BL_MOD_LEV_MASK; 3454 1.17.2.2 jmcneill lvds |= rlevel << RADEON_LVDS_BL_MOD_LEV_SHIFT; 3455 1.17.2.2 jmcneill lvds |= RADEON_LVDS_ON; 3456 1.17.2.2 jmcneill lvds |= dp->rd_bl_lvds_val & RADEON_LVDS_BL_MOD_EN; 3457 1.17.2.2 jmcneill } else { 3458 1.17.2.2 jmcneill lvds &= ~RADEON_LVDS_BL_MOD_LEV_MASK; 3459 1.17.2.2 jmcneill lvds |= rlevel << RADEON_LVDS_BL_MOD_LEV_SHIFT; 3460 1.17.2.2 jmcneill radeonfb_put32(sc, RADEON_LVDS_GEN_CNTL, lvds); 3461 1.17.2.2 jmcneill } 3462 1.17.2.2 jmcneill 3463 1.17.2.2 jmcneill dp->rd_bl_lvds_val &= ~RADEON_LVDS_STATE_MASK; 3464 1.17.2.2 jmcneill dp->rd_bl_lvds_val |= lvds & RADEON_LVDS_STATE_MASK; 3465 1.17.2.2 jmcneill /* XXX What is the correct delay? */ 3466 1.17.2.2 jmcneill callout_schedule(&dp->rd_bl_lvds_co, 200 * hz); 3467 1.17.2.2 jmcneill 3468 1.17.2.2 jmcneill splx(s); 3469 1.17.2.2 jmcneill 3470 1.17.2.2 jmcneill return 0; 3471 1.17.2.2 jmcneill } 3472 1.17.2.2 jmcneill 3473 1.17.2.2 jmcneill /* 3474 1.17.2.2 jmcneill * Callout function for delayed operations on the LVDS_GEN_CNTL register. 3475 1.17.2.2 jmcneill * Set the delayed bits in the register, and clear the stored delayed 3476 1.17.2.2 jmcneill * value. 3477 1.17.2.2 jmcneill */ 3478 1.17.2.2 jmcneill 3479 1.17.2.2 jmcneill static void radeonfb_lvds_callout(void *arg) 3480 1.17.2.2 jmcneill { 3481 1.17.2.2 jmcneill struct radeonfb_display *dp = arg; 3482 1.17.2.2 jmcneill int s; 3483 1.17.2.2 jmcneill 3484 1.17.2.2 jmcneill s = splhigh(); 3485 1.17.2.2 jmcneill 3486 1.17.2.2 jmcneill radeonfb_mask32(dp->rd_softc, RADEON_LVDS_GEN_CNTL, ~0, 3487 1.17.2.2 jmcneill dp->rd_bl_lvds_val); 3488 1.17.2.2 jmcneill dp->rd_bl_lvds_val = 0; 3489 1.17.2.2 jmcneill 3490 1.17.2.2 jmcneill splx(s); 3491 1.17.2.2 jmcneill } 3492
Indexes created Thu Oct 23 22:10:10 GMT 2025