radeonfb.c revision 1.5.6.2
1 1.5.6.2 rpaulo /* $NetBSD: radeonfb.c,v 1.5.6.2 2006/09/09 02:52:19 rpaulo Exp $ */ 2 1.5.6.2 rpaulo 3 1.5.6.2 rpaulo /*- 4 1.5.6.2 rpaulo * Copyright (c) 2006 Itronix Inc. 5 1.5.6.2 rpaulo * All rights reserved. 6 1.5.6.2 rpaulo * 7 1.5.6.2 rpaulo * Written by Garrett D'Amore for Itronix Inc. 8 1.5.6.2 rpaulo * 9 1.5.6.2 rpaulo * Redistribution and use in source and binary forms, with or without 10 1.5.6.2 rpaulo * modification, are permitted provided that the following conditions 11 1.5.6.2 rpaulo * are met: 12 1.5.6.2 rpaulo * 1. Redistributions of source code must retain the above copyright 13 1.5.6.2 rpaulo * notice, this list of conditions and the following disclaimer. 14 1.5.6.2 rpaulo * 2. Redistributions in binary form must reproduce the above copyright 15 1.5.6.2 rpaulo * notice, this list of conditions and the following disclaimer in the 16 1.5.6.2 rpaulo * documentation and/or other materials provided with the distribution. 17 1.5.6.2 rpaulo * 3. The name of Itronix Inc. may not be used to endorse 18 1.5.6.2 rpaulo * or promote products derived from this software without specific 19 1.5.6.2 rpaulo * prior written permission. 20 1.5.6.2 rpaulo * 21 1.5.6.2 rpaulo * THIS SOFTWARE IS PROVIDED BY ITRONIX INC. ``AS IS'' AND ANY EXPRESS 22 1.5.6.2 rpaulo * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 23 1.5.6.2 rpaulo * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 1.5.6.2 rpaulo * ARE DISCLAIMED. IN NO EVENT SHALL ITRONIX INC. BE LIABLE FOR ANY 25 1.5.6.2 rpaulo * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 26 1.5.6.2 rpaulo * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE 27 1.5.6.2 rpaulo * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 1.5.6.2 rpaulo * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 29 1.5.6.2 rpaulo * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 30 1.5.6.2 rpaulo * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 31 1.5.6.2 rpaulo * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 1.5.6.2 rpaulo */ 33 1.5.6.2 rpaulo 34 1.5.6.2 rpaulo /* 35 1.5.6.2 rpaulo * ATI Technologies Inc. ("ATI") has not assisted in the creation of, and 36 1.5.6.2 rpaulo * does not endorse, this software. ATI will not be responsible or liable 37 1.5.6.2 rpaulo * for any actual or alleged damage or loss caused by or in connection with 38 1.5.6.2 rpaulo * the use of or reliance on this software. 39 1.5.6.2 rpaulo */ 40 1.5.6.2 rpaulo 41 1.5.6.2 rpaulo /* 42 1.5.6.2 rpaulo * Portions of this code were taken from XFree86's Radeon driver, which bears 43 1.5.6.2 rpaulo * this notice: 44 1.5.6.2 rpaulo * 45 1.5.6.2 rpaulo * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and 46 1.5.6.2 rpaulo * VA Linux Systems Inc., Fremont, California. 47 1.5.6.2 rpaulo * 48 1.5.6.2 rpaulo * All Rights Reserved. 49 1.5.6.2 rpaulo * 50 1.5.6.2 rpaulo * Permission is hereby granted, free of charge, to any person obtaining 51 1.5.6.2 rpaulo * a copy of this software and associated documentation files (the 52 1.5.6.2 rpaulo * "Software"), to deal in the Software without restriction, including 53 1.5.6.2 rpaulo * without limitation on the rights to use, copy, modify, merge, 54 1.5.6.2 rpaulo * publish, distribute, sublicense, and/or sell copies of the Software, 55 1.5.6.2 rpaulo * and to permit persons to whom the Software is furnished to do so, 56 1.5.6.2 rpaulo * subject to the following conditions: 57 1.5.6.2 rpaulo * 58 1.5.6.2 rpaulo * The above copyright notice and this permission notice (including the 59 1.5.6.2 rpaulo * next paragraph) shall be included in all copies or substantial 60 1.5.6.2 rpaulo * portions of the Software. 61 1.5.6.2 rpaulo * 62 1.5.6.2 rpaulo * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 63 1.5.6.2 rpaulo * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 64 1.5.6.2 rpaulo * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 65 1.5.6.2 rpaulo * NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR 66 1.5.6.2 rpaulo * THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 67 1.5.6.2 rpaulo * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 68 1.5.6.2 rpaulo * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 69 1.5.6.2 rpaulo * DEALINGS IN THE SOFTWARE. 70 1.5.6.2 rpaulo */ 71 1.5.6.2 rpaulo 72 1.5.6.2 rpaulo #include <sys/cdefs.h> 73 1.5.6.2 rpaulo __KERNEL_RCSID(0, "$NetBSD: radeonfb.c,v 1.5.6.2 2006/09/09 02:52:19 rpaulo Exp $"); 74 1.5.6.2 rpaulo 75 1.5.6.2 rpaulo #define RADEONFB_DEFAULT_DEPTH 32 76 1.5.6.2 rpaulo 77 1.5.6.2 rpaulo #include <sys/param.h> 78 1.5.6.2 rpaulo #include <sys/systm.h> 79 1.5.6.2 rpaulo #include <sys/device.h> 80 1.5.6.2 rpaulo #include <sys/malloc.h> 81 1.5.6.2 rpaulo #include <machine/bus.h> 82 1.5.6.2 rpaulo #include <sys/kernel.h> 83 1.5.6.2 rpaulo #include <sys/lwp.h> 84 1.5.6.2 rpaulo #include <sys/kauth.h> 85 1.5.6.2 rpaulo 86 1.5.6.2 rpaulo #include <dev/wscons/wsdisplayvar.h> 87 1.5.6.2 rpaulo #include <dev/wscons/wsconsio.h> 88 1.5.6.2 rpaulo #include <dev/wsfont/wsfont.h> 89 1.5.6.2 rpaulo #include <dev/rasops/rasops.h> 90 1.5.6.2 rpaulo #include <dev/videomode/videomode.h> 91 1.5.6.2 rpaulo #include <dev/videomode/edidvar.h> 92 1.5.6.2 rpaulo #include <dev/wscons/wsdisplay_vconsvar.h> 93 1.5.6.2 rpaulo 94 1.5.6.2 rpaulo #include <dev/pci/pcidevs.h> 95 1.5.6.2 rpaulo #include <dev/pci/pcireg.h> 96 1.5.6.2 rpaulo #include <dev/pci/pcivar.h> 97 1.5.6.2 rpaulo #include <dev/pci/radeonfbreg.h> 98 1.5.6.2 rpaulo #include <dev/pci/radeonfbvar.h> 99 1.5.6.2 rpaulo 100 1.5.6.2 rpaulo static int radeonfb_match(struct device *, struct cfdata *, void *); 101 1.5.6.2 rpaulo static void radeonfb_attach(struct device *, struct device *, void *); 102 1.5.6.2 rpaulo static int radeonfb_ioctl(void *, void *, unsigned long, caddr_t, int, 103 1.5.6.2 rpaulo struct lwp *); 104 1.5.6.2 rpaulo static paddr_t radeonfb_mmap(void *, void *, off_t, int); 105 1.5.6.2 rpaulo static int radeonfb_scratch_test(struct radeonfb_softc *, int, uint32_t); 106 1.5.6.2 rpaulo static void radeonfb_loadbios(struct radeonfb_softc *, 107 1.5.6.2 rpaulo struct pci_attach_args *); 108 1.5.6.2 rpaulo 109 1.5.6.2 rpaulo static uintmax_t radeonfb_getprop_num(struct radeonfb_softc *, const char *, 110 1.5.6.2 rpaulo uintmax_t); 111 1.5.6.2 rpaulo static int radeonfb_getclocks(struct radeonfb_softc *); 112 1.5.6.2 rpaulo static int radeonfb_gettmds(struct radeonfb_softc *); 113 1.5.6.2 rpaulo static int radeonfb_calc_dividers(struct radeonfb_softc *, uint32_t, 114 1.5.6.2 rpaulo uint32_t *, uint32_t *); 115 1.5.6.2 rpaulo static int radeonfb_getconnectors(struct radeonfb_softc *); 116 1.5.6.2 rpaulo static const struct videomode *radeonfb_modelookup(const char *); 117 1.5.6.2 rpaulo static void radeonfb_init_screen(void *, struct vcons_screen *, int, long *); 118 1.5.6.2 rpaulo static void radeonfb_pllwriteupdate(struct radeonfb_softc *, int); 119 1.5.6.2 rpaulo static void radeonfb_pllwaitatomicread(struct radeonfb_softc *, int); 120 1.5.6.2 rpaulo static void radeonfb_program_vclk(struct radeonfb_softc *, int, int); 121 1.5.6.2 rpaulo static void radeonfb_modeswitch(struct radeonfb_display *); 122 1.5.6.2 rpaulo static void radeonfb_setcrtc(struct radeonfb_display *, int); 123 1.5.6.2 rpaulo static void radeonfb_init_misc(struct radeonfb_softc *); 124 1.5.6.2 rpaulo static void radeonfb_set_fbloc(struct radeonfb_softc *); 125 1.5.6.2 rpaulo static void radeonfb_init_palette(struct radeonfb_softc *, int); 126 1.5.6.2 rpaulo static void radeonfb_r300cg_workaround(struct radeonfb_softc *); 127 1.5.6.2 rpaulo 128 1.5.6.2 rpaulo static int radeonfb_isblank(struct radeonfb_display *); 129 1.5.6.2 rpaulo static void radeonfb_blank(struct radeonfb_display *, int); 130 1.5.6.2 rpaulo static int radeonfb_set_cursor(struct radeonfb_display *, 131 1.5.6.2 rpaulo struct wsdisplay_cursor *); 132 1.5.6.2 rpaulo static int radeonfb_set_curpos(struct radeonfb_display *, 133 1.5.6.2 rpaulo struct wsdisplay_curpos *); 134 1.5.6.2 rpaulo 135 1.5.6.2 rpaulo /* acceleration support */ 136 1.5.6.2 rpaulo static void radeonfb_rectfill(struct radeonfb_display *, int dstx, int dsty, 137 1.5.6.2 rpaulo int width, int height, uint32_t color); 138 1.5.6.2 rpaulo static void radeonfb_bitblt(struct radeonfb_display *, int srcx, int srcy, 139 1.5.6.2 rpaulo int dstx, int dsty, int width, int height, int rop, uint32_t mask); 140 1.5.6.2 rpaulo static void radeonfb_feed_bytes(struct radeonfb_display *, int, uint8_t *); 141 1.5.6.2 rpaulo static void radeonfb_setup_mono(struct radeonfb_display *, int, int, int, 142 1.5.6.2 rpaulo int, uint32_t, uint32_t); 143 1.5.6.2 rpaulo 144 1.5.6.2 rpaulo /* hw cursor support */ 145 1.5.6.2 rpaulo static void radeonfb_cursor_cmap(struct radeonfb_display *); 146 1.5.6.2 rpaulo static void radeonfb_cursor_shape(struct radeonfb_display *); 147 1.5.6.2 rpaulo static void radeonfb_cursor_position(struct radeonfb_display *); 148 1.5.6.2 rpaulo static void radeonfb_cursor_visible(struct radeonfb_display *); 149 1.5.6.2 rpaulo static void radeonfb_cursor_update(struct radeonfb_display *, unsigned); 150 1.5.6.2 rpaulo 151 1.5.6.2 rpaulo static void radeonfb_wait_fifo(struct radeonfb_softc *, int); 152 1.5.6.2 rpaulo static void radeonfb_engine_idle(struct radeonfb_softc *); 153 1.5.6.2 rpaulo static void radeonfb_engine_flush(struct radeonfb_softc *); 154 1.5.6.2 rpaulo static void radeonfb_engine_reset(struct radeonfb_softc *); 155 1.5.6.2 rpaulo static void radeonfb_engine_init(struct radeonfb_display *); 156 1.5.6.2 rpaulo static inline void radeonfb_unclip(struct radeonfb_softc *); 157 1.5.6.2 rpaulo 158 1.5.6.2 rpaulo static void radeonfb_eraserows(void *, int, int, long); 159 1.5.6.2 rpaulo static void radeonfb_erasecols(void *, int, int, int, long); 160 1.5.6.2 rpaulo static void radeonfb_copyrows(void *, int, int, int); 161 1.5.6.2 rpaulo static void radeonfb_copycols(void *, int, int, int, int); 162 1.5.6.2 rpaulo static void radeonfb_cursor(void *, int, int, int); 163 1.5.6.2 rpaulo static void radeonfb_putchar(void *, int, int, unsigned, long); 164 1.5.6.2 rpaulo static int radeonfb_allocattr(void *, int, int, int, long *); 165 1.5.6.2 rpaulo 166 1.5.6.2 rpaulo static struct videomode *radeonfb_best_refresh(struct videomode *, 167 1.5.6.2 rpaulo struct videomode *); 168 1.5.6.2 rpaulo static void radeonfb_pickres(struct radeonfb_display *, uint16_t *, 169 1.5.6.2 rpaulo uint16_t *, int); 170 1.5.6.2 rpaulo static const struct videomode *radeonfb_port_mode(struct radeonfb_port *, 171 1.5.6.2 rpaulo int, int); 172 1.5.6.2 rpaulo 173 1.5.6.2 rpaulo 174 1.5.6.2 rpaulo #define RADEON_DEBUG 175 1.5.6.2 rpaulo #ifdef RADEON_DEBUG 176 1.5.6.2 rpaulo int radeon_debug = 1; 177 1.5.6.2 rpaulo #define DPRINTF(x) \ 178 1.5.6.2 rpaulo if (radeon_debug) printf x 179 1.5.6.2 rpaulo #define PRINTREG(r) DPRINTF((#r " = %08x\n", GET32(sc, r))) 180 1.5.6.2 rpaulo #define PRINTPLL(r) DPRINTF((#r " = %08x\n", GETPLL(sc, r))) 181 1.5.6.2 rpaulo #else 182 1.5.6.2 rpaulo #define DPRINTF(x) 183 1.5.6.2 rpaulo #define PRINTREG(r) 184 1.5.6.2 rpaulo #define PRINTPLL(r) 185 1.5.6.2 rpaulo #endif 186 1.5.6.2 rpaulo 187 1.5.6.2 rpaulo #define ROUNDUP(x,y) (((x) + ((y) - 1)) & ~((y) - 1)) 188 1.5.6.2 rpaulo 189 1.5.6.2 rpaulo #ifndef RADEON_DEFAULT_MODE 190 1.5.6.2 rpaulo /* any reasonably modern display should handle this */ 191 1.5.6.2 rpaulo #define RADEON_DEFAULT_MODE "1024x768x60" 192 1.5.6.2 rpaulo //#define RADEON_DEFAULT_MODE "1280x1024x60" 193 1.5.6.2 rpaulo #endif 194 1.5.6.2 rpaulo 195 1.5.6.2 rpaulo const char *radeonfb_default_mode = RADEON_DEFAULT_MODE; 196 1.5.6.2 rpaulo 197 1.5.6.2 rpaulo static struct { 198 1.5.6.2 rpaulo int size; /* minimum memory size (MB) */ 199 1.5.6.2 rpaulo int maxx; /* maximum x dimension */ 200 1.5.6.2 rpaulo int maxy; /* maximum y dimension */ 201 1.5.6.2 rpaulo int maxbpp; /* maximum bpp */ 202 1.5.6.2 rpaulo int maxdisp; /* maximum logical display count */ 203 1.5.6.2 rpaulo } radeonfb_limits[] = { 204 1.5.6.2 rpaulo { 32, 2048, 1536, 32, 2 }, 205 1.5.6.2 rpaulo { 16, 1600, 1200, 32, 2 }, 206 1.5.6.2 rpaulo { 8, 1600, 1200, 32, 1 }, 207 1.5.6.2 rpaulo { 0, 0, 0, 0 }, 208 1.5.6.2 rpaulo }; 209 1.5.6.2 rpaulo 210 1.5.6.2 rpaulo static struct wsscreen_descr radeonfb_stdscreen = { 211 1.5.6.2 rpaulo "fb", /* name */ 212 1.5.6.2 rpaulo 0, 0, /* ncols, nrows */ 213 1.5.6.2 rpaulo NULL, /* textops */ 214 1.5.6.2 rpaulo 8, 16, /* fontwidth, fontheight */ 215 1.5.6.2 rpaulo WSSCREEN_WSCOLORS, 216 1.5.6.2 rpaulo }; 217 1.5.6.2 rpaulo 218 1.5.6.2 rpaulo struct wsdisplay_accessops radeonfb_accessops = { 219 1.5.6.2 rpaulo radeonfb_ioctl, 220 1.5.6.2 rpaulo radeonfb_mmap, 221 1.5.6.2 rpaulo NULL, /* vcons_alloc_screen */ 222 1.5.6.2 rpaulo NULL, /* vcons_free_screen */ 223 1.5.6.2 rpaulo NULL, /* vcons_show_screen */ 224 1.5.6.2 rpaulo NULL /* load_font */ 225 1.5.6.2 rpaulo }; 226 1.5.6.2 rpaulo 227 1.5.6.2 rpaulo static struct { 228 1.5.6.2 rpaulo uint16_t devid; 229 1.5.6.2 rpaulo uint16_t family; 230 1.5.6.2 rpaulo uint16_t flags; 231 1.5.6.2 rpaulo } radeonfb_devices[] = 232 1.5.6.2 rpaulo { 233 1.5.6.2 rpaulo /* R100 family */ 234 1.5.6.2 rpaulo { PCI_PRODUCT_ATI_RADEON_R100_QD, RADEON_R100, 0 }, 235 1.5.6.2 rpaulo { PCI_PRODUCT_ATI_RADEON_R100_QE, RADEON_R100, 0 }, 236 1.5.6.2 rpaulo { PCI_PRODUCT_ATI_RADEON_R100_QF, RADEON_R100, 0 }, 237 1.5.6.2 rpaulo { PCI_PRODUCT_ATI_RADEON_R100_QG, RADEON_R100, 0 }, 238 1.5.6.2 rpaulo 239 1.5.6.2 rpaulo /* RV100 family */ 240 1.5.6.2 rpaulo { PCI_PRODUCT_ATI_RADEON_RV100_LY, RADEON_RV100, RFB_MOB }, 241 1.5.6.2 rpaulo { PCI_PRODUCT_ATI_RADEON_RV100_LZ, RADEON_RV100, RFB_MOB }, 242 1.5.6.2 rpaulo { PCI_PRODUCT_ATI_RADEON_RV100_QY, RADEON_RV100, 0 }, 243 1.5.6.2 rpaulo { PCI_PRODUCT_ATI_RADEON_RV100_QZ, RADEON_RV100, 0 }, 244 1.5.6.2 rpaulo 245 1.5.6.2 rpaulo /* RS100 family */ 246 1.5.6.2 rpaulo { PCI_PRODUCT_ATI_RADEON_RS100_4136, RADEON_RS100, 0 }, 247 1.5.6.2 rpaulo { PCI_PRODUCT_ATI_RADEON_RS100_4336, RADEON_RS100, RFB_MOB }, 248 1.5.6.2 rpaulo 249 1.5.6.2 rpaulo /* RS200/RS250 family */ 250 1.5.6.2 rpaulo { PCI_PRODUCT_ATI_RADEON_RS200_4337, RADEON_RS200, RFB_MOB }, 251 1.5.6.2 rpaulo { PCI_PRODUCT_ATI_RADEON_RS200_A7, RADEON_RS200, 0 }, 252 1.5.6.2 rpaulo { PCI_PRODUCT_ATI_RADEON_RS250_B7, RADEON_RS200, RFB_MOB }, 253 1.5.6.2 rpaulo { PCI_PRODUCT_ATI_RADEON_RS250_D7, RADEON_RS200, 0 }, 254 1.5.6.2 rpaulo 255 1.5.6.2 rpaulo /* R200 family */ 256 1.5.6.2 rpaulo /* add more R200 products? , 5148 */ 257 1.5.6.2 rpaulo { PCI_PRODUCT_ATI_RADEON_R200_BB, RADEON_R200, 0 }, 258 1.5.6.2 rpaulo { PCI_PRODUCT_ATI_RADEON_R200_BC, RADEON_R200, 0 }, 259 1.5.6.2 rpaulo { PCI_PRODUCT_ATI_RADEON_R200_QH, RADEON_R200, 0 }, 260 1.5.6.2 rpaulo { PCI_PRODUCT_ATI_RADEON_R200_QL, RADEON_R200, 0 }, 261 1.5.6.2 rpaulo { PCI_PRODUCT_ATI_RADEON_R200_QM, RADEON_R200, 0 }, 262 1.5.6.2 rpaulo 263 1.5.6.2 rpaulo /* RV200 family */ 264 1.5.6.2 rpaulo { PCI_PRODUCT_ATI_RADEON_RV200_LW, RADEON_RV200, RFB_MOB }, 265 1.5.6.2 rpaulo { PCI_PRODUCT_ATI_RADEON_RV200_LX, RADEON_RV200, RFB_MOB }, 266 1.5.6.2 rpaulo { PCI_PRODUCT_ATI_RADEON_RV200_QW, RADEON_RV200, 0 }, 267 1.5.6.2 rpaulo { PCI_PRODUCT_ATI_RADEON_RV200_QX, RADEON_RV200, 0 }, 268 1.5.6.2 rpaulo 269 1.5.6.2 rpaulo /* RV250 family */ 270 1.5.6.2 rpaulo { PCI_PRODUCT_ATI_RADEON_RV250_4966, RADEON_RV250, 0 }, 271 1.5.6.2 rpaulo { PCI_PRODUCT_ATI_RADEON_RV250_4967, RADEON_RV250, 0 }, 272 1.5.6.2 rpaulo { PCI_PRODUCT_ATI_RADEON_RV250_4C64, RADEON_RV250, RFB_MOB }, 273 1.5.6.2 rpaulo { PCI_PRODUCT_ATI_RADEON_RV250_4C66, RADEON_RV250, RFB_MOB }, 274 1.5.6.2 rpaulo { PCI_PRODUCT_ATI_RADEON_RV250_4C67, RADEON_RV250, RFB_MOB }, 275 1.5.6.2 rpaulo 276 1.5.6.2 rpaulo /* RS300 family */ 277 1.5.6.2 rpaulo { PCI_PRODUCT_ATI_RADEON_RS300_X5, RADEON_RS300, 0 }, 278 1.5.6.2 rpaulo { PCI_PRODUCT_ATI_RADEON_RS300_X4, RADEON_RS300, 0 }, 279 1.5.6.2 rpaulo { PCI_PRODUCT_ATI_RADEON_RS300_7834, RADEON_RS300, 0 }, 280 1.5.6.2 rpaulo { PCI_PRODUCT_ATI_RADEON_RS300_7835, RADEON_RS300, RFB_MOB }, 281 1.5.6.2 rpaulo 282 1.5.6.2 rpaulo /* RV280 family */ 283 1.5.6.2 rpaulo { PCI_PRODUCT_ATI_RADEON_RV280_5960, RADEON_RV280, 0 }, 284 1.5.6.2 rpaulo { PCI_PRODUCT_ATI_RADEON_RV280_5961, RADEON_RV280, 0 }, 285 1.5.6.2 rpaulo { PCI_PRODUCT_ATI_RADEON_RV280_5962, RADEON_RV280, 0 }, 286 1.5.6.2 rpaulo { PCI_PRODUCT_ATI_RADEON_RV280_5963, RADEON_RV280, 0 }, 287 1.5.6.2 rpaulo { PCI_PRODUCT_ATI_RADEON_RV280_5964, RADEON_RV280, 0 }, 288 1.5.6.2 rpaulo { PCI_PRODUCT_ATI_RADEON_RV280_5C61, RADEON_RV280, RFB_MOB }, 289 1.5.6.2 rpaulo { PCI_PRODUCT_ATI_RADEON_RV280_5C63, RADEON_RV280, RFB_MOB }, 290 1.5.6.2 rpaulo 291 1.5.6.2 rpaulo /* R300 family */ 292 1.5.6.2 rpaulo { PCI_PRODUCT_ATI_RADEON_R300_AD, RADEON_R300, 0 }, 293 1.5.6.2 rpaulo { PCI_PRODUCT_ATI_RADEON_R300_AE, RADEON_R300, 0 }, 294 1.5.6.2 rpaulo { PCI_PRODUCT_ATI_RADEON_R300_AF, RADEON_R300, 0 }, 295 1.5.6.2 rpaulo { PCI_PRODUCT_ATI_RADEON_R300_AG, RADEON_R300, 0 }, 296 1.5.6.2 rpaulo { PCI_PRODUCT_ATI_RADEON_R300_ND, RADEON_R300, 0 }, 297 1.5.6.2 rpaulo { PCI_PRODUCT_ATI_RADEON_R300_NE, RADEON_R300, 0 }, 298 1.5.6.2 rpaulo { PCI_PRODUCT_ATI_RADEON_R300_NF, RADEON_R300, 0 }, 299 1.5.6.2 rpaulo { PCI_PRODUCT_ATI_RADEON_R300_NG, RADEON_R300, 0 }, 300 1.5.6.2 rpaulo 301 1.5.6.2 rpaulo /* RV350/RV360 family */ 302 1.5.6.2 rpaulo { PCI_PRODUCT_ATI_RADEON_RV350_AP, RADEON_RV350, 0 }, 303 1.5.6.2 rpaulo { PCI_PRODUCT_ATI_RADEON_RV350_AQ, RADEON_RV350, 0 }, 304 1.5.6.2 rpaulo { PCI_PRODUCT_ATI_RADEON_RV360_AR, RADEON_RV350, 0 }, 305 1.5.6.2 rpaulo { PCI_PRODUCT_ATI_RADEON_RV350_AS, RADEON_RV350, 0 }, 306 1.5.6.2 rpaulo { PCI_PRODUCT_ATI_RADEON_RV350_AT, RADEON_RV350, 0 }, 307 1.5.6.2 rpaulo { PCI_PRODUCT_ATI_RADEON_RV350_AV, RADEON_RV350, 0 }, 308 1.5.6.2 rpaulo { PCI_PRODUCT_ATI_RADEON_RV350_NP, RADEON_RV350, RFB_MOB }, 309 1.5.6.2 rpaulo { PCI_PRODUCT_ATI_RADEON_RV350_NQ, RADEON_RV350, RFB_MOB }, 310 1.5.6.2 rpaulo { PCI_PRODUCT_ATI_RADEON_RV350_NR, RADEON_RV350, RFB_MOB }, 311 1.5.6.2 rpaulo { PCI_PRODUCT_ATI_RADEON_RV350_NS, RADEON_RV350, RFB_MOB }, 312 1.5.6.2 rpaulo { PCI_PRODUCT_ATI_RADEON_RV350_NT, RADEON_RV350, RFB_MOB }, 313 1.5.6.2 rpaulo { PCI_PRODUCT_ATI_RADEON_RV350_NV, RADEON_RV350, RFB_MOB }, 314 1.5.6.2 rpaulo 315 1.5.6.2 rpaulo /* R350/R360 family */ 316 1.5.6.2 rpaulo { PCI_PRODUCT_ATI_RADEON_R350_AH, RADEON_R350, 0 }, 317 1.5.6.2 rpaulo { PCI_PRODUCT_ATI_RADEON_R350_AI, RADEON_R350, 0 }, 318 1.5.6.2 rpaulo { PCI_PRODUCT_ATI_RADEON_R350_AJ, RADEON_R350, 0 }, 319 1.5.6.2 rpaulo { PCI_PRODUCT_ATI_RADEON_R350_AK, RADEON_R350, 0 }, 320 1.5.6.2 rpaulo { PCI_PRODUCT_ATI_RADEON_R350_NH, RADEON_R350, 0 }, 321 1.5.6.2 rpaulo { PCI_PRODUCT_ATI_RADEON_R350_NI, RADEON_R350, 0 }, 322 1.5.6.2 rpaulo { PCI_PRODUCT_ATI_RADEON_R350_NK, RADEON_R350, 0 }, 323 1.5.6.2 rpaulo { PCI_PRODUCT_ATI_RADEON_R360_NJ, RADEON_R350, 0 }, 324 1.5.6.2 rpaulo 325 1.5.6.2 rpaulo /* RV380/RV370 family */ 326 1.5.6.2 rpaulo { PCI_PRODUCT_ATI_RADEON_RV380_3150, RADEON_RV380, RFB_MOB }, 327 1.5.6.2 rpaulo { PCI_PRODUCT_ATI_RADEON_RV380_3154, RADEON_RV380, RFB_MOB }, 328 1.5.6.2 rpaulo { PCI_PRODUCT_ATI_RADEON_RV380_3E50, RADEON_RV380, 0 }, 329 1.5.6.2 rpaulo { PCI_PRODUCT_ATI_RADEON_RV380_3E54, RADEON_RV380, 0 }, 330 1.5.6.2 rpaulo { PCI_PRODUCT_ATI_RADEON_RV370_5460, RADEON_RV380, RFB_MOB }, 331 1.5.6.2 rpaulo { PCI_PRODUCT_ATI_RADEON_RV370_5464, RADEON_RV380, RFB_MOB }, 332 1.5.6.2 rpaulo { PCI_PRODUCT_ATI_RADEON_RV370_5B60, RADEON_RV380, 0 }, 333 1.5.6.2 rpaulo { PCI_PRODUCT_ATI_RADEON_RV370_5B64, RADEON_RV380, 0 }, 334 1.5.6.2 rpaulo { PCI_PRODUCT_ATI_RADEON_RV370_5B65, RADEON_RV380, 0 }, 335 1.5.6.2 rpaulo 336 1.5.6.2 rpaulo /* R420/R423 family */ 337 1.5.6.2 rpaulo { PCI_PRODUCT_ATI_RADEON_R420_JH, RADEON_R420, 0 }, 338 1.5.6.2 rpaulo { PCI_PRODUCT_ATI_RADEON_R420_JI, RADEON_R420, 0 }, 339 1.5.6.2 rpaulo { PCI_PRODUCT_ATI_RADEON_R420_JJ, RADEON_R420, 0 }, 340 1.5.6.2 rpaulo { PCI_PRODUCT_ATI_RADEON_R420_JK, RADEON_R420, 0 }, 341 1.5.6.2 rpaulo { PCI_PRODUCT_ATI_RADEON_R420_JL, RADEON_R420, 0 }, 342 1.5.6.2 rpaulo { PCI_PRODUCT_ATI_RADEON_R420_JM, RADEON_R420, 0 }, 343 1.5.6.2 rpaulo { PCI_PRODUCT_ATI_RADEON_R420_JN, RADEON_R420, RFB_MOB }, 344 1.5.6.2 rpaulo { PCI_PRODUCT_ATI_RADEON_R420_JP, RADEON_R420, 0 }, 345 1.5.6.2 rpaulo { PCI_PRODUCT_ATI_RADEON_R423_UH, RADEON_R420, 0 }, 346 1.5.6.2 rpaulo { PCI_PRODUCT_ATI_RADEON_R423_UI, RADEON_R420, 0 }, 347 1.5.6.2 rpaulo { PCI_PRODUCT_ATI_RADEON_R423_UJ, RADEON_R420, 0 }, 348 1.5.6.2 rpaulo { PCI_PRODUCT_ATI_RADEON_R423_UK, RADEON_R420, 0 }, 349 1.5.6.2 rpaulo { PCI_PRODUCT_ATI_RADEON_R423_UQ, RADEON_R420, 0 }, 350 1.5.6.2 rpaulo { PCI_PRODUCT_ATI_RADEON_R423_UR, RADEON_R420, 0 }, 351 1.5.6.2 rpaulo { PCI_PRODUCT_ATI_RADEON_R423_UT, RADEON_R420, 0 }, 352 1.5.6.2 rpaulo { PCI_PRODUCT_ATI_RADEON_R423_5D57, RADEON_R420, 0 }, 353 1.5.6.2 rpaulo 354 1.5.6.2 rpaulo { 0, 0, 0 } 355 1.5.6.2 rpaulo }; 356 1.5.6.2 rpaulo 357 1.5.6.2 rpaulo static struct { 358 1.5.6.2 rpaulo int divider; 359 1.5.6.2 rpaulo int mask; 360 1.5.6.2 rpaulo } radeonfb_dividers[] = { 361 1.5.6.2 rpaulo { 1, 0 }, 362 1.5.6.2 rpaulo { 2, 1 }, 363 1.5.6.2 rpaulo { 3, 4 }, 364 1.5.6.2 rpaulo { 4, 2 }, 365 1.5.6.2 rpaulo { 6, 6 }, 366 1.5.6.2 rpaulo { 8, 3 }, 367 1.5.6.2 rpaulo { 12, 7 }, 368 1.5.6.2 rpaulo { 0, 0 } 369 1.5.6.2 rpaulo }; 370 1.5.6.2 rpaulo 371 1.5.6.2 rpaulo /* 372 1.5.6.2 rpaulo * This table taken from X11. 373 1.5.6.2 rpaulo */ 374 1.5.6.2 rpaulo static const struct { 375 1.5.6.2 rpaulo int family; 376 1.5.6.2 rpaulo struct radeon_tmds_pll plls[4]; 377 1.5.6.2 rpaulo } radeonfb_tmds_pll[] = { 378 1.5.6.2 rpaulo { RADEON_R100, {{12000, 0xa1b}, {-1, 0xa3f}}}, 379 1.5.6.2 rpaulo { RADEON_RV100, {{12000, 0xa1b}, {-1, 0xa3f}}}, 380 1.5.6.2 rpaulo { RADEON_RS100, {{0, 0}}}, 381 1.5.6.2 rpaulo { RADEON_RV200, {{15000, 0xa1b}, {-1, 0xa3f}}}, 382 1.5.6.2 rpaulo { RADEON_RS200, {{15000, 0xa1b}, {-1, 0xa3f}}}, 383 1.5.6.2 rpaulo { RADEON_R200, {{15000, 0xa1b}, {-1, 0xa3f}}}, 384 1.5.6.2 rpaulo { RADEON_RV250, {{15500, 0x81b}, {-1, 0x83f}}}, 385 1.5.6.2 rpaulo { RADEON_RS300, {{0, 0}}}, 386 1.5.6.2 rpaulo { RADEON_RV280, {{13000, 0x400f4}, {15000, 0x400f7}}}, 387 1.5.6.2 rpaulo { RADEON_R300, {{-1, 0xb01cb}}}, 388 1.5.6.2 rpaulo { RADEON_R350, {{-1, 0xb01cb}}}, 389 1.5.6.2 rpaulo { RADEON_RV350, {{15000, 0xb0155}, {-1, 0xb01cb}}}, 390 1.5.6.2 rpaulo { RADEON_RV380, {{15000, 0xb0155}, {-1, 0xb01cb}}}, 391 1.5.6.2 rpaulo { RADEON_R420, {{-1, 0xb01cb}}}, 392 1.5.6.2 rpaulo }; 393 1.5.6.2 rpaulo 394 1.5.6.2 rpaulo 395 1.5.6.2 rpaulo CFATTACH_DECL(radeonfb, sizeof (struct radeonfb_softc), 396 1.5.6.2 rpaulo radeonfb_match, radeonfb_attach, NULL, NULL); 397 1.5.6.2 rpaulo 398 1.5.6.2 rpaulo static int 399 1.5.6.2 rpaulo radeonfb_match(struct device *parent, struct cfdata *match, void *aux) 400 1.5.6.2 rpaulo { 401 1.5.6.2 rpaulo struct pci_attach_args *pa = aux; 402 1.5.6.2 rpaulo int i; 403 1.5.6.2 rpaulo 404 1.5.6.2 rpaulo if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_ATI) 405 1.5.6.2 rpaulo return 0; 406 1.5.6.2 rpaulo 407 1.5.6.2 rpaulo for (i = 0; radeonfb_devices[i].devid; i++) { 408 1.5.6.2 rpaulo if (PCI_PRODUCT(pa->pa_id) == radeonfb_devices[i].devid) 409 1.5.6.2 rpaulo return 100; /* high to defeat VGA/VESA */ 410 1.5.6.2 rpaulo } 411 1.5.6.2 rpaulo 412 1.5.6.2 rpaulo return 0; 413 1.5.6.2 rpaulo } 414 1.5.6.2 rpaulo 415 1.5.6.2 rpaulo static void 416 1.5.6.2 rpaulo radeonfb_attach(struct device *parent, struct device *dev, void *aux) 417 1.5.6.2 rpaulo { 418 1.5.6.2 rpaulo struct radeonfb_softc *sc = (struct radeonfb_softc *)dev; 419 1.5.6.2 rpaulo struct pci_attach_args *pa = aux; 420 1.5.6.2 rpaulo bus_size_t bsz; 421 1.5.6.2 rpaulo pcireg_t screg; 422 1.5.6.2 rpaulo int i, j; 423 1.5.6.2 rpaulo uint32_t v; 424 1.5.6.2 rpaulo 425 1.5.6.2 rpaulo sc->sc_id = pa->pa_id; 426 1.5.6.2 rpaulo for (i = 0; radeonfb_devices[i].devid; i++) { 427 1.5.6.2 rpaulo if (PCI_PRODUCT(sc->sc_id) == radeonfb_devices[i].devid) 428 1.5.6.2 rpaulo break; 429 1.5.6.2 rpaulo } 430 1.5.6.2 rpaulo 431 1.5.6.2 rpaulo pci_devinfo(sc->sc_id, pa->pa_class, 0, sc->sc_devinfo, 432 1.5.6.2 rpaulo sizeof(sc->sc_devinfo)); 433 1.5.6.2 rpaulo 434 1.5.6.2 rpaulo aprint_naive("\n"); 435 1.5.6.2 rpaulo aprint_normal(": %s\n", sc->sc_devinfo); 436 1.5.6.2 rpaulo 437 1.5.6.2 rpaulo KASSERT(radeonfb_devices[i].devid != 0); 438 1.5.6.2 rpaulo sc->sc_pt = pa->pa_tag; 439 1.5.6.2 rpaulo sc->sc_pc = pa->pa_pc; 440 1.5.6.2 rpaulo sc->sc_family = radeonfb_devices[i].family; 441 1.5.6.2 rpaulo sc->sc_flags = radeonfb_devices[i].flags; 442 1.5.6.2 rpaulo 443 1.5.6.2 rpaulo /* enable memory and IO access */ 444 1.5.6.2 rpaulo screg = pci_conf_read(sc->sc_pc, sc->sc_pt, PCI_COMMAND_STATUS_REG); 445 1.5.6.2 rpaulo screg |= PCI_FLAGS_IO_ENABLED | PCI_FLAGS_MEM_ENABLED; 446 1.5.6.2 rpaulo pci_conf_write(sc->sc_pc, sc->sc_pt, PCI_COMMAND_STATUS_REG, screg); 447 1.5.6.2 rpaulo 448 1.5.6.2 rpaulo /* 449 1.5.6.2 rpaulo * Some flags are general to entire chip families, and rather 450 1.5.6.2 rpaulo * than clutter up the table with them, we go ahead and set 451 1.5.6.2 rpaulo * them here. 452 1.5.6.2 rpaulo */ 453 1.5.6.2 rpaulo switch (sc->sc_family) { 454 1.5.6.2 rpaulo case RADEON_RS100: 455 1.5.6.2 rpaulo case RADEON_RS200: 456 1.5.6.2 rpaulo sc->sc_flags |= RFB_IGP | RFB_RV100; 457 1.5.6.2 rpaulo break; 458 1.5.6.2 rpaulo 459 1.5.6.2 rpaulo case RADEON_RV100: 460 1.5.6.2 rpaulo case RADEON_RV200: 461 1.5.6.2 rpaulo case RADEON_RV250: 462 1.5.6.2 rpaulo case RADEON_RV280: 463 1.5.6.2 rpaulo sc->sc_flags |= RFB_RV100; 464 1.5.6.2 rpaulo break; 465 1.5.6.2 rpaulo 466 1.5.6.2 rpaulo case RADEON_RS300: 467 1.5.6.2 rpaulo sc->sc_flags |= RFB_SDAC | RFB_IGP | RFB_RV100; 468 1.5.6.2 rpaulo break; 469 1.5.6.2 rpaulo 470 1.5.6.2 rpaulo case RADEON_R300: 471 1.5.6.2 rpaulo case RADEON_RV350: 472 1.5.6.2 rpaulo case RADEON_R350: 473 1.5.6.2 rpaulo case RADEON_RV380: 474 1.5.6.2 rpaulo case RADEON_R420: 475 1.5.6.2 rpaulo /* newer chips */ 476 1.5.6.2 rpaulo sc->sc_flags |= RFB_R300; 477 1.5.6.2 rpaulo break; 478 1.5.6.2 rpaulo 479 1.5.6.2 rpaulo case RADEON_R100: 480 1.5.6.2 rpaulo sc->sc_flags |= RFB_NCRTC2; 481 1.5.6.2 rpaulo break; 482 1.5.6.2 rpaulo } 483 1.5.6.2 rpaulo 484 1.5.6.2 rpaulo /* 485 1.5.6.2 rpaulo * XXX: to support true multihead, this must change. 486 1.5.6.2 rpaulo */ 487 1.5.6.2 rpaulo sc->sc_ndisplays = 1; 488 1.5.6.2 rpaulo 489 1.5.6.2 rpaulo /* XXX: */ 490 1.5.6.2 rpaulo if (!HAS_CRTC2(sc)) { 491 1.5.6.2 rpaulo sc->sc_ndisplays = 1; 492 1.5.6.2 rpaulo } 493 1.5.6.2 rpaulo 494 1.5.6.2 rpaulo if (pci_mapreg_map(pa, RADEON_MAPREG_MMIO, PCI_MAPREG_TYPE_MEM, 0, 495 1.5.6.2 rpaulo &sc->sc_regt, &sc->sc_regh, &sc->sc_regaddr, 496 1.5.6.2 rpaulo &sc->sc_regsz) != 0) { 497 1.5.6.2 rpaulo aprint_error("%s: unable to map registers!\n", XNAME(sc)); 498 1.5.6.2 rpaulo goto error; 499 1.5.6.2 rpaulo } 500 1.5.6.2 rpaulo 501 1.5.6.2 rpaulo if (pci_mapreg_map(pa, RADEON_MAPREG_IO, PCI_MAPREG_TYPE_IO, 0, 502 1.5.6.2 rpaulo &sc->sc_iot, &sc->sc_ioh, &sc->sc_ioaddr, 503 1.5.6.2 rpaulo &sc->sc_iosz) != 0) { 504 1.5.6.2 rpaulo aprint_error("%s: unable to map IO registers!\n", XNAME(sc)); 505 1.5.6.2 rpaulo } 506 1.5.6.2 rpaulo 507 1.5.6.2 rpaulo /* scratch register test... */ 508 1.5.6.2 rpaulo if (radeonfb_scratch_test(sc, RADEON_BIOS_0_SCRATCH, 0x55555555) || 509 1.5.6.2 rpaulo radeonfb_scratch_test(sc, RADEON_BIOS_0_SCRATCH, 0xaaaaaaaa)) { 510 1.5.6.2 rpaulo aprint_error("%s: scratch register test failed!\n", XNAME(sc)); 511 1.5.6.2 rpaulo goto error; 512 1.5.6.2 rpaulo } 513 1.5.6.2 rpaulo 514 1.5.6.2 rpaulo PRINTREG(RADEON_BIOS_4_SCRATCH); 515 1.5.6.2 rpaulo PRINTREG(RADEON_FP_GEN_CNTL); 516 1.5.6.2 rpaulo PRINTREG(RADEON_FP2_GEN_CNTL); 517 1.5.6.2 rpaulo PRINTREG(RADEON_TMDS_CNTL); 518 1.5.6.2 rpaulo PRINTREG(RADEON_TMDS_TRANSMITTER_CNTL); 519 1.5.6.2 rpaulo PRINTREG(RADEON_TMDS_PLL_CNTL); 520 1.5.6.2 rpaulo PRINTREG(RADEON_LVDS_GEN_CNTL); 521 1.5.6.2 rpaulo PRINTREG(RADEON_FP_HORZ_STRETCH); 522 1.5.6.2 rpaulo PRINTREG(RADEON_FP_VERT_STRETCH); 523 1.5.6.2 rpaulo 524 1.5.6.2 rpaulo /* XXX: RV100 specific */ 525 1.5.6.2 rpaulo PUT32(sc, RADEON_TMDS_PLL_CNTL, 0xa27); 526 1.5.6.2 rpaulo 527 1.5.6.2 rpaulo PATCH32(sc, RADEON_TMDS_TRANSMITTER_CNTL, 528 1.5.6.2 rpaulo RADEON_TMDS_TRANSMITTER_PLLEN, 529 1.5.6.2 rpaulo RADEON_TMDS_TRANSMITTER_PLLEN | RADEON_TMDS_TRANSMITTER_PLLRST); 530 1.5.6.2 rpaulo 531 1.5.6.2 rpaulo radeonfb_i2c_init(sc); 532 1.5.6.2 rpaulo 533 1.5.6.2 rpaulo radeonfb_loadbios(sc, pa); 534 1.5.6.2 rpaulo 535 1.5.6.2 rpaulo #ifdef RADEON_BIOS_INIT 536 1.5.6.2 rpaulo if (radeonfb_bios_init(sc)) { 537 1.5.6.2 rpaulo aprint_error("%s: BIOS inititialization failed\n", XNAME(sc)); 538 1.5.6.2 rpaulo goto error; 539 1.5.6.2 rpaulo } 540 1.5.6.2 rpaulo #endif 541 1.5.6.2 rpaulo 542 1.5.6.2 rpaulo if (radeonfb_getclocks(sc)) { 543 1.5.6.2 rpaulo aprint_error("%s: Unable to get reference clocks from BIOS\n", 544 1.5.6.2 rpaulo XNAME(sc)); 545 1.5.6.2 rpaulo goto error; 546 1.5.6.2 rpaulo } 547 1.5.6.2 rpaulo 548 1.5.6.2 rpaulo if (radeonfb_gettmds(sc)) { 549 1.5.6.2 rpaulo aprint_error("%s: Unable to identify TMDS PLL settings\n", 550 1.5.6.2 rpaulo XNAME(sc)); 551 1.5.6.2 rpaulo goto error; 552 1.5.6.2 rpaulo } 553 1.5.6.2 rpaulo 554 1.5.6.2 rpaulo aprint_verbose("%s: refclk = %d.%03d MHz, refdiv = %d " 555 1.5.6.2 rpaulo "minpll = %d, maxpll = %d\n", XNAME(sc), 556 1.5.6.2 rpaulo (int)sc->sc_refclk / 1000, (int)sc->sc_refclk % 1000, 557 1.5.6.2 rpaulo (int)sc->sc_refdiv, (int)sc->sc_minpll, (int)sc->sc_maxpll); 558 1.5.6.2 rpaulo 559 1.5.6.2 rpaulo radeonfb_getconnectors(sc); 560 1.5.6.2 rpaulo 561 1.5.6.2 rpaulo radeonfb_set_fbloc(sc); 562 1.5.6.2 rpaulo 563 1.5.6.2 rpaulo for (i = 0; radeonfb_limits[i].size; i++) { 564 1.5.6.2 rpaulo if (sc->sc_memsz >= radeonfb_limits[i].size) { 565 1.5.6.2 rpaulo sc->sc_maxx = radeonfb_limits[i].maxx; 566 1.5.6.2 rpaulo sc->sc_maxy = radeonfb_limits[i].maxy; 567 1.5.6.2 rpaulo sc->sc_maxbpp = radeonfb_limits[i].maxbpp; 568 1.5.6.2 rpaulo /* framebuffer offset, start at a 4K page */ 569 1.5.6.2 rpaulo sc->sc_fboffset = sc->sc_memsz / 570 1.5.6.2 rpaulo radeonfb_limits[i].maxdisp; 571 1.5.6.2 rpaulo /* 572 1.5.6.2 rpaulo * we use the fbsize to figure out where we can store 573 1.5.6.2 rpaulo * things like cursor data. 574 1.5.6.2 rpaulo */ 575 1.5.6.2 rpaulo sc->sc_fbsize = 576 1.5.6.2 rpaulo ROUNDUP(ROUNDUP(sc->sc_maxx * sc->sc_maxbpp / 8 , 577 1.5.6.2 rpaulo RADEON_STRIDEALIGN) * sc->sc_maxy, 578 1.5.6.2 rpaulo 4096); 579 1.5.6.2 rpaulo break; 580 1.5.6.2 rpaulo } 581 1.5.6.2 rpaulo } 582 1.5.6.2 rpaulo 583 1.5.6.2 rpaulo 584 1.5.6.2 rpaulo radeonfb_init_misc(sc); 585 1.5.6.2 rpaulo radeonfb_init_palette(sc, 0); 586 1.5.6.2 rpaulo if (HAS_CRTC2(sc)) 587 1.5.6.2 rpaulo radeonfb_init_palette(sc, 1); 588 1.5.6.2 rpaulo 589 1.5.6.2 rpaulo /* program the DAC wirings */ 590 1.5.6.2 rpaulo for (i = 0; i < (HAS_CRTC2(sc) ? 2 : 1); i++) { 591 1.5.6.2 rpaulo switch (sc->sc_ports[i].rp_dac_type) { 592 1.5.6.2 rpaulo case RADEON_DAC_PRIMARY: 593 1.5.6.2 rpaulo PATCH32(sc, RADEON_DAC_CNTL2, 594 1.5.6.2 rpaulo i ? RADEON_DAC2_DAC_CLK_SEL : 0, 595 1.5.6.2 rpaulo ~RADEON_DAC2_DAC_CLK_SEL); 596 1.5.6.2 rpaulo break; 597 1.5.6.2 rpaulo case RADEON_DAC_TVDAC: 598 1.5.6.2 rpaulo /* we always use the TVDAC to drive a secondary analog 599 1.5.6.2 rpaulo * CRT for now. if we ever support TV-out this will 600 1.5.6.2 rpaulo * have to change. 601 1.5.6.2 rpaulo */ 602 1.5.6.2 rpaulo SET32(sc, RADEON_DAC_CNTL2, 603 1.5.6.2 rpaulo RADEON_DAC2_DAC2_CLK_SEL); 604 1.5.6.2 rpaulo PATCH32(sc, RADEON_DISP_HW_DEBUG, 605 1.5.6.2 rpaulo i ? 0 : RADEON_CRT2_DISP1_SEL, 606 1.5.6.2 rpaulo ~RADEON_CRT2_DISP1_SEL); 607 1.5.6.2 rpaulo break; 608 1.5.6.2 rpaulo } 609 1.5.6.2 rpaulo } 610 1.5.6.2 rpaulo PRINTREG(RADEON_DAC_CNTL2); 611 1.5.6.2 rpaulo PRINTREG(RADEON_DISP_HW_DEBUG); 612 1.5.6.2 rpaulo 613 1.5.6.2 rpaulo /* other DAC programming */ 614 1.5.6.2 rpaulo v = GET32(sc, RADEON_DAC_CNTL); 615 1.5.6.2 rpaulo v &= (RADEON_DAC_RANGE_CNTL_MASK | RADEON_DAC_BLANKING); 616 1.5.6.2 rpaulo v |= RADEON_DAC_MASK_ALL | RADEON_DAC_8BIT_EN; 617 1.5.6.2 rpaulo PUT32(sc, RADEON_DAC_CNTL, v); 618 1.5.6.2 rpaulo PRINTREG(RADEON_DAC_CNTL); 619 1.5.6.2 rpaulo 620 1.5.6.2 rpaulo /* XXX: this may need more investigation */ 621 1.5.6.2 rpaulo PUT32(sc, RADEON_TV_DAC_CNTL, 0x00280203); 622 1.5.6.2 rpaulo PRINTREG(RADEON_TV_DAC_CNTL); 623 1.5.6.2 rpaulo 624 1.5.6.2 rpaulo /* enable TMDS */ 625 1.5.6.2 rpaulo SET32(sc, RADEON_FP_GEN_CNTL, 626 1.5.6.2 rpaulo RADEON_FP_TMDS_EN | 627 1.5.6.2 rpaulo RADEON_FP_CRTC_DONT_SHADOW_VPAR | 628 1.5.6.2 rpaulo RADEON_FP_CRTC_DONT_SHADOW_HEND); 629 1.5.6.2 rpaulo CLR32(sc, RADEON_FP_GEN_CNTL, RADEON_FP_SEL_CRTC2); 630 1.5.6.2 rpaulo if (HAS_CRTC2(sc)) 631 1.5.6.2 rpaulo SET32(sc, RADEON_FP2_GEN_CNTL, RADEON_FP2_SRC_SEL_CRTC2); 632 1.5.6.2 rpaulo 633 1.5.6.2 rpaulo /* 634 1.5.6.2 rpaulo * we use bus_space_map instead of pci_mapreg, because we don't 635 1.5.6.2 rpaulo * need the full aperature space. no point in wasting virtual 636 1.5.6.2 rpaulo * address space we don't intend to use, right? 637 1.5.6.2 rpaulo */ 638 1.5.6.2 rpaulo if ((sc->sc_memsz < (4096 * 1024)) || 639 1.5.6.2 rpaulo (pci_mapreg_info(sc->sc_pc, sc->sc_pt, RADEON_MAPREG_VRAM, 640 1.5.6.2 rpaulo PCI_MAPREG_TYPE_MEM, &sc->sc_memaddr, &bsz, NULL) != 0) || 641 1.5.6.2 rpaulo (bsz < sc->sc_memsz)) { 642 1.5.6.2 rpaulo sc->sc_memsz = 0; 643 1.5.6.2 rpaulo aprint_error("%s: Bad frame buffer configuration\n", 644 1.5.6.2 rpaulo XNAME(sc)); 645 1.5.6.2 rpaulo goto error; 646 1.5.6.2 rpaulo } 647 1.5.6.2 rpaulo 648 1.5.6.2 rpaulo /* 64 MB should be enough -- more just wastes map entries */ 649 1.5.6.2 rpaulo if (sc->sc_memsz > (64 << 20)) 650 1.5.6.2 rpaulo sc->sc_memsz = (64 << 20); 651 1.5.6.2 rpaulo 652 1.5.6.2 rpaulo sc->sc_memt = pa->pa_memt; 653 1.5.6.2 rpaulo if (bus_space_map(sc->sc_memt, sc->sc_memaddr, sc->sc_memsz, 654 1.5.6.2 rpaulo BUS_SPACE_MAP_LINEAR, &sc->sc_memh) != 0) { 655 1.5.6.2 rpaulo sc->sc_memsz = 0; 656 1.5.6.2 rpaulo aprint_error("%s: Unable to map frame buffer\n", XNAME(sc)); 657 1.5.6.2 rpaulo goto error; 658 1.5.6.2 rpaulo } 659 1.5.6.2 rpaulo 660 1.5.6.2 rpaulo aprint_normal("%s: %d MB aperture at 0x%08x, " 661 1.5.6.2 rpaulo "%d KB registers at 0x%08x\n", XNAME(sc), 662 1.5.6.2 rpaulo (int)sc->sc_memsz >> 20, (unsigned)sc->sc_memaddr, 663 1.5.6.2 rpaulo (int)sc->sc_regsz >> 10, (unsigned)sc->sc_regaddr); 664 1.5.6.2 rpaulo 665 1.5.6.2 rpaulo #if 0 666 1.5.6.2 rpaulo /* setup default video mode from devprop (allows PROM override) */ 667 1.5.6.2 rpaulo sc->sc_defaultmode = radeonfb_default_mode; 668 1.5.6.2 rpaulo ps = prop_dictionary_get(device_properties(&sc->sc_dev), 669 1.5.6.2 rpaulo "videomode"); 670 1.5.6.2 rpaulo if (ps != NULL) { 671 1.5.6.2 rpaulo sc->sc_modebuf = prop_string_cstring(ps); 672 1.5.6.2 rpaulo if (sc->sc_modebuf) 673 1.5.6.2 rpaulo sc->sc_defaultmode = sc->sc_modebuf; 674 1.5.6.2 rpaulo } 675 1.5.6.2 rpaulo #endif 676 1.5.6.2 rpaulo 677 1.5.6.2 rpaulo /* initialize some basic display parameters */ 678 1.5.6.2 rpaulo for (i = 0; i < sc->sc_ndisplays; i++) { 679 1.5.6.2 rpaulo struct radeonfb_display *dp = &sc->sc_displays[i]; 680 1.5.6.2 rpaulo struct rasops_info *ri; 681 1.5.6.2 rpaulo long defattr; 682 1.5.6.2 rpaulo struct wsemuldisplaydev_attach_args aa; 683 1.5.6.2 rpaulo 684 1.5.6.2 rpaulo /* 685 1.5.6.2 rpaulo * Figure out how many "displays" (desktops) we are going to 686 1.5.6.2 rpaulo * support. If more than one, then each CRTC gets its own 687 1.5.6.2 rpaulo * programming. 688 1.5.6.2 rpaulo * 689 1.5.6.2 rpaulo * XXX: this code needs to change to support mergedfb. 690 1.5.6.2 rpaulo * XXX: would be nice to allow this to be overridden 691 1.5.6.2 rpaulo */ 692 1.5.6.2 rpaulo if (HAS_CRTC2(sc) && (sc->sc_ndisplays == 1)) { 693 1.5.6.2 rpaulo DPRINTF(("dual crtcs!\n")); 694 1.5.6.2 rpaulo dp->rd_ncrtcs = 2; 695 1.5.6.2 rpaulo dp->rd_crtcs[0].rc_number = 0; 696 1.5.6.2 rpaulo dp->rd_crtcs[1].rc_number = 1; 697 1.5.6.2 rpaulo } else { 698 1.5.6.2 rpaulo dp->rd_ncrtcs = 1; 699 1.5.6.2 rpaulo dp->rd_crtcs[0].rc_number = i; 700 1.5.6.2 rpaulo } 701 1.5.6.2 rpaulo 702 1.5.6.2 rpaulo /* set up port pointer */ 703 1.5.6.2 rpaulo for (j = 0; j < dp->rd_ncrtcs; j++) { 704 1.5.6.2 rpaulo dp->rd_crtcs[j].rc_port = 705 1.5.6.2 rpaulo &sc->sc_ports[dp->rd_crtcs[j].rc_number]; 706 1.5.6.2 rpaulo } 707 1.5.6.2 rpaulo 708 1.5.6.2 rpaulo dp->rd_softc = sc; 709 1.5.6.2 rpaulo dp->rd_wsmode = WSDISPLAYIO_MODE_EMUL; 710 1.5.6.2 rpaulo dp->rd_bg = WS_DEFAULT_BG; 711 1.5.6.2 rpaulo #if 0 712 1.5.6.2 rpaulo dp->rd_bpp = sc->sc_maxbpp; /* XXX: for now */ 713 1.5.6.2 rpaulo #else 714 1.5.6.2 rpaulo dp->rd_bpp = RADEONFB_DEFAULT_DEPTH; /* XXX */ 715 1.5.6.2 rpaulo #endif 716 1.5.6.2 rpaulo /* for text mode, we pick a resolution that won't 717 1.5.6.2 rpaulo * require panning */ 718 1.5.6.2 rpaulo radeonfb_pickres(dp, &dp->rd_virtx, &dp->rd_virty, 0); 719 1.5.6.2 rpaulo 720 1.5.6.2 rpaulo aprint_normal("%s: display %d: " 721 1.5.6.2 rpaulo "virtual resolution %dx%d at %d bpp\n", 722 1.5.6.2 rpaulo XNAME(sc), i, dp->rd_virtx, dp->rd_virty, dp->rd_bpp); 723 1.5.6.2 rpaulo 724 1.5.6.2 rpaulo /* now select the *video mode* that we will use */ 725 1.5.6.2 rpaulo for (j = 0; j < dp->rd_ncrtcs; j++) { 726 1.5.6.2 rpaulo const struct videomode *vmp; 727 1.5.6.2 rpaulo vmp = radeonfb_port_mode(dp->rd_crtcs[j].rc_port, 728 1.5.6.2 rpaulo dp->rd_virtx, dp->rd_virty); 729 1.5.6.2 rpaulo dp->rd_crtcs[j].rc_videomode = *vmp; 730 1.5.6.2 rpaulo printf("%s: port %d: physical %dx%d %dHz\n", 731 1.5.6.2 rpaulo XNAME(sc), j, vmp->hdisplay, vmp->vdisplay, 732 1.5.6.2 rpaulo DIVIDE(DIVIDE(vmp->dot_clock * 1000, 733 1.5.6.2 rpaulo vmp->htotal), vmp->vtotal)); 734 1.5.6.2 rpaulo } 735 1.5.6.2 rpaulo 736 1.5.6.2 rpaulo /* N.B.: radeon wants 64-byte aligned stride */ 737 1.5.6.2 rpaulo dp->rd_stride = dp->rd_virtx * dp->rd_bpp / 8; 738 1.5.6.2 rpaulo //dp->rd_stride = sc->sc_maxx * sc->sc_maxbpp / 8; 739 1.5.6.2 rpaulo dp->rd_stride = ROUNDUP(dp->rd_stride, RADEON_STRIDEALIGN); 740 1.5.6.2 rpaulo 741 1.5.6.2 rpaulo dp->rd_offset = sc->sc_fboffset * i; 742 1.5.6.2 rpaulo dp->rd_fbptr = (vaddr_t)bus_space_vaddr(sc->sc_memt, 743 1.5.6.2 rpaulo sc->sc_memh) + dp->rd_offset; 744 1.5.6.2 rpaulo dp->rd_curoff = sc->sc_fbsize; 745 1.5.6.2 rpaulo dp->rd_curptr = dp->rd_fbptr + dp->rd_curoff; 746 1.5.6.2 rpaulo 747 1.5.6.2 rpaulo DPRINTF(("fpbtr = %p\n", (void *)dp->rd_fbptr)); 748 1.5.6.2 rpaulo 749 1.5.6.2 rpaulo switch (dp->rd_bpp) { 750 1.5.6.2 rpaulo case 8: 751 1.5.6.2 rpaulo dp->rd_format = 2; 752 1.5.6.2 rpaulo break; 753 1.5.6.2 rpaulo case 32: 754 1.5.6.2 rpaulo dp->rd_format = 6; 755 1.5.6.2 rpaulo break; 756 1.5.6.2 rpaulo default: 757 1.5.6.2 rpaulo aprint_error("%s: bad depth %d\n", XNAME(sc), 758 1.5.6.2 rpaulo dp->rd_bpp); 759 1.5.6.2 rpaulo goto error; 760 1.5.6.2 rpaulo } 761 1.5.6.2 rpaulo 762 1.5.6.2 rpaulo printf("init engine\n"); 763 1.5.6.2 rpaulo /* XXX: this seems suspicious - per display engine 764 1.5.6.2 rpaulo initialization? */ 765 1.5.6.2 rpaulo radeonfb_engine_init(dp); 766 1.5.6.2 rpaulo 767 1.5.6.2 rpaulo /* copy the template into place */ 768 1.5.6.2 rpaulo dp->rd_wsscreens_storage[0] = radeonfb_stdscreen; 769 1.5.6.2 rpaulo dp->rd_wsscreens = dp->rd_wsscreens_storage; 770 1.5.6.2 rpaulo 771 1.5.6.2 rpaulo /* and make up the list */ 772 1.5.6.2 rpaulo dp->rd_wsscreenlist.nscreens = 1; 773 1.5.6.2 rpaulo dp->rd_wsscreenlist.screens = 774 1.5.6.2 rpaulo (const struct wsscreen_descr **)&dp->rd_wsscreens; 775 1.5.6.2 rpaulo 776 1.5.6.2 rpaulo vcons_init(&dp->rd_vd, dp, dp->rd_wsscreens, 777 1.5.6.2 rpaulo &radeonfb_accessops); 778 1.5.6.2 rpaulo 779 1.5.6.2 rpaulo dp->rd_vd.init_screen = radeonfb_init_screen; 780 1.5.6.2 rpaulo 781 1.5.6.2 rpaulo dp->rd_console = 1; 782 1.5.6.2 rpaulo 783 1.5.6.2 rpaulo dp->rd_vscreen.scr_flags |= VCONS_SCREEN_IS_STATIC; 784 1.5.6.2 rpaulo 785 1.5.6.2 rpaulo vcons_init_screen(&dp->rd_vd, &dp->rd_vscreen, 786 1.5.6.2 rpaulo dp->rd_console, &defattr); 787 1.5.6.2 rpaulo 788 1.5.6.2 rpaulo ri = &dp->rd_vscreen.scr_ri; 789 1.5.6.2 rpaulo dp->rd_wsscreens->textops = &ri->ri_ops; 790 1.5.6.2 rpaulo dp->rd_wsscreens->capabilities = ri->ri_caps; 791 1.5.6.2 rpaulo dp->rd_wsscreens->nrows = ri->ri_rows; 792 1.5.6.2 rpaulo dp->rd_wsscreens->ncols = ri->ri_cols; 793 1.5.6.2 rpaulo 794 1.5.6.2 rpaulo #ifdef SPLASHSCREEN 795 1.5.6.2 rpaulo dp->rd_splash.si_depth = ri->ri_depth; 796 1.5.6.2 rpaulo dp->rd_splash.si_bits = ri->ri_bits; 797 1.5.6.2 rpaulo dp->rd_splash.si_hwbits = ri->ri_hwbits; 798 1.5.6.2 rpaulo dp->rd_splash.si_width = ri->ri_width; 799 1.5.6.2 rpaulo dp->rd_splash.si_height = ri->ri_height; 800 1.5.6.2 rpaulo dp->rd_splash.si_stride = ri->ri_stride; 801 1.5.6.2 rpaulo dp->rd_splash.si_fillrect = NULL; 802 1.5.6.2 rpaulo #endif 803 1.5.6.2 rpaulo if (dp->rd_console) { 804 1.5.6.2 rpaulo 805 1.5.6.2 rpaulo wsdisplay_cnattach(dp->rd_wsscreens, ri, 0, 0, 806 1.5.6.2 rpaulo defattr); 807 1.5.6.2 rpaulo #ifdef SPLASHSCREEN 808 1.5.6.2 rpaulo splash_render(&dp->rd_splash, 809 1.5.6.2 rpaulo SPLASH_F_CENTER|SPLASH_F_FILL); 810 1.5.6.2 rpaulo #endif 811 1.5.6.2 rpaulo 812 1.5.6.2 rpaulo #ifdef SPLASHSCREEN_PROGRESS 813 1.5.6.2 rpaulo dp->rd_progress.sp_top = (dp->rd_virty / 8) * 7; 814 1.5.6.2 rpaulo dp->rd_progress.sp_width = (dp->rd_virtx / 4) * 3; 815 1.5.6.2 rpaulo dp->rd_progress.sp_left = (dp->rd_virtx - 816 1.5.6.2 rpaulo dp->rd_progress.sp_width) / 2; 817 1.5.6.2 rpaulo dp->rd_progress.sp_height = 20; 818 1.5.6.2 rpaulo dp->rd_progress.sp_state = -1; 819 1.5.6.2 rpaulo dp->rd_progress.sp_si = &dp->rd_splash; 820 1.5.6.2 rpaulo splash_progress_init(&dp->rd_progress); 821 1.5.6.2 rpaulo SCREEN_DISABLE_DRAWING(&dp->rd_vscreen); 822 1.5.6.2 rpaulo #endif 823 1.5.6.2 rpaulo 824 1.5.6.2 rpaulo } else { 825 1.5.6.2 rpaulo 826 1.5.6.2 rpaulo /* 827 1.5.6.2 rpaulo * since we're not the console we can postpone 828 1.5.6.2 rpaulo * the rest until someone actually allocates a 829 1.5.6.2 rpaulo * screen for us. but we do clear the screen 830 1.5.6.2 rpaulo * at least. 831 1.5.6.2 rpaulo */ 832 1.5.6.2 rpaulo memset(ri->ri_bits, 0, 1024); 833 1.5.6.2 rpaulo 834 1.5.6.2 rpaulo radeonfb_modeswitch(dp); 835 1.5.6.2 rpaulo #ifdef SPLASHSCREEN 836 1.5.6.2 rpaulo splash_render(&dp->rd_splash, 837 1.5.6.2 rpaulo SPLASH_F_CENTER|SPLASH_F_FILL); 838 1.5.6.2 rpaulo SCREEN_DISABLE_DRAWING(&dp->rd_vscreen); 839 1.5.6.2 rpaulo #endif 840 1.5.6.2 rpaulo } 841 1.5.6.2 rpaulo 842 1.5.6.2 rpaulo aa.console = dp->rd_console; 843 1.5.6.2 rpaulo aa.scrdata = &dp->rd_wsscreenlist; 844 1.5.6.2 rpaulo aa.accessops = &radeonfb_accessops; 845 1.5.6.2 rpaulo aa.accesscookie = &dp->rd_vd; 846 1.5.6.2 rpaulo 847 1.5.6.2 rpaulo config_found(&sc->sc_dev, &aa, wsemuldisplaydevprint); 848 1.5.6.2 rpaulo radeonfb_blank(dp, 0); 849 1.5.6.2 rpaulo } 850 1.5.6.2 rpaulo 851 1.5.6.2 rpaulo return; 852 1.5.6.2 rpaulo 853 1.5.6.2 rpaulo error: 854 1.5.6.2 rpaulo if (sc->sc_biossz) 855 1.5.6.2 rpaulo free(sc->sc_bios, M_DEVBUF); 856 1.5.6.2 rpaulo 857 1.5.6.2 rpaulo if (sc->sc_regsz) 858 1.5.6.2 rpaulo bus_space_unmap(sc->sc_regt, sc->sc_regh, sc->sc_regsz); 859 1.5.6.2 rpaulo 860 1.5.6.2 rpaulo if (sc->sc_memsz) 861 1.5.6.2 rpaulo bus_space_unmap(sc->sc_memt, sc->sc_memh, sc->sc_memsz); 862 1.5.6.2 rpaulo } 863 1.5.6.2 rpaulo 864 1.5.6.2 rpaulo int 865 1.5.6.2 rpaulo radeonfb_ioctl(void *v, void *vs, 866 1.5.6.2 rpaulo unsigned long cmd, caddr_t d, int flag, struct lwp *l) 867 1.5.6.2 rpaulo { 868 1.5.6.2 rpaulo struct vcons_data *vd; 869 1.5.6.2 rpaulo struct radeonfb_display *dp; 870 1.5.6.2 rpaulo struct radeonfb_softc *sc; 871 1.5.6.2 rpaulo 872 1.5.6.2 rpaulo vd = (struct vcons_data *)v; 873 1.5.6.2 rpaulo dp = (struct radeonfb_display *)vd->cookie; 874 1.5.6.2 rpaulo sc = dp->rd_softc; 875 1.5.6.2 rpaulo 876 1.5.6.2 rpaulo switch (cmd) { 877 1.5.6.2 rpaulo case WSDISPLAYIO_GTYPE: 878 1.5.6.2 rpaulo *(unsigned *)d = WSDISPLAY_TYPE_PCIMISC; 879 1.5.6.2 rpaulo return 0; 880 1.5.6.2 rpaulo 881 1.5.6.2 rpaulo case WSDISPLAYIO_GINFO: 882 1.5.6.2 rpaulo if (vd->active != NULL) { 883 1.5.6.2 rpaulo struct wsdisplay_fbinfo *fb; 884 1.5.6.2 rpaulo fb = (struct wsdisplay_fbinfo *)d; 885 1.5.6.2 rpaulo fb->width = dp->rd_virtx; 886 1.5.6.2 rpaulo fb->height = dp->rd_virty; 887 1.5.6.2 rpaulo fb->depth = dp->rd_bpp; 888 1.5.6.2 rpaulo fb->cmsize = 256; 889 1.5.6.2 rpaulo return 0; 890 1.5.6.2 rpaulo } else 891 1.5.6.2 rpaulo return ENODEV; 892 1.5.6.2 rpaulo case WSDISPLAYIO_GVIDEO: 893 1.5.6.2 rpaulo if (radeonfb_isblank(dp)) 894 1.5.6.2 rpaulo *(unsigned *)d = WSDISPLAYIO_VIDEO_OFF; 895 1.5.6.2 rpaulo else 896 1.5.6.2 rpaulo *(unsigned *)d = WSDISPLAYIO_VIDEO_ON; 897 1.5.6.2 rpaulo return 0; 898 1.5.6.2 rpaulo 899 1.5.6.2 rpaulo case WSDISPLAYIO_SVIDEO: 900 1.5.6.2 rpaulo radeonfb_blank(dp, 901 1.5.6.2 rpaulo (*(unsigned int *)d == WSDISPLAYIO_VIDEO_OFF)); 902 1.5.6.2 rpaulo return 0; 903 1.5.6.2 rpaulo 904 1.5.6.2 rpaulo case WSDISPLAYIO_GETCMAP: 905 1.5.6.2 rpaulo #if 0 906 1.5.6.2 rpaulo if (dp->rd_bpp == 8) 907 1.5.6.2 rpaulo return radeonfb_getcmap(sc, 908 1.5.6.2 rpaulo (struct wsdisplay_cmap *)d); 909 1.5.6.2 rpaulo #endif 910 1.5.6.2 rpaulo return EINVAL; 911 1.5.6.2 rpaulo 912 1.5.6.2 rpaulo case WSDISPLAYIO_PUTCMAP: 913 1.5.6.2 rpaulo #if 0 914 1.5.6.2 rpaulo if (dp->rd_bpp == 8) 915 1.5.6.2 rpaulo return radeonfb_putcmap(sc, 916 1.5.6.2 rpaulo (struct wsdisplay_cmap *)d); 917 1.5.6.2 rpaulo #endif 918 1.5.6.2 rpaulo return EINVAL; 919 1.5.6.2 rpaulo 920 1.5.6.2 rpaulo case WSDISPLAYIO_LINEBYTES: 921 1.5.6.2 rpaulo *(unsigned *)d = dp->rd_stride; 922 1.5.6.2 rpaulo return 0; 923 1.5.6.2 rpaulo 924 1.5.6.2 rpaulo case WSDISPLAYIO_SMODE: 925 1.5.6.2 rpaulo if (*(int *)d != dp->rd_wsmode) { 926 1.5.6.2 rpaulo dp->rd_wsmode = *(int *)d; 927 1.5.6.2 rpaulo if ((dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) && 928 1.5.6.2 rpaulo (dp->rd_vd.active)) { 929 1.5.6.2 rpaulo vcons_redraw_screen(dp->rd_vd.active); 930 1.5.6.2 rpaulo } 931 1.5.6.2 rpaulo } 932 1.5.6.2 rpaulo return 0; 933 1.5.6.2 rpaulo 934 1.5.6.2 rpaulo case WSDISPLAYIO_GCURMAX: 935 1.5.6.2 rpaulo ((struct wsdisplay_curpos *)d)->x = RADEON_CURSORMAXX; 936 1.5.6.2 rpaulo ((struct wsdisplay_curpos *)d)->y = RADEON_CURSORMAXY; 937 1.5.6.2 rpaulo return 0; 938 1.5.6.2 rpaulo 939 1.5.6.2 rpaulo case WSDISPLAYIO_SCURSOR: 940 1.5.6.2 rpaulo return radeonfb_set_cursor(dp, (struct wsdisplay_cursor *)d); 941 1.5.6.2 rpaulo 942 1.5.6.2 rpaulo case WSDISPLAYIO_GCURSOR: 943 1.5.6.2 rpaulo return EPASSTHROUGH; 944 1.5.6.2 rpaulo 945 1.5.6.2 rpaulo case WSDISPLAYIO_GCURPOS: 946 1.5.6.2 rpaulo ((struct wsdisplay_curpos *)d)->x = dp->rd_cursor.rc_pos.x; 947 1.5.6.2 rpaulo ((struct wsdisplay_curpos *)d)->y = dp->rd_cursor.rc_pos.y; 948 1.5.6.2 rpaulo return 0; 949 1.5.6.2 rpaulo 950 1.5.6.2 rpaulo case WSDISPLAYIO_SCURPOS: 951 1.5.6.2 rpaulo return radeonfb_set_curpos(dp, (struct wsdisplay_curpos *)d); 952 1.5.6.2 rpaulo 953 1.5.6.2 rpaulo case WSDISPLAYIO_SSPLASH: 954 1.5.6.2 rpaulo #if defined(SPLASHSCREEN) 955 1.5.6.2 rpaulo if (*(int *)d == 1) { 956 1.5.6.2 rpaulo SCREEN_DISABLE_DRAWING(&dp->rd_vscreen); 957 1.5.6.2 rpaulo splash_render(&dp->rd_splash, 958 1.5.6.2 rpaulo SPLASH_F_CENTER|SPLASH_F_FILL); 959 1.5.6.2 rpaulo } else 960 1.5.6.2 rpaulo SCREEN_ENABLE_DRAWING(&dp->rd_vscreen); 961 1.5.6.2 rpaulo return 0; 962 1.5.6.2 rpaulo #else 963 1.5.6.2 rpaulo return ENODEV; 964 1.5.6.2 rpaulo #endif 965 1.5.6.2 rpaulo case WSDISPLAYIO_SPROGRESS: 966 1.5.6.2 rpaulo #if defined(SPLASHSCREEN) && defined(SPLASHSCREEN_PROGRESS) 967 1.5.6.2 rpaulo dp->rd_progress.sp_force = 1; 968 1.5.6.2 rpaulo splash_progress_update(&dp->rd_progress); 969 1.5.6.2 rpaulo dp->rd_progress.sp_force = 0; 970 1.5.6.2 rpaulo return 0; 971 1.5.6.2 rpaulo #else 972 1.5.6.2 rpaulo return ENODEV; 973 1.5.6.2 rpaulo #endif 974 1.5.6.2 rpaulo 975 1.5.6.2 rpaulo default: 976 1.5.6.2 rpaulo return EPASSTHROUGH; 977 1.5.6.2 rpaulo } 978 1.5.6.2 rpaulo } 979 1.5.6.2 rpaulo 980 1.5.6.2 rpaulo paddr_t 981 1.5.6.2 rpaulo radeonfb_mmap(void *v, void *vs, off_t offset, int prot) 982 1.5.6.2 rpaulo { 983 1.5.6.2 rpaulo struct vcons_data *vd; 984 1.5.6.2 rpaulo struct radeonfb_display *dp; 985 1.5.6.2 rpaulo struct radeonfb_softc *sc; 986 1.5.6.2 rpaulo #ifdef RADEONFB_MMAP_BARS 987 1.5.6.2 rpaulo struct lwp *me; 988 1.5.6.2 rpaulo #endif 989 1.5.6.2 rpaulo paddr_t pa; 990 1.5.6.2 rpaulo 991 1.5.6.2 rpaulo vd = (struct vcons_data *)v; 992 1.5.6.2 rpaulo dp = (struct radeonfb_display *)vd->cookie; 993 1.5.6.2 rpaulo sc = dp->rd_softc; 994 1.5.6.2 rpaulo 995 1.5.6.2 rpaulo /* XXX: note that we don't allow mapping of registers right now */ 996 1.5.6.2 rpaulo /* XXX: this means that the XFree86 radeon driver won't work */ 997 1.5.6.2 rpaulo 998 1.5.6.2 rpaulo if ((offset >= 0) && (offset < (dp->rd_virty * dp->rd_stride))) { 999 1.5.6.2 rpaulo pa = bus_space_mmap(sc->sc_memt, 1000 1.5.6.2 rpaulo sc->sc_memaddr + dp->rd_offset + offset, 0, 1001 1.5.6.2 rpaulo prot, BUS_SPACE_MAP_LINEAR); 1002 1.5.6.2 rpaulo return pa; 1003 1.5.6.2 rpaulo } 1004 1.5.6.2 rpaulo 1005 1.5.6.2 rpaulo #ifdef RADEONFB_MMAP_BARS 1006 1.5.6.2 rpaulo /* 1007 1.5.6.2 rpaulo * restrict all other mappings to processes with superuser privileges 1008 1.5.6.2 rpaulo * or the kernel itself 1009 1.5.6.2 rpaulo */ 1010 1.5.6.2 rpaulo me = curlwp; 1011 1.5.6.2 rpaulo if (me != NULL) { 1012 1.5.6.2 rpaulo if (kauth_authorize_generic(me->l_cred, KAUTH_GENERIC_ISSUSER, 1013 1.5.6.2 rpaulo NULL) != 0) { 1014 1.5.6.2 rpaulo printf("%s: mmap() rejected.\n", sc->sc_dev.dv_xname); 1015 1.5.6.2 rpaulo return -1; 1016 1.5.6.2 rpaulo } 1017 1.5.6.2 rpaulo } 1018 1.5.6.2 rpaulo 1019 1.5.6.2 rpaulo if ((offset >= sc->sc_regaddr) && 1020 1.5.6.2 rpaulo (offset < sc->sc_regaddr + sc->sc_regsz)) { 1021 1.5.6.2 rpaulo return bus_space_mmap(sc->sc_regt, offset, 0, prot, 1022 1.5.6.2 rpaulo BUS_SPACE_MAP_LINEAR); 1023 1.5.6.2 rpaulo } 1024 1.5.6.2 rpaulo 1025 1.5.6.2 rpaulo if ((offset >= sc->sc_memaddr) && 1026 1.5.6.2 rpaulo (offset < sc->sc_memaddr + sc->sc_memsz)) { 1027 1.5.6.2 rpaulo return bus_space_mmap(sc->sc_memt, offset, 0, prot, 1028 1.5.6.2 rpaulo BUS_SPACE_MAP_LINEAR); 1029 1.5.6.2 rpaulo } 1030 1.5.6.2 rpaulo 1031 1.5.6.2 rpaulo #ifdef macppc 1032 1.5.6.2 rpaulo /* allow mapping of IO space */ 1033 1.5.6.2 rpaulo if ((offset >= 0xf2000000) && (offset < 0xf2800000)) { 1034 1.5.6.2 rpaulo pa = bus_space_mmap(sc->sc_iot, offset-0xf2000000, 0, prot, 1035 1.5.6.2 rpaulo BUS_SPACE_MAP_LINEAR); 1036 1.5.6.2 rpaulo return pa; 1037 1.5.6.2 rpaulo } 1038 1.5.6.2 rpaulo #endif /* macppc */ 1039 1.5.6.2 rpaulo 1040 1.5.6.2 rpaulo #endif /* RADEONFB_MMAP_BARS */ 1041 1.5.6.2 rpaulo 1042 1.5.6.2 rpaulo return -1; 1043 1.5.6.2 rpaulo } 1044 1.5.6.2 rpaulo 1045 1.5.6.2 rpaulo static void 1046 1.5.6.2 rpaulo radeonfb_loadbios(struct radeonfb_softc *sc, struct pci_attach_args *pa) 1047 1.5.6.2 rpaulo { 1048 1.5.6.2 rpaulo bus_space_tag_t romt; 1049 1.5.6.2 rpaulo bus_space_handle_t romh, biosh; 1050 1.5.6.2 rpaulo bus_size_t romsz; 1051 1.5.6.2 rpaulo bus_addr_t ptr; 1052 1.5.6.2 rpaulo 1053 1.5.6.2 rpaulo if (pci_mapreg_map(pa, PCI_MAPREG_ROM, PCI_MAPREG_TYPE_ROM, 1054 1.5.6.2 rpaulo BUS_SPACE_MAP_PREFETCHABLE, &romt, &romh, NULL, &romsz) != 0) { 1055 1.5.6.2 rpaulo aprint_verbose("%s: unable to map BIOS!\n", XNAME(sc)); 1056 1.5.6.2 rpaulo return; 1057 1.5.6.2 rpaulo } 1058 1.5.6.2 rpaulo 1059 1.5.6.2 rpaulo pci_find_rom(pa, romt, romh, PCI_ROM_CODE_TYPE_X86, &biosh, 1060 1.5.6.2 rpaulo &sc->sc_biossz); 1061 1.5.6.2 rpaulo if (sc->sc_biossz == 0) { 1062 1.5.6.2 rpaulo aprint_verbose("%s: Video BIOS not present\n", XNAME(sc)); 1063 1.5.6.2 rpaulo return; 1064 1.5.6.2 rpaulo } 1065 1.5.6.2 rpaulo 1066 1.5.6.2 rpaulo sc->sc_bios = malloc(sc->sc_biossz, M_DEVBUF, M_WAITOK); 1067 1.5.6.2 rpaulo bus_space_read_region_1(romt, biosh, 0, sc->sc_bios, sc->sc_biossz); 1068 1.5.6.2 rpaulo 1069 1.5.6.2 rpaulo /* unmap the PCI expansion rom */ 1070 1.5.6.2 rpaulo bus_space_unmap(romt, romh, romsz); 1071 1.5.6.2 rpaulo 1072 1.5.6.2 rpaulo /* turn off rom decoder now */ 1073 1.5.6.2 rpaulo pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM, 1074 1.5.6.2 rpaulo pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM) & 1075 1.5.6.2 rpaulo ~PCI_MAPREG_ROM_ENABLE); 1076 1.5.6.2 rpaulo 1077 1.5.6.2 rpaulo ptr = GETBIOS16(sc, 0x48); 1078 1.5.6.2 rpaulo if ((GETBIOS32(sc, ptr + 4) == 0x41544f4d /* "ATOM" */) || 1079 1.5.6.2 rpaulo (GETBIOS32(sc, ptr + 4) == 0x4d4f5441 /* "MOTA" */)) { 1080 1.5.6.2 rpaulo sc->sc_flags |= RFB_ATOM; 1081 1.5.6.2 rpaulo } 1082 1.5.6.2 rpaulo 1083 1.5.6.2 rpaulo aprint_verbose("%s: Found %d KB %s BIOS\n", XNAME(sc), 1084 1.5.6.2 rpaulo (unsigned)sc->sc_biossz >> 10, IS_ATOM(sc) ? "ATOM" : "Legacy"); 1085 1.5.6.2 rpaulo } 1086 1.5.6.2 rpaulo 1087 1.5.6.2 rpaulo 1088 1.5.6.2 rpaulo uint32_t 1089 1.5.6.2 rpaulo radeonfb_get32(struct radeonfb_softc *sc, uint32_t reg) 1090 1.5.6.2 rpaulo { 1091 1.5.6.2 rpaulo 1092 1.5.6.2 rpaulo return bus_space_read_4(sc->sc_regt, sc->sc_regh, reg); 1093 1.5.6.2 rpaulo } 1094 1.5.6.2 rpaulo 1095 1.5.6.2 rpaulo void 1096 1.5.6.2 rpaulo radeonfb_put32(struct radeonfb_softc *sc, uint32_t reg, uint32_t val) 1097 1.5.6.2 rpaulo { 1098 1.5.6.2 rpaulo 1099 1.5.6.2 rpaulo bus_space_write_4(sc->sc_regt, sc->sc_regh, reg, val); 1100 1.5.6.2 rpaulo } 1101 1.5.6.2 rpaulo 1102 1.5.6.2 rpaulo void 1103 1.5.6.2 rpaulo radeonfb_mask32(struct radeonfb_softc *sc, uint32_t reg, 1104 1.5.6.2 rpaulo uint32_t andmask, uint32_t ormask) 1105 1.5.6.2 rpaulo { 1106 1.5.6.2 rpaulo int s; 1107 1.5.6.2 rpaulo uint32_t val; 1108 1.5.6.2 rpaulo 1109 1.5.6.2 rpaulo s = splhigh(); 1110 1.5.6.2 rpaulo val = radeonfb_get32(sc, reg); 1111 1.5.6.2 rpaulo val = (val & andmask) | ormask; 1112 1.5.6.2 rpaulo radeonfb_put32(sc, reg, val); 1113 1.5.6.2 rpaulo splx(s); 1114 1.5.6.2 rpaulo } 1115 1.5.6.2 rpaulo 1116 1.5.6.2 rpaulo uint32_t 1117 1.5.6.2 rpaulo radeonfb_getindex(struct radeonfb_softc *sc, uint32_t idx) 1118 1.5.6.2 rpaulo { 1119 1.5.6.2 rpaulo int s; 1120 1.5.6.2 rpaulo uint32_t val; 1121 1.5.6.2 rpaulo 1122 1.5.6.2 rpaulo s = splhigh(); 1123 1.5.6.2 rpaulo radeonfb_put32(sc, RADEON_MM_INDEX, idx); 1124 1.5.6.2 rpaulo val = radeonfb_get32(sc, RADEON_MM_DATA); 1125 1.5.6.2 rpaulo splx(s); 1126 1.5.6.2 rpaulo 1127 1.5.6.2 rpaulo return (val); 1128 1.5.6.2 rpaulo } 1129 1.5.6.2 rpaulo 1130 1.5.6.2 rpaulo void 1131 1.5.6.2 rpaulo radeonfb_putindex(struct radeonfb_softc *sc, uint32_t idx, uint32_t val) 1132 1.5.6.2 rpaulo { 1133 1.5.6.2 rpaulo int s; 1134 1.5.6.2 rpaulo 1135 1.5.6.2 rpaulo s = splhigh(); 1136 1.5.6.2 rpaulo radeonfb_put32(sc, RADEON_MM_INDEX, idx); 1137 1.5.6.2 rpaulo radeonfb_put32(sc, RADEON_MM_DATA, val); 1138 1.5.6.2 rpaulo splx(s); 1139 1.5.6.2 rpaulo } 1140 1.5.6.2 rpaulo 1141 1.5.6.2 rpaulo void 1142 1.5.6.2 rpaulo radeonfb_maskindex(struct radeonfb_softc *sc, uint32_t idx, 1143 1.5.6.2 rpaulo uint32_t andmask, uint32_t ormask) 1144 1.5.6.2 rpaulo { 1145 1.5.6.2 rpaulo int s; 1146 1.5.6.2 rpaulo uint32_t val; 1147 1.5.6.2 rpaulo 1148 1.5.6.2 rpaulo s = splhigh(); 1149 1.5.6.2 rpaulo radeonfb_put32(sc, RADEON_MM_INDEX, idx); 1150 1.5.6.2 rpaulo val = radeonfb_get32(sc, RADEON_MM_DATA); 1151 1.5.6.2 rpaulo val = (val & andmask) | ormask; 1152 1.5.6.2 rpaulo radeonfb_put32(sc, RADEON_MM_DATA, val); 1153 1.5.6.2 rpaulo splx(s); 1154 1.5.6.2 rpaulo } 1155 1.5.6.2 rpaulo 1156 1.5.6.2 rpaulo uint32_t 1157 1.5.6.2 rpaulo radeonfb_getpll(struct radeonfb_softc *sc, uint32_t idx) 1158 1.5.6.2 rpaulo { 1159 1.5.6.2 rpaulo int s; 1160 1.5.6.2 rpaulo uint32_t val; 1161 1.5.6.2 rpaulo 1162 1.5.6.2 rpaulo s = splhigh(); 1163 1.5.6.2 rpaulo radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, idx & 0x3f); 1164 1.5.6.2 rpaulo val = radeonfb_get32(sc, RADEON_CLOCK_CNTL_DATA); 1165 1.5.6.2 rpaulo if (HAS_R300CG(sc)) 1166 1.5.6.2 rpaulo radeonfb_r300cg_workaround(sc); 1167 1.5.6.2 rpaulo splx(s); 1168 1.5.6.2 rpaulo 1169 1.5.6.2 rpaulo return (val); 1170 1.5.6.2 rpaulo } 1171 1.5.6.2 rpaulo 1172 1.5.6.2 rpaulo void 1173 1.5.6.2 rpaulo radeonfb_putpll(struct radeonfb_softc *sc, uint32_t idx, uint32_t val) 1174 1.5.6.2 rpaulo { 1175 1.5.6.2 rpaulo int s; 1176 1.5.6.2 rpaulo 1177 1.5.6.2 rpaulo s = splhigh(); 1178 1.5.6.2 rpaulo radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, (idx & 0x3f) | 1179 1.5.6.2 rpaulo RADEON_PLL_WR_EN); 1180 1.5.6.2 rpaulo radeonfb_put32(sc, RADEON_CLOCK_CNTL_DATA, val); 1181 1.5.6.2 rpaulo radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, 0); 1182 1.5.6.2 rpaulo splx(s); 1183 1.5.6.2 rpaulo } 1184 1.5.6.2 rpaulo 1185 1.5.6.2 rpaulo void 1186 1.5.6.2 rpaulo radeonfb_maskpll(struct radeonfb_softc *sc, uint32_t idx, 1187 1.5.6.2 rpaulo uint32_t andmask, uint32_t ormask) 1188 1.5.6.2 rpaulo { 1189 1.5.6.2 rpaulo int s; 1190 1.5.6.2 rpaulo uint32_t val; 1191 1.5.6.2 rpaulo 1192 1.5.6.2 rpaulo s = splhigh(); 1193 1.5.6.2 rpaulo radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, (idx & 0x3f) | 1194 1.5.6.2 rpaulo RADEON_PLL_WR_EN); 1195 1.5.6.2 rpaulo val = radeonfb_get32(sc, RADEON_CLOCK_CNTL_DATA); 1196 1.5.6.2 rpaulo val = (val & andmask) | ormask; 1197 1.5.6.2 rpaulo radeonfb_put32(sc, RADEON_CLOCK_CNTL_DATA, val); 1198 1.5.6.2 rpaulo radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, 0); 1199 1.5.6.2 rpaulo splx(s); 1200 1.5.6.2 rpaulo } 1201 1.5.6.2 rpaulo 1202 1.5.6.2 rpaulo int 1203 1.5.6.2 rpaulo radeonfb_scratch_test(struct radeonfb_softc *sc, int reg, uint32_t v) 1204 1.5.6.2 rpaulo { 1205 1.5.6.2 rpaulo uint32_t saved; 1206 1.5.6.2 rpaulo 1207 1.5.6.2 rpaulo saved = GET32(sc, reg); 1208 1.5.6.2 rpaulo PUT32(sc, reg, v); 1209 1.5.6.2 rpaulo if (GET32(sc, reg) != v) { 1210 1.5.6.2 rpaulo return -1; 1211 1.5.6.2 rpaulo } 1212 1.5.6.2 rpaulo PUT32(sc, reg, saved); 1213 1.5.6.2 rpaulo return 0; 1214 1.5.6.2 rpaulo } 1215 1.5.6.2 rpaulo 1216 1.5.6.2 rpaulo uintmax_t 1217 1.5.6.2 rpaulo radeonfb_getprop_num(struct radeonfb_softc *sc, const char *name, 1218 1.5.6.2 rpaulo uintmax_t defval) 1219 1.5.6.2 rpaulo { 1220 1.5.6.2 rpaulo prop_number_t pn; 1221 1.5.6.2 rpaulo pn = prop_dictionary_get(device_properties(&sc->sc_dev), name); 1222 1.5.6.2 rpaulo if (pn == NULL) { 1223 1.5.6.2 rpaulo return defval; 1224 1.5.6.2 rpaulo } 1225 1.5.6.2 rpaulo KASSERT(prop_object_type(pn) == PROP_TYPE_NUMBER); 1226 1.5.6.2 rpaulo return (prop_number_integer_value(pn)); 1227 1.5.6.2 rpaulo } 1228 1.5.6.2 rpaulo 1229 1.5.6.2 rpaulo int 1230 1.5.6.2 rpaulo radeonfb_getclocks(struct radeonfb_softc *sc) 1231 1.5.6.2 rpaulo { 1232 1.5.6.2 rpaulo bus_addr_t ptr; 1233 1.5.6.2 rpaulo int refclk = 0; 1234 1.5.6.2 rpaulo int refdiv = 0; 1235 1.5.6.2 rpaulo int minpll = 0; 1236 1.5.6.2 rpaulo int maxpll = 0; 1237 1.5.6.2 rpaulo 1238 1.5.6.2 rpaulo /* load initial property values if port/board provides them */ 1239 1.5.6.2 rpaulo refclk = radeonfb_getprop_num(sc, "refclk", 0) & 0xffff; 1240 1.5.6.2 rpaulo refdiv = radeonfb_getprop_num(sc, "refdiv", 0) & 0xffff; 1241 1.5.6.2 rpaulo minpll = radeonfb_getprop_num(sc, "minpll", 0) & 0xffffffffU; 1242 1.5.6.2 rpaulo maxpll = radeonfb_getprop_num(sc, "maxpll", 0) & 0xffffffffU; 1243 1.5.6.2 rpaulo 1244 1.5.6.2 rpaulo if (refclk && refdiv && minpll && maxpll) 1245 1.5.6.2 rpaulo goto dontprobe; 1246 1.5.6.2 rpaulo 1247 1.5.6.2 rpaulo if (!sc->sc_biossz) { 1248 1.5.6.2 rpaulo /* no BIOS */ 1249 1.5.6.2 rpaulo aprint_verbose("%s: No video BIOS, using default clocks\n", 1250 1.5.6.2 rpaulo XNAME(sc)); 1251 1.5.6.2 rpaulo if (IS_IGP(sc)) 1252 1.5.6.2 rpaulo refclk = refclk ? refclk : 1432; 1253 1.5.6.2 rpaulo else 1254 1.5.6.2 rpaulo refclk = refclk ? refclk : 2700; 1255 1.5.6.2 rpaulo refdiv = refdiv ? refdiv : 12; 1256 1.5.6.2 rpaulo minpll = minpll ? minpll : 12500; 1257 1.5.6.2 rpaulo maxpll = maxpll ? maxpll : 35000; 1258 1.5.6.2 rpaulo } else if (IS_ATOM(sc)) { 1259 1.5.6.2 rpaulo /* ATOM BIOS */ 1260 1.5.6.2 rpaulo ptr = GETBIOS16(sc, 0x48); 1261 1.5.6.2 rpaulo ptr = GETBIOS16(sc, ptr + 32); /* aka MasterDataStart */ 1262 1.5.6.2 rpaulo ptr = GETBIOS16(sc, ptr + 12); /* pll info block */ 1263 1.5.6.2 rpaulo refclk = refclk ? refclk : GETBIOS16(sc, ptr + 82); 1264 1.5.6.2 rpaulo minpll = minpll ? minpll : GETBIOS16(sc, ptr + 78); 1265 1.5.6.2 rpaulo maxpll = maxpll ? maxpll : GETBIOS16(sc, ptr + 32); 1266 1.5.6.2 rpaulo /* 1267 1.5.6.2 rpaulo * ATOM BIOS doesn't supply a reference divider, so we 1268 1.5.6.2 rpaulo * have to probe for it. 1269 1.5.6.2 rpaulo */ 1270 1.5.6.2 rpaulo if (refdiv < 2) 1271 1.5.6.2 rpaulo refdiv = GETPLL(sc, RADEON_PPLL_REF_DIV) & 1272 1.5.6.2 rpaulo RADEON_PPLL_REF_DIV_MASK; 1273 1.5.6.2 rpaulo /* 1274 1.5.6.2 rpaulo * if probe is zero, just assume one that should work 1275 1.5.6.2 rpaulo * for most parts 1276 1.5.6.2 rpaulo */ 1277 1.5.6.2 rpaulo if (refdiv < 2) 1278 1.5.6.2 rpaulo refdiv = 12; 1279 1.5.6.2 rpaulo 1280 1.5.6.2 rpaulo } else { 1281 1.5.6.2 rpaulo /* Legacy BIOS */ 1282 1.5.6.2 rpaulo ptr = GETBIOS16(sc, 0x48); 1283 1.5.6.2 rpaulo ptr = GETBIOS16(sc, ptr + 0x30); 1284 1.5.6.2 rpaulo refclk = refclk ? refclk : GETBIOS16(sc, ptr + 0x0E); 1285 1.5.6.2 rpaulo refdiv = refdiv ? refdiv : GETBIOS16(sc, ptr + 0x10); 1286 1.5.6.2 rpaulo minpll = minpll ? minpll : GETBIOS32(sc, ptr + 0x12); 1287 1.5.6.2 rpaulo maxpll = maxpll ? maxpll : GETBIOS32(sc, ptr + 0x16); 1288 1.5.6.2 rpaulo } 1289 1.5.6.2 rpaulo 1290 1.5.6.2 rpaulo 1291 1.5.6.2 rpaulo dontprobe: 1292 1.5.6.2 rpaulo sc->sc_refclk = refclk * 10; 1293 1.5.6.2 rpaulo sc->sc_refdiv = refdiv; 1294 1.5.6.2 rpaulo sc->sc_minpll = minpll * 10; 1295 1.5.6.2 rpaulo sc->sc_maxpll = maxpll * 10; 1296 1.5.6.2 rpaulo return 0; 1297 1.5.6.2 rpaulo } 1298 1.5.6.2 rpaulo 1299 1.5.6.2 rpaulo int 1300 1.5.6.2 rpaulo radeonfb_calc_dividers(struct radeonfb_softc *sc, uint32_t dotclock, 1301 1.5.6.2 rpaulo uint32_t *postdivbit, uint32_t *feedbackdiv) 1302 1.5.6.2 rpaulo { 1303 1.5.6.2 rpaulo int i; 1304 1.5.6.2 rpaulo uint32_t outfreq; 1305 1.5.6.2 rpaulo int div; 1306 1.5.6.2 rpaulo 1307 1.5.6.2 rpaulo DPRINTF(("dot clock: %u\n", dotclock)); 1308 1.5.6.2 rpaulo for (i = 0; (div = radeonfb_dividers[i].divider) != 0; i++) { 1309 1.5.6.2 rpaulo outfreq = div * dotclock; 1310 1.5.6.2 rpaulo if ((outfreq >= sc->sc_minpll) && 1311 1.5.6.2 rpaulo (outfreq <= sc->sc_maxpll)) { 1312 1.5.6.2 rpaulo DPRINTF(("outfreq: %u\n", outfreq)); 1313 1.5.6.2 rpaulo *postdivbit = 1314 1.5.6.2 rpaulo ((uint32_t)radeonfb_dividers[i].mask << 16); 1315 1.5.6.2 rpaulo DPRINTF(("post divider: %d (mask %x)\n", div, 1316 1.5.6.2 rpaulo *postdivbit)); 1317 1.5.6.2 rpaulo break; 1318 1.5.6.2 rpaulo } 1319 1.5.6.2 rpaulo } 1320 1.5.6.2 rpaulo 1321 1.5.6.2 rpaulo if (div == 0) 1322 1.5.6.2 rpaulo return 1; 1323 1.5.6.2 rpaulo 1324 1.5.6.2 rpaulo *feedbackdiv = DIVIDE(sc->sc_refdiv * outfreq, sc->sc_refclk); 1325 1.5.6.2 rpaulo DPRINTF(("feedback divider: %d\n", *feedbackdiv)); 1326 1.5.6.2 rpaulo return 0; 1327 1.5.6.2 rpaulo } 1328 1.5.6.2 rpaulo 1329 1.5.6.2 rpaulo #if 0 1330 1.5.6.2 rpaulo #ifdef RADEON_DEBUG 1331 1.5.6.2 rpaulo static void 1332 1.5.6.2 rpaulo dump_buffer(const char *pfx, void *buffer, unsigned int size) 1333 1.5.6.2 rpaulo { 1334 1.5.6.2 rpaulo char asc[17]; 1335 1.5.6.2 rpaulo unsigned ptr = (unsigned)buffer; 1336 1.5.6.2 rpaulo char *start = (char *)(ptr & ~0xf); 1337 1.5.6.2 rpaulo char *end = (char *)(ptr + size); 1338 1.5.6.2 rpaulo 1339 1.5.6.2 rpaulo end = (char *)(((unsigned)end + 0xf) & ~0xf); 1340 1.5.6.2 rpaulo 1341 1.5.6.2 rpaulo if (pfx == NULL) { 1342 1.5.6.2 rpaulo pfx = ""; 1343 1.5.6.2 rpaulo } 1344 1.5.6.2 rpaulo 1345 1.5.6.2 rpaulo while (start < end) { 1346 1.5.6.2 rpaulo unsigned offset = (unsigned)start & 0xf; 1347 1.5.6.2 rpaulo if (offset == 0) { 1348 1.5.6.2 rpaulo printf("%s%x: ", pfx, (unsigned)start); 1349 1.5.6.2 rpaulo } 1350 1.5.6.2 rpaulo if (((unsigned)start < ptr) || 1351 1.5.6.2 rpaulo ((unsigned)start >= (ptr + size))) { 1352 1.5.6.2 rpaulo printf(" "); 1353 1.5.6.2 rpaulo asc[offset] = ' '; 1354 1.5.6.2 rpaulo } else { 1355 1.5.6.2 rpaulo printf("%02x", *(unsigned char *)start); 1356 1.5.6.2 rpaulo if ((*start >= ' ') && (*start <= '~')) { 1357 1.5.6.2 rpaulo asc[offset] = *start; 1358 1.5.6.2 rpaulo } else { 1359 1.5.6.2 rpaulo asc[offset] = '.'; 1360 1.5.6.2 rpaulo } 1361 1.5.6.2 rpaulo } 1362 1.5.6.2 rpaulo asc[offset + 1] = 0; 1363 1.5.6.2 rpaulo if (offset % 2) { 1364 1.5.6.2 rpaulo printf(" "); 1365 1.5.6.2 rpaulo } 1366 1.5.6.2 rpaulo if (offset == 15) { 1367 1.5.6.2 rpaulo printf(" %s\n", asc); 1368 1.5.6.2 rpaulo } 1369 1.5.6.2 rpaulo start++; 1370 1.5.6.2 rpaulo } 1371 1.5.6.2 rpaulo } 1372 1.5.6.2 rpaulo #endif 1373 1.5.6.2 rpaulo #endif 1374 1.5.6.2 rpaulo 1375 1.5.6.2 rpaulo int 1376 1.5.6.2 rpaulo radeonfb_getconnectors(struct radeonfb_softc *sc) 1377 1.5.6.2 rpaulo { 1378 1.5.6.2 rpaulo int i; 1379 1.5.6.2 rpaulo int found = 0; 1380 1.5.6.2 rpaulo 1381 1.5.6.2 rpaulo for (i = 0; i < 2; i++) { 1382 1.5.6.2 rpaulo sc->sc_ports[i].rp_mon_type = RADEON_MT_UNKNOWN; 1383 1.5.6.2 rpaulo sc->sc_ports[i].rp_ddc_type = RADEON_DDC_NONE; 1384 1.5.6.2 rpaulo sc->sc_ports[i].rp_dac_type = RADEON_DAC_UNKNOWN; 1385 1.5.6.2 rpaulo sc->sc_ports[i].rp_conn_type = RADEON_CONN_NONE; 1386 1.5.6.2 rpaulo sc->sc_ports[i].rp_tmds_type = RADEON_TMDS_UNKNOWN; 1387 1.5.6.2 rpaulo } 1388 1.5.6.2 rpaulo 1389 1.5.6.2 rpaulo /* 1390 1.5.6.2 rpaulo * This logic is borrowed from Xorg's radeon driver. 1391 1.5.6.2 rpaulo */ 1392 1.5.6.2 rpaulo if (!sc->sc_biossz) 1393 1.5.6.2 rpaulo goto nobios; 1394 1.5.6.2 rpaulo 1395 1.5.6.2 rpaulo if (IS_ATOM(sc)) { 1396 1.5.6.2 rpaulo /* not done yet */ 1397 1.5.6.2 rpaulo } else { 1398 1.5.6.2 rpaulo uint16_t ptr; 1399 1.5.6.2 rpaulo int port = 0; 1400 1.5.6.2 rpaulo 1401 1.5.6.2 rpaulo ptr = GETBIOS16(sc, 0x48); 1402 1.5.6.2 rpaulo ptr = GETBIOS16(sc, ptr + 0x50); 1403 1.5.6.2 rpaulo for (i = 1; i < 4; i++) { 1404 1.5.6.2 rpaulo uint16_t entry; 1405 1.5.6.2 rpaulo uint8_t conn, ddc, dac, tmds; 1406 1.5.6.2 rpaulo 1407 1.5.6.2 rpaulo /* 1408 1.5.6.2 rpaulo * Parse the connector table. From reading the code, 1409 1.5.6.2 rpaulo * it appears to made up of 16-bit entries for each 1410 1.5.6.2 rpaulo * connector. The 16-bits are defined as: 1411 1.5.6.2 rpaulo * 1412 1.5.6.2 rpaulo * bits 12-15 - connector type (0 == end of table) 1413 1.5.6.2 rpaulo * bits 8-11 - DDC type 1414 1.5.6.2 rpaulo * bits 5-7 - ??? 1415 1.5.6.2 rpaulo * bit 4 - TMDS type (1 = EXT, 0 = INT) 1416 1.5.6.2 rpaulo * bits 1-3 - ??? 1417 1.5.6.2 rpaulo * bit 0 - DAC, 1 = TVDAC, 0 = primary 1418 1.5.6.2 rpaulo */ 1419 1.5.6.2 rpaulo if (!GETBIOS8(sc, ptr + i * 2) && i > 1) 1420 1.5.6.2 rpaulo break; 1421 1.5.6.2 rpaulo entry = GETBIOS16(sc, ptr + i * 2); 1422 1.5.6.2 rpaulo 1423 1.5.6.2 rpaulo conn = (entry >> 12) & 0xf; 1424 1.5.6.2 rpaulo ddc = (entry >> 8) & 0xf; 1425 1.5.6.2 rpaulo dac = (entry & 0x1) ? RADEON_DAC_TVDAC : 1426 1.5.6.2 rpaulo RADEON_DAC_PRIMARY; 1427 1.5.6.2 rpaulo tmds = ((entry >> 4) & 0x1) ? RADEON_TMDS_EXT : 1428 1.5.6.2 rpaulo RADEON_TMDS_INT; 1429 1.5.6.2 rpaulo 1430 1.5.6.2 rpaulo if (conn == RADEON_CONN_NONE) 1431 1.5.6.2 rpaulo continue; /* no connector */ 1432 1.5.6.2 rpaulo 1433 1.5.6.2 rpaulo if ((found > 0) && 1434 1.5.6.2 rpaulo (sc->sc_ports[port].rp_ddc_type == ddc)) { 1435 1.5.6.2 rpaulo /* duplicate entry for same connector */ 1436 1.5.6.2 rpaulo continue; 1437 1.5.6.2 rpaulo } 1438 1.5.6.2 rpaulo 1439 1.5.6.2 rpaulo /* internal DDC_DVI port gets priority */ 1440 1.5.6.2 rpaulo if ((ddc == RADEON_DDC_DVI) || (port == 1)) 1441 1.5.6.2 rpaulo port = 0; 1442 1.5.6.2 rpaulo else 1443 1.5.6.2 rpaulo port = 1; 1444 1.5.6.2 rpaulo 1445 1.5.6.2 rpaulo sc->sc_ports[port].rp_ddc_type = 1446 1.5.6.2 rpaulo ddc > RADEON_DDC_CRT2 ? RADEON_DDC_NONE : ddc; 1447 1.5.6.2 rpaulo sc->sc_ports[port].rp_dac_type = dac; 1448 1.5.6.2 rpaulo sc->sc_ports[port].rp_conn_type = 1449 1.5.6.2 rpaulo min(conn, RADEON_CONN_UNSUPPORTED) ; 1450 1.5.6.2 rpaulo 1451 1.5.6.2 rpaulo sc->sc_ports[port].rp_tmds_type = tmds; 1452 1.5.6.2 rpaulo 1453 1.5.6.2 rpaulo if ((conn != RADEON_CONN_DVI_I) && 1454 1.5.6.2 rpaulo (conn != RADEON_CONN_DVI_D) && 1455 1.5.6.2 rpaulo (tmds == RADEON_TMDS_INT)) 1456 1.5.6.2 rpaulo sc->sc_ports[port].rp_tmds_type = 1457 1.5.6.2 rpaulo RADEON_TMDS_UNKNOWN; 1458 1.5.6.2 rpaulo 1459 1.5.6.2 rpaulo found += (port + 1); 1460 1.5.6.2 rpaulo } 1461 1.5.6.2 rpaulo } 1462 1.5.6.2 rpaulo 1463 1.5.6.2 rpaulo nobios: 1464 1.5.6.2 rpaulo if (!found) { 1465 1.5.6.2 rpaulo DPRINTF(("No connector info in BIOS!\n")); 1466 1.5.6.2 rpaulo /* default, port 0 = internal TMDS, port 1 = CRT */ 1467 1.5.6.2 rpaulo sc->sc_ports[0].rp_mon_type = RADEON_MT_UNKNOWN; 1468 1.5.6.2 rpaulo sc->sc_ports[0].rp_ddc_type = RADEON_DDC_DVI; 1469 1.5.6.2 rpaulo sc->sc_ports[0].rp_dac_type = RADEON_DAC_TVDAC; 1470 1.5.6.2 rpaulo sc->sc_ports[0].rp_conn_type = RADEON_CONN_DVI_D; 1471 1.5.6.2 rpaulo sc->sc_ports[0].rp_tmds_type = RADEON_TMDS_INT; 1472 1.5.6.2 rpaulo 1473 1.5.6.2 rpaulo sc->sc_ports[1].rp_mon_type = RADEON_MT_UNKNOWN; 1474 1.5.6.2 rpaulo sc->sc_ports[1].rp_ddc_type = RADEON_DDC_VGA; 1475 1.5.6.2 rpaulo sc->sc_ports[1].rp_dac_type = RADEON_DAC_PRIMARY; 1476 1.5.6.2 rpaulo sc->sc_ports[1].rp_conn_type = RADEON_CONN_CRT; 1477 1.5.6.2 rpaulo sc->sc_ports[1].rp_tmds_type = RADEON_TMDS_EXT; 1478 1.5.6.2 rpaulo } 1479 1.5.6.2 rpaulo 1480 1.5.6.2 rpaulo /* 1481 1.5.6.2 rpaulo * Fixup for RS300/RS350/RS400 chips, that lack a primary DAC. 1482 1.5.6.2 rpaulo * these chips should use TVDAC for the VGA port. 1483 1.5.6.2 rpaulo */ 1484 1.5.6.2 rpaulo if (HAS_SDAC(sc)) { 1485 1.5.6.2 rpaulo if (sc->sc_ports[0].rp_conn_type == RADEON_CONN_CRT) { 1486 1.5.6.2 rpaulo sc->sc_ports[0].rp_dac_type = RADEON_DAC_TVDAC; 1487 1.5.6.2 rpaulo sc->sc_ports[1].rp_dac_type = RADEON_DAC_PRIMARY; 1488 1.5.6.2 rpaulo } else { 1489 1.5.6.2 rpaulo sc->sc_ports[1].rp_dac_type = RADEON_DAC_TVDAC; 1490 1.5.6.2 rpaulo sc->sc_ports[0].rp_dac_type = RADEON_DAC_PRIMARY; 1491 1.5.6.2 rpaulo } 1492 1.5.6.2 rpaulo } else if (!HAS_CRTC2(sc)) { 1493 1.5.6.2 rpaulo sc->sc_ports[0].rp_dac_type = RADEON_DAC_PRIMARY; 1494 1.5.6.2 rpaulo } 1495 1.5.6.2 rpaulo 1496 1.5.6.2 rpaulo for (i = 0; i < 2; i++) { 1497 1.5.6.2 rpaulo char edid[128]; 1498 1.5.6.2 rpaulo uint8_t ddc; 1499 1.5.6.2 rpaulo struct edid_info *eip = &sc->sc_ports[i].rp_edid; 1500 1.5.6.2 rpaulo 1501 1.5.6.2 rpaulo DPRINTF(("Port #%d:\n", i)); 1502 1.5.6.2 rpaulo DPRINTF((" conn = %d\n", sc->sc_ports[i].rp_conn_type)); 1503 1.5.6.2 rpaulo DPRINTF((" ddc = %d\n", sc->sc_ports[i].rp_ddc_type)); 1504 1.5.6.2 rpaulo DPRINTF((" dac = %d\n", sc->sc_ports[i].rp_dac_type)); 1505 1.5.6.2 rpaulo DPRINTF((" tmds = %d\n", sc->sc_ports[i].rp_tmds_type)); 1506 1.5.6.2 rpaulo 1507 1.5.6.2 rpaulo sc->sc_ports[i].rp_edid_valid = 0; 1508 1.5.6.2 rpaulo ddc = sc->sc_ports[i].rp_ddc_type; 1509 1.5.6.2 rpaulo if (ddc != RADEON_DDC_NONE) { 1510 1.5.6.2 rpaulo if ((radeonfb_i2c_read_edid(sc, ddc, edid) == 0) && 1511 1.5.6.2 rpaulo (edid_parse(edid, eip) == 0)) { 1512 1.5.6.2 rpaulo sc->sc_ports[i].rp_edid_valid = 1; 1513 1.5.6.2 rpaulo edid_print(eip); 1514 1.5.6.2 rpaulo } 1515 1.5.6.2 rpaulo } 1516 1.5.6.2 rpaulo } 1517 1.5.6.2 rpaulo 1518 1.5.6.2 rpaulo return found; 1519 1.5.6.2 rpaulo } 1520 1.5.6.2 rpaulo 1521 1.5.6.2 rpaulo int 1522 1.5.6.2 rpaulo radeonfb_gettmds(struct radeonfb_softc *sc) 1523 1.5.6.2 rpaulo { 1524 1.5.6.2 rpaulo int i; 1525 1.5.6.2 rpaulo 1526 1.5.6.2 rpaulo if (!sc->sc_biossz) { 1527 1.5.6.2 rpaulo goto nobios; 1528 1.5.6.2 rpaulo } 1529 1.5.6.2 rpaulo 1530 1.5.6.2 rpaulo if (IS_ATOM(sc)) { 1531 1.5.6.2 rpaulo /* XXX: not done yet */ 1532 1.5.6.2 rpaulo } else { 1533 1.5.6.2 rpaulo uint16_t ptr; 1534 1.5.6.2 rpaulo int n; 1535 1.5.6.2 rpaulo 1536 1.5.6.2 rpaulo ptr = GETBIOS16(sc, 0x48); 1537 1.5.6.2 rpaulo ptr = GETBIOS16(sc, ptr + 0x34); 1538 1.5.6.2 rpaulo DPRINTF(("DFP table revision %d\n", GETBIOS8(sc, ptr))); 1539 1.5.6.2 rpaulo if (GETBIOS8(sc, ptr) == 3) { 1540 1.5.6.2 rpaulo /* revision three table */ 1541 1.5.6.2 rpaulo n = GETBIOS8(sc, ptr + 5) + 1; 1542 1.5.6.2 rpaulo n = min(n, 4); 1543 1.5.6.2 rpaulo 1544 1.5.6.2 rpaulo memset(sc->sc_tmds_pll, 0, sizeof (sc->sc_tmds_pll)); 1545 1.5.6.2 rpaulo for (i = 0; i < n; i++) { 1546 1.5.6.2 rpaulo sc->sc_tmds_pll[i].rtp_pll = GETBIOS32(sc, 1547 1.5.6.2 rpaulo ptr + i * 10 + 8); 1548 1.5.6.2 rpaulo sc->sc_tmds_pll[i].rtp_freq = GETBIOS16(sc, 1549 1.5.6.2 rpaulo ptr + i * 10 + 0x10); 1550 1.5.6.2 rpaulo DPRINTF(("TMDS_PLL dot clock %d pll %x\n", 1551 1.5.6.2 rpaulo sc->sc_tmds_pll[i].rtp_freq, 1552 1.5.6.2 rpaulo sc->sc_tmds_pll[i].rtp_pll)); 1553 1.5.6.2 rpaulo } 1554 1.5.6.2 rpaulo return 0; 1555 1.5.6.2 rpaulo } 1556 1.5.6.2 rpaulo } 1557 1.5.6.2 rpaulo 1558 1.5.6.2 rpaulo nobios: 1559 1.5.6.2 rpaulo DPRINTF(("no suitable DFP table present\n")); 1560 1.5.6.2 rpaulo for (i = 0; 1561 1.5.6.2 rpaulo i < sizeof (radeonfb_tmds_pll) / sizeof (radeonfb_tmds_pll[0]); 1562 1.5.6.2 rpaulo i++) { 1563 1.5.6.2 rpaulo int j; 1564 1.5.6.2 rpaulo 1565 1.5.6.2 rpaulo if (radeonfb_tmds_pll[i].family != sc->sc_family) 1566 1.5.6.2 rpaulo continue; 1567 1.5.6.2 rpaulo 1568 1.5.6.2 rpaulo for (j = 0; j < 4; j++) { 1569 1.5.6.2 rpaulo sc->sc_tmds_pll[j] = radeonfb_tmds_pll[i].plls[j]; 1570 1.5.6.2 rpaulo DPRINTF(("TMDS_PLL dot clock %d pll %x\n", 1571 1.5.6.2 rpaulo sc->sc_tmds_pll[j].rtp_freq, 1572 1.5.6.2 rpaulo sc->sc_tmds_pll[j].rtp_pll)); 1573 1.5.6.2 rpaulo } 1574 1.5.6.2 rpaulo return 0; 1575 1.5.6.2 rpaulo } 1576 1.5.6.2 rpaulo 1577 1.5.6.2 rpaulo return -1; 1578 1.5.6.2 rpaulo } 1579 1.5.6.2 rpaulo 1580 1.5.6.2 rpaulo const struct videomode * 1581 1.5.6.2 rpaulo radeonfb_modelookup(const char *name) 1582 1.5.6.2 rpaulo { 1583 1.5.6.2 rpaulo int i; 1584 1.5.6.2 rpaulo 1585 1.5.6.2 rpaulo for (i = 0; i < videomode_count; i++) 1586 1.5.6.2 rpaulo if (!strcmp(name, videomode_list[i].name)) 1587 1.5.6.2 rpaulo return &videomode_list[i]; 1588 1.5.6.2 rpaulo 1589 1.5.6.2 rpaulo return NULL; 1590 1.5.6.2 rpaulo } 1591 1.5.6.2 rpaulo 1592 1.5.6.2 rpaulo void 1593 1.5.6.2 rpaulo radeonfb_pllwriteupdate(struct radeonfb_softc *sc, int crtc) 1594 1.5.6.2 rpaulo { 1595 1.5.6.2 rpaulo if (crtc) { 1596 1.5.6.2 rpaulo while (GETPLL(sc, RADEON_P2PLL_REF_DIV) & 1597 1.5.6.2 rpaulo RADEON_P2PLL_ATOMIC_UPDATE_R); 1598 1.5.6.2 rpaulo SETPLL(sc, RADEON_P2PLL_REF_DIV, RADEON_P2PLL_ATOMIC_UPDATE_W); 1599 1.5.6.2 rpaulo } else { 1600 1.5.6.2 rpaulo while (GETPLL(sc, RADEON_PPLL_REF_DIV) & 1601 1.5.6.2 rpaulo RADEON_PPLL_ATOMIC_UPDATE_R); 1602 1.5.6.2 rpaulo SETPLL(sc, RADEON_PPLL_REF_DIV, RADEON_PPLL_ATOMIC_UPDATE_W); 1603 1.5.6.2 rpaulo } 1604 1.5.6.2 rpaulo } 1605 1.5.6.2 rpaulo 1606 1.5.6.2 rpaulo void 1607 1.5.6.2 rpaulo radeonfb_pllwaitatomicread(struct radeonfb_softc *sc, int crtc) 1608 1.5.6.2 rpaulo { 1609 1.5.6.2 rpaulo int i; 1610 1.5.6.2 rpaulo 1611 1.5.6.2 rpaulo for (i = 10000; i; i--) { 1612 1.5.6.2 rpaulo if (crtc) { 1613 1.5.6.2 rpaulo if (GETPLL(sc, RADEON_P2PLL_REF_DIV) & 1614 1.5.6.2 rpaulo RADEON_P2PLL_ATOMIC_UPDATE_R) 1615 1.5.6.2 rpaulo break; 1616 1.5.6.2 rpaulo } else { 1617 1.5.6.2 rpaulo if (GETPLL(sc, RADEON_PPLL_REF_DIV) & 1618 1.5.6.2 rpaulo RADEON_PPLL_ATOMIC_UPDATE_R) 1619 1.5.6.2 rpaulo break; 1620 1.5.6.2 rpaulo } 1621 1.5.6.2 rpaulo } 1622 1.5.6.2 rpaulo } 1623 1.5.6.2 rpaulo 1624 1.5.6.2 rpaulo void 1625 1.5.6.2 rpaulo radeonfb_program_vclk(struct radeonfb_softc *sc, int dotclock, int crtc) 1626 1.5.6.2 rpaulo { 1627 1.5.6.2 rpaulo uint32_t pbit = 0; 1628 1.5.6.2 rpaulo uint32_t feed = 0; 1629 1.5.6.2 rpaulo uint32_t data; 1630 1.5.6.2 rpaulo #if 1 1631 1.5.6.2 rpaulo int i; 1632 1.5.6.2 rpaulo #endif 1633 1.5.6.2 rpaulo 1634 1.5.6.2 rpaulo radeonfb_calc_dividers(sc, dotclock, &pbit, &feed); 1635 1.5.6.2 rpaulo 1636 1.5.6.2 rpaulo if (crtc == 0) { 1637 1.5.6.2 rpaulo 1638 1.5.6.2 rpaulo /* XXXX: mobility workaround missing */ 1639 1.5.6.2 rpaulo /* XXXX: R300 stuff missing */ 1640 1.5.6.2 rpaulo 1641 1.5.6.2 rpaulo PATCHPLL(sc, RADEON_VCLK_ECP_CNTL, 1642 1.5.6.2 rpaulo RADEON_VCLK_SRC_SEL_CPUCLK, 1643 1.5.6.2 rpaulo ~RADEON_VCLK_SRC_SEL_MASK); 1644 1.5.6.2 rpaulo 1645 1.5.6.2 rpaulo /* put vclk into reset, use atomic updates */ 1646 1.5.6.2 rpaulo SETPLL(sc, RADEON_PPLL_CNTL, 1647 1.5.6.2 rpaulo RADEON_PPLL_REFCLK_SEL | 1648 1.5.6.2 rpaulo RADEON_PPLL_FBCLK_SEL | 1649 1.5.6.2 rpaulo RADEON_PPLL_RESET | 1650 1.5.6.2 rpaulo RADEON_PPLL_ATOMIC_UPDATE_EN | 1651 1.5.6.2 rpaulo RADEON_PPLL_VGA_ATOMIC_UPDATE_EN); 1652 1.5.6.2 rpaulo 1653 1.5.6.2 rpaulo /* select clock 3 */ 1654 1.5.6.2 rpaulo #if 0 1655 1.5.6.2 rpaulo PATCH32(sc, RADEON_CLOCK_CNTL_INDEX, RADEON_PLL_DIV_SEL, 1656 1.5.6.2 rpaulo ~RADEON_PLL_DIV_SEL); 1657 1.5.6.2 rpaulo #else 1658 1.5.6.2 rpaulo PATCH32(sc, RADEON_CLOCK_CNTL_INDEX, 0, 1659 1.5.6.2 rpaulo ~RADEON_PLL_DIV_SEL); 1660 1.5.6.2 rpaulo #endif 1661 1.5.6.2 rpaulo 1662 1.5.6.2 rpaulo /* XXX: R300 family -- program divider differently? */ 1663 1.5.6.2 rpaulo 1664 1.5.6.2 rpaulo /* program reference divider */ 1665 1.5.6.2 rpaulo PATCHPLL(sc, RADEON_PPLL_REF_DIV, sc->sc_refdiv, 1666 1.5.6.2 rpaulo ~RADEON_PPLL_REF_DIV_MASK); 1667 1.5.6.2 rpaulo PRINTPLL(RADEON_PPLL_REF_DIV); 1668 1.5.6.2 rpaulo 1669 1.5.6.2 rpaulo #if 0 1670 1.5.6.2 rpaulo data = GETPLL(sc, RADEON_PPLL_DIV_3); 1671 1.5.6.2 rpaulo data &= ~(RADEON_PPLL_FB3_DIV_MASK | 1672 1.5.6.2 rpaulo RADEON_PPLL_POST3_DIV_MASK); 1673 1.5.6.2 rpaulo data |= pbit; 1674 1.5.6.2 rpaulo data |= (feed & RADEON_PPLL_FB3_DIV_MASK); 1675 1.5.6.2 rpaulo PUTPLL(sc, RADEON_PPLL_DIV_3, data); 1676 1.5.6.2 rpaulo #else 1677 1.5.6.2 rpaulo for (i = 0; i < 4; i++) { 1678 1.5.6.2 rpaulo } 1679 1.5.6.2 rpaulo #endif 1680 1.5.6.2 rpaulo 1681 1.5.6.2 rpaulo /* use the atomic update */ 1682 1.5.6.2 rpaulo radeonfb_pllwriteupdate(sc, crtc); 1683 1.5.6.2 rpaulo 1684 1.5.6.2 rpaulo /* and wait for it to complete */ 1685 1.5.6.2 rpaulo radeonfb_pllwaitatomicread(sc, crtc); 1686 1.5.6.2 rpaulo 1687 1.5.6.2 rpaulo /* program HTOTAL (why?) */ 1688 1.5.6.2 rpaulo PUTPLL(sc, RADEON_HTOTAL_CNTL, 0); 1689 1.5.6.2 rpaulo 1690 1.5.6.2 rpaulo /* drop reset */ 1691 1.5.6.2 rpaulo CLRPLL(sc, RADEON_PPLL_CNTL, 1692 1.5.6.2 rpaulo RADEON_PPLL_RESET | RADEON_PPLL_SLEEP | 1693 1.5.6.2 rpaulo RADEON_PPLL_ATOMIC_UPDATE_EN | 1694 1.5.6.2 rpaulo RADEON_PPLL_VGA_ATOMIC_UPDATE_EN); 1695 1.5.6.2 rpaulo 1696 1.5.6.2 rpaulo PRINTPLL(RADEON_PPLL_CNTL); 1697 1.5.6.2 rpaulo 1698 1.5.6.2 rpaulo /* give clock time to lock */ 1699 1.5.6.2 rpaulo delay(50000); 1700 1.5.6.2 rpaulo 1701 1.5.6.2 rpaulo PATCHPLL(sc, RADEON_VCLK_ECP_CNTL, 1702 1.5.6.2 rpaulo RADEON_VCLK_SRC_SEL_PPLLCLK, 1703 1.5.6.2 rpaulo ~RADEON_VCLK_SRC_SEL_MASK); 1704 1.5.6.2 rpaulo 1705 1.5.6.2 rpaulo } else { 1706 1.5.6.2 rpaulo 1707 1.5.6.2 rpaulo PATCHPLL(sc, RADEON_PIXCLKS_CNTL, 1708 1.5.6.2 rpaulo RADEON_PIX2CLK_SRC_SEL_CPUCLK, 1709 1.5.6.2 rpaulo ~RADEON_PIX2CLK_SRC_SEL_MASK); 1710 1.5.6.2 rpaulo 1711 1.5.6.2 rpaulo /* put vclk into reset, use atomic updates */ 1712 1.5.6.2 rpaulo SETPLL(sc, RADEON_P2PLL_CNTL, 1713 1.5.6.2 rpaulo RADEON_P2PLL_RESET | 1714 1.5.6.2 rpaulo RADEON_P2PLL_ATOMIC_UPDATE_EN | 1715 1.5.6.2 rpaulo RADEON_P2PLL_VGA_ATOMIC_UPDATE_EN); 1716 1.5.6.2 rpaulo 1717 1.5.6.2 rpaulo /* XXX: R300 family -- program divider differently? */ 1718 1.5.6.2 rpaulo 1719 1.5.6.2 rpaulo /* program reference divider */ 1720 1.5.6.2 rpaulo PATCHPLL(sc, RADEON_P2PLL_REF_DIV, sc->sc_refdiv, 1721 1.5.6.2 rpaulo ~RADEON_P2PLL_REF_DIV_MASK); 1722 1.5.6.2 rpaulo 1723 1.5.6.2 rpaulo /* program feedback and post dividers */ 1724 1.5.6.2 rpaulo data = GETPLL(sc, RADEON_P2PLL_DIV_0); 1725 1.5.6.2 rpaulo data &= ~(RADEON_P2PLL_FB0_DIV_MASK | 1726 1.5.6.2 rpaulo RADEON_P2PLL_POST0_DIV_MASK); 1727 1.5.6.2 rpaulo data |= pbit; 1728 1.5.6.2 rpaulo data |= (feed & RADEON_P2PLL_FB0_DIV_MASK); 1729 1.5.6.2 rpaulo PUTPLL(sc, RADEON_P2PLL_DIV_0, data); 1730 1.5.6.2 rpaulo 1731 1.5.6.2 rpaulo /* use the atomic update */ 1732 1.5.6.2 rpaulo radeonfb_pllwriteupdate(sc, crtc); 1733 1.5.6.2 rpaulo 1734 1.5.6.2 rpaulo /* and wait for it to complete */ 1735 1.5.6.2 rpaulo radeonfb_pllwaitatomicread(sc, crtc); 1736 1.5.6.2 rpaulo 1737 1.5.6.2 rpaulo /* program HTOTAL (why?) */ 1738 1.5.6.2 rpaulo PUTPLL(sc, RADEON_HTOTAL2_CNTL, 0); 1739 1.5.6.2 rpaulo 1740 1.5.6.2 rpaulo /* drop reset */ 1741 1.5.6.2 rpaulo CLRPLL(sc, RADEON_P2PLL_CNTL, 1742 1.5.6.2 rpaulo RADEON_P2PLL_RESET | RADEON_P2PLL_SLEEP | 1743 1.5.6.2 rpaulo RADEON_P2PLL_ATOMIC_UPDATE_EN | 1744 1.5.6.2 rpaulo RADEON_P2PLL_VGA_ATOMIC_UPDATE_EN); 1745 1.5.6.2 rpaulo 1746 1.5.6.2 rpaulo /* allow time for clock to lock */ 1747 1.5.6.2 rpaulo delay(50000); 1748 1.5.6.2 rpaulo 1749 1.5.6.2 rpaulo PATCHPLL(sc, RADEON_PIXCLKS_CNTL, 1750 1.5.6.2 rpaulo RADEON_PIX2CLK_SRC_SEL_P2PLLCLK, 1751 1.5.6.2 rpaulo ~RADEON_PIX2CLK_SRC_SEL_MASK); 1752 1.5.6.2 rpaulo } 1753 1.5.6.2 rpaulo PRINTREG(RADEON_CRTC_MORE_CNTL); 1754 1.5.6.2 rpaulo } 1755 1.5.6.2 rpaulo 1756 1.5.6.2 rpaulo void 1757 1.5.6.2 rpaulo radeonfb_modeswitch(struct radeonfb_display *dp) 1758 1.5.6.2 rpaulo { 1759 1.5.6.2 rpaulo struct radeonfb_softc *sc = dp->rd_softc; 1760 1.5.6.2 rpaulo int i; 1761 1.5.6.2 rpaulo 1762 1.5.6.2 rpaulo /* blank the display while we switch modes */ 1763 1.5.6.2 rpaulo //radeonfb_blank(dp, 1); 1764 1.5.6.2 rpaulo 1765 1.5.6.2 rpaulo #if 0 1766 1.5.6.2 rpaulo SET32(sc, RADEON_CRTC_EXT_CNTL, 1767 1.5.6.2 rpaulo RADEON_CRTC_VSYNC_DIS | RADEON_CRTC_HSYNC_DIS | 1768 1.5.6.2 rpaulo RADEON_CRTC_DISPLAY_DIS /* | RADEON_CRTC_DISP_REQ_EN_B */); 1769 1.5.6.2 rpaulo #endif 1770 1.5.6.2 rpaulo 1771 1.5.6.2 rpaulo /* these registers might get in the way... */ 1772 1.5.6.2 rpaulo PUT32(sc, RADEON_OVR_CLR, 0); 1773 1.5.6.2 rpaulo PUT32(sc, RADEON_OVR_WID_LEFT_RIGHT, 0); 1774 1.5.6.2 rpaulo PUT32(sc, RADEON_OVR_WID_TOP_BOTTOM, 0); 1775 1.5.6.2 rpaulo PUT32(sc, RADEON_OV0_SCALE_CNTL, 0); 1776 1.5.6.2 rpaulo PUT32(sc, RADEON_SUBPIC_CNTL, 0); 1777 1.5.6.2 rpaulo PUT32(sc, RADEON_VIPH_CONTROL, 0); 1778 1.5.6.2 rpaulo PUT32(sc, RADEON_I2C_CNTL_1, 0); 1779 1.5.6.2 rpaulo PUT32(sc, RADEON_GEN_INT_CNTL, 0); 1780 1.5.6.2 rpaulo PUT32(sc, RADEON_CAP0_TRIG_CNTL, 0); 1781 1.5.6.2 rpaulo PUT32(sc, RADEON_CAP1_TRIG_CNTL, 0); 1782 1.5.6.2 rpaulo PUT32(sc, RADEON_SURFACE_CNTL, 0); 1783 1.5.6.2 rpaulo 1784 1.5.6.2 rpaulo for (i = 0; i < dp->rd_ncrtcs; i++) 1785 1.5.6.2 rpaulo radeonfb_setcrtc(dp, i); 1786 1.5.6.2 rpaulo 1787 1.5.6.2 rpaulo /* activate the display */ 1788 1.5.6.2 rpaulo //radeonfb_blank(dp, 0); 1789 1.5.6.2 rpaulo } 1790 1.5.6.2 rpaulo 1791 1.5.6.2 rpaulo void 1792 1.5.6.2 rpaulo radeonfb_setcrtc(struct radeonfb_display *dp, int index) 1793 1.5.6.2 rpaulo { 1794 1.5.6.2 rpaulo int crtc; 1795 1.5.6.2 rpaulo struct videomode *mode; 1796 1.5.6.2 rpaulo struct radeonfb_softc *sc; 1797 1.5.6.2 rpaulo struct radeonfb_crtc *cp; 1798 1.5.6.2 rpaulo uint32_t v; 1799 1.5.6.2 rpaulo uint32_t gencntl; 1800 1.5.6.2 rpaulo uint32_t htotaldisp; 1801 1.5.6.2 rpaulo uint32_t hsyncstrt; 1802 1.5.6.2 rpaulo uint32_t vtotaldisp; 1803 1.5.6.2 rpaulo uint32_t vsyncstrt; 1804 1.5.6.2 rpaulo uint32_t fphsyncstrt; 1805 1.5.6.2 rpaulo uint32_t fpvsyncstrt; 1806 1.5.6.2 rpaulo uint32_t fphtotaldisp; 1807 1.5.6.2 rpaulo uint32_t fpvtotaldisp; 1808 1.5.6.2 rpaulo uint32_t pitch; 1809 1.5.6.2 rpaulo 1810 1.5.6.2 rpaulo sc = dp->rd_softc; 1811 1.5.6.2 rpaulo cp = &dp->rd_crtcs[index]; 1812 1.5.6.2 rpaulo crtc = cp->rc_number; 1813 1.5.6.2 rpaulo mode = &cp->rc_videomode; 1814 1.5.6.2 rpaulo 1815 1.5.6.2 rpaulo #if 1 1816 1.5.6.2 rpaulo pitch = (((dp->rd_virtx * dp->rd_bpp) + ((dp->rd_bpp * 8) - 1)) / 1817 1.5.6.2 rpaulo (dp->rd_bpp * 8)); 1818 1.5.6.2 rpaulo #else 1819 1.5.6.2 rpaulo pitch = (((sc->sc_maxx * sc->sc_maxbpp) + ((sc->sc_maxbpp * 8) - 1)) / 1820 1.5.6.2 rpaulo (sc->sc_maxbpp * 8)); 1821 1.5.6.2 rpaulo #endif 1822 1.5.6.2 rpaulo //pitch = pitch | (pitch << 16); 1823 1.5.6.2 rpaulo 1824 1.5.6.2 rpaulo switch (crtc) { 1825 1.5.6.2 rpaulo case 0: 1826 1.5.6.2 rpaulo gencntl = RADEON_CRTC_GEN_CNTL; 1827 1.5.6.2 rpaulo htotaldisp = RADEON_CRTC_H_TOTAL_DISP; 1828 1.5.6.2 rpaulo hsyncstrt = RADEON_CRTC_H_SYNC_STRT_WID; 1829 1.5.6.2 rpaulo vtotaldisp = RADEON_CRTC_V_TOTAL_DISP; 1830 1.5.6.2 rpaulo vsyncstrt = RADEON_CRTC_V_SYNC_STRT_WID; 1831 1.5.6.2 rpaulo fpvsyncstrt = RADEON_FP_V_SYNC_STRT_WID; 1832 1.5.6.2 rpaulo fphsyncstrt = RADEON_FP_H_SYNC_STRT_WID; 1833 1.5.6.2 rpaulo fpvtotaldisp = RADEON_FP_CRTC_V_TOTAL_DISP; 1834 1.5.6.2 rpaulo fphtotaldisp = RADEON_FP_CRTC_H_TOTAL_DISP; 1835 1.5.6.2 rpaulo break; 1836 1.5.6.2 rpaulo case 1: 1837 1.5.6.2 rpaulo gencntl = RADEON_CRTC2_GEN_CNTL; 1838 1.5.6.2 rpaulo htotaldisp = RADEON_CRTC2_H_TOTAL_DISP; 1839 1.5.6.2 rpaulo hsyncstrt = RADEON_CRTC2_H_SYNC_STRT_WID; 1840 1.5.6.2 rpaulo vtotaldisp = RADEON_CRTC2_V_TOTAL_DISP; 1841 1.5.6.2 rpaulo vsyncstrt = RADEON_CRTC2_V_SYNC_STRT_WID; 1842 1.5.6.2 rpaulo fpvsyncstrt = RADEON_FP_V2_SYNC_STRT_WID; 1843 1.5.6.2 rpaulo fphsyncstrt = RADEON_FP_H2_SYNC_STRT_WID; 1844 1.5.6.2 rpaulo fpvtotaldisp = RADEON_FP_CRTC2_V_TOTAL_DISP; 1845 1.5.6.2 rpaulo fphtotaldisp = RADEON_FP_CRTC2_H_TOTAL_DISP; 1846 1.5.6.2 rpaulo break; 1847 1.5.6.2 rpaulo default: 1848 1.5.6.2 rpaulo panic("Bad CRTC!"); 1849 1.5.6.2 rpaulo break; 1850 1.5.6.2 rpaulo } 1851 1.5.6.2 rpaulo 1852 1.5.6.2 rpaulo /* 1853 1.5.6.2 rpaulo * CRTC_GEN_CNTL - depth, accelerator mode, etc. 1854 1.5.6.2 rpaulo */ 1855 1.5.6.2 rpaulo /* only bother with 32bpp and 8bpp */ 1856 1.5.6.2 rpaulo v = dp->rd_format << RADEON_CRTC_PIX_WIDTH_SHIFT; 1857 1.5.6.2 rpaulo 1858 1.5.6.2 rpaulo if (crtc == 1) { 1859 1.5.6.2 rpaulo v |= RADEON_CRTC2_CRT2_ON | RADEON_CRTC2_EN; 1860 1.5.6.2 rpaulo } else { 1861 1.5.6.2 rpaulo v |= RADEON_CRTC_EXT_DISP_EN | RADEON_CRTC_EN; 1862 1.5.6.2 rpaulo } 1863 1.5.6.2 rpaulo 1864 1.5.6.2 rpaulo if (mode->flags & VID_DBLSCAN) 1865 1.5.6.2 rpaulo v |= RADEON_CRTC2_DBL_SCAN_EN; 1866 1.5.6.2 rpaulo 1867 1.5.6.2 rpaulo if (mode->flags & VID_INTERLACE) 1868 1.5.6.2 rpaulo v |= RADEON_CRTC2_INTERLACE_EN; 1869 1.5.6.2 rpaulo 1870 1.5.6.2 rpaulo if (mode->flags & VID_CSYNC) { 1871 1.5.6.2 rpaulo v |= RADEON_CRTC2_CSYNC_EN; 1872 1.5.6.2 rpaulo if (crtc == 1) 1873 1.5.6.2 rpaulo v |= RADEON_CRTC2_VSYNC_TRISTAT; 1874 1.5.6.2 rpaulo } 1875 1.5.6.2 rpaulo 1876 1.5.6.2 rpaulo PUT32(sc, gencntl, v); 1877 1.5.6.2 rpaulo DPRINTF(("CRTC%s_GEN_CNTL = %08x\n", crtc ? "2" : "", v)); 1878 1.5.6.2 rpaulo 1879 1.5.6.2 rpaulo /* 1880 1.5.6.2 rpaulo * CRTC_EXT_CNTL - preserve disable flags, set ATI linear and EXT_CNT 1881 1.5.6.2 rpaulo */ 1882 1.5.6.2 rpaulo v = GET32(sc, RADEON_CRTC_EXT_CNTL); 1883 1.5.6.2 rpaulo if (crtc == 0) { 1884 1.5.6.2 rpaulo v &= (RADEON_CRTC_VSYNC_DIS | RADEON_CRTC_HSYNC_DIS | 1885 1.5.6.2 rpaulo RADEON_CRTC_DISPLAY_DIS); 1886 1.5.6.2 rpaulo v |= RADEON_XCRT_CNT_EN | RADEON_VGA_ATI_LINEAR; 1887 1.5.6.2 rpaulo if (mode->flags & VID_CSYNC) 1888 1.5.6.2 rpaulo v |= RADEON_CRTC_VSYNC_TRISTAT; 1889 1.5.6.2 rpaulo } 1890 1.5.6.2 rpaulo /* unconditional turn on CRT, in case first CRTC is DFP */ 1891 1.5.6.2 rpaulo v |= RADEON_CRTC_CRT_ON; 1892 1.5.6.2 rpaulo PUT32(sc, RADEON_CRTC_EXT_CNTL, v); 1893 1.5.6.2 rpaulo PRINTREG(RADEON_CRTC_EXT_CNTL); 1894 1.5.6.2 rpaulo 1895 1.5.6.2 rpaulo /* 1896 1.5.6.2 rpaulo * H_TOTAL_DISP 1897 1.5.6.2 rpaulo */ 1898 1.5.6.2 rpaulo v = ((mode->hdisplay / 8) - 1) << 16; 1899 1.5.6.2 rpaulo v |= (mode->htotal / 8) - 1; 1900 1.5.6.2 rpaulo PUT32(sc, htotaldisp, v); 1901 1.5.6.2 rpaulo DPRINTF(("CRTC%s_H_TOTAL_DISP = %08x\n", crtc ? "2" : "", v)); 1902 1.5.6.2 rpaulo PUT32(sc, fphtotaldisp, v); 1903 1.5.6.2 rpaulo DPRINTF(("FP_H%s_TOTAL_DISP = %08x\n", crtc ? "2" : "", v)); 1904 1.5.6.2 rpaulo 1905 1.5.6.2 rpaulo /* 1906 1.5.6.2 rpaulo * H_SYNC_STRT_WID 1907 1.5.6.2 rpaulo */ 1908 1.5.6.2 rpaulo v = (((mode->hsync_end - mode->hsync_start) / 8) << 16); 1909 1.5.6.2 rpaulo v |= mode->hsync_start; 1910 1.5.6.2 rpaulo if (mode->flags & VID_NHSYNC) 1911 1.5.6.2 rpaulo v |= RADEON_CRTC_H_SYNC_POL; 1912 1.5.6.2 rpaulo PUT32(sc, hsyncstrt, v); 1913 1.5.6.2 rpaulo DPRINTF(("CRTC%s_H_SYNC_STRT_WID = %08x\n", crtc ? "2" : "", v)); 1914 1.5.6.2 rpaulo PUT32(sc, fphsyncstrt, v); 1915 1.5.6.2 rpaulo DPRINTF(("FP_H%s_SYNC_STRT_WID = %08x\n", crtc ? "2" : "", v)); 1916 1.5.6.2 rpaulo 1917 1.5.6.2 rpaulo /* 1918 1.5.6.2 rpaulo * V_TOTAL_DISP 1919 1.5.6.2 rpaulo */ 1920 1.5.6.2 rpaulo v = ((mode->vdisplay - 1) << 16); 1921 1.5.6.2 rpaulo v |= (mode->vtotal - 1); 1922 1.5.6.2 rpaulo PUT32(sc, vtotaldisp, v); 1923 1.5.6.2 rpaulo DPRINTF(("CRTC%s_V_TOTAL_DISP = %08x\n", crtc ? "2" : "", v)); 1924 1.5.6.2 rpaulo PUT32(sc, fpvtotaldisp, v); 1925 1.5.6.2 rpaulo DPRINTF(("FP_V%s_TOTAL_DISP = %08x\n", crtc ? "2" : "", v)); 1926 1.5.6.2 rpaulo 1927 1.5.6.2 rpaulo /* 1928 1.5.6.2 rpaulo * V_SYNC_STRT_WID 1929 1.5.6.2 rpaulo */ 1930 1.5.6.2 rpaulo v = ((mode->vsync_end - mode->vsync_start) << 16); 1931 1.5.6.2 rpaulo v |= (mode->vsync_start - 1); 1932 1.5.6.2 rpaulo if (mode->flags & VID_NVSYNC) 1933 1.5.6.2 rpaulo v |= RADEON_CRTC_V_SYNC_POL; 1934 1.5.6.2 rpaulo PUT32(sc, vsyncstrt, v); 1935 1.5.6.2 rpaulo DPRINTF(("CRTC%s_V_SYNC_STRT_WID = %08x\n", crtc ? "2" : "", v)); 1936 1.5.6.2 rpaulo PUT32(sc, fpvsyncstrt, v); 1937 1.5.6.2 rpaulo DPRINTF(("FP_V%s_SYNC_STRT_WID = %08x\n", crtc ? "2" : "", v)); 1938 1.5.6.2 rpaulo 1939 1.5.6.2 rpaulo radeonfb_program_vclk(sc, mode->dot_clock, crtc); 1940 1.5.6.2 rpaulo 1941 1.5.6.2 rpaulo switch (crtc) { 1942 1.5.6.2 rpaulo case 0: 1943 1.5.6.2 rpaulo PUT32(sc, RADEON_CRTC_OFFSET, 0); 1944 1.5.6.2 rpaulo PUT32(sc, RADEON_CRTC_OFFSET_CNTL, 0); 1945 1.5.6.2 rpaulo PUT32(sc, RADEON_CRTC_PITCH, pitch); 1946 1.5.6.2 rpaulo CLR32(sc, RADEON_DISP_MERGE_CNTL, RADEON_DISP_RGB_OFFSET_EN); 1947 1.5.6.2 rpaulo 1948 1.5.6.2 rpaulo CLR32(sc, RADEON_CRTC_EXT_CNTL, 1949 1.5.6.2 rpaulo RADEON_CRTC_VSYNC_DIS | RADEON_CRTC_HSYNC_DIS | 1950 1.5.6.2 rpaulo RADEON_CRTC_DISPLAY_DIS /* | RADEON_CRTC_DISP_REQ_EN_B */); 1951 1.5.6.2 rpaulo CLR32(sc, RADEON_CRTC_GEN_CNTL, RADEON_CRTC_DISP_REQ_EN_B); 1952 1.5.6.2 rpaulo PRINTREG(RADEON_CRTC_EXT_CNTL); 1953 1.5.6.2 rpaulo PRINTREG(RADEON_CRTC_GEN_CNTL); 1954 1.5.6.2 rpaulo PRINTREG(RADEON_CLOCK_CNTL_INDEX); 1955 1.5.6.2 rpaulo break; 1956 1.5.6.2 rpaulo 1957 1.5.6.2 rpaulo case 1: 1958 1.5.6.2 rpaulo PUT32(sc, RADEON_CRTC2_OFFSET, 0); 1959 1.5.6.2 rpaulo PUT32(sc, RADEON_CRTC2_OFFSET_CNTL, 0); 1960 1.5.6.2 rpaulo PUT32(sc, RADEON_CRTC2_PITCH, pitch); 1961 1.5.6.2 rpaulo CLR32(sc, RADEON_DISP2_MERGE_CNTL, RADEON_DISP2_RGB_OFFSET_EN); 1962 1.5.6.2 rpaulo CLR32(sc, RADEON_CRTC2_GEN_CNTL, 1963 1.5.6.2 rpaulo RADEON_CRTC2_VSYNC_DIS | 1964 1.5.6.2 rpaulo RADEON_CRTC2_HSYNC_DIS | 1965 1.5.6.2 rpaulo RADEON_CRTC2_DISP_DIS | RADEON_CRTC2_DISP_REQ_EN_B); 1966 1.5.6.2 rpaulo PRINTREG(RADEON_CRTC2_GEN_CNTL); 1967 1.5.6.2 rpaulo break; 1968 1.5.6.2 rpaulo } 1969 1.5.6.2 rpaulo } 1970 1.5.6.2 rpaulo 1971 1.5.6.2 rpaulo int 1972 1.5.6.2 rpaulo radeonfb_isblank(struct radeonfb_display *dp) 1973 1.5.6.2 rpaulo { 1974 1.5.6.2 rpaulo uint32_t reg, mask; 1975 1.5.6.2 rpaulo 1976 1.5.6.2 rpaulo if (dp->rd_crtcs[0].rc_number) { 1977 1.5.6.2 rpaulo reg = RADEON_CRTC2_GEN_CNTL; 1978 1.5.6.2 rpaulo mask = RADEON_CRTC2_DISP_DIS; 1979 1.5.6.2 rpaulo } else { 1980 1.5.6.2 rpaulo reg = RADEON_CRTC_EXT_CNTL; 1981 1.5.6.2 rpaulo mask = RADEON_CRTC_DISPLAY_DIS; 1982 1.5.6.2 rpaulo } 1983 1.5.6.2 rpaulo return ((GET32(dp->rd_softc, reg) & mask) ? 1 : 0); 1984 1.5.6.2 rpaulo } 1985 1.5.6.2 rpaulo 1986 1.5.6.2 rpaulo void 1987 1.5.6.2 rpaulo radeonfb_blank(struct radeonfb_display *dp, int blank) 1988 1.5.6.2 rpaulo { 1989 1.5.6.2 rpaulo struct radeonfb_softc *sc = dp->rd_softc; 1990 1.5.6.2 rpaulo uint32_t reg, mask; 1991 1.5.6.2 rpaulo uint32_t fpreg, fpval; 1992 1.5.6.2 rpaulo int i; 1993 1.5.6.2 rpaulo 1994 1.5.6.2 rpaulo for (i = 0; i < dp->rd_ncrtcs; i++) { 1995 1.5.6.2 rpaulo 1996 1.5.6.2 rpaulo if (dp->rd_crtcs[i].rc_number) { 1997 1.5.6.2 rpaulo reg = RADEON_CRTC2_GEN_CNTL; 1998 1.5.6.2 rpaulo mask = RADEON_CRTC2_DISP_DIS; 1999 1.5.6.2 rpaulo fpreg = RADEON_FP2_GEN_CNTL; 2000 1.5.6.2 rpaulo fpval = RADEON_FP2_ON; 2001 1.5.6.2 rpaulo } else { 2002 1.5.6.2 rpaulo reg = RADEON_CRTC_EXT_CNTL; 2003 1.5.6.2 rpaulo mask = RADEON_CRTC_DISPLAY_DIS; 2004 1.5.6.2 rpaulo fpreg = RADEON_FP_GEN_CNTL; 2005 1.5.6.2 rpaulo fpval = RADEON_FP_FPON; 2006 1.5.6.2 rpaulo } 2007 1.5.6.2 rpaulo 2008 1.5.6.2 rpaulo if (blank) { 2009 1.5.6.2 rpaulo SET32(sc, reg, mask); 2010 1.5.6.2 rpaulo CLR32(sc, fpreg, fpval); 2011 1.5.6.2 rpaulo } else { 2012 1.5.6.2 rpaulo CLR32(sc, reg, mask); 2013 1.5.6.2 rpaulo SET32(sc, fpreg, fpval); 2014 1.5.6.2 rpaulo } 2015 1.5.6.2 rpaulo } 2016 1.5.6.2 rpaulo PRINTREG(RADEON_FP_GEN_CNTL); 2017 1.5.6.2 rpaulo PRINTREG(RADEON_FP2_GEN_CNTL); 2018 1.5.6.2 rpaulo } 2019 1.5.6.2 rpaulo 2020 1.5.6.2 rpaulo void 2021 1.5.6.2 rpaulo radeonfb_init_screen(void *cookie, struct vcons_screen *scr, int existing, 2022 1.5.6.2 rpaulo long *defattr) 2023 1.5.6.2 rpaulo { 2024 1.5.6.2 rpaulo struct radeonfb_display *dp = cookie; 2025 1.5.6.2 rpaulo struct rasops_info *ri = &scr->scr_ri; 2026 1.5.6.2 rpaulo 2027 1.5.6.2 rpaulo /* initialize font subsystem */ 2028 1.5.6.2 rpaulo wsfont_init(); 2029 1.5.6.2 rpaulo 2030 1.5.6.2 rpaulo DPRINTF(("init screen called, existing %d\n", existing)); 2031 1.5.6.2 rpaulo 2032 1.5.6.2 rpaulo ri->ri_depth = dp->rd_bpp; 2033 1.5.6.2 rpaulo ri->ri_width = dp->rd_virtx; 2034 1.5.6.2 rpaulo ri->ri_height = dp->rd_virty; 2035 1.5.6.2 rpaulo ri->ri_stride = dp->rd_stride; 2036 1.5.6.2 rpaulo ri->ri_flg = RI_CENTER; 2037 1.5.6.2 rpaulo ri->ri_bits = (void *)dp->rd_fbptr; 2038 1.5.6.2 rpaulo 2039 1.5.6.2 rpaulo /* XXX: 32 bpp only */ 2040 1.5.6.2 rpaulo /* this is rgb in "big-endian order..." */ 2041 1.5.6.2 rpaulo ri->ri_rnum = 8; 2042 1.5.6.2 rpaulo ri->ri_gnum = 8; 2043 1.5.6.2 rpaulo ri->ri_bnum = 8; 2044 1.5.6.2 rpaulo ri->ri_rpos = 16; 2045 1.5.6.2 rpaulo ri->ri_gpos = 8; 2046 1.5.6.2 rpaulo ri->ri_bpos = 0; 2047 1.5.6.2 rpaulo 2048 1.5.6.2 rpaulo if (existing) { 2049 1.5.6.2 rpaulo ri->ri_flg |= RI_CLEAR; 2050 1.5.6.2 rpaulo 2051 1.5.6.2 rpaulo /* start a modeswitch now */ 2052 1.5.6.2 rpaulo radeonfb_modeswitch(dp); 2053 1.5.6.2 rpaulo } 2054 1.5.6.2 rpaulo 2055 1.5.6.2 rpaulo /* 2056 1.5.6.2 rpaulo * XXX: font selection should be based on properties, with some 2057 1.5.6.2 rpaulo * normal/reasonable default. 2058 1.5.6.2 rpaulo */ 2059 1.5.6.2 rpaulo ri->ri_caps = WSSCREEN_WSCOLORS; 2060 1.5.6.2 rpaulo 2061 1.5.6.2 rpaulo /* initialize and look for an initial font */ 2062 1.5.6.2 rpaulo rasops_init(ri, dp->rd_virty/8, dp->rd_virtx/8); 2063 1.5.6.2 rpaulo 2064 1.5.6.2 rpaulo rasops_reconfig(ri, dp->rd_virty / ri->ri_font->fontheight, 2065 1.5.6.2 rpaulo dp->rd_virtx / ri->ri_font->fontwidth); 2066 1.5.6.2 rpaulo 2067 1.5.6.2 rpaulo /* enable acceleration */ 2068 1.5.6.2 rpaulo ri->ri_ops.copyrows = radeonfb_copyrows; 2069 1.5.6.2 rpaulo ri->ri_ops.copycols = radeonfb_copycols; 2070 1.5.6.2 rpaulo ri->ri_ops.eraserows = radeonfb_eraserows; 2071 1.5.6.2 rpaulo ri->ri_ops.erasecols = radeonfb_erasecols; 2072 1.5.6.2 rpaulo ri->ri_ops.allocattr = radeonfb_allocattr; 2073 1.5.6.2 rpaulo ri->ri_ops.putchar = radeonfb_putchar; 2074 1.5.6.2 rpaulo ri->ri_ops.cursor = radeonfb_cursor; 2075 1.5.6.2 rpaulo } 2076 1.5.6.2 rpaulo 2077 1.5.6.2 rpaulo void 2078 1.5.6.2 rpaulo radeonfb_set_fbloc(struct radeonfb_softc *sc) 2079 1.5.6.2 rpaulo { 2080 1.5.6.2 rpaulo uint32_t gen, ext, gen2 = 0; 2081 1.5.6.2 rpaulo uint32_t agploc, aperbase, apersize, mcfbloc; 2082 1.5.6.2 rpaulo 2083 1.5.6.2 rpaulo gen = GET32(sc, RADEON_CRTC_GEN_CNTL); 2084 1.5.6.2 rpaulo ext = GET32(sc, RADEON_CRTC_EXT_CNTL); 2085 1.5.6.2 rpaulo agploc = GET32(sc, RADEON_MC_AGP_LOCATION); 2086 1.5.6.2 rpaulo aperbase = GET32(sc, RADEON_CONFIG_APER_0_BASE); 2087 1.5.6.2 rpaulo apersize = GET32(sc, RADEON_CONFIG_APER_SIZE); 2088 1.5.6.2 rpaulo 2089 1.5.6.2 rpaulo PUT32(sc, RADEON_CRTC_GEN_CNTL, gen | RADEON_CRTC_DISP_REQ_EN_B); 2090 1.5.6.2 rpaulo PUT32(sc, RADEON_CRTC_EXT_CNTL, ext | RADEON_CRTC_DISPLAY_DIS); 2091 1.5.6.2 rpaulo //PUT32(sc, RADEON_CRTC_GEN_CNTL, gen | RADEON_CRTC_DISPLAY_DIS); 2092 1.5.6.2 rpaulo //PUT32(sc, RADEON_CRTC_EXT_CNTL, ext | RADEON_CRTC_DISP_REQ_EN_B); 2093 1.5.6.2 rpaulo 2094 1.5.6.2 rpaulo if (HAS_CRTC2(sc)) { 2095 1.5.6.2 rpaulo gen2 = GET32(sc, RADEON_CRTC2_GEN_CNTL); 2096 1.5.6.2 rpaulo PUT32(sc, RADEON_CRTC2_GEN_CNTL, 2097 1.5.6.2 rpaulo gen2 | RADEON_CRTC2_DISP_REQ_EN_B); 2098 1.5.6.2 rpaulo } 2099 1.5.6.2 rpaulo 2100 1.5.6.2 rpaulo delay(100000); 2101 1.5.6.2 rpaulo 2102 1.5.6.2 rpaulo mcfbloc = (aperbase >> 16) | 2103 1.5.6.2 rpaulo ((aperbase + (apersize - 1)) & 0xffff0000); 2104 1.5.6.2 rpaulo 2105 1.5.6.2 rpaulo sc->sc_aperbase = (mcfbloc & 0xffff) << 16; 2106 1.5.6.2 rpaulo sc->sc_memsz = apersize; 2107 1.5.6.2 rpaulo 2108 1.5.6.2 rpaulo if (((agploc & 0xffff) << 16) != 2109 1.5.6.2 rpaulo ((mcfbloc & 0xffff0000U) + 0x10000)) { 2110 1.5.6.2 rpaulo agploc = mcfbloc & 0xffff0000U; 2111 1.5.6.2 rpaulo agploc |= ((agploc + 0x10000) >> 16); 2112 1.5.6.2 rpaulo } 2113 1.5.6.2 rpaulo 2114 1.5.6.2 rpaulo PUT32(sc, RADEON_HOST_PATH_CNTL, 0); 2115 1.5.6.2 rpaulo 2116 1.5.6.2 rpaulo PUT32(sc, RADEON_MC_FB_LOCATION, mcfbloc); 2117 1.5.6.2 rpaulo PUT32(sc, RADEON_MC_AGP_LOCATION, agploc); 2118 1.5.6.2 rpaulo 2119 1.5.6.2 rpaulo DPRINTF(("aperbase = %u\n", aperbase)); 2120 1.5.6.2 rpaulo PRINTREG(RADEON_MC_FB_LOCATION); 2121 1.5.6.2 rpaulo PRINTREG(RADEON_MC_AGP_LOCATION); 2122 1.5.6.2 rpaulo 2123 1.5.6.2 rpaulo PUT32(sc, RADEON_DISPLAY_BASE_ADDR, sc->sc_aperbase); 2124 1.5.6.2 rpaulo 2125 1.5.6.2 rpaulo if (HAS_CRTC2(sc)) 2126 1.5.6.2 rpaulo PUT32(sc, RADEON_DISPLAY2_BASE_ADDR, sc->sc_aperbase); 2127 1.5.6.2 rpaulo 2128 1.5.6.2 rpaulo PUT32(sc, RADEON_OV0_BASE_ADDR, sc->sc_aperbase); 2129 1.5.6.2 rpaulo 2130 1.5.6.2 rpaulo #if 0 2131 1.5.6.2 rpaulo /* XXX: what is this AGP garbage? :-) */ 2132 1.5.6.2 rpaulo PUT32(sc, RADEON_AGP_CNTL, 0x00100000); 2133 1.5.6.2 rpaulo #endif 2134 1.5.6.2 rpaulo 2135 1.5.6.2 rpaulo delay(100000); 2136 1.5.6.2 rpaulo 2137 1.5.6.2 rpaulo PUT32(sc, RADEON_CRTC_GEN_CNTL, gen); 2138 1.5.6.2 rpaulo PUT32(sc, RADEON_CRTC_EXT_CNTL, ext); 2139 1.5.6.2 rpaulo 2140 1.5.6.2 rpaulo if (HAS_CRTC2(sc)) 2141 1.5.6.2 rpaulo PUT32(sc, RADEON_CRTC2_GEN_CNTL, gen2); 2142 1.5.6.2 rpaulo } 2143 1.5.6.2 rpaulo 2144 1.5.6.2 rpaulo void 2145 1.5.6.2 rpaulo radeonfb_init_misc(struct radeonfb_softc *sc) 2146 1.5.6.2 rpaulo { 2147 1.5.6.2 rpaulo PUT32(sc, RADEON_BUS_CNTL, 2148 1.5.6.2 rpaulo RADEON_BUS_MASTER_DIS | 2149 1.5.6.2 rpaulo RADEON_BUS_PREFETCH_MODE_ACT | 2150 1.5.6.2 rpaulo RADEON_BUS_PCI_READ_RETRY_EN | 2151 1.5.6.2 rpaulo RADEON_BUS_PCI_WRT_RETRY_EN | 2152 1.5.6.2 rpaulo (3 << RADEON_BUS_RETRY_WS_SHIFT) | 2153 1.5.6.2 rpaulo RADEON_BUS_MSTR_RD_MULT | 2154 1.5.6.2 rpaulo RADEON_BUS_MSTR_RD_LINE | 2155 1.5.6.2 rpaulo RADEON_BUS_RD_DISCARD_EN | 2156 1.5.6.2 rpaulo RADEON_BUS_MSTR_DISCONNECT_EN | 2157 1.5.6.2 rpaulo RADEON_BUS_READ_BURST); 2158 1.5.6.2 rpaulo 2159 1.5.6.2 rpaulo PUT32(sc, RADEON_BUS_CNTL1, 0xf0); 2160 1.5.6.2 rpaulo /* PUT32(sc, RADEON_SEPROM_CNTL1, 0x09ff0000); */ 2161 1.5.6.2 rpaulo PUT32(sc, RADEON_FCP_CNTL, RADEON_FCP0_SRC_GND); 2162 1.5.6.2 rpaulo PUT32(sc, RADEON_RBBM_CNTL, 2163 1.5.6.2 rpaulo (3 << RADEON_RB_SETTLE_SHIFT) | 2164 1.5.6.2 rpaulo (4 << RADEON_ABORTCLKS_HI_SHIFT) | 2165 1.5.6.2 rpaulo (4 << RADEON_ABORTCLKS_CP_SHIFT) | 2166 1.5.6.2 rpaulo (4 << RADEON_ABORTCLKS_CFIFO_SHIFT)); 2167 1.5.6.2 rpaulo 2168 1.5.6.2 rpaulo /* XXX: figure out what these mean! */ 2169 1.5.6.2 rpaulo PUT32(sc, RADEON_AGP_CNTL, 0x00100000); 2170 1.5.6.2 rpaulo PUT32(sc, RADEON_HOST_PATH_CNTL, 0); 2171 1.5.6.2 rpaulo //PUT32(sc, RADEON_DISP_MISC_CNTL, 0x5bb00400); 2172 1.5.6.2 rpaulo 2173 1.5.6.2 rpaulo PUT32(sc, RADEON_GEN_INT_CNTL, 0); 2174 1.5.6.2 rpaulo PUT32(sc, RADEON_GEN_INT_STATUS, GET32(sc, RADEON_GEN_INT_STATUS)); 2175 1.5.6.2 rpaulo } 2176 1.5.6.2 rpaulo 2177 1.5.6.2 rpaulo /* 2178 1.5.6.2 rpaulo * This loads a linear color map for true color. 2179 1.5.6.2 rpaulo */ 2180 1.5.6.2 rpaulo void 2181 1.5.6.2 rpaulo radeonfb_init_palette(struct radeonfb_softc *sc, int crtc) 2182 1.5.6.2 rpaulo { 2183 1.5.6.2 rpaulo int i; 2184 1.5.6.2 rpaulo uint32_t vclk; 2185 1.5.6.2 rpaulo 2186 1.5.6.2 rpaulo #define DAC_WIDTH ((1 << 10) - 1) 2187 1.5.6.2 rpaulo #define CLUT_WIDTH ((1 << 8) - 1) 2188 1.5.6.2 rpaulo #define CLUT_COLOR(i) ((i * DAC_WIDTH * 2 / CLUT_WIDTH + 1) / 2) 2189 1.5.6.2 rpaulo 2190 1.5.6.2 rpaulo vclk = GETPLL(sc, RADEON_VCLK_ECP_CNTL); 2191 1.5.6.2 rpaulo PUTPLL(sc, RADEON_VCLK_ECP_CNTL, vclk & ~RADEON_PIXCLK_DAC_ALWAYS_ONb); 2192 1.5.6.2 rpaulo 2193 1.5.6.2 rpaulo if (crtc) 2194 1.5.6.2 rpaulo SET32(sc, RADEON_DAC_CNTL2, RADEON_DAC2_PALETTE_ACC_CTL); 2195 1.5.6.2 rpaulo else 2196 1.5.6.2 rpaulo CLR32(sc, RADEON_DAC_CNTL2, RADEON_DAC2_PALETTE_ACC_CTL); 2197 1.5.6.2 rpaulo 2198 1.5.6.2 rpaulo PUT32(sc, RADEON_PALETTE_INDEX, 0); 2199 1.5.6.2 rpaulo for (i = 0; i <= CLUT_WIDTH; ++i) { 2200 1.5.6.2 rpaulo PUT32(sc, RADEON_PALETTE_30_DATA, 2201 1.5.6.2 rpaulo (CLUT_COLOR(i) << 10) | 2202 1.5.6.2 rpaulo (CLUT_COLOR(i) << 20) | 2203 1.5.6.2 rpaulo (CLUT_COLOR(i))); 2204 1.5.6.2 rpaulo } 2205 1.5.6.2 rpaulo 2206 1.5.6.2 rpaulo CLR32(sc, RADEON_DAC_CNTL2, RADEON_DAC2_PALETTE_ACC_CTL); 2207 1.5.6.2 rpaulo PRINTREG(RADEON_DAC_CNTL2); 2208 1.5.6.2 rpaulo 2209 1.5.6.2 rpaulo PUTPLL(sc, RADEON_VCLK_ECP_CNTL, vclk); 2210 1.5.6.2 rpaulo } 2211 1.5.6.2 rpaulo 2212 1.5.6.2 rpaulo /* 2213 1.5.6.2 rpaulo * Bugs in some R300 hardware requires this when accessing CLOCK_CNTL_INDEX. 2214 1.5.6.2 rpaulo */ 2215 1.5.6.2 rpaulo void 2216 1.5.6.2 rpaulo radeonfb_r300cg_workaround(struct radeonfb_softc *sc) 2217 1.5.6.2 rpaulo { 2218 1.5.6.2 rpaulo uint32_t tmp, save; 2219 1.5.6.2 rpaulo 2220 1.5.6.2 rpaulo save = GET32(sc, RADEON_CLOCK_CNTL_INDEX); 2221 1.5.6.2 rpaulo tmp = save & ~(0x3f | RADEON_PLL_WR_EN); 2222 1.5.6.2 rpaulo PUT32(sc, RADEON_CLOCK_CNTL_INDEX, tmp); 2223 1.5.6.2 rpaulo tmp = GET32(sc, RADEON_CLOCK_CNTL_DATA); 2224 1.5.6.2 rpaulo PUT32(sc, RADEON_CLOCK_CNTL_INDEX, save); 2225 1.5.6.2 rpaulo } 2226 1.5.6.2 rpaulo 2227 1.5.6.2 rpaulo /* 2228 1.5.6.2 rpaulo * Acceleration entry points. 2229 1.5.6.2 rpaulo */ 2230 1.5.6.2 rpaulo static void 2231 1.5.6.2 rpaulo radeonfb_putchar(void *cookie, int row, int col, u_int c, long attr) 2232 1.5.6.2 rpaulo { 2233 1.5.6.2 rpaulo struct rasops_info *ri = cookie; 2234 1.5.6.2 rpaulo struct vcons_screen *scr = ri->ri_hw; 2235 1.5.6.2 rpaulo struct radeonfb_display *dp = scr->scr_cookie; 2236 1.5.6.2 rpaulo uint32_t x, y, w, h; 2237 1.5.6.2 rpaulo uint32_t bg, fg; 2238 1.5.6.2 rpaulo uint8_t *data; 2239 1.5.6.2 rpaulo 2240 1.5.6.2 rpaulo if (dp->rd_wsmode != WSDISPLAYIO_MODE_EMUL) 2241 1.5.6.2 rpaulo return; 2242 1.5.6.2 rpaulo 2243 1.5.6.2 rpaulo if (!CHAR_IN_FONT(c, ri->ri_font)) 2244 1.5.6.2 rpaulo return; 2245 1.5.6.2 rpaulo 2246 1.5.6.2 rpaulo w = ri->ri_font->fontwidth; 2247 1.5.6.2 rpaulo h = ri->ri_font->fontheight; 2248 1.5.6.2 rpaulo 2249 1.5.6.2 rpaulo bg = ri->ri_devcmap[(attr >> 16) & 0xf]; 2250 1.5.6.2 rpaulo fg = ri->ri_devcmap[(attr >> 24) & 0xf]; 2251 1.5.6.2 rpaulo 2252 1.5.6.2 rpaulo x = ri->ri_xorigin + col * w; 2253 1.5.6.2 rpaulo y = ri->ri_yorigin + row * h; 2254 1.5.6.2 rpaulo 2255 1.5.6.2 rpaulo if (c == 0x20) { 2256 1.5.6.2 rpaulo radeonfb_rectfill(dp, x, y, w, h, bg); 2257 1.5.6.2 rpaulo } else { 2258 1.5.6.2 rpaulo data = (uint8_t *)ri->ri_font->data + 2259 1.5.6.2 rpaulo (c - ri->ri_font->firstchar) * ri->ri_fontscale; 2260 1.5.6.2 rpaulo 2261 1.5.6.2 rpaulo radeonfb_setup_mono(dp, x, y, w, h, fg, bg); 2262 1.5.6.2 rpaulo radeonfb_feed_bytes(dp, ri->ri_fontscale, data); 2263 1.5.6.2 rpaulo } 2264 1.5.6.2 rpaulo } 2265 1.5.6.2 rpaulo 2266 1.5.6.2 rpaulo static void 2267 1.5.6.2 rpaulo radeonfb_eraserows(void *cookie, int row, int nrows, long fillattr) 2268 1.5.6.2 rpaulo { 2269 1.5.6.2 rpaulo struct rasops_info *ri = cookie; 2270 1.5.6.2 rpaulo struct vcons_screen *scr = ri->ri_hw; 2271 1.5.6.2 rpaulo struct radeonfb_display *dp = scr->scr_cookie; 2272 1.5.6.2 rpaulo uint32_t x, y, w, h, fg, bg, ul; 2273 1.5.6.2 rpaulo 2274 1.5.6.2 rpaulo /* XXX: check for full emulation mode? */ 2275 1.5.6.2 rpaulo if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 2276 1.5.6.2 rpaulo x = ri->ri_xorigin; 2277 1.5.6.2 rpaulo y = ri->ri_yorigin + ri->ri_font->fontheight * row; 2278 1.5.6.2 rpaulo w = ri->ri_emuwidth; 2279 1.5.6.2 rpaulo h = ri->ri_font->fontheight * nrows; 2280 1.5.6.2 rpaulo 2281 1.5.6.2 rpaulo rasops_unpack_attr(fillattr, &fg, &bg, &ul); 2282 1.5.6.2 rpaulo radeonfb_rectfill(dp, x, y, w, h, ri->ri_devcmap[bg & 0xf]); 2283 1.5.6.2 rpaulo } 2284 1.5.6.2 rpaulo } 2285 1.5.6.2 rpaulo 2286 1.5.6.2 rpaulo static void 2287 1.5.6.2 rpaulo radeonfb_copyrows(void *cookie, int srcrow, int dstrow, int nrows) 2288 1.5.6.2 rpaulo { 2289 1.5.6.2 rpaulo struct rasops_info *ri = cookie; 2290 1.5.6.2 rpaulo struct vcons_screen *scr = ri->ri_hw; 2291 1.5.6.2 rpaulo struct radeonfb_display *dp = scr->scr_cookie; 2292 1.5.6.2 rpaulo uint32_t x, ys, yd, w, h; 2293 1.5.6.2 rpaulo 2294 1.5.6.2 rpaulo if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 2295 1.5.6.2 rpaulo x = ri->ri_xorigin; 2296 1.5.6.2 rpaulo ys = ri->ri_yorigin + ri->ri_font->fontheight * srcrow; 2297 1.5.6.2 rpaulo yd = ri->ri_yorigin + ri->ri_font->fontheight * dstrow; 2298 1.5.6.2 rpaulo w = ri->ri_emuwidth; 2299 1.5.6.2 rpaulo h = ri->ri_font->fontheight * nrows; 2300 1.5.6.2 rpaulo radeonfb_bitblt(dp, x, ys, x, yd, w, h, 2301 1.5.6.2 rpaulo RADEON_ROP3_S, 0xffffffff); 2302 1.5.6.2 rpaulo } 2303 1.5.6.2 rpaulo } 2304 1.5.6.2 rpaulo 2305 1.5.6.2 rpaulo static void 2306 1.5.6.2 rpaulo radeonfb_copycols(void *cookie, int row, int srccol, int dstcol, int ncols) 2307 1.5.6.2 rpaulo { 2308 1.5.6.2 rpaulo struct rasops_info *ri = cookie; 2309 1.5.6.2 rpaulo struct vcons_screen *scr = ri->ri_hw; 2310 1.5.6.2 rpaulo struct radeonfb_display *dp = scr->scr_cookie; 2311 1.5.6.2 rpaulo uint32_t xs, xd, y, w, h; 2312 1.5.6.2 rpaulo 2313 1.5.6.2 rpaulo if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 2314 1.5.6.2 rpaulo xs = ri->ri_xorigin + ri->ri_font->fontwidth * srccol; 2315 1.5.6.2 rpaulo xd = ri->ri_xorigin + ri->ri_font->fontwidth * dstcol; 2316 1.5.6.2 rpaulo y = ri->ri_yorigin + ri->ri_font->fontheight * row; 2317 1.5.6.2 rpaulo w = ri->ri_font->fontwidth * ncols; 2318 1.5.6.2 rpaulo h = ri->ri_font->fontheight; 2319 1.5.6.2 rpaulo radeonfb_bitblt(dp, xs, y, xd, y, w, h, 2320 1.5.6.2 rpaulo RADEON_ROP3_S, 0xffffffff); 2321 1.5.6.2 rpaulo } 2322 1.5.6.2 rpaulo } 2323 1.5.6.2 rpaulo 2324 1.5.6.2 rpaulo static void 2325 1.5.6.2 rpaulo radeonfb_erasecols(void *cookie, int row, int startcol, int ncols, 2326 1.5.6.2 rpaulo long fillattr) 2327 1.5.6.2 rpaulo { 2328 1.5.6.2 rpaulo struct rasops_info *ri = cookie; 2329 1.5.6.2 rpaulo struct vcons_screen *scr = ri->ri_hw; 2330 1.5.6.2 rpaulo struct radeonfb_display *dp = scr->scr_cookie; 2331 1.5.6.2 rpaulo uint32_t x, y, w, h, fg, bg, ul; 2332 1.5.6.2 rpaulo 2333 1.5.6.2 rpaulo if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 2334 1.5.6.2 rpaulo x = ri->ri_xorigin + ri->ri_font->fontwidth * startcol; 2335 1.5.6.2 rpaulo y = ri->ri_yorigin + ri->ri_font->fontheight * row; 2336 1.5.6.2 rpaulo w = ri->ri_font->fontwidth * ncols; 2337 1.5.6.2 rpaulo h = ri->ri_font->fontheight; 2338 1.5.6.2 rpaulo 2339 1.5.6.2 rpaulo rasops_unpack_attr(fillattr, &fg, &bg, &ul); 2340 1.5.6.2 rpaulo radeonfb_rectfill(dp, x, y, w, h, ri->ri_devcmap[bg & 0xf]); 2341 1.5.6.2 rpaulo } 2342 1.5.6.2 rpaulo } 2343 1.5.6.2 rpaulo 2344 1.5.6.2 rpaulo static void 2345 1.5.6.2 rpaulo radeonfb_cursor(void *cookie, int on, int row, int col) 2346 1.5.6.2 rpaulo { 2347 1.5.6.2 rpaulo struct rasops_info *ri = cookie; 2348 1.5.6.2 rpaulo struct vcons_screen *scr = ri->ri_hw; 2349 1.5.6.2 rpaulo struct radeonfb_display *dp = scr->scr_cookie; 2350 1.5.6.2 rpaulo int x, y, wi, he; 2351 1.5.6.2 rpaulo 2352 1.5.6.2 rpaulo wi = ri->ri_font->fontwidth; 2353 1.5.6.2 rpaulo he = ri->ri_font->fontheight; 2354 1.5.6.2 rpaulo 2355 1.5.6.2 rpaulo if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 2356 1.5.6.2 rpaulo x = ri->ri_ccol * wi + ri->ri_xorigin; 2357 1.5.6.2 rpaulo y = ri->ri_crow * he + ri->ri_yorigin; 2358 1.5.6.2 rpaulo /* first turn off the old cursor */ 2359 1.5.6.2 rpaulo if (ri->ri_flg & RI_CURSOR) { 2360 1.5.6.2 rpaulo radeonfb_bitblt(dp, x, y, x, y, wi, he, 2361 1.5.6.2 rpaulo RADEON_ROP3_Dn, 0xffffffff); 2362 1.5.6.2 rpaulo ri->ri_flg &= ~RI_CURSOR; 2363 1.5.6.2 rpaulo } 2364 1.5.6.2 rpaulo ri->ri_crow = row; 2365 1.5.6.2 rpaulo ri->ri_ccol = col; 2366 1.5.6.2 rpaulo /* then (possibly) turn on the new one */ 2367 1.5.6.2 rpaulo if (on) { 2368 1.5.6.2 rpaulo x = ri->ri_ccol * wi + ri->ri_xorigin; 2369 1.5.6.2 rpaulo y = ri->ri_crow * he + ri->ri_yorigin; 2370 1.5.6.2 rpaulo radeonfb_bitblt(dp, x, y, x, y, wi, he, 2371 1.5.6.2 rpaulo RADEON_ROP3_Dn, 0xffffffff); 2372 1.5.6.2 rpaulo ri->ri_flg |= RI_CURSOR; 2373 1.5.6.2 rpaulo } 2374 1.5.6.2 rpaulo } else { 2375 1.5.6.2 rpaulo scr->scr_ri.ri_crow = row; 2376 1.5.6.2 rpaulo scr->scr_ri.ri_ccol = col; 2377 1.5.6.2 rpaulo scr->scr_ri.ri_flg &= ~RI_CURSOR; 2378 1.5.6.2 rpaulo } 2379 1.5.6.2 rpaulo } 2380 1.5.6.2 rpaulo 2381 1.5.6.2 rpaulo static int 2382 1.5.6.2 rpaulo radeonfb_allocattr(void *cookie, int fg, int bg, int flags, long *attrp) 2383 1.5.6.2 rpaulo { 2384 1.5.6.2 rpaulo if ((fg == 0) && (bg == 0)) { 2385 1.5.6.2 rpaulo fg = WS_DEFAULT_FG; 2386 1.5.6.2 rpaulo bg = WS_DEFAULT_BG; 2387 1.5.6.2 rpaulo } 2388 1.5.6.2 rpaulo *attrp = ((fg & 0xf) << 24) | ((bg & 0xf) << 16) | (flags & 0xff) << 8; 2389 1.5.6.2 rpaulo return 0; 2390 1.5.6.2 rpaulo } 2391 1.5.6.2 rpaulo 2392 1.5.6.2 rpaulo /* 2393 1.5.6.2 rpaulo * Underlying acceleration support. 2394 1.5.6.2 rpaulo */ 2395 1.5.6.2 rpaulo static void 2396 1.5.6.2 rpaulo radeonfb_setup_mono(struct radeonfb_display *dp, int xd, int yd, int width, 2397 1.5.6.2 rpaulo int height, uint32_t fg, uint32_t bg) 2398 1.5.6.2 rpaulo { 2399 1.5.6.2 rpaulo struct radeonfb_softc *sc = dp->rd_softc; 2400 1.5.6.2 rpaulo uint32_t gmc; 2401 1.5.6.2 rpaulo uint32_t padded_width = (width+7) & 0xfff8; 2402 1.5.6.2 rpaulo uint32_t topleft, bottomright; 2403 1.5.6.2 rpaulo 2404 1.5.6.2 rpaulo gmc = dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT; 2405 1.5.6.2 rpaulo 2406 1.5.6.2 rpaulo if (width != padded_width) { 2407 1.5.6.2 rpaulo 2408 1.5.6.2 rpaulo radeonfb_wait_fifo(sc, 2); 2409 1.5.6.2 rpaulo topleft = ((yd << 16) & 0x1fff0000) | (xd & 0x1fff); 2410 1.5.6.2 rpaulo bottomright = (((yd + height) << 16) & 0x1fff0000) | 2411 1.5.6.2 rpaulo ((xd + width) & 0x1fff); 2412 1.5.6.2 rpaulo PUT32(sc, RADEON_SC_TOP_LEFT, topleft); 2413 1.5.6.2 rpaulo PUT32(sc, RADEON_SC_BOTTOM_RIGHT, bottomright); 2414 1.5.6.2 rpaulo } 2415 1.5.6.2 rpaulo 2416 1.5.6.2 rpaulo radeonfb_wait_fifo(sc, 5); 2417 1.5.6.2 rpaulo 2418 1.5.6.2 rpaulo PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 2419 1.5.6.2 rpaulo RADEON_GMC_BRUSH_NONE | 2420 1.5.6.2 rpaulo RADEON_GMC_SRC_DATATYPE_MONO_FG_BG | 2421 1.5.6.2 rpaulo //RADEON_GMC_BYTE_LSB_TO_MSB | 2422 1.5.6.2 rpaulo RADEON_GMC_DST_CLIPPING | 2423 1.5.6.2 rpaulo RADEON_ROP3_S | 2424 1.5.6.2 rpaulo RADEON_DP_SRC_SOURCE_HOST_DATA | 2425 1.5.6.2 rpaulo RADEON_GMC_CLR_CMP_CNTL_DIS | 2426 1.5.6.2 rpaulo RADEON_GMC_WR_MSK_DIS | 2427 1.5.6.2 rpaulo gmc); 2428 1.5.6.2 rpaulo 2429 1.5.6.2 rpaulo PUT32(sc, RADEON_DP_SRC_FRGD_CLR, fg); 2430 1.5.6.2 rpaulo PUT32(sc, RADEON_DP_SRC_BKGD_CLR, bg); 2431 1.5.6.2 rpaulo 2432 1.5.6.2 rpaulo PUT32(sc, RADEON_DST_X_Y, (xd << 16) | yd); 2433 1.5.6.2 rpaulo PUT32(sc, RADEON_DST_WIDTH_HEIGHT, (padded_width << 16) | height); 2434 1.5.6.2 rpaulo 2435 1.5.6.2 rpaulo } 2436 1.5.6.2 rpaulo 2437 1.5.6.2 rpaulo static void 2438 1.5.6.2 rpaulo radeonfb_feed_bytes(struct radeonfb_display *dp, int count, uint8_t *data) 2439 1.5.6.2 rpaulo { 2440 1.5.6.2 rpaulo struct radeonfb_softc *sc = dp->rd_softc; 2441 1.5.6.2 rpaulo int i; 2442 1.5.6.2 rpaulo uint32_t latch = 0; 2443 1.5.6.2 rpaulo int shift = 0; 2444 1.5.6.2 rpaulo 2445 1.5.6.2 rpaulo for (i = 0; i < count; i++) { 2446 1.5.6.2 rpaulo latch |= (data[i] << shift); 2447 1.5.6.2 rpaulo if (shift == 24) { 2448 1.5.6.2 rpaulo radeonfb_wait_fifo(sc, 1); 2449 1.5.6.2 rpaulo PUT32(sc, RADEON_HOST_DATA0, latch); 2450 1.5.6.2 rpaulo latch = 0; 2451 1.5.6.2 rpaulo shift = 0; 2452 1.5.6.2 rpaulo } else 2453 1.5.6.2 rpaulo shift += 8; 2454 1.5.6.2 rpaulo } 2455 1.5.6.2 rpaulo if (shift != 0) { 2456 1.5.6.2 rpaulo radeonfb_wait_fifo(sc, 1); 2457 1.5.6.2 rpaulo PUT32(sc, RADEON_HOST_DATA0, latch); 2458 1.5.6.2 rpaulo } 2459 1.5.6.2 rpaulo radeonfb_unclip(sc); 2460 1.5.6.2 rpaulo } 2461 1.5.6.2 rpaulo 2462 1.5.6.2 rpaulo static void 2463 1.5.6.2 rpaulo radeonfb_rectfill(struct radeonfb_display *dp, int dstx, int dsty, 2464 1.5.6.2 rpaulo int width, int height, uint32_t color) 2465 1.5.6.2 rpaulo { 2466 1.5.6.2 rpaulo struct radeonfb_softc *sc = dp->rd_softc; 2467 1.5.6.2 rpaulo uint32_t gmc; 2468 1.5.6.2 rpaulo 2469 1.5.6.2 rpaulo gmc = dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT; 2470 1.5.6.2 rpaulo 2471 1.5.6.2 rpaulo radeonfb_wait_fifo(sc, 6); 2472 1.5.6.2 rpaulo 2473 1.5.6.2 rpaulo PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 2474 1.5.6.2 rpaulo RADEON_GMC_BRUSH_SOLID_COLOR | 2475 1.5.6.2 rpaulo RADEON_GMC_SRC_DATATYPE_COLOR | 2476 1.5.6.2 rpaulo RADEON_GMC_CLR_CMP_CNTL_DIS | 2477 1.5.6.2 rpaulo RADEON_ROP3_P | gmc); 2478 1.5.6.2 rpaulo 2479 1.5.6.2 rpaulo PUT32(sc, RADEON_DP_BRUSH_FRGD_CLR, color); 2480 1.5.6.2 rpaulo PUT32(sc, RADEON_DP_WRITE_MASK, 0xffffffff); 2481 1.5.6.2 rpaulo PUT32(sc, RADEON_DP_CNTL, 2482 1.5.6.2 rpaulo RADEON_DST_X_LEFT_TO_RIGHT | 2483 1.5.6.2 rpaulo RADEON_DST_Y_TOP_TO_BOTTOM); 2484 1.5.6.2 rpaulo PUT32(sc, RADEON_DST_Y_X, (dsty << 16) | dstx); 2485 1.5.6.2 rpaulo PUT32(sc, RADEON_DST_WIDTH_HEIGHT, (width << 16) | (height)); 2486 1.5.6.2 rpaulo 2487 1.5.6.2 rpaulo /* 2488 1.5.6.2 rpaulo * XXX: we don't wait for the fifo to empty -- that would slow 2489 1.5.6.2 rpaulo * things down! The linux radeonfb driver waits, but xfree doesn't 2490 1.5.6.2 rpaulo */ 2491 1.5.6.2 rpaulo /* XXX: for now we do, to make it safe for direct drawing */ 2492 1.5.6.2 rpaulo radeonfb_engine_idle(sc); 2493 1.5.6.2 rpaulo } 2494 1.5.6.2 rpaulo 2495 1.5.6.2 rpaulo static void 2496 1.5.6.2 rpaulo radeonfb_bitblt(struct radeonfb_display *dp, int srcx, int srcy, 2497 1.5.6.2 rpaulo int dstx, int dsty, int width, int height, int rop, uint32_t mask) 2498 1.5.6.2 rpaulo { 2499 1.5.6.2 rpaulo struct radeonfb_softc *sc = dp->rd_softc; 2500 1.5.6.2 rpaulo uint32_t gmc; 2501 1.5.6.2 rpaulo uint32_t dir; 2502 1.5.6.2 rpaulo 2503 1.5.6.2 rpaulo if (dsty < srcy) { 2504 1.5.6.2 rpaulo dir = RADEON_DST_Y_TOP_TO_BOTTOM; 2505 1.5.6.2 rpaulo } else { 2506 1.5.6.2 rpaulo srcy += height - 1; 2507 1.5.6.2 rpaulo dsty += height - 1; 2508 1.5.6.2 rpaulo dir = 0; 2509 1.5.6.2 rpaulo } 2510 1.5.6.2 rpaulo if (dstx < dsty) { 2511 1.5.6.2 rpaulo dir |= RADEON_DST_X_LEFT_TO_RIGHT; 2512 1.5.6.2 rpaulo } else { 2513 1.5.6.2 rpaulo srcx += width - 1; 2514 1.5.6.2 rpaulo dstx += width - 1; 2515 1.5.6.2 rpaulo } 2516 1.5.6.2 rpaulo 2517 1.5.6.2 rpaulo gmc = dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT; 2518 1.5.6.2 rpaulo 2519 1.5.6.2 rpaulo radeonfb_wait_fifo(sc, 6); 2520 1.5.6.2 rpaulo 2521 1.5.6.2 rpaulo PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 2522 1.5.6.2 rpaulo //RADEON_GMC_SRC_CLIPPING | 2523 1.5.6.2 rpaulo RADEON_GMC_BRUSH_SOLID_COLOR | 2524 1.5.6.2 rpaulo RADEON_GMC_SRC_DATATYPE_COLOR | 2525 1.5.6.2 rpaulo RADEON_GMC_CLR_CMP_CNTL_DIS | 2526 1.5.6.2 rpaulo RADEON_DP_SRC_SOURCE_MEMORY | 2527 1.5.6.2 rpaulo rop | gmc); 2528 1.5.6.2 rpaulo 2529 1.5.6.2 rpaulo PUT32(sc, RADEON_DP_WRITE_MASK, mask); 2530 1.5.6.2 rpaulo PUT32(sc, RADEON_DP_CNTL, dir); 2531 1.5.6.2 rpaulo PUT32(sc, RADEON_SRC_Y_X, (srcy << 16) | srcx); 2532 1.5.6.2 rpaulo PUT32(sc, RADEON_DST_Y_X, (dsty << 16) | dstx); 2533 1.5.6.2 rpaulo PUT32(sc, RADEON_DST_WIDTH_HEIGHT, (width << 16) | (height)); 2534 1.5.6.2 rpaulo 2535 1.5.6.2 rpaulo /* 2536 1.5.6.2 rpaulo * XXX: we don't wait for the fifo to empty -- that would slow 2537 1.5.6.2 rpaulo * things down! The linux radeonfb driver waits, but xfree doesn't 2538 1.5.6.2 rpaulo */ 2539 1.5.6.2 rpaulo /* XXX: for now we do, to make it safe for direct drawing */ 2540 1.5.6.2 rpaulo radeonfb_engine_idle(sc); 2541 1.5.6.2 rpaulo } 2542 1.5.6.2 rpaulo 2543 1.5.6.2 rpaulo static void 2544 1.5.6.2 rpaulo radeonfb_engine_idle(struct radeonfb_softc *sc) 2545 1.5.6.2 rpaulo { 2546 1.5.6.2 rpaulo int i; 2547 1.5.6.2 rpaulo 2548 1.5.6.2 rpaulo radeonfb_wait_fifo(sc, 64); 2549 1.5.6.2 rpaulo for (i = RADEON_TIMEOUT; i; i--) { 2550 1.5.6.2 rpaulo if ((GET32(sc, RADEON_RBBM_STATUS) & 2551 1.5.6.2 rpaulo RADEON_RBBM_ACTIVE) == 0) { 2552 1.5.6.2 rpaulo radeonfb_engine_flush(sc); 2553 1.5.6.2 rpaulo break; 2554 1.5.6.2 rpaulo } 2555 1.5.6.2 rpaulo } 2556 1.5.6.2 rpaulo } 2557 1.5.6.2 rpaulo 2558 1.5.6.2 rpaulo static void 2559 1.5.6.2 rpaulo radeonfb_wait_fifo(struct radeonfb_softc *sc, int n) 2560 1.5.6.2 rpaulo { 2561 1.5.6.2 rpaulo int i; 2562 1.5.6.2 rpaulo 2563 1.5.6.2 rpaulo for (i = RADEON_TIMEOUT; i; i--) { 2564 1.5.6.2 rpaulo if ((GET32(sc, RADEON_RBBM_STATUS) & 2565 1.5.6.2 rpaulo RADEON_RBBM_FIFOCNT_MASK) >= n) 2566 1.5.6.2 rpaulo return; 2567 1.5.6.2 rpaulo } 2568 1.5.6.2 rpaulo #ifdef DIAGNOSTIC 2569 1.5.6.2 rpaulo if (!i) 2570 1.5.6.2 rpaulo printf("%s: timed out waiting for fifo (%x)\n", 2571 1.5.6.2 rpaulo XNAME(sc), GET32(sc, RADEON_RBBM_STATUS)); 2572 1.5.6.2 rpaulo #endif 2573 1.5.6.2 rpaulo } 2574 1.5.6.2 rpaulo 2575 1.5.6.2 rpaulo static void 2576 1.5.6.2 rpaulo radeonfb_engine_flush(struct radeonfb_softc *sc) 2577 1.5.6.2 rpaulo { 2578 1.5.6.2 rpaulo int i; 2579 1.5.6.2 rpaulo SET32(sc, RADEON_RB2D_DSTCACHE_CTLSTAT, RADEON_RB2D_DC_FLUSH_ALL); 2580 1.5.6.2 rpaulo for (i = RADEON_TIMEOUT; i; i--) { 2581 1.5.6.2 rpaulo if ((GET32(sc, RADEON_RB2D_DSTCACHE_CTLSTAT) & 2582 1.5.6.2 rpaulo RADEON_RB2D_DC_BUSY) == 0) 2583 1.5.6.2 rpaulo break; 2584 1.5.6.2 rpaulo } 2585 1.5.6.2 rpaulo #ifdef DIAGNOSTIC 2586 1.5.6.2 rpaulo if (!i) 2587 1.5.6.2 rpaulo printf("%s: engine flush timed out!\n", XNAME(sc)); 2588 1.5.6.2 rpaulo #endif 2589 1.5.6.2 rpaulo } 2590 1.5.6.2 rpaulo 2591 1.5.6.2 rpaulo static inline void 2592 1.5.6.2 rpaulo radeonfb_unclip(struct radeonfb_softc *sc) 2593 1.5.6.2 rpaulo { 2594 1.5.6.2 rpaulo 2595 1.5.6.2 rpaulo radeonfb_wait_fifo(sc, 2); 2596 1.5.6.2 rpaulo PUT32(sc, RADEON_SC_TOP_LEFT, 0); 2597 1.5.6.2 rpaulo PUT32(sc, RADEON_SC_BOTTOM_RIGHT, 0x1fff1fff); 2598 1.5.6.2 rpaulo } 2599 1.5.6.2 rpaulo 2600 1.5.6.2 rpaulo static void 2601 1.5.6.2 rpaulo radeonfb_engine_init(struct radeonfb_display *dp) 2602 1.5.6.2 rpaulo { 2603 1.5.6.2 rpaulo struct radeonfb_softc *sc = dp->rd_softc; 2604 1.5.6.2 rpaulo uint32_t pitch; 2605 1.5.6.2 rpaulo 2606 1.5.6.2 rpaulo /* no 3D */ 2607 1.5.6.2 rpaulo PUT32(sc, RADEON_RB3D_CNTL, 0); 2608 1.5.6.2 rpaulo 2609 1.5.6.2 rpaulo radeonfb_engine_reset(sc); 2610 1.5.6.2 rpaulo pitch = ((dp->rd_virtx * (dp->rd_bpp / 8) + 0x3f)) >> 6; 2611 1.5.6.2 rpaulo //pitch = ((sc->sc_maxx * (sc->sc_maxbpp / 8) + 0x3f)) >> 6; 2612 1.5.6.2 rpaulo 2613 1.5.6.2 rpaulo radeonfb_wait_fifo(sc, 1); 2614 1.5.6.2 rpaulo if (!IS_R300(sc)) 2615 1.5.6.2 rpaulo PUT32(sc, RADEON_RB2D_DSTCACHE_MODE, 0); 2616 1.5.6.2 rpaulo 2617 1.5.6.2 rpaulo radeonfb_wait_fifo(sc, 3); 2618 1.5.6.2 rpaulo PUT32(sc, RADEON_DEFAULT_PITCH_OFFSET, 2619 1.5.6.2 rpaulo (pitch << 22) | (sc->sc_aperbase >> 10)); 2620 1.5.6.2 rpaulo 2621 1.5.6.2 rpaulo 2622 1.5.6.2 rpaulo PUT32(sc, RADEON_DST_PITCH_OFFSET, 2623 1.5.6.2 rpaulo (pitch << 22) | (sc->sc_aperbase >> 10)); 2624 1.5.6.2 rpaulo PUT32(sc, RADEON_SRC_PITCH_OFFSET, 2625 1.5.6.2 rpaulo (pitch << 22) | (sc->sc_aperbase >> 10)); 2626 1.5.6.2 rpaulo 2627 1.5.6.2 rpaulo radeonfb_wait_fifo(sc, 1); 2628 1.5.6.2 rpaulo #if _BYTE_ORDER == _BIG_ENDIAN 2629 1.5.6.2 rpaulo SET32(sc, RADEON_DP_DATATYPE, RADEON_HOST_BIG_ENDIAN_EN); 2630 1.5.6.2 rpaulo #else 2631 1.5.6.2 rpaulo CLR32(sc, RADEON_DP_DATATYPE, RADEON_HOST_BIG_ENDIAN_EN); 2632 1.5.6.2 rpaulo #endif 2633 1.5.6.2 rpaulo 2634 1.5.6.2 rpaulo /* default scissors -- no clipping */ 2635 1.5.6.2 rpaulo radeonfb_wait_fifo(sc, 1); 2636 1.5.6.2 rpaulo PUT32(sc, RADEON_DEFAULT_SC_BOTTOM_RIGHT, 2637 1.5.6.2 rpaulo RADEON_DEFAULT_SC_RIGHT_MAX | RADEON_DEFAULT_SC_BOTTOM_MAX); 2638 1.5.6.2 rpaulo 2639 1.5.6.2 rpaulo radeonfb_wait_fifo(sc, 1); 2640 1.5.6.2 rpaulo PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 2641 1.5.6.2 rpaulo (dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT) | 2642 1.5.6.2 rpaulo RADEON_GMC_CLR_CMP_CNTL_DIS | 2643 1.5.6.2 rpaulo RADEON_GMC_BRUSH_SOLID_COLOR | 2644 1.5.6.2 rpaulo RADEON_GMC_SRC_DATATYPE_COLOR); 2645 1.5.6.2 rpaulo 2646 1.5.6.2 rpaulo radeonfb_wait_fifo(sc, 7); 2647 1.5.6.2 rpaulo PUT32(sc, RADEON_DST_LINE_START, 0); 2648 1.5.6.2 rpaulo PUT32(sc, RADEON_DST_LINE_END, 0); 2649 1.5.6.2 rpaulo PUT32(sc, RADEON_DP_BRUSH_FRGD_CLR, 0xffffffff); 2650 1.5.6.2 rpaulo PUT32(sc, RADEON_DP_BRUSH_BKGD_CLR, 0); 2651 1.5.6.2 rpaulo PUT32(sc, RADEON_DP_SRC_FRGD_CLR, 0xffffffff); 2652 1.5.6.2 rpaulo PUT32(sc, RADEON_DP_SRC_BKGD_CLR, 0); 2653 1.5.6.2 rpaulo PUT32(sc, RADEON_DP_WRITE_MASK, 0xffffffff); 2654 1.5.6.2 rpaulo 2655 1.5.6.2 rpaulo radeonfb_engine_idle(sc); 2656 1.5.6.2 rpaulo } 2657 1.5.6.2 rpaulo 2658 1.5.6.2 rpaulo static void 2659 1.5.6.2 rpaulo radeonfb_engine_reset(struct radeonfb_softc *sc) 2660 1.5.6.2 rpaulo { 2661 1.5.6.2 rpaulo uint32_t hpc, rbbm, mclkcntl, clkindex; 2662 1.5.6.2 rpaulo 2663 1.5.6.2 rpaulo radeonfb_engine_flush(sc); 2664 1.5.6.2 rpaulo 2665 1.5.6.2 rpaulo clkindex = GET32(sc, RADEON_CLOCK_CNTL_INDEX); 2666 1.5.6.2 rpaulo if (HAS_R300CG(sc)) 2667 1.5.6.2 rpaulo radeonfb_r300cg_workaround(sc); 2668 1.5.6.2 rpaulo mclkcntl = GETPLL(sc, RADEON_MCLK_CNTL); 2669 1.5.6.2 rpaulo 2670 1.5.6.2 rpaulo /* 2671 1.5.6.2 rpaulo * According to comments in XFree code, resetting the HDP via 2672 1.5.6.2 rpaulo * the RBBM_SOFT_RESET can cause bad behavior on some systems. 2673 1.5.6.2 rpaulo * So we use HOST_PATH_CNTL instead. 2674 1.5.6.2 rpaulo */ 2675 1.5.6.2 rpaulo 2676 1.5.6.2 rpaulo hpc = GET32(sc, RADEON_HOST_PATH_CNTL); 2677 1.5.6.2 rpaulo rbbm = GET32(sc, RADEON_RBBM_SOFT_RESET); 2678 1.5.6.2 rpaulo if (IS_R300(sc)) { 2679 1.5.6.2 rpaulo PUT32(sc, RADEON_RBBM_SOFT_RESET, rbbm | 2680 1.5.6.2 rpaulo RADEON_SOFT_RESET_CP | 2681 1.5.6.2 rpaulo RADEON_SOFT_RESET_HI | 2682 1.5.6.2 rpaulo RADEON_SOFT_RESET_E2); 2683 1.5.6.2 rpaulo GET32(sc, RADEON_RBBM_SOFT_RESET); 2684 1.5.6.2 rpaulo PUT32(sc, RADEON_RBBM_SOFT_RESET, 0); 2685 1.5.6.2 rpaulo /* 2686 1.5.6.2 rpaulo * XXX: this bit is not defined in any ATI docs I have, 2687 1.5.6.2 rpaulo * nor in the XFree code, but XFree does it. Why? 2688 1.5.6.2 rpaulo */ 2689 1.5.6.2 rpaulo SET32(sc, RADEON_RB2D_DSTCACHE_MODE, (1<<17)); 2690 1.5.6.2 rpaulo } else { 2691 1.5.6.2 rpaulo PUT32(sc, RADEON_RBBM_SOFT_RESET, rbbm | 2692 1.5.6.2 rpaulo RADEON_SOFT_RESET_CP | 2693 1.5.6.2 rpaulo RADEON_SOFT_RESET_SE | 2694 1.5.6.2 rpaulo RADEON_SOFT_RESET_RE | 2695 1.5.6.2 rpaulo RADEON_SOFT_RESET_PP | 2696 1.5.6.2 rpaulo RADEON_SOFT_RESET_E2 | 2697 1.5.6.2 rpaulo RADEON_SOFT_RESET_RB); 2698 1.5.6.2 rpaulo GET32(sc, RADEON_RBBM_SOFT_RESET); 2699 1.5.6.2 rpaulo PUT32(sc, RADEON_RBBM_SOFT_RESET, rbbm & 2700 1.5.6.2 rpaulo ~(RADEON_SOFT_RESET_CP | 2701 1.5.6.2 rpaulo RADEON_SOFT_RESET_SE | 2702 1.5.6.2 rpaulo RADEON_SOFT_RESET_RE | 2703 1.5.6.2 rpaulo RADEON_SOFT_RESET_PP | 2704 1.5.6.2 rpaulo RADEON_SOFT_RESET_E2 | 2705 1.5.6.2 rpaulo RADEON_SOFT_RESET_RB)); 2706 1.5.6.2 rpaulo GET32(sc, RADEON_RBBM_SOFT_RESET); 2707 1.5.6.2 rpaulo } 2708 1.5.6.2 rpaulo 2709 1.5.6.2 rpaulo PUT32(sc, RADEON_HOST_PATH_CNTL, hpc | RADEON_HDP_SOFT_RESET); 2710 1.5.6.2 rpaulo GET32(sc, RADEON_HOST_PATH_CNTL); 2711 1.5.6.2 rpaulo PUT32(sc, RADEON_HOST_PATH_CNTL, hpc); 2712 1.5.6.2 rpaulo 2713 1.5.6.2 rpaulo if (IS_R300(sc)) 2714 1.5.6.2 rpaulo PUT32(sc, RADEON_RBBM_SOFT_RESET, rbbm); 2715 1.5.6.2 rpaulo 2716 1.5.6.2 rpaulo PUT32(sc, RADEON_CLOCK_CNTL_INDEX, clkindex); 2717 1.5.6.2 rpaulo PUTPLL(sc, RADEON_MCLK_CNTL, mclkcntl); 2718 1.5.6.2 rpaulo 2719 1.5.6.2 rpaulo if (HAS_R300CG(sc)) 2720 1.5.6.2 rpaulo radeonfb_r300cg_workaround(sc); 2721 1.5.6.2 rpaulo } 2722 1.5.6.2 rpaulo 2723 1.5.6.2 rpaulo static int 2724 1.5.6.2 rpaulo radeonfb_set_curpos(struct radeonfb_display *dp, struct wsdisplay_curpos *pos) 2725 1.5.6.2 rpaulo { 2726 1.5.6.2 rpaulo int x, y; 2727 1.5.6.2 rpaulo 2728 1.5.6.2 rpaulo x = pos->x; 2729 1.5.6.2 rpaulo y = pos->y; 2730 1.5.6.2 rpaulo 2731 1.5.6.2 rpaulo /* 2732 1.5.6.2 rpaulo * This doesn't let a cursor move off the screen. I'm not 2733 1.5.6.2 rpaulo * sure if this will have negative effects for e.g. Xinerama. 2734 1.5.6.2 rpaulo * I'd guess Xinerama handles it by changing the cursor shape, 2735 1.5.6.2 rpaulo * but that needs verification. 2736 1.5.6.2 rpaulo */ 2737 1.5.6.2 rpaulo if (x >= dp->rd_virtx) 2738 1.5.6.2 rpaulo x = dp->rd_virtx - 1; 2739 1.5.6.2 rpaulo if (x < 0) 2740 1.5.6.2 rpaulo x = 0; 2741 1.5.6.2 rpaulo if (y >= dp->rd_virty) 2742 1.5.6.2 rpaulo y = dp->rd_virty - 1; 2743 1.5.6.2 rpaulo if (y < 0) 2744 1.5.6.2 rpaulo y = 0; 2745 1.5.6.2 rpaulo 2746 1.5.6.2 rpaulo dp->rd_cursor.rc_pos.x = x; 2747 1.5.6.2 rpaulo dp->rd_cursor.rc_pos.y = y; 2748 1.5.6.2 rpaulo 2749 1.5.6.2 rpaulo radeonfb_cursor_position(dp); 2750 1.5.6.2 rpaulo return 0; 2751 1.5.6.2 rpaulo } 2752 1.5.6.2 rpaulo 2753 1.5.6.2 rpaulo static int 2754 1.5.6.2 rpaulo radeonfb_set_cursor(struct radeonfb_display *dp, struct wsdisplay_cursor *wc) 2755 1.5.6.2 rpaulo { 2756 1.5.6.2 rpaulo unsigned flags; 2757 1.5.6.2 rpaulo 2758 1.5.6.2 rpaulo uint8_t r[2], g[2], b[2]; 2759 1.5.6.2 rpaulo unsigned index, count; 2760 1.5.6.2 rpaulo int i, err; 2761 1.5.6.2 rpaulo int pitch, size; 2762 1.5.6.2 rpaulo struct radeonfb_cursor nc; 2763 1.5.6.2 rpaulo 2764 1.5.6.2 rpaulo flags = wc->which; 2765 1.5.6.2 rpaulo 2766 1.5.6.2 rpaulo /* copy old values */ 2767 1.5.6.2 rpaulo nc = dp->rd_cursor; 2768 1.5.6.2 rpaulo 2769 1.5.6.2 rpaulo if (flags & WSDISPLAY_CURSOR_DOCMAP) { 2770 1.5.6.2 rpaulo index = wc->cmap.index; 2771 1.5.6.2 rpaulo count = wc->cmap.count; 2772 1.5.6.2 rpaulo 2773 1.5.6.2 rpaulo if (index >= 2 || (index + count) > 2) 2774 1.5.6.2 rpaulo return EINVAL; 2775 1.5.6.2 rpaulo 2776 1.5.6.2 rpaulo err = copyin(wc->cmap.red, &r[index], count); 2777 1.5.6.2 rpaulo if (err) 2778 1.5.6.2 rpaulo return err; 2779 1.5.6.2 rpaulo err = copyin(wc->cmap.green, &g[index], count); 2780 1.5.6.2 rpaulo if (err) 2781 1.5.6.2 rpaulo return err; 2782 1.5.6.2 rpaulo err = copyin(wc->cmap.blue, &b[index], count); 2783 1.5.6.2 rpaulo if (err) 2784 1.5.6.2 rpaulo return err; 2785 1.5.6.2 rpaulo 2786 1.5.6.2 rpaulo for (i = index; i < index + count; i++) { 2787 1.5.6.2 rpaulo nc.rc_cmap[i] = 2788 1.5.6.2 rpaulo (r[i] << 16) + (g[i] << 8) + (b[i] << 0); 2789 1.5.6.2 rpaulo } 2790 1.5.6.2 rpaulo } 2791 1.5.6.2 rpaulo 2792 1.5.6.2 rpaulo if (flags & WSDISPLAY_CURSOR_DOSHAPE) { 2793 1.5.6.2 rpaulo if ((wc->size.x > RADEON_CURSORMAXX) || 2794 1.5.6.2 rpaulo (wc->size.y > RADEON_CURSORMAXY)) 2795 1.5.6.2 rpaulo return EINVAL; 2796 1.5.6.2 rpaulo 2797 1.5.6.2 rpaulo /* figure bytes per line */ 2798 1.5.6.2 rpaulo pitch = (wc->size.x + 7) / 8; 2799 1.5.6.2 rpaulo size = pitch * wc->size.y; 2800 1.5.6.2 rpaulo 2801 1.5.6.2 rpaulo /* clear the old cursor and mask */ 2802 1.5.6.2 rpaulo memset(nc.rc_image, 0, 512); 2803 1.5.6.2 rpaulo memset(nc.rc_mask, 0, 512); 2804 1.5.6.2 rpaulo 2805 1.5.6.2 rpaulo nc.rc_size = wc->size; 2806 1.5.6.2 rpaulo 2807 1.5.6.2 rpaulo if ((err = copyin(wc->image, nc.rc_image, size)) != 0) 2808 1.5.6.2 rpaulo return err; 2809 1.5.6.2 rpaulo 2810 1.5.6.2 rpaulo if ((err = copyin(wc->mask, nc.rc_mask, size)) != 0) 2811 1.5.6.2 rpaulo return err; 2812 1.5.6.2 rpaulo } 2813 1.5.6.2 rpaulo 2814 1.5.6.2 rpaulo if (flags & WSDISPLAY_CURSOR_DOHOT) { 2815 1.5.6.2 rpaulo nc.rc_hot = wc->hot; 2816 1.5.6.2 rpaulo if (nc.rc_hot.x >= nc.rc_size.x) 2817 1.5.6.2 rpaulo nc.rc_hot.x = nc.rc_size.x - 1; 2818 1.5.6.2 rpaulo if (nc.rc_hot.y >= nc.rc_size.y) 2819 1.5.6.2 rpaulo nc.rc_hot.y = nc.rc_size.y - 1; 2820 1.5.6.2 rpaulo } 2821 1.5.6.2 rpaulo 2822 1.5.6.2 rpaulo if (flags & WSDISPLAY_CURSOR_DOPOS) { 2823 1.5.6.2 rpaulo nc.rc_pos = wc->pos; 2824 1.5.6.2 rpaulo if (nc.rc_pos.x >= dp->rd_virtx) 2825 1.5.6.2 rpaulo nc.rc_pos.x = dp->rd_virtx - 1; 2826 1.5.6.2 rpaulo if (nc.rc_pos.x < 0) 2827 1.5.6.2 rpaulo nc.rc_pos.x = 0; 2828 1.5.6.2 rpaulo if (nc.rc_pos.y >= dp->rd_virty) 2829 1.5.6.2 rpaulo nc.rc_pos.y = dp->rd_virty - 1; 2830 1.5.6.2 rpaulo if (nc.rc_pos.y < 0) 2831 1.5.6.2 rpaulo nc.rc_pos.y = 0; 2832 1.5.6.2 rpaulo } 2833 1.5.6.2 rpaulo if (flags & WSDISPLAY_CURSOR_DOCUR) { 2834 1.5.6.2 rpaulo nc.rc_visible = wc->enable; 2835 1.5.6.2 rpaulo } 2836 1.5.6.2 rpaulo 2837 1.5.6.2 rpaulo dp->rd_cursor = nc; 2838 1.5.6.2 rpaulo radeonfb_cursor_update(dp, wc->which); 2839 1.5.6.2 rpaulo 2840 1.5.6.2 rpaulo return 0; 2841 1.5.6.2 rpaulo } 2842 1.5.6.2 rpaulo 2843 1.5.6.2 rpaulo /* 2844 1.5.6.2 rpaulo * Change the cursor shape. Call this with the cursor locked to avoid 2845 1.5.6.2 rpaulo * flickering/tearing. 2846 1.5.6.2 rpaulo */ 2847 1.5.6.2 rpaulo static void 2848 1.5.6.2 rpaulo radeonfb_cursor_shape(struct radeonfb_display *dp) 2849 1.5.6.2 rpaulo { 2850 1.5.6.2 rpaulo uint8_t and[512], xor[512]; 2851 1.5.6.2 rpaulo int i, j, src, dst, pitch; 2852 1.5.6.2 rpaulo const uint8_t *msk = dp->rd_cursor.rc_mask; 2853 1.5.6.2 rpaulo const uint8_t *img = dp->rd_cursor.rc_image; 2854 1.5.6.2 rpaulo 2855 1.5.6.2 rpaulo /* 2856 1.5.6.2 rpaulo * Radeon cursor data interleaves one line of AND data followed 2857 1.5.6.2 rpaulo * by a line of XOR data. (Each line corresponds to a whole hardware 2858 1.5.6.2 rpaulo * pitch - i.e. 64 pixels or 8 bytes.) 2859 1.5.6.2 rpaulo * 2860 1.5.6.2 rpaulo * The cursor is displayed using the following table: 2861 1.5.6.2 rpaulo * 2862 1.5.6.2 rpaulo * AND XOR Result 2863 1.5.6.2 rpaulo * ---------------------- 2864 1.5.6.2 rpaulo * 0 0 Cursor color 0 2865 1.5.6.2 rpaulo * 0 1 Cursor color 1 2866 1.5.6.2 rpaulo * 1 0 Transparent 2867 1.5.6.2 rpaulo * 1 1 Complement of background 2868 1.5.6.2 rpaulo * 2869 1.5.6.2 rpaulo * Our masks are therefore different from what we were passed. 2870 1.5.6.2 rpaulo * Passed in, I'm assuming the data represents either color 0 or 1, 2871 1.5.6.2 rpaulo * and a mask, so the passed in table looks like: 2872 1.5.6.2 rpaulo * 2873 1.5.6.2 rpaulo * IMG Mask Result 2874 1.5.6.2 rpaulo * ----------------------- 2875 1.5.6.2 rpaulo * 0 0 Transparent 2876 1.5.6.2 rpaulo * 0 1 Cursor color 0 2877 1.5.6.2 rpaulo * 1 0 Transparent 2878 1.5.6.2 rpaulo * 1 1 Cursor color 1 2879 1.5.6.2 rpaulo * 2880 1.5.6.2 rpaulo * IF mask bit == 1, AND = 0, XOR = color. 2881 1.5.6.2 rpaulo * IF mask bit == 0, AND = 1, XOR = 0. 2882 1.5.6.2 rpaulo * 2883 1.5.6.2 rpaulo * hence: AND = ~(mask); XOR = color & ~(mask); 2884 1.5.6.2 rpaulo */ 2885 1.5.6.2 rpaulo 2886 1.5.6.2 rpaulo pitch = ((dp->rd_cursor.rc_size.x + 7) / 8); 2887 1.5.6.2 rpaulo 2888 1.5.6.2 rpaulo /* start by assuming all bits are transparent */ 2889 1.5.6.2 rpaulo memset(and, 0xff, 512); 2890 1.5.6.2 rpaulo memset(xor, 0x00, 512); 2891 1.5.6.2 rpaulo 2892 1.5.6.2 rpaulo src = 0; 2893 1.5.6.2 rpaulo dst = 0; 2894 1.5.6.2 rpaulo for (i = 0; i < 64; i++) { 2895 1.5.6.2 rpaulo for (j = 0; j < 64; j += 8) { 2896 1.5.6.2 rpaulo if ((i < dp->rd_cursor.rc_size.y) && 2897 1.5.6.2 rpaulo (j < dp->rd_cursor.rc_size.x)) { 2898 1.5.6.2 rpaulo 2899 1.5.6.2 rpaulo /* take care to leave odd bits alone */ 2900 1.5.6.2 rpaulo and[dst] &= ~(msk[src]); 2901 1.5.6.2 rpaulo xor[dst] = img[src] & msk[src]; 2902 1.5.6.2 rpaulo src++; 2903 1.5.6.2 rpaulo } 2904 1.5.6.2 rpaulo dst++; 2905 1.5.6.2 rpaulo } 2906 1.5.6.2 rpaulo } 2907 1.5.6.2 rpaulo 2908 1.5.6.2 rpaulo /* copy the image into place */ 2909 1.5.6.2 rpaulo for (i = 0; i < 64; i++) { 2910 1.5.6.2 rpaulo memcpy((uint8_t *)dp->rd_curptr + (i * 16), 2911 1.5.6.2 rpaulo &and[i * 8], 8); 2912 1.5.6.2 rpaulo memcpy((uint8_t *)dp->rd_curptr + (i * 16) + 8, 2913 1.5.6.2 rpaulo &xor[i * 8], 8); 2914 1.5.6.2 rpaulo } 2915 1.5.6.2 rpaulo } 2916 1.5.6.2 rpaulo 2917 1.5.6.2 rpaulo static void 2918 1.5.6.2 rpaulo radeonfb_cursor_position(struct radeonfb_display *dp) 2919 1.5.6.2 rpaulo { 2920 1.5.6.2 rpaulo struct radeonfb_softc *sc = dp->rd_softc; 2921 1.5.6.2 rpaulo uint32_t offset, hvoff, hvpos; /* registers */ 2922 1.5.6.2 rpaulo uint32_t coff; /* cursor offset */ 2923 1.5.6.2 rpaulo int i, x, y, xoff, yoff, crtcoff; 2924 1.5.6.2 rpaulo 2925 1.5.6.2 rpaulo /* 2926 1.5.6.2 rpaulo * XXX: this also needs to handle pan/scan 2927 1.5.6.2 rpaulo */ 2928 1.5.6.2 rpaulo for (i = 0; i < dp->rd_ncrtcs; i++) { 2929 1.5.6.2 rpaulo 2930 1.5.6.2 rpaulo struct radeonfb_crtc *rcp = &dp->rd_crtcs[i]; 2931 1.5.6.2 rpaulo 2932 1.5.6.2 rpaulo if (rcp->rc_number) { 2933 1.5.6.2 rpaulo offset = RADEON_CUR2_OFFSET; 2934 1.5.6.2 rpaulo hvoff = RADEON_CUR2_HORZ_VERT_OFF; 2935 1.5.6.2 rpaulo hvpos = RADEON_CUR2_HORZ_VERT_POSN; 2936 1.5.6.2 rpaulo crtcoff = RADEON_CRTC2_OFFSET; 2937 1.5.6.2 rpaulo } else { 2938 1.5.6.2 rpaulo offset = RADEON_CUR_OFFSET; 2939 1.5.6.2 rpaulo hvoff = RADEON_CUR_HORZ_VERT_OFF; 2940 1.5.6.2 rpaulo hvpos = RADEON_CUR_HORZ_VERT_POSN; 2941 1.5.6.2 rpaulo crtcoff = RADEON_CRTC_OFFSET; 2942 1.5.6.2 rpaulo } 2943 1.5.6.2 rpaulo 2944 1.5.6.2 rpaulo x = dp->rd_cursor.rc_pos.x; 2945 1.5.6.2 rpaulo y = dp->rd_cursor.rc_pos.y; 2946 1.5.6.2 rpaulo 2947 1.5.6.2 rpaulo while (y < rcp->rc_yoffset) { 2948 1.5.6.2 rpaulo rcp->rc_yoffset -= RADEON_PANINCREMENT; 2949 1.5.6.2 rpaulo } 2950 1.5.6.2 rpaulo while (y >= (rcp->rc_yoffset + rcp->rc_videomode.vdisplay)) { 2951 1.5.6.2 rpaulo rcp->rc_yoffset += RADEON_PANINCREMENT; 2952 1.5.6.2 rpaulo } 2953 1.5.6.2 rpaulo while (x < rcp->rc_xoffset) { 2954 1.5.6.2 rpaulo rcp->rc_xoffset -= RADEON_PANINCREMENT; 2955 1.5.6.2 rpaulo } 2956 1.5.6.2 rpaulo while (x >= (rcp->rc_xoffset + rcp->rc_videomode.hdisplay)) { 2957 1.5.6.2 rpaulo rcp->rc_xoffset += RADEON_PANINCREMENT; 2958 1.5.6.2 rpaulo } 2959 1.5.6.2 rpaulo 2960 1.5.6.2 rpaulo /* adjust for the cursor's hotspot */ 2961 1.5.6.2 rpaulo x -= dp->rd_cursor.rc_hot.x; 2962 1.5.6.2 rpaulo y -= dp->rd_cursor.rc_hot.y; 2963 1.5.6.2 rpaulo xoff = yoff = 0; 2964 1.5.6.2 rpaulo 2965 1.5.6.2 rpaulo if (x >= dp->rd_virtx) 2966 1.5.6.2 rpaulo x = dp->rd_virtx - 1; 2967 1.5.6.2 rpaulo if (y >= dp->rd_virty) 2968 1.5.6.2 rpaulo y = dp->rd_virty - 1; 2969 1.5.6.2 rpaulo 2970 1.5.6.2 rpaulo /* now adjust cursor so it is relative to viewport */ 2971 1.5.6.2 rpaulo x -= rcp->rc_xoffset; 2972 1.5.6.2 rpaulo y -= rcp->rc_yoffset; 2973 1.5.6.2 rpaulo 2974 1.5.6.2 rpaulo /* 2975 1.5.6.2 rpaulo * no need to check for fall off, because we should 2976 1.5.6.2 rpaulo * never move off the screen entirely! 2977 1.5.6.2 rpaulo */ 2978 1.5.6.2 rpaulo coff = 0; 2979 1.5.6.2 rpaulo if (x < 0) { 2980 1.5.6.2 rpaulo xoff = -x; 2981 1.5.6.2 rpaulo x = 0; 2982 1.5.6.2 rpaulo } 2983 1.5.6.2 rpaulo if (y < 0) { 2984 1.5.6.2 rpaulo yoff = -y; 2985 1.5.6.2 rpaulo y = 0; 2986 1.5.6.2 rpaulo coff = (yoff * 2) * 8; 2987 1.5.6.2 rpaulo } 2988 1.5.6.2 rpaulo 2989 1.5.6.2 rpaulo /* pan the display */ 2990 1.5.6.2 rpaulo PUT32(sc, crtcoff, (rcp->rc_yoffset * dp->rd_stride) + 2991 1.5.6.2 rpaulo rcp->rc_xoffset); 2992 1.5.6.2 rpaulo 2993 1.5.6.2 rpaulo PUT32(sc, offset, (dp->rd_curoff + coff) | RADEON_CUR_LOCK); 2994 1.5.6.2 rpaulo PUT32(sc, hvoff, (xoff << 16) | (yoff) | RADEON_CUR_LOCK); 2995 1.5.6.2 rpaulo /* NB: this unlocks the cursor */ 2996 1.5.6.2 rpaulo PUT32(sc, hvpos, (x << 16) | y); 2997 1.5.6.2 rpaulo } 2998 1.5.6.2 rpaulo } 2999 1.5.6.2 rpaulo 3000 1.5.6.2 rpaulo static void 3001 1.5.6.2 rpaulo radeonfb_cursor_visible(struct radeonfb_display *dp) 3002 1.5.6.2 rpaulo { 3003 1.5.6.2 rpaulo int i; 3004 1.5.6.2 rpaulo uint32_t gencntl, bit; 3005 1.5.6.2 rpaulo 3006 1.5.6.2 rpaulo for (i = 0; i < dp->rd_ncrtcs; i++) { 3007 1.5.6.2 rpaulo if (dp->rd_crtcs[i].rc_number) { 3008 1.5.6.2 rpaulo gencntl = RADEON_CRTC2_GEN_CNTL; 3009 1.5.6.2 rpaulo bit = RADEON_CRTC2_CUR_EN; 3010 1.5.6.2 rpaulo } else { 3011 1.5.6.2 rpaulo gencntl = RADEON_CRTC_GEN_CNTL; 3012 1.5.6.2 rpaulo bit = RADEON_CRTC_CUR_EN; 3013 1.5.6.2 rpaulo } 3014 1.5.6.2 rpaulo 3015 1.5.6.2 rpaulo if (dp->rd_cursor.rc_visible) 3016 1.5.6.2 rpaulo SET32(dp->rd_softc, gencntl, bit); 3017 1.5.6.2 rpaulo else 3018 1.5.6.2 rpaulo CLR32(dp->rd_softc, gencntl, bit); 3019 1.5.6.2 rpaulo } 3020 1.5.6.2 rpaulo } 3021 1.5.6.2 rpaulo 3022 1.5.6.2 rpaulo static void 3023 1.5.6.2 rpaulo radeonfb_cursor_cmap(struct radeonfb_display *dp) 3024 1.5.6.2 rpaulo { 3025 1.5.6.2 rpaulo int i; 3026 1.5.6.2 rpaulo uint32_t c0reg, c1reg; 3027 1.5.6.2 rpaulo struct radeonfb_softc *sc = dp->rd_softc; 3028 1.5.6.2 rpaulo 3029 1.5.6.2 rpaulo for (i = 0; i < dp->rd_ncrtcs; i++) { 3030 1.5.6.2 rpaulo if (dp->rd_crtcs[i].rc_number) { 3031 1.5.6.2 rpaulo c0reg = RADEON_CUR2_CLR0; 3032 1.5.6.2 rpaulo c1reg = RADEON_CUR2_CLR1; 3033 1.5.6.2 rpaulo } else { 3034 1.5.6.2 rpaulo c0reg = RADEON_CUR_CLR0; 3035 1.5.6.2 rpaulo c1reg = RADEON_CUR_CLR1; 3036 1.5.6.2 rpaulo } 3037 1.5.6.2 rpaulo 3038 1.5.6.2 rpaulo PUT32(sc, c0reg, dp->rd_cursor.rc_cmap[0]); 3039 1.5.6.2 rpaulo PUT32(sc, c1reg, dp->rd_cursor.rc_cmap[1]); 3040 1.5.6.2 rpaulo } 3041 1.5.6.2 rpaulo } 3042 1.5.6.2 rpaulo 3043 1.5.6.2 rpaulo static void 3044 1.5.6.2 rpaulo radeonfb_cursor_update(struct radeonfb_display *dp, unsigned which) 3045 1.5.6.2 rpaulo { 3046 1.5.6.2 rpaulo struct radeonfb_softc *sc; 3047 1.5.6.2 rpaulo int i; 3048 1.5.6.2 rpaulo 3049 1.5.6.2 rpaulo sc = dp->rd_softc; 3050 1.5.6.2 rpaulo for (i = 0; i < dp->rd_ncrtcs; i++) { 3051 1.5.6.2 rpaulo if (dp->rd_crtcs[i].rc_number) { 3052 1.5.6.2 rpaulo SET32(sc, RADEON_CUR2_OFFSET, RADEON_CUR_LOCK); 3053 1.5.6.2 rpaulo } else { 3054 1.5.6.2 rpaulo SET32(sc, RADEON_CUR_OFFSET,RADEON_CUR_LOCK); 3055 1.5.6.2 rpaulo } 3056 1.5.6.2 rpaulo } 3057 1.5.6.2 rpaulo 3058 1.5.6.2 rpaulo if (which & WSDISPLAY_CURSOR_DOCMAP) 3059 1.5.6.2 rpaulo radeonfb_cursor_cmap(dp); 3060 1.5.6.2 rpaulo 3061 1.5.6.2 rpaulo if (which & WSDISPLAY_CURSOR_DOSHAPE) 3062 1.5.6.2 rpaulo radeonfb_cursor_shape(dp); 3063 1.5.6.2 rpaulo 3064 1.5.6.2 rpaulo if (which & WSDISPLAY_CURSOR_DOCUR) 3065 1.5.6.2 rpaulo radeonfb_cursor_visible(dp); 3066 1.5.6.2 rpaulo 3067 1.5.6.2 rpaulo /* this one is unconditional, because it updates other stuff */ 3068 1.5.6.2 rpaulo radeonfb_cursor_position(dp); 3069 1.5.6.2 rpaulo } 3070 1.5.6.2 rpaulo 3071 1.5.6.2 rpaulo static struct videomode * 3072 1.5.6.2 rpaulo radeonfb_best_refresh(struct videomode *m1, struct videomode *m2) 3073 1.5.6.2 rpaulo { 3074 1.5.6.2 rpaulo int r1, r2; 3075 1.5.6.2 rpaulo 3076 1.5.6.2 rpaulo /* otherwise pick the higher refresh rate */ 3077 1.5.6.2 rpaulo r1 = DIVIDE(DIVIDE(m1->dot_clock, m1->htotal), m1->vtotal); 3078 1.5.6.2 rpaulo r2 = DIVIDE(DIVIDE(m2->dot_clock, m2->htotal), m2->vtotal); 3079 1.5.6.2 rpaulo 3080 1.5.6.2 rpaulo return (r1 < r2 ? m2 : m1); 3081 1.5.6.2 rpaulo } 3082 1.5.6.2 rpaulo 3083 1.5.6.2 rpaulo static const struct videomode * 3084 1.5.6.2 rpaulo radeonfb_port_mode(struct radeonfb_port *rp, int x, int y) 3085 1.5.6.2 rpaulo { 3086 1.5.6.2 rpaulo struct edid_info *ep = &rp->rp_edid; 3087 1.5.6.2 rpaulo struct videomode *vmp = NULL; 3088 1.5.6.2 rpaulo int i; 3089 1.5.6.2 rpaulo 3090 1.5.6.2 rpaulo if (!rp->rp_edid_valid) { 3091 1.5.6.2 rpaulo /* fallback to safe mode */ 3092 1.5.6.2 rpaulo return radeonfb_modelookup(RADEON_DEFAULT_MODE); 3093 1.5.6.2 rpaulo } 3094 1.5.6.2 rpaulo 3095 1.5.6.2 rpaulo /* always choose the preferred mode first! */ 3096 1.5.6.2 rpaulo if (ep->edid_preferred_mode) { 3097 1.5.6.2 rpaulo 3098 1.5.6.2 rpaulo /* XXX: add auto-stretching support for native mode */ 3099 1.5.6.2 rpaulo 3100 1.5.6.2 rpaulo /* this may want panning to occur, btw */ 3101 1.5.6.2 rpaulo if ((ep->edid_preferred_mode->hdisplay <= x) && 3102 1.5.6.2 rpaulo (ep->edid_preferred_mode->vdisplay <= y)) 3103 1.5.6.2 rpaulo return ep->edid_preferred_mode; 3104 1.5.6.2 rpaulo } 3105 1.5.6.2 rpaulo 3106 1.5.6.2 rpaulo for (i = 0; i < ep->edid_nmodes; i++) { 3107 1.5.6.2 rpaulo /* 3108 1.5.6.2 rpaulo * We elect to pick a resolution that is too large for 3109 1.5.6.2 rpaulo * the monitor than one that is too small. This means 3110 1.5.6.2 rpaulo * that we will prefer to pan rather than to try to 3111 1.5.6.2 rpaulo * center a smaller display on a larger screen. In 3112 1.5.6.2 rpaulo * practice, this shouldn't matter because if a 3113 1.5.6.2 rpaulo * monitor can support a larger resolution, it can 3114 1.5.6.2 rpaulo * probably also support the smaller. A specific 3115 1.5.6.2 rpaulo * exception is fixed format panels, but hopefully 3116 1.5.6.2 rpaulo * they are properly dealt with by the "autostretch" 3117 1.5.6.2 rpaulo * logic above. 3118 1.5.6.2 rpaulo */ 3119 1.5.6.2 rpaulo if ((ep->edid_modes[i].hdisplay > x) || 3120 1.5.6.2 rpaulo (ep->edid_modes[i].vdisplay > y)) { 3121 1.5.6.2 rpaulo continue; 3122 1.5.6.2 rpaulo } 3123 1.5.6.2 rpaulo 3124 1.5.6.2 rpaulo /* 3125 1.5.6.2 rpaulo * at this point, the display mode is no larger than 3126 1.5.6.2 rpaulo * what we've requested. 3127 1.5.6.2 rpaulo */ 3128 1.5.6.2 rpaulo if (vmp == NULL) 3129 1.5.6.2 rpaulo vmp = &ep->edid_modes[i]; 3130 1.5.6.2 rpaulo 3131 1.5.6.2 rpaulo /* eliminate smaller modes */ 3132 1.5.6.2 rpaulo if ((vmp->hdisplay >= ep->edid_modes[i].hdisplay) || 3133 1.5.6.2 rpaulo (vmp->vdisplay >= ep->edid_modes[i].vdisplay)) 3134 1.5.6.2 rpaulo continue; 3135 1.5.6.2 rpaulo 3136 1.5.6.2 rpaulo if ((vmp->hdisplay < ep->edid_modes[i].hdisplay) || 3137 1.5.6.2 rpaulo (vmp->vdisplay < ep->edid_modes[i].vdisplay)) { 3138 1.5.6.2 rpaulo vmp = &ep->edid_modes[i]; 3139 1.5.6.2 rpaulo continue; 3140 1.5.6.2 rpaulo } 3141 1.5.6.2 rpaulo 3142 1.5.6.2 rpaulo KASSERT(vmp->hdisplay == ep->edid_modes[i].hdisplay); 3143 1.5.6.2 rpaulo KASSERT(vmp->vdisplay == ep->edid_modes[i].vdisplay); 3144 1.5.6.2 rpaulo 3145 1.5.6.2 rpaulo vmp = radeonfb_best_refresh(vmp, &ep->edid_modes[i]); 3146 1.5.6.2 rpaulo } 3147 1.5.6.2 rpaulo 3148 1.5.6.2 rpaulo return (vmp ? vmp : radeonfb_modelookup(RADEON_DEFAULT_MODE)); 3149 1.5.6.2 rpaulo } 3150 1.5.6.2 rpaulo 3151 1.5.6.2 rpaulo static int 3152 1.5.6.2 rpaulo radeonfb_hasres(struct videomode *list, int nlist, int x, int y) 3153 1.5.6.2 rpaulo { 3154 1.5.6.2 rpaulo int i; 3155 1.5.6.2 rpaulo 3156 1.5.6.2 rpaulo for (i = 0; i < nlist; i++) { 3157 1.5.6.2 rpaulo if ((x == list[i].hdisplay) && 3158 1.5.6.2 rpaulo (y == list[i].vdisplay)) { 3159 1.5.6.2 rpaulo return 1; 3160 1.5.6.2 rpaulo } 3161 1.5.6.2 rpaulo } 3162 1.5.6.2 rpaulo return 0; 3163 1.5.6.2 rpaulo } 3164 1.5.6.2 rpaulo 3165 1.5.6.2 rpaulo static void 3166 1.5.6.2 rpaulo radeonfb_pickres(struct radeonfb_display *dp, uint16_t *x, uint16_t *y, 3167 1.5.6.2 rpaulo int pan) 3168 1.5.6.2 rpaulo { 3169 1.5.6.2 rpaulo struct radeonfb_port *rp; 3170 1.5.6.2 rpaulo struct edid_info *ep; 3171 1.5.6.2 rpaulo int i, j; 3172 1.5.6.2 rpaulo 3173 1.5.6.2 rpaulo *x = 0; 3174 1.5.6.2 rpaulo *y = 0; 3175 1.5.6.2 rpaulo 3176 1.5.6.2 rpaulo if (pan) { 3177 1.5.6.2 rpaulo for (i = 0; i < dp->rd_ncrtcs; i++) { 3178 1.5.6.2 rpaulo rp = dp->rd_crtcs[i].rc_port; 3179 1.5.6.2 rpaulo ep = &rp->rp_edid; 3180 1.5.6.2 rpaulo if (!rp->rp_edid_valid) { 3181 1.5.6.2 rpaulo /* monitor not present */ 3182 1.5.6.2 rpaulo continue; 3183 1.5.6.2 rpaulo } 3184 1.5.6.2 rpaulo 3185 1.5.6.2 rpaulo /* 3186 1.5.6.2 rpaulo * For now we are ignoring "conflict" that 3187 1.5.6.2 rpaulo * could occur when mixing some modes like 3188 1.5.6.2 rpaulo * 1280x1024 and 1400x800. It isn't clear 3189 1.5.6.2 rpaulo * which is better, so the first one wins. 3190 1.5.6.2 rpaulo */ 3191 1.5.6.2 rpaulo for (j = 0; j < ep->edid_nmodes; j++) { 3192 1.5.6.2 rpaulo /* 3193 1.5.6.2 rpaulo * ignore resolutions that are too big for 3194 1.5.6.2 rpaulo * the radeon 3195 1.5.6.2 rpaulo */ 3196 1.5.6.2 rpaulo if (ep->edid_modes[j].hdisplay > 3197 1.5.6.2 rpaulo dp->rd_softc->sc_maxx) 3198 1.5.6.2 rpaulo continue; 3199 1.5.6.2 rpaulo if (ep->edid_modes[j].vdisplay > 3200 1.5.6.2 rpaulo dp->rd_softc->sc_maxy) 3201 1.5.6.2 rpaulo continue; 3202 1.5.6.2 rpaulo 3203 1.5.6.2 rpaulo /* 3204 1.5.6.2 rpaulo * pick largest resolution, the 3205 1.5.6.2 rpaulo * smaller monitor will pan 3206 1.5.6.2 rpaulo */ 3207 1.5.6.2 rpaulo if ((ep->edid_modes[j].hdisplay >= *x) && 3208 1.5.6.2 rpaulo (ep->edid_modes[j].vdisplay >= *y)) { 3209 1.5.6.2 rpaulo *x = ep->edid_modes[j].hdisplay; 3210 1.5.6.2 rpaulo *y = ep->edid_modes[j].vdisplay; 3211 1.5.6.2 rpaulo } 3212 1.5.6.2 rpaulo } 3213 1.5.6.2 rpaulo } 3214 1.5.6.2 rpaulo 3215 1.5.6.2 rpaulo } else { 3216 1.5.6.2 rpaulo struct videomode modes[64]; 3217 1.5.6.2 rpaulo int nmodes = 0; 3218 1.5.6.2 rpaulo int valid = 0; 3219 1.5.6.2 rpaulo 3220 1.5.6.2 rpaulo for (i = 0; i < dp->rd_ncrtcs; i++) { 3221 1.5.6.2 rpaulo /* 3222 1.5.6.2 rpaulo * pick the largest resolution in common. 3223 1.5.6.2 rpaulo */ 3224 1.5.6.2 rpaulo rp = dp->rd_crtcs[i].rc_port; 3225 1.5.6.2 rpaulo ep = &rp->rp_edid; 3226 1.5.6.2 rpaulo 3227 1.5.6.2 rpaulo if (!rp->rp_edid_valid) 3228 1.5.6.2 rpaulo continue; 3229 1.5.6.2 rpaulo 3230 1.5.6.2 rpaulo if (!valid) { 3231 1.5.6.2 rpaulo /* initialize starting list */ 3232 1.5.6.2 rpaulo for (j = 0; j < ep->edid_nmodes; j++) { 3233 1.5.6.2 rpaulo /* 3234 1.5.6.2 rpaulo * ignore resolutions that are 3235 1.5.6.2 rpaulo * too big for the radeon 3236 1.5.6.2 rpaulo */ 3237 1.5.6.2 rpaulo if (ep->edid_modes[j].hdisplay > 3238 1.5.6.2 rpaulo dp->rd_softc->sc_maxx) 3239 1.5.6.2 rpaulo continue; 3240 1.5.6.2 rpaulo if (ep->edid_modes[j].vdisplay > 3241 1.5.6.2 rpaulo dp->rd_softc->sc_maxy) 3242 1.5.6.2 rpaulo continue; 3243 1.5.6.2 rpaulo 3244 1.5.6.2 rpaulo modes[nmodes] = ep->edid_modes[j]; 3245 1.5.6.2 rpaulo nmodes++; 3246 1.5.6.2 rpaulo } 3247 1.5.6.2 rpaulo valid = 1; 3248 1.5.6.2 rpaulo } else { 3249 1.5.6.2 rpaulo /* merge into preexisting list */ 3250 1.5.6.2 rpaulo for (j = 0; j < nmodes; j++) { 3251 1.5.6.2 rpaulo if (!radeonfb_hasres(ep->edid_modes, 3252 1.5.6.2 rpaulo ep->edid_nmodes, 3253 1.5.6.2 rpaulo modes[j].hdisplay, 3254 1.5.6.2 rpaulo modes[j].vdisplay)) { 3255 1.5.6.2 rpaulo modes[j] = modes[nmodes]; 3256 1.5.6.2 rpaulo j--; 3257 1.5.6.2 rpaulo nmodes--; 3258 1.5.6.2 rpaulo } 3259 1.5.6.2 rpaulo } 3260 1.5.6.2 rpaulo } 3261 1.5.6.2 rpaulo } 3262 1.5.6.2 rpaulo 3263 1.5.6.2 rpaulo /* now we have to pick from the merged list */ 3264 1.5.6.2 rpaulo for (i = 0; i < nmodes; i++) { 3265 1.5.6.2 rpaulo if ((modes[i].hdisplay >= *x) && 3266 1.5.6.2 rpaulo (modes[i].vdisplay >= *y)) { 3267 1.5.6.2 rpaulo *x = modes[i].hdisplay; 3268 1.5.6.2 rpaulo *y = modes[i].vdisplay; 3269 1.5.6.2 rpaulo } 3270 1.5.6.2 rpaulo } 3271 1.5.6.2 rpaulo } 3272 1.5.6.2 rpaulo 3273 1.5.6.2 rpaulo if ((*x == 0) || (*y == 0)) { 3274 1.5.6.2 rpaulo /* fallback to safe mode */ 3275 1.5.6.2 rpaulo *x = 640; 3276 1.5.6.2 rpaulo *y = 480; 3277 1.5.6.2 rpaulo } 3278 1.5.6.2 rpaulo } 3279
Indexes created Tue Oct 21 08:09:48 GMT 2025