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radeonfb.c revision 1.76.4.1
      1  1.76.4.1     rmind /*	$NetBSD: radeonfb.c,v 1.76.4.1 2014/05/18 17:45:44 rmind Exp $ */
      2       1.1   gdamore 
      3       1.1   gdamore /*-
      4       1.1   gdamore  * Copyright (c) 2006 Itronix Inc.
      5       1.1   gdamore  * All rights reserved.
      6       1.1   gdamore  *
      7       1.1   gdamore  * Written by Garrett D'Amore for Itronix Inc.
      8       1.1   gdamore  *
      9       1.1   gdamore  * Redistribution and use in source and binary forms, with or without
     10       1.1   gdamore  * modification, are permitted provided that the following conditions
     11       1.1   gdamore  * are met:
     12       1.1   gdamore  * 1. Redistributions of source code must retain the above copyright
     13       1.1   gdamore  *    notice, this list of conditions and the following disclaimer.
     14       1.1   gdamore  * 2. Redistributions in binary form must reproduce the above copyright
     15       1.1   gdamore  *    notice, this list of conditions and the following disclaimer in the
     16       1.1   gdamore  *    documentation and/or other materials provided with the distribution.
     17       1.1   gdamore  * 3. The name of Itronix Inc. may not be used to endorse
     18       1.1   gdamore  *    or promote products derived from this software without specific
     19       1.1   gdamore  *    prior written permission.
     20       1.1   gdamore  *
     21       1.1   gdamore  * THIS SOFTWARE IS PROVIDED BY ITRONIX INC. ``AS IS'' AND ANY EXPRESS
     22       1.1   gdamore  * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
     23       1.1   gdamore  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
     24       1.1   gdamore  * ARE DISCLAIMED.  IN NO EVENT SHALL ITRONIX INC. BE LIABLE FOR ANY
     25       1.1   gdamore  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
     26       1.1   gdamore  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
     27       1.1   gdamore  * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     28       1.1   gdamore  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
     29       1.1   gdamore  * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
     30       1.1   gdamore  * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
     31       1.1   gdamore  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
     32      1.11        ad  */
     33       1.1   gdamore 
     34       1.1   gdamore /*
     35       1.1   gdamore  * ATI Technologies Inc. ("ATI") has not assisted in the creation of, and
     36       1.1   gdamore  * does not endorse, this software.  ATI will not be responsible or liable
     37       1.1   gdamore  * for any actual or alleged damage or loss caused by or in connection with
     38       1.1   gdamore  * the use of or reliance on this software.
     39       1.1   gdamore  */
     40       1.1   gdamore 
     41       1.1   gdamore /*
     42       1.1   gdamore  * Portions of this code were taken from XFree86's Radeon driver, which bears
     43       1.1   gdamore  * this notice:
     44       1.1   gdamore  *
     45       1.1   gdamore  * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and
     46       1.1   gdamore  *                VA Linux Systems Inc., Fremont, California.
     47       1.1   gdamore  *
     48       1.1   gdamore  * All Rights Reserved.
     49       1.1   gdamore  *
     50       1.1   gdamore  * Permission is hereby granted, free of charge, to any person obtaining
     51       1.1   gdamore  * a copy of this software and associated documentation files (the
     52       1.1   gdamore  * "Software"), to deal in the Software without restriction, including
     53       1.1   gdamore  * without limitation on the rights to use, copy, modify, merge,
     54       1.1   gdamore  * publish, distribute, sublicense, and/or sell copies of the Software,
     55       1.1   gdamore  * and to permit persons to whom the Software is furnished to do so,
     56       1.1   gdamore  * subject to the following conditions:
     57       1.1   gdamore  *
     58       1.1   gdamore  * The above copyright notice and this permission notice (including the
     59       1.1   gdamore  * next paragraph) shall be included in all copies or substantial
     60       1.1   gdamore  * portions of the Software.
     61       1.1   gdamore  *
     62       1.1   gdamore  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
     63       1.1   gdamore  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
     64       1.1   gdamore  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
     65       1.1   gdamore  * NON-INFRINGEMENT.  IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR
     66       1.1   gdamore  * THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
     67       1.1   gdamore  * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
     68       1.1   gdamore  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
     69       1.1   gdamore  * DEALINGS IN THE SOFTWARE.
     70       1.1   gdamore  */
     71       1.1   gdamore 
     72       1.1   gdamore #include <sys/cdefs.h>
     73  1.76.4.1     rmind __KERNEL_RCSID(0, "$NetBSD: radeonfb.c,v 1.76.4.1 2014/05/18 17:45:44 rmind Exp $");
     74       1.1   gdamore 
     75       1.1   gdamore #include <sys/param.h>
     76       1.1   gdamore #include <sys/systm.h>
     77       1.1   gdamore #include <sys/device.h>
     78       1.1   gdamore #include <sys/malloc.h>
     79      1.21        ad #include <sys/bus.h>
     80       1.5  macallan #include <sys/kernel.h>
     81       1.5  macallan #include <sys/lwp.h>
     82       1.5  macallan #include <sys/kauth.h>
     83       1.1   gdamore 
     84       1.1   gdamore #include <dev/wscons/wsdisplayvar.h>
     85       1.1   gdamore #include <dev/wscons/wsconsio.h>
     86       1.1   gdamore #include <dev/wsfont/wsfont.h>
     87       1.1   gdamore #include <dev/rasops/rasops.h>
     88       1.1   gdamore #include <dev/videomode/videomode.h>
     89       1.1   gdamore #include <dev/videomode/edidvar.h>
     90       1.1   gdamore #include <dev/wscons/wsdisplay_vconsvar.h>
     91      1.41    cegger #include <dev/pci/wsdisplay_pci.h>
     92      1.54  macallan #include <dev/wscons/wsdisplay_glyphcachevar.h>
     93       1.1   gdamore 
     94       1.1   gdamore #include <dev/pci/pcidevs.h>
     95       1.1   gdamore #include <dev/pci/pcireg.h>
     96       1.1   gdamore #include <dev/pci/pcivar.h>
     97      1.26       phx #include <dev/pci/pciio.h>
     98       1.1   gdamore #include <dev/pci/radeonfbreg.h>
     99       1.1   gdamore #include <dev/pci/radeonfbvar.h>
    100      1.14  macallan #include "opt_radeonfb.h"
    101      1.48  macallan #include "opt_vcons.h"
    102       1.1   gdamore 
    103      1.49  macallan #ifdef RADEONFB_DEPTH_32
    104      1.49  macallan #define RADEONFB_DEFAULT_DEPTH 32
    105      1.49  macallan #else
    106      1.49  macallan #define RADEONFB_DEFAULT_DEPTH 8
    107      1.49  macallan #endif
    108      1.49  macallan 
    109      1.31    cegger static int radeonfb_match(device_t, cfdata_t, void *);
    110      1.31    cegger static void radeonfb_attach(device_t, device_t, void *);
    111      1.12  christos static int radeonfb_ioctl(void *, void *, unsigned long, void *, int,
    112       1.1   gdamore     struct lwp *);
    113       1.1   gdamore static paddr_t radeonfb_mmap(void *, void *, off_t, int);
    114       1.1   gdamore static int radeonfb_scratch_test(struct radeonfb_softc *, int, uint32_t);
    115       1.1   gdamore static void radeonfb_loadbios(struct radeonfb_softc *,
    116      1.44    dyoung     const struct pci_attach_args *);
    117       1.1   gdamore 
    118       1.1   gdamore static uintmax_t radeonfb_getprop_num(struct radeonfb_softc *, const char *,
    119       1.1   gdamore     uintmax_t);
    120       1.1   gdamore static int radeonfb_getclocks(struct radeonfb_softc *);
    121       1.1   gdamore static int radeonfb_gettmds(struct radeonfb_softc *);
    122       1.1   gdamore static int radeonfb_calc_dividers(struct radeonfb_softc *, uint32_t,
    123       1.1   gdamore     uint32_t *, uint32_t *);
    124       1.1   gdamore static int radeonfb_getconnectors(struct radeonfb_softc *);
    125       1.1   gdamore static const struct videomode *radeonfb_modelookup(const char *);
    126       1.1   gdamore static void radeonfb_init_screen(void *, struct vcons_screen *, int, long *);
    127       1.1   gdamore static void radeonfb_pllwriteupdate(struct radeonfb_softc *, int);
    128       1.1   gdamore static void radeonfb_pllwaitatomicread(struct radeonfb_softc *, int);
    129       1.1   gdamore static void radeonfb_program_vclk(struct radeonfb_softc *, int, int);
    130       1.1   gdamore static void radeonfb_modeswitch(struct radeonfb_display *);
    131       1.1   gdamore static void radeonfb_setcrtc(struct radeonfb_display *, int);
    132       1.1   gdamore static void radeonfb_init_misc(struct radeonfb_softc *);
    133       1.1   gdamore static void radeonfb_set_fbloc(struct radeonfb_softc *);
    134      1.70  macallan static void radeonfb_init_palette(struct radeonfb_display *);
    135       1.1   gdamore static void radeonfb_r300cg_workaround(struct radeonfb_softc *);
    136       1.1   gdamore 
    137       1.1   gdamore static int radeonfb_isblank(struct radeonfb_display *);
    138       1.1   gdamore static void radeonfb_blank(struct radeonfb_display *, int);
    139       1.1   gdamore static int radeonfb_set_cursor(struct radeonfb_display *,
    140       1.1   gdamore     struct wsdisplay_cursor *);
    141       1.1   gdamore static int radeonfb_set_curpos(struct radeonfb_display *,
    142       1.1   gdamore     struct wsdisplay_curpos *);
    143  1.76.4.1     rmind static void radeonfb_putpal(struct radeonfb_display *, int, int, int, int);
    144  1.76.4.1     rmind static int radeonfb_putcmap(struct radeonfb_display *, struct wsdisplay_cmap *);
    145  1.76.4.1     rmind static int radeonfb_getcmap(struct radeonfb_display *, struct wsdisplay_cmap *);
    146       1.1   gdamore 
    147       1.1   gdamore /* acceleration support */
    148       1.2  macallan static void  radeonfb_rectfill(struct radeonfb_display *, int dstx, int dsty,
    149       1.1   gdamore     int width, int height, uint32_t color);
    150      1.64  macallan static void  radeonfb_rectfill_a(void *, int, int, int, int, long);
    151      1.54  macallan static void radeonfb_bitblt(void *, int srcx, int srcy,
    152      1.54  macallan     int dstx, int dsty, int width, int height, int rop);
    153       1.2  macallan 
    154       1.1   gdamore /* hw cursor support */
    155       1.1   gdamore static void radeonfb_cursor_cmap(struct radeonfb_display *);
    156       1.1   gdamore static void radeonfb_cursor_shape(struct radeonfb_display *);
    157       1.1   gdamore static void radeonfb_cursor_position(struct radeonfb_display *);
    158       1.1   gdamore static void radeonfb_cursor_visible(struct radeonfb_display *);
    159       1.1   gdamore static void radeonfb_cursor_update(struct radeonfb_display *, unsigned);
    160       1.1   gdamore 
    161      1.62  uebayasi static inline void radeonfb_wait_fifo(struct radeonfb_softc *, int);
    162       1.1   gdamore static void radeonfb_engine_idle(struct radeonfb_softc *);
    163       1.1   gdamore static void radeonfb_engine_flush(struct radeonfb_softc *);
    164       1.1   gdamore static void radeonfb_engine_reset(struct radeonfb_softc *);
    165       1.1   gdamore static void radeonfb_engine_init(struct radeonfb_display *);
    166  1.76.4.1     rmind static inline void radeonfb_unclip(struct radeonfb_softc *) __unused;
    167       1.1   gdamore 
    168       1.1   gdamore static void radeonfb_eraserows(void *, int, int, long);
    169       1.1   gdamore static void radeonfb_erasecols(void *, int, int, int, long);
    170       1.1   gdamore static void radeonfb_copyrows(void *, int, int, int);
    171       1.1   gdamore static void radeonfb_copycols(void *, int, int, int, int);
    172       1.1   gdamore static void radeonfb_cursor(void *, int, int, int);
    173       1.2  macallan static void radeonfb_putchar(void *, int, int, unsigned, long);
    174      1.49  macallan static void radeonfb_putchar_aa32(void *, int, int, unsigned, long);
    175      1.55  macallan static void radeonfb_putchar_aa8(void *, int, int, unsigned, long);
    176      1.73  macallan #ifndef RADEONFB_ALWAYS_ACCEL_PUTCHAR
    177      1.38  macallan static void radeonfb_putchar_wrapper(void *, int, int, unsigned, long);
    178      1.73  macallan #endif
    179       1.1   gdamore 
    180      1.59  macallan static int radeonfb_set_backlight(struct radeonfb_display *, int);
    181       1.9  macallan static int radeonfb_get_backlight(struct radeonfb_display *);
    182      1.59  macallan static void radeonfb_switch_backlight(struct radeonfb_display *, int);
    183       1.9  macallan static void radeonfb_lvds_callout(void *);
    184       1.9  macallan 
    185      1.34  macallan static void radeonfb_brightness_up(device_t);
    186      1.34  macallan static void radeonfb_brightness_down(device_t);
    187      1.34  macallan 
    188       1.1   gdamore static struct videomode *radeonfb_best_refresh(struct videomode *,
    189       1.1   gdamore     struct videomode *);
    190       1.1   gdamore static void radeonfb_pickres(struct radeonfb_display *, uint16_t *,
    191       1.1   gdamore     uint16_t *, int);
    192      1.11        ad static const struct videomode *radeonfb_port_mode(struct radeonfb_softc *,
    193       1.9  macallan     struct radeonfb_port *, int, int);
    194       1.1   gdamore 
    195      1.14  macallan static int radeonfb_drm_print(void *, const char *);
    196      1.14  macallan 
    197      1.36  macallan #ifdef	RADEONFB_DEBUG
    198       1.1   gdamore int	radeon_debug = 1;
    199       1.1   gdamore #define	DPRINTF(x)	\
    200       1.1   gdamore 	if (radeon_debug) printf x
    201       1.1   gdamore #define	PRINTREG(r)	DPRINTF((#r " = %08x\n", GET32(sc, r)))
    202       1.1   gdamore #define	PRINTPLL(r)	DPRINTF((#r " = %08x\n", GETPLL(sc, r)))
    203       1.1   gdamore #else
    204       1.1   gdamore #define	DPRINTF(x)
    205       1.1   gdamore #define	PRINTREG(r)
    206       1.1   gdamore #define	PRINTPLL(r)
    207       1.1   gdamore #endif
    208       1.1   gdamore 
    209       1.1   gdamore #define	ROUNDUP(x,y)	(((x) + ((y) - 1)) & ~((y) - 1))
    210       1.1   gdamore 
    211       1.1   gdamore #ifndef	RADEON_DEFAULT_MODE
    212       1.1   gdamore /* any reasonably modern display should handle this */
    213       1.1   gdamore #define	RADEON_DEFAULT_MODE	"1024x768x60"
    214       1.1   gdamore #endif
    215       1.1   gdamore 
    216      1.36  macallan extern const u_char rasops_cmap[768];
    217      1.36  macallan 
    218       1.1   gdamore const char	*radeonfb_default_mode = RADEON_DEFAULT_MODE;
    219       1.1   gdamore 
    220       1.1   gdamore static struct {
    221       1.1   gdamore 	int		size;		/* minimum memory size (MB) */
    222       1.1   gdamore 	int		maxx;		/* maximum x dimension */
    223       1.1   gdamore 	int		maxy;		/* maximum y dimension */
    224       1.1   gdamore 	int		maxbpp;		/* maximum bpp */
    225       1.1   gdamore 	int		maxdisp;	/* maximum logical display count */
    226       1.1   gdamore } radeonfb_limits[] = {
    227       1.1   gdamore 	{ 32,	2048, 1536, 32, 2 },
    228       1.1   gdamore 	{ 16,	1600, 1200, 32, 2 },
    229       1.1   gdamore 	{ 8,	1600, 1200, 32, 1 },
    230       1.7  christos 	{ 0,	0, 0, 0, 0 },
    231       1.1   gdamore };
    232       1.1   gdamore 
    233       1.1   gdamore static struct wsscreen_descr radeonfb_stdscreen = {
    234       1.1   gdamore 	"fb",		/* name */
    235       1.1   gdamore 	0, 0,		/* ncols, nrows */
    236       1.1   gdamore 	NULL,		/* textops */
    237       1.2  macallan 	8, 16,		/* fontwidth, fontheight */
    238      1.64  macallan 	WSSCREEN_WSCOLORS | WSSCREEN_UNDERLINE, /* capabilities */
    239       1.7  christos 	0,		/* modecookie */
    240       1.1   gdamore };
    241       1.1   gdamore 
    242       1.1   gdamore struct wsdisplay_accessops radeonfb_accessops = {
    243       1.1   gdamore 	radeonfb_ioctl,
    244       1.1   gdamore 	radeonfb_mmap,
    245       1.1   gdamore 	NULL,		/* vcons_alloc_screen */
    246       1.1   gdamore 	NULL,		/* vcons_free_screen */
    247       1.1   gdamore 	NULL,		/* vcons_show_screen */
    248       1.7  christos 	NULL,		/* load_font */
    249       1.7  christos 	NULL,		/* pollc */
    250       1.7  christos 	NULL,		/* scroll */
    251       1.1   gdamore };
    252       1.1   gdamore 
    253       1.1   gdamore static struct {
    254       1.1   gdamore 	uint16_t	devid;
    255       1.1   gdamore 	uint16_t	family;
    256       1.1   gdamore 	uint16_t	flags;
    257      1.11        ad } radeonfb_devices[] =
    258       1.1   gdamore {
    259       1.1   gdamore 	/* R100 family */
    260       1.1   gdamore 	{ PCI_PRODUCT_ATI_RADEON_R100_QD,	RADEON_R100, 0 },
    261       1.1   gdamore 	{ PCI_PRODUCT_ATI_RADEON_R100_QE,	RADEON_R100, 0 },
    262       1.1   gdamore 	{ PCI_PRODUCT_ATI_RADEON_R100_QF,	RADEON_R100, 0 },
    263       1.1   gdamore 	{ PCI_PRODUCT_ATI_RADEON_R100_QG,	RADEON_R100, 0 },
    264       1.1   gdamore 
    265       1.1   gdamore 	/* RV100 family */
    266       1.1   gdamore 	{ PCI_PRODUCT_ATI_RADEON_RV100_LY,	RADEON_RV100, RFB_MOB },
    267       1.1   gdamore 	{ PCI_PRODUCT_ATI_RADEON_RV100_LZ,	RADEON_RV100, RFB_MOB },
    268       1.1   gdamore 	{ PCI_PRODUCT_ATI_RADEON_RV100_QY,	RADEON_RV100, 0 },
    269       1.1   gdamore 	{ PCI_PRODUCT_ATI_RADEON_RV100_QZ,	RADEON_RV100, 0 },
    270       1.1   gdamore 
    271       1.1   gdamore 	/* RS100 family */
    272       1.1   gdamore 	{ PCI_PRODUCT_ATI_RADEON_RS100_4136,	RADEON_RS100, 0 },
    273       1.1   gdamore 	{ PCI_PRODUCT_ATI_RADEON_RS100_4336,	RADEON_RS100, RFB_MOB },
    274       1.1   gdamore 
    275       1.1   gdamore 	/* RS200/RS250 family */
    276       1.1   gdamore 	{ PCI_PRODUCT_ATI_RADEON_RS200_4337,	RADEON_RS200, RFB_MOB },
    277       1.1   gdamore 	{ PCI_PRODUCT_ATI_RADEON_RS200_A7,	RADEON_RS200, 0 },
    278       1.1   gdamore 	{ PCI_PRODUCT_ATI_RADEON_RS250_B7,	RADEON_RS200, RFB_MOB },
    279       1.1   gdamore 	{ PCI_PRODUCT_ATI_RADEON_RS250_D7,	RADEON_RS200, 0 },
    280       1.1   gdamore 
    281       1.1   gdamore 	/* R200 family */
    282       1.1   gdamore 	/* add more R200 products? , 5148 */
    283       1.1   gdamore 	{ PCI_PRODUCT_ATI_RADEON_R200_BB,	RADEON_R200, 0 },
    284       1.1   gdamore 	{ PCI_PRODUCT_ATI_RADEON_R200_BC,	RADEON_R200, 0 },
    285       1.1   gdamore 	{ PCI_PRODUCT_ATI_RADEON_R200_QH,	RADEON_R200, 0 },
    286       1.1   gdamore 	{ PCI_PRODUCT_ATI_RADEON_R200_QL,	RADEON_R200, 0 },
    287       1.1   gdamore 	{ PCI_PRODUCT_ATI_RADEON_R200_QM,	RADEON_R200, 0 },
    288       1.1   gdamore 
    289       1.1   gdamore 	/* RV200 family */
    290       1.1   gdamore 	{ PCI_PRODUCT_ATI_RADEON_RV200_LW,	RADEON_RV200, RFB_MOB },
    291       1.1   gdamore 	{ PCI_PRODUCT_ATI_RADEON_RV200_LX,	RADEON_RV200, RFB_MOB },
    292       1.1   gdamore 	{ PCI_PRODUCT_ATI_RADEON_RV200_QW,	RADEON_RV200, 0 },
    293       1.1   gdamore 	{ PCI_PRODUCT_ATI_RADEON_RV200_QX,	RADEON_RV200, 0 },
    294       1.1   gdamore 
    295       1.1   gdamore 	/* RV250 family */
    296       1.1   gdamore 	{ PCI_PRODUCT_ATI_RADEON_RV250_4966,	RADEON_RV250, 0 },
    297       1.1   gdamore 	{ PCI_PRODUCT_ATI_RADEON_RV250_4967,	RADEON_RV250, 0 },
    298       1.1   gdamore 	{ PCI_PRODUCT_ATI_RADEON_RV250_4C64,	RADEON_RV250, RFB_MOB },
    299       1.1   gdamore 	{ PCI_PRODUCT_ATI_RADEON_RV250_4C66,	RADEON_RV250, RFB_MOB },
    300       1.1   gdamore 	{ PCI_PRODUCT_ATI_RADEON_RV250_4C67,	RADEON_RV250, RFB_MOB },
    301       1.1   gdamore 
    302       1.1   gdamore 	/* RS300 family */
    303       1.1   gdamore 	{ PCI_PRODUCT_ATI_RADEON_RS300_X5,	RADEON_RS300, 0 },
    304       1.1   gdamore 	{ PCI_PRODUCT_ATI_RADEON_RS300_X4,	RADEON_RS300, 0 },
    305       1.1   gdamore 	{ PCI_PRODUCT_ATI_RADEON_RS300_7834,	RADEON_RS300, 0 },
    306       1.1   gdamore 	{ PCI_PRODUCT_ATI_RADEON_RS300_7835,	RADEON_RS300, RFB_MOB },
    307       1.1   gdamore 
    308       1.1   gdamore 	/* RV280 family */
    309       1.1   gdamore 	{ PCI_PRODUCT_ATI_RADEON_RV280_5960,	RADEON_RV280, 0 },
    310       1.1   gdamore 	{ PCI_PRODUCT_ATI_RADEON_RV280_5961,	RADEON_RV280, 0 },
    311       1.1   gdamore 	{ PCI_PRODUCT_ATI_RADEON_RV280_5962,	RADEON_RV280, 0 },
    312       1.1   gdamore 	{ PCI_PRODUCT_ATI_RADEON_RV280_5963,	RADEON_RV280, 0 },
    313       1.1   gdamore 	{ PCI_PRODUCT_ATI_RADEON_RV280_5964,	RADEON_RV280, 0 },
    314       1.1   gdamore 	{ PCI_PRODUCT_ATI_RADEON_RV280_5C61,	RADEON_RV280, RFB_MOB },
    315       1.1   gdamore 	{ PCI_PRODUCT_ATI_RADEON_RV280_5C63,	RADEON_RV280, RFB_MOB },
    316       1.1   gdamore 
    317       1.1   gdamore 	/* R300 family */
    318       1.1   gdamore 	{ PCI_PRODUCT_ATI_RADEON_R300_AD,	RADEON_R300, 0 },
    319       1.1   gdamore 	{ PCI_PRODUCT_ATI_RADEON_R300_AE,	RADEON_R300, 0 },
    320       1.1   gdamore 	{ PCI_PRODUCT_ATI_RADEON_R300_AF,	RADEON_R300, 0 },
    321       1.1   gdamore 	{ PCI_PRODUCT_ATI_RADEON_R300_AG,	RADEON_R300, 0 },
    322       1.1   gdamore 	{ PCI_PRODUCT_ATI_RADEON_R300_ND,	RADEON_R300, 0 },
    323       1.1   gdamore 	{ PCI_PRODUCT_ATI_RADEON_R300_NE,	RADEON_R300, 0 },
    324       1.1   gdamore 	{ PCI_PRODUCT_ATI_RADEON_R300_NF,	RADEON_R300, 0 },
    325       1.1   gdamore 	{ PCI_PRODUCT_ATI_RADEON_R300_NG,	RADEON_R300, 0 },
    326       1.1   gdamore 
    327       1.1   gdamore 	/* RV350/RV360 family */
    328       1.1   gdamore 	{ PCI_PRODUCT_ATI_RADEON_RV350_AP,	RADEON_RV350, 0 },
    329       1.1   gdamore 	{ PCI_PRODUCT_ATI_RADEON_RV350_AQ,	RADEON_RV350, 0 },
    330       1.1   gdamore 	{ PCI_PRODUCT_ATI_RADEON_RV360_AR,	RADEON_RV350, 0 },
    331       1.1   gdamore 	{ PCI_PRODUCT_ATI_RADEON_RV350_AS,	RADEON_RV350, 0 },
    332       1.1   gdamore 	{ PCI_PRODUCT_ATI_RADEON_RV350_AT,	RADEON_RV350, 0 },
    333       1.1   gdamore 	{ PCI_PRODUCT_ATI_RADEON_RV350_AV,	RADEON_RV350, 0 },
    334       1.1   gdamore 	{ PCI_PRODUCT_ATI_RADEON_RV350_NP,	RADEON_RV350, RFB_MOB },
    335       1.1   gdamore 	{ PCI_PRODUCT_ATI_RADEON_RV350_NQ,	RADEON_RV350, RFB_MOB },
    336       1.1   gdamore 	{ PCI_PRODUCT_ATI_RADEON_RV350_NR,	RADEON_RV350, RFB_MOB },
    337       1.1   gdamore 	{ PCI_PRODUCT_ATI_RADEON_RV350_NS,	RADEON_RV350, RFB_MOB },
    338       1.1   gdamore 	{ PCI_PRODUCT_ATI_RADEON_RV350_NT,	RADEON_RV350, RFB_MOB },
    339       1.1   gdamore 	{ PCI_PRODUCT_ATI_RADEON_RV350_NV,	RADEON_RV350, RFB_MOB },
    340       1.1   gdamore 
    341       1.1   gdamore 	/* R350/R360 family */
    342       1.1   gdamore 	{ PCI_PRODUCT_ATI_RADEON_R350_AH,	RADEON_R350, 0 },
    343       1.1   gdamore 	{ PCI_PRODUCT_ATI_RADEON_R350_AI,	RADEON_R350, 0 },
    344       1.1   gdamore 	{ PCI_PRODUCT_ATI_RADEON_R350_AJ,	RADEON_R350, 0 },
    345       1.1   gdamore 	{ PCI_PRODUCT_ATI_RADEON_R350_AK,	RADEON_R350, 0 },
    346       1.1   gdamore 	{ PCI_PRODUCT_ATI_RADEON_R350_NH,	RADEON_R350, 0 },
    347       1.1   gdamore 	{ PCI_PRODUCT_ATI_RADEON_R350_NI,	RADEON_R350, 0 },
    348       1.1   gdamore 	{ PCI_PRODUCT_ATI_RADEON_R350_NK,	RADEON_R350, 0 },
    349       1.1   gdamore 	{ PCI_PRODUCT_ATI_RADEON_R360_NJ,	RADEON_R350, 0 },
    350       1.1   gdamore 
    351       1.1   gdamore 	/* RV380/RV370 family */
    352       1.1   gdamore 	{ PCI_PRODUCT_ATI_RADEON_RV380_3150,	RADEON_RV380, RFB_MOB },
    353       1.1   gdamore 	{ PCI_PRODUCT_ATI_RADEON_RV380_3154,	RADEON_RV380, RFB_MOB },
    354       1.1   gdamore 	{ PCI_PRODUCT_ATI_RADEON_RV380_3E50,	RADEON_RV380, 0 },
    355       1.1   gdamore 	{ PCI_PRODUCT_ATI_RADEON_RV380_3E54,	RADEON_RV380, 0 },
    356       1.1   gdamore 	{ PCI_PRODUCT_ATI_RADEON_RV370_5460,	RADEON_RV380, RFB_MOB },
    357       1.1   gdamore 	{ PCI_PRODUCT_ATI_RADEON_RV370_5464,	RADEON_RV380, RFB_MOB },
    358       1.1   gdamore 	{ PCI_PRODUCT_ATI_RADEON_RV370_5B60,	RADEON_RV380, 0 },
    359      1.74  macallan 	{ PCI_PRODUCT_ATI_RADEON_RV370_5B63,	RADEON_RV380, 0 },
    360       1.1   gdamore 	{ PCI_PRODUCT_ATI_RADEON_RV370_5B64,	RADEON_RV380, 0 },
    361       1.1   gdamore 	{ PCI_PRODUCT_ATI_RADEON_RV370_5B65,	RADEON_RV380, 0 },
    362       1.1   gdamore 
    363      1.71  macallan #if notyet
    364       1.1   gdamore 	/* R420/R423 family */
    365       1.1   gdamore 	{ PCI_PRODUCT_ATI_RADEON_R420_JH,	RADEON_R420, 0 },
    366       1.1   gdamore 	{ PCI_PRODUCT_ATI_RADEON_R420_JI,	RADEON_R420, 0 },
    367       1.1   gdamore 	{ PCI_PRODUCT_ATI_RADEON_R420_JJ,	RADEON_R420, 0 },
    368       1.1   gdamore 	{ PCI_PRODUCT_ATI_RADEON_R420_JK,	RADEON_R420, 0 },
    369       1.1   gdamore 	{ PCI_PRODUCT_ATI_RADEON_R420_JL,	RADEON_R420, 0 },
    370       1.1   gdamore 	{ PCI_PRODUCT_ATI_RADEON_R420_JM,	RADEON_R420, 0 },
    371       1.1   gdamore 	{ PCI_PRODUCT_ATI_RADEON_R420_JN,	RADEON_R420, RFB_MOB },
    372       1.1   gdamore 	{ PCI_PRODUCT_ATI_RADEON_R420_JP,	RADEON_R420, 0 },
    373       1.1   gdamore 	{ PCI_PRODUCT_ATI_RADEON_R423_UH,	RADEON_R420, 0 },
    374       1.1   gdamore 	{ PCI_PRODUCT_ATI_RADEON_R423_UI,	RADEON_R420, 0 },
    375       1.1   gdamore 	{ PCI_PRODUCT_ATI_RADEON_R423_UJ,	RADEON_R420, 0 },
    376       1.1   gdamore 	{ PCI_PRODUCT_ATI_RADEON_R423_UK,	RADEON_R420, 0 },
    377       1.1   gdamore 	{ PCI_PRODUCT_ATI_RADEON_R423_UQ,	RADEON_R420, 0 },
    378       1.1   gdamore 	{ PCI_PRODUCT_ATI_RADEON_R423_UR,	RADEON_R420, 0 },
    379       1.1   gdamore 	{ PCI_PRODUCT_ATI_RADEON_R423_UT,	RADEON_R420, 0 },
    380       1.1   gdamore 	{ PCI_PRODUCT_ATI_RADEON_R423_5D57,	RADEON_R420, 0 },
    381      1.22       bjs 	{ PCI_PRODUCT_ATI_RADEON_R430_554F,	RADEON_R420, 0 },
    382      1.71  macallan #endif
    383       1.1   gdamore 	{ 0, 0, 0 }
    384       1.1   gdamore };
    385       1.1   gdamore 
    386       1.1   gdamore static struct {
    387       1.1   gdamore 	int divider;
    388       1.1   gdamore 	int mask;
    389       1.1   gdamore } radeonfb_dividers[] = {
    390      1.69  macallan 	{ 16, 5 },
    391      1.69  macallan 	{ 12, 7 },
    392      1.69  macallan 	{  8, 3 },
    393      1.69  macallan 	{  6, 6 },
    394      1.69  macallan 	{  4, 2 },
    395      1.69  macallan 	{  3, 4 },
    396      1.69  macallan 	{  2, 1 },
    397       1.1   gdamore 	{  1, 0 },
    398       1.1   gdamore 	{  0, 0 }
    399       1.1   gdamore };
    400       1.1   gdamore 
    401       1.1   gdamore /*
    402       1.1   gdamore  * This table taken from X11.
    403       1.1   gdamore  */
    404       1.1   gdamore static const struct {
    405       1.1   gdamore 	int			family;
    406       1.1   gdamore 	struct radeon_tmds_pll	plls[4];
    407       1.1   gdamore } radeonfb_tmds_pll[] = {
    408       1.1   gdamore 	{ RADEON_R100,	{{12000, 0xa1b}, {-1, 0xa3f}}},
    409       1.1   gdamore 	{ RADEON_RV100,	{{12000, 0xa1b}, {-1, 0xa3f}}},
    410       1.1   gdamore 	{ RADEON_RS100, {{0, 0}}},
    411       1.1   gdamore 	{ RADEON_RV200,	{{15000, 0xa1b}, {-1, 0xa3f}}},
    412       1.1   gdamore 	{ RADEON_RS200,	{{15000, 0xa1b}, {-1, 0xa3f}}},
    413       1.1   gdamore 	{ RADEON_R200,	{{15000, 0xa1b}, {-1, 0xa3f}}},
    414       1.1   gdamore 	{ RADEON_RV250,	{{15500, 0x81b}, {-1, 0x83f}}},
    415       1.1   gdamore 	{ RADEON_RS300, {{0, 0}}},
    416       1.1   gdamore 	{ RADEON_RV280,	{{13000, 0x400f4}, {15000, 0x400f7}}},
    417       1.1   gdamore 	{ RADEON_R300,	{{-1, 0xb01cb}}},
    418       1.1   gdamore 	{ RADEON_R350,	{{-1, 0xb01cb}}},
    419       1.1   gdamore 	{ RADEON_RV350,	{{15000, 0xb0155}, {-1, 0xb01cb}}},
    420       1.1   gdamore 	{ RADEON_RV380,	{{15000, 0xb0155}, {-1, 0xb01cb}}},
    421       1.1   gdamore 	{ RADEON_R420,	{{-1, 0xb01cb}}},
    422       1.1   gdamore };
    423       1.1   gdamore 
    424       1.9  macallan #define RADEONFB_BACKLIGHT_MAX    255  /* Maximum backlight level. */
    425       1.9  macallan 
    426       1.1   gdamore 
    427      1.47  macallan CFATTACH_DECL_NEW(radeonfb, sizeof (struct radeonfb_softc),
    428       1.1   gdamore     radeonfb_match, radeonfb_attach, NULL, NULL);
    429       1.1   gdamore 
    430       1.1   gdamore static int
    431      1.31    cegger radeonfb_match(device_t parent, cfdata_t match, void *aux)
    432       1.1   gdamore {
    433      1.44    dyoung 	const struct pci_attach_args	*pa = aux;
    434       1.1   gdamore 	int			i;
    435       1.1   gdamore 
    436       1.1   gdamore 	if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_ATI)
    437       1.1   gdamore 		return 0;
    438       1.1   gdamore 
    439       1.1   gdamore 	for (i = 0; radeonfb_devices[i].devid; i++) {
    440       1.1   gdamore 		if (PCI_PRODUCT(pa->pa_id) == radeonfb_devices[i].devid)
    441       1.1   gdamore 			return 100;	/* high to defeat VGA/VESA */
    442       1.1   gdamore 	}
    443       1.1   gdamore 
    444       1.1   gdamore 	return 0;
    445       1.1   gdamore }
    446       1.1   gdamore 
    447       1.1   gdamore static void
    448      1.31    cegger radeonfb_attach(device_t parent, device_t dev, void *aux)
    449       1.1   gdamore {
    450      1.33    cegger 	struct radeonfb_softc	*sc = device_private(dev);
    451      1.44    dyoung 	const struct pci_attach_args	*pa = aux;
    452       1.9  macallan 	const char		*mptr;
    453       1.1   gdamore 	bus_size_t		bsz;
    454       1.5  macallan 	pcireg_t		screg;
    455      1.34  macallan 	int			i, j, fg, bg, ul, flags;
    456       1.1   gdamore 	uint32_t		v;
    457       1.1   gdamore 
    458      1.47  macallan 	sc->sc_dev = dev;
    459       1.1   gdamore 	sc->sc_id = pa->pa_id;
    460       1.1   gdamore 	for (i = 0; radeonfb_devices[i].devid; i++) {
    461       1.1   gdamore 		if (PCI_PRODUCT(sc->sc_id) == radeonfb_devices[i].devid)
    462       1.1   gdamore 			break;
    463       1.1   gdamore 	}
    464       1.1   gdamore 
    465      1.53  drochner 	pci_aprint_devinfo(pa, NULL);
    466       1.1   gdamore 
    467      1.17  macallan 	DPRINTF((prop_dictionary_externalize(device_properties(dev))));
    468      1.17  macallan 
    469       1.1   gdamore 	KASSERT(radeonfb_devices[i].devid != 0);
    470       1.1   gdamore 	sc->sc_pt = pa->pa_tag;
    471      1.16  macallan 	sc->sc_iot = pa->pa_iot;
    472       1.1   gdamore 	sc->sc_pc = pa->pa_pc;
    473       1.1   gdamore 	sc->sc_family = radeonfb_devices[i].family;
    474       1.1   gdamore 	sc->sc_flags = radeonfb_devices[i].flags;
    475       1.1   gdamore 
    476       1.5  macallan 	/* enable memory and IO access */
    477       1.5  macallan 	screg = pci_conf_read(sc->sc_pc, sc->sc_pt, PCI_COMMAND_STATUS_REG);
    478      1.43    dyoung 	screg |= PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE;
    479       1.5  macallan 	pci_conf_write(sc->sc_pc, sc->sc_pt, PCI_COMMAND_STATUS_REG, screg);
    480       1.5  macallan 
    481       1.1   gdamore 	/*
    482       1.1   gdamore 	 * Some flags are general to entire chip families, and rather
    483       1.1   gdamore 	 * than clutter up the table with them, we go ahead and set
    484       1.1   gdamore 	 * them here.
    485       1.1   gdamore 	 */
    486       1.1   gdamore 	switch (sc->sc_family) {
    487       1.1   gdamore 	case RADEON_RS100:
    488       1.1   gdamore 	case RADEON_RS200:
    489       1.1   gdamore 		sc->sc_flags |= RFB_IGP | RFB_RV100;
    490       1.1   gdamore 		break;
    491       1.1   gdamore 
    492       1.1   gdamore 	case RADEON_RV100:
    493       1.1   gdamore 	case RADEON_RV200:
    494       1.1   gdamore 	case RADEON_RV250:
    495       1.1   gdamore 	case RADEON_RV280:
    496       1.1   gdamore 		sc->sc_flags |= RFB_RV100;
    497       1.1   gdamore 		break;
    498       1.1   gdamore 
    499       1.1   gdamore 	case RADEON_RS300:
    500       1.1   gdamore 		sc->sc_flags |= RFB_SDAC | RFB_IGP | RFB_RV100;
    501       1.1   gdamore 		break;
    502       1.1   gdamore 
    503       1.1   gdamore 	case RADEON_R300:
    504       1.1   gdamore 	case RADEON_RV350:
    505       1.1   gdamore 	case RADEON_R350:
    506       1.1   gdamore 	case RADEON_RV380:
    507       1.1   gdamore 	case RADEON_R420:
    508       1.1   gdamore 		/* newer chips */
    509       1.1   gdamore 		sc->sc_flags |= RFB_R300;
    510       1.1   gdamore 		break;
    511       1.1   gdamore 
    512       1.1   gdamore 	case RADEON_R100:
    513       1.1   gdamore 		sc->sc_flags |= RFB_NCRTC2;
    514       1.1   gdamore 		break;
    515       1.1   gdamore 	}
    516       1.1   gdamore 
    517      1.17  macallan 	if ((sc->sc_family == RADEON_RV200) ||
    518      1.17  macallan 	    (sc->sc_family == RADEON_RV250) ||
    519      1.17  macallan 	    (sc->sc_family == RADEON_RV280) ||
    520      1.17  macallan 	    (sc->sc_family == RADEON_RV350)) {
    521      1.18  macallan 		bool inverted = 0;
    522      1.17  macallan 		/* backlight level is linear */
    523      1.17  macallan 		DPRINTF(("found RV* chip, backlight is supposedly linear\n"));
    524      1.47  macallan 		prop_dictionary_get_bool(device_properties(sc->sc_dev),
    525      1.17  macallan 		    "backlight_level_reverted", &inverted);
    526      1.17  macallan 		if (inverted) {
    527      1.17  macallan 			DPRINTF(("nope, it's inverted\n"));
    528      1.17  macallan 			sc->sc_flags |= RFB_INV_BLIGHT;
    529      1.17  macallan 		}
    530      1.17  macallan 	} else
    531      1.17  macallan 		sc->sc_flags |= RFB_INV_BLIGHT;
    532      1.17  macallan 
    533       1.1   gdamore 	/*
    534       1.1   gdamore 	 * XXX: to support true multihead, this must change.
    535       1.1   gdamore 	 */
    536       1.1   gdamore 	sc->sc_ndisplays = 1;
    537       1.1   gdamore 
    538       1.1   gdamore 	/* XXX: */
    539       1.1   gdamore 	if (!HAS_CRTC2(sc)) {
    540       1.1   gdamore 		sc->sc_ndisplays = 1;
    541       1.1   gdamore 	}
    542       1.1   gdamore 
    543       1.1   gdamore 	if (pci_mapreg_map(pa, RADEON_MAPREG_MMIO, PCI_MAPREG_TYPE_MEM,	0,
    544       1.1   gdamore 		&sc->sc_regt, &sc->sc_regh, &sc->sc_regaddr,
    545       1.1   gdamore 		&sc->sc_regsz) != 0) {
    546       1.1   gdamore 		aprint_error("%s: unable to map registers!\n", XNAME(sc));
    547       1.1   gdamore 		goto error;
    548       1.1   gdamore 	}
    549       1.1   gdamore 
    550      1.34  macallan 	if (pci_mapreg_info(sc->sc_pc, sc->sc_pt, PCI_MAPREG_ROM,
    551      1.34  macallan 	     PCI_MAPREG_TYPE_ROM, &sc->sc_romaddr, &sc->sc_romsz, &flags) != 0)
    552      1.34  macallan 	{
    553      1.34  macallan 		aprint_error("%s: unable to find ROM!\n", XNAME(sc));
    554      1.34  macallan 		goto error;
    555      1.34  macallan 	}
    556      1.34  macallan 	sc->sc_romt = sc->sc_memt;
    557      1.34  macallan 
    558      1.68  macallan 	sc->sc_mapped = TRUE;
    559      1.68  macallan 
    560       1.1   gdamore 	/* scratch register test... */
    561       1.1   gdamore 	if (radeonfb_scratch_test(sc, RADEON_BIOS_0_SCRATCH, 0x55555555) ||
    562       1.1   gdamore 	    radeonfb_scratch_test(sc, RADEON_BIOS_0_SCRATCH, 0xaaaaaaaa)) {
    563       1.1   gdamore 		aprint_error("%s: scratch register test failed!\n", XNAME(sc));
    564       1.1   gdamore 		goto error;
    565       1.1   gdamore 	}
    566       1.1   gdamore 
    567      1.66  macallan 	PRINTREG(RADEON_CRTC_EXT_CNTL);
    568      1.66  macallan 	PRINTREG(RADEON_CRTC_GEN_CNTL);
    569      1.66  macallan 	PRINTREG(RADEON_CRTC2_GEN_CNTL);
    570      1.66  macallan 	PRINTREG(RADEON_DISP_OUTPUT_CNTL);
    571      1.66  macallan 	PRINTREG(RADEON_DAC_CNTL2);
    572      1.69  macallan 	PRINTREG(RADEON_FP_GEN_CNTL);
    573      1.69  macallan 	PRINTREG(RADEON_FP2_GEN_CNTL);
    574      1.66  macallan 
    575       1.1   gdamore 	PRINTREG(RADEON_BIOS_4_SCRATCH);
    576       1.1   gdamore 	PRINTREG(RADEON_FP_GEN_CNTL);
    577      1.36  macallan 	sc->sc_fp_gen_cntl = GET32(sc, RADEON_FP_GEN_CNTL);
    578       1.1   gdamore 	PRINTREG(RADEON_FP2_GEN_CNTL);
    579       1.1   gdamore 	PRINTREG(RADEON_TMDS_CNTL);
    580       1.1   gdamore 	PRINTREG(RADEON_TMDS_TRANSMITTER_CNTL);
    581       1.1   gdamore 	PRINTREG(RADEON_TMDS_PLL_CNTL);
    582       1.1   gdamore 	PRINTREG(RADEON_LVDS_GEN_CNTL);
    583       1.1   gdamore 	PRINTREG(RADEON_FP_HORZ_STRETCH);
    584       1.1   gdamore 	PRINTREG(RADEON_FP_VERT_STRETCH);
    585       1.1   gdamore 
    586      1.69  macallan 	if (IS_RV100(sc))
    587      1.69  macallan 		PUT32(sc, RADEON_TMDS_PLL_CNTL, 0xa27);
    588       1.1   gdamore 
    589      1.69  macallan 	/* XXX
    590      1.69  macallan 	 * according to xf86-video-radeon R3xx has this bit backwards
    591      1.69  macallan 	 */
    592      1.69  macallan 	if (IS_R300(sc)) {
    593      1.69  macallan 		PATCH32(sc, RADEON_TMDS_TRANSMITTER_CNTL,
    594      1.69  macallan 		    0,
    595      1.69  macallan 		    ~(RADEON_TMDS_TRANSMITTER_PLLEN | RADEON_TMDS_TRANSMITTER_PLLRST));
    596      1.69  macallan 	} else {
    597      1.69  macallan 		PATCH32(sc, RADEON_TMDS_TRANSMITTER_CNTL,
    598      1.69  macallan 		    RADEON_TMDS_TRANSMITTER_PLLEN,
    599      1.69  macallan 		    ~(RADEON_TMDS_TRANSMITTER_PLLEN | RADEON_TMDS_TRANSMITTER_PLLRST));
    600      1.69  macallan 	}
    601      1.69  macallan 
    602       1.1   gdamore 	radeonfb_i2c_init(sc);
    603       1.1   gdamore 
    604       1.1   gdamore 	radeonfb_loadbios(sc, pa);
    605       1.1   gdamore 
    606      1.39  macallan #ifdef	RADEONFB_BIOS_INIT
    607       1.1   gdamore 	if (radeonfb_bios_init(sc)) {
    608       1.1   gdamore 		aprint_error("%s: BIOS inititialization failed\n", XNAME(sc));
    609       1.1   gdamore 	}
    610       1.1   gdamore #endif
    611       1.1   gdamore 
    612       1.1   gdamore 	if (radeonfb_getclocks(sc)) {
    613       1.1   gdamore 		aprint_error("%s: Unable to get reference clocks from BIOS\n",
    614       1.1   gdamore 		    XNAME(sc));
    615       1.1   gdamore 		goto error;
    616       1.1   gdamore 	}
    617       1.1   gdamore 
    618       1.1   gdamore 	if (radeonfb_gettmds(sc)) {
    619       1.1   gdamore 		aprint_error("%s: Unable to identify TMDS PLL settings\n",
    620       1.1   gdamore 		    XNAME(sc));
    621       1.1   gdamore 		goto error;
    622       1.1   gdamore 	}
    623       1.1   gdamore 
    624       1.1   gdamore 	aprint_verbose("%s: refclk = %d.%03d MHz, refdiv = %d "
    625       1.1   gdamore 	    "minpll = %d, maxpll = %d\n", XNAME(sc),
    626       1.1   gdamore 	    (int)sc->sc_refclk / 1000, (int)sc->sc_refclk % 1000,
    627       1.1   gdamore 	    (int)sc->sc_refdiv, (int)sc->sc_minpll, (int)sc->sc_maxpll);
    628       1.1   gdamore 
    629       1.1   gdamore 	radeonfb_getconnectors(sc);
    630       1.1   gdamore 
    631       1.1   gdamore 	radeonfb_set_fbloc(sc);
    632       1.1   gdamore 
    633  1.76.4.1     rmind 	/* 64 MB should be enough -- more just wastes map entries */
    634  1.76.4.1     rmind 	if (sc->sc_memsz > (64 << 20))
    635  1.76.4.1     rmind 		sc->sc_memsz = (64 << 20);
    636  1.76.4.1     rmind 
    637       1.1   gdamore 	for (i = 0; radeonfb_limits[i].size; i++) {
    638       1.1   gdamore 		if (sc->sc_memsz >= radeonfb_limits[i].size) {
    639       1.1   gdamore 			sc->sc_maxx = radeonfb_limits[i].maxx;
    640       1.1   gdamore 			sc->sc_maxy = radeonfb_limits[i].maxy;
    641       1.1   gdamore 			sc->sc_maxbpp = radeonfb_limits[i].maxbpp;
    642       1.1   gdamore 			/* framebuffer offset, start at a 4K page */
    643       1.1   gdamore 			sc->sc_fboffset = sc->sc_memsz /
    644       1.1   gdamore 			    radeonfb_limits[i].maxdisp;
    645       1.1   gdamore 			/*
    646       1.1   gdamore 			 * we use the fbsize to figure out where we can store
    647       1.1   gdamore 			 * things like cursor data.
    648       1.1   gdamore 			 */
    649       1.1   gdamore 			sc->sc_fbsize =
    650       1.1   gdamore 			    ROUNDUP(ROUNDUP(sc->sc_maxx * sc->sc_maxbpp / 8 ,
    651       1.1   gdamore 					RADEON_STRIDEALIGN) * sc->sc_maxy,
    652       1.1   gdamore 				4096);
    653       1.1   gdamore 			break;
    654       1.1   gdamore 		}
    655       1.1   gdamore 	}
    656       1.1   gdamore 
    657       1.1   gdamore 
    658       1.1   gdamore 	radeonfb_init_misc(sc);
    659       1.1   gdamore 
    660       1.1   gdamore 	/* program the DAC wirings */
    661       1.1   gdamore 	for (i = 0; i < (HAS_CRTC2(sc) ? 2 : 1); i++) {
    662       1.1   gdamore 		switch (sc->sc_ports[i].rp_dac_type) {
    663       1.1   gdamore 		case RADEON_DAC_PRIMARY:
    664       1.1   gdamore 			PATCH32(sc, RADEON_DAC_CNTL2,
    665       1.1   gdamore 			    i ? RADEON_DAC2_DAC_CLK_SEL : 0,
    666       1.1   gdamore 			    ~RADEON_DAC2_DAC_CLK_SEL);
    667       1.1   gdamore 			break;
    668       1.1   gdamore 		case RADEON_DAC_TVDAC:
    669       1.1   gdamore 			/* we always use the TVDAC to drive a secondary analog
    670       1.1   gdamore 			 * CRT for now.  if we ever support TV-out this will
    671       1.1   gdamore 			 * have to change.
    672       1.1   gdamore 			 */
    673       1.1   gdamore 			SET32(sc, RADEON_DAC_CNTL2,
    674       1.1   gdamore 			    RADEON_DAC2_DAC2_CLK_SEL);
    675       1.1   gdamore 			PATCH32(sc, RADEON_DISP_HW_DEBUG,
    676       1.1   gdamore 			    i ? 0 : RADEON_CRT2_DISP1_SEL,
    677       1.1   gdamore 			    ~RADEON_CRT2_DISP1_SEL);
    678      1.69  macallan 			/* we're using CRTC2 for the 2nd port */
    679      1.70  macallan 			if (sc->sc_ports[i].rp_number == 1) {
    680      1.69  macallan 				PATCH32(sc, RADEON_DISP_OUTPUT_CNTL,
    681      1.69  macallan 				    RADEON_DISP_DAC2_SOURCE_CRTC2,
    682      1.69  macallan 				    ~RADEON_DISP_DAC2_SOURCE_MASK);
    683      1.69  macallan 			}
    684      1.69  macallan 
    685       1.1   gdamore 			break;
    686       1.1   gdamore 		}
    687      1.70  macallan 		DPRINTF(("%s: port %d tmds type %d\n", __func__, i,
    688      1.70  macallan 		    sc->sc_ports[i].rp_tmds_type));
    689      1.69  macallan 		switch (sc->sc_ports[i].rp_tmds_type) {
    690      1.69  macallan 		case RADEON_TMDS_INT:
    691      1.69  macallan 			/* point FP0 at the CRTC this port uses */
    692      1.70  macallan 			DPRINTF(("%s: plugging internal TMDS into CRTC %d\n",
    693      1.70  macallan 			    __func__, sc->sc_ports[i].rp_number));
    694      1.69  macallan 			if (IS_R300(sc)) {
    695      1.69  macallan 				PATCH32(sc, RADEON_FP_GEN_CNTL,
    696      1.69  macallan 				    sc->sc_ports[i].rp_number ?
    697      1.69  macallan 				      R200_FP_SOURCE_SEL_CRTC2 :
    698      1.69  macallan 				      R200_FP_SOURCE_SEL_CRTC1,
    699      1.69  macallan 				    ~R200_FP_SOURCE_SEL_MASK);
    700      1.69  macallan 			} else {
    701      1.69  macallan 				PATCH32(sc, RADEON_FP_GEN_CNTL,
    702      1.69  macallan 				    sc->sc_ports[i].rp_number ?
    703      1.69  macallan 				      RADEON_FP_SEL_CRTC2 :
    704      1.69  macallan 				      RADEON_FP_SEL_CRTC1,
    705      1.69  macallan 				    ~RADEON_FP_SEL_MASK);
    706      1.69  macallan 			}
    707      1.69  macallan 		}
    708       1.1   gdamore 	}
    709       1.1   gdamore 	PRINTREG(RADEON_DAC_CNTL2);
    710       1.1   gdamore 	PRINTREG(RADEON_DISP_HW_DEBUG);
    711       1.1   gdamore 
    712       1.1   gdamore 	/* other DAC programming */
    713       1.1   gdamore 	v = GET32(sc, RADEON_DAC_CNTL);
    714       1.1   gdamore 	v &= (RADEON_DAC_RANGE_CNTL_MASK | RADEON_DAC_BLANKING);
    715       1.1   gdamore 	v |= RADEON_DAC_MASK_ALL | RADEON_DAC_8BIT_EN;
    716       1.1   gdamore 	PUT32(sc, RADEON_DAC_CNTL, v);
    717       1.1   gdamore 	PRINTREG(RADEON_DAC_CNTL);
    718      1.11        ad 
    719       1.1   gdamore 	/* XXX: this may need more investigation */
    720       1.1   gdamore 	PUT32(sc, RADEON_TV_DAC_CNTL, 0x00280203);
    721       1.1   gdamore 	PRINTREG(RADEON_TV_DAC_CNTL);
    722       1.1   gdamore 
    723       1.1   gdamore 	/* enable TMDS */
    724       1.1   gdamore 	SET32(sc, RADEON_FP_GEN_CNTL,
    725       1.1   gdamore 	    RADEON_FP_TMDS_EN |
    726       1.1   gdamore 		RADEON_FP_CRTC_DONT_SHADOW_VPAR |
    727       1.1   gdamore 		RADEON_FP_CRTC_DONT_SHADOW_HEND);
    728      1.36  macallan 	/*
    729      1.36  macallan 	 * XXX
    730      1.36  macallan 	 * no idea why this is necessary - if I do not clear this bit on my
    731      1.36  macallan 	 * iBook G4 the screen remains black, even though it's already clear.
    732      1.36  macallan 	 * It needs to be set on my Sun XVR-100 for the DVI port to work
    733      1.69  macallan 	 * TODO:
    734      1.69  macallan 	 * see if this is still necessary now that CRTCs, DACs and outputs are
    735      1.69  macallan 	 * getting wired up in a halfway sane way
    736      1.36  macallan 	 */
    737      1.36  macallan 	if (sc->sc_fp_gen_cntl & RADEON_FP_SEL_CRTC2) {
    738      1.36  macallan 		SET32(sc, RADEON_FP_GEN_CNTL, RADEON_FP_SEL_CRTC2);
    739      1.69  macallan 	} else {
    740      1.36  macallan 		CLR32(sc, RADEON_FP_GEN_CNTL, RADEON_FP_SEL_CRTC2);
    741      1.69  macallan 	}
    742       1.1   gdamore 
    743       1.1   gdamore 	/*
    744       1.1   gdamore 	 * we use bus_space_map instead of pci_mapreg, because we don't
    745       1.1   gdamore 	 * need the full aperature space.  no point in wasting virtual
    746       1.1   gdamore 	 * address space we don't intend to use, right?
    747       1.1   gdamore 	 */
    748       1.1   gdamore 	if ((sc->sc_memsz < (4096 * 1024)) ||
    749       1.1   gdamore 	    (pci_mapreg_info(sc->sc_pc, sc->sc_pt, RADEON_MAPREG_VRAM,
    750       1.1   gdamore 		PCI_MAPREG_TYPE_MEM, &sc->sc_memaddr, &bsz, NULL) != 0) ||
    751       1.1   gdamore 	    (bsz < sc->sc_memsz)) {
    752       1.1   gdamore 		sc->sc_memsz = 0;
    753       1.1   gdamore 		aprint_error("%s: Bad frame buffer configuration\n",
    754       1.1   gdamore 		    XNAME(sc));
    755       1.1   gdamore 		goto error;
    756       1.1   gdamore 	}
    757       1.1   gdamore 
    758       1.1   gdamore 	sc->sc_memt = pa->pa_memt;
    759       1.1   gdamore 	if (bus_space_map(sc->sc_memt, sc->sc_memaddr, sc->sc_memsz,
    760       1.1   gdamore 		BUS_SPACE_MAP_LINEAR, &sc->sc_memh) != 0) {
    761       1.1   gdamore 		sc->sc_memsz = 0;
    762       1.1   gdamore 		aprint_error("%s: Unable to map frame buffer\n", XNAME(sc));
    763       1.1   gdamore 		goto error;
    764       1.1   gdamore 	}
    765       1.1   gdamore 
    766       1.1   gdamore 	aprint_normal("%s: %d MB aperture at 0x%08x, "
    767       1.1   gdamore 	    "%d KB registers at 0x%08x\n", XNAME(sc),
    768       1.1   gdamore 	    (int)sc->sc_memsz >> 20, (unsigned)sc->sc_memaddr,
    769       1.1   gdamore 	    (int)sc->sc_regsz >> 10, (unsigned)sc->sc_regaddr);
    770       1.1   gdamore 
    771       1.1   gdamore 	/* setup default video mode from devprop (allows PROM override) */
    772       1.1   gdamore 	sc->sc_defaultmode = radeonfb_default_mode;
    773      1.47  macallan 	if (prop_dictionary_get_cstring_nocopy(device_properties(sc->sc_dev),
    774       1.9  macallan 	    "videomode", &mptr)) {
    775       1.9  macallan 
    776       1.9  macallan 		strncpy(sc->sc_modebuf, mptr, sizeof(sc->sc_modebuf));
    777       1.9  macallan 		sc->sc_defaultmode = sc->sc_modebuf;
    778       1.1   gdamore 	}
    779       1.1   gdamore 
    780       1.1   gdamore 	/* initialize some basic display parameters */
    781       1.1   gdamore 	for (i = 0; i < sc->sc_ndisplays; i++) {
    782       1.1   gdamore 		struct radeonfb_display *dp = &sc->sc_displays[i];
    783       1.1   gdamore 		struct rasops_info *ri;
    784       1.1   gdamore 		long defattr;
    785       1.1   gdamore 		struct wsemuldisplaydev_attach_args aa;
    786      1.11        ad 
    787       1.1   gdamore 		/*
    788       1.1   gdamore 		 * Figure out how many "displays" (desktops) we are going to
    789       1.1   gdamore 		 * support.  If more than one, then each CRTC gets its own
    790       1.1   gdamore 		 * programming.
    791       1.1   gdamore 		 *
    792       1.1   gdamore 		 * XXX: this code needs to change to support mergedfb.
    793       1.1   gdamore 		 * XXX: would be nice to allow this to be overridden
    794       1.1   gdamore 		 */
    795       1.1   gdamore 		if (HAS_CRTC2(sc) && (sc->sc_ndisplays == 1)) {
    796       1.1   gdamore 			DPRINTF(("dual crtcs!\n"));
    797       1.1   gdamore 			dp->rd_ncrtcs = 2;
    798      1.69  macallan 			dp->rd_crtcs[0].rc_port =
    799      1.69  macallan 			    &sc->sc_ports[0];
    800      1.69  macallan 			dp->rd_crtcs[0].rc_number = sc->sc_ports[0].rp_number;
    801      1.69  macallan 			dp->rd_crtcs[1].rc_port =
    802      1.69  macallan 			    &sc->sc_ports[1];
    803      1.69  macallan 			dp->rd_crtcs[1].rc_number = sc->sc_ports[1].rp_number;
    804       1.1   gdamore 		} else {
    805       1.1   gdamore 			dp->rd_ncrtcs = 1;
    806      1.69  macallan 			dp->rd_crtcs[0].rc_port =
    807      1.69  macallan 			    &sc->sc_ports[i];
    808      1.69  macallan 			dp->rd_crtcs[0].rc_number = sc->sc_ports[i].rp_number;
    809       1.1   gdamore 		}
    810       1.1   gdamore 
    811       1.1   gdamore 		dp->rd_softc = sc;
    812       1.1   gdamore 		dp->rd_wsmode = WSDISPLAYIO_MODE_EMUL;
    813       1.2  macallan 		dp->rd_bpp = RADEONFB_DEFAULT_DEPTH;	/* XXX */
    814      1.49  macallan 
    815       1.1   gdamore 		/* for text mode, we pick a resolution that won't
    816       1.1   gdamore 		 * require panning */
    817       1.1   gdamore 		radeonfb_pickres(dp, &dp->rd_virtx, &dp->rd_virty, 0);
    818       1.1   gdamore 
    819       1.1   gdamore 		aprint_normal("%s: display %d: "
    820       1.8  macallan 		    "initial virtual resolution %dx%d at %d bpp\n",
    821       1.1   gdamore 		    XNAME(sc), i, dp->rd_virtx, dp->rd_virty, dp->rd_bpp);
    822  1.76.4.1     rmind 		aprint_normal_dev(sc->sc_dev, "using %d MB per display\n",
    823  1.76.4.1     rmind 		    sc->sc_fboffset >> 20);
    824       1.1   gdamore 		/* now select the *video mode* that we will use */
    825       1.1   gdamore 		for (j = 0; j < dp->rd_ncrtcs; j++) {
    826       1.1   gdamore 			const struct videomode *vmp;
    827       1.9  macallan 			vmp = radeonfb_port_mode(sc, dp->rd_crtcs[j].rc_port,
    828       1.1   gdamore 			    dp->rd_virtx, dp->rd_virty);
    829       1.8  macallan 
    830       1.8  macallan 			/*
    831       1.8  macallan 			 * virtual resolution should be at least as high as
    832       1.8  macallan 			 * physical
    833       1.8  macallan 			 */
    834       1.8  macallan 			if (dp->rd_virtx < vmp->hdisplay ||
    835       1.8  macallan 			    dp->rd_virty < vmp->vdisplay) {
    836       1.8  macallan 				dp->rd_virtx = vmp->hdisplay;
    837       1.8  macallan 				dp->rd_virty = vmp->vdisplay;
    838       1.8  macallan 			}
    839       1.8  macallan 
    840       1.1   gdamore 			dp->rd_crtcs[j].rc_videomode = *vmp;
    841       1.1   gdamore 			printf("%s: port %d: physical %dx%d %dHz\n",
    842       1.1   gdamore 			    XNAME(sc), j, vmp->hdisplay, vmp->vdisplay,
    843       1.1   gdamore 			    DIVIDE(DIVIDE(vmp->dot_clock * 1000,
    844       1.1   gdamore 				       vmp->htotal), vmp->vtotal));
    845       1.1   gdamore 		}
    846       1.1   gdamore 
    847       1.1   gdamore 		/* N.B.: radeon wants 64-byte aligned stride */
    848       1.2  macallan 		dp->rd_stride = dp->rd_virtx * dp->rd_bpp / 8;
    849       1.1   gdamore 		dp->rd_stride = ROUNDUP(dp->rd_stride, RADEON_STRIDEALIGN);
    850      1.65  macallan 		DPRINTF(("stride: %d\n", dp->rd_stride));
    851       1.1   gdamore 
    852       1.1   gdamore 		dp->rd_offset = sc->sc_fboffset * i;
    853       1.1   gdamore 		dp->rd_fbptr = (vaddr_t)bus_space_vaddr(sc->sc_memt,
    854       1.1   gdamore 		    sc->sc_memh) + dp->rd_offset;
    855  1.76.4.1     rmind 		dp->rd_curoff = sc->sc_fboffset - 4096;	/* 4KB cursor space */
    856       1.1   gdamore 		dp->rd_curptr = dp->rd_fbptr + dp->rd_curoff;
    857       1.1   gdamore 
    858       1.1   gdamore 		DPRINTF(("fpbtr = %p\n", (void *)dp->rd_fbptr));
    859       1.1   gdamore 
    860       1.1   gdamore 		switch (dp->rd_bpp) {
    861       1.1   gdamore 		case 8:
    862       1.1   gdamore 			dp->rd_format = 2;
    863       1.1   gdamore 			break;
    864       1.1   gdamore 		case 32:
    865       1.1   gdamore 			dp->rd_format = 6;
    866       1.1   gdamore 			break;
    867       1.1   gdamore 		default:
    868       1.1   gdamore 			aprint_error("%s: bad depth %d\n", XNAME(sc),
    869       1.1   gdamore 			    dp->rd_bpp);
    870       1.1   gdamore 			goto error;
    871       1.1   gdamore 		}
    872       1.1   gdamore 
    873      1.45     njoly 		DPRINTF(("init engine\n"));
    874       1.2  macallan 		/* XXX: this seems suspicious - per display engine
    875       1.2  macallan 		   initialization? */
    876       1.2  macallan 		radeonfb_engine_init(dp);
    877       1.2  macallan 
    878       1.1   gdamore 		/* copy the template into place */
    879       1.1   gdamore 		dp->rd_wsscreens_storage[0] = radeonfb_stdscreen;
    880       1.1   gdamore 		dp->rd_wsscreens = dp->rd_wsscreens_storage;
    881       1.1   gdamore 
    882       1.1   gdamore 		/* and make up the list */
    883       1.1   gdamore 		dp->rd_wsscreenlist.nscreens = 1;
    884      1.46  christos 		dp->rd_wsscreenlist.screens = (void *)&dp->rd_wsscreens;
    885       1.8  macallan 
    886       1.1   gdamore 		vcons_init(&dp->rd_vd, dp, dp->rd_wsscreens,
    887       1.1   gdamore 		    &radeonfb_accessops);
    888       1.1   gdamore 
    889       1.1   gdamore 		dp->rd_vd.init_screen = radeonfb_init_screen;
    890       1.1   gdamore 
    891      1.64  macallan #ifdef RADEONFB_DEBUG
    892      1.64  macallan 		dp->rd_virty -= 200;
    893      1.64  macallan #endif
    894      1.64  macallan 
    895      1.34  macallan 		dp->rd_console = 0;
    896      1.47  macallan 		prop_dictionary_get_bool(device_properties(sc->sc_dev),
    897      1.34  macallan 		    "is_console", &dp->rd_console);
    898       1.1   gdamore 
    899       1.1   gdamore 		dp->rd_vscreen.scr_flags |= VCONS_SCREEN_IS_STATIC;
    900       1.1   gdamore 
    901       1.8  macallan 
    902       1.1   gdamore 		vcons_init_screen(&dp->rd_vd, &dp->rd_vscreen,
    903       1.1   gdamore 		    dp->rd_console, &defattr);
    904       1.1   gdamore 
    905       1.1   gdamore 		ri = &dp->rd_vscreen.scr_ri;
    906       1.8  macallan 
    907       1.8  macallan 		/* clear the screen */
    908       1.8  macallan 		rasops_unpack_attr(defattr, &fg, &bg, &ul);
    909      1.76  macallan 		dp->rd_bg = ri->ri_devcmap[bg & 0xf];
    910       1.8  macallan 		radeonfb_rectfill(dp, 0, 0, ri->ri_width, ri->ri_height,
    911      1.76  macallan 		    dp->rd_bg);
    912       1.8  macallan 
    913       1.1   gdamore 		dp->rd_wsscreens->textops = &ri->ri_ops;
    914       1.1   gdamore 		dp->rd_wsscreens->capabilities = ri->ri_caps;
    915       1.1   gdamore 		dp->rd_wsscreens->nrows = ri->ri_rows;
    916       1.1   gdamore 		dp->rd_wsscreens->ncols = ri->ri_cols;
    917       1.1   gdamore 
    918       1.1   gdamore #ifdef SPLASHSCREEN
    919       1.1   gdamore 		dp->rd_splash.si_depth = ri->ri_depth;
    920       1.1   gdamore 		dp->rd_splash.si_bits = ri->ri_bits;
    921       1.1   gdamore 		dp->rd_splash.si_hwbits = ri->ri_hwbits;
    922       1.1   gdamore 		dp->rd_splash.si_width = ri->ri_width;
    923       1.1   gdamore 		dp->rd_splash.si_height = ri->ri_height;
    924       1.1   gdamore 		dp->rd_splash.si_stride = ri->ri_stride;
    925       1.1   gdamore 		dp->rd_splash.si_fillrect = NULL;
    926       1.1   gdamore #endif
    927      1.54  macallan 		dp->rd_gc.gc_bitblt = radeonfb_bitblt;
    928      1.64  macallan 		dp->rd_gc.gc_rectfill = radeonfb_rectfill_a;
    929      1.54  macallan 		dp->rd_gc.gc_rop = RADEON_ROP3_S;
    930      1.54  macallan 		dp->rd_gc.gc_blitcookie = dp;
    931  1.76.4.1     rmind 		/*
    932  1.76.4.1     rmind 		 * use memory between framebuffer and cursor area as glyph
    933  1.76.4.1     rmind 		 * cache, cap at 4096 lines
    934  1.76.4.1     rmind 		 */
    935      1.54  macallan 		glyphcache_init(&dp->rd_gc, dp->rd_virty + 4,
    936  1.76.4.1     rmind 		    min(4096,
    937  1.76.4.1     rmind 		        (dp->rd_curoff / dp->rd_stride) - (dp->rd_virty + 4)),
    938      1.64  macallan 		    dp->rd_virtx,
    939      1.54  macallan 		    ri->ri_font->fontwidth,
    940      1.54  macallan 		    ri->ri_font->fontheight,
    941      1.54  macallan 		    defattr);
    942       1.1   gdamore 		if (dp->rd_console) {
    943       1.1   gdamore 
    944      1.36  macallan 			radeonfb_modeswitch(dp);
    945       1.1   gdamore 			wsdisplay_cnattach(dp->rd_wsscreens, ri, 0, 0,
    946       1.1   gdamore 			    defattr);
    947       1.1   gdamore #ifdef SPLASHSCREEN
    948      1.42  jmcneill 			if (splash_render(&dp->rd_splash,
    949      1.42  jmcneill 			    SPLASH_F_CENTER|SPLASH_F_FILL) == 0)
    950      1.42  jmcneill 				SCREEN_DISABLE_DRAWING(&dp->rd_vscreen);
    951      1.42  jmcneill 			else
    952       1.1   gdamore #endif
    953      1.42  jmcneill 				vcons_replay_msgbuf(&dp->rd_vscreen);
    954       1.1   gdamore 		} else {
    955       1.1   gdamore 
    956       1.1   gdamore 			/*
    957       1.1   gdamore 			 * since we're not the console we can postpone
    958       1.1   gdamore 			 * the rest until someone actually allocates a
    959       1.1   gdamore 			 * screen for us.  but we do clear the screen
    960       1.1   gdamore 			 * at least.
    961       1.1   gdamore 			 */
    962       1.1   gdamore 			memset(ri->ri_bits, 0, 1024);
    963       1.1   gdamore 
    964       1.1   gdamore 			radeonfb_modeswitch(dp);
    965       1.1   gdamore #ifdef SPLASHSCREEN
    966      1.42  jmcneill 			if (splash_render(&dp->rd_splash,
    967      1.42  jmcneill 			    SPLASH_F_CENTER|SPLASH_F_FILL) == 0)
    968      1.42  jmcneill 				SCREEN_DISABLE_DRAWING(&dp->rd_vscreen);
    969       1.1   gdamore #endif
    970       1.1   gdamore 		}
    971       1.1   gdamore 
    972       1.1   gdamore 		aa.console = dp->rd_console;
    973       1.1   gdamore 		aa.scrdata = &dp->rd_wsscreenlist;
    974       1.1   gdamore 		aa.accessops = &radeonfb_accessops;
    975       1.1   gdamore 		aa.accesscookie = &dp->rd_vd;
    976       1.1   gdamore 
    977      1.47  macallan 		config_found(sc->sc_dev, &aa, wsemuldisplaydevprint);
    978      1.36  macallan 
    979       1.2  macallan 		radeonfb_blank(dp, 0);
    980      1.59  macallan 
    981       1.9  macallan 		/* Initialise delayed lvds operations for backlight. */
    982      1.15        ad 		callout_init(&dp->rd_bl_lvds_co, 0);
    983       1.9  macallan 		callout_setfunc(&dp->rd_bl_lvds_co,
    984       1.9  macallan 				radeonfb_lvds_callout, dp);
    985      1.59  macallan 		dp->rd_bl_on = 1;
    986      1.59  macallan 		dp->rd_bl_level = radeonfb_get_backlight(dp);
    987      1.59  macallan 		radeonfb_set_backlight(dp, dp->rd_bl_level);
    988       1.1   gdamore 	}
    989       1.1   gdamore 
    990      1.72  macallan 	for (i = 0; i < RADEON_NDISPLAYS; i++)
    991      1.70  macallan 		radeonfb_init_palette(&sc->sc_displays[i]);
    992      1.70  macallan 
    993      1.66  macallan 	if (HAS_CRTC2(sc)) {
    994      1.66  macallan 		CLR32(sc, RADEON_CRTC2_GEN_CNTL, RADEON_CRTC2_DISP_DIS);
    995      1.66  macallan 	}
    996      1.70  macallan 
    997      1.69  macallan 	CLR32(sc, RADEON_CRTC_EXT_CNTL, RADEON_CRTC_DISPLAY_DIS);
    998      1.69  macallan 	SET32(sc, RADEON_FP_GEN_CNTL, RADEON_FP_FPON);
    999      1.34  macallan 	pmf_event_register(dev, PMFE_DISPLAY_BRIGHTNESS_UP,
   1000      1.34  macallan 	    radeonfb_brightness_up, TRUE);
   1001      1.34  macallan 	pmf_event_register(dev, PMFE_DISPLAY_BRIGHTNESS_DOWN,
   1002      1.34  macallan 	    radeonfb_brightness_down, TRUE);
   1003      1.34  macallan 
   1004      1.14  macallan 	config_found_ia(dev, "drm", aux, radeonfb_drm_print);
   1005      1.14  macallan 
   1006      1.66  macallan 	PRINTREG(RADEON_CRTC_EXT_CNTL);
   1007      1.66  macallan 	PRINTREG(RADEON_CRTC_GEN_CNTL);
   1008      1.66  macallan 	PRINTREG(RADEON_CRTC2_GEN_CNTL);
   1009      1.66  macallan 	PRINTREG(RADEON_DISP_OUTPUT_CNTL);
   1010      1.66  macallan 	PRINTREG(RADEON_DAC_CNTL2);
   1011      1.69  macallan 	PRINTREG(RADEON_FP_GEN_CNTL);
   1012      1.69  macallan 	PRINTREG(RADEON_FP2_GEN_CNTL);
   1013      1.66  macallan 
   1014       1.1   gdamore 	return;
   1015       1.1   gdamore 
   1016       1.1   gdamore error:
   1017       1.1   gdamore 	if (sc->sc_biossz)
   1018       1.1   gdamore 		free(sc->sc_bios, M_DEVBUF);
   1019       1.1   gdamore 
   1020       1.1   gdamore 	if (sc->sc_regsz)
   1021       1.1   gdamore 		bus_space_unmap(sc->sc_regt, sc->sc_regh, sc->sc_regsz);
   1022       1.1   gdamore 
   1023       1.1   gdamore 	if (sc->sc_memsz)
   1024       1.1   gdamore 		bus_space_unmap(sc->sc_memt, sc->sc_memh, sc->sc_memsz);
   1025       1.1   gdamore }
   1026       1.1   gdamore 
   1027      1.56  macallan static void
   1028      1.56  macallan radeonfb_map(struct radeonfb_softc *sc)
   1029      1.56  macallan {
   1030      1.68  macallan 	if (!sc->sc_mapped) {
   1031      1.68  macallan 		if (bus_space_map(sc->sc_regt, sc->sc_regaddr, sc->sc_regsz, 0,
   1032      1.68  macallan 		    &sc->sc_regh) != 0) {
   1033      1.68  macallan 			aprint_error_dev(sc->sc_dev,
   1034      1.68  macallan 			    "unable to map registers!\n");
   1035      1.68  macallan 			return;
   1036      1.68  macallan 		}
   1037      1.68  macallan 		if (bus_space_map(sc->sc_memt, sc->sc_memaddr, sc->sc_memsz,
   1038      1.68  macallan 		    BUS_SPACE_MAP_LINEAR, &sc->sc_memh) != 0) {
   1039      1.68  macallan 			sc->sc_memsz = 0;
   1040      1.68  macallan 			aprint_error_dev(sc->sc_dev,
   1041      1.68  macallan 			    "Unable to map frame buffer\n");
   1042      1.68  macallan 			return;
   1043      1.68  macallan 		}
   1044      1.68  macallan 		sc->sc_mapped = TRUE;
   1045      1.56  macallan 	}
   1046      1.56  macallan }
   1047      1.56  macallan 
   1048      1.56  macallan static void
   1049      1.56  macallan radeonfb_unmap(struct radeonfb_softc *sc)
   1050      1.56  macallan {
   1051      1.68  macallan 	if (sc->sc_mapped) {
   1052      1.68  macallan 		bus_space_unmap(sc->sc_regt, sc->sc_regh, sc->sc_regsz);
   1053      1.68  macallan 		bus_space_unmap(sc->sc_memt, sc->sc_memh, sc->sc_memsz);
   1054      1.68  macallan 		sc->sc_mapped = FALSE;
   1055      1.68  macallan 	}
   1056      1.56  macallan }
   1057      1.56  macallan 
   1058      1.14  macallan static int
   1059      1.14  macallan radeonfb_drm_print(void *aux, const char *pnp)
   1060      1.14  macallan {
   1061      1.14  macallan 	if (pnp)
   1062      1.28  jmcneill 		aprint_normal("drm at %s", pnp);
   1063      1.28  jmcneill 	return (UNCONF);
   1064      1.14  macallan }
   1065      1.14  macallan 
   1066       1.1   gdamore int
   1067       1.1   gdamore radeonfb_ioctl(void *v, void *vs,
   1068      1.12  christos     unsigned long cmd, void *d, int flag, struct lwp *l)
   1069       1.1   gdamore {
   1070       1.1   gdamore 	struct vcons_data	*vd;
   1071       1.1   gdamore 	struct radeonfb_display	*dp;
   1072       1.1   gdamore 	struct radeonfb_softc	*sc;
   1073       1.9  macallan 	struct wsdisplay_param  *param;
   1074  1.76.4.1     rmind 	struct vcons_screen 	*ms;
   1075       1.1   gdamore 
   1076       1.1   gdamore 	vd = (struct vcons_data *)v;
   1077  1.76.4.1     rmind 	ms = vd->active;
   1078       1.1   gdamore 	dp = (struct radeonfb_display *)vd->cookie;
   1079       1.1   gdamore 	sc = dp->rd_softc;
   1080       1.1   gdamore 
   1081  1.76.4.1     rmind 	/* can't do these without registers being mapped */
   1082  1.76.4.1     rmind 	if (!sc->sc_mapped) {
   1083  1.76.4.1     rmind 		switch (cmd) {
   1084  1.76.4.1     rmind 			case WSDISPLAYIO_GVIDEO:
   1085  1.76.4.1     rmind 			case WSDISPLAYIO_SVIDEO:
   1086  1.76.4.1     rmind 			case WSDISPLAYIO_GETCMAP:
   1087  1.76.4.1     rmind 			case WSDISPLAYIO_PUTCMAP:
   1088  1.76.4.1     rmind 			case WSDISPLAYIO_SCURSOR:
   1089  1.76.4.1     rmind 			case WSDISPLAYIO_GCURPOS:
   1090  1.76.4.1     rmind 			case WSDISPLAYIO_SCURPOS:
   1091  1.76.4.1     rmind 			case WSDISPLAYIO_SETPARAM:
   1092  1.76.4.1     rmind 				return EINVAL;
   1093  1.76.4.1     rmind 		}
   1094  1.76.4.1     rmind 	}
   1095  1.76.4.1     rmind 
   1096       1.1   gdamore 	switch (cmd) {
   1097       1.1   gdamore 	case WSDISPLAYIO_GTYPE:
   1098       1.1   gdamore 		*(unsigned *)d = WSDISPLAY_TYPE_PCIMISC;
   1099       1.1   gdamore 		return 0;
   1100       1.1   gdamore 
   1101       1.1   gdamore 	case WSDISPLAYIO_GINFO:
   1102       1.1   gdamore 		if (vd->active != NULL) {
   1103       1.1   gdamore 			struct wsdisplay_fbinfo *fb;
   1104       1.1   gdamore 			fb = (struct wsdisplay_fbinfo *)d;
   1105      1.11        ad 			fb->width = dp->rd_virtx;
   1106      1.11        ad 			fb->height = dp->rd_virty;
   1107       1.1   gdamore 			fb->depth = dp->rd_bpp;
   1108       1.1   gdamore 			fb->cmsize = 256;
   1109       1.1   gdamore 			return 0;
   1110       1.1   gdamore 		} else
   1111       1.1   gdamore 			return ENODEV;
   1112       1.1   gdamore 	case WSDISPLAYIO_GVIDEO:
   1113       1.1   gdamore 		if (radeonfb_isblank(dp))
   1114       1.1   gdamore 			*(unsigned *)d = WSDISPLAYIO_VIDEO_OFF;
   1115       1.1   gdamore 		else
   1116       1.1   gdamore 			*(unsigned *)d = WSDISPLAYIO_VIDEO_ON;
   1117       1.1   gdamore 		return 0;
   1118       1.1   gdamore 
   1119       1.1   gdamore 	case WSDISPLAYIO_SVIDEO:
   1120       1.1   gdamore 		radeonfb_blank(dp,
   1121       1.1   gdamore 		    (*(unsigned int *)d == WSDISPLAYIO_VIDEO_OFF));
   1122       1.1   gdamore 		return 0;
   1123       1.1   gdamore 
   1124       1.1   gdamore 	case WSDISPLAYIO_GETCMAP:
   1125       1.1   gdamore 		if (dp->rd_bpp == 8)
   1126  1.76.4.1     rmind 			return radeonfb_getcmap(dp,
   1127       1.1   gdamore 			    (struct wsdisplay_cmap *)d);
   1128       1.1   gdamore 		return EINVAL;
   1129      1.11        ad 
   1130       1.1   gdamore 	case WSDISPLAYIO_PUTCMAP:
   1131       1.1   gdamore 		if (dp->rd_bpp == 8)
   1132  1.76.4.1     rmind 			return radeonfb_putcmap(dp,
   1133       1.1   gdamore 			    (struct wsdisplay_cmap *)d);
   1134       1.1   gdamore 		return EINVAL;
   1135      1.11        ad 
   1136       1.1   gdamore 	case WSDISPLAYIO_LINEBYTES:
   1137       1.1   gdamore 		*(unsigned *)d = dp->rd_stride;
   1138       1.1   gdamore 		return 0;
   1139       1.1   gdamore 
   1140       1.1   gdamore 	case WSDISPLAYIO_SMODE:
   1141       1.1   gdamore 		if (*(int *)d != dp->rd_wsmode) {
   1142       1.1   gdamore 			dp->rd_wsmode = *(int *)d;
   1143  1.76.4.1     rmind 			if ((dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) ||
   1144  1.76.4.1     rmind 			    (dp->rd_wsmode == WSDISPLAYIO_MODE_DUMBFB))
   1145  1.76.4.1     rmind 				radeonfb_map(sc);
   1146  1.76.4.1     rmind 
   1147       1.1   gdamore 			if ((dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) &&
   1148       1.1   gdamore 			    (dp->rd_vd.active)) {
   1149      1.17  macallan 				radeonfb_engine_init(dp);
   1150      1.54  macallan 				glyphcache_wipe(&dp->rd_gc);
   1151      1.70  macallan 				radeonfb_init_palette(dp);
   1152      1.36  macallan 				radeonfb_modeswitch(dp);
   1153      1.76  macallan 				radeonfb_rectfill(dp, 0, 0, dp->rd_virtx,
   1154      1.76  macallan 				    dp->rd_virty, dp->rd_bg);
   1155       1.1   gdamore 				vcons_redraw_screen(dp->rd_vd.active);
   1156       1.1   gdamore 			}
   1157  1.76.4.1     rmind 			if (dp->rd_wsmode == WSDISPLAYIO_MODE_MAPPED)
   1158  1.76.4.1     rmind 				radeonfb_unmap(sc);
   1159       1.1   gdamore 		}
   1160       1.1   gdamore 		return 0;
   1161       1.1   gdamore 
   1162       1.1   gdamore 	case WSDISPLAYIO_GCURMAX:
   1163       1.1   gdamore 		((struct wsdisplay_curpos *)d)->x = RADEON_CURSORMAXX;
   1164       1.1   gdamore 		((struct wsdisplay_curpos *)d)->y = RADEON_CURSORMAXY;
   1165       1.1   gdamore 		return 0;
   1166       1.1   gdamore 
   1167       1.1   gdamore 	case WSDISPLAYIO_SCURSOR:
   1168       1.1   gdamore 		return radeonfb_set_cursor(dp, (struct wsdisplay_cursor *)d);
   1169       1.1   gdamore 
   1170       1.1   gdamore 	case WSDISPLAYIO_GCURSOR:
   1171       1.1   gdamore 		return EPASSTHROUGH;
   1172       1.1   gdamore 
   1173       1.1   gdamore 	case WSDISPLAYIO_GCURPOS:
   1174       1.1   gdamore 		((struct wsdisplay_curpos *)d)->x = dp->rd_cursor.rc_pos.x;
   1175       1.1   gdamore 		((struct wsdisplay_curpos *)d)->y = dp->rd_cursor.rc_pos.y;
   1176       1.1   gdamore 		return 0;
   1177       1.1   gdamore 
   1178       1.1   gdamore 	case WSDISPLAYIO_SCURPOS:
   1179       1.1   gdamore 		return radeonfb_set_curpos(dp, (struct wsdisplay_curpos *)d);
   1180       1.1   gdamore 
   1181       1.1   gdamore 	case WSDISPLAYIO_SSPLASH:
   1182       1.1   gdamore #if defined(SPLASHSCREEN)
   1183       1.1   gdamore 		if (*(int *)d == 1) {
   1184       1.1   gdamore 			SCREEN_DISABLE_DRAWING(&dp->rd_vscreen);
   1185       1.1   gdamore 			splash_render(&dp->rd_splash,
   1186       1.1   gdamore 			    SPLASH_F_CENTER|SPLASH_F_FILL);
   1187       1.1   gdamore 		} else
   1188       1.1   gdamore 			SCREEN_ENABLE_DRAWING(&dp->rd_vscreen);
   1189       1.1   gdamore 		return 0;
   1190       1.1   gdamore #else
   1191       1.1   gdamore 		return ENODEV;
   1192       1.1   gdamore #endif
   1193       1.9  macallan 	case WSDISPLAYIO_GETPARAM:
   1194       1.9  macallan 		param = (struct wsdisplay_param *)d;
   1195      1.59  macallan 		switch (param->param) {
   1196      1.59  macallan 		case WSDISPLAYIO_PARAM_BRIGHTNESS:
   1197      1.59  macallan 			param->min = 0;
   1198      1.59  macallan 			param->max = 255;
   1199      1.59  macallan 			param->curval = dp->rd_bl_level;
   1200      1.59  macallan 			return 0;
   1201      1.59  macallan 		case WSDISPLAYIO_PARAM_BACKLIGHT:
   1202       1.9  macallan 			param->min = 0;
   1203       1.9  macallan 			param->max = RADEONFB_BACKLIGHT_MAX;
   1204      1.59  macallan 			param->curval = dp->rd_bl_on;
   1205       1.9  macallan 			return 0;
   1206       1.9  macallan 		}
   1207       1.9  macallan 		return EPASSTHROUGH;
   1208       1.9  macallan 
   1209       1.9  macallan 	case WSDISPLAYIO_SETPARAM:
   1210       1.9  macallan 		param = (struct wsdisplay_param *)d;
   1211      1.59  macallan 		switch (param->param) {
   1212      1.59  macallan 		case WSDISPLAYIO_PARAM_BRIGHTNESS:
   1213      1.59  macallan 			radeonfb_set_backlight(dp, param->curval);
   1214      1.59  macallan 			return 0;
   1215      1.59  macallan 		case WSDISPLAYIO_PARAM_BACKLIGHT:
   1216      1.59  macallan 			radeonfb_switch_backlight(dp,  param->curval);
   1217      1.59  macallan 			return 0;
   1218       1.9  macallan 		}
   1219       1.9  macallan 		return EPASSTHROUGH;
   1220       1.1   gdamore 
   1221      1.26       phx 	/* PCI config read/write passthrough. */
   1222      1.26       phx 	case PCI_IOC_CFGREAD:
   1223      1.26       phx 	case PCI_IOC_CFGWRITE:
   1224      1.40    cegger 		return pci_devioctl(sc->sc_pc, sc->sc_pt, cmd, d, flag, l);
   1225      1.26       phx 
   1226      1.41    cegger 	case WSDISPLAYIO_GET_BUSID:
   1227      1.47  macallan 		return wsdisplayio_busid_pci(sc->sc_dev, sc->sc_pc,
   1228      1.41    cegger 		    sc->sc_pt, d);
   1229      1.41    cegger 
   1230      1.48  macallan 	case WSDISPLAYIO_GET_EDID: {
   1231      1.48  macallan 		struct wsdisplayio_edid_info *ei = d;
   1232      1.48  macallan 		return wsdisplayio_get_edid(sc->sc_dev, ei);
   1233      1.48  macallan 	}
   1234      1.48  macallan 
   1235  1.76.4.1     rmind 	case WSDISPLAYIO_GET_FBINFO: {
   1236  1.76.4.1     rmind 		struct wsdisplayio_fbinfo *fbi = d;
   1237  1.76.4.1     rmind 		return wsdisplayio_get_fbinfo(&ms->scr_ri, fbi);
   1238  1.76.4.1     rmind 	}
   1239  1.76.4.1     rmind 
   1240       1.1   gdamore 	default:
   1241       1.1   gdamore 		return EPASSTHROUGH;
   1242       1.1   gdamore 	}
   1243       1.1   gdamore }
   1244       1.1   gdamore 
   1245       1.1   gdamore paddr_t
   1246       1.1   gdamore radeonfb_mmap(void *v, void *vs, off_t offset, int prot)
   1247       1.1   gdamore {
   1248       1.1   gdamore 	struct vcons_data	*vd;
   1249       1.1   gdamore 	struct radeonfb_display	*dp;
   1250       1.1   gdamore 	struct radeonfb_softc	*sc;
   1251       1.1   gdamore 	paddr_t			pa;
   1252       1.1   gdamore 
   1253       1.1   gdamore 	vd = (struct vcons_data *)v;
   1254       1.1   gdamore 	dp = (struct radeonfb_display *)vd->cookie;
   1255       1.1   gdamore 	sc = dp->rd_softc;
   1256       1.1   gdamore 
   1257       1.1   gdamore 	/* XXX: note that we don't allow mapping of registers right now */
   1258       1.1   gdamore 	/* XXX: this means that the XFree86 radeon driver won't work */
   1259       1.1   gdamore 	if ((offset >= 0) && (offset < (dp->rd_virty * dp->rd_stride))) {
   1260       1.1   gdamore 		pa = bus_space_mmap(sc->sc_memt,
   1261       1.1   gdamore 		    sc->sc_memaddr + dp->rd_offset + offset, 0,
   1262       1.1   gdamore 		    prot, BUS_SPACE_MAP_LINEAR);
   1263       1.1   gdamore 		return pa;
   1264       1.1   gdamore 	}
   1265       1.1   gdamore 
   1266       1.3  macallan #ifdef RADEONFB_MMAP_BARS
   1267       1.5  macallan 	/*
   1268       1.5  macallan 	 * restrict all other mappings to processes with superuser privileges
   1269       1.5  macallan 	 * or the kernel itself
   1270       1.5  macallan 	 */
   1271      1.58      elad 	if (kauth_authorize_machdep(kauth_cred_get(), KAUTH_MACHDEP_UNMANAGEDMEM,
   1272      1.58      elad 	    NULL, NULL, NULL, NULL) != 0) {
   1273      1.47  macallan 		aprint_error_dev(sc->sc_dev, "mmap() rejected.\n");
   1274      1.32      elad 		return -1;
   1275       1.5  macallan 	}
   1276       1.5  macallan 
   1277      1.11        ad 	if ((offset >= sc->sc_regaddr) &&
   1278       1.3  macallan 	    (offset < sc->sc_regaddr + sc->sc_regsz)) {
   1279      1.11        ad 		return bus_space_mmap(sc->sc_regt, offset, 0, prot,
   1280       1.3  macallan 		    BUS_SPACE_MAP_LINEAR);
   1281       1.3  macallan 	}
   1282       1.3  macallan 
   1283      1.11        ad 	if ((offset >= sc->sc_memaddr) &&
   1284       1.3  macallan 	    (offset < sc->sc_memaddr + sc->sc_memsz)) {
   1285      1.11        ad 		return bus_space_mmap(sc->sc_memt, offset, 0, prot,
   1286       1.3  macallan 		    BUS_SPACE_MAP_LINEAR);
   1287       1.3  macallan 	}
   1288       1.5  macallan 
   1289      1.34  macallan 	if ((offset >= sc->sc_romaddr) &&
   1290      1.34  macallan 	    (offset < sc->sc_romaddr + sc->sc_romsz)) {
   1291      1.34  macallan 		return bus_space_mmap(sc->sc_memt, offset, 0, prot,
   1292      1.34  macallan 		    BUS_SPACE_MAP_LINEAR);
   1293      1.34  macallan 	}
   1294      1.34  macallan 
   1295      1.25  macallan #ifdef PCI_MAGIC_IO_RANGE
   1296       1.5  macallan 	/* allow mapping of IO space */
   1297      1.25  macallan 	if ((offset >= PCI_MAGIC_IO_RANGE) &&
   1298      1.25  macallan 	    (offset < PCI_MAGIC_IO_RANGE + 0x10000)) {
   1299      1.25  macallan 		pa = bus_space_mmap(sc->sc_iot, offset - PCI_MAGIC_IO_RANGE,
   1300      1.25  macallan 		    0, prot, 0);
   1301       1.5  macallan 		return pa;
   1302      1.11        ad 	}
   1303      1.49  macallan #endif /* PCI_MAGIC_IO_RANGE */
   1304       1.5  macallan 
   1305       1.3  macallan #endif /* RADEONFB_MMAP_BARS */
   1306       1.3  macallan 
   1307       1.1   gdamore 	return -1;
   1308       1.1   gdamore }
   1309       1.1   gdamore 
   1310       1.2  macallan static void
   1311      1.44    dyoung radeonfb_loadbios(struct radeonfb_softc *sc, const struct pci_attach_args *pa)
   1312       1.1   gdamore {
   1313       1.1   gdamore 	bus_space_tag_t		romt;
   1314       1.1   gdamore 	bus_space_handle_t	romh, biosh;
   1315       1.1   gdamore 	bus_size_t		romsz;
   1316       1.1   gdamore 	bus_addr_t		ptr;
   1317       1.1   gdamore 
   1318       1.1   gdamore 	if (pci_mapreg_map(pa, PCI_MAPREG_ROM, PCI_MAPREG_TYPE_ROM,
   1319       1.1   gdamore 		BUS_SPACE_MAP_PREFETCHABLE, &romt, &romh, NULL, &romsz) != 0) {
   1320       1.1   gdamore 		aprint_verbose("%s: unable to map BIOS!\n", XNAME(sc));
   1321       1.1   gdamore 		return;
   1322       1.1   gdamore 	}
   1323       1.1   gdamore 
   1324       1.1   gdamore 	pci_find_rom(pa, romt, romh, PCI_ROM_CODE_TYPE_X86, &biosh,
   1325       1.1   gdamore 	    &sc->sc_biossz);
   1326       1.1   gdamore 	if (sc->sc_biossz == 0) {
   1327       1.1   gdamore 		aprint_verbose("%s: Video BIOS not present\n", XNAME(sc));
   1328       1.1   gdamore 		return;
   1329       1.1   gdamore 	}
   1330       1.1   gdamore 
   1331       1.1   gdamore 	sc->sc_bios = malloc(sc->sc_biossz, M_DEVBUF, M_WAITOK);
   1332       1.1   gdamore 	bus_space_read_region_1(romt, biosh, 0, sc->sc_bios, sc->sc_biossz);
   1333       1.1   gdamore 
   1334       1.1   gdamore 	/* unmap the PCI expansion rom */
   1335       1.1   gdamore 	bus_space_unmap(romt, romh, romsz);
   1336       1.1   gdamore 
   1337       1.1   gdamore 	/* turn off rom decoder now */
   1338       1.1   gdamore 	pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM,
   1339       1.1   gdamore 	    pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM) &
   1340       1.1   gdamore 	    ~PCI_MAPREG_ROM_ENABLE);
   1341       1.1   gdamore 
   1342       1.1   gdamore 	ptr = GETBIOS16(sc, 0x48);
   1343       1.1   gdamore 	if ((GETBIOS32(sc, ptr + 4) == 0x41544f4d /* "ATOM" */) ||
   1344       1.1   gdamore 	    (GETBIOS32(sc, ptr + 4) == 0x4d4f5441 /* "MOTA" */)) {
   1345       1.1   gdamore 		sc->sc_flags |= RFB_ATOM;
   1346       1.1   gdamore 	}
   1347       1.1   gdamore 
   1348       1.1   gdamore 	aprint_verbose("%s: Found %d KB %s BIOS\n", XNAME(sc),
   1349       1.1   gdamore 	    (unsigned)sc->sc_biossz >> 10, IS_ATOM(sc) ? "ATOM" : "Legacy");
   1350       1.1   gdamore }
   1351       1.1   gdamore 
   1352       1.1   gdamore 
   1353       1.1   gdamore uint32_t
   1354       1.1   gdamore radeonfb_get32(struct radeonfb_softc *sc, uint32_t reg)
   1355       1.1   gdamore {
   1356       1.1   gdamore 
   1357       1.1   gdamore 	return bus_space_read_4(sc->sc_regt, sc->sc_regh, reg);
   1358       1.1   gdamore }
   1359       1.1   gdamore 
   1360       1.1   gdamore void
   1361       1.1   gdamore radeonfb_put32(struct radeonfb_softc *sc, uint32_t reg, uint32_t val)
   1362       1.1   gdamore {
   1363       1.1   gdamore 
   1364       1.1   gdamore 	bus_space_write_4(sc->sc_regt, sc->sc_regh, reg, val);
   1365       1.1   gdamore }
   1366       1.1   gdamore 
   1367       1.1   gdamore void
   1368      1.55  macallan radeonfb_put32s(struct radeonfb_softc *sc, uint32_t reg, uint32_t val)
   1369      1.55  macallan {
   1370      1.55  macallan 
   1371      1.55  macallan 	bus_space_write_stream_4(sc->sc_regt, sc->sc_regh, reg, val);
   1372      1.55  macallan }
   1373      1.55  macallan 
   1374      1.55  macallan void
   1375       1.1   gdamore radeonfb_mask32(struct radeonfb_softc *sc, uint32_t reg,
   1376       1.1   gdamore     uint32_t andmask, uint32_t ormask)
   1377       1.1   gdamore {
   1378       1.1   gdamore 	int		s;
   1379       1.1   gdamore 	uint32_t	val;
   1380       1.1   gdamore 
   1381       1.1   gdamore 	s = splhigh();
   1382       1.1   gdamore 	val = radeonfb_get32(sc, reg);
   1383       1.1   gdamore 	val = (val & andmask) | ormask;
   1384       1.1   gdamore 	radeonfb_put32(sc, reg, val);
   1385       1.1   gdamore 	splx(s);
   1386       1.1   gdamore }
   1387       1.1   gdamore 
   1388       1.1   gdamore uint32_t
   1389       1.1   gdamore radeonfb_getindex(struct radeonfb_softc *sc, uint32_t idx)
   1390       1.1   gdamore {
   1391       1.1   gdamore 	int		s;
   1392       1.1   gdamore 	uint32_t	val;
   1393       1.1   gdamore 
   1394       1.1   gdamore 	s = splhigh();
   1395       1.1   gdamore 	radeonfb_put32(sc, RADEON_MM_INDEX, idx);
   1396       1.1   gdamore 	val = radeonfb_get32(sc, RADEON_MM_DATA);
   1397       1.1   gdamore 	splx(s);
   1398       1.1   gdamore 
   1399       1.1   gdamore 	return (val);
   1400       1.1   gdamore }
   1401       1.1   gdamore 
   1402       1.1   gdamore void
   1403       1.1   gdamore radeonfb_putindex(struct radeonfb_softc *sc, uint32_t idx, uint32_t val)
   1404       1.1   gdamore {
   1405       1.1   gdamore 	int	s;
   1406       1.1   gdamore 
   1407       1.1   gdamore 	s = splhigh();
   1408       1.1   gdamore 	radeonfb_put32(sc, RADEON_MM_INDEX, idx);
   1409       1.1   gdamore 	radeonfb_put32(sc, RADEON_MM_DATA, val);
   1410       1.1   gdamore 	splx(s);
   1411       1.1   gdamore }
   1412       1.1   gdamore 
   1413       1.1   gdamore void
   1414       1.1   gdamore radeonfb_maskindex(struct radeonfb_softc *sc, uint32_t idx,
   1415       1.1   gdamore     uint32_t andmask, uint32_t ormask)
   1416       1.1   gdamore {
   1417       1.1   gdamore 	int		s;
   1418       1.1   gdamore 	uint32_t	val;
   1419       1.1   gdamore 
   1420       1.1   gdamore 	s = splhigh();
   1421       1.1   gdamore 	radeonfb_put32(sc, RADEON_MM_INDEX, idx);
   1422       1.1   gdamore 	val = radeonfb_get32(sc, RADEON_MM_DATA);
   1423       1.1   gdamore 	val = (val & andmask) | ormask;
   1424       1.1   gdamore 	radeonfb_put32(sc, RADEON_MM_DATA, val);
   1425       1.1   gdamore 	splx(s);
   1426       1.1   gdamore }
   1427       1.1   gdamore 
   1428       1.1   gdamore uint32_t
   1429       1.1   gdamore radeonfb_getpll(struct radeonfb_softc *sc, uint32_t idx)
   1430       1.1   gdamore {
   1431       1.1   gdamore 	int		s;
   1432       1.1   gdamore 	uint32_t	val;
   1433       1.1   gdamore 
   1434       1.1   gdamore 	s = splhigh();
   1435      1.69  macallan 	radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, (idx & 0x3f));
   1436       1.1   gdamore 	val = radeonfb_get32(sc, RADEON_CLOCK_CNTL_DATA);
   1437       1.1   gdamore 	if (HAS_R300CG(sc))
   1438       1.1   gdamore 		radeonfb_r300cg_workaround(sc);
   1439       1.1   gdamore 	splx(s);
   1440       1.1   gdamore 
   1441       1.1   gdamore 	return (val);
   1442       1.1   gdamore }
   1443       1.1   gdamore 
   1444       1.1   gdamore void
   1445       1.1   gdamore radeonfb_putpll(struct radeonfb_softc *sc, uint32_t idx, uint32_t val)
   1446       1.1   gdamore {
   1447       1.1   gdamore 	int	s;
   1448       1.1   gdamore 
   1449       1.1   gdamore 	s = splhigh();
   1450       1.1   gdamore 	radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, (idx & 0x3f) |
   1451       1.1   gdamore 	    RADEON_PLL_WR_EN);
   1452       1.1   gdamore 	radeonfb_put32(sc, RADEON_CLOCK_CNTL_DATA, val);
   1453       1.1   gdamore 	radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, 0);
   1454       1.1   gdamore 	splx(s);
   1455       1.1   gdamore }
   1456       1.1   gdamore 
   1457       1.1   gdamore void
   1458       1.1   gdamore radeonfb_maskpll(struct radeonfb_softc *sc, uint32_t idx,
   1459       1.1   gdamore     uint32_t andmask, uint32_t ormask)
   1460       1.1   gdamore {
   1461       1.1   gdamore 	int		s;
   1462       1.1   gdamore 	uint32_t	val;
   1463       1.1   gdamore 
   1464       1.1   gdamore 	s = splhigh();
   1465       1.1   gdamore 	radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, (idx & 0x3f) |
   1466       1.1   gdamore 		RADEON_PLL_WR_EN);
   1467       1.1   gdamore 	val = radeonfb_get32(sc, RADEON_CLOCK_CNTL_DATA);
   1468       1.1   gdamore 	val = (val & andmask) | ormask;
   1469       1.1   gdamore 	radeonfb_put32(sc, RADEON_CLOCK_CNTL_DATA, val);
   1470       1.1   gdamore 	radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, 0);
   1471       1.1   gdamore 	splx(s);
   1472       1.1   gdamore }
   1473       1.1   gdamore 
   1474       1.1   gdamore int
   1475       1.1   gdamore radeonfb_scratch_test(struct radeonfb_softc *sc, int reg, uint32_t v)
   1476       1.1   gdamore {
   1477       1.1   gdamore 	uint32_t	saved;
   1478       1.1   gdamore 
   1479       1.1   gdamore 	saved = GET32(sc, reg);
   1480       1.1   gdamore 	PUT32(sc, reg, v);
   1481       1.1   gdamore 	if (GET32(sc, reg) != v) {
   1482       1.1   gdamore 		return -1;
   1483       1.1   gdamore 	}
   1484       1.1   gdamore 	PUT32(sc, reg, saved);
   1485       1.1   gdamore 	return 0;
   1486       1.1   gdamore }
   1487       1.1   gdamore 
   1488       1.1   gdamore uintmax_t
   1489       1.1   gdamore radeonfb_getprop_num(struct radeonfb_softc *sc, const char *name,
   1490       1.1   gdamore     uintmax_t defval)
   1491       1.1   gdamore {
   1492       1.1   gdamore 	prop_number_t	pn;
   1493      1.47  macallan 	pn = prop_dictionary_get(device_properties(sc->sc_dev), name);
   1494       1.1   gdamore 	if (pn == NULL) {
   1495       1.1   gdamore 		return defval;
   1496       1.1   gdamore 	}
   1497       1.1   gdamore 	KASSERT(prop_object_type(pn) == PROP_TYPE_NUMBER);
   1498       1.1   gdamore 	return (prop_number_integer_value(pn));
   1499       1.1   gdamore }
   1500       1.1   gdamore 
   1501       1.1   gdamore int
   1502       1.1   gdamore radeonfb_getclocks(struct radeonfb_softc *sc)
   1503       1.1   gdamore {
   1504       1.1   gdamore 	bus_addr_t	ptr;
   1505       1.1   gdamore 	int		refclk = 0;
   1506       1.1   gdamore 	int		refdiv = 0;
   1507       1.1   gdamore 	int		minpll = 0;
   1508       1.1   gdamore 	int		maxpll = 0;
   1509       1.1   gdamore 
   1510       1.1   gdamore 	/* load initial property values if port/board provides them */
   1511       1.1   gdamore 	refclk = radeonfb_getprop_num(sc, "refclk", 0) & 0xffff;
   1512       1.1   gdamore 	refdiv = radeonfb_getprop_num(sc, "refdiv", 0) & 0xffff;
   1513       1.1   gdamore 	minpll = radeonfb_getprop_num(sc, "minpll", 0) & 0xffffffffU;
   1514       1.1   gdamore 	maxpll = radeonfb_getprop_num(sc, "maxpll", 0) & 0xffffffffU;
   1515       1.1   gdamore 
   1516      1.69  macallan 	PRINTPLL(RADEON_PPLL_REF_DIV);
   1517      1.69  macallan 	PRINTPLL(RADEON_PPLL_DIV_0);
   1518      1.69  macallan 	PRINTPLL(RADEON_PPLL_DIV_1);
   1519      1.69  macallan 	PRINTPLL(RADEON_PPLL_DIV_2);
   1520      1.69  macallan 	PRINTPLL(RADEON_PPLL_DIV_3);
   1521      1.69  macallan 	PRINTREG(RADEON_CLOCK_CNTL_INDEX);
   1522      1.69  macallan 	PRINTPLL(RADEON_P2PLL_REF_DIV);
   1523      1.69  macallan 	PRINTPLL(RADEON_P2PLL_DIV_0);
   1524      1.69  macallan 
   1525       1.1   gdamore 	if (refclk && refdiv && minpll && maxpll)
   1526       1.1   gdamore 		goto dontprobe;
   1527       1.1   gdamore 
   1528       1.1   gdamore 	if (!sc->sc_biossz) {
   1529       1.1   gdamore 		/* no BIOS */
   1530       1.1   gdamore 		aprint_verbose("%s: No video BIOS, using default clocks\n",
   1531       1.1   gdamore 		    XNAME(sc));
   1532       1.1   gdamore 		if (IS_IGP(sc))
   1533       1.1   gdamore 			refclk = refclk ? refclk : 1432;
   1534       1.1   gdamore 		else
   1535       1.1   gdamore 			refclk = refclk ? refclk : 2700;
   1536      1.20  macallan 		refdiv = refdiv ? refdiv : 12;
   1537       1.1   gdamore 		minpll = minpll ? minpll : 12500;
   1538      1.69  macallan 		/* XXX
   1539      1.69  macallan 		 * Need to check if the firmware or something programmed a
   1540      1.69  macallan 		 * higher value than this, and if so, bump it.
   1541      1.69  macallan 		 * The RV280 in my iBook is unhappy if the PLL input is less
   1542      1.69  macallan 		 * than 360MHz
   1543      1.69  macallan 		 */
   1544      1.69  macallan 		maxpll = maxpll ? maxpll : 40000/*35000*/;
   1545       1.1   gdamore 	} else if (IS_ATOM(sc)) {
   1546       1.1   gdamore 		/* ATOM BIOS */
   1547       1.1   gdamore 		ptr = GETBIOS16(sc, 0x48);
   1548       1.1   gdamore 		ptr = GETBIOS16(sc, ptr + 32);	/* aka MasterDataStart */
   1549       1.1   gdamore 		ptr = GETBIOS16(sc, ptr + 12);	/* pll info block */
   1550       1.1   gdamore 		refclk = refclk ? refclk : GETBIOS16(sc, ptr + 82);
   1551       1.1   gdamore 		minpll = minpll ? minpll : GETBIOS16(sc, ptr + 78);
   1552       1.1   gdamore 		maxpll = maxpll ? maxpll : GETBIOS16(sc, ptr + 32);
   1553       1.1   gdamore 		/*
   1554       1.1   gdamore 		 * ATOM BIOS doesn't supply a reference divider, so we
   1555       1.1   gdamore 		 * have to probe for it.
   1556       1.1   gdamore 		 */
   1557       1.1   gdamore 		if (refdiv < 2)
   1558       1.1   gdamore 			refdiv = GETPLL(sc, RADEON_PPLL_REF_DIV) &
   1559       1.1   gdamore 			    RADEON_PPLL_REF_DIV_MASK;
   1560       1.1   gdamore 		/*
   1561       1.1   gdamore 		 * if probe is zero, just assume one that should work
   1562       1.1   gdamore 		 * for most parts
   1563       1.1   gdamore 		 */
   1564       1.1   gdamore 		if (refdiv < 2)
   1565       1.1   gdamore 			refdiv = 12;
   1566      1.11        ad 
   1567       1.1   gdamore 	} else {
   1568      1.69  macallan 		uint32_t tmp = GETPLL(sc, RADEON_PPLL_REF_DIV);
   1569       1.1   gdamore 		/* Legacy BIOS */
   1570       1.1   gdamore 		ptr = GETBIOS16(sc, 0x48);
   1571       1.1   gdamore 		ptr = GETBIOS16(sc, ptr + 0x30);
   1572      1.69  macallan 		if (IS_R300(sc)) {
   1573      1.69  macallan 			refdiv = refdiv ? refdiv :
   1574      1.69  macallan 			    (tmp & R300_PPLL_REF_DIV_ACC_MASK) >>
   1575      1.69  macallan 			    R300_PPLL_REF_DIV_ACC_SHIFT;
   1576      1.69  macallan 		} else {
   1577      1.69  macallan 			refdiv = refdiv ? refdiv :
   1578      1.69  macallan 			    tmp & RADEON_PPLL_REF_DIV_MASK;
   1579      1.69  macallan 		}
   1580       1.1   gdamore 		refclk = refclk ? refclk : GETBIOS16(sc, ptr + 0x0E);
   1581       1.1   gdamore 		refdiv = refdiv ? refdiv : GETBIOS16(sc, ptr + 0x10);
   1582       1.1   gdamore 		minpll = minpll ? minpll : GETBIOS32(sc, ptr + 0x12);
   1583       1.1   gdamore 		maxpll = maxpll ? maxpll : GETBIOS32(sc, ptr + 0x16);
   1584       1.1   gdamore 	}
   1585       1.1   gdamore 
   1586       1.1   gdamore 
   1587       1.1   gdamore dontprobe:
   1588       1.1   gdamore 	sc->sc_refclk = refclk * 10;
   1589       1.1   gdamore 	sc->sc_refdiv = refdiv;
   1590       1.1   gdamore 	sc->sc_minpll = minpll * 10;
   1591       1.1   gdamore 	sc->sc_maxpll = maxpll * 10;
   1592       1.1   gdamore 	return 0;
   1593       1.1   gdamore }
   1594       1.1   gdamore 
   1595       1.1   gdamore int
   1596       1.1   gdamore radeonfb_calc_dividers(struct radeonfb_softc *sc, uint32_t dotclock,
   1597       1.1   gdamore     uint32_t *postdivbit, uint32_t *feedbackdiv)
   1598       1.1   gdamore {
   1599       1.1   gdamore 	int		i;
   1600       1.1   gdamore 	uint32_t	outfreq;
   1601       1.1   gdamore 	int		div;
   1602       1.1   gdamore 
   1603       1.1   gdamore 	DPRINTF(("dot clock: %u\n", dotclock));
   1604       1.1   gdamore 	for (i = 0; (div = radeonfb_dividers[i].divider) != 0; i++) {
   1605       1.1   gdamore 		outfreq = div * dotclock;
   1606       1.1   gdamore 		if ((outfreq >= sc->sc_minpll) &&
   1607       1.1   gdamore 		    (outfreq <= sc->sc_maxpll)) {
   1608       1.1   gdamore 			DPRINTF(("outfreq: %u\n", outfreq));
   1609       1.1   gdamore 			*postdivbit =
   1610       1.1   gdamore 			    ((uint32_t)radeonfb_dividers[i].mask << 16);
   1611       1.1   gdamore 			DPRINTF(("post divider: %d (mask %x)\n", div,
   1612       1.1   gdamore 				    *postdivbit));
   1613       1.1   gdamore 			break;
   1614       1.1   gdamore 		}
   1615       1.1   gdamore 	}
   1616       1.1   gdamore 
   1617       1.1   gdamore 	if (div == 0)
   1618       1.1   gdamore 		return 1;
   1619       1.1   gdamore 
   1620       1.1   gdamore 	*feedbackdiv = DIVIDE(sc->sc_refdiv * outfreq, sc->sc_refclk);
   1621       1.1   gdamore 	DPRINTF(("feedback divider: %d\n", *feedbackdiv));
   1622       1.1   gdamore 	return 0;
   1623       1.1   gdamore }
   1624       1.1   gdamore 
   1625       1.1   gdamore #if 0
   1626      1.36  macallan #ifdef RADEONFB_DEBUG
   1627       1.1   gdamore static void
   1628       1.1   gdamore dump_buffer(const char *pfx, void *buffer, unsigned int size)
   1629       1.1   gdamore {
   1630       1.1   gdamore 	char		asc[17];
   1631       1.1   gdamore 	unsigned	ptr = (unsigned)buffer;
   1632       1.1   gdamore 	char		*start = (char *)(ptr & ~0xf);
   1633       1.1   gdamore 	char		*end = (char *)(ptr + size);
   1634       1.1   gdamore 
   1635       1.1   gdamore 	end = (char *)(((unsigned)end + 0xf) & ~0xf);
   1636       1.1   gdamore 
   1637       1.1   gdamore 	if (pfx == NULL) {
   1638       1.1   gdamore 		pfx = "";
   1639       1.1   gdamore 	}
   1640       1.1   gdamore 
   1641       1.1   gdamore 	while (start < end) {
   1642       1.1   gdamore 		unsigned offset = (unsigned)start & 0xf;
   1643       1.1   gdamore 		if (offset == 0) {
   1644       1.1   gdamore 			printf("%s%x: ", pfx, (unsigned)start);
   1645       1.1   gdamore 		}
   1646       1.1   gdamore 		if (((unsigned)start < ptr) ||
   1647       1.1   gdamore 		    ((unsigned)start >= (ptr + size))) {
   1648       1.1   gdamore 			printf("  ");
   1649       1.1   gdamore 			asc[offset] = ' ';
   1650       1.1   gdamore 		} else {
   1651       1.1   gdamore 			printf("%02x", *(unsigned char *)start);
   1652       1.1   gdamore 			if ((*start >= ' ') && (*start <= '~')) {
   1653       1.1   gdamore 				asc[offset] = *start;
   1654       1.1   gdamore 			} else {
   1655       1.1   gdamore 				asc[offset] = '.';
   1656       1.1   gdamore 			}
   1657       1.1   gdamore 		}
   1658       1.1   gdamore 		asc[offset + 1] = 0;
   1659       1.1   gdamore 		if (offset % 2) {
   1660       1.1   gdamore 			printf(" ");
   1661       1.1   gdamore 		}
   1662       1.1   gdamore 		if (offset == 15) {
   1663       1.1   gdamore 			printf(" %s\n", asc);
   1664       1.1   gdamore 		}
   1665       1.1   gdamore 		start++;
   1666       1.1   gdamore 	}
   1667       1.1   gdamore }
   1668       1.1   gdamore #endif
   1669       1.1   gdamore #endif
   1670       1.1   gdamore 
   1671       1.1   gdamore int
   1672       1.1   gdamore radeonfb_getconnectors(struct radeonfb_softc *sc)
   1673       1.1   gdamore {
   1674       1.1   gdamore 	int	i;
   1675       1.1   gdamore 	int	found = 0;
   1676       1.1   gdamore 
   1677       1.1   gdamore 	for (i = 0; i < 2; i++) {
   1678       1.1   gdamore 		sc->sc_ports[i].rp_mon_type = RADEON_MT_UNKNOWN;
   1679       1.1   gdamore 		sc->sc_ports[i].rp_ddc_type = RADEON_DDC_NONE;
   1680       1.1   gdamore 		sc->sc_ports[i].rp_dac_type = RADEON_DAC_UNKNOWN;
   1681       1.1   gdamore 		sc->sc_ports[i].rp_conn_type = RADEON_CONN_NONE;
   1682       1.1   gdamore 		sc->sc_ports[i].rp_tmds_type = RADEON_TMDS_UNKNOWN;
   1683       1.1   gdamore 	}
   1684       1.1   gdamore 
   1685       1.1   gdamore 	/*
   1686       1.1   gdamore 	 * This logic is borrowed from Xorg's radeon driver.
   1687       1.1   gdamore 	 */
   1688       1.1   gdamore 	if (!sc->sc_biossz)
   1689       1.1   gdamore 		goto nobios;
   1690       1.1   gdamore 
   1691       1.1   gdamore 	if (IS_ATOM(sc)) {
   1692       1.1   gdamore 		/* not done yet */
   1693       1.1   gdamore 	} else {
   1694       1.1   gdamore 		uint16_t	ptr;
   1695       1.1   gdamore 		int		port = 0;
   1696       1.1   gdamore 
   1697       1.1   gdamore 		ptr = GETBIOS16(sc, 0x48);
   1698       1.1   gdamore 		ptr = GETBIOS16(sc, ptr + 0x50);
   1699       1.1   gdamore 		for (i = 1; i < 4; i++) {
   1700       1.1   gdamore 			uint16_t	entry;
   1701       1.1   gdamore 			uint8_t		conn, ddc, dac, tmds;
   1702       1.1   gdamore 
   1703       1.1   gdamore 			/*
   1704       1.1   gdamore 			 * Parse the connector table.  From reading the code,
   1705       1.1   gdamore 			 * it appears to made up of 16-bit entries for each
   1706       1.1   gdamore 			 * connector.  The 16-bits are defined as:
   1707       1.1   gdamore 			 *
   1708       1.1   gdamore 			 * bits 12-15	- connector type (0 == end of table)
   1709       1.1   gdamore 			 * bits 8-11	- DDC type
   1710       1.1   gdamore 			 * bits 5-7	- ???
   1711       1.1   gdamore 			 * bit 4	- TMDS type (1 = EXT, 0 = INT)
   1712       1.1   gdamore 			 * bits 1-3	- ???
   1713       1.1   gdamore 			 * bit 0	- DAC, 1 = TVDAC, 0 = primary
   1714       1.1   gdamore 			 */
   1715       1.1   gdamore 			if (!GETBIOS8(sc, ptr + i * 2) && i > 1)
   1716       1.1   gdamore 				break;
   1717       1.1   gdamore 			entry = GETBIOS16(sc, ptr + i * 2);
   1718       1.1   gdamore 
   1719       1.1   gdamore 			conn = (entry >> 12) & 0xf;
   1720       1.1   gdamore 			ddc = (entry >> 8) & 0xf;
   1721       1.1   gdamore 			dac = (entry & 0x1) ? RADEON_DAC_TVDAC :
   1722       1.1   gdamore 			    RADEON_DAC_PRIMARY;
   1723       1.1   gdamore 			tmds = ((entry >> 4) & 0x1) ? RADEON_TMDS_EXT :
   1724       1.1   gdamore 			    RADEON_TMDS_INT;
   1725       1.1   gdamore 
   1726       1.1   gdamore 			if (conn == RADEON_CONN_NONE)
   1727       1.1   gdamore 				continue;	/* no connector */
   1728       1.1   gdamore 
   1729       1.1   gdamore 			if ((found > 0) &&
   1730       1.1   gdamore 			    (sc->sc_ports[port].rp_ddc_type == ddc)) {
   1731       1.1   gdamore 				/* duplicate entry for same connector */
   1732       1.1   gdamore 				continue;
   1733       1.1   gdamore 			}
   1734       1.1   gdamore 
   1735       1.1   gdamore 			/* internal DDC_DVI port gets priority */
   1736       1.1   gdamore 			if ((ddc == RADEON_DDC_DVI) || (port == 1))
   1737       1.1   gdamore 				port = 0;
   1738       1.1   gdamore 			else
   1739       1.1   gdamore 				port = 1;
   1740       1.1   gdamore 
   1741       1.1   gdamore 			sc->sc_ports[port].rp_ddc_type =
   1742       1.1   gdamore 			    ddc > RADEON_DDC_CRT2 ? RADEON_DDC_NONE : ddc;
   1743       1.1   gdamore 			sc->sc_ports[port].rp_dac_type = dac;
   1744       1.1   gdamore 			sc->sc_ports[port].rp_conn_type =
   1745       1.1   gdamore 			    min(conn, RADEON_CONN_UNSUPPORTED) ;
   1746       1.1   gdamore 
   1747       1.1   gdamore 			sc->sc_ports[port].rp_tmds_type = tmds;
   1748       1.1   gdamore 
   1749       1.1   gdamore 			if ((conn != RADEON_CONN_DVI_I) &&
   1750       1.1   gdamore 			    (conn != RADEON_CONN_DVI_D) &&
   1751       1.1   gdamore 			    (tmds == RADEON_TMDS_INT))
   1752       1.1   gdamore 				sc->sc_ports[port].rp_tmds_type =
   1753       1.1   gdamore 				    RADEON_TMDS_UNKNOWN;
   1754      1.69  macallan 			sc->sc_ports[port].rp_number = i - 1;
   1755       1.1   gdamore 
   1756       1.1   gdamore 			found += (port + 1);
   1757       1.1   gdamore 		}
   1758       1.1   gdamore 	}
   1759       1.1   gdamore 
   1760       1.1   gdamore nobios:
   1761       1.1   gdamore 	if (!found) {
   1762       1.1   gdamore 		DPRINTF(("No connector info in BIOS!\n"));
   1763      1.69  macallan 		if IS_MOBILITY(sc) {
   1764      1.69  macallan 			/* default, port 0 = internal TMDS, port 1 = CRT */
   1765      1.69  macallan 			sc->sc_ports[0].rp_mon_type = RADEON_MT_UNKNOWN;
   1766      1.69  macallan 			sc->sc_ports[0].rp_ddc_type = RADEON_DDC_DVI;
   1767      1.69  macallan 			sc->sc_ports[0].rp_dac_type = RADEON_DAC_TVDAC;
   1768      1.69  macallan 			sc->sc_ports[0].rp_conn_type = RADEON_CONN_DVI_D;
   1769      1.69  macallan 			sc->sc_ports[0].rp_tmds_type = RADEON_TMDS_INT;
   1770      1.69  macallan 			sc->sc_ports[0].rp_number = 0;
   1771      1.69  macallan 
   1772      1.69  macallan 			sc->sc_ports[1].rp_mon_type = RADEON_MT_UNKNOWN;
   1773      1.69  macallan 			sc->sc_ports[1].rp_ddc_type = RADEON_DDC_VGA;
   1774      1.69  macallan 			sc->sc_ports[1].rp_dac_type = RADEON_DAC_PRIMARY;
   1775      1.69  macallan 			sc->sc_ports[1].rp_conn_type = RADEON_CONN_CRT;
   1776      1.69  macallan 			sc->sc_ports[1].rp_tmds_type = RADEON_TMDS_EXT;
   1777      1.69  macallan 			sc->sc_ports[1].rp_number = 1;
   1778      1.69  macallan 		} else {
   1779      1.69  macallan 			/* default, port 0 = DVI, port 1 = CRT */
   1780      1.69  macallan 			sc->sc_ports[0].rp_mon_type = RADEON_MT_UNKNOWN;
   1781      1.69  macallan 			sc->sc_ports[0].rp_ddc_type = RADEON_DDC_DVI;
   1782      1.69  macallan 			sc->sc_ports[0].rp_dac_type = RADEON_DAC_TVDAC;
   1783      1.69  macallan 			sc->sc_ports[0].rp_conn_type = RADEON_CONN_DVI_D;
   1784      1.69  macallan 			sc->sc_ports[0].rp_tmds_type = RADEON_TMDS_INT;
   1785      1.69  macallan 			sc->sc_ports[0].rp_number = 1;
   1786      1.69  macallan 
   1787      1.69  macallan 			sc->sc_ports[1].rp_mon_type = RADEON_MT_UNKNOWN;
   1788      1.69  macallan 			sc->sc_ports[1].rp_ddc_type = RADEON_DDC_VGA;
   1789      1.69  macallan 			sc->sc_ports[1].rp_dac_type = RADEON_DAC_PRIMARY;
   1790      1.69  macallan 			sc->sc_ports[1].rp_conn_type = RADEON_CONN_CRT;
   1791      1.70  macallan 			sc->sc_ports[1].rp_tmds_type = RADEON_TMDS_UNKNOWN;
   1792      1.69  macallan 			sc->sc_ports[1].rp_number = 0;
   1793      1.69  macallan 		}
   1794       1.1   gdamore 	}
   1795       1.1   gdamore 
   1796       1.1   gdamore 	/*
   1797       1.1   gdamore 	 * Fixup for RS300/RS350/RS400 chips, that lack a primary DAC.
   1798       1.1   gdamore 	 * these chips should use TVDAC for the VGA port.
   1799       1.1   gdamore 	 */
   1800       1.1   gdamore 	if (HAS_SDAC(sc)) {
   1801       1.1   gdamore 		if (sc->sc_ports[0].rp_conn_type == RADEON_CONN_CRT) {
   1802       1.1   gdamore 			sc->sc_ports[0].rp_dac_type = RADEON_DAC_TVDAC;
   1803       1.1   gdamore 			sc->sc_ports[1].rp_dac_type = RADEON_DAC_PRIMARY;
   1804       1.1   gdamore 		} else {
   1805       1.1   gdamore 			sc->sc_ports[1].rp_dac_type = RADEON_DAC_TVDAC;
   1806       1.1   gdamore 			sc->sc_ports[0].rp_dac_type = RADEON_DAC_PRIMARY;
   1807       1.1   gdamore 		}
   1808       1.1   gdamore 	} else if (!HAS_CRTC2(sc)) {
   1809       1.1   gdamore 		sc->sc_ports[0].rp_dac_type = RADEON_DAC_PRIMARY;
   1810       1.1   gdamore 	}
   1811       1.1   gdamore 
   1812       1.1   gdamore 	for (i = 0; i < 2; i++) {
   1813       1.1   gdamore 		char	edid[128];
   1814       1.1   gdamore 		uint8_t	ddc;
   1815       1.1   gdamore 		struct edid_info *eip = &sc->sc_ports[i].rp_edid;
   1816      1.13  macallan 		prop_data_t edid_data;
   1817       1.1   gdamore 
   1818       1.1   gdamore 		DPRINTF(("Port #%d:\n", i));
   1819      1.69  macallan 		DPRINTF(("   conn = %d\n", sc->sc_ports[i].rp_conn_type));
   1820       1.1   gdamore 		DPRINTF(("    ddc = %d\n", sc->sc_ports[i].rp_ddc_type));
   1821       1.1   gdamore 		DPRINTF(("    dac = %d\n", sc->sc_ports[i].rp_dac_type));
   1822      1.69  macallan 		DPRINTF(("   tmds = %d\n", sc->sc_ports[i].rp_tmds_type));
   1823      1.69  macallan 		DPRINTF(("   crtc = %d\n", sc->sc_ports[i].rp_number));
   1824       1.1   gdamore 
   1825       1.1   gdamore 		sc->sc_ports[i].rp_edid_valid = 0;
   1826      1.13  macallan 		/* first look for static EDID data */
   1827      1.13  macallan 		if ((edid_data = prop_dictionary_get(device_properties(
   1828      1.47  macallan 		    sc->sc_dev), "EDID")) != NULL) {
   1829      1.13  macallan 
   1830      1.69  macallan 			aprint_debug_dev(sc->sc_dev, "using static EDID\n");
   1831      1.13  macallan 			memcpy(edid, prop_data_data_nocopy(edid_data), 128);
   1832      1.13  macallan 			if (edid_parse(edid, eip) == 0) {
   1833      1.13  macallan 
   1834       1.1   gdamore 				sc->sc_ports[i].rp_edid_valid = 1;
   1835       1.1   gdamore 			}
   1836       1.1   gdamore 		}
   1837      1.13  macallan 		/* if we didn't find any we'll try to talk to the monitor */
   1838      1.13  macallan 		if (sc->sc_ports[i].rp_edid_valid != 1) {
   1839      1.13  macallan 
   1840      1.13  macallan 			ddc = sc->sc_ports[i].rp_ddc_type;
   1841      1.13  macallan 			if (ddc != RADEON_DDC_NONE) {
   1842      1.13  macallan 				if ((radeonfb_i2c_read_edid(sc, ddc, edid)
   1843      1.13  macallan 				    == 0) && (edid_parse(edid, eip) == 0)) {
   1844      1.13  macallan 
   1845      1.13  macallan 					sc->sc_ports[i].rp_edid_valid = 1;
   1846      1.63  macallan #ifdef RADEONFB_DEBUG
   1847      1.13  macallan 					edid_print(eip);
   1848      1.63  macallan #endif
   1849      1.13  macallan 				}
   1850      1.13  macallan 			}
   1851      1.13  macallan 		}
   1852       1.1   gdamore 	}
   1853       1.1   gdamore 
   1854       1.1   gdamore 	return found;
   1855       1.1   gdamore }
   1856       1.1   gdamore 
   1857       1.1   gdamore int
   1858       1.1   gdamore radeonfb_gettmds(struct radeonfb_softc *sc)
   1859       1.1   gdamore {
   1860       1.1   gdamore 	int	i;
   1861       1.1   gdamore 
   1862       1.1   gdamore 	if (!sc->sc_biossz) {
   1863       1.1   gdamore 		goto nobios;
   1864       1.1   gdamore 	}
   1865       1.1   gdamore 
   1866       1.1   gdamore 	if (IS_ATOM(sc)) {
   1867       1.1   gdamore 		/* XXX: not done yet */
   1868       1.1   gdamore 	} else {
   1869       1.1   gdamore 		uint16_t	ptr;
   1870       1.1   gdamore 		int		n;
   1871       1.1   gdamore 
   1872       1.1   gdamore 		ptr = GETBIOS16(sc, 0x48);
   1873       1.1   gdamore 		ptr = GETBIOS16(sc, ptr + 0x34);
   1874       1.1   gdamore 		DPRINTF(("DFP table revision %d\n", GETBIOS8(sc, ptr)));
   1875      1.11        ad 		if (GETBIOS8(sc, ptr) == 3) {
   1876       1.1   gdamore 			/* revision three table */
   1877       1.1   gdamore 			n = GETBIOS8(sc, ptr + 5) + 1;
   1878       1.1   gdamore 			n = min(n, 4);
   1879       1.1   gdamore 
   1880       1.1   gdamore 			memset(sc->sc_tmds_pll, 0, sizeof (sc->sc_tmds_pll));
   1881       1.1   gdamore 			for (i = 0; i < n; i++) {
   1882       1.1   gdamore 				sc->sc_tmds_pll[i].rtp_pll = GETBIOS32(sc,
   1883       1.1   gdamore 				    ptr + i * 10 + 8);
   1884       1.1   gdamore 				sc->sc_tmds_pll[i].rtp_freq = GETBIOS16(sc,
   1885       1.1   gdamore 				    ptr + i * 10 + 0x10);
   1886       1.1   gdamore 				DPRINTF(("TMDS_PLL dot clock %d pll %x\n",
   1887       1.1   gdamore 					    sc->sc_tmds_pll[i].rtp_freq,
   1888       1.1   gdamore 					    sc->sc_tmds_pll[i].rtp_pll));
   1889       1.1   gdamore 			}
   1890       1.1   gdamore 			return 0;
   1891       1.1   gdamore 		}
   1892       1.1   gdamore 	}
   1893       1.1   gdamore 
   1894       1.1   gdamore nobios:
   1895       1.1   gdamore 	DPRINTF(("no suitable DFP table present\n"));
   1896       1.1   gdamore 	for (i = 0;
   1897       1.1   gdamore 	     i < sizeof (radeonfb_tmds_pll) / sizeof (radeonfb_tmds_pll[0]);
   1898       1.1   gdamore 	     i++) {
   1899       1.1   gdamore 		int	j;
   1900       1.1   gdamore 
   1901       1.1   gdamore 		if (radeonfb_tmds_pll[i].family != sc->sc_family)
   1902       1.1   gdamore 			continue;
   1903       1.1   gdamore 
   1904       1.1   gdamore 		for (j = 0; j < 4; j++) {
   1905       1.1   gdamore 			sc->sc_tmds_pll[j] = radeonfb_tmds_pll[i].plls[j];
   1906       1.1   gdamore 			DPRINTF(("TMDS_PLL dot clock %d pll %x\n",
   1907       1.1   gdamore 				    sc->sc_tmds_pll[j].rtp_freq,
   1908       1.1   gdamore 				    sc->sc_tmds_pll[j].rtp_pll));
   1909       1.1   gdamore 		}
   1910       1.1   gdamore 		return 0;
   1911       1.1   gdamore 	}
   1912       1.1   gdamore 
   1913       1.1   gdamore 	return -1;
   1914       1.1   gdamore }
   1915       1.1   gdamore 
   1916       1.1   gdamore const struct videomode *
   1917       1.1   gdamore radeonfb_modelookup(const char *name)
   1918       1.1   gdamore {
   1919       1.1   gdamore 	int	i;
   1920       1.1   gdamore 
   1921       1.1   gdamore 	for (i = 0; i < videomode_count; i++)
   1922       1.1   gdamore 		if (!strcmp(name, videomode_list[i].name))
   1923       1.1   gdamore 			return &videomode_list[i];
   1924       1.1   gdamore 
   1925       1.1   gdamore 	return NULL;
   1926       1.1   gdamore }
   1927       1.1   gdamore 
   1928       1.1   gdamore void
   1929       1.1   gdamore radeonfb_pllwriteupdate(struct radeonfb_softc *sc, int crtc)
   1930       1.1   gdamore {
   1931       1.1   gdamore 	if (crtc) {
   1932       1.1   gdamore 		while (GETPLL(sc, RADEON_P2PLL_REF_DIV) &
   1933       1.1   gdamore 		    RADEON_P2PLL_ATOMIC_UPDATE_R);
   1934       1.1   gdamore 		SETPLL(sc, RADEON_P2PLL_REF_DIV, RADEON_P2PLL_ATOMIC_UPDATE_W);
   1935       1.1   gdamore 	} else {
   1936       1.1   gdamore 		while (GETPLL(sc, RADEON_PPLL_REF_DIV) &
   1937       1.1   gdamore 		    RADEON_PPLL_ATOMIC_UPDATE_R);
   1938       1.1   gdamore 		SETPLL(sc, RADEON_PPLL_REF_DIV, RADEON_PPLL_ATOMIC_UPDATE_W);
   1939       1.1   gdamore 	}
   1940       1.1   gdamore }
   1941       1.1   gdamore 
   1942       1.1   gdamore void
   1943       1.1   gdamore radeonfb_pllwaitatomicread(struct radeonfb_softc *sc, int crtc)
   1944       1.1   gdamore {
   1945       1.1   gdamore 	int	i;
   1946       1.1   gdamore 
   1947       1.1   gdamore 	for (i = 10000; i; i--) {
   1948       1.1   gdamore 		if (crtc) {
   1949       1.1   gdamore 			if (GETPLL(sc, RADEON_P2PLL_REF_DIV) &
   1950       1.1   gdamore 			    RADEON_P2PLL_ATOMIC_UPDATE_R)
   1951       1.1   gdamore 				break;
   1952       1.1   gdamore 		} else {
   1953       1.1   gdamore 			if (GETPLL(sc, RADEON_PPLL_REF_DIV) &
   1954       1.1   gdamore 			    RADEON_PPLL_ATOMIC_UPDATE_R)
   1955       1.1   gdamore 				break;
   1956       1.1   gdamore 		}
   1957       1.1   gdamore 	}
   1958       1.1   gdamore }
   1959       1.1   gdamore 
   1960       1.1   gdamore void
   1961       1.1   gdamore radeonfb_program_vclk(struct radeonfb_softc *sc, int dotclock, int crtc)
   1962       1.1   gdamore {
   1963       1.2  macallan 	uint32_t	pbit = 0;
   1964       1.2  macallan 	uint32_t	feed = 0;
   1965      1.69  macallan 	uint32_t	data, refdiv, div0;
   1966       1.1   gdamore 
   1967       1.1   gdamore 	radeonfb_calc_dividers(sc, dotclock, &pbit, &feed);
   1968       1.1   gdamore 
   1969       1.1   gdamore 	if (crtc == 0) {
   1970       1.1   gdamore 
   1971      1.69  macallan 		refdiv = GETPLL(sc, RADEON_PPLL_REF_DIV);
   1972      1.69  macallan 		if (IS_R300(sc)) {
   1973      1.69  macallan 			refdiv = (refdiv & ~R300_PPLL_REF_DIV_ACC_MASK) |
   1974      1.69  macallan 			    (sc->sc_refdiv << R300_PPLL_REF_DIV_ACC_SHIFT);
   1975      1.69  macallan 		} else {
   1976      1.69  macallan 			refdiv = (refdiv & ~RADEON_PPLL_REF_DIV_MASK) |
   1977      1.69  macallan 			    sc->sc_refdiv;
   1978      1.69  macallan 		}
   1979      1.69  macallan 		div0 = GETPLL(sc, RADEON_PPLL_DIV_0);
   1980      1.69  macallan 		div0 &= ~(RADEON_PPLL_FB3_DIV_MASK |
   1981      1.69  macallan 		    RADEON_PPLL_POST3_DIV_MASK);
   1982      1.69  macallan 		div0 |= pbit;
   1983      1.69  macallan 		div0 |= (feed & RADEON_PPLL_FB3_DIV_MASK);
   1984      1.69  macallan 
   1985      1.69  macallan 		if ((refdiv == GETPLL(sc, RADEON_PPLL_REF_DIV)) &&
   1986      1.69  macallan 		    (div0 == GETPLL(sc, RADEON_PPLL_DIV_0))) {
   1987      1.69  macallan 			/*
   1988      1.69  macallan 			 * nothing to do here, the PLL is already where we
   1989      1.69  macallan 			 * want it
   1990      1.69  macallan 			 */
   1991      1.69  macallan 			PATCH32(sc, RADEON_CLOCK_CNTL_INDEX, 0,
   1992      1.69  macallan 			    ~RADEON_PLL_DIV_SEL);
   1993      1.69  macallan 			aprint_debug_dev(sc->sc_dev, "no need to touch the PLL\n");
   1994      1.69  macallan 			return;
   1995      1.69  macallan 		}
   1996       1.1   gdamore 
   1997      1.69  macallan 		/* alright, we do need to reprogram stuff */
   1998       1.1   gdamore 		PATCHPLL(sc, RADEON_VCLK_ECP_CNTL,
   1999       1.1   gdamore 		    RADEON_VCLK_SRC_SEL_CPUCLK,
   2000       1.1   gdamore 		    ~RADEON_VCLK_SRC_SEL_MASK);
   2001      1.11        ad 
   2002       1.1   gdamore 		/* put vclk into reset, use atomic updates */
   2003       1.1   gdamore 		SETPLL(sc, RADEON_PPLL_CNTL,
   2004       1.1   gdamore 		    RADEON_PPLL_REFCLK_SEL |
   2005       1.1   gdamore 		    RADEON_PPLL_FBCLK_SEL |
   2006       1.1   gdamore 		    RADEON_PPLL_RESET |
   2007       1.1   gdamore 		    RADEON_PPLL_ATOMIC_UPDATE_EN |
   2008       1.1   gdamore 		    RADEON_PPLL_VGA_ATOMIC_UPDATE_EN);
   2009       1.1   gdamore 
   2010      1.69  macallan 		/* select clock 0 */
   2011       1.1   gdamore 		PATCH32(sc, RADEON_CLOCK_CNTL_INDEX, 0,
   2012       1.1   gdamore 		    ~RADEON_PLL_DIV_SEL);
   2013      1.11        ad 
   2014      1.69  macallan 		PUTPLL(sc, RADEON_PPLL_REF_DIV, refdiv);
   2015       1.1   gdamore 
   2016      1.69  macallan 		/* xf86-video-radeon does this, not sure why */
   2017      1.69  macallan 		PUTPLL(sc, RADEON_PPLL_DIV_0, div0);
   2018      1.69  macallan 		PUTPLL(sc, RADEON_PPLL_DIV_0, div0);
   2019       1.1   gdamore 
   2020       1.1   gdamore 		/* use the atomic update */
   2021       1.1   gdamore 		radeonfb_pllwriteupdate(sc, crtc);
   2022       1.1   gdamore 
   2023       1.1   gdamore 		/* and wait for it to complete */
   2024       1.1   gdamore 		radeonfb_pllwaitatomicread(sc, crtc);
   2025       1.1   gdamore 
   2026       1.1   gdamore 		/* program HTOTAL (why?) */
   2027       1.1   gdamore 		PUTPLL(sc, RADEON_HTOTAL_CNTL, 0);
   2028       1.1   gdamore 
   2029       1.1   gdamore 		/* drop reset */
   2030       1.1   gdamore 		CLRPLL(sc, RADEON_PPLL_CNTL,
   2031       1.1   gdamore 		    RADEON_PPLL_RESET | RADEON_PPLL_SLEEP |
   2032       1.1   gdamore 		    RADEON_PPLL_ATOMIC_UPDATE_EN |
   2033       1.1   gdamore 		    RADEON_PPLL_VGA_ATOMIC_UPDATE_EN);
   2034       1.1   gdamore 
   2035       1.1   gdamore 		PRINTPLL(RADEON_PPLL_CNTL);
   2036      1.69  macallan 		PRINTPLL(RADEON_PPLL_REF_DIV);
   2037      1.69  macallan 		PRINTPLL(RADEON_PPLL_DIV_3);
   2038       1.1   gdamore 
   2039       1.1   gdamore 		/* give clock time to lock */
   2040       1.1   gdamore 		delay(50000);
   2041       1.1   gdamore 
   2042       1.1   gdamore 		PATCHPLL(sc, RADEON_VCLK_ECP_CNTL,
   2043       1.1   gdamore 		    RADEON_VCLK_SRC_SEL_PPLLCLK,
   2044       1.1   gdamore 		    ~RADEON_VCLK_SRC_SEL_MASK);
   2045       1.1   gdamore 
   2046       1.1   gdamore 	} else {
   2047       1.1   gdamore 
   2048       1.1   gdamore 		PATCHPLL(sc, RADEON_PIXCLKS_CNTL,
   2049       1.1   gdamore 		    RADEON_PIX2CLK_SRC_SEL_CPUCLK,
   2050       1.1   gdamore 		    ~RADEON_PIX2CLK_SRC_SEL_MASK);
   2051       1.1   gdamore 
   2052       1.1   gdamore 		/* put vclk into reset, use atomic updates */
   2053       1.1   gdamore 		SETPLL(sc, RADEON_P2PLL_CNTL,
   2054       1.1   gdamore 		    RADEON_P2PLL_RESET |
   2055       1.1   gdamore 		    RADEON_P2PLL_ATOMIC_UPDATE_EN |
   2056       1.1   gdamore 		    RADEON_P2PLL_VGA_ATOMIC_UPDATE_EN);
   2057       1.1   gdamore 
   2058       1.1   gdamore 		/* program reference divider */
   2059       1.1   gdamore 		PATCHPLL(sc, RADEON_P2PLL_REF_DIV, sc->sc_refdiv,
   2060       1.1   gdamore 		    ~RADEON_P2PLL_REF_DIV_MASK);
   2061       1.1   gdamore 
   2062       1.1   gdamore 		/* program feedback and post dividers */
   2063       1.1   gdamore 		data = GETPLL(sc, RADEON_P2PLL_DIV_0);
   2064       1.1   gdamore 		data &= ~(RADEON_P2PLL_FB0_DIV_MASK |
   2065       1.1   gdamore 		    RADEON_P2PLL_POST0_DIV_MASK);
   2066       1.1   gdamore 		data |= pbit;
   2067       1.1   gdamore 		data |= (feed & RADEON_P2PLL_FB0_DIV_MASK);
   2068       1.1   gdamore 		PUTPLL(sc, RADEON_P2PLL_DIV_0, data);
   2069      1.69  macallan 		PUTPLL(sc, RADEON_P2PLL_DIV_0, data);
   2070      1.69  macallan 
   2071      1.69  macallan 		PRINTPLL(RADEON_P2PLL_REF_DIV);
   2072      1.69  macallan 		PRINTPLL(RADEON_P2PLL_DIV_0);
   2073       1.1   gdamore 
   2074       1.1   gdamore 		/* use the atomic update */
   2075       1.1   gdamore 		radeonfb_pllwriteupdate(sc, crtc);
   2076       1.1   gdamore 
   2077       1.1   gdamore 		/* and wait for it to complete */
   2078       1.1   gdamore 		radeonfb_pllwaitatomicread(sc, crtc);
   2079       1.1   gdamore 
   2080       1.1   gdamore 		/* program HTOTAL (why?) */
   2081       1.1   gdamore 		PUTPLL(sc, RADEON_HTOTAL2_CNTL, 0);
   2082       1.1   gdamore 
   2083       1.1   gdamore 		/* drop reset */
   2084       1.1   gdamore 		CLRPLL(sc, RADEON_P2PLL_CNTL,
   2085       1.1   gdamore 		    RADEON_P2PLL_RESET | RADEON_P2PLL_SLEEP |
   2086       1.1   gdamore 		    RADEON_P2PLL_ATOMIC_UPDATE_EN |
   2087       1.1   gdamore 		    RADEON_P2PLL_VGA_ATOMIC_UPDATE_EN);
   2088       1.1   gdamore 
   2089       1.1   gdamore 		/* allow time for clock to lock */
   2090       1.1   gdamore 		delay(50000);
   2091       1.1   gdamore 
   2092       1.1   gdamore 		PATCHPLL(sc, RADEON_PIXCLKS_CNTL,
   2093       1.1   gdamore 		    RADEON_PIX2CLK_SRC_SEL_P2PLLCLK,
   2094       1.1   gdamore 		    ~RADEON_PIX2CLK_SRC_SEL_MASK);
   2095       1.1   gdamore 	}
   2096       1.1   gdamore 	PRINTREG(RADEON_CRTC_MORE_CNTL);
   2097       1.1   gdamore }
   2098       1.1   gdamore 
   2099       1.1   gdamore void
   2100       1.1   gdamore radeonfb_modeswitch(struct radeonfb_display *dp)
   2101       1.1   gdamore {
   2102       1.1   gdamore 	struct radeonfb_softc	*sc = dp->rd_softc;
   2103       1.1   gdamore 	int			i;
   2104       1.1   gdamore 
   2105       1.1   gdamore 	/* blank the display while we switch modes */
   2106      1.36  macallan 	radeonfb_blank(dp, 1);
   2107       1.1   gdamore 
   2108       1.1   gdamore #if 0
   2109       1.1   gdamore 	SET32(sc, RADEON_CRTC_EXT_CNTL,
   2110       1.1   gdamore 	    RADEON_CRTC_VSYNC_DIS | RADEON_CRTC_HSYNC_DIS |
   2111       1.1   gdamore 	    RADEON_CRTC_DISPLAY_DIS /* | RADEON_CRTC_DISP_REQ_EN_B */);
   2112       1.1   gdamore #endif
   2113       1.1   gdamore 
   2114       1.1   gdamore 	/* these registers might get in the way... */
   2115       1.1   gdamore 	PUT32(sc, RADEON_OVR_CLR, 0);
   2116       1.1   gdamore 	PUT32(sc, RADEON_OVR_WID_LEFT_RIGHT, 0);
   2117       1.1   gdamore 	PUT32(sc, RADEON_OVR_WID_TOP_BOTTOM, 0);
   2118       1.1   gdamore 	PUT32(sc, RADEON_OV0_SCALE_CNTL, 0);
   2119       1.1   gdamore 	PUT32(sc, RADEON_SUBPIC_CNTL, 0);
   2120       1.1   gdamore 	PUT32(sc, RADEON_VIPH_CONTROL, 0);
   2121       1.1   gdamore 	PUT32(sc, RADEON_I2C_CNTL_1, 0);
   2122       1.1   gdamore 	PUT32(sc, RADEON_GEN_INT_CNTL, 0);
   2123       1.1   gdamore 	PUT32(sc, RADEON_CAP0_TRIG_CNTL, 0);
   2124       1.1   gdamore 	PUT32(sc, RADEON_CAP1_TRIG_CNTL, 0);
   2125       1.1   gdamore 	PUT32(sc, RADEON_SURFACE_CNTL, 0);
   2126       1.1   gdamore 
   2127       1.1   gdamore 	for (i = 0; i < dp->rd_ncrtcs; i++)
   2128       1.1   gdamore 		radeonfb_setcrtc(dp, i);
   2129       1.1   gdamore 
   2130       1.1   gdamore 	/* activate the display */
   2131      1.36  macallan 	radeonfb_blank(dp, 0);
   2132       1.1   gdamore }
   2133       1.1   gdamore 
   2134       1.1   gdamore void
   2135       1.1   gdamore radeonfb_setcrtc(struct radeonfb_display *dp, int index)
   2136       1.1   gdamore {
   2137       1.1   gdamore 	int			crtc;
   2138       1.1   gdamore 	struct videomode	*mode;
   2139       1.1   gdamore 	struct radeonfb_softc	*sc;
   2140       1.1   gdamore 	struct radeonfb_crtc	*cp;
   2141       1.1   gdamore 	uint32_t		v;
   2142       1.1   gdamore 	uint32_t		gencntl;
   2143       1.1   gdamore 	uint32_t		htotaldisp;
   2144       1.1   gdamore 	uint32_t		hsyncstrt;
   2145       1.1   gdamore 	uint32_t		vtotaldisp;
   2146       1.1   gdamore 	uint32_t		vsyncstrt;
   2147       1.1   gdamore 	uint32_t		fphsyncstrt;
   2148       1.1   gdamore 	uint32_t		fpvsyncstrt;
   2149       1.1   gdamore 	uint32_t		fphtotaldisp;
   2150       1.1   gdamore 	uint32_t		fpvtotaldisp;
   2151       1.1   gdamore 	uint32_t		pitch;
   2152       1.1   gdamore 
   2153       1.1   gdamore 	sc = dp->rd_softc;
   2154       1.1   gdamore 	cp = &dp->rd_crtcs[index];
   2155       1.1   gdamore 	crtc = cp->rc_number;
   2156       1.1   gdamore 	mode = &cp->rc_videomode;
   2157       1.1   gdamore 
   2158       1.2  macallan #if 1
   2159      1.65  macallan 	pitch = dp->rd_stride / dp->rd_bpp;
   2160       1.1   gdamore #else
   2161       1.1   gdamore 	pitch = (((sc->sc_maxx * sc->sc_maxbpp) + ((sc->sc_maxbpp * 8) - 1)) /
   2162       1.1   gdamore 	    (sc->sc_maxbpp * 8));
   2163       1.1   gdamore #endif
   2164       1.1   gdamore 	switch (crtc) {
   2165       1.1   gdamore 	case 0:
   2166       1.1   gdamore 		gencntl = RADEON_CRTC_GEN_CNTL;
   2167       1.1   gdamore 		htotaldisp = RADEON_CRTC_H_TOTAL_DISP;
   2168       1.1   gdamore 		hsyncstrt = RADEON_CRTC_H_SYNC_STRT_WID;
   2169       1.1   gdamore 		vtotaldisp = RADEON_CRTC_V_TOTAL_DISP;
   2170       1.1   gdamore 		vsyncstrt = RADEON_CRTC_V_SYNC_STRT_WID;
   2171       1.1   gdamore 		fpvsyncstrt = RADEON_FP_V_SYNC_STRT_WID;
   2172       1.1   gdamore 		fphsyncstrt = RADEON_FP_H_SYNC_STRT_WID;
   2173       1.1   gdamore 		fpvtotaldisp = RADEON_FP_CRTC_V_TOTAL_DISP;
   2174       1.1   gdamore 		fphtotaldisp = RADEON_FP_CRTC_H_TOTAL_DISP;
   2175       1.1   gdamore 		break;
   2176       1.1   gdamore 	case 1:
   2177       1.1   gdamore 		gencntl = RADEON_CRTC2_GEN_CNTL;
   2178       1.1   gdamore 		htotaldisp = RADEON_CRTC2_H_TOTAL_DISP;
   2179       1.1   gdamore 		hsyncstrt = RADEON_CRTC2_H_SYNC_STRT_WID;
   2180       1.1   gdamore 		vtotaldisp = RADEON_CRTC2_V_TOTAL_DISP;
   2181       1.1   gdamore 		vsyncstrt = RADEON_CRTC2_V_SYNC_STRT_WID;
   2182       1.1   gdamore 		fpvsyncstrt = RADEON_FP_V2_SYNC_STRT_WID;
   2183       1.1   gdamore 		fphsyncstrt = RADEON_FP_H2_SYNC_STRT_WID;
   2184       1.1   gdamore 		fpvtotaldisp = RADEON_FP_CRTC2_V_TOTAL_DISP;
   2185       1.1   gdamore 		fphtotaldisp = RADEON_FP_CRTC2_H_TOTAL_DISP;
   2186       1.1   gdamore 		break;
   2187       1.1   gdamore 	default:
   2188       1.1   gdamore 		panic("Bad CRTC!");
   2189       1.1   gdamore 		break;
   2190       1.1   gdamore 	}
   2191       1.1   gdamore 
   2192       1.1   gdamore 	/*
   2193       1.1   gdamore 	 * CRTC_GEN_CNTL - depth, accelerator mode, etc.
   2194       1.1   gdamore 	 */
   2195       1.1   gdamore 	/* only bother with 32bpp and 8bpp */
   2196       1.1   gdamore 	v = dp->rd_format << RADEON_CRTC_PIX_WIDTH_SHIFT;
   2197       1.1   gdamore 
   2198       1.1   gdamore 	if (crtc == 1) {
   2199       1.1   gdamore 		v |= RADEON_CRTC2_CRT2_ON | RADEON_CRTC2_EN;
   2200       1.1   gdamore 	} else {
   2201       1.1   gdamore 		v |= RADEON_CRTC_EXT_DISP_EN | RADEON_CRTC_EN;
   2202       1.1   gdamore 	}
   2203       1.1   gdamore 
   2204       1.1   gdamore 	if (mode->flags & VID_DBLSCAN)
   2205       1.1   gdamore 		v |= RADEON_CRTC2_DBL_SCAN_EN;
   2206       1.1   gdamore 
   2207       1.1   gdamore 	if (mode->flags & VID_INTERLACE)
   2208       1.1   gdamore 		v |= RADEON_CRTC2_INTERLACE_EN;
   2209       1.1   gdamore 
   2210       1.1   gdamore 	if (mode->flags & VID_CSYNC) {
   2211       1.1   gdamore 		v |= RADEON_CRTC2_CSYNC_EN;
   2212       1.1   gdamore 		if (crtc == 1)
   2213       1.1   gdamore 			v |= RADEON_CRTC2_VSYNC_TRISTAT;
   2214       1.1   gdamore 	}
   2215      1.11        ad 
   2216       1.1   gdamore 	PUT32(sc, gencntl, v);
   2217       1.1   gdamore 	DPRINTF(("CRTC%s_GEN_CNTL = %08x\n", crtc ? "2" : "", v));
   2218       1.1   gdamore 
   2219       1.1   gdamore 	/*
   2220       1.1   gdamore 	 * CRTC_EXT_CNTL - preserve disable flags, set ATI linear and EXT_CNT
   2221       1.1   gdamore 	 */
   2222       1.1   gdamore 	v = GET32(sc, RADEON_CRTC_EXT_CNTL);
   2223       1.1   gdamore 	if (crtc == 0) {
   2224       1.1   gdamore 		v &= (RADEON_CRTC_VSYNC_DIS | RADEON_CRTC_HSYNC_DIS |
   2225       1.1   gdamore 		    RADEON_CRTC_DISPLAY_DIS);
   2226       1.1   gdamore 		v |= RADEON_XCRT_CNT_EN | RADEON_VGA_ATI_LINEAR;
   2227       1.1   gdamore 		if (mode->flags & VID_CSYNC)
   2228       1.1   gdamore 			v |= RADEON_CRTC_VSYNC_TRISTAT;
   2229       1.1   gdamore 	}
   2230       1.1   gdamore 	/* unconditional turn on CRT, in case first CRTC is DFP */
   2231       1.1   gdamore 	v |= RADEON_CRTC_CRT_ON;
   2232       1.1   gdamore 	PUT32(sc, RADEON_CRTC_EXT_CNTL, v);
   2233       1.1   gdamore 	PRINTREG(RADEON_CRTC_EXT_CNTL);
   2234       1.1   gdamore 
   2235       1.1   gdamore 	/*
   2236       1.1   gdamore 	 * H_TOTAL_DISP
   2237       1.1   gdamore 	 */
   2238       1.1   gdamore 	v = ((mode->hdisplay / 8) - 1) << 16;
   2239       1.1   gdamore 	v |= (mode->htotal / 8) - 1;
   2240       1.1   gdamore 	PUT32(sc, htotaldisp, v);
   2241       1.1   gdamore 	DPRINTF(("CRTC%s_H_TOTAL_DISP = %08x\n", crtc ? "2" : "", v));
   2242       1.1   gdamore 	PUT32(sc, fphtotaldisp, v);
   2243       1.1   gdamore 	DPRINTF(("FP_H%s_TOTAL_DISP = %08x\n", crtc ? "2" : "", v));
   2244       1.1   gdamore 
   2245       1.1   gdamore 	/*
   2246       1.1   gdamore 	 * H_SYNC_STRT_WID
   2247       1.1   gdamore 	 */
   2248       1.1   gdamore 	v = (((mode->hsync_end - mode->hsync_start) / 8) << 16);
   2249      1.75  macallan 	v |= (mode->hsync_start - 8);	/* match xf86-video-radeon */
   2250       1.1   gdamore 	if (mode->flags & VID_NHSYNC)
   2251       1.1   gdamore 		v |= RADEON_CRTC_H_SYNC_POL;
   2252       1.1   gdamore 	PUT32(sc, hsyncstrt, v);
   2253       1.1   gdamore 	DPRINTF(("CRTC%s_H_SYNC_STRT_WID = %08x\n", crtc ? "2" : "", v));
   2254       1.1   gdamore 	PUT32(sc, fphsyncstrt, v);
   2255       1.1   gdamore 	DPRINTF(("FP_H%s_SYNC_STRT_WID = %08x\n", crtc ? "2" : "", v));
   2256       1.1   gdamore 
   2257       1.1   gdamore 	/*
   2258       1.1   gdamore 	 * V_TOTAL_DISP
   2259       1.1   gdamore 	 */
   2260       1.1   gdamore 	v = ((mode->vdisplay - 1) << 16);
   2261       1.1   gdamore 	v |= (mode->vtotal - 1);
   2262       1.1   gdamore 	PUT32(sc, vtotaldisp, v);
   2263       1.1   gdamore 	DPRINTF(("CRTC%s_V_TOTAL_DISP = %08x\n", crtc ? "2" : "", v));
   2264       1.1   gdamore 	PUT32(sc, fpvtotaldisp, v);
   2265       1.1   gdamore 	DPRINTF(("FP_V%s_TOTAL_DISP = %08x\n", crtc ? "2" : "", v));
   2266       1.1   gdamore 
   2267       1.1   gdamore 	/*
   2268       1.1   gdamore 	 * V_SYNC_STRT_WID
   2269       1.1   gdamore 	 */
   2270       1.1   gdamore 	v = ((mode->vsync_end - mode->vsync_start) << 16);
   2271       1.1   gdamore 	v |= (mode->vsync_start - 1);
   2272       1.1   gdamore 	if (mode->flags & VID_NVSYNC)
   2273       1.1   gdamore 		v |= RADEON_CRTC_V_SYNC_POL;
   2274       1.1   gdamore 	PUT32(sc, vsyncstrt, v);
   2275       1.1   gdamore 	DPRINTF(("CRTC%s_V_SYNC_STRT_WID = %08x\n", crtc ? "2" : "", v));
   2276       1.1   gdamore 	PUT32(sc, fpvsyncstrt, v);
   2277       1.1   gdamore 	DPRINTF(("FP_V%s_SYNC_STRT_WID = %08x\n", crtc ? "2" : "", v));
   2278       1.1   gdamore 
   2279       1.1   gdamore 	radeonfb_program_vclk(sc, mode->dot_clock, crtc);
   2280       1.1   gdamore 
   2281       1.1   gdamore 	switch (crtc) {
   2282       1.1   gdamore 	case 0:
   2283       1.1   gdamore 		PUT32(sc, RADEON_CRTC_OFFSET, 0);
   2284       1.1   gdamore 		PUT32(sc, RADEON_CRTC_OFFSET_CNTL, 0);
   2285       1.1   gdamore 		PUT32(sc, RADEON_CRTC_PITCH, pitch);
   2286       1.1   gdamore 		CLR32(sc, RADEON_DISP_MERGE_CNTL, RADEON_DISP_RGB_OFFSET_EN);
   2287       1.1   gdamore 
   2288       1.1   gdamore 		CLR32(sc, RADEON_CRTC_EXT_CNTL,
   2289       1.1   gdamore 		    RADEON_CRTC_VSYNC_DIS | RADEON_CRTC_HSYNC_DIS |
   2290       1.1   gdamore 		    RADEON_CRTC_DISPLAY_DIS /* | RADEON_CRTC_DISP_REQ_EN_B */);
   2291       1.1   gdamore 		CLR32(sc, RADEON_CRTC_GEN_CNTL, RADEON_CRTC_DISP_REQ_EN_B);
   2292       1.1   gdamore 		PRINTREG(RADEON_CRTC_EXT_CNTL);
   2293       1.1   gdamore 		PRINTREG(RADEON_CRTC_GEN_CNTL);
   2294       1.1   gdamore 		PRINTREG(RADEON_CLOCK_CNTL_INDEX);
   2295       1.1   gdamore 		break;
   2296       1.1   gdamore 
   2297       1.1   gdamore 	case 1:
   2298       1.1   gdamore 		PUT32(sc, RADEON_CRTC2_OFFSET, 0);
   2299       1.1   gdamore 		PUT32(sc, RADEON_CRTC2_OFFSET_CNTL, 0);
   2300       1.1   gdamore 		PUT32(sc, RADEON_CRTC2_PITCH, pitch);
   2301       1.1   gdamore 		CLR32(sc, RADEON_DISP2_MERGE_CNTL, RADEON_DISP2_RGB_OFFSET_EN);
   2302       1.1   gdamore 		CLR32(sc, RADEON_CRTC2_GEN_CNTL,
   2303       1.1   gdamore 		    RADEON_CRTC2_VSYNC_DIS |
   2304       1.1   gdamore 		    RADEON_CRTC2_HSYNC_DIS |
   2305      1.11        ad 		    RADEON_CRTC2_DISP_DIS | RADEON_CRTC2_DISP_REQ_EN_B);
   2306       1.1   gdamore 		PRINTREG(RADEON_CRTC2_GEN_CNTL);
   2307       1.1   gdamore 		break;
   2308       1.1   gdamore 	}
   2309       1.1   gdamore }
   2310       1.1   gdamore 
   2311       1.1   gdamore int
   2312       1.1   gdamore radeonfb_isblank(struct radeonfb_display *dp)
   2313       1.1   gdamore {
   2314       1.1   gdamore 	uint32_t	reg, mask;
   2315       1.1   gdamore 
   2316      1.68  macallan 	if(!dp->rd_softc->sc_mapped)
   2317      1.68  macallan 		return 1;
   2318      1.68  macallan 
   2319       1.1   gdamore 	if (dp->rd_crtcs[0].rc_number) {
   2320       1.1   gdamore 		reg = RADEON_CRTC2_GEN_CNTL;
   2321       1.1   gdamore 		mask = RADEON_CRTC2_DISP_DIS;
   2322       1.1   gdamore 	} else {
   2323       1.1   gdamore 		reg = RADEON_CRTC_EXT_CNTL;
   2324       1.1   gdamore 		mask = RADEON_CRTC_DISPLAY_DIS;
   2325       1.1   gdamore 	}
   2326       1.1   gdamore 	return ((GET32(dp->rd_softc, reg) & mask) ? 1 : 0);
   2327       1.1   gdamore }
   2328       1.1   gdamore 
   2329       1.1   gdamore void
   2330       1.1   gdamore radeonfb_blank(struct radeonfb_display *dp, int blank)
   2331       1.1   gdamore {
   2332       1.1   gdamore 	struct radeonfb_softc	*sc = dp->rd_softc;
   2333       1.1   gdamore 	uint32_t		reg, mask;
   2334       1.1   gdamore 	uint32_t		fpreg, fpval;
   2335       1.1   gdamore 	int			i;
   2336       1.1   gdamore 
   2337      1.68  macallan 	if (!sc->sc_mapped)
   2338      1.68  macallan 		return;
   2339      1.68  macallan 
   2340       1.1   gdamore 	for (i = 0; i < dp->rd_ncrtcs; i++) {
   2341       1.1   gdamore 
   2342       1.1   gdamore 		if (dp->rd_crtcs[i].rc_number) {
   2343       1.1   gdamore 			reg = RADEON_CRTC2_GEN_CNTL;
   2344       1.1   gdamore 			mask = RADEON_CRTC2_DISP_DIS;
   2345       1.1   gdamore 			fpreg = RADEON_FP2_GEN_CNTL;
   2346       1.1   gdamore 			fpval = RADEON_FP2_ON;
   2347       1.1   gdamore 		} else {
   2348       1.1   gdamore 			reg = RADEON_CRTC_EXT_CNTL;
   2349       1.1   gdamore 			mask = RADEON_CRTC_DISPLAY_DIS;
   2350       1.1   gdamore 			fpreg = RADEON_FP_GEN_CNTL;
   2351       1.1   gdamore 			fpval = RADEON_FP_FPON;
   2352       1.1   gdamore 		}
   2353      1.11        ad 
   2354       1.1   gdamore 		if (blank) {
   2355       1.1   gdamore 			SET32(sc, reg, mask);
   2356       1.1   gdamore 			CLR32(sc, fpreg, fpval);
   2357       1.1   gdamore 		} else {
   2358       1.1   gdamore 			CLR32(sc, reg, mask);
   2359       1.1   gdamore 			SET32(sc, fpreg, fpval);
   2360       1.1   gdamore 		}
   2361       1.1   gdamore 	}
   2362       1.1   gdamore 	PRINTREG(RADEON_FP_GEN_CNTL);
   2363       1.1   gdamore 	PRINTREG(RADEON_FP2_GEN_CNTL);
   2364       1.1   gdamore }
   2365       1.1   gdamore 
   2366       1.1   gdamore void
   2367       1.1   gdamore radeonfb_init_screen(void *cookie, struct vcons_screen *scr, int existing,
   2368       1.1   gdamore     long *defattr)
   2369       1.1   gdamore {
   2370       1.1   gdamore 	struct radeonfb_display *dp = cookie;
   2371       1.1   gdamore 	struct rasops_info *ri = &scr->scr_ri;
   2372       1.1   gdamore 
   2373       1.1   gdamore 	/* initialize font subsystem */
   2374       1.1   gdamore 	wsfont_init();
   2375       1.1   gdamore 
   2376       1.1   gdamore 	DPRINTF(("init screen called, existing %d\n", existing));
   2377       1.1   gdamore 
   2378       1.1   gdamore 	ri->ri_depth = dp->rd_bpp;
   2379       1.1   gdamore 	ri->ri_width = dp->rd_virtx;
   2380       1.1   gdamore 	ri->ri_height = dp->rd_virty;
   2381       1.1   gdamore 	ri->ri_stride = dp->rd_stride;
   2382       1.1   gdamore 	ri->ri_flg = RI_CENTER;
   2383      1.61  macallan 	switch (ri->ri_depth) {
   2384      1.61  macallan 		case 8:
   2385      1.61  macallan 			ri->ri_flg |= RI_ENABLE_ALPHA | RI_8BIT_IS_RGB;
   2386      1.61  macallan 			break;
   2387      1.61  macallan 		case 32:
   2388      1.65  macallan 			ri->ri_flg |= RI_ENABLE_ALPHA;
   2389      1.61  macallan 			/* we run radeons in RGB even on SPARC hardware */
   2390      1.61  macallan 			ri->ri_rnum = 8;
   2391      1.61  macallan 			ri->ri_gnum = 8;
   2392      1.61  macallan 			ri->ri_bnum = 8;
   2393      1.61  macallan 			ri->ri_rpos = 16;
   2394      1.61  macallan 			ri->ri_gpos = 8;
   2395      1.61  macallan 			ri->ri_bpos = 0;
   2396      1.61  macallan 			break;
   2397      1.55  macallan 	}
   2398      1.61  macallan 
   2399       1.1   gdamore 	ri->ri_bits = (void *)dp->rd_fbptr;
   2400       1.1   gdamore 
   2401      1.48  macallan #ifdef VCONS_DRAW_INTR
   2402      1.48  macallan 	scr->scr_flags |= VCONS_DONT_READ;
   2403      1.48  macallan #endif
   2404      1.48  macallan 
   2405       1.1   gdamore 	if (existing) {
   2406       1.1   gdamore 		ri->ri_flg |= RI_CLEAR;
   2407       1.1   gdamore 
   2408       1.1   gdamore 		/* start a modeswitch now */
   2409       1.1   gdamore 		radeonfb_modeswitch(dp);
   2410       1.1   gdamore 	}
   2411       1.1   gdamore 
   2412       1.1   gdamore 	/*
   2413       1.1   gdamore 	 * XXX: font selection should be based on properties, with some
   2414       1.1   gdamore 	 * normal/reasonable default.
   2415       1.1   gdamore 	 */
   2416       1.1   gdamore 
   2417       1.1   gdamore 	/* initialize and look for an initial font */
   2418      1.52  macallan 	rasops_init(ri, 0, 0);
   2419      1.64  macallan 	ri->ri_caps = WSSCREEN_UNDERLINE | WSSCREEN_HILIT |
   2420      1.64  macallan 		    WSSCREEN_WSCOLORS | WSSCREEN_REVERSE;
   2421       1.1   gdamore 
   2422       1.2  macallan 	rasops_reconfig(ri, dp->rd_virty / ri->ri_font->fontheight,
   2423       1.2  macallan 		    dp->rd_virtx / ri->ri_font->fontwidth);
   2424       1.2  macallan 
   2425       1.1   gdamore 	/* enable acceleration */
   2426      1.38  macallan 	dp->rd_putchar = ri->ri_ops.putchar;
   2427       1.1   gdamore 	ri->ri_ops.copyrows = radeonfb_copyrows;
   2428       1.1   gdamore 	ri->ri_ops.copycols = radeonfb_copycols;
   2429       1.1   gdamore 	ri->ri_ops.eraserows = radeonfb_eraserows;
   2430       1.1   gdamore 	ri->ri_ops.erasecols = radeonfb_erasecols;
   2431      1.49  macallan 	/* pick a putchar method based on font and Radeon model */
   2432      1.49  macallan 	if (ri->ri_font->stride < ri->ri_font->fontwidth) {
   2433      1.49  macallan 		/* got a bitmap font */
   2434      1.73  macallan #ifndef RADEONFB_ALWAYS_ACCEL_PUTCHAR
   2435      1.49  macallan 		if (IS_R300(dp->rd_softc)) {
   2436      1.49  macallan 			/*
   2437      1.49  macallan 			 * radeonfb_putchar() doesn't work right on some R3xx
   2438      1.49  macallan 			 * so we use software drawing here, the wrapper just
   2439      1.49  macallan 			 *  makes sure the engine is idle before scribbling
   2440      1.49  macallan 			 * into vram
   2441      1.49  macallan 			 */
   2442      1.49  macallan 			ri->ri_ops.putchar = radeonfb_putchar_wrapper;
   2443      1.73  macallan 		} else
   2444      1.73  macallan #endif
   2445      1.49  macallan 			ri->ri_ops.putchar = radeonfb_putchar;
   2446      1.48  macallan 	} else {
   2447      1.49  macallan 		/* got an alpha font */
   2448      1.55  macallan 		switch(ri->ri_depth) {
   2449      1.55  macallan 			case 32:
   2450      1.55  macallan 				ri->ri_ops.putchar = radeonfb_putchar_aa32;
   2451      1.55  macallan 				break;
   2452      1.55  macallan 			case 8:
   2453      1.55  macallan 				ri->ri_ops.putchar = radeonfb_putchar_aa8;
   2454      1.55  macallan 				break;
   2455      1.55  macallan 			default:
   2456      1.55  macallan 				/* XXX this should never happen */
   2457      1.64  macallan 				panic("%s: depth is not 8 or 32 but we got an" \
   2458      1.64  macallan 					 " alpha font?!", __func__);
   2459      1.55  macallan 		}
   2460       1.8  macallan 	}
   2461       1.1   gdamore 	ri->ri_ops.cursor = radeonfb_cursor;
   2462       1.1   gdamore }
   2463       1.1   gdamore 
   2464       1.1   gdamore void
   2465       1.1   gdamore radeonfb_set_fbloc(struct radeonfb_softc *sc)
   2466       1.1   gdamore {
   2467       1.1   gdamore 	uint32_t	gen, ext, gen2 = 0;
   2468       1.1   gdamore 	uint32_t	agploc, aperbase, apersize, mcfbloc;
   2469       1.1   gdamore 
   2470       1.1   gdamore 	gen = GET32(sc, RADEON_CRTC_GEN_CNTL);
   2471      1.69  macallan 	/* XXX */
   2472      1.69  macallan 	ext = GET32(sc, RADEON_CRTC_EXT_CNTL) & ~RADEON_CRTC_DISPLAY_DIS;
   2473       1.1   gdamore 	agploc = GET32(sc, RADEON_MC_AGP_LOCATION);
   2474       1.1   gdamore 	aperbase = GET32(sc, RADEON_CONFIG_APER_0_BASE);
   2475       1.1   gdamore 	apersize = GET32(sc, RADEON_CONFIG_APER_SIZE);
   2476       1.1   gdamore 
   2477       1.1   gdamore 	PUT32(sc, RADEON_CRTC_GEN_CNTL, gen | RADEON_CRTC_DISP_REQ_EN_B);
   2478       1.1   gdamore 	PUT32(sc, RADEON_CRTC_EXT_CNTL, ext | RADEON_CRTC_DISPLAY_DIS);
   2479      1.64  macallan #if 0
   2480      1.64  macallan 	PUT32(sc, RADEON_CRTC_GEN_CNTL, gen | RADEON_CRTC_DISPLAY_DIS);
   2481      1.64  macallan 	PUT32(sc, RADEON_CRTC_EXT_CNTL, ext | RADEON_CRTC_DISP_REQ_EN_B);
   2482      1.64  macallan #endif
   2483       1.1   gdamore 
   2484       1.1   gdamore 	if (HAS_CRTC2(sc)) {
   2485       1.1   gdamore 		gen2 = GET32(sc, RADEON_CRTC2_GEN_CNTL);
   2486      1.11        ad 		PUT32(sc, RADEON_CRTC2_GEN_CNTL,
   2487       1.1   gdamore 		    gen2 | RADEON_CRTC2_DISP_REQ_EN_B);
   2488       1.1   gdamore 	}
   2489       1.1   gdamore 
   2490       1.1   gdamore 	delay(100000);
   2491       1.1   gdamore 
   2492       1.1   gdamore 	mcfbloc = (aperbase >> 16) |
   2493       1.1   gdamore 	    ((aperbase + (apersize - 1)) & 0xffff0000);
   2494       1.1   gdamore 
   2495       1.1   gdamore 	sc->sc_aperbase = (mcfbloc & 0xffff) << 16;
   2496       1.1   gdamore 	sc->sc_memsz = apersize;
   2497       1.1   gdamore 
   2498       1.1   gdamore 	if (((agploc & 0xffff) << 16) !=
   2499       1.1   gdamore 	    ((mcfbloc & 0xffff0000U) + 0x10000)) {
   2500       1.1   gdamore 		agploc = mcfbloc & 0xffff0000U;
   2501       1.1   gdamore 		agploc |= ((agploc + 0x10000) >> 16);
   2502       1.1   gdamore 	}
   2503       1.1   gdamore 
   2504       1.1   gdamore 	PUT32(sc, RADEON_HOST_PATH_CNTL, 0);
   2505       1.1   gdamore 
   2506       1.1   gdamore 	PUT32(sc, RADEON_MC_FB_LOCATION, mcfbloc);
   2507       1.1   gdamore 	PUT32(sc, RADEON_MC_AGP_LOCATION, agploc);
   2508       1.1   gdamore 
   2509       1.1   gdamore 	DPRINTF(("aperbase = %u\n", aperbase));
   2510       1.1   gdamore 	PRINTREG(RADEON_MC_FB_LOCATION);
   2511       1.1   gdamore 	PRINTREG(RADEON_MC_AGP_LOCATION);
   2512       1.1   gdamore 
   2513       1.1   gdamore 	PUT32(sc, RADEON_DISPLAY_BASE_ADDR, sc->sc_aperbase);
   2514       1.1   gdamore 
   2515       1.1   gdamore 	if (HAS_CRTC2(sc))
   2516       1.1   gdamore 		PUT32(sc, RADEON_DISPLAY2_BASE_ADDR, sc->sc_aperbase);
   2517       1.1   gdamore 
   2518       1.1   gdamore 	PUT32(sc, RADEON_OV0_BASE_ADDR, sc->sc_aperbase);
   2519       1.1   gdamore 
   2520       1.1   gdamore #if 0
   2521       1.1   gdamore 	/* XXX: what is this AGP garbage? :-) */
   2522       1.1   gdamore 	PUT32(sc, RADEON_AGP_CNTL, 0x00100000);
   2523       1.1   gdamore #endif
   2524       1.1   gdamore 
   2525       1.1   gdamore 	delay(100000);
   2526       1.1   gdamore 
   2527       1.1   gdamore 	PUT32(sc, RADEON_CRTC_GEN_CNTL, gen);
   2528       1.1   gdamore 	PUT32(sc, RADEON_CRTC_EXT_CNTL, ext);
   2529       1.1   gdamore 
   2530       1.1   gdamore 	if (HAS_CRTC2(sc))
   2531       1.1   gdamore 		PUT32(sc, RADEON_CRTC2_GEN_CNTL, gen2);
   2532       1.1   gdamore }
   2533       1.1   gdamore 
   2534       1.1   gdamore void
   2535       1.1   gdamore radeonfb_init_misc(struct radeonfb_softc *sc)
   2536       1.1   gdamore {
   2537       1.1   gdamore 	PUT32(sc, RADEON_BUS_CNTL,
   2538       1.1   gdamore 	    RADEON_BUS_MASTER_DIS |
   2539       1.1   gdamore 	    RADEON_BUS_PREFETCH_MODE_ACT |
   2540       1.1   gdamore 	    RADEON_BUS_PCI_READ_RETRY_EN |
   2541       1.1   gdamore 	    RADEON_BUS_PCI_WRT_RETRY_EN |
   2542       1.1   gdamore 	    (3 << RADEON_BUS_RETRY_WS_SHIFT) |
   2543       1.1   gdamore 	    RADEON_BUS_MSTR_RD_MULT |
   2544       1.1   gdamore 	    RADEON_BUS_MSTR_RD_LINE |
   2545       1.1   gdamore 	    RADEON_BUS_RD_DISCARD_EN |
   2546       1.1   gdamore 	    RADEON_BUS_MSTR_DISCONNECT_EN |
   2547       1.1   gdamore 	    RADEON_BUS_READ_BURST);
   2548       1.1   gdamore 
   2549       1.1   gdamore 	PUT32(sc, RADEON_BUS_CNTL1, 0xf0);
   2550       1.1   gdamore 	/* PUT32(sc, RADEON_SEPROM_CNTL1, 0x09ff0000); */
   2551       1.1   gdamore 	PUT32(sc, RADEON_FCP_CNTL, RADEON_FCP0_SRC_GND);
   2552       1.1   gdamore 	PUT32(sc, RADEON_RBBM_CNTL,
   2553       1.1   gdamore 	    (3 << RADEON_RB_SETTLE_SHIFT) |
   2554       1.1   gdamore 	    (4 << RADEON_ABORTCLKS_HI_SHIFT) |
   2555       1.1   gdamore 	    (4 << RADEON_ABORTCLKS_CP_SHIFT) |
   2556       1.1   gdamore 	    (4 << RADEON_ABORTCLKS_CFIFO_SHIFT));
   2557       1.1   gdamore 
   2558       1.1   gdamore 	/* XXX: figure out what these mean! */
   2559       1.1   gdamore 	PUT32(sc, RADEON_AGP_CNTL, 0x00100000);
   2560       1.1   gdamore 	PUT32(sc, RADEON_HOST_PATH_CNTL, 0);
   2561      1.64  macallan #if 0
   2562      1.64  macallan 	PUT32(sc, RADEON_DISP_MISC_CNTL, 0x5bb00400);
   2563      1.64  macallan #endif
   2564       1.1   gdamore 
   2565       1.1   gdamore 	PUT32(sc, RADEON_GEN_INT_CNTL, 0);
   2566       1.1   gdamore 	PUT32(sc, RADEON_GEN_INT_STATUS, GET32(sc, RADEON_GEN_INT_STATUS));
   2567       1.1   gdamore }
   2568       1.1   gdamore 
   2569  1.76.4.1     rmind static void
   2570  1.76.4.1     rmind radeonfb_putpal(struct radeonfb_display *dp, int idx, int r, int g, int b)
   2571       1.1   gdamore {
   2572      1.70  macallan 	struct radeonfb_softc *sc = dp->rd_softc;
   2573  1.76.4.1     rmind 	int		crtc, cc;
   2574       1.1   gdamore 	uint32_t	vclk;
   2575       1.1   gdamore 
   2576       1.1   gdamore 	vclk = GETPLL(sc, RADEON_VCLK_ECP_CNTL);
   2577       1.1   gdamore 	PUTPLL(sc, RADEON_VCLK_ECP_CNTL, vclk & ~RADEON_PIXCLK_DAC_ALWAYS_ONb);
   2578       1.1   gdamore 
   2579      1.70  macallan 	/* initialize the palette for every CRTC used by this display */
   2580      1.70  macallan 	for (cc = 0; cc < dp->rd_ncrtcs; cc++) {
   2581      1.70  macallan 		crtc = dp->rd_crtcs[cc].rc_number;
   2582      1.72  macallan 		DPRINTF(("%s: doing crtc %d %d\n", __func__, cc, crtc));
   2583      1.70  macallan 
   2584      1.70  macallan 		if (crtc)
   2585      1.70  macallan 			SET32(sc, RADEON_DAC_CNTL2, RADEON_DAC2_PALETTE_ACC_CTL);
   2586      1.70  macallan 		else
   2587      1.70  macallan 			CLR32(sc, RADEON_DAC_CNTL2, RADEON_DAC2_PALETTE_ACC_CTL);
   2588      1.70  macallan 
   2589  1.76.4.1     rmind 		PUT32(sc, RADEON_PALETTE_INDEX, idx);
   2590  1.76.4.1     rmind             	PUT32(sc, RADEON_PALETTE_30_DATA,
   2591  1.76.4.1     rmind             	    (r << 22) | (g << 12) | (b << 2));
   2592  1.76.4.1     rmind 	}
   2593      1.70  macallan 
   2594  1.76.4.1     rmind 	PUTPLL(sc, RADEON_VCLK_ECP_CNTL, vclk);
   2595  1.76.4.1     rmind }
   2596      1.36  macallan 
   2597  1.76.4.1     rmind /*
   2598  1.76.4.1     rmind  * This loads a linear color map for true color.
   2599  1.76.4.1     rmind  */
   2600  1.76.4.1     rmind void
   2601  1.76.4.1     rmind radeonfb_init_palette(struct radeonfb_display *dp)
   2602  1.76.4.1     rmind {
   2603  1.76.4.1     rmind 	int		i;
   2604      1.70  macallan 
   2605  1.76.4.1     rmind #define	DAC_WIDTH ((1 << 10) - 1)
   2606  1.76.4.1     rmind #define	CLUT_WIDTH ((1 << 8) - 1)
   2607  1.76.4.1     rmind #define	CLUT_COLOR(i)      ((i * DAC_WIDTH * 2 / CLUT_WIDTH + 1) / 2)
   2608      1.55  macallan 
   2609  1.76.4.1     rmind 	if (dp->rd_bpp == 8) {
   2610  1.76.4.1     rmind 
   2611  1.76.4.1     rmind 		/* R3G3B2 palette */
   2612  1.76.4.1     rmind 		uint32_t tmp, r, g, b;
   2613  1.76.4.1     rmind 
   2614  1.76.4.1     rmind 	        for (i = 0; i <= CLUT_WIDTH; ++i) {
   2615  1.76.4.1     rmind 			tmp = i & 0xe0;
   2616  1.76.4.1     rmind 
   2617  1.76.4.1     rmind 			/*
   2618  1.76.4.1     rmind 			 * replicate bits so 0xe0 maps to a red value of 0xff
   2619  1.76.4.1     rmind 			 * in order to make white look actually white
   2620  1.76.4.1     rmind 			 */
   2621  1.76.4.1     rmind 			tmp |= (tmp >> 3) | (tmp >> 6);
   2622  1.76.4.1     rmind 			r = tmp;
   2623  1.76.4.1     rmind 
   2624  1.76.4.1     rmind 			tmp = (i & 0x1c) << 3;
   2625  1.76.4.1     rmind 			tmp |= (tmp >> 3) | (tmp >> 6);
   2626  1.76.4.1     rmind 			g = tmp;
   2627  1.76.4.1     rmind 
   2628  1.76.4.1     rmind 			tmp = (i & 0x03) << 6;
   2629  1.76.4.1     rmind 			tmp |= tmp >> 2;
   2630  1.76.4.1     rmind 			tmp |= tmp >> 4;
   2631  1.76.4.1     rmind 			b = tmp;
   2632  1.76.4.1     rmind 
   2633  1.76.4.1     rmind 			radeonfb_putpal(dp, i, r, g, b);
   2634  1.76.4.1     rmind 		}
   2635  1.76.4.1     rmind 	} else {
   2636  1.76.4.1     rmind 		/* linear ramp */
   2637  1.76.4.1     rmind 		for (i = 0; i <= CLUT_WIDTH; ++i) {
   2638  1.76.4.1     rmind 			radeonfb_putpal(dp, i, i, i, i);
   2639      1.36  macallan 		}
   2640       1.1   gdamore 	}
   2641  1.76.4.1     rmind }
   2642       1.1   gdamore 
   2643  1.76.4.1     rmind static int
   2644  1.76.4.1     rmind radeonfb_putcmap(struct radeonfb_display *dp, struct wsdisplay_cmap *cm)
   2645  1.76.4.1     rmind {
   2646  1.76.4.1     rmind 	u_char *r, *g, *b;
   2647  1.76.4.1     rmind 	u_int index = cm->index;
   2648  1.76.4.1     rmind 	u_int count = cm->count;
   2649  1.76.4.1     rmind 	int i, error;
   2650  1.76.4.1     rmind 	u_char rbuf[256], gbuf[256], bbuf[256];
   2651       1.1   gdamore 
   2652  1.76.4.1     rmind #ifdef GENFB_DEBUG
   2653  1.76.4.1     rmind 	aprint_debug("putcmap: %d %d\n",index, count);
   2654  1.76.4.1     rmind #endif
   2655  1.76.4.1     rmind 	if (cm->index >= 256 || cm->count > 256 ||
   2656  1.76.4.1     rmind 	    (cm->index + cm->count) > 256)
   2657  1.76.4.1     rmind 		return EINVAL;
   2658  1.76.4.1     rmind 	error = copyin(cm->red, &rbuf[index], count);
   2659  1.76.4.1     rmind 	if (error)
   2660  1.76.4.1     rmind 		return error;
   2661  1.76.4.1     rmind 	error = copyin(cm->green, &gbuf[index], count);
   2662  1.76.4.1     rmind 	if (error)
   2663  1.76.4.1     rmind 		return error;
   2664  1.76.4.1     rmind 	error = copyin(cm->blue, &bbuf[index], count);
   2665  1.76.4.1     rmind 	if (error)
   2666  1.76.4.1     rmind 		return error;
   2667  1.76.4.1     rmind 
   2668  1.76.4.1     rmind 	memcpy(&dp->rd_cmap_red[index], &rbuf[index], count);
   2669  1.76.4.1     rmind 	memcpy(&dp->rd_cmap_green[index], &gbuf[index], count);
   2670  1.76.4.1     rmind 	memcpy(&dp->rd_cmap_blue[index], &bbuf[index], count);
   2671  1.76.4.1     rmind 
   2672  1.76.4.1     rmind 	r = &dp->rd_cmap_red[index];
   2673  1.76.4.1     rmind 	g = &dp->rd_cmap_green[index];
   2674  1.76.4.1     rmind 	b = &dp->rd_cmap_blue[index];
   2675  1.76.4.1     rmind 
   2676  1.76.4.1     rmind 	for (i = 0; i < count; i++) {
   2677  1.76.4.1     rmind 		radeonfb_putpal(dp, index, *r, *g, *b);
   2678  1.76.4.1     rmind 		index++;
   2679  1.76.4.1     rmind 		r++, g++, b++;
   2680  1.76.4.1     rmind 	}
   2681  1.76.4.1     rmind 	return 0;
   2682  1.76.4.1     rmind }
   2683  1.76.4.1     rmind 
   2684  1.76.4.1     rmind static int
   2685  1.76.4.1     rmind radeonfb_getcmap(struct radeonfb_display *dp, struct wsdisplay_cmap *cm)
   2686  1.76.4.1     rmind {
   2687  1.76.4.1     rmind 	u_int index = cm->index;
   2688  1.76.4.1     rmind 	u_int count = cm->count;
   2689  1.76.4.1     rmind 	int error;
   2690  1.76.4.1     rmind 
   2691  1.76.4.1     rmind 	if (index >= 255 || count > 256 || index + count > 256)
   2692  1.76.4.1     rmind 		return EINVAL;
   2693  1.76.4.1     rmind 
   2694  1.76.4.1     rmind 	error = copyout(&dp->rd_cmap_red[index],   cm->red,   count);
   2695  1.76.4.1     rmind 	if (error)
   2696  1.76.4.1     rmind 		return error;
   2697  1.76.4.1     rmind 	error = copyout(&dp->rd_cmap_green[index], cm->green, count);
   2698  1.76.4.1     rmind 	if (error)
   2699  1.76.4.1     rmind 		return error;
   2700  1.76.4.1     rmind 	error = copyout(&dp->rd_cmap_blue[index],  cm->blue,  count);
   2701  1.76.4.1     rmind 	if (error)
   2702  1.76.4.1     rmind 		return error;
   2703  1.76.4.1     rmind 
   2704  1.76.4.1     rmind 	return 0;
   2705       1.1   gdamore }
   2706       1.1   gdamore 
   2707       1.1   gdamore /*
   2708       1.1   gdamore  * Bugs in some R300 hardware requires this when accessing CLOCK_CNTL_INDEX.
   2709       1.1   gdamore  */
   2710       1.1   gdamore void
   2711       1.1   gdamore radeonfb_r300cg_workaround(struct radeonfb_softc *sc)
   2712       1.1   gdamore {
   2713       1.1   gdamore 	uint32_t	tmp, save;
   2714       1.1   gdamore 
   2715       1.1   gdamore 	save = GET32(sc, RADEON_CLOCK_CNTL_INDEX);
   2716       1.1   gdamore 	tmp = save & ~(0x3f | RADEON_PLL_WR_EN);
   2717       1.1   gdamore 	PUT32(sc, RADEON_CLOCK_CNTL_INDEX, tmp);
   2718       1.1   gdamore 	tmp = GET32(sc, RADEON_CLOCK_CNTL_DATA);
   2719       1.1   gdamore 	PUT32(sc, RADEON_CLOCK_CNTL_INDEX, save);
   2720       1.1   gdamore }
   2721       1.1   gdamore 
   2722       1.1   gdamore /*
   2723       1.1   gdamore  * Acceleration entry points.
   2724       1.1   gdamore  */
   2725      1.49  macallan 
   2726      1.49  macallan /* this one draws characters using bitmap fonts */
   2727       1.2  macallan static void
   2728       1.2  macallan radeonfb_putchar(void *cookie, int row, int col, u_int c, long attr)
   2729       1.1   gdamore {
   2730       1.1   gdamore 	struct rasops_info	*ri = cookie;
   2731       1.1   gdamore 	struct vcons_screen	*scr = ri->ri_hw;
   2732       1.1   gdamore 	struct radeonfb_display	*dp = scr->scr_cookie;
   2733      1.48  macallan 	struct radeonfb_softc	*sc = dp->rd_softc;
   2734      1.35  macallan 	struct wsdisplay_font	*font = PICK_FONT(ri, c);
   2735      1.48  macallan 	uint32_t		w, h;
   2736      1.48  macallan 	int			xd, yd, offset, i;
   2737      1.48  macallan 	uint32_t		bg, fg, gmc;
   2738      1.48  macallan 	uint32_t		reg;
   2739      1.48  macallan 	uint8_t			*data8;
   2740      1.48  macallan 	uint16_t		*data16;
   2741      1.48  macallan 	void			*data;
   2742       1.1   gdamore 
   2743       1.1   gdamore 	if (dp->rd_wsmode != WSDISPLAYIO_MODE_EMUL)
   2744       1.1   gdamore 		return;
   2745       1.1   gdamore 
   2746      1.35  macallan 	if (!CHAR_IN_FONT(c, font))
   2747       1.1   gdamore 		return;
   2748       1.1   gdamore 
   2749      1.35  macallan 	w = font->fontwidth;
   2750      1.35  macallan 	h = font->fontheight;
   2751       1.1   gdamore 
   2752      1.48  macallan 	bg = ri->ri_devcmap[(attr >> 16) & 0xf];
   2753      1.48  macallan 	fg = ri->ri_devcmap[(attr >> 24) & 0xf];
   2754      1.48  macallan 
   2755      1.48  macallan 	xd = ri->ri_xorigin + col * w;
   2756      1.48  macallan 	yd = ri->ri_yorigin + row * h;
   2757      1.48  macallan 
   2758      1.48  macallan 	if (c == 0x20) {
   2759      1.48  macallan 		radeonfb_rectfill(dp, xd, yd, w, h, bg);
   2760      1.48  macallan 		return;
   2761      1.35  macallan 	}
   2762      1.50  macallan 	data = WSFONT_GLYPH(c, font);
   2763       1.1   gdamore 
   2764      1.48  macallan 	gmc = dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT;
   2765       1.1   gdamore 
   2766      1.48  macallan 	radeonfb_wait_fifo(sc, 9);
   2767      1.48  macallan 
   2768      1.48  macallan 	PUT32(sc, RADEON_DP_GUI_MASTER_CNTL,
   2769      1.48  macallan 	    RADEON_GMC_BRUSH_NONE |
   2770      1.48  macallan 	    RADEON_GMC_SRC_DATATYPE_MONO_FG_BG |
   2771      1.48  macallan 	    RADEON_GMC_DST_CLIPPING |
   2772      1.48  macallan 	    RADEON_ROP3_S |
   2773      1.48  macallan 	    RADEON_DP_SRC_SOURCE_HOST_DATA |
   2774      1.48  macallan 	    RADEON_GMC_CLR_CMP_CNTL_DIS |
   2775      1.48  macallan 	    RADEON_GMC_WR_MSK_DIS |
   2776      1.48  macallan 	    gmc);
   2777      1.48  macallan 
   2778      1.48  macallan 	PUT32(sc, RADEON_SC_LEFT, xd);
   2779      1.48  macallan 	PUT32(sc, RADEON_SC_RIGHT, xd + w);
   2780      1.48  macallan 	PUT32(sc, RADEON_DP_SRC_FRGD_CLR, fg);
   2781      1.48  macallan 	PUT32(sc, RADEON_DP_SRC_BKGD_CLR, bg);
   2782      1.48  macallan 	PUT32(sc, RADEON_DP_CNTL,
   2783      1.48  macallan 	    RADEON_DST_X_LEFT_TO_RIGHT |
   2784      1.48  macallan 	    RADEON_DST_Y_TOP_TO_BOTTOM);
   2785       1.1   gdamore 
   2786      1.48  macallan 	PUT32(sc, RADEON_SRC_X_Y, 0);
   2787      1.48  macallan 	offset = 32 - (font->stride << 3);
   2788      1.48  macallan 	PUT32(sc, RADEON_DST_X_Y, ((xd - offset) << 16) | yd);
   2789      1.48  macallan 	PUT32(sc, RADEON_DST_WIDTH_HEIGHT, (32 << 16) | h);
   2790      1.48  macallan 
   2791      1.48  macallan 	radeonfb_wait_fifo(sc, h);
   2792      1.48  macallan 	switch (font->stride) {
   2793      1.48  macallan 		case 1: {
   2794      1.48  macallan 			data8 = data;
   2795      1.48  macallan 			for (i = 0; i < h; i++) {
   2796      1.48  macallan 				reg = *data8;
   2797      1.67  macallan #if BYTE_ORDER == LITTLE_ENDIAN
   2798      1.67  macallan 				reg = reg << 24;
   2799      1.67  macallan #endif
   2800      1.49  macallan 				bus_space_write_stream_4(sc->sc_regt,
   2801      1.48  macallan 				    sc->sc_regh, RADEON_HOST_DATA0, reg);
   2802      1.48  macallan 				data8++;
   2803      1.48  macallan 			}
   2804      1.48  macallan 			break;
   2805      1.48  macallan 		}
   2806      1.48  macallan 		case 2: {
   2807      1.48  macallan 			data16 = data;
   2808      1.48  macallan 			for (i = 0; i < h; i++) {
   2809      1.48  macallan 				reg = *data16;
   2810      1.67  macallan #if BYTE_ORDER == LITTLE_ENDIAN
   2811      1.67  macallan 				reg = reg << 16;
   2812      1.67  macallan #endif
   2813      1.49  macallan 				bus_space_write_stream_4(sc->sc_regt,
   2814      1.48  macallan 				    sc->sc_regh, RADEON_HOST_DATA0, reg);
   2815      1.48  macallan 				data16++;
   2816      1.48  macallan 			}
   2817      1.48  macallan 			break;
   2818      1.48  macallan 		}
   2819       1.1   gdamore 	}
   2820      1.64  macallan 	if (attr & 1)
   2821      1.64  macallan 		radeonfb_rectfill(dp, xd, yd + h - 2, w, 1, fg);
   2822       1.1   gdamore }
   2823       1.1   gdamore 
   2824      1.49  macallan /* ... while this one is for anti-aliased ones */
   2825      1.49  macallan static void
   2826      1.49  macallan radeonfb_putchar_aa32(void *cookie, int row, int col, u_int c, long attr)
   2827      1.49  macallan {
   2828      1.49  macallan 	struct rasops_info	*ri = cookie;
   2829      1.49  macallan 	struct vcons_screen	*scr = ri->ri_hw;
   2830      1.49  macallan 	struct radeonfb_display	*dp = scr->scr_cookie;
   2831      1.49  macallan 	struct radeonfb_softc	*sc = dp->rd_softc;
   2832      1.49  macallan 	struct wsdisplay_font	*font = PICK_FONT(ri, c);
   2833      1.49  macallan 	uint32_t		bg, fg, gmc;
   2834      1.49  macallan 	uint8_t			*data;
   2835      1.49  macallan 	int			w, h, xd, yd;
   2836      1.49  macallan 	int 			i, r, g, b, aval;
   2837      1.49  macallan 	int 			rf, gf, bf, rb, gb, bb;
   2838      1.49  macallan 	uint32_t 		pixel;
   2839      1.54  macallan 	int rv;
   2840      1.49  macallan 
   2841      1.49  macallan 	if (dp->rd_wsmode != WSDISPLAYIO_MODE_EMUL)
   2842      1.49  macallan 		return;
   2843      1.49  macallan 
   2844      1.49  macallan 	if (!CHAR_IN_FONT(c, font))
   2845      1.49  macallan 		return;
   2846      1.49  macallan 
   2847      1.49  macallan 	w = font->fontwidth;
   2848      1.49  macallan 	h = font->fontheight;
   2849      1.49  macallan 
   2850      1.49  macallan 	bg = ri->ri_devcmap[(attr >> 16) & 0xf];
   2851      1.49  macallan 	fg = ri->ri_devcmap[(attr >> 24) & 0xf];
   2852      1.49  macallan 
   2853      1.49  macallan 	xd = ri->ri_xorigin + col * w;
   2854      1.49  macallan 	yd = ri->ri_yorigin + row * h;
   2855      1.49  macallan 
   2856      1.49  macallan 	if (c == 0x20) {
   2857      1.49  macallan 		radeonfb_rectfill(dp, xd, yd, w, h, bg);
   2858      1.64  macallan 		if (attr & 1)
   2859      1.64  macallan 			radeonfb_rectfill(dp, xd, yd + h - 2, w, 1, fg);
   2860      1.49  macallan 		return;
   2861      1.49  macallan 	}
   2862      1.54  macallan 	rv = glyphcache_try(&dp->rd_gc, c, xd, yd, attr);
   2863      1.54  macallan 	if (rv == GC_OK)
   2864      1.54  macallan 		return;
   2865      1.54  macallan 
   2866      1.50  macallan 	data = WSFONT_GLYPH(c, font);
   2867      1.49  macallan 
   2868      1.49  macallan 	gmc = dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT;
   2869      1.49  macallan 
   2870      1.49  macallan 	radeonfb_wait_fifo(sc, 5);
   2871      1.49  macallan 
   2872      1.49  macallan 	PUT32(sc, RADEON_DP_GUI_MASTER_CNTL,
   2873      1.49  macallan 	    RADEON_GMC_BRUSH_NONE |
   2874      1.49  macallan 	    RADEON_GMC_SRC_DATATYPE_COLOR |
   2875      1.49  macallan 	    RADEON_ROP3_S |
   2876      1.49  macallan 	    RADEON_DP_SRC_SOURCE_HOST_DATA |
   2877      1.49  macallan 	    RADEON_GMC_CLR_CMP_CNTL_DIS |
   2878      1.49  macallan 	    RADEON_GMC_WR_MSK_DIS |
   2879      1.49  macallan 	    gmc);
   2880      1.49  macallan 
   2881      1.49  macallan 	PUT32(sc, RADEON_DP_CNTL,
   2882      1.49  macallan 	    RADEON_DST_X_LEFT_TO_RIGHT |
   2883      1.49  macallan 	    RADEON_DST_Y_TOP_TO_BOTTOM);
   2884      1.49  macallan 
   2885      1.49  macallan 	PUT32(sc, RADEON_SRC_X_Y, 0);
   2886      1.49  macallan 	PUT32(sc, RADEON_DST_X_Y, (xd << 16) | yd);
   2887      1.49  macallan 	PUT32(sc, RADEON_DST_WIDTH_HEIGHT, (w << 16) | h);
   2888      1.49  macallan 
   2889      1.49  macallan 	rf = (fg >> 16) & 0xff;
   2890      1.49  macallan 	rb = (bg >> 16) & 0xff;
   2891      1.49  macallan 	gf = (fg >> 8) & 0xff;
   2892      1.49  macallan 	gb = (bg >> 8) & 0xff;
   2893      1.49  macallan 	bf =  fg & 0xff;
   2894      1.49  macallan 	bb =  bg & 0xff;
   2895      1.49  macallan 
   2896      1.49  macallan 	/*
   2897      1.49  macallan 	 * I doubt we can upload data faster than even the slowest Radeon
   2898      1.49  macallan 	 * could process them, especially when doing the alpha blending stuff
   2899      1.49  macallan 	 * along the way, so just make sure there's some room in the FIFO and
   2900      1.49  macallan 	 * then hammer away
   2901      1.51  macallan 	 * As it turns out we can, so make periodic stops to let the FIFO
   2902      1.51  macallan 	 * drain.
   2903      1.49  macallan 	 */
   2904      1.51  macallan 	radeonfb_wait_fifo(sc, 20);
   2905      1.49  macallan 	for (i = 0; i < ri->ri_fontscale; i++) {
   2906      1.49  macallan 		aval = *data;
   2907      1.49  macallan 		data++;
   2908      1.49  macallan 		if (aval == 0) {
   2909      1.49  macallan 			pixel = bg;
   2910      1.49  macallan 		} else if (aval == 255) {
   2911      1.49  macallan 			pixel = fg;
   2912      1.49  macallan 		} else {
   2913      1.49  macallan 			r = aval * rf + (255 - aval) * rb;
   2914      1.49  macallan 			g = aval * gf + (255 - aval) * gb;
   2915      1.49  macallan 			b = aval * bf + (255 - aval) * bb;
   2916      1.49  macallan 			pixel = (r & 0xff00) << 8 |
   2917      1.49  macallan 			        (g & 0xff00) |
   2918      1.49  macallan 			        (b & 0xff00) >> 8;
   2919      1.49  macallan 		}
   2920      1.51  macallan 		if (i & 16)
   2921      1.51  macallan 			radeonfb_wait_fifo(sc, 20);
   2922      1.49  macallan 		PUT32(sc, RADEON_HOST_DATA0, pixel);
   2923      1.49  macallan 	}
   2924      1.64  macallan 	if (rv == GC_ADD) {
   2925      1.54  macallan 		glyphcache_add(&dp->rd_gc, c, xd, yd);
   2926      1.64  macallan 	} else
   2927      1.64  macallan 		if (attr & 1)
   2928      1.64  macallan 			radeonfb_rectfill(dp, xd, yd + h - 2, w, 1, fg);
   2929      1.64  macallan 
   2930      1.49  macallan }
   2931      1.49  macallan 
   2932      1.55  macallan static void
   2933      1.55  macallan radeonfb_putchar_aa8(void *cookie, int row, int col, u_int c, long attr)
   2934      1.55  macallan {
   2935      1.55  macallan 	struct rasops_info	*ri = cookie;
   2936      1.55  macallan 	struct vcons_screen	*scr = ri->ri_hw;
   2937      1.55  macallan 	struct radeonfb_display	*dp = scr->scr_cookie;
   2938      1.55  macallan 	struct radeonfb_softc	*sc = dp->rd_softc;
   2939      1.55  macallan 	struct wsdisplay_font	*font = PICK_FONT(ri, c);
   2940      1.64  macallan 	uint32_t bg, fg, latch = 0, bg8, fg8, pixel, gmc;
   2941      1.55  macallan 	int i, x, y, wi, he, r, g, b, aval;
   2942      1.55  macallan 	int r1, g1, b1, r0, g0, b0, fgo, bgo;
   2943      1.55  macallan 	uint8_t *data8;
   2944      1.57  macallan 	int rv, cnt;
   2945      1.55  macallan 
   2946      1.55  macallan 	if (dp->rd_wsmode != WSDISPLAYIO_MODE_EMUL)
   2947      1.55  macallan 		return;
   2948      1.55  macallan 
   2949      1.55  macallan 	if (!CHAR_IN_FONT(c, font))
   2950      1.55  macallan 		return;
   2951      1.55  macallan 
   2952      1.55  macallan 	wi = font->fontwidth;
   2953      1.55  macallan 	he = font->fontheight;
   2954      1.55  macallan 
   2955      1.55  macallan 	bg = ri->ri_devcmap[(attr >> 16) & 0xf];
   2956      1.64  macallan 	fg = ri->ri_devcmap[(attr >> 24) & 0xf];
   2957      1.55  macallan 
   2958      1.55  macallan 	x = ri->ri_xorigin + col * wi;
   2959      1.55  macallan 	y = ri->ri_yorigin + row * he;
   2960      1.55  macallan 
   2961      1.55  macallan 	if (c == 0x20) {
   2962      1.55  macallan 		radeonfb_rectfill(dp, x, y, wi, he, bg);
   2963      1.64  macallan 		if (attr & 1)
   2964      1.64  macallan 			radeonfb_rectfill(dp, x, y + he - 2, wi, 1, fg);
   2965      1.55  macallan 		return;
   2966      1.55  macallan 	}
   2967      1.55  macallan 	rv = glyphcache_try(&dp->rd_gc, c, x, y, attr);
   2968      1.55  macallan 	if (rv == GC_OK)
   2969      1.55  macallan 		return;
   2970      1.55  macallan 
   2971      1.55  macallan 	data8 = WSFONT_GLYPH(c, font);
   2972      1.55  macallan 
   2973      1.55  macallan 	gmc = dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT;
   2974      1.55  macallan 
   2975      1.55  macallan 	radeonfb_wait_fifo(sc, 5);
   2976      1.55  macallan 
   2977      1.55  macallan 	PUT32(sc, RADEON_DP_GUI_MASTER_CNTL,
   2978      1.55  macallan 	    RADEON_GMC_BRUSH_NONE |
   2979      1.55  macallan 	    RADEON_GMC_SRC_DATATYPE_COLOR |
   2980      1.55  macallan 	    RADEON_ROP3_S |
   2981      1.55  macallan 	    RADEON_DP_SRC_SOURCE_HOST_DATA |
   2982      1.55  macallan 	    RADEON_GMC_CLR_CMP_CNTL_DIS |
   2983      1.55  macallan 	    RADEON_GMC_WR_MSK_DIS |
   2984      1.55  macallan 	    gmc);
   2985      1.55  macallan 
   2986      1.55  macallan 	PUT32(sc, RADEON_DP_CNTL,
   2987      1.55  macallan 	    RADEON_DST_X_LEFT_TO_RIGHT |
   2988      1.55  macallan 	    RADEON_DST_Y_TOP_TO_BOTTOM);
   2989      1.55  macallan 
   2990      1.55  macallan 	PUT32(sc, RADEON_SRC_X_Y, 0);
   2991      1.55  macallan 	PUT32(sc, RADEON_DST_X_Y, (x << 16) | y);
   2992      1.55  macallan 	PUT32(sc, RADEON_DST_WIDTH_HEIGHT, (wi << 16) | he);
   2993      1.55  macallan 
   2994      1.55  macallan 	/*
   2995      1.55  macallan 	 * we need the RGB colours here, so get offsets into rasops_cmap
   2996      1.55  macallan 	 */
   2997      1.55  macallan 	fgo = ((attr >> 24) & 0xf) * 3;
   2998      1.55  macallan 	bgo = ((attr >> 16) & 0xf) * 3;
   2999      1.55  macallan 
   3000      1.55  macallan 	r0 = rasops_cmap[bgo];
   3001      1.55  macallan 	r1 = rasops_cmap[fgo];
   3002      1.55  macallan 	g0 = rasops_cmap[bgo + 1];
   3003      1.55  macallan 	g1 = rasops_cmap[fgo + 1];
   3004      1.55  macallan 	b0 = rasops_cmap[bgo + 2];
   3005      1.55  macallan 	b1 = rasops_cmap[fgo + 2];
   3006      1.55  macallan #define R3G3B2(r, g, b) ((r & 0xe0) | ((g >> 3) & 0x1c) | (b >> 6))
   3007      1.55  macallan 	bg8 = R3G3B2(r0, g0, b0);
   3008      1.55  macallan 	fg8 = R3G3B2(r1, g1, b1);
   3009      1.57  macallan 
   3010      1.57  macallan 	radeonfb_wait_fifo(sc, 20);
   3011      1.57  macallan 	cnt = 0;
   3012      1.55  macallan 	for (i = 0; i < ri->ri_fontscale; i++) {
   3013      1.55  macallan 		aval = *data8;
   3014      1.55  macallan 		if (aval == 0) {
   3015      1.55  macallan 			pixel = bg8;
   3016      1.55  macallan 		} else if (aval == 255) {
   3017      1.55  macallan 			pixel = fg8;
   3018      1.55  macallan 		} else {
   3019      1.55  macallan 			r = aval * r1 + (255 - aval) * r0;
   3020      1.55  macallan 			g = aval * g1 + (255 - aval) * g0;
   3021      1.55  macallan 			b = aval * b1 + (255 - aval) * b0;
   3022      1.55  macallan 			pixel = ((r & 0xe000) >> 8) |
   3023      1.55  macallan 				((g & 0xe000) >> 11) |
   3024      1.55  macallan 				((b & 0xc000) >> 14);
   3025      1.55  macallan 		}
   3026      1.67  macallan 		latch |= pixel << (8 * (i & 3));
   3027      1.55  macallan 		/* write in 32bit chunks */
   3028      1.55  macallan 		if ((i & 3) == 3) {
   3029      1.67  macallan 			PUT32(sc, RADEON_HOST_DATA0, latch);
   3030      1.55  macallan 			/*
   3031      1.55  macallan 			 * not strictly necessary, old data should be shifted
   3032      1.55  macallan 			 * out
   3033      1.55  macallan 			 */
   3034      1.55  macallan 			latch = 0;
   3035      1.57  macallan 			cnt++;
   3036      1.57  macallan 			if (cnt > 16) {
   3037      1.57  macallan 				cnt = 0;
   3038      1.57  macallan 				radeonfb_wait_fifo(sc, 20);
   3039      1.57  macallan 			}
   3040      1.55  macallan 		}
   3041      1.55  macallan 		data8++;
   3042      1.55  macallan 	}
   3043      1.55  macallan 	/* if we have pixels left in latch write them out */
   3044      1.55  macallan 	if ((i & 3) != 0) {
   3045      1.60  macallan 		/*
   3046      1.60  macallan 		 * radeon is weird - apparently leftover pixels are written
   3047      1.60  macallan 		 * from the middle, not from the left as everything else
   3048      1.60  macallan 		 */
   3049      1.55  macallan 		PUT32(sc, RADEON_HOST_DATA0, latch);
   3050      1.55  macallan 	}
   3051      1.55  macallan 
   3052      1.64  macallan 	if (rv == GC_ADD) {
   3053      1.55  macallan 		glyphcache_add(&dp->rd_gc, c, x, y);
   3054      1.64  macallan 	} else
   3055      1.64  macallan 		if (attr & 1)
   3056      1.64  macallan 			radeonfb_rectfill(dp, x, y + he - 2, wi, 1, fg);
   3057      1.64  macallan 
   3058      1.55  macallan }
   3059      1.55  macallan 
   3060      1.38  macallan /*
   3061      1.38  macallan  * wrapper for software character drawing
   3062      1.38  macallan  * just sync the engine and call rasops*_putchar()
   3063      1.38  macallan  */
   3064      1.38  macallan 
   3065      1.73  macallan #ifndef RADEONFB_ALWAYS_ACCEL_PUTCHAR
   3066      1.38  macallan static void
   3067      1.38  macallan radeonfb_putchar_wrapper(void *cookie, int row, int col, u_int c, long attr)
   3068      1.38  macallan {
   3069      1.38  macallan 	struct rasops_info	*ri = cookie;
   3070      1.38  macallan 	struct vcons_screen	*scr = ri->ri_hw;
   3071      1.38  macallan 	struct radeonfb_display	*dp = scr->scr_cookie;
   3072      1.38  macallan 
   3073      1.38  macallan 	radeonfb_engine_idle(dp->rd_softc);
   3074      1.38  macallan 	dp->rd_putchar(ri, row, col, c, attr);
   3075      1.38  macallan }
   3076      1.73  macallan #endif
   3077      1.38  macallan 
   3078       1.2  macallan static void
   3079       1.1   gdamore radeonfb_eraserows(void *cookie, int row, int nrows, long fillattr)
   3080       1.1   gdamore {
   3081       1.1   gdamore 	struct rasops_info	*ri = cookie;
   3082       1.1   gdamore 	struct vcons_screen	*scr = ri->ri_hw;
   3083       1.1   gdamore 	struct radeonfb_display	*dp = scr->scr_cookie;
   3084       1.1   gdamore 	uint32_t		x, y, w, h, fg, bg, ul;
   3085       1.1   gdamore 
   3086       1.1   gdamore 	/* XXX: check for full emulation mode? */
   3087       1.1   gdamore 	if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) {
   3088       1.1   gdamore 		x = ri->ri_xorigin;
   3089       1.1   gdamore 		y = ri->ri_yorigin + ri->ri_font->fontheight * row;
   3090       1.1   gdamore 		w = ri->ri_emuwidth;
   3091       1.1   gdamore 		h = ri->ri_font->fontheight * nrows;
   3092       1.1   gdamore 
   3093       1.1   gdamore 		rasops_unpack_attr(fillattr, &fg, &bg, &ul);
   3094       1.2  macallan 		radeonfb_rectfill(dp, x, y, w, h, ri->ri_devcmap[bg & 0xf]);
   3095       1.1   gdamore 	}
   3096       1.1   gdamore }
   3097       1.1   gdamore 
   3098       1.2  macallan static void
   3099       1.1   gdamore radeonfb_copyrows(void *cookie, int srcrow, int dstrow, int nrows)
   3100       1.1   gdamore {
   3101       1.1   gdamore 	struct rasops_info	*ri = cookie;
   3102       1.1   gdamore 	struct vcons_screen	*scr = ri->ri_hw;
   3103       1.1   gdamore 	struct radeonfb_display	*dp = scr->scr_cookie;
   3104       1.1   gdamore 	uint32_t		x, ys, yd, w, h;
   3105       1.1   gdamore 
   3106       1.1   gdamore 	if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) {
   3107       1.1   gdamore 		x = ri->ri_xorigin;
   3108       1.1   gdamore 		ys = ri->ri_yorigin + ri->ri_font->fontheight * srcrow;
   3109       1.1   gdamore 		yd = ri->ri_yorigin + ri->ri_font->fontheight * dstrow;
   3110       1.1   gdamore 		w = ri->ri_emuwidth;
   3111       1.1   gdamore 		h = ri->ri_font->fontheight * nrows;
   3112       1.1   gdamore 		radeonfb_bitblt(dp, x, ys, x, yd, w, h,
   3113      1.54  macallan 		    RADEON_ROP3_S);
   3114       1.1   gdamore 	}
   3115       1.1   gdamore }
   3116       1.1   gdamore 
   3117       1.2  macallan static void
   3118       1.1   gdamore radeonfb_copycols(void *cookie, int row, int srccol, int dstcol, int ncols)
   3119       1.1   gdamore {
   3120       1.1   gdamore 	struct rasops_info	*ri = cookie;
   3121       1.1   gdamore 	struct vcons_screen	*scr = ri->ri_hw;
   3122       1.1   gdamore 	struct radeonfb_display	*dp = scr->scr_cookie;
   3123       1.1   gdamore 	uint32_t		xs, xd, y, w, h;
   3124       1.1   gdamore 
   3125       1.1   gdamore 	if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) {
   3126       1.1   gdamore 		xs = ri->ri_xorigin + ri->ri_font->fontwidth * srccol;
   3127       1.1   gdamore 		xd = ri->ri_xorigin + ri->ri_font->fontwidth * dstcol;
   3128       1.1   gdamore 		y = ri->ri_yorigin + ri->ri_font->fontheight * row;
   3129       1.1   gdamore 		w = ri->ri_font->fontwidth * ncols;
   3130       1.1   gdamore 		h = ri->ri_font->fontheight;
   3131       1.1   gdamore 		radeonfb_bitblt(dp, xs, y, xd, y, w, h,
   3132      1.54  macallan 		    RADEON_ROP3_S);
   3133       1.1   gdamore 	}
   3134       1.1   gdamore }
   3135       1.1   gdamore 
   3136       1.2  macallan static void
   3137       1.1   gdamore radeonfb_erasecols(void *cookie, int row, int startcol, int ncols,
   3138       1.1   gdamore     long fillattr)
   3139       1.1   gdamore {
   3140       1.1   gdamore 	struct rasops_info	*ri = cookie;
   3141       1.1   gdamore 	struct vcons_screen	*scr = ri->ri_hw;
   3142       1.1   gdamore 	struct radeonfb_display	*dp = scr->scr_cookie;
   3143       1.1   gdamore 	uint32_t		x, y, w, h, fg, bg, ul;
   3144       1.1   gdamore 
   3145       1.1   gdamore 	if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) {
   3146       1.1   gdamore 		x = ri->ri_xorigin + ri->ri_font->fontwidth * startcol;
   3147       1.1   gdamore 		y = ri->ri_yorigin + ri->ri_font->fontheight * row;
   3148       1.1   gdamore 		w = ri->ri_font->fontwidth * ncols;
   3149       1.1   gdamore 		h = ri->ri_font->fontheight;
   3150       1.1   gdamore 
   3151       1.1   gdamore 		rasops_unpack_attr(fillattr, &fg, &bg, &ul);
   3152       1.2  macallan 		radeonfb_rectfill(dp, x, y, w, h, ri->ri_devcmap[bg & 0xf]);
   3153       1.1   gdamore 	}
   3154       1.1   gdamore }
   3155       1.1   gdamore 
   3156       1.2  macallan static void
   3157       1.1   gdamore radeonfb_cursor(void *cookie, int on, int row, int col)
   3158       1.1   gdamore {
   3159       1.1   gdamore 	struct rasops_info *ri = cookie;
   3160       1.1   gdamore 	struct vcons_screen *scr = ri->ri_hw;
   3161       1.1   gdamore 	struct radeonfb_display	*dp = scr->scr_cookie;
   3162       1.1   gdamore 	int x, y, wi, he;
   3163      1.11        ad 
   3164       1.1   gdamore 	wi = ri->ri_font->fontwidth;
   3165       1.1   gdamore 	he = ri->ri_font->fontheight;
   3166      1.11        ad 
   3167       1.1   gdamore 	if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) {
   3168       1.1   gdamore 		x = ri->ri_ccol * wi + ri->ri_xorigin;
   3169       1.1   gdamore 		y = ri->ri_crow * he + ri->ri_yorigin;
   3170       1.1   gdamore 		/* first turn off the old cursor */
   3171       1.1   gdamore 		if (ri->ri_flg & RI_CURSOR) {
   3172       1.1   gdamore 			radeonfb_bitblt(dp, x, y, x, y, wi, he,
   3173      1.54  macallan 			    RADEON_ROP3_Dn);
   3174       1.1   gdamore 			ri->ri_flg &= ~RI_CURSOR;
   3175       1.1   gdamore 		}
   3176       1.1   gdamore 		ri->ri_crow = row;
   3177       1.1   gdamore 		ri->ri_ccol = col;
   3178       1.1   gdamore 		/* then (possibly) turn on the new one */
   3179       1.1   gdamore 		if (on) {
   3180       1.1   gdamore 			x = ri->ri_ccol * wi + ri->ri_xorigin;
   3181       1.1   gdamore 			y = ri->ri_crow * he + ri->ri_yorigin;
   3182       1.1   gdamore 			radeonfb_bitblt(dp, x, y, x, y, wi, he,
   3183      1.54  macallan 			    RADEON_ROP3_Dn);
   3184       1.2  macallan 			ri->ri_flg |= RI_CURSOR;
   3185       1.1   gdamore 		}
   3186       1.1   gdamore 	} else {
   3187       1.1   gdamore 		scr->scr_ri.ri_crow = row;
   3188       1.1   gdamore 		scr->scr_ri.ri_ccol = col;
   3189       1.1   gdamore 		scr->scr_ri.ri_flg &= ~RI_CURSOR;
   3190       1.1   gdamore 	}
   3191       1.1   gdamore }
   3192       1.1   gdamore 
   3193       1.1   gdamore /*
   3194       1.1   gdamore  * Underlying acceleration support.
   3195       1.1   gdamore  */
   3196       1.1   gdamore 
   3197       1.2  macallan static void
   3198       1.2  macallan radeonfb_rectfill(struct radeonfb_display *dp, int dstx, int dsty,
   3199       1.1   gdamore     int width, int height, uint32_t color)
   3200       1.1   gdamore {
   3201       1.1   gdamore 	struct radeonfb_softc	*sc = dp->rd_softc;
   3202       1.1   gdamore 	uint32_t		gmc;
   3203       1.1   gdamore 
   3204       1.1   gdamore 	gmc = dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT;
   3205       1.1   gdamore 
   3206       1.1   gdamore 	radeonfb_wait_fifo(sc, 6);
   3207       1.1   gdamore 
   3208       1.1   gdamore 	PUT32(sc, RADEON_DP_GUI_MASTER_CNTL,
   3209       1.1   gdamore 	    RADEON_GMC_BRUSH_SOLID_COLOR |
   3210       1.1   gdamore 	    RADEON_GMC_SRC_DATATYPE_COLOR |
   3211       1.1   gdamore 	    RADEON_GMC_CLR_CMP_CNTL_DIS |
   3212       1.1   gdamore 	    RADEON_ROP3_P | gmc);
   3213       1.1   gdamore 
   3214       1.1   gdamore 	PUT32(sc, RADEON_DP_BRUSH_FRGD_CLR, color);
   3215       1.1   gdamore 	PUT32(sc, RADEON_DP_WRITE_MASK, 0xffffffff);
   3216       1.1   gdamore 	PUT32(sc, RADEON_DP_CNTL,
   3217       1.1   gdamore 	    RADEON_DST_X_LEFT_TO_RIGHT |
   3218       1.1   gdamore 	    RADEON_DST_Y_TOP_TO_BOTTOM);
   3219       1.1   gdamore 	PUT32(sc, RADEON_DST_Y_X, (dsty << 16) | dstx);
   3220       1.1   gdamore 	PUT32(sc, RADEON_DST_WIDTH_HEIGHT, (width << 16) | (height));
   3221       1.1   gdamore 
   3222       1.1   gdamore }
   3223       1.1   gdamore 
   3224       1.2  macallan static void
   3225      1.64  macallan radeonfb_rectfill_a(void *cookie, int dstx, int dsty,
   3226      1.64  macallan     int width, int height, long attr)
   3227      1.64  macallan {
   3228      1.64  macallan 	struct radeonfb_display *dp = cookie;
   3229      1.64  macallan 
   3230      1.64  macallan 	radeonfb_rectfill(dp, dstx, dsty, width, height,
   3231      1.64  macallan 	    dp->rd_vscreen.scr_ri.ri_devcmap[(attr >> 24 & 0xf)]);
   3232      1.64  macallan }
   3233      1.64  macallan 
   3234      1.64  macallan static void
   3235      1.54  macallan radeonfb_bitblt(void *cookie, int srcx, int srcy,
   3236      1.54  macallan     int dstx, int dsty, int width, int height, int rop)
   3237       1.1   gdamore {
   3238      1.54  macallan 	struct radeonfb_display *dp = cookie;
   3239       1.1   gdamore 	struct radeonfb_softc	*sc = dp->rd_softc;
   3240       1.1   gdamore 	uint32_t		gmc;
   3241       1.1   gdamore 	uint32_t		dir;
   3242       1.1   gdamore 
   3243       1.1   gdamore 	if (dsty < srcy) {
   3244       1.1   gdamore 		dir = RADEON_DST_Y_TOP_TO_BOTTOM;
   3245       1.1   gdamore 	} else {
   3246       1.1   gdamore 		srcy += height - 1;
   3247       1.1   gdamore 		dsty += height - 1;
   3248       1.1   gdamore 		dir = 0;
   3249       1.1   gdamore 	}
   3250       1.6   gdamore 	if (dstx < srcx) {
   3251       1.1   gdamore 		dir |= RADEON_DST_X_LEFT_TO_RIGHT;
   3252       1.1   gdamore 	} else {
   3253       1.1   gdamore 		srcx += width - 1;
   3254       1.1   gdamore 		dstx += width - 1;
   3255       1.1   gdamore 	}
   3256       1.1   gdamore 
   3257       1.1   gdamore 	gmc = dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT;
   3258      1.11        ad 
   3259       1.1   gdamore 	radeonfb_wait_fifo(sc, 6);
   3260       1.1   gdamore 
   3261       1.1   gdamore 	PUT32(sc, RADEON_DP_GUI_MASTER_CNTL,
   3262       1.1   gdamore 	    RADEON_GMC_BRUSH_SOLID_COLOR |
   3263       1.1   gdamore 	    RADEON_GMC_SRC_DATATYPE_COLOR |
   3264       1.1   gdamore 	    RADEON_GMC_CLR_CMP_CNTL_DIS |
   3265       1.1   gdamore 	    RADEON_DP_SRC_SOURCE_MEMORY |
   3266       1.1   gdamore 	    rop | gmc);
   3267       1.1   gdamore 
   3268      1.54  macallan 	PUT32(sc, RADEON_DP_WRITE_MASK, 0xffffffff);
   3269       1.1   gdamore 	PUT32(sc, RADEON_DP_CNTL, dir);
   3270       1.1   gdamore 	PUT32(sc, RADEON_SRC_Y_X, (srcy << 16) | srcx);
   3271       1.1   gdamore 	PUT32(sc, RADEON_DST_Y_X, (dsty << 16) | dstx);
   3272       1.1   gdamore 	PUT32(sc, RADEON_DST_WIDTH_HEIGHT, (width << 16) | (height));
   3273       1.1   gdamore }
   3274       1.1   gdamore 
   3275       1.2  macallan static void
   3276       1.1   gdamore radeonfb_engine_idle(struct radeonfb_softc *sc)
   3277       1.1   gdamore {
   3278       1.1   gdamore 
   3279       1.1   gdamore 	radeonfb_wait_fifo(sc, 64);
   3280      1.48  macallan 	while ((GET32(sc, RADEON_RBBM_STATUS) &
   3281      1.48  macallan 			RADEON_RBBM_ACTIVE) != 0);
   3282      1.48  macallan 	radeonfb_engine_flush(sc);
   3283       1.1   gdamore }
   3284       1.1   gdamore 
   3285      1.55  macallan static inline void
   3286       1.1   gdamore radeonfb_wait_fifo(struct radeonfb_softc *sc, int n)
   3287       1.1   gdamore {
   3288       1.1   gdamore 	int	i;
   3289       1.1   gdamore 
   3290       1.1   gdamore 	for (i = RADEON_TIMEOUT; i; i--) {
   3291       1.1   gdamore 		if ((GET32(sc, RADEON_RBBM_STATUS) &
   3292       1.1   gdamore 			RADEON_RBBM_FIFOCNT_MASK) >= n)
   3293       1.1   gdamore 			return;
   3294       1.1   gdamore 	}
   3295       1.1   gdamore #ifdef	DIAGNOSTIC
   3296       1.1   gdamore 	if (!i)
   3297       1.1   gdamore 		printf("%s: timed out waiting for fifo (%x)\n",
   3298       1.1   gdamore 		    XNAME(sc), GET32(sc, RADEON_RBBM_STATUS));
   3299       1.1   gdamore #endif
   3300       1.1   gdamore }
   3301       1.1   gdamore 
   3302       1.2  macallan static void
   3303       1.1   gdamore radeonfb_engine_flush(struct radeonfb_softc *sc)
   3304       1.1   gdamore {
   3305      1.48  macallan 	int	i = 0;
   3306      1.48  macallan 
   3307      1.48  macallan 	if (IS_R300(sc)) {
   3308      1.48  macallan 		SET32(sc, R300_DSTCACHE_CTLSTAT, R300_RB2D_DC_FLUSH_ALL);
   3309      1.48  macallan 		while (GET32(sc, R300_DSTCACHE_CTLSTAT) & R300_RB2D_DC_BUSY) {
   3310      1.48  macallan 			i++;
   3311      1.48  macallan 		}
   3312      1.48  macallan 	} else {
   3313      1.48  macallan 		SET32(sc, RADEON_RB2D_DSTCACHE_CTLSTAT,
   3314      1.48  macallan 		    RADEON_RB2D_DC_FLUSH_ALL);
   3315      1.48  macallan 		while (GET32(sc, RADEON_RB2D_DSTCACHE_CTLSTAT) &
   3316      1.48  macallan 			RADEON_RB2D_DC_BUSY) {
   3317      1.48  macallan 			i++;
   3318      1.48  macallan 		}
   3319       1.1   gdamore 	}
   3320       1.1   gdamore #ifdef DIAGNOSTIC
   3321      1.48  macallan 	if (i > RADEON_TIMEOUT)
   3322       1.1   gdamore 		printf("%s: engine flush timed out!\n", XNAME(sc));
   3323       1.1   gdamore #endif
   3324       1.1   gdamore }
   3325       1.1   gdamore 
   3326       1.2  macallan static inline void
   3327       1.2  macallan radeonfb_unclip(struct radeonfb_softc *sc)
   3328       1.2  macallan {
   3329       1.2  macallan 
   3330       1.2  macallan 	radeonfb_wait_fifo(sc, 2);
   3331       1.4  macallan 	PUT32(sc, RADEON_SC_TOP_LEFT, 0);
   3332       1.5  macallan 	PUT32(sc, RADEON_SC_BOTTOM_RIGHT, 0x1fff1fff);
   3333       1.2  macallan }
   3334       1.2  macallan 
   3335       1.2  macallan static void
   3336       1.1   gdamore radeonfb_engine_init(struct radeonfb_display *dp)
   3337       1.1   gdamore {
   3338       1.1   gdamore 	struct radeonfb_softc	*sc = dp->rd_softc;
   3339       1.1   gdamore 	uint32_t		pitch;
   3340       1.1   gdamore 
   3341       1.1   gdamore 	/* no 3D */
   3342       1.1   gdamore 	PUT32(sc, RADEON_RB3D_CNTL, 0);
   3343       1.1   gdamore 
   3344       1.1   gdamore 	radeonfb_engine_reset(sc);
   3345       1.2  macallan 	pitch = ((dp->rd_virtx * (dp->rd_bpp / 8) + 0x3f)) >> 6;
   3346       1.1   gdamore 
   3347       1.1   gdamore 	radeonfb_wait_fifo(sc, 1);
   3348       1.1   gdamore 	if (!IS_R300(sc))
   3349       1.1   gdamore 		PUT32(sc, RADEON_RB2D_DSTCACHE_MODE, 0);
   3350       1.1   gdamore 
   3351       1.1   gdamore 	radeonfb_wait_fifo(sc, 3);
   3352       1.1   gdamore 	PUT32(sc, RADEON_DEFAULT_PITCH_OFFSET,
   3353       1.1   gdamore 	    (pitch << 22) | (sc->sc_aperbase >> 10));
   3354       1.1   gdamore 
   3355       1.1   gdamore 
   3356       1.1   gdamore 	PUT32(sc, RADEON_DST_PITCH_OFFSET,
   3357       1.1   gdamore 	    (pitch << 22) | (sc->sc_aperbase >> 10));
   3358       1.1   gdamore 	PUT32(sc, RADEON_SRC_PITCH_OFFSET,
   3359       1.1   gdamore 	    (pitch << 22) | (sc->sc_aperbase >> 10));
   3360       1.1   gdamore 
   3361  1.76.4.1     rmind 	(void)GET32(sc, RADEON_DP_DATATYPE);
   3362       1.1   gdamore 
   3363       1.1   gdamore 	/* default scissors -- no clipping */
   3364       1.1   gdamore 	radeonfb_wait_fifo(sc, 1);
   3365       1.1   gdamore 	PUT32(sc, RADEON_DEFAULT_SC_BOTTOM_RIGHT,
   3366       1.1   gdamore 	    RADEON_DEFAULT_SC_RIGHT_MAX | RADEON_DEFAULT_SC_BOTTOM_MAX);
   3367       1.1   gdamore 
   3368       1.1   gdamore 	radeonfb_wait_fifo(sc, 1);
   3369       1.1   gdamore 	PUT32(sc, RADEON_DP_GUI_MASTER_CNTL,
   3370       1.1   gdamore 	    (dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT) |
   3371       1.1   gdamore 	    RADEON_GMC_CLR_CMP_CNTL_DIS |
   3372       1.1   gdamore 	    RADEON_GMC_BRUSH_SOLID_COLOR |
   3373       1.1   gdamore 	    RADEON_GMC_SRC_DATATYPE_COLOR);
   3374       1.1   gdamore 
   3375      1.48  macallan 	radeonfb_wait_fifo(sc, 10);
   3376       1.1   gdamore 	PUT32(sc, RADEON_DST_LINE_START, 0);
   3377       1.1   gdamore 	PUT32(sc, RADEON_DST_LINE_END, 0);
   3378       1.1   gdamore 	PUT32(sc, RADEON_DP_BRUSH_FRGD_CLR, 0xffffffff);
   3379       1.1   gdamore 	PUT32(sc, RADEON_DP_BRUSH_BKGD_CLR, 0);
   3380       1.1   gdamore 	PUT32(sc, RADEON_DP_SRC_FRGD_CLR, 0xffffffff);
   3381       1.1   gdamore 	PUT32(sc, RADEON_DP_SRC_BKGD_CLR, 0);
   3382       1.1   gdamore 	PUT32(sc, RADEON_DP_WRITE_MASK, 0xffffffff);
   3383      1.48  macallan 	PUT32(sc, RADEON_SC_TOP_LEFT, 0);
   3384      1.48  macallan 	PUT32(sc, RADEON_SC_BOTTOM_RIGHT, 0x1fff1fff);
   3385      1.48  macallan 	PUT32(sc, RADEON_AUX_SC_CNTL, 0);
   3386       1.1   gdamore 	radeonfb_engine_idle(sc);
   3387       1.1   gdamore }
   3388       1.1   gdamore 
   3389       1.2  macallan static void
   3390       1.1   gdamore radeonfb_engine_reset(struct radeonfb_softc *sc)
   3391       1.1   gdamore {
   3392       1.1   gdamore 	uint32_t	hpc, rbbm, mclkcntl, clkindex;
   3393       1.1   gdamore 
   3394       1.1   gdamore 	radeonfb_engine_flush(sc);
   3395       1.1   gdamore 
   3396       1.1   gdamore 	clkindex = GET32(sc, RADEON_CLOCK_CNTL_INDEX);
   3397       1.1   gdamore 	if (HAS_R300CG(sc))
   3398       1.1   gdamore 		radeonfb_r300cg_workaround(sc);
   3399       1.1   gdamore 	mclkcntl = GETPLL(sc, RADEON_MCLK_CNTL);
   3400       1.1   gdamore 
   3401       1.1   gdamore 	/*
   3402       1.1   gdamore 	 * According to comments in XFree code, resetting the HDP via
   3403       1.1   gdamore 	 * the RBBM_SOFT_RESET can cause bad behavior on some systems.
   3404       1.1   gdamore 	 * So we use HOST_PATH_CNTL instead.
   3405       1.1   gdamore 	 */
   3406       1.1   gdamore 
   3407       1.1   gdamore 	hpc = GET32(sc, RADEON_HOST_PATH_CNTL);
   3408       1.1   gdamore 	rbbm = GET32(sc, RADEON_RBBM_SOFT_RESET);
   3409       1.1   gdamore 	if (IS_R300(sc)) {
   3410       1.1   gdamore 		PUT32(sc, RADEON_RBBM_SOFT_RESET, rbbm |
   3411       1.1   gdamore 		    RADEON_SOFT_RESET_CP |
   3412       1.1   gdamore 		    RADEON_SOFT_RESET_HI |
   3413       1.1   gdamore 		    RADEON_SOFT_RESET_E2);
   3414       1.1   gdamore 		GET32(sc, RADEON_RBBM_SOFT_RESET);
   3415       1.1   gdamore 		PUT32(sc, RADEON_RBBM_SOFT_RESET, 0);
   3416       1.1   gdamore 		/*
   3417       1.1   gdamore 		 * XXX: this bit is not defined in any ATI docs I have,
   3418       1.1   gdamore 		 * nor in the XFree code, but XFree does it.  Why?
   3419       1.1   gdamore 		 */
   3420       1.1   gdamore 		SET32(sc, RADEON_RB2D_DSTCACHE_MODE, (1<<17));
   3421       1.1   gdamore 	} else {
   3422       1.1   gdamore 		PUT32(sc, RADEON_RBBM_SOFT_RESET, rbbm |
   3423       1.1   gdamore 		    RADEON_SOFT_RESET_CP |
   3424       1.1   gdamore 		    RADEON_SOFT_RESET_SE |
   3425       1.1   gdamore 		    RADEON_SOFT_RESET_RE |
   3426       1.1   gdamore 		    RADEON_SOFT_RESET_PP |
   3427       1.1   gdamore 		    RADEON_SOFT_RESET_E2 |
   3428       1.1   gdamore 		    RADEON_SOFT_RESET_RB);
   3429       1.1   gdamore 		GET32(sc, RADEON_RBBM_SOFT_RESET);
   3430       1.1   gdamore 		PUT32(sc, RADEON_RBBM_SOFT_RESET, rbbm &
   3431       1.1   gdamore 		    ~(RADEON_SOFT_RESET_CP |
   3432       1.1   gdamore 			RADEON_SOFT_RESET_SE |
   3433       1.1   gdamore 			RADEON_SOFT_RESET_RE |
   3434       1.1   gdamore 			RADEON_SOFT_RESET_PP |
   3435       1.1   gdamore 			RADEON_SOFT_RESET_E2 |
   3436       1.1   gdamore 			RADEON_SOFT_RESET_RB));
   3437       1.1   gdamore 		GET32(sc, RADEON_RBBM_SOFT_RESET);
   3438       1.1   gdamore 	}
   3439       1.1   gdamore 
   3440       1.1   gdamore 	PUT32(sc, RADEON_HOST_PATH_CNTL, hpc | RADEON_HDP_SOFT_RESET);
   3441       1.1   gdamore 	GET32(sc, RADEON_HOST_PATH_CNTL);
   3442       1.1   gdamore 	PUT32(sc, RADEON_HOST_PATH_CNTL, hpc);
   3443       1.1   gdamore 
   3444       1.1   gdamore 	if (IS_R300(sc))
   3445       1.1   gdamore 		PUT32(sc, RADEON_RBBM_SOFT_RESET, rbbm);
   3446       1.1   gdamore 
   3447       1.1   gdamore 	PUT32(sc, RADEON_CLOCK_CNTL_INDEX, clkindex);
   3448      1.69  macallan 	PRINTREG(RADEON_CLOCK_CNTL_INDEX);
   3449       1.1   gdamore 	PUTPLL(sc, RADEON_MCLK_CNTL, mclkcntl);
   3450       1.1   gdamore 
   3451       1.1   gdamore 	if (HAS_R300CG(sc))
   3452       1.1   gdamore 		radeonfb_r300cg_workaround(sc);
   3453       1.1   gdamore }
   3454       1.1   gdamore 
   3455       1.2  macallan static int
   3456       1.1   gdamore radeonfb_set_curpos(struct radeonfb_display *dp, struct wsdisplay_curpos *pos)
   3457       1.1   gdamore {
   3458       1.1   gdamore 	int		x, y;
   3459       1.1   gdamore 
   3460       1.1   gdamore 	x = pos->x;
   3461       1.1   gdamore 	y = pos->y;
   3462       1.1   gdamore 
   3463       1.1   gdamore 	/*
   3464       1.1   gdamore 	 * This doesn't let a cursor move off the screen.  I'm not
   3465       1.1   gdamore 	 * sure if this will have negative effects for e.g. Xinerama.
   3466       1.1   gdamore 	 * I'd guess Xinerama handles it by changing the cursor shape,
   3467       1.1   gdamore 	 * but that needs verification.
   3468       1.1   gdamore 	 */
   3469       1.1   gdamore 	if (x >= dp->rd_virtx)
   3470       1.1   gdamore 		x = dp->rd_virtx - 1;
   3471       1.1   gdamore 	if (x < 0)
   3472       1.1   gdamore 		x = 0;
   3473       1.1   gdamore 	if (y >= dp->rd_virty)
   3474       1.1   gdamore 		y = dp->rd_virty - 1;
   3475       1.1   gdamore 	if (y < 0)
   3476       1.1   gdamore 		y = 0;
   3477       1.1   gdamore 
   3478       1.1   gdamore 	dp->rd_cursor.rc_pos.x = x;
   3479       1.1   gdamore 	dp->rd_cursor.rc_pos.y = y;
   3480       1.1   gdamore 
   3481       1.1   gdamore 	radeonfb_cursor_position(dp);
   3482       1.1   gdamore 	return 0;
   3483       1.1   gdamore }
   3484       1.1   gdamore 
   3485       1.2  macallan static int
   3486       1.1   gdamore radeonfb_set_cursor(struct radeonfb_display *dp, struct wsdisplay_cursor *wc)
   3487       1.1   gdamore {
   3488       1.1   gdamore 	unsigned	flags;
   3489       1.1   gdamore 
   3490       1.1   gdamore 	uint8_t		r[2], g[2], b[2];
   3491       1.1   gdamore 	unsigned	index, count;
   3492       1.1   gdamore 	int		i, err;
   3493       1.1   gdamore 	int		pitch, size;
   3494       1.1   gdamore 	struct radeonfb_cursor	nc;
   3495       1.1   gdamore 
   3496       1.1   gdamore 	flags = wc->which;
   3497       1.1   gdamore 
   3498       1.1   gdamore 	/* copy old values */
   3499       1.1   gdamore 	nc = dp->rd_cursor;
   3500       1.1   gdamore 
   3501       1.1   gdamore 	if (flags & WSDISPLAY_CURSOR_DOCMAP) {
   3502       1.1   gdamore 		index = wc->cmap.index;
   3503       1.1   gdamore 		count = wc->cmap.count;
   3504      1.11        ad 
   3505       1.1   gdamore 		if (index >= 2 || (index + count) > 2)
   3506       1.1   gdamore 			return EINVAL;
   3507       1.1   gdamore 
   3508       1.1   gdamore 		err = copyin(wc->cmap.red, &r[index], count);
   3509       1.1   gdamore 		if (err)
   3510       1.1   gdamore 			return err;
   3511       1.1   gdamore 		err = copyin(wc->cmap.green, &g[index], count);
   3512       1.1   gdamore 		if (err)
   3513       1.1   gdamore 			return err;
   3514       1.1   gdamore 		err = copyin(wc->cmap.blue, &b[index], count);
   3515       1.1   gdamore 		if (err)
   3516       1.1   gdamore 			return err;
   3517       1.1   gdamore 
   3518       1.1   gdamore 		for (i = index; i < index + count; i++) {
   3519       1.1   gdamore 			nc.rc_cmap[i] =
   3520       1.1   gdamore 			    (r[i] << 16) + (g[i] << 8) + (b[i] << 0);
   3521       1.1   gdamore 		}
   3522       1.1   gdamore 	}
   3523       1.1   gdamore 
   3524       1.1   gdamore 	if (flags & WSDISPLAY_CURSOR_DOSHAPE) {
   3525       1.1   gdamore 		if ((wc->size.x > RADEON_CURSORMAXX) ||
   3526       1.1   gdamore 		    (wc->size.y > RADEON_CURSORMAXY))
   3527       1.1   gdamore 			return EINVAL;
   3528       1.1   gdamore 
   3529       1.1   gdamore 		/* figure bytes per line */
   3530       1.1   gdamore 		pitch = (wc->size.x + 7) / 8;
   3531       1.1   gdamore 		size = pitch * wc->size.y;
   3532       1.1   gdamore 
   3533       1.1   gdamore 		/* clear the old cursor and mask */
   3534       1.1   gdamore 		memset(nc.rc_image, 0, 512);
   3535       1.1   gdamore 		memset(nc.rc_mask, 0, 512);
   3536       1.1   gdamore 
   3537       1.1   gdamore 		nc.rc_size = wc->size;
   3538       1.1   gdamore 
   3539       1.1   gdamore 		if ((err = copyin(wc->image, nc.rc_image, size)) != 0)
   3540       1.1   gdamore 			return err;
   3541       1.1   gdamore 
   3542       1.1   gdamore 		if ((err = copyin(wc->mask, nc.rc_mask, size)) != 0)
   3543       1.1   gdamore 			return err;
   3544       1.1   gdamore 	}
   3545       1.1   gdamore 
   3546       1.1   gdamore 	if (flags & WSDISPLAY_CURSOR_DOHOT) {
   3547       1.1   gdamore 		nc.rc_hot = wc->hot;
   3548       1.1   gdamore 		if (nc.rc_hot.x >= nc.rc_size.x)
   3549       1.1   gdamore 			nc.rc_hot.x = nc.rc_size.x - 1;
   3550       1.1   gdamore 		if (nc.rc_hot.y >= nc.rc_size.y)
   3551       1.1   gdamore 			nc.rc_hot.y = nc.rc_size.y - 1;
   3552       1.1   gdamore 	}
   3553       1.1   gdamore 
   3554       1.1   gdamore 	if (flags & WSDISPLAY_CURSOR_DOPOS) {
   3555       1.1   gdamore 		nc.rc_pos = wc->pos;
   3556       1.1   gdamore 		if (nc.rc_pos.x >= dp->rd_virtx)
   3557       1.1   gdamore 			nc.rc_pos.x = dp->rd_virtx - 1;
   3558       1.7  christos #if 0
   3559       1.1   gdamore 		if (nc.rc_pos.x < 0)
   3560       1.1   gdamore 			nc.rc_pos.x = 0;
   3561       1.7  christos #endif
   3562       1.1   gdamore 		if (nc.rc_pos.y >= dp->rd_virty)
   3563       1.1   gdamore 			nc.rc_pos.y = dp->rd_virty - 1;
   3564       1.7  christos #if 0
   3565       1.1   gdamore 		if (nc.rc_pos.y < 0)
   3566       1.1   gdamore 			nc.rc_pos.y = 0;
   3567       1.7  christos #endif
   3568       1.1   gdamore 	}
   3569       1.1   gdamore 	if (flags & WSDISPLAY_CURSOR_DOCUR) {
   3570       1.1   gdamore 		nc.rc_visible = wc->enable;
   3571       1.1   gdamore 	}
   3572       1.1   gdamore 
   3573       1.1   gdamore 	dp->rd_cursor = nc;
   3574       1.1   gdamore 	radeonfb_cursor_update(dp, wc->which);
   3575       1.1   gdamore 
   3576       1.1   gdamore 	return 0;
   3577       1.1   gdamore }
   3578       1.1   gdamore 
   3579  1.76.4.1     rmind static uint8_t
   3580  1.76.4.1     rmind radeonfb_backwards(uint8_t d)
   3581  1.76.4.1     rmind {
   3582  1.76.4.1     rmind 	uint8_t l;
   3583  1.76.4.1     rmind 
   3584  1.76.4.1     rmind 	l = d << 7;
   3585  1.76.4.1     rmind 	l |= ((d & 0x02) << 5);
   3586  1.76.4.1     rmind 	l |= ((d & 0x04) << 3);
   3587  1.76.4.1     rmind 	l |= ((d & 0x08) << 1);
   3588  1.76.4.1     rmind 	l |= ((d & 0x10) >> 1);
   3589  1.76.4.1     rmind 	l |= ((d & 0x20) >> 3);
   3590  1.76.4.1     rmind 	l |= ((d & 0x40) >> 5);
   3591  1.76.4.1     rmind 	l |= ((d & 0x80) >> 7);
   3592  1.76.4.1     rmind 	return l;
   3593  1.76.4.1     rmind }
   3594  1.76.4.1     rmind 
   3595       1.1   gdamore /*
   3596       1.1   gdamore  * Change the cursor shape.  Call this with the cursor locked to avoid
   3597       1.1   gdamore  * flickering/tearing.
   3598       1.1   gdamore  */
   3599       1.2  macallan static void
   3600       1.1   gdamore radeonfb_cursor_shape(struct radeonfb_display *dp)
   3601       1.1   gdamore {
   3602       1.1   gdamore 	uint8_t	and[512], xor[512];
   3603  1.76.4.1     rmind 	int	i, j, src, dst /* , pitch */;
   3604       1.1   gdamore 	const uint8_t	*msk = dp->rd_cursor.rc_mask;
   3605       1.1   gdamore 	const uint8_t	*img = dp->rd_cursor.rc_image;
   3606       1.1   gdamore 
   3607       1.1   gdamore 	/*
   3608       1.1   gdamore 	 * Radeon cursor data interleaves one line of AND data followed
   3609       1.1   gdamore 	 * by a line of XOR data.  (Each line corresponds to a whole hardware
   3610       1.1   gdamore 	 * pitch - i.e. 64 pixels or 8 bytes.)
   3611       1.1   gdamore 	 *
   3612       1.1   gdamore 	 * The cursor is displayed using the following table:
   3613       1.1   gdamore 	 *
   3614       1.1   gdamore 	 * AND	XOR	Result
   3615       1.1   gdamore 	 * ----------------------
   3616       1.1   gdamore 	 *  0    0	Cursor color 0
   3617       1.1   gdamore 	 *  0	 1	Cursor color 1
   3618       1.1   gdamore 	 *  1	 0	Transparent
   3619       1.1   gdamore 	 *  1	 1	Complement of background
   3620       1.1   gdamore 	 *
   3621       1.1   gdamore 	 * Our masks are therefore different from what we were passed.
   3622       1.1   gdamore 	 * Passed in, I'm assuming the data represents either color 0 or 1,
   3623       1.1   gdamore 	 * and a mask, so the passed in table looks like:
   3624       1.1   gdamore 	 *
   3625       1.1   gdamore 	 * IMG	Mask	Result
   3626       1.1   gdamore 	 * -----------------------
   3627       1.1   gdamore 	 *  0	 0	Transparent
   3628       1.1   gdamore 	 *  0	 1	Cursor color 0
   3629       1.1   gdamore 	 *  1	 0	Transparent
   3630       1.1   gdamore 	 *  1	 1	Cursor color 1
   3631       1.1   gdamore 	 *
   3632       1.1   gdamore 	 * IF mask bit == 1, AND = 0, XOR = color.
   3633       1.1   gdamore 	 * IF mask bit == 0, AND = 1, XOR = 0.
   3634       1.1   gdamore 	 *
   3635       1.1   gdamore 	 * hence:	AND = ~(mask);	XOR = color & ~(mask);
   3636       1.1   gdamore 	 */
   3637       1.1   gdamore 
   3638  1.76.4.1     rmind 	/* pitch = ((dp->rd_cursor.rc_size.x + 7) / 8); */
   3639       1.1   gdamore 
   3640       1.1   gdamore 	/* start by assuming all bits are transparent */
   3641       1.1   gdamore 	memset(and, 0xff, 512);
   3642       1.1   gdamore 	memset(xor, 0x00, 512);
   3643       1.1   gdamore 
   3644       1.1   gdamore 	src = 0;
   3645       1.1   gdamore 	dst = 0;
   3646       1.1   gdamore 	for (i = 0; i < 64; i++) {
   3647       1.1   gdamore 		for (j = 0; j < 64; j += 8) {
   3648       1.1   gdamore 			if ((i < dp->rd_cursor.rc_size.y) &&
   3649       1.1   gdamore 			    (j < dp->rd_cursor.rc_size.x)) {
   3650       1.1   gdamore 
   3651       1.1   gdamore 				/* take care to leave odd bits alone */
   3652       1.1   gdamore 				and[dst] &= ~(msk[src]);
   3653       1.1   gdamore 				xor[dst] = img[src] & msk[src];
   3654       1.1   gdamore 				src++;
   3655       1.1   gdamore 			}
   3656       1.1   gdamore 			dst++;
   3657       1.1   gdamore 		}
   3658       1.1   gdamore 	}
   3659       1.1   gdamore 
   3660  1.76.4.1     rmind 	for (i = 0; i < 512; i++) {
   3661  1.76.4.1     rmind 		and[i] = radeonfb_backwards(and[i]);
   3662  1.76.4.1     rmind 		xor[i] = radeonfb_backwards(xor[i]);
   3663  1.76.4.1     rmind 	}
   3664  1.76.4.1     rmind 
   3665       1.1   gdamore 	/* copy the image into place */
   3666       1.1   gdamore 	for (i = 0; i < 64; i++) {
   3667       1.1   gdamore 		memcpy((uint8_t *)dp->rd_curptr + (i * 16),
   3668       1.1   gdamore 		    &and[i * 8], 8);
   3669       1.1   gdamore 		memcpy((uint8_t *)dp->rd_curptr + (i * 16) + 8,
   3670       1.1   gdamore 		    &xor[i * 8], 8);
   3671       1.1   gdamore 	}
   3672       1.1   gdamore }
   3673       1.1   gdamore 
   3674       1.2  macallan static void
   3675       1.1   gdamore radeonfb_cursor_position(struct radeonfb_display *dp)
   3676       1.1   gdamore {
   3677       1.1   gdamore 	struct radeonfb_softc	*sc = dp->rd_softc;
   3678       1.1   gdamore 	uint32_t		offset, hvoff, hvpos;	/* registers */
   3679       1.1   gdamore 	uint32_t		coff;			/* cursor offset */
   3680       1.1   gdamore 	int			i, x, y, xoff, yoff, crtcoff;
   3681       1.1   gdamore 
   3682       1.1   gdamore 	/*
   3683       1.1   gdamore 	 * XXX: this also needs to handle pan/scan
   3684       1.1   gdamore 	 */
   3685       1.1   gdamore 	for (i = 0; i < dp->rd_ncrtcs; i++) {
   3686       1.1   gdamore 
   3687       1.1   gdamore 		struct radeonfb_crtc	*rcp = &dp->rd_crtcs[i];
   3688       1.1   gdamore 
   3689       1.1   gdamore 		if (rcp->rc_number) {
   3690       1.1   gdamore 			offset = RADEON_CUR2_OFFSET;
   3691       1.1   gdamore 			hvoff = RADEON_CUR2_HORZ_VERT_OFF;
   3692       1.1   gdamore 			hvpos = RADEON_CUR2_HORZ_VERT_POSN;
   3693       1.1   gdamore 			crtcoff = RADEON_CRTC2_OFFSET;
   3694       1.1   gdamore 		} else {
   3695       1.1   gdamore 			offset = RADEON_CUR_OFFSET;
   3696       1.1   gdamore 			hvoff = RADEON_CUR_HORZ_VERT_OFF;
   3697       1.1   gdamore 			hvpos = RADEON_CUR_HORZ_VERT_POSN;
   3698       1.1   gdamore 			crtcoff = RADEON_CRTC_OFFSET;
   3699       1.1   gdamore 		}
   3700       1.1   gdamore 
   3701       1.1   gdamore 		x = dp->rd_cursor.rc_pos.x;
   3702       1.1   gdamore 		y = dp->rd_cursor.rc_pos.y;
   3703       1.1   gdamore 
   3704       1.1   gdamore 		while (y < rcp->rc_yoffset) {
   3705       1.1   gdamore 			rcp->rc_yoffset -= RADEON_PANINCREMENT;
   3706       1.1   gdamore 		}
   3707       1.1   gdamore 		while (y >= (rcp->rc_yoffset + rcp->rc_videomode.vdisplay)) {
   3708       1.1   gdamore 			rcp->rc_yoffset += RADEON_PANINCREMENT;
   3709       1.1   gdamore 		}
   3710       1.1   gdamore 		while (x < rcp->rc_xoffset) {
   3711       1.1   gdamore 			rcp->rc_xoffset -= RADEON_PANINCREMENT;
   3712       1.1   gdamore 		}
   3713       1.1   gdamore 		while (x >= (rcp->rc_xoffset + rcp->rc_videomode.hdisplay)) {
   3714       1.1   gdamore 			rcp->rc_xoffset += RADEON_PANINCREMENT;
   3715       1.1   gdamore 		}
   3716       1.1   gdamore 
   3717       1.1   gdamore 		/* adjust for the cursor's hotspot */
   3718       1.1   gdamore 		x -= dp->rd_cursor.rc_hot.x;
   3719       1.1   gdamore 		y -= dp->rd_cursor.rc_hot.y;
   3720       1.1   gdamore 		xoff = yoff = 0;
   3721       1.1   gdamore 
   3722       1.1   gdamore 		if (x >= dp->rd_virtx)
   3723       1.1   gdamore 			x = dp->rd_virtx - 1;
   3724       1.1   gdamore 		if (y >= dp->rd_virty)
   3725       1.1   gdamore 			y = dp->rd_virty - 1;
   3726       1.1   gdamore 
   3727       1.1   gdamore 		/* now adjust cursor so it is relative to viewport */
   3728       1.1   gdamore 		x -= rcp->rc_xoffset;
   3729       1.1   gdamore 		y -= rcp->rc_yoffset;
   3730       1.1   gdamore 
   3731       1.1   gdamore 		/*
   3732       1.1   gdamore 		 * no need to check for fall off, because we should
   3733       1.1   gdamore 		 * never move off the screen entirely!
   3734       1.1   gdamore 		 */
   3735       1.1   gdamore 		coff = 0;
   3736       1.1   gdamore 		if (x < 0) {
   3737       1.1   gdamore 			xoff = -x;
   3738       1.1   gdamore 			x = 0;
   3739       1.1   gdamore 		}
   3740       1.1   gdamore 		if (y < 0) {
   3741       1.1   gdamore 			yoff = -y;
   3742       1.1   gdamore 			y = 0;
   3743       1.1   gdamore 			coff = (yoff * 2) * 8;
   3744       1.1   gdamore 		}
   3745       1.1   gdamore 
   3746       1.1   gdamore 		/* pan the display */
   3747       1.1   gdamore 		PUT32(sc, crtcoff, (rcp->rc_yoffset * dp->rd_stride) +
   3748       1.1   gdamore 		    rcp->rc_xoffset);
   3749       1.1   gdamore 
   3750       1.1   gdamore 		PUT32(sc, offset, (dp->rd_curoff + coff) | RADEON_CUR_LOCK);
   3751       1.1   gdamore 		PUT32(sc, hvoff, (xoff << 16) | (yoff) | RADEON_CUR_LOCK);
   3752       1.1   gdamore 		/* NB: this unlocks the cursor */
   3753       1.1   gdamore 		PUT32(sc, hvpos, (x << 16) | y);
   3754       1.1   gdamore 	}
   3755       1.1   gdamore }
   3756       1.1   gdamore 
   3757       1.2  macallan static void
   3758       1.1   gdamore radeonfb_cursor_visible(struct radeonfb_display *dp)
   3759       1.1   gdamore {
   3760       1.1   gdamore 	int		i;
   3761       1.1   gdamore 	uint32_t	gencntl, bit;
   3762       1.1   gdamore 
   3763       1.1   gdamore 	for (i = 0; i < dp->rd_ncrtcs; i++) {
   3764       1.1   gdamore 		if (dp->rd_crtcs[i].rc_number) {
   3765       1.1   gdamore 			gencntl = RADEON_CRTC2_GEN_CNTL;
   3766       1.1   gdamore 			bit = RADEON_CRTC2_CUR_EN;
   3767       1.1   gdamore 		} else {
   3768       1.1   gdamore 			gencntl = RADEON_CRTC_GEN_CNTL;
   3769       1.1   gdamore 			bit = RADEON_CRTC_CUR_EN;
   3770       1.1   gdamore 		}
   3771      1.11        ad 
   3772       1.1   gdamore 		if (dp->rd_cursor.rc_visible)
   3773       1.1   gdamore 			SET32(dp->rd_softc, gencntl, bit);
   3774       1.1   gdamore 		else
   3775       1.1   gdamore 			CLR32(dp->rd_softc, gencntl, bit);
   3776       1.1   gdamore 	}
   3777       1.1   gdamore }
   3778       1.1   gdamore 
   3779       1.2  macallan static void
   3780       1.1   gdamore radeonfb_cursor_cmap(struct radeonfb_display *dp)
   3781       1.1   gdamore {
   3782       1.1   gdamore 	int		i;
   3783       1.1   gdamore 	uint32_t	c0reg, c1reg;
   3784       1.1   gdamore 	struct radeonfb_softc	*sc = dp->rd_softc;
   3785       1.1   gdamore 
   3786       1.1   gdamore 	for (i = 0; i < dp->rd_ncrtcs; i++) {
   3787       1.1   gdamore 		if (dp->rd_crtcs[i].rc_number) {
   3788       1.1   gdamore 			c0reg = RADEON_CUR2_CLR0;
   3789       1.1   gdamore 			c1reg = RADEON_CUR2_CLR1;
   3790       1.1   gdamore 		} else {
   3791       1.1   gdamore 			c0reg = RADEON_CUR_CLR0;
   3792       1.1   gdamore 			c1reg = RADEON_CUR_CLR1;
   3793       1.1   gdamore 		}
   3794       1.1   gdamore 
   3795       1.1   gdamore 		PUT32(sc, c0reg, dp->rd_cursor.rc_cmap[0]);
   3796       1.1   gdamore 		PUT32(sc, c1reg, dp->rd_cursor.rc_cmap[1]);
   3797       1.1   gdamore 	}
   3798       1.1   gdamore }
   3799       1.1   gdamore 
   3800       1.2  macallan static void
   3801       1.1   gdamore radeonfb_cursor_update(struct radeonfb_display *dp, unsigned which)
   3802       1.1   gdamore {
   3803       1.1   gdamore 	struct radeonfb_softc	*sc;
   3804       1.1   gdamore 	int		i;
   3805       1.1   gdamore 
   3806       1.1   gdamore 	sc = dp->rd_softc;
   3807       1.1   gdamore 	for (i = 0; i < dp->rd_ncrtcs; i++) {
   3808       1.1   gdamore 		if (dp->rd_crtcs[i].rc_number) {
   3809       1.1   gdamore 			SET32(sc, RADEON_CUR2_OFFSET, RADEON_CUR_LOCK);
   3810       1.1   gdamore 		} else {
   3811       1.1   gdamore 			SET32(sc, RADEON_CUR_OFFSET,RADEON_CUR_LOCK);
   3812       1.1   gdamore 		}
   3813       1.1   gdamore 	}
   3814       1.1   gdamore 
   3815       1.1   gdamore 	if (which & WSDISPLAY_CURSOR_DOCMAP)
   3816       1.1   gdamore 		radeonfb_cursor_cmap(dp);
   3817       1.1   gdamore 
   3818       1.1   gdamore 	if (which & WSDISPLAY_CURSOR_DOSHAPE)
   3819       1.1   gdamore 		radeonfb_cursor_shape(dp);
   3820       1.1   gdamore 
   3821       1.1   gdamore 	if (which & WSDISPLAY_CURSOR_DOCUR)
   3822       1.1   gdamore 		radeonfb_cursor_visible(dp);
   3823       1.1   gdamore 
   3824       1.1   gdamore 	/* this one is unconditional, because it updates other stuff */
   3825       1.1   gdamore 	radeonfb_cursor_position(dp);
   3826       1.1   gdamore }
   3827       1.1   gdamore 
   3828       1.1   gdamore static struct videomode *
   3829       1.1   gdamore radeonfb_best_refresh(struct videomode *m1, struct videomode *m2)
   3830       1.1   gdamore {
   3831       1.1   gdamore 	int	r1, r2;
   3832       1.1   gdamore 
   3833       1.1   gdamore 	/* otherwise pick the higher refresh rate */
   3834       1.1   gdamore 	r1 = DIVIDE(DIVIDE(m1->dot_clock, m1->htotal), m1->vtotal);
   3835       1.1   gdamore 	r2 = DIVIDE(DIVIDE(m2->dot_clock, m2->htotal), m2->vtotal);
   3836       1.1   gdamore 
   3837       1.1   gdamore 	return (r1 < r2 ? m2 : m1);
   3838       1.1   gdamore }
   3839       1.1   gdamore 
   3840       1.1   gdamore static const struct videomode *
   3841       1.9  macallan radeonfb_port_mode(struct radeonfb_softc *sc, struct radeonfb_port *rp,
   3842       1.9  macallan     int x, int y)
   3843       1.1   gdamore {
   3844       1.1   gdamore 	struct edid_info	*ep = &rp->rp_edid;
   3845       1.1   gdamore 	struct videomode	*vmp = NULL;
   3846       1.1   gdamore 	int			i;
   3847       1.1   gdamore 
   3848       1.1   gdamore 	if (!rp->rp_edid_valid) {
   3849       1.1   gdamore 		/* fallback to safe mode */
   3850       1.9  macallan 		return radeonfb_modelookup(sc->sc_defaultmode);
   3851       1.1   gdamore 	}
   3852      1.11        ad 
   3853       1.1   gdamore 	/* always choose the preferred mode first! */
   3854       1.1   gdamore 	if (ep->edid_preferred_mode) {
   3855       1.1   gdamore 
   3856       1.1   gdamore 		/* XXX: add auto-stretching support for native mode */
   3857       1.1   gdamore 
   3858       1.1   gdamore 		/* this may want panning to occur, btw */
   3859       1.1   gdamore 		if ((ep->edid_preferred_mode->hdisplay <= x) &&
   3860       1.1   gdamore 		    (ep->edid_preferred_mode->vdisplay <= y))
   3861       1.1   gdamore 			return ep->edid_preferred_mode;
   3862       1.1   gdamore 	}
   3863       1.1   gdamore 
   3864       1.1   gdamore 	for (i = 0; i < ep->edid_nmodes; i++) {
   3865       1.1   gdamore 		/*
   3866       1.1   gdamore 		 * We elect to pick a resolution that is too large for
   3867       1.1   gdamore 		 * the monitor than one that is too small.  This means
   3868       1.1   gdamore 		 * that we will prefer to pan rather than to try to
   3869       1.1   gdamore 		 * center a smaller display on a larger screen.  In
   3870       1.1   gdamore 		 * practice, this shouldn't matter because if a
   3871       1.1   gdamore 		 * monitor can support a larger resolution, it can
   3872       1.1   gdamore 		 * probably also support the smaller.  A specific
   3873       1.1   gdamore 		 * exception is fixed format panels, but hopefully
   3874       1.1   gdamore 		 * they are properly dealt with by the "autostretch"
   3875       1.1   gdamore 		 * logic above.
   3876       1.1   gdamore 		 */
   3877       1.1   gdamore 		if ((ep->edid_modes[i].hdisplay > x) ||
   3878       1.1   gdamore 		    (ep->edid_modes[i].vdisplay > y)) {
   3879       1.1   gdamore 			continue;
   3880       1.1   gdamore 		}
   3881       1.1   gdamore 
   3882       1.1   gdamore 		/*
   3883       1.1   gdamore 		 * at this point, the display mode is no larger than
   3884       1.1   gdamore 		 * what we've requested.
   3885       1.1   gdamore 		 */
   3886       1.1   gdamore 		if (vmp == NULL)
   3887       1.1   gdamore 			vmp = &ep->edid_modes[i];
   3888       1.1   gdamore 
   3889       1.1   gdamore 		/* eliminate smaller modes */
   3890       1.1   gdamore 		if ((vmp->hdisplay >= ep->edid_modes[i].hdisplay) ||
   3891       1.1   gdamore 		    (vmp->vdisplay >= ep->edid_modes[i].vdisplay))
   3892       1.1   gdamore 			continue;
   3893       1.1   gdamore 
   3894       1.1   gdamore 		if ((vmp->hdisplay < ep->edid_modes[i].hdisplay) ||
   3895       1.1   gdamore 		    (vmp->vdisplay < ep->edid_modes[i].vdisplay)) {
   3896       1.1   gdamore 			vmp = &ep->edid_modes[i];
   3897       1.1   gdamore 			continue;
   3898       1.1   gdamore 		}
   3899       1.1   gdamore 
   3900       1.1   gdamore 		KASSERT(vmp->hdisplay == ep->edid_modes[i].hdisplay);
   3901       1.1   gdamore 		KASSERT(vmp->vdisplay == ep->edid_modes[i].vdisplay);
   3902       1.1   gdamore 
   3903       1.1   gdamore 		vmp = radeonfb_best_refresh(vmp, &ep->edid_modes[i]);
   3904       1.1   gdamore 	}
   3905       1.1   gdamore 
   3906       1.9  macallan 	return (vmp ? vmp : radeonfb_modelookup(sc->sc_defaultmode));
   3907       1.1   gdamore }
   3908       1.1   gdamore 
   3909       1.1   gdamore static int
   3910       1.1   gdamore radeonfb_hasres(struct videomode *list, int nlist, int x, int y)
   3911       1.1   gdamore {
   3912       1.1   gdamore 	int	i;
   3913       1.1   gdamore 
   3914       1.1   gdamore 	for (i = 0; i < nlist; i++) {
   3915       1.1   gdamore 		if ((x == list[i].hdisplay) &&
   3916       1.1   gdamore 		    (y == list[i].vdisplay)) {
   3917       1.1   gdamore 			return 1;
   3918       1.1   gdamore 		}
   3919       1.1   gdamore 	}
   3920       1.1   gdamore 	return 0;
   3921       1.1   gdamore }
   3922       1.1   gdamore 
   3923       1.2  macallan static void
   3924       1.1   gdamore radeonfb_pickres(struct radeonfb_display *dp, uint16_t *x, uint16_t *y,
   3925       1.1   gdamore     int pan)
   3926       1.1   gdamore {
   3927       1.1   gdamore 	struct radeonfb_port	*rp;
   3928       1.1   gdamore 	struct edid_info	*ep;
   3929       1.1   gdamore 	int			i, j;
   3930       1.1   gdamore 
   3931       1.1   gdamore 	*x = 0;
   3932       1.1   gdamore 	*y = 0;
   3933       1.1   gdamore 
   3934       1.1   gdamore 	if (pan) {
   3935       1.1   gdamore 		for (i = 0; i < dp->rd_ncrtcs; i++) {
   3936       1.1   gdamore 			rp = dp->rd_crtcs[i].rc_port;
   3937       1.1   gdamore 			ep = &rp->rp_edid;
   3938       1.1   gdamore 			if (!rp->rp_edid_valid) {
   3939       1.1   gdamore 				/* monitor not present */
   3940       1.1   gdamore 				continue;
   3941       1.1   gdamore 			}
   3942       1.1   gdamore 
   3943       1.1   gdamore 			/*
   3944       1.1   gdamore 			 * For now we are ignoring "conflict" that
   3945       1.1   gdamore 			 * could occur when mixing some modes like
   3946       1.1   gdamore 			 * 1280x1024 and 1400x800.  It isn't clear
   3947       1.1   gdamore 			 * which is better, so the first one wins.
   3948       1.1   gdamore 			 */
   3949       1.1   gdamore 			for (j = 0; j < ep->edid_nmodes; j++) {
   3950       1.1   gdamore 				/*
   3951       1.1   gdamore 				 * ignore resolutions that are too big for
   3952       1.1   gdamore 				 * the radeon
   3953       1.1   gdamore 				 */
   3954       1.1   gdamore 				if (ep->edid_modes[j].hdisplay >
   3955       1.1   gdamore 				    dp->rd_softc->sc_maxx)
   3956       1.1   gdamore 					continue;
   3957       1.1   gdamore 				if (ep->edid_modes[j].vdisplay >
   3958       1.1   gdamore 				    dp->rd_softc->sc_maxy)
   3959       1.1   gdamore 					continue;
   3960       1.1   gdamore 
   3961       1.1   gdamore 				/*
   3962       1.1   gdamore 				 * pick largest resolution, the
   3963       1.1   gdamore 				 * smaller monitor will pan
   3964       1.1   gdamore 				 */
   3965       1.1   gdamore 				if ((ep->edid_modes[j].hdisplay >= *x) &&
   3966       1.1   gdamore 				    (ep->edid_modes[j].vdisplay >= *y)) {
   3967       1.1   gdamore 					*x = ep->edid_modes[j].hdisplay;
   3968       1.1   gdamore 					*y = ep->edid_modes[j].vdisplay;
   3969       1.1   gdamore 				}
   3970       1.1   gdamore 			}
   3971       1.1   gdamore 		}
   3972       1.1   gdamore 
   3973       1.1   gdamore 	} else {
   3974       1.1   gdamore 		struct videomode	modes[64];
   3975       1.1   gdamore 		int			nmodes = 0;
   3976       1.1   gdamore 		int			valid = 0;
   3977       1.1   gdamore 
   3978       1.1   gdamore 		for (i = 0; i < dp->rd_ncrtcs; i++) {
   3979       1.1   gdamore 			/*
   3980       1.1   gdamore 			 * pick the largest resolution in common.
   3981       1.1   gdamore 			 */
   3982       1.1   gdamore 			rp = dp->rd_crtcs[i].rc_port;
   3983       1.1   gdamore 			ep = &rp->rp_edid;
   3984       1.1   gdamore 
   3985       1.1   gdamore 			if (!rp->rp_edid_valid)
   3986       1.1   gdamore 				continue;
   3987       1.1   gdamore 
   3988       1.1   gdamore 			if (!valid) {
   3989      1.29  macallan 				/*
   3990      1.29  macallan 				 * Pick the preferred mode for this port
   3991      1.29  macallan 				 * if available.
   3992      1.29  macallan 				 */
   3993      1.29  macallan 				if (ep->edid_preferred_mode) {
   3994      1.29  macallan 					struct videomode *vmp =
   3995      1.29  macallan 						ep->edid_preferred_mode;
   3996      1.29  macallan 
   3997      1.29  macallan 					if ((vmp->hdisplay <=
   3998      1.29  macallan 					     dp->rd_softc->sc_maxx) &&
   3999      1.29  macallan 					    (vmp->vdisplay <=
   4000      1.29  macallan 					     dp->rd_softc->sc_maxy))
   4001      1.29  macallan 						modes[nmodes++] = *vmp;
   4002      1.29  macallan 				} else {
   4003      1.29  macallan 
   4004      1.29  macallan 					/* initialize starting list */
   4005      1.29  macallan 					for (j = 0; j < ep->edid_nmodes; j++) {
   4006      1.29  macallan 						/*
   4007      1.29  macallan 						 * ignore resolutions that are
   4008      1.29  macallan 						 * too big for the radeon
   4009      1.29  macallan 						 */
   4010      1.29  macallan 						if (ep->edid_modes[j].hdisplay >
   4011      1.29  macallan 						    dp->rd_softc->sc_maxx)
   4012      1.29  macallan 							continue;
   4013      1.29  macallan 						if (ep->edid_modes[j].vdisplay >
   4014      1.29  macallan 						    dp->rd_softc->sc_maxy)
   4015      1.29  macallan 							continue;
   4016      1.29  macallan 
   4017      1.29  macallan 						modes[nmodes] =
   4018      1.29  macallan 							ep->edid_modes[j];
   4019      1.29  macallan 						nmodes++;
   4020      1.29  macallan 					}
   4021       1.1   gdamore 				}
   4022       1.1   gdamore 				valid = 1;
   4023       1.1   gdamore 			} else {
   4024       1.1   gdamore 				/* merge into preexisting list */
   4025       1.1   gdamore 				for (j = 0; j < nmodes; j++) {
   4026       1.1   gdamore 					if (!radeonfb_hasres(ep->edid_modes,
   4027       1.1   gdamore 						ep->edid_nmodes,
   4028       1.1   gdamore 						modes[j].hdisplay,
   4029       1.1   gdamore 						modes[j].vdisplay)) {
   4030       1.1   gdamore 						modes[j] = modes[nmodes];
   4031       1.1   gdamore 						j--;
   4032       1.1   gdamore 						nmodes--;
   4033       1.1   gdamore 					}
   4034       1.1   gdamore 				}
   4035       1.1   gdamore 			}
   4036       1.1   gdamore 		}
   4037       1.1   gdamore 
   4038       1.1   gdamore 		/* now we have to pick from the merged list */
   4039       1.1   gdamore 		for (i = 0; i < nmodes; i++) {
   4040       1.1   gdamore 			if ((modes[i].hdisplay >= *x) &&
   4041       1.1   gdamore 			    (modes[i].vdisplay >= *y)) {
   4042       1.1   gdamore 				*x = modes[i].hdisplay;
   4043       1.1   gdamore 				*y = modes[i].vdisplay;
   4044       1.1   gdamore 			}
   4045       1.1   gdamore 		}
   4046       1.1   gdamore 	}
   4047       1.1   gdamore 
   4048       1.1   gdamore 	if ((*x == 0) || (*y == 0)) {
   4049       1.1   gdamore 		/* fallback to safe mode */
   4050       1.1   gdamore 		*x = 640;
   4051       1.1   gdamore 		*y = 480;
   4052       1.1   gdamore 	}
   4053       1.1   gdamore }
   4054       1.9  macallan 
   4055      1.17  macallan /*
   4056      1.17  macallan  * backlight levels are linear on:
   4057      1.17  macallan  * - RV200, RV250, RV280, RV350
   4058      1.17  macallan  * - but NOT on PowerBook4,3 6,3 6,5
   4059      1.17  macallan  * according to Linux' radeonfb
   4060      1.17  macallan  */
   4061       1.9  macallan 
   4062       1.9  macallan /* Get the current backlight level for the display.  */
   4063       1.9  macallan 
   4064      1.11        ad static int
   4065       1.9  macallan radeonfb_get_backlight(struct radeonfb_display *dp)
   4066       1.9  macallan {
   4067       1.9  macallan 	int s;
   4068       1.9  macallan 	uint32_t level;
   4069       1.9  macallan 
   4070       1.9  macallan 	s = spltty();
   4071       1.9  macallan 
   4072       1.9  macallan 	level = radeonfb_get32(dp->rd_softc, RADEON_LVDS_GEN_CNTL);
   4073       1.9  macallan 	level &= RADEON_LVDS_BL_MOD_LEV_MASK;
   4074       1.9  macallan 	level >>= RADEON_LVDS_BL_MOD_LEV_SHIFT;
   4075       1.9  macallan 
   4076      1.11        ad 	/*
   4077      1.11        ad 	 * On some chips, we should negate the backlight level.
   4078      1.11        ad 	 * XXX Find out on which chips.
   4079      1.11        ad 	 */
   4080      1.17  macallan 	if (dp->rd_softc->sc_flags & RFB_INV_BLIGHT)
   4081      1.11        ad 	level = RADEONFB_BACKLIGHT_MAX - level;
   4082       1.9  macallan 
   4083       1.9  macallan 	splx(s);
   4084       1.9  macallan 
   4085       1.9  macallan 	return level;
   4086      1.11        ad }
   4087       1.9  macallan 
   4088       1.9  macallan /* Set the backlight to the given level for the display.  */
   4089      1.59  macallan static void
   4090      1.59  macallan radeonfb_switch_backlight(struct radeonfb_display *dp, int on)
   4091      1.59  macallan {
   4092      1.59  macallan 	if (dp->rd_bl_on == on)
   4093      1.59  macallan 		return;
   4094      1.59  macallan 	dp->rd_bl_on = on;
   4095      1.59  macallan 	radeonfb_set_backlight(dp, dp->rd_bl_level);
   4096      1.59  macallan }
   4097       1.9  macallan 
   4098      1.11        ad static int
   4099       1.9  macallan radeonfb_set_backlight(struct radeonfb_display *dp, int level)
   4100       1.9  macallan {
   4101       1.9  macallan 	struct radeonfb_softc *sc;
   4102       1.9  macallan 	int rlevel, s;
   4103       1.9  macallan 	uint32_t lvds;
   4104       1.9  macallan 
   4105       1.9  macallan 	s = spltty();
   4106      1.59  macallan 
   4107      1.59  macallan 	dp->rd_bl_level = level;
   4108      1.59  macallan 	if (dp->rd_bl_on == 0)
   4109      1.59  macallan 		level = 0;
   4110      1.59  macallan 
   4111       1.9  macallan 	if (level < 0)
   4112       1.9  macallan 		level = 0;
   4113       1.9  macallan 	else if (level >= RADEONFB_BACKLIGHT_MAX)
   4114       1.9  macallan 		level = RADEONFB_BACKLIGHT_MAX;
   4115       1.9  macallan 
   4116       1.9  macallan 	sc = dp->rd_softc;
   4117       1.9  macallan 
   4118       1.9  macallan 	/* On some chips, we should negate the backlight level. */
   4119      1.17  macallan 	if (dp->rd_softc->sc_flags & RFB_INV_BLIGHT) {
   4120      1.11        ad 	rlevel = RADEONFB_BACKLIGHT_MAX - level;
   4121      1.17  macallan 	} else
   4122      1.11        ad 	rlevel = level;
   4123       1.9  macallan 
   4124       1.9  macallan 	callout_stop(&dp->rd_bl_lvds_co);
   4125       1.9  macallan 	radeonfb_engine_idle(sc);
   4126       1.9  macallan 
   4127      1.11        ad 	/*
   4128       1.9  macallan 	 * Turn off the display if the backlight is set to 0, since the
   4129      1.11        ad 	 * display is useless without backlight anyway.
   4130       1.9  macallan 	 */
   4131       1.9  macallan 	if (level == 0)
   4132       1.9  macallan 		radeonfb_blank(dp, 1);
   4133       1.9  macallan 	else if (radeonfb_get_backlight(dp) == 0)
   4134       1.9  macallan 		radeonfb_blank(dp, 0);
   4135      1.11        ad 
   4136       1.9  macallan 	lvds = radeonfb_get32(sc, RADEON_LVDS_GEN_CNTL);
   4137       1.9  macallan 	lvds &= ~RADEON_LVDS_DISPLAY_DIS;
   4138       1.9  macallan 	if (!(lvds & RADEON_LVDS_BLON) || !(lvds & RADEON_LVDS_ON)) {
   4139       1.9  macallan 		lvds |= dp->rd_bl_lvds_val & RADEON_LVDS_DIGON;
   4140       1.9  macallan 		lvds |= RADEON_LVDS_BLON | RADEON_LVDS_EN;
   4141       1.9  macallan 		radeonfb_put32(sc, RADEON_LVDS_GEN_CNTL, lvds);
   4142       1.9  macallan 		lvds &= ~RADEON_LVDS_BL_MOD_LEV_MASK;
   4143       1.9  macallan 		lvds |= rlevel << RADEON_LVDS_BL_MOD_LEV_SHIFT;
   4144       1.9  macallan 		lvds |= RADEON_LVDS_ON;
   4145       1.9  macallan 		lvds |= dp->rd_bl_lvds_val & RADEON_LVDS_BL_MOD_EN;
   4146       1.9  macallan 	} else {
   4147       1.9  macallan 		lvds &= ~RADEON_LVDS_BL_MOD_LEV_MASK;
   4148       1.9  macallan 		lvds |= rlevel << RADEON_LVDS_BL_MOD_LEV_SHIFT;
   4149       1.9  macallan 		radeonfb_put32(sc, RADEON_LVDS_GEN_CNTL, lvds);
   4150       1.9  macallan 	}
   4151      1.11        ad 
   4152       1.9  macallan 	dp->rd_bl_lvds_val &= ~RADEON_LVDS_STATE_MASK;
   4153       1.9  macallan 	dp->rd_bl_lvds_val |= lvds & RADEON_LVDS_STATE_MASK;
   4154       1.9  macallan 	/* XXX What is the correct delay? */
   4155      1.11        ad 	callout_schedule(&dp->rd_bl_lvds_co, 200 * hz);
   4156       1.9  macallan 
   4157       1.9  macallan 	splx(s);
   4158       1.9  macallan 
   4159       1.9  macallan 	return 0;
   4160       1.9  macallan }
   4161       1.9  macallan 
   4162      1.11        ad /*
   4163      1.11        ad  * Callout function for delayed operations on the LVDS_GEN_CNTL register.
   4164       1.9  macallan  * Set the delayed bits in the register, and clear the stored delayed
   4165       1.9  macallan  * value.
   4166       1.9  macallan  */
   4167       1.9  macallan 
   4168       1.9  macallan static void radeonfb_lvds_callout(void *arg)
   4169       1.9  macallan {
   4170       1.9  macallan 	struct radeonfb_display *dp = arg;
   4171       1.9  macallan 	int s;
   4172       1.9  macallan 
   4173       1.9  macallan 	s = splhigh();
   4174       1.9  macallan 
   4175      1.11        ad 	radeonfb_mask32(dp->rd_softc, RADEON_LVDS_GEN_CNTL, ~0,
   4176       1.9  macallan 			dp->rd_bl_lvds_val);
   4177       1.9  macallan 	dp->rd_bl_lvds_val = 0;
   4178       1.9  macallan 
   4179       1.9  macallan 	splx(s);
   4180       1.9  macallan }
   4181      1.34  macallan 
   4182      1.34  macallan static void
   4183      1.34  macallan radeonfb_brightness_up(device_t dev)
   4184      1.34  macallan {
   4185      1.34  macallan 	struct radeonfb_softc *sc = device_private(dev);
   4186      1.59  macallan 	struct radeonfb_display *dp = &sc->sc_displays[0];
   4187      1.34  macallan 	int level;
   4188      1.34  macallan 
   4189      1.34  macallan 	/* we assume the main display is the first one - need a better way */
   4190      1.34  macallan 	if (sc->sc_ndisplays < 1) return;
   4191      1.59  macallan 	/* make sure pushing the hotkeys always has an effect */
   4192      1.59  macallan 	dp->rd_bl_on = 1;
   4193      1.59  macallan 	level = dp->rd_bl_level;
   4194      1.34  macallan 	level = min(RADEONFB_BACKLIGHT_MAX, level + 5);
   4195      1.59  macallan 	radeonfb_set_backlight(dp, level);
   4196      1.34  macallan }
   4197      1.34  macallan 
   4198      1.34  macallan static void
   4199      1.34  macallan radeonfb_brightness_down(device_t dev)
   4200      1.34  macallan {
   4201      1.34  macallan 	struct radeonfb_softc *sc = device_private(dev);
   4202      1.59  macallan 	struct radeonfb_display *dp = &sc->sc_displays[0];
   4203      1.34  macallan 	int level;
   4204      1.34  macallan 
   4205      1.34  macallan 	/* we assume the main display is the first one - need a better way */
   4206      1.34  macallan 	if (sc->sc_ndisplays < 1) return;
   4207      1.59  macallan 	/* make sure pushing the hotkeys always has an effect */
   4208      1.59  macallan 	dp->rd_bl_on = 1;
   4209      1.59  macallan 	level = dp->rd_bl_level;
   4210      1.34  macallan 	level = max(0, level - 5);
   4211      1.59  macallan 	radeonfb_set_backlight(dp, level);
   4212      1.34  macallan }
   4213