radeonfb.c revision 1.8.2.6
1 1.8.2.6 yamt /* $NetBSD: radeonfb.c,v 1.8.2.6 2007/12/07 17:30:31 yamt Exp $ */ 2 1.8.2.2 yamt 3 1.8.2.2 yamt /*- 4 1.8.2.2 yamt * Copyright (c) 2006 Itronix Inc. 5 1.8.2.2 yamt * All rights reserved. 6 1.8.2.2 yamt * 7 1.8.2.2 yamt * Written by Garrett D'Amore for Itronix Inc. 8 1.8.2.2 yamt * 9 1.8.2.2 yamt * Redistribution and use in source and binary forms, with or without 10 1.8.2.2 yamt * modification, are permitted provided that the following conditions 11 1.8.2.2 yamt * are met: 12 1.8.2.2 yamt * 1. Redistributions of source code must retain the above copyright 13 1.8.2.2 yamt * notice, this list of conditions and the following disclaimer. 14 1.8.2.2 yamt * 2. Redistributions in binary form must reproduce the above copyright 15 1.8.2.2 yamt * notice, this list of conditions and the following disclaimer in the 16 1.8.2.2 yamt * documentation and/or other materials provided with the distribution. 17 1.8.2.2 yamt * 3. The name of Itronix Inc. may not be used to endorse 18 1.8.2.2 yamt * or promote products derived from this software without specific 19 1.8.2.2 yamt * prior written permission. 20 1.8.2.2 yamt * 21 1.8.2.2 yamt * THIS SOFTWARE IS PROVIDED BY ITRONIX INC. ``AS IS'' AND ANY EXPRESS 22 1.8.2.2 yamt * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 23 1.8.2.2 yamt * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 1.8.2.2 yamt * ARE DISCLAIMED. IN NO EVENT SHALL ITRONIX INC. BE LIABLE FOR ANY 25 1.8.2.2 yamt * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 26 1.8.2.2 yamt * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE 27 1.8.2.2 yamt * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 1.8.2.2 yamt * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 29 1.8.2.2 yamt * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 30 1.8.2.2 yamt * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 31 1.8.2.2 yamt * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 1.8.2.2 yamt */ 33 1.8.2.2 yamt 34 1.8.2.2 yamt /* 35 1.8.2.2 yamt * ATI Technologies Inc. ("ATI") has not assisted in the creation of, and 36 1.8.2.2 yamt * does not endorse, this software. ATI will not be responsible or liable 37 1.8.2.2 yamt * for any actual or alleged damage or loss caused by or in connection with 38 1.8.2.2 yamt * the use of or reliance on this software. 39 1.8.2.2 yamt */ 40 1.8.2.2 yamt 41 1.8.2.2 yamt /* 42 1.8.2.2 yamt * Portions of this code were taken from XFree86's Radeon driver, which bears 43 1.8.2.2 yamt * this notice: 44 1.8.2.2 yamt * 45 1.8.2.2 yamt * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and 46 1.8.2.2 yamt * VA Linux Systems Inc., Fremont, California. 47 1.8.2.2 yamt * 48 1.8.2.2 yamt * All Rights Reserved. 49 1.8.2.2 yamt * 50 1.8.2.2 yamt * Permission is hereby granted, free of charge, to any person obtaining 51 1.8.2.2 yamt * a copy of this software and associated documentation files (the 52 1.8.2.2 yamt * "Software"), to deal in the Software without restriction, including 53 1.8.2.2 yamt * without limitation on the rights to use, copy, modify, merge, 54 1.8.2.2 yamt * publish, distribute, sublicense, and/or sell copies of the Software, 55 1.8.2.2 yamt * and to permit persons to whom the Software is furnished to do so, 56 1.8.2.2 yamt * subject to the following conditions: 57 1.8.2.2 yamt * 58 1.8.2.2 yamt * The above copyright notice and this permission notice (including the 59 1.8.2.2 yamt * next paragraph) shall be included in all copies or substantial 60 1.8.2.2 yamt * portions of the Software. 61 1.8.2.2 yamt * 62 1.8.2.2 yamt * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 63 1.8.2.2 yamt * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 64 1.8.2.2 yamt * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 65 1.8.2.2 yamt * NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR 66 1.8.2.2 yamt * THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 67 1.8.2.2 yamt * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 68 1.8.2.2 yamt * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 69 1.8.2.2 yamt * DEALINGS IN THE SOFTWARE. 70 1.8.2.2 yamt */ 71 1.8.2.2 yamt 72 1.8.2.2 yamt #include <sys/cdefs.h> 73 1.8.2.6 yamt __KERNEL_RCSID(0, "$NetBSD: radeonfb.c,v 1.8.2.6 2007/12/07 17:30:31 yamt Exp $"); 74 1.8.2.2 yamt 75 1.8.2.2 yamt #define RADEONFB_DEFAULT_DEPTH 32 76 1.8.2.2 yamt 77 1.8.2.2 yamt #include <sys/param.h> 78 1.8.2.2 yamt #include <sys/systm.h> 79 1.8.2.2 yamt #include <sys/device.h> 80 1.8.2.2 yamt #include <sys/malloc.h> 81 1.8.2.5 yamt #include <sys/bus.h> 82 1.8.2.2 yamt #include <sys/kernel.h> 83 1.8.2.2 yamt #include <sys/lwp.h> 84 1.8.2.2 yamt #include <sys/kauth.h> 85 1.8.2.2 yamt 86 1.8.2.2 yamt #include <dev/wscons/wsdisplayvar.h> 87 1.8.2.2 yamt #include <dev/wscons/wsconsio.h> 88 1.8.2.2 yamt #include <dev/wsfont/wsfont.h> 89 1.8.2.2 yamt #include <dev/rasops/rasops.h> 90 1.8.2.2 yamt #include <dev/videomode/videomode.h> 91 1.8.2.2 yamt #include <dev/videomode/edidvar.h> 92 1.8.2.2 yamt #include <dev/wscons/wsdisplay_vconsvar.h> 93 1.8.2.2 yamt 94 1.8.2.2 yamt #include <dev/pci/pcidevs.h> 95 1.8.2.2 yamt #include <dev/pci/pcireg.h> 96 1.8.2.2 yamt #include <dev/pci/pcivar.h> 97 1.8.2.2 yamt #include <dev/pci/radeonfbreg.h> 98 1.8.2.2 yamt #include <dev/pci/radeonfbvar.h> 99 1.8.2.4 yamt #include "opt_radeonfb.h" 100 1.8.2.2 yamt 101 1.8.2.2 yamt static int radeonfb_match(struct device *, struct cfdata *, void *); 102 1.8.2.2 yamt static void radeonfb_attach(struct device *, struct device *, void *); 103 1.8.2.4 yamt static int radeonfb_ioctl(void *, void *, unsigned long, void *, int, 104 1.8.2.2 yamt struct lwp *); 105 1.8.2.2 yamt static paddr_t radeonfb_mmap(void *, void *, off_t, int); 106 1.8.2.2 yamt static int radeonfb_scratch_test(struct radeonfb_softc *, int, uint32_t); 107 1.8.2.2 yamt static void radeonfb_loadbios(struct radeonfb_softc *, 108 1.8.2.2 yamt struct pci_attach_args *); 109 1.8.2.2 yamt 110 1.8.2.2 yamt static uintmax_t radeonfb_getprop_num(struct radeonfb_softc *, const char *, 111 1.8.2.2 yamt uintmax_t); 112 1.8.2.2 yamt static int radeonfb_getclocks(struct radeonfb_softc *); 113 1.8.2.2 yamt static int radeonfb_gettmds(struct radeonfb_softc *); 114 1.8.2.2 yamt static int radeonfb_calc_dividers(struct radeonfb_softc *, uint32_t, 115 1.8.2.2 yamt uint32_t *, uint32_t *); 116 1.8.2.2 yamt static int radeonfb_getconnectors(struct radeonfb_softc *); 117 1.8.2.2 yamt static const struct videomode *radeonfb_modelookup(const char *); 118 1.8.2.2 yamt static void radeonfb_init_screen(void *, struct vcons_screen *, int, long *); 119 1.8.2.2 yamt static void radeonfb_pllwriteupdate(struct radeonfb_softc *, int); 120 1.8.2.2 yamt static void radeonfb_pllwaitatomicread(struct radeonfb_softc *, int); 121 1.8.2.2 yamt static void radeonfb_program_vclk(struct radeonfb_softc *, int, int); 122 1.8.2.2 yamt static void radeonfb_modeswitch(struct radeonfb_display *); 123 1.8.2.2 yamt static void radeonfb_setcrtc(struct radeonfb_display *, int); 124 1.8.2.2 yamt static void radeonfb_init_misc(struct radeonfb_softc *); 125 1.8.2.2 yamt static void radeonfb_set_fbloc(struct radeonfb_softc *); 126 1.8.2.2 yamt static void radeonfb_init_palette(struct radeonfb_softc *, int); 127 1.8.2.2 yamt static void radeonfb_r300cg_workaround(struct radeonfb_softc *); 128 1.8.2.2 yamt 129 1.8.2.2 yamt static int radeonfb_isblank(struct radeonfb_display *); 130 1.8.2.2 yamt static void radeonfb_blank(struct radeonfb_display *, int); 131 1.8.2.2 yamt static int radeonfb_set_cursor(struct radeonfb_display *, 132 1.8.2.2 yamt struct wsdisplay_cursor *); 133 1.8.2.2 yamt static int radeonfb_set_curpos(struct radeonfb_display *, 134 1.8.2.2 yamt struct wsdisplay_curpos *); 135 1.8.2.2 yamt 136 1.8.2.2 yamt /* acceleration support */ 137 1.8.2.2 yamt static void radeonfb_rectfill(struct radeonfb_display *, int dstx, int dsty, 138 1.8.2.2 yamt int width, int height, uint32_t color); 139 1.8.2.2 yamt static void radeonfb_bitblt(struct radeonfb_display *, int srcx, int srcy, 140 1.8.2.2 yamt int dstx, int dsty, int width, int height, int rop, uint32_t mask); 141 1.8.2.2 yamt static void radeonfb_feed_bytes(struct radeonfb_display *, int, uint8_t *); 142 1.8.2.2 yamt static void radeonfb_setup_mono(struct radeonfb_display *, int, int, int, 143 1.8.2.2 yamt int, uint32_t, uint32_t); 144 1.8.2.2 yamt 145 1.8.2.2 yamt /* hw cursor support */ 146 1.8.2.2 yamt static void radeonfb_cursor_cmap(struct radeonfb_display *); 147 1.8.2.2 yamt static void radeonfb_cursor_shape(struct radeonfb_display *); 148 1.8.2.2 yamt static void radeonfb_cursor_position(struct radeonfb_display *); 149 1.8.2.2 yamt static void radeonfb_cursor_visible(struct radeonfb_display *); 150 1.8.2.2 yamt static void radeonfb_cursor_update(struct radeonfb_display *, unsigned); 151 1.8.2.2 yamt 152 1.8.2.2 yamt static void radeonfb_wait_fifo(struct radeonfb_softc *, int); 153 1.8.2.2 yamt static void radeonfb_engine_idle(struct radeonfb_softc *); 154 1.8.2.2 yamt static void radeonfb_engine_flush(struct radeonfb_softc *); 155 1.8.2.2 yamt static void radeonfb_engine_reset(struct radeonfb_softc *); 156 1.8.2.2 yamt static void radeonfb_engine_init(struct radeonfb_display *); 157 1.8.2.2 yamt static inline void radeonfb_unclip(struct radeonfb_softc *); 158 1.8.2.2 yamt 159 1.8.2.2 yamt static void radeonfb_eraserows(void *, int, int, long); 160 1.8.2.2 yamt static void radeonfb_erasecols(void *, int, int, int, long); 161 1.8.2.2 yamt static void radeonfb_copyrows(void *, int, int, int); 162 1.8.2.2 yamt static void radeonfb_copycols(void *, int, int, int, int); 163 1.8.2.2 yamt static void radeonfb_cursor(void *, int, int, int); 164 1.8.2.2 yamt static void radeonfb_putchar(void *, int, int, unsigned, long); 165 1.8.2.2 yamt static int radeonfb_allocattr(void *, int, int, int, long *); 166 1.8.2.2 yamt 167 1.8.2.3 yamt static int radeonfb_get_backlight(struct radeonfb_display *); 168 1.8.2.3 yamt static int radeonfb_set_backlight(struct radeonfb_display *, int); 169 1.8.2.3 yamt static void radeonfb_lvds_callout(void *); 170 1.8.2.3 yamt 171 1.8.2.2 yamt static struct videomode *radeonfb_best_refresh(struct videomode *, 172 1.8.2.2 yamt struct videomode *); 173 1.8.2.2 yamt static void radeonfb_pickres(struct radeonfb_display *, uint16_t *, 174 1.8.2.2 yamt uint16_t *, int); 175 1.8.2.3 yamt static const struct videomode *radeonfb_port_mode(struct radeonfb_softc *, 176 1.8.2.3 yamt struct radeonfb_port *, int, int); 177 1.8.2.2 yamt 178 1.8.2.4 yamt static int radeonfb_drm_print(void *, const char *); 179 1.8.2.2 yamt 180 1.8.2.2 yamt #ifdef RADEON_DEBUG 181 1.8.2.2 yamt int radeon_debug = 1; 182 1.8.2.2 yamt #define DPRINTF(x) \ 183 1.8.2.2 yamt if (radeon_debug) printf x 184 1.8.2.2 yamt #define PRINTREG(r) DPRINTF((#r " = %08x\n", GET32(sc, r))) 185 1.8.2.2 yamt #define PRINTPLL(r) DPRINTF((#r " = %08x\n", GETPLL(sc, r))) 186 1.8.2.2 yamt #else 187 1.8.2.2 yamt #define DPRINTF(x) 188 1.8.2.2 yamt #define PRINTREG(r) 189 1.8.2.2 yamt #define PRINTPLL(r) 190 1.8.2.2 yamt #endif 191 1.8.2.2 yamt 192 1.8.2.2 yamt #define ROUNDUP(x,y) (((x) + ((y) - 1)) & ~((y) - 1)) 193 1.8.2.2 yamt 194 1.8.2.2 yamt #ifndef RADEON_DEFAULT_MODE 195 1.8.2.2 yamt /* any reasonably modern display should handle this */ 196 1.8.2.2 yamt #define RADEON_DEFAULT_MODE "1024x768x60" 197 1.8.2.2 yamt #endif 198 1.8.2.2 yamt 199 1.8.2.2 yamt const char *radeonfb_default_mode = RADEON_DEFAULT_MODE; 200 1.8.2.2 yamt 201 1.8.2.2 yamt static struct { 202 1.8.2.2 yamt int size; /* minimum memory size (MB) */ 203 1.8.2.2 yamt int maxx; /* maximum x dimension */ 204 1.8.2.2 yamt int maxy; /* maximum y dimension */ 205 1.8.2.2 yamt int maxbpp; /* maximum bpp */ 206 1.8.2.2 yamt int maxdisp; /* maximum logical display count */ 207 1.8.2.2 yamt } radeonfb_limits[] = { 208 1.8.2.2 yamt { 32, 2048, 1536, 32, 2 }, 209 1.8.2.2 yamt { 16, 1600, 1200, 32, 2 }, 210 1.8.2.2 yamt { 8, 1600, 1200, 32, 1 }, 211 1.8.2.2 yamt { 0, 0, 0, 0, 0 }, 212 1.8.2.2 yamt }; 213 1.8.2.2 yamt 214 1.8.2.2 yamt static struct wsscreen_descr radeonfb_stdscreen = { 215 1.8.2.2 yamt "fb", /* name */ 216 1.8.2.2 yamt 0, 0, /* ncols, nrows */ 217 1.8.2.2 yamt NULL, /* textops */ 218 1.8.2.2 yamt 8, 16, /* fontwidth, fontheight */ 219 1.8.2.2 yamt WSSCREEN_WSCOLORS, /* capabilities */ 220 1.8.2.2 yamt 0, /* modecookie */ 221 1.8.2.2 yamt }; 222 1.8.2.2 yamt 223 1.8.2.2 yamt struct wsdisplay_accessops radeonfb_accessops = { 224 1.8.2.2 yamt radeonfb_ioctl, 225 1.8.2.2 yamt radeonfb_mmap, 226 1.8.2.2 yamt NULL, /* vcons_alloc_screen */ 227 1.8.2.2 yamt NULL, /* vcons_free_screen */ 228 1.8.2.2 yamt NULL, /* vcons_show_screen */ 229 1.8.2.2 yamt NULL, /* load_font */ 230 1.8.2.2 yamt NULL, /* pollc */ 231 1.8.2.2 yamt NULL, /* scroll */ 232 1.8.2.2 yamt }; 233 1.8.2.2 yamt 234 1.8.2.2 yamt static struct { 235 1.8.2.2 yamt uint16_t devid; 236 1.8.2.2 yamt uint16_t family; 237 1.8.2.2 yamt uint16_t flags; 238 1.8.2.2 yamt } radeonfb_devices[] = 239 1.8.2.2 yamt { 240 1.8.2.2 yamt /* R100 family */ 241 1.8.2.2 yamt { PCI_PRODUCT_ATI_RADEON_R100_QD, RADEON_R100, 0 }, 242 1.8.2.2 yamt { PCI_PRODUCT_ATI_RADEON_R100_QE, RADEON_R100, 0 }, 243 1.8.2.2 yamt { PCI_PRODUCT_ATI_RADEON_R100_QF, RADEON_R100, 0 }, 244 1.8.2.2 yamt { PCI_PRODUCT_ATI_RADEON_R100_QG, RADEON_R100, 0 }, 245 1.8.2.2 yamt 246 1.8.2.2 yamt /* RV100 family */ 247 1.8.2.2 yamt { PCI_PRODUCT_ATI_RADEON_RV100_LY, RADEON_RV100, RFB_MOB }, 248 1.8.2.2 yamt { PCI_PRODUCT_ATI_RADEON_RV100_LZ, RADEON_RV100, RFB_MOB }, 249 1.8.2.2 yamt { PCI_PRODUCT_ATI_RADEON_RV100_QY, RADEON_RV100, 0 }, 250 1.8.2.2 yamt { PCI_PRODUCT_ATI_RADEON_RV100_QZ, RADEON_RV100, 0 }, 251 1.8.2.2 yamt 252 1.8.2.2 yamt /* RS100 family */ 253 1.8.2.2 yamt { PCI_PRODUCT_ATI_RADEON_RS100_4136, RADEON_RS100, 0 }, 254 1.8.2.2 yamt { PCI_PRODUCT_ATI_RADEON_RS100_4336, RADEON_RS100, RFB_MOB }, 255 1.8.2.2 yamt 256 1.8.2.2 yamt /* RS200/RS250 family */ 257 1.8.2.2 yamt { PCI_PRODUCT_ATI_RADEON_RS200_4337, RADEON_RS200, RFB_MOB }, 258 1.8.2.2 yamt { PCI_PRODUCT_ATI_RADEON_RS200_A7, RADEON_RS200, 0 }, 259 1.8.2.2 yamt { PCI_PRODUCT_ATI_RADEON_RS250_B7, RADEON_RS200, RFB_MOB }, 260 1.8.2.2 yamt { PCI_PRODUCT_ATI_RADEON_RS250_D7, RADEON_RS200, 0 }, 261 1.8.2.2 yamt 262 1.8.2.2 yamt /* R200 family */ 263 1.8.2.2 yamt /* add more R200 products? , 5148 */ 264 1.8.2.2 yamt { PCI_PRODUCT_ATI_RADEON_R200_BB, RADEON_R200, 0 }, 265 1.8.2.2 yamt { PCI_PRODUCT_ATI_RADEON_R200_BC, RADEON_R200, 0 }, 266 1.8.2.2 yamt { PCI_PRODUCT_ATI_RADEON_R200_QH, RADEON_R200, 0 }, 267 1.8.2.2 yamt { PCI_PRODUCT_ATI_RADEON_R200_QL, RADEON_R200, 0 }, 268 1.8.2.2 yamt { PCI_PRODUCT_ATI_RADEON_R200_QM, RADEON_R200, 0 }, 269 1.8.2.2 yamt 270 1.8.2.2 yamt /* RV200 family */ 271 1.8.2.2 yamt { PCI_PRODUCT_ATI_RADEON_RV200_LW, RADEON_RV200, RFB_MOB }, 272 1.8.2.2 yamt { PCI_PRODUCT_ATI_RADEON_RV200_LX, RADEON_RV200, RFB_MOB }, 273 1.8.2.2 yamt { PCI_PRODUCT_ATI_RADEON_RV200_QW, RADEON_RV200, 0 }, 274 1.8.2.2 yamt { PCI_PRODUCT_ATI_RADEON_RV200_QX, RADEON_RV200, 0 }, 275 1.8.2.2 yamt 276 1.8.2.2 yamt /* RV250 family */ 277 1.8.2.2 yamt { PCI_PRODUCT_ATI_RADEON_RV250_4966, RADEON_RV250, 0 }, 278 1.8.2.2 yamt { PCI_PRODUCT_ATI_RADEON_RV250_4967, RADEON_RV250, 0 }, 279 1.8.2.2 yamt { PCI_PRODUCT_ATI_RADEON_RV250_4C64, RADEON_RV250, RFB_MOB }, 280 1.8.2.2 yamt { PCI_PRODUCT_ATI_RADEON_RV250_4C66, RADEON_RV250, RFB_MOB }, 281 1.8.2.2 yamt { PCI_PRODUCT_ATI_RADEON_RV250_4C67, RADEON_RV250, RFB_MOB }, 282 1.8.2.2 yamt 283 1.8.2.2 yamt /* RS300 family */ 284 1.8.2.2 yamt { PCI_PRODUCT_ATI_RADEON_RS300_X5, RADEON_RS300, 0 }, 285 1.8.2.2 yamt { PCI_PRODUCT_ATI_RADEON_RS300_X4, RADEON_RS300, 0 }, 286 1.8.2.2 yamt { PCI_PRODUCT_ATI_RADEON_RS300_7834, RADEON_RS300, 0 }, 287 1.8.2.2 yamt { PCI_PRODUCT_ATI_RADEON_RS300_7835, RADEON_RS300, RFB_MOB }, 288 1.8.2.2 yamt 289 1.8.2.2 yamt /* RV280 family */ 290 1.8.2.2 yamt { PCI_PRODUCT_ATI_RADEON_RV280_5960, RADEON_RV280, 0 }, 291 1.8.2.2 yamt { PCI_PRODUCT_ATI_RADEON_RV280_5961, RADEON_RV280, 0 }, 292 1.8.2.2 yamt { PCI_PRODUCT_ATI_RADEON_RV280_5962, RADEON_RV280, 0 }, 293 1.8.2.2 yamt { PCI_PRODUCT_ATI_RADEON_RV280_5963, RADEON_RV280, 0 }, 294 1.8.2.2 yamt { PCI_PRODUCT_ATI_RADEON_RV280_5964, RADEON_RV280, 0 }, 295 1.8.2.2 yamt { PCI_PRODUCT_ATI_RADEON_RV280_5C61, RADEON_RV280, RFB_MOB }, 296 1.8.2.2 yamt { PCI_PRODUCT_ATI_RADEON_RV280_5C63, RADEON_RV280, RFB_MOB }, 297 1.8.2.2 yamt 298 1.8.2.2 yamt /* R300 family */ 299 1.8.2.2 yamt { PCI_PRODUCT_ATI_RADEON_R300_AD, RADEON_R300, 0 }, 300 1.8.2.2 yamt { PCI_PRODUCT_ATI_RADEON_R300_AE, RADEON_R300, 0 }, 301 1.8.2.2 yamt { PCI_PRODUCT_ATI_RADEON_R300_AF, RADEON_R300, 0 }, 302 1.8.2.2 yamt { PCI_PRODUCT_ATI_RADEON_R300_AG, RADEON_R300, 0 }, 303 1.8.2.2 yamt { PCI_PRODUCT_ATI_RADEON_R300_ND, RADEON_R300, 0 }, 304 1.8.2.2 yamt { PCI_PRODUCT_ATI_RADEON_R300_NE, RADEON_R300, 0 }, 305 1.8.2.2 yamt { PCI_PRODUCT_ATI_RADEON_R300_NF, RADEON_R300, 0 }, 306 1.8.2.2 yamt { PCI_PRODUCT_ATI_RADEON_R300_NG, RADEON_R300, 0 }, 307 1.8.2.2 yamt 308 1.8.2.2 yamt /* RV350/RV360 family */ 309 1.8.2.2 yamt { PCI_PRODUCT_ATI_RADEON_RV350_AP, RADEON_RV350, 0 }, 310 1.8.2.2 yamt { PCI_PRODUCT_ATI_RADEON_RV350_AQ, RADEON_RV350, 0 }, 311 1.8.2.2 yamt { PCI_PRODUCT_ATI_RADEON_RV360_AR, RADEON_RV350, 0 }, 312 1.8.2.2 yamt { PCI_PRODUCT_ATI_RADEON_RV350_AS, RADEON_RV350, 0 }, 313 1.8.2.2 yamt { PCI_PRODUCT_ATI_RADEON_RV350_AT, RADEON_RV350, 0 }, 314 1.8.2.2 yamt { PCI_PRODUCT_ATI_RADEON_RV350_AV, RADEON_RV350, 0 }, 315 1.8.2.2 yamt { PCI_PRODUCT_ATI_RADEON_RV350_NP, RADEON_RV350, RFB_MOB }, 316 1.8.2.2 yamt { PCI_PRODUCT_ATI_RADEON_RV350_NQ, RADEON_RV350, RFB_MOB }, 317 1.8.2.2 yamt { PCI_PRODUCT_ATI_RADEON_RV350_NR, RADEON_RV350, RFB_MOB }, 318 1.8.2.2 yamt { PCI_PRODUCT_ATI_RADEON_RV350_NS, RADEON_RV350, RFB_MOB }, 319 1.8.2.2 yamt { PCI_PRODUCT_ATI_RADEON_RV350_NT, RADEON_RV350, RFB_MOB }, 320 1.8.2.2 yamt { PCI_PRODUCT_ATI_RADEON_RV350_NV, RADEON_RV350, RFB_MOB }, 321 1.8.2.2 yamt 322 1.8.2.2 yamt /* R350/R360 family */ 323 1.8.2.2 yamt { PCI_PRODUCT_ATI_RADEON_R350_AH, RADEON_R350, 0 }, 324 1.8.2.2 yamt { PCI_PRODUCT_ATI_RADEON_R350_AI, RADEON_R350, 0 }, 325 1.8.2.2 yamt { PCI_PRODUCT_ATI_RADEON_R350_AJ, RADEON_R350, 0 }, 326 1.8.2.2 yamt { PCI_PRODUCT_ATI_RADEON_R350_AK, RADEON_R350, 0 }, 327 1.8.2.2 yamt { PCI_PRODUCT_ATI_RADEON_R350_NH, RADEON_R350, 0 }, 328 1.8.2.2 yamt { PCI_PRODUCT_ATI_RADEON_R350_NI, RADEON_R350, 0 }, 329 1.8.2.2 yamt { PCI_PRODUCT_ATI_RADEON_R350_NK, RADEON_R350, 0 }, 330 1.8.2.2 yamt { PCI_PRODUCT_ATI_RADEON_R360_NJ, RADEON_R350, 0 }, 331 1.8.2.2 yamt 332 1.8.2.2 yamt /* RV380/RV370 family */ 333 1.8.2.2 yamt { PCI_PRODUCT_ATI_RADEON_RV380_3150, RADEON_RV380, RFB_MOB }, 334 1.8.2.2 yamt { PCI_PRODUCT_ATI_RADEON_RV380_3154, RADEON_RV380, RFB_MOB }, 335 1.8.2.2 yamt { PCI_PRODUCT_ATI_RADEON_RV380_3E50, RADEON_RV380, 0 }, 336 1.8.2.2 yamt { PCI_PRODUCT_ATI_RADEON_RV380_3E54, RADEON_RV380, 0 }, 337 1.8.2.2 yamt { PCI_PRODUCT_ATI_RADEON_RV370_5460, RADEON_RV380, RFB_MOB }, 338 1.8.2.2 yamt { PCI_PRODUCT_ATI_RADEON_RV370_5464, RADEON_RV380, RFB_MOB }, 339 1.8.2.2 yamt { PCI_PRODUCT_ATI_RADEON_RV370_5B60, RADEON_RV380, 0 }, 340 1.8.2.2 yamt { PCI_PRODUCT_ATI_RADEON_RV370_5B64, RADEON_RV380, 0 }, 341 1.8.2.2 yamt { PCI_PRODUCT_ATI_RADEON_RV370_5B65, RADEON_RV380, 0 }, 342 1.8.2.2 yamt 343 1.8.2.2 yamt /* R420/R423 family */ 344 1.8.2.2 yamt { PCI_PRODUCT_ATI_RADEON_R420_JH, RADEON_R420, 0 }, 345 1.8.2.2 yamt { PCI_PRODUCT_ATI_RADEON_R420_JI, RADEON_R420, 0 }, 346 1.8.2.2 yamt { PCI_PRODUCT_ATI_RADEON_R420_JJ, RADEON_R420, 0 }, 347 1.8.2.2 yamt { PCI_PRODUCT_ATI_RADEON_R420_JK, RADEON_R420, 0 }, 348 1.8.2.2 yamt { PCI_PRODUCT_ATI_RADEON_R420_JL, RADEON_R420, 0 }, 349 1.8.2.2 yamt { PCI_PRODUCT_ATI_RADEON_R420_JM, RADEON_R420, 0 }, 350 1.8.2.2 yamt { PCI_PRODUCT_ATI_RADEON_R420_JN, RADEON_R420, RFB_MOB }, 351 1.8.2.2 yamt { PCI_PRODUCT_ATI_RADEON_R420_JP, RADEON_R420, 0 }, 352 1.8.2.2 yamt { PCI_PRODUCT_ATI_RADEON_R423_UH, RADEON_R420, 0 }, 353 1.8.2.2 yamt { PCI_PRODUCT_ATI_RADEON_R423_UI, RADEON_R420, 0 }, 354 1.8.2.2 yamt { PCI_PRODUCT_ATI_RADEON_R423_UJ, RADEON_R420, 0 }, 355 1.8.2.2 yamt { PCI_PRODUCT_ATI_RADEON_R423_UK, RADEON_R420, 0 }, 356 1.8.2.2 yamt { PCI_PRODUCT_ATI_RADEON_R423_UQ, RADEON_R420, 0 }, 357 1.8.2.2 yamt { PCI_PRODUCT_ATI_RADEON_R423_UR, RADEON_R420, 0 }, 358 1.8.2.2 yamt { PCI_PRODUCT_ATI_RADEON_R423_UT, RADEON_R420, 0 }, 359 1.8.2.2 yamt { PCI_PRODUCT_ATI_RADEON_R423_5D57, RADEON_R420, 0 }, 360 1.8.2.6 yamt { PCI_PRODUCT_ATI_RADEON_R430_554F, RADEON_R420, 0 }, 361 1.8.2.2 yamt 362 1.8.2.2 yamt { 0, 0, 0 } 363 1.8.2.2 yamt }; 364 1.8.2.2 yamt 365 1.8.2.2 yamt static struct { 366 1.8.2.2 yamt int divider; 367 1.8.2.2 yamt int mask; 368 1.8.2.2 yamt } radeonfb_dividers[] = { 369 1.8.2.2 yamt { 1, 0 }, 370 1.8.2.2 yamt { 2, 1 }, 371 1.8.2.2 yamt { 3, 4 }, 372 1.8.2.2 yamt { 4, 2 }, 373 1.8.2.2 yamt { 6, 6 }, 374 1.8.2.2 yamt { 8, 3 }, 375 1.8.2.2 yamt { 12, 7 }, 376 1.8.2.2 yamt { 0, 0 } 377 1.8.2.2 yamt }; 378 1.8.2.2 yamt 379 1.8.2.2 yamt /* 380 1.8.2.2 yamt * This table taken from X11. 381 1.8.2.2 yamt */ 382 1.8.2.2 yamt static const struct { 383 1.8.2.2 yamt int family; 384 1.8.2.2 yamt struct radeon_tmds_pll plls[4]; 385 1.8.2.2 yamt } radeonfb_tmds_pll[] = { 386 1.8.2.2 yamt { RADEON_R100, {{12000, 0xa1b}, {-1, 0xa3f}}}, 387 1.8.2.2 yamt { RADEON_RV100, {{12000, 0xa1b}, {-1, 0xa3f}}}, 388 1.8.2.2 yamt { RADEON_RS100, {{0, 0}}}, 389 1.8.2.2 yamt { RADEON_RV200, {{15000, 0xa1b}, {-1, 0xa3f}}}, 390 1.8.2.2 yamt { RADEON_RS200, {{15000, 0xa1b}, {-1, 0xa3f}}}, 391 1.8.2.2 yamt { RADEON_R200, {{15000, 0xa1b}, {-1, 0xa3f}}}, 392 1.8.2.2 yamt { RADEON_RV250, {{15500, 0x81b}, {-1, 0x83f}}}, 393 1.8.2.2 yamt { RADEON_RS300, {{0, 0}}}, 394 1.8.2.2 yamt { RADEON_RV280, {{13000, 0x400f4}, {15000, 0x400f7}}}, 395 1.8.2.2 yamt { RADEON_R300, {{-1, 0xb01cb}}}, 396 1.8.2.2 yamt { RADEON_R350, {{-1, 0xb01cb}}}, 397 1.8.2.2 yamt { RADEON_RV350, {{15000, 0xb0155}, {-1, 0xb01cb}}}, 398 1.8.2.2 yamt { RADEON_RV380, {{15000, 0xb0155}, {-1, 0xb01cb}}}, 399 1.8.2.2 yamt { RADEON_R420, {{-1, 0xb01cb}}}, 400 1.8.2.2 yamt }; 401 1.8.2.2 yamt 402 1.8.2.3 yamt #define RADEONFB_BACKLIGHT_MAX 255 /* Maximum backlight level. */ 403 1.8.2.3 yamt 404 1.8.2.2 yamt 405 1.8.2.2 yamt CFATTACH_DECL(radeonfb, sizeof (struct radeonfb_softc), 406 1.8.2.2 yamt radeonfb_match, radeonfb_attach, NULL, NULL); 407 1.8.2.2 yamt 408 1.8.2.2 yamt static int 409 1.8.2.2 yamt radeonfb_match(struct device *parent, struct cfdata *match, void *aux) 410 1.8.2.2 yamt { 411 1.8.2.2 yamt struct pci_attach_args *pa = aux; 412 1.8.2.2 yamt int i; 413 1.8.2.2 yamt 414 1.8.2.2 yamt if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_ATI) 415 1.8.2.2 yamt return 0; 416 1.8.2.2 yamt 417 1.8.2.2 yamt for (i = 0; radeonfb_devices[i].devid; i++) { 418 1.8.2.2 yamt if (PCI_PRODUCT(pa->pa_id) == radeonfb_devices[i].devid) 419 1.8.2.2 yamt return 100; /* high to defeat VGA/VESA */ 420 1.8.2.2 yamt } 421 1.8.2.2 yamt 422 1.8.2.2 yamt return 0; 423 1.8.2.2 yamt } 424 1.8.2.2 yamt 425 1.8.2.2 yamt static void 426 1.8.2.2 yamt radeonfb_attach(struct device *parent, struct device *dev, void *aux) 427 1.8.2.2 yamt { 428 1.8.2.2 yamt struct radeonfb_softc *sc = (struct radeonfb_softc *)dev; 429 1.8.2.2 yamt struct pci_attach_args *pa = aux; 430 1.8.2.3 yamt const char *mptr; 431 1.8.2.2 yamt bus_size_t bsz; 432 1.8.2.2 yamt pcireg_t screg; 433 1.8.2.2 yamt int i, j, fg, bg, ul; 434 1.8.2.2 yamt uint32_t v; 435 1.8.2.2 yamt 436 1.8.2.2 yamt sc->sc_id = pa->pa_id; 437 1.8.2.2 yamt for (i = 0; radeonfb_devices[i].devid; i++) { 438 1.8.2.2 yamt if (PCI_PRODUCT(sc->sc_id) == radeonfb_devices[i].devid) 439 1.8.2.2 yamt break; 440 1.8.2.2 yamt } 441 1.8.2.2 yamt 442 1.8.2.2 yamt pci_devinfo(sc->sc_id, pa->pa_class, 0, sc->sc_devinfo, 443 1.8.2.2 yamt sizeof(sc->sc_devinfo)); 444 1.8.2.2 yamt 445 1.8.2.2 yamt aprint_naive("\n"); 446 1.8.2.2 yamt aprint_normal(": %s\n", sc->sc_devinfo); 447 1.8.2.2 yamt 448 1.8.2.4 yamt DPRINTF((prop_dictionary_externalize(device_properties(dev)))); 449 1.8.2.4 yamt 450 1.8.2.2 yamt KASSERT(radeonfb_devices[i].devid != 0); 451 1.8.2.2 yamt sc->sc_pt = pa->pa_tag; 452 1.8.2.4 yamt sc->sc_iot = pa->pa_iot; 453 1.8.2.2 yamt sc->sc_pc = pa->pa_pc; 454 1.8.2.2 yamt sc->sc_family = radeonfb_devices[i].family; 455 1.8.2.2 yamt sc->sc_flags = radeonfb_devices[i].flags; 456 1.8.2.2 yamt 457 1.8.2.2 yamt /* enable memory and IO access */ 458 1.8.2.2 yamt screg = pci_conf_read(sc->sc_pc, sc->sc_pt, PCI_COMMAND_STATUS_REG); 459 1.8.2.2 yamt screg |= PCI_FLAGS_IO_ENABLED | PCI_FLAGS_MEM_ENABLED; 460 1.8.2.2 yamt pci_conf_write(sc->sc_pc, sc->sc_pt, PCI_COMMAND_STATUS_REG, screg); 461 1.8.2.2 yamt 462 1.8.2.2 yamt /* 463 1.8.2.2 yamt * Some flags are general to entire chip families, and rather 464 1.8.2.2 yamt * than clutter up the table with them, we go ahead and set 465 1.8.2.2 yamt * them here. 466 1.8.2.2 yamt */ 467 1.8.2.2 yamt switch (sc->sc_family) { 468 1.8.2.2 yamt case RADEON_RS100: 469 1.8.2.2 yamt case RADEON_RS200: 470 1.8.2.2 yamt sc->sc_flags |= RFB_IGP | RFB_RV100; 471 1.8.2.2 yamt break; 472 1.8.2.2 yamt 473 1.8.2.2 yamt case RADEON_RV100: 474 1.8.2.2 yamt case RADEON_RV200: 475 1.8.2.2 yamt case RADEON_RV250: 476 1.8.2.2 yamt case RADEON_RV280: 477 1.8.2.2 yamt sc->sc_flags |= RFB_RV100; 478 1.8.2.2 yamt break; 479 1.8.2.2 yamt 480 1.8.2.2 yamt case RADEON_RS300: 481 1.8.2.2 yamt sc->sc_flags |= RFB_SDAC | RFB_IGP | RFB_RV100; 482 1.8.2.2 yamt break; 483 1.8.2.2 yamt 484 1.8.2.2 yamt case RADEON_R300: 485 1.8.2.2 yamt case RADEON_RV350: 486 1.8.2.2 yamt case RADEON_R350: 487 1.8.2.2 yamt case RADEON_RV380: 488 1.8.2.2 yamt case RADEON_R420: 489 1.8.2.2 yamt /* newer chips */ 490 1.8.2.2 yamt sc->sc_flags |= RFB_R300; 491 1.8.2.2 yamt break; 492 1.8.2.2 yamt 493 1.8.2.2 yamt case RADEON_R100: 494 1.8.2.2 yamt sc->sc_flags |= RFB_NCRTC2; 495 1.8.2.2 yamt break; 496 1.8.2.2 yamt } 497 1.8.2.2 yamt 498 1.8.2.4 yamt if ((sc->sc_family == RADEON_RV200) || 499 1.8.2.4 yamt (sc->sc_family == RADEON_RV250) || 500 1.8.2.4 yamt (sc->sc_family == RADEON_RV280) || 501 1.8.2.4 yamt (sc->sc_family == RADEON_RV350)) { 502 1.8.2.4 yamt bool inverted = 0; 503 1.8.2.4 yamt /* backlight level is linear */ 504 1.8.2.4 yamt DPRINTF(("found RV* chip, backlight is supposedly linear\n")); 505 1.8.2.4 yamt prop_dictionary_get_bool(device_properties(&sc->sc_dev), 506 1.8.2.4 yamt "backlight_level_reverted", &inverted); 507 1.8.2.4 yamt if (inverted) { 508 1.8.2.4 yamt DPRINTF(("nope, it's inverted\n")); 509 1.8.2.4 yamt sc->sc_flags |= RFB_INV_BLIGHT; 510 1.8.2.4 yamt } 511 1.8.2.4 yamt } else 512 1.8.2.4 yamt sc->sc_flags |= RFB_INV_BLIGHT; 513 1.8.2.4 yamt 514 1.8.2.2 yamt /* 515 1.8.2.2 yamt * XXX: to support true multihead, this must change. 516 1.8.2.2 yamt */ 517 1.8.2.2 yamt sc->sc_ndisplays = 1; 518 1.8.2.2 yamt 519 1.8.2.2 yamt /* XXX: */ 520 1.8.2.2 yamt if (!HAS_CRTC2(sc)) { 521 1.8.2.2 yamt sc->sc_ndisplays = 1; 522 1.8.2.2 yamt } 523 1.8.2.2 yamt 524 1.8.2.2 yamt if (pci_mapreg_map(pa, RADEON_MAPREG_MMIO, PCI_MAPREG_TYPE_MEM, 0, 525 1.8.2.2 yamt &sc->sc_regt, &sc->sc_regh, &sc->sc_regaddr, 526 1.8.2.2 yamt &sc->sc_regsz) != 0) { 527 1.8.2.2 yamt aprint_error("%s: unable to map registers!\n", XNAME(sc)); 528 1.8.2.2 yamt goto error; 529 1.8.2.2 yamt } 530 1.8.2.2 yamt 531 1.8.2.2 yamt /* scratch register test... */ 532 1.8.2.2 yamt if (radeonfb_scratch_test(sc, RADEON_BIOS_0_SCRATCH, 0x55555555) || 533 1.8.2.2 yamt radeonfb_scratch_test(sc, RADEON_BIOS_0_SCRATCH, 0xaaaaaaaa)) { 534 1.8.2.2 yamt aprint_error("%s: scratch register test failed!\n", XNAME(sc)); 535 1.8.2.2 yamt goto error; 536 1.8.2.2 yamt } 537 1.8.2.2 yamt 538 1.8.2.2 yamt PRINTREG(RADEON_BIOS_4_SCRATCH); 539 1.8.2.2 yamt PRINTREG(RADEON_FP_GEN_CNTL); 540 1.8.2.2 yamt PRINTREG(RADEON_FP2_GEN_CNTL); 541 1.8.2.2 yamt PRINTREG(RADEON_TMDS_CNTL); 542 1.8.2.2 yamt PRINTREG(RADEON_TMDS_TRANSMITTER_CNTL); 543 1.8.2.2 yamt PRINTREG(RADEON_TMDS_PLL_CNTL); 544 1.8.2.2 yamt PRINTREG(RADEON_LVDS_GEN_CNTL); 545 1.8.2.2 yamt PRINTREG(RADEON_FP_HORZ_STRETCH); 546 1.8.2.2 yamt PRINTREG(RADEON_FP_VERT_STRETCH); 547 1.8.2.2 yamt 548 1.8.2.2 yamt /* XXX: RV100 specific */ 549 1.8.2.2 yamt PUT32(sc, RADEON_TMDS_PLL_CNTL, 0xa27); 550 1.8.2.2 yamt 551 1.8.2.2 yamt PATCH32(sc, RADEON_TMDS_TRANSMITTER_CNTL, 552 1.8.2.2 yamt RADEON_TMDS_TRANSMITTER_PLLEN, 553 1.8.2.2 yamt RADEON_TMDS_TRANSMITTER_PLLEN | RADEON_TMDS_TRANSMITTER_PLLRST); 554 1.8.2.2 yamt 555 1.8.2.2 yamt radeonfb_i2c_init(sc); 556 1.8.2.2 yamt 557 1.8.2.2 yamt radeonfb_loadbios(sc, pa); 558 1.8.2.2 yamt 559 1.8.2.2 yamt #ifdef RADEON_BIOS_INIT 560 1.8.2.2 yamt if (radeonfb_bios_init(sc)) { 561 1.8.2.2 yamt aprint_error("%s: BIOS inititialization failed\n", XNAME(sc)); 562 1.8.2.2 yamt goto error; 563 1.8.2.2 yamt } 564 1.8.2.2 yamt #endif 565 1.8.2.2 yamt 566 1.8.2.2 yamt if (radeonfb_getclocks(sc)) { 567 1.8.2.2 yamt aprint_error("%s: Unable to get reference clocks from BIOS\n", 568 1.8.2.2 yamt XNAME(sc)); 569 1.8.2.2 yamt goto error; 570 1.8.2.2 yamt } 571 1.8.2.2 yamt 572 1.8.2.2 yamt if (radeonfb_gettmds(sc)) { 573 1.8.2.2 yamt aprint_error("%s: Unable to identify TMDS PLL settings\n", 574 1.8.2.2 yamt XNAME(sc)); 575 1.8.2.2 yamt goto error; 576 1.8.2.2 yamt } 577 1.8.2.2 yamt 578 1.8.2.2 yamt aprint_verbose("%s: refclk = %d.%03d MHz, refdiv = %d " 579 1.8.2.2 yamt "minpll = %d, maxpll = %d\n", XNAME(sc), 580 1.8.2.2 yamt (int)sc->sc_refclk / 1000, (int)sc->sc_refclk % 1000, 581 1.8.2.2 yamt (int)sc->sc_refdiv, (int)sc->sc_minpll, (int)sc->sc_maxpll); 582 1.8.2.2 yamt 583 1.8.2.2 yamt radeonfb_getconnectors(sc); 584 1.8.2.2 yamt 585 1.8.2.2 yamt radeonfb_set_fbloc(sc); 586 1.8.2.2 yamt 587 1.8.2.2 yamt for (i = 0; radeonfb_limits[i].size; i++) { 588 1.8.2.2 yamt if (sc->sc_memsz >= radeonfb_limits[i].size) { 589 1.8.2.2 yamt sc->sc_maxx = radeonfb_limits[i].maxx; 590 1.8.2.2 yamt sc->sc_maxy = radeonfb_limits[i].maxy; 591 1.8.2.2 yamt sc->sc_maxbpp = radeonfb_limits[i].maxbpp; 592 1.8.2.2 yamt /* framebuffer offset, start at a 4K page */ 593 1.8.2.2 yamt sc->sc_fboffset = sc->sc_memsz / 594 1.8.2.2 yamt radeonfb_limits[i].maxdisp; 595 1.8.2.2 yamt /* 596 1.8.2.2 yamt * we use the fbsize to figure out where we can store 597 1.8.2.2 yamt * things like cursor data. 598 1.8.2.2 yamt */ 599 1.8.2.2 yamt sc->sc_fbsize = 600 1.8.2.2 yamt ROUNDUP(ROUNDUP(sc->sc_maxx * sc->sc_maxbpp / 8 , 601 1.8.2.2 yamt RADEON_STRIDEALIGN) * sc->sc_maxy, 602 1.8.2.2 yamt 4096); 603 1.8.2.2 yamt break; 604 1.8.2.2 yamt } 605 1.8.2.2 yamt } 606 1.8.2.2 yamt 607 1.8.2.2 yamt 608 1.8.2.2 yamt radeonfb_init_misc(sc); 609 1.8.2.2 yamt radeonfb_init_palette(sc, 0); 610 1.8.2.2 yamt if (HAS_CRTC2(sc)) 611 1.8.2.2 yamt radeonfb_init_palette(sc, 1); 612 1.8.2.2 yamt 613 1.8.2.2 yamt /* program the DAC wirings */ 614 1.8.2.2 yamt for (i = 0; i < (HAS_CRTC2(sc) ? 2 : 1); i++) { 615 1.8.2.2 yamt switch (sc->sc_ports[i].rp_dac_type) { 616 1.8.2.2 yamt case RADEON_DAC_PRIMARY: 617 1.8.2.2 yamt PATCH32(sc, RADEON_DAC_CNTL2, 618 1.8.2.2 yamt i ? RADEON_DAC2_DAC_CLK_SEL : 0, 619 1.8.2.2 yamt ~RADEON_DAC2_DAC_CLK_SEL); 620 1.8.2.2 yamt break; 621 1.8.2.2 yamt case RADEON_DAC_TVDAC: 622 1.8.2.2 yamt /* we always use the TVDAC to drive a secondary analog 623 1.8.2.2 yamt * CRT for now. if we ever support TV-out this will 624 1.8.2.2 yamt * have to change. 625 1.8.2.2 yamt */ 626 1.8.2.2 yamt SET32(sc, RADEON_DAC_CNTL2, 627 1.8.2.2 yamt RADEON_DAC2_DAC2_CLK_SEL); 628 1.8.2.2 yamt PATCH32(sc, RADEON_DISP_HW_DEBUG, 629 1.8.2.2 yamt i ? 0 : RADEON_CRT2_DISP1_SEL, 630 1.8.2.2 yamt ~RADEON_CRT2_DISP1_SEL); 631 1.8.2.2 yamt break; 632 1.8.2.2 yamt } 633 1.8.2.2 yamt } 634 1.8.2.2 yamt PRINTREG(RADEON_DAC_CNTL2); 635 1.8.2.2 yamt PRINTREG(RADEON_DISP_HW_DEBUG); 636 1.8.2.2 yamt 637 1.8.2.2 yamt /* other DAC programming */ 638 1.8.2.2 yamt v = GET32(sc, RADEON_DAC_CNTL); 639 1.8.2.2 yamt v &= (RADEON_DAC_RANGE_CNTL_MASK | RADEON_DAC_BLANKING); 640 1.8.2.2 yamt v |= RADEON_DAC_MASK_ALL | RADEON_DAC_8BIT_EN; 641 1.8.2.2 yamt PUT32(sc, RADEON_DAC_CNTL, v); 642 1.8.2.2 yamt PRINTREG(RADEON_DAC_CNTL); 643 1.8.2.2 yamt 644 1.8.2.2 yamt /* XXX: this may need more investigation */ 645 1.8.2.2 yamt PUT32(sc, RADEON_TV_DAC_CNTL, 0x00280203); 646 1.8.2.2 yamt PRINTREG(RADEON_TV_DAC_CNTL); 647 1.8.2.2 yamt 648 1.8.2.2 yamt /* enable TMDS */ 649 1.8.2.2 yamt SET32(sc, RADEON_FP_GEN_CNTL, 650 1.8.2.2 yamt RADEON_FP_TMDS_EN | 651 1.8.2.2 yamt RADEON_FP_CRTC_DONT_SHADOW_VPAR | 652 1.8.2.2 yamt RADEON_FP_CRTC_DONT_SHADOW_HEND); 653 1.8.2.2 yamt CLR32(sc, RADEON_FP_GEN_CNTL, RADEON_FP_SEL_CRTC2); 654 1.8.2.2 yamt if (HAS_CRTC2(sc)) 655 1.8.2.2 yamt SET32(sc, RADEON_FP2_GEN_CNTL, RADEON_FP2_SRC_SEL_CRTC2); 656 1.8.2.2 yamt 657 1.8.2.2 yamt /* 658 1.8.2.2 yamt * we use bus_space_map instead of pci_mapreg, because we don't 659 1.8.2.2 yamt * need the full aperature space. no point in wasting virtual 660 1.8.2.2 yamt * address space we don't intend to use, right? 661 1.8.2.2 yamt */ 662 1.8.2.2 yamt if ((sc->sc_memsz < (4096 * 1024)) || 663 1.8.2.2 yamt (pci_mapreg_info(sc->sc_pc, sc->sc_pt, RADEON_MAPREG_VRAM, 664 1.8.2.2 yamt PCI_MAPREG_TYPE_MEM, &sc->sc_memaddr, &bsz, NULL) != 0) || 665 1.8.2.2 yamt (bsz < sc->sc_memsz)) { 666 1.8.2.2 yamt sc->sc_memsz = 0; 667 1.8.2.2 yamt aprint_error("%s: Bad frame buffer configuration\n", 668 1.8.2.2 yamt XNAME(sc)); 669 1.8.2.2 yamt goto error; 670 1.8.2.2 yamt } 671 1.8.2.2 yamt 672 1.8.2.2 yamt /* 64 MB should be enough -- more just wastes map entries */ 673 1.8.2.2 yamt if (sc->sc_memsz > (64 << 20)) 674 1.8.2.2 yamt sc->sc_memsz = (64 << 20); 675 1.8.2.2 yamt 676 1.8.2.2 yamt sc->sc_memt = pa->pa_memt; 677 1.8.2.2 yamt if (bus_space_map(sc->sc_memt, sc->sc_memaddr, sc->sc_memsz, 678 1.8.2.2 yamt BUS_SPACE_MAP_LINEAR, &sc->sc_memh) != 0) { 679 1.8.2.2 yamt sc->sc_memsz = 0; 680 1.8.2.2 yamt aprint_error("%s: Unable to map frame buffer\n", XNAME(sc)); 681 1.8.2.2 yamt goto error; 682 1.8.2.2 yamt } 683 1.8.2.2 yamt 684 1.8.2.2 yamt aprint_normal("%s: %d MB aperture at 0x%08x, " 685 1.8.2.2 yamt "%d KB registers at 0x%08x\n", XNAME(sc), 686 1.8.2.2 yamt (int)sc->sc_memsz >> 20, (unsigned)sc->sc_memaddr, 687 1.8.2.2 yamt (int)sc->sc_regsz >> 10, (unsigned)sc->sc_regaddr); 688 1.8.2.2 yamt 689 1.8.2.2 yamt /* setup default video mode from devprop (allows PROM override) */ 690 1.8.2.2 yamt sc->sc_defaultmode = radeonfb_default_mode; 691 1.8.2.3 yamt if (prop_dictionary_get_cstring_nocopy(device_properties(&sc->sc_dev), 692 1.8.2.3 yamt "videomode", &mptr)) { 693 1.8.2.3 yamt 694 1.8.2.3 yamt strncpy(sc->sc_modebuf, mptr, sizeof(sc->sc_modebuf)); 695 1.8.2.3 yamt sc->sc_defaultmode = sc->sc_modebuf; 696 1.8.2.2 yamt } 697 1.8.2.2 yamt 698 1.8.2.2 yamt /* initialize some basic display parameters */ 699 1.8.2.2 yamt for (i = 0; i < sc->sc_ndisplays; i++) { 700 1.8.2.2 yamt struct radeonfb_display *dp = &sc->sc_displays[i]; 701 1.8.2.2 yamt struct rasops_info *ri; 702 1.8.2.2 yamt long defattr; 703 1.8.2.2 yamt struct wsemuldisplaydev_attach_args aa; 704 1.8.2.2 yamt 705 1.8.2.2 yamt /* 706 1.8.2.2 yamt * Figure out how many "displays" (desktops) we are going to 707 1.8.2.2 yamt * support. If more than one, then each CRTC gets its own 708 1.8.2.2 yamt * programming. 709 1.8.2.2 yamt * 710 1.8.2.2 yamt * XXX: this code needs to change to support mergedfb. 711 1.8.2.2 yamt * XXX: would be nice to allow this to be overridden 712 1.8.2.2 yamt */ 713 1.8.2.2 yamt if (HAS_CRTC2(sc) && (sc->sc_ndisplays == 1)) { 714 1.8.2.2 yamt DPRINTF(("dual crtcs!\n")); 715 1.8.2.2 yamt dp->rd_ncrtcs = 2; 716 1.8.2.2 yamt dp->rd_crtcs[0].rc_number = 0; 717 1.8.2.2 yamt dp->rd_crtcs[1].rc_number = 1; 718 1.8.2.2 yamt } else { 719 1.8.2.2 yamt dp->rd_ncrtcs = 1; 720 1.8.2.2 yamt dp->rd_crtcs[0].rc_number = i; 721 1.8.2.2 yamt } 722 1.8.2.2 yamt 723 1.8.2.2 yamt /* set up port pointer */ 724 1.8.2.2 yamt for (j = 0; j < dp->rd_ncrtcs; j++) { 725 1.8.2.2 yamt dp->rd_crtcs[j].rc_port = 726 1.8.2.2 yamt &sc->sc_ports[dp->rd_crtcs[j].rc_number]; 727 1.8.2.2 yamt } 728 1.8.2.2 yamt 729 1.8.2.2 yamt dp->rd_softc = sc; 730 1.8.2.2 yamt dp->rd_wsmode = WSDISPLAYIO_MODE_EMUL; 731 1.8.2.2 yamt dp->rd_bg = WS_DEFAULT_BG; 732 1.8.2.2 yamt #if 0 733 1.8.2.2 yamt dp->rd_bpp = sc->sc_maxbpp; /* XXX: for now */ 734 1.8.2.2 yamt #else 735 1.8.2.2 yamt dp->rd_bpp = RADEONFB_DEFAULT_DEPTH; /* XXX */ 736 1.8.2.2 yamt #endif 737 1.8.2.2 yamt /* for text mode, we pick a resolution that won't 738 1.8.2.2 yamt * require panning */ 739 1.8.2.2 yamt radeonfb_pickres(dp, &dp->rd_virtx, &dp->rd_virty, 0); 740 1.8.2.2 yamt 741 1.8.2.2 yamt aprint_normal("%s: display %d: " 742 1.8.2.2 yamt "initial virtual resolution %dx%d at %d bpp\n", 743 1.8.2.2 yamt XNAME(sc), i, dp->rd_virtx, dp->rd_virty, dp->rd_bpp); 744 1.8.2.2 yamt 745 1.8.2.2 yamt /* now select the *video mode* that we will use */ 746 1.8.2.2 yamt for (j = 0; j < dp->rd_ncrtcs; j++) { 747 1.8.2.2 yamt const struct videomode *vmp; 748 1.8.2.3 yamt vmp = radeonfb_port_mode(sc, dp->rd_crtcs[j].rc_port, 749 1.8.2.2 yamt dp->rd_virtx, dp->rd_virty); 750 1.8.2.2 yamt 751 1.8.2.2 yamt /* 752 1.8.2.2 yamt * virtual resolution should be at least as high as 753 1.8.2.2 yamt * physical 754 1.8.2.2 yamt */ 755 1.8.2.2 yamt if (dp->rd_virtx < vmp->hdisplay || 756 1.8.2.2 yamt dp->rd_virty < vmp->vdisplay) { 757 1.8.2.2 yamt dp->rd_virtx = vmp->hdisplay; 758 1.8.2.2 yamt dp->rd_virty = vmp->vdisplay; 759 1.8.2.2 yamt } 760 1.8.2.2 yamt 761 1.8.2.2 yamt dp->rd_crtcs[j].rc_videomode = *vmp; 762 1.8.2.2 yamt printf("%s: port %d: physical %dx%d %dHz\n", 763 1.8.2.2 yamt XNAME(sc), j, vmp->hdisplay, vmp->vdisplay, 764 1.8.2.2 yamt DIVIDE(DIVIDE(vmp->dot_clock * 1000, 765 1.8.2.2 yamt vmp->htotal), vmp->vtotal)); 766 1.8.2.2 yamt } 767 1.8.2.2 yamt 768 1.8.2.2 yamt /* N.B.: radeon wants 64-byte aligned stride */ 769 1.8.2.2 yamt dp->rd_stride = dp->rd_virtx * dp->rd_bpp / 8; 770 1.8.2.2 yamt dp->rd_stride = ROUNDUP(dp->rd_stride, RADEON_STRIDEALIGN); 771 1.8.2.2 yamt 772 1.8.2.2 yamt dp->rd_offset = sc->sc_fboffset * i; 773 1.8.2.2 yamt dp->rd_fbptr = (vaddr_t)bus_space_vaddr(sc->sc_memt, 774 1.8.2.2 yamt sc->sc_memh) + dp->rd_offset; 775 1.8.2.2 yamt dp->rd_curoff = sc->sc_fbsize; 776 1.8.2.2 yamt dp->rd_curptr = dp->rd_fbptr + dp->rd_curoff; 777 1.8.2.2 yamt 778 1.8.2.2 yamt DPRINTF(("fpbtr = %p\n", (void *)dp->rd_fbptr)); 779 1.8.2.2 yamt 780 1.8.2.2 yamt switch (dp->rd_bpp) { 781 1.8.2.2 yamt case 8: 782 1.8.2.2 yamt dp->rd_format = 2; 783 1.8.2.2 yamt break; 784 1.8.2.2 yamt case 32: 785 1.8.2.2 yamt dp->rd_format = 6; 786 1.8.2.2 yamt break; 787 1.8.2.2 yamt default: 788 1.8.2.2 yamt aprint_error("%s: bad depth %d\n", XNAME(sc), 789 1.8.2.2 yamt dp->rd_bpp); 790 1.8.2.2 yamt goto error; 791 1.8.2.2 yamt } 792 1.8.2.2 yamt 793 1.8.2.2 yamt printf("init engine\n"); 794 1.8.2.2 yamt /* XXX: this seems suspicious - per display engine 795 1.8.2.2 yamt initialization? */ 796 1.8.2.2 yamt radeonfb_engine_init(dp); 797 1.8.2.2 yamt 798 1.8.2.2 yamt /* copy the template into place */ 799 1.8.2.2 yamt dp->rd_wsscreens_storage[0] = radeonfb_stdscreen; 800 1.8.2.2 yamt dp->rd_wsscreens = dp->rd_wsscreens_storage; 801 1.8.2.2 yamt 802 1.8.2.2 yamt /* and make up the list */ 803 1.8.2.2 yamt dp->rd_wsscreenlist.nscreens = 1; 804 1.8.2.2 yamt dp->rd_wsscreenlist.screens = 805 1.8.2.2 yamt (const struct wsscreen_descr **)&dp->rd_wsscreens; 806 1.8.2.2 yamt 807 1.8.2.2 yamt vcons_init(&dp->rd_vd, dp, dp->rd_wsscreens, 808 1.8.2.2 yamt &radeonfb_accessops); 809 1.8.2.2 yamt 810 1.8.2.2 yamt dp->rd_vd.init_screen = radeonfb_init_screen; 811 1.8.2.2 yamt 812 1.8.2.2 yamt dp->rd_console = 1; 813 1.8.2.2 yamt 814 1.8.2.2 yamt dp->rd_vscreen.scr_flags |= VCONS_SCREEN_IS_STATIC; 815 1.8.2.2 yamt 816 1.8.2.2 yamt 817 1.8.2.2 yamt vcons_init_screen(&dp->rd_vd, &dp->rd_vscreen, 818 1.8.2.2 yamt dp->rd_console, &defattr); 819 1.8.2.2 yamt 820 1.8.2.2 yamt ri = &dp->rd_vscreen.scr_ri; 821 1.8.2.2 yamt 822 1.8.2.2 yamt /* clear the screen */ 823 1.8.2.2 yamt rasops_unpack_attr(defattr, &fg, &bg, &ul); 824 1.8.2.2 yamt radeonfb_rectfill(dp, 0, 0, ri->ri_width, ri->ri_height, 825 1.8.2.2 yamt ri->ri_devcmap[bg & 0xf]); 826 1.8.2.2 yamt 827 1.8.2.2 yamt dp->rd_wsscreens->textops = &ri->ri_ops; 828 1.8.2.2 yamt dp->rd_wsscreens->capabilities = ri->ri_caps; 829 1.8.2.2 yamt dp->rd_wsscreens->nrows = ri->ri_rows; 830 1.8.2.2 yamt dp->rd_wsscreens->ncols = ri->ri_cols; 831 1.8.2.2 yamt 832 1.8.2.2 yamt #ifdef SPLASHSCREEN 833 1.8.2.2 yamt dp->rd_splash.si_depth = ri->ri_depth; 834 1.8.2.2 yamt dp->rd_splash.si_bits = ri->ri_bits; 835 1.8.2.2 yamt dp->rd_splash.si_hwbits = ri->ri_hwbits; 836 1.8.2.2 yamt dp->rd_splash.si_width = ri->ri_width; 837 1.8.2.2 yamt dp->rd_splash.si_height = ri->ri_height; 838 1.8.2.2 yamt dp->rd_splash.si_stride = ri->ri_stride; 839 1.8.2.2 yamt dp->rd_splash.si_fillrect = NULL; 840 1.8.2.2 yamt #endif 841 1.8.2.2 yamt if (dp->rd_console) { 842 1.8.2.2 yamt 843 1.8.2.2 yamt wsdisplay_cnattach(dp->rd_wsscreens, ri, 0, 0, 844 1.8.2.2 yamt defattr); 845 1.8.2.2 yamt #ifdef SPLASHSCREEN 846 1.8.2.2 yamt splash_render(&dp->rd_splash, 847 1.8.2.2 yamt SPLASH_F_CENTER|SPLASH_F_FILL); 848 1.8.2.2 yamt #endif 849 1.8.2.2 yamt 850 1.8.2.2 yamt #ifdef SPLASHSCREEN_PROGRESS 851 1.8.2.2 yamt dp->rd_progress.sp_top = (dp->rd_virty / 8) * 7; 852 1.8.2.2 yamt dp->rd_progress.sp_width = (dp->rd_virtx / 4) * 3; 853 1.8.2.2 yamt dp->rd_progress.sp_left = (dp->rd_virtx - 854 1.8.2.2 yamt dp->rd_progress.sp_width) / 2; 855 1.8.2.2 yamt dp->rd_progress.sp_height = 20; 856 1.8.2.2 yamt dp->rd_progress.sp_state = -1; 857 1.8.2.2 yamt dp->rd_progress.sp_si = &dp->rd_splash; 858 1.8.2.2 yamt splash_progress_init(&dp->rd_progress); 859 1.8.2.2 yamt SCREEN_DISABLE_DRAWING(&dp->rd_vscreen); 860 1.8.2.2 yamt #endif 861 1.8.2.2 yamt 862 1.8.2.2 yamt } else { 863 1.8.2.2 yamt 864 1.8.2.2 yamt /* 865 1.8.2.2 yamt * since we're not the console we can postpone 866 1.8.2.2 yamt * the rest until someone actually allocates a 867 1.8.2.2 yamt * screen for us. but we do clear the screen 868 1.8.2.2 yamt * at least. 869 1.8.2.2 yamt */ 870 1.8.2.2 yamt memset(ri->ri_bits, 0, 1024); 871 1.8.2.2 yamt 872 1.8.2.2 yamt radeonfb_modeswitch(dp); 873 1.8.2.2 yamt #ifdef SPLASHSCREEN 874 1.8.2.2 yamt splash_render(&dp->rd_splash, 875 1.8.2.2 yamt SPLASH_F_CENTER|SPLASH_F_FILL); 876 1.8.2.2 yamt SCREEN_DISABLE_DRAWING(&dp->rd_vscreen); 877 1.8.2.2 yamt #endif 878 1.8.2.2 yamt } 879 1.8.2.2 yamt 880 1.8.2.2 yamt aa.console = dp->rd_console; 881 1.8.2.2 yamt aa.scrdata = &dp->rd_wsscreenlist; 882 1.8.2.2 yamt aa.accessops = &radeonfb_accessops; 883 1.8.2.2 yamt aa.accesscookie = &dp->rd_vd; 884 1.8.2.2 yamt 885 1.8.2.2 yamt config_found(&sc->sc_dev, &aa, wsemuldisplaydevprint); 886 1.8.2.2 yamt radeonfb_blank(dp, 0); 887 1.8.2.3 yamt 888 1.8.2.3 yamt /* Initialise delayed lvds operations for backlight. */ 889 1.8.2.4 yamt callout_init(&dp->rd_bl_lvds_co, 0); 890 1.8.2.3 yamt callout_setfunc(&dp->rd_bl_lvds_co, 891 1.8.2.3 yamt radeonfb_lvds_callout, dp); 892 1.8.2.2 yamt } 893 1.8.2.2 yamt 894 1.8.2.4 yamt config_found_ia(dev, "drm", aux, radeonfb_drm_print); 895 1.8.2.4 yamt 896 1.8.2.2 yamt return; 897 1.8.2.2 yamt 898 1.8.2.2 yamt error: 899 1.8.2.2 yamt if (sc->sc_biossz) 900 1.8.2.2 yamt free(sc->sc_bios, M_DEVBUF); 901 1.8.2.2 yamt 902 1.8.2.2 yamt if (sc->sc_regsz) 903 1.8.2.2 yamt bus_space_unmap(sc->sc_regt, sc->sc_regh, sc->sc_regsz); 904 1.8.2.2 yamt 905 1.8.2.2 yamt if (sc->sc_memsz) 906 1.8.2.2 yamt bus_space_unmap(sc->sc_memt, sc->sc_memh, sc->sc_memsz); 907 1.8.2.2 yamt } 908 1.8.2.2 yamt 909 1.8.2.4 yamt static int 910 1.8.2.4 yamt radeonfb_drm_print(void *aux, const char *pnp) 911 1.8.2.4 yamt { 912 1.8.2.4 yamt if (pnp) 913 1.8.2.4 yamt aprint_normal("direct rendering for %s", pnp); 914 1.8.2.4 yamt return (UNSUPP); 915 1.8.2.4 yamt } 916 1.8.2.4 yamt 917 1.8.2.2 yamt int 918 1.8.2.2 yamt radeonfb_ioctl(void *v, void *vs, 919 1.8.2.4 yamt unsigned long cmd, void *d, int flag, struct lwp *l) 920 1.8.2.2 yamt { 921 1.8.2.2 yamt struct vcons_data *vd; 922 1.8.2.2 yamt struct radeonfb_display *dp; 923 1.8.2.2 yamt struct radeonfb_softc *sc; 924 1.8.2.3 yamt struct wsdisplay_param *param; 925 1.8.2.2 yamt 926 1.8.2.2 yamt vd = (struct vcons_data *)v; 927 1.8.2.2 yamt dp = (struct radeonfb_display *)vd->cookie; 928 1.8.2.2 yamt sc = dp->rd_softc; 929 1.8.2.2 yamt 930 1.8.2.2 yamt switch (cmd) { 931 1.8.2.2 yamt case WSDISPLAYIO_GTYPE: 932 1.8.2.2 yamt *(unsigned *)d = WSDISPLAY_TYPE_PCIMISC; 933 1.8.2.2 yamt return 0; 934 1.8.2.2 yamt 935 1.8.2.2 yamt case WSDISPLAYIO_GINFO: 936 1.8.2.2 yamt if (vd->active != NULL) { 937 1.8.2.2 yamt struct wsdisplay_fbinfo *fb; 938 1.8.2.2 yamt fb = (struct wsdisplay_fbinfo *)d; 939 1.8.2.2 yamt fb->width = dp->rd_virtx; 940 1.8.2.2 yamt fb->height = dp->rd_virty; 941 1.8.2.2 yamt fb->depth = dp->rd_bpp; 942 1.8.2.2 yamt fb->cmsize = 256; 943 1.8.2.2 yamt return 0; 944 1.8.2.2 yamt } else 945 1.8.2.2 yamt return ENODEV; 946 1.8.2.2 yamt case WSDISPLAYIO_GVIDEO: 947 1.8.2.2 yamt if (radeonfb_isblank(dp)) 948 1.8.2.2 yamt *(unsigned *)d = WSDISPLAYIO_VIDEO_OFF; 949 1.8.2.2 yamt else 950 1.8.2.2 yamt *(unsigned *)d = WSDISPLAYIO_VIDEO_ON; 951 1.8.2.2 yamt return 0; 952 1.8.2.2 yamt 953 1.8.2.2 yamt case WSDISPLAYIO_SVIDEO: 954 1.8.2.2 yamt radeonfb_blank(dp, 955 1.8.2.2 yamt (*(unsigned int *)d == WSDISPLAYIO_VIDEO_OFF)); 956 1.8.2.2 yamt return 0; 957 1.8.2.2 yamt 958 1.8.2.2 yamt case WSDISPLAYIO_GETCMAP: 959 1.8.2.2 yamt #if 0 960 1.8.2.2 yamt if (dp->rd_bpp == 8) 961 1.8.2.2 yamt return radeonfb_getcmap(sc, 962 1.8.2.2 yamt (struct wsdisplay_cmap *)d); 963 1.8.2.2 yamt #endif 964 1.8.2.2 yamt return EINVAL; 965 1.8.2.2 yamt 966 1.8.2.2 yamt case WSDISPLAYIO_PUTCMAP: 967 1.8.2.2 yamt #if 0 968 1.8.2.2 yamt if (dp->rd_bpp == 8) 969 1.8.2.2 yamt return radeonfb_putcmap(sc, 970 1.8.2.2 yamt (struct wsdisplay_cmap *)d); 971 1.8.2.2 yamt #endif 972 1.8.2.2 yamt return EINVAL; 973 1.8.2.2 yamt 974 1.8.2.2 yamt case WSDISPLAYIO_LINEBYTES: 975 1.8.2.2 yamt *(unsigned *)d = dp->rd_stride; 976 1.8.2.2 yamt return 0; 977 1.8.2.2 yamt 978 1.8.2.2 yamt case WSDISPLAYIO_SMODE: 979 1.8.2.2 yamt if (*(int *)d != dp->rd_wsmode) { 980 1.8.2.2 yamt dp->rd_wsmode = *(int *)d; 981 1.8.2.2 yamt if ((dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) && 982 1.8.2.2 yamt (dp->rd_vd.active)) { 983 1.8.2.4 yamt radeonfb_engine_init(dp); 984 1.8.2.4 yamt radeonfb_modeswitch(dp); 985 1.8.2.2 yamt vcons_redraw_screen(dp->rd_vd.active); 986 1.8.2.2 yamt } 987 1.8.2.2 yamt } 988 1.8.2.2 yamt return 0; 989 1.8.2.2 yamt 990 1.8.2.2 yamt case WSDISPLAYIO_GCURMAX: 991 1.8.2.2 yamt ((struct wsdisplay_curpos *)d)->x = RADEON_CURSORMAXX; 992 1.8.2.2 yamt ((struct wsdisplay_curpos *)d)->y = RADEON_CURSORMAXY; 993 1.8.2.2 yamt return 0; 994 1.8.2.2 yamt 995 1.8.2.2 yamt case WSDISPLAYIO_SCURSOR: 996 1.8.2.2 yamt return radeonfb_set_cursor(dp, (struct wsdisplay_cursor *)d); 997 1.8.2.2 yamt 998 1.8.2.2 yamt case WSDISPLAYIO_GCURSOR: 999 1.8.2.2 yamt return EPASSTHROUGH; 1000 1.8.2.2 yamt 1001 1.8.2.2 yamt case WSDISPLAYIO_GCURPOS: 1002 1.8.2.2 yamt ((struct wsdisplay_curpos *)d)->x = dp->rd_cursor.rc_pos.x; 1003 1.8.2.2 yamt ((struct wsdisplay_curpos *)d)->y = dp->rd_cursor.rc_pos.y; 1004 1.8.2.2 yamt return 0; 1005 1.8.2.2 yamt 1006 1.8.2.2 yamt case WSDISPLAYIO_SCURPOS: 1007 1.8.2.2 yamt return radeonfb_set_curpos(dp, (struct wsdisplay_curpos *)d); 1008 1.8.2.2 yamt 1009 1.8.2.2 yamt case WSDISPLAYIO_SSPLASH: 1010 1.8.2.2 yamt #if defined(SPLASHSCREEN) 1011 1.8.2.2 yamt if (*(int *)d == 1) { 1012 1.8.2.2 yamt SCREEN_DISABLE_DRAWING(&dp->rd_vscreen); 1013 1.8.2.2 yamt splash_render(&dp->rd_splash, 1014 1.8.2.2 yamt SPLASH_F_CENTER|SPLASH_F_FILL); 1015 1.8.2.2 yamt } else 1016 1.8.2.2 yamt SCREEN_ENABLE_DRAWING(&dp->rd_vscreen); 1017 1.8.2.2 yamt return 0; 1018 1.8.2.2 yamt #else 1019 1.8.2.2 yamt return ENODEV; 1020 1.8.2.2 yamt #endif 1021 1.8.2.2 yamt case WSDISPLAYIO_SPROGRESS: 1022 1.8.2.2 yamt #if defined(SPLASHSCREEN) && defined(SPLASHSCREEN_PROGRESS) 1023 1.8.2.2 yamt dp->rd_progress.sp_force = 1; 1024 1.8.2.2 yamt splash_progress_update(&dp->rd_progress); 1025 1.8.2.2 yamt dp->rd_progress.sp_force = 0; 1026 1.8.2.2 yamt return 0; 1027 1.8.2.2 yamt #else 1028 1.8.2.2 yamt return ENODEV; 1029 1.8.2.2 yamt #endif 1030 1.8.2.3 yamt case WSDISPLAYIO_GETPARAM: 1031 1.8.2.3 yamt param = (struct wsdisplay_param *)d; 1032 1.8.2.3 yamt if (param->param == WSDISPLAYIO_PARAM_BACKLIGHT) { 1033 1.8.2.3 yamt param->min = 0; 1034 1.8.2.3 yamt param->max = RADEONFB_BACKLIGHT_MAX; 1035 1.8.2.3 yamt param->curval = radeonfb_get_backlight(dp); 1036 1.8.2.3 yamt return 0; 1037 1.8.2.3 yamt } 1038 1.8.2.3 yamt return EPASSTHROUGH; 1039 1.8.2.3 yamt 1040 1.8.2.3 yamt case WSDISPLAYIO_SETPARAM: 1041 1.8.2.3 yamt param = (struct wsdisplay_param *)d; 1042 1.8.2.3 yamt if (param->param == WSDISPLAYIO_PARAM_BACKLIGHT) { 1043 1.8.2.3 yamt return radeonfb_set_backlight(dp, param->curval); 1044 1.8.2.3 yamt } 1045 1.8.2.3 yamt return EPASSTHROUGH; 1046 1.8.2.2 yamt 1047 1.8.2.2 yamt default: 1048 1.8.2.2 yamt return EPASSTHROUGH; 1049 1.8.2.2 yamt } 1050 1.8.2.2 yamt } 1051 1.8.2.2 yamt 1052 1.8.2.2 yamt paddr_t 1053 1.8.2.2 yamt radeonfb_mmap(void *v, void *vs, off_t offset, int prot) 1054 1.8.2.2 yamt { 1055 1.8.2.2 yamt struct vcons_data *vd; 1056 1.8.2.2 yamt struct radeonfb_display *dp; 1057 1.8.2.2 yamt struct radeonfb_softc *sc; 1058 1.8.2.2 yamt #ifdef RADEONFB_MMAP_BARS 1059 1.8.2.2 yamt struct lwp *me; 1060 1.8.2.2 yamt #endif 1061 1.8.2.2 yamt paddr_t pa; 1062 1.8.2.2 yamt 1063 1.8.2.2 yamt vd = (struct vcons_data *)v; 1064 1.8.2.2 yamt dp = (struct radeonfb_display *)vd->cookie; 1065 1.8.2.2 yamt sc = dp->rd_softc; 1066 1.8.2.2 yamt 1067 1.8.2.2 yamt /* XXX: note that we don't allow mapping of registers right now */ 1068 1.8.2.2 yamt /* XXX: this means that the XFree86 radeon driver won't work */ 1069 1.8.2.2 yamt 1070 1.8.2.2 yamt if ((offset >= 0) && (offset < (dp->rd_virty * dp->rd_stride))) { 1071 1.8.2.2 yamt pa = bus_space_mmap(sc->sc_memt, 1072 1.8.2.2 yamt sc->sc_memaddr + dp->rd_offset + offset, 0, 1073 1.8.2.2 yamt prot, BUS_SPACE_MAP_LINEAR); 1074 1.8.2.2 yamt return pa; 1075 1.8.2.2 yamt } 1076 1.8.2.2 yamt 1077 1.8.2.2 yamt #ifdef RADEONFB_MMAP_BARS 1078 1.8.2.2 yamt /* 1079 1.8.2.2 yamt * restrict all other mappings to processes with superuser privileges 1080 1.8.2.2 yamt * or the kernel itself 1081 1.8.2.2 yamt */ 1082 1.8.2.2 yamt me = curlwp; 1083 1.8.2.2 yamt if (me != NULL) { 1084 1.8.2.2 yamt if (kauth_authorize_generic(me->l_cred, KAUTH_GENERIC_ISSUSER, 1085 1.8.2.2 yamt NULL) != 0) { 1086 1.8.2.2 yamt printf("%s: mmap() rejected.\n", sc->sc_dev.dv_xname); 1087 1.8.2.2 yamt return -1; 1088 1.8.2.2 yamt } 1089 1.8.2.2 yamt } 1090 1.8.2.2 yamt 1091 1.8.2.2 yamt if ((offset >= sc->sc_regaddr) && 1092 1.8.2.2 yamt (offset < sc->sc_regaddr + sc->sc_regsz)) { 1093 1.8.2.2 yamt return bus_space_mmap(sc->sc_regt, offset, 0, prot, 1094 1.8.2.2 yamt BUS_SPACE_MAP_LINEAR); 1095 1.8.2.2 yamt } 1096 1.8.2.2 yamt 1097 1.8.2.2 yamt if ((offset >= sc->sc_memaddr) && 1098 1.8.2.2 yamt (offset < sc->sc_memaddr + sc->sc_memsz)) { 1099 1.8.2.2 yamt return bus_space_mmap(sc->sc_memt, offset, 0, prot, 1100 1.8.2.2 yamt BUS_SPACE_MAP_LINEAR); 1101 1.8.2.2 yamt } 1102 1.8.2.2 yamt 1103 1.8.2.2 yamt #ifdef macppc 1104 1.8.2.2 yamt /* allow mapping of IO space */ 1105 1.8.2.2 yamt if ((offset >= 0xf2000000) && (offset < 0xf2800000)) { 1106 1.8.2.4 yamt pa = bus_space_mmap(sc->sc_iot, offset - 0xf2000000, 0, prot, 1107 1.8.2.4 yamt 0); 1108 1.8.2.2 yamt return pa; 1109 1.8.2.2 yamt } 1110 1.8.2.2 yamt #endif /* macppc */ 1111 1.8.2.2 yamt 1112 1.8.2.2 yamt #endif /* RADEONFB_MMAP_BARS */ 1113 1.8.2.2 yamt 1114 1.8.2.2 yamt return -1; 1115 1.8.2.2 yamt } 1116 1.8.2.2 yamt 1117 1.8.2.2 yamt static void 1118 1.8.2.2 yamt radeonfb_loadbios(struct radeonfb_softc *sc, struct pci_attach_args *pa) 1119 1.8.2.2 yamt { 1120 1.8.2.2 yamt bus_space_tag_t romt; 1121 1.8.2.2 yamt bus_space_handle_t romh, biosh; 1122 1.8.2.2 yamt bus_size_t romsz; 1123 1.8.2.2 yamt bus_addr_t ptr; 1124 1.8.2.2 yamt 1125 1.8.2.2 yamt if (pci_mapreg_map(pa, PCI_MAPREG_ROM, PCI_MAPREG_TYPE_ROM, 1126 1.8.2.2 yamt BUS_SPACE_MAP_PREFETCHABLE, &romt, &romh, NULL, &romsz) != 0) { 1127 1.8.2.2 yamt aprint_verbose("%s: unable to map BIOS!\n", XNAME(sc)); 1128 1.8.2.2 yamt return; 1129 1.8.2.2 yamt } 1130 1.8.2.2 yamt 1131 1.8.2.2 yamt pci_find_rom(pa, romt, romh, PCI_ROM_CODE_TYPE_X86, &biosh, 1132 1.8.2.2 yamt &sc->sc_biossz); 1133 1.8.2.2 yamt if (sc->sc_biossz == 0) { 1134 1.8.2.2 yamt aprint_verbose("%s: Video BIOS not present\n", XNAME(sc)); 1135 1.8.2.2 yamt return; 1136 1.8.2.2 yamt } 1137 1.8.2.2 yamt 1138 1.8.2.2 yamt sc->sc_bios = malloc(sc->sc_biossz, M_DEVBUF, M_WAITOK); 1139 1.8.2.2 yamt bus_space_read_region_1(romt, biosh, 0, sc->sc_bios, sc->sc_biossz); 1140 1.8.2.2 yamt 1141 1.8.2.2 yamt /* unmap the PCI expansion rom */ 1142 1.8.2.2 yamt bus_space_unmap(romt, romh, romsz); 1143 1.8.2.2 yamt 1144 1.8.2.2 yamt /* turn off rom decoder now */ 1145 1.8.2.2 yamt pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM, 1146 1.8.2.2 yamt pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM) & 1147 1.8.2.2 yamt ~PCI_MAPREG_ROM_ENABLE); 1148 1.8.2.2 yamt 1149 1.8.2.2 yamt ptr = GETBIOS16(sc, 0x48); 1150 1.8.2.2 yamt if ((GETBIOS32(sc, ptr + 4) == 0x41544f4d /* "ATOM" */) || 1151 1.8.2.2 yamt (GETBIOS32(sc, ptr + 4) == 0x4d4f5441 /* "MOTA" */)) { 1152 1.8.2.2 yamt sc->sc_flags |= RFB_ATOM; 1153 1.8.2.2 yamt } 1154 1.8.2.2 yamt 1155 1.8.2.2 yamt aprint_verbose("%s: Found %d KB %s BIOS\n", XNAME(sc), 1156 1.8.2.2 yamt (unsigned)sc->sc_biossz >> 10, IS_ATOM(sc) ? "ATOM" : "Legacy"); 1157 1.8.2.2 yamt } 1158 1.8.2.2 yamt 1159 1.8.2.2 yamt 1160 1.8.2.2 yamt uint32_t 1161 1.8.2.2 yamt radeonfb_get32(struct radeonfb_softc *sc, uint32_t reg) 1162 1.8.2.2 yamt { 1163 1.8.2.2 yamt 1164 1.8.2.2 yamt return bus_space_read_4(sc->sc_regt, sc->sc_regh, reg); 1165 1.8.2.2 yamt } 1166 1.8.2.2 yamt 1167 1.8.2.2 yamt void 1168 1.8.2.2 yamt radeonfb_put32(struct radeonfb_softc *sc, uint32_t reg, uint32_t val) 1169 1.8.2.2 yamt { 1170 1.8.2.2 yamt 1171 1.8.2.2 yamt bus_space_write_4(sc->sc_regt, sc->sc_regh, reg, val); 1172 1.8.2.2 yamt } 1173 1.8.2.2 yamt 1174 1.8.2.2 yamt void 1175 1.8.2.2 yamt radeonfb_mask32(struct radeonfb_softc *sc, uint32_t reg, 1176 1.8.2.2 yamt uint32_t andmask, uint32_t ormask) 1177 1.8.2.2 yamt { 1178 1.8.2.2 yamt int s; 1179 1.8.2.2 yamt uint32_t val; 1180 1.8.2.2 yamt 1181 1.8.2.2 yamt s = splhigh(); 1182 1.8.2.2 yamt val = radeonfb_get32(sc, reg); 1183 1.8.2.2 yamt val = (val & andmask) | ormask; 1184 1.8.2.2 yamt radeonfb_put32(sc, reg, val); 1185 1.8.2.2 yamt splx(s); 1186 1.8.2.2 yamt } 1187 1.8.2.2 yamt 1188 1.8.2.2 yamt uint32_t 1189 1.8.2.2 yamt radeonfb_getindex(struct radeonfb_softc *sc, uint32_t idx) 1190 1.8.2.2 yamt { 1191 1.8.2.2 yamt int s; 1192 1.8.2.2 yamt uint32_t val; 1193 1.8.2.2 yamt 1194 1.8.2.2 yamt s = splhigh(); 1195 1.8.2.2 yamt radeonfb_put32(sc, RADEON_MM_INDEX, idx); 1196 1.8.2.2 yamt val = radeonfb_get32(sc, RADEON_MM_DATA); 1197 1.8.2.2 yamt splx(s); 1198 1.8.2.2 yamt 1199 1.8.2.2 yamt return (val); 1200 1.8.2.2 yamt } 1201 1.8.2.2 yamt 1202 1.8.2.2 yamt void 1203 1.8.2.2 yamt radeonfb_putindex(struct radeonfb_softc *sc, uint32_t idx, uint32_t val) 1204 1.8.2.2 yamt { 1205 1.8.2.2 yamt int s; 1206 1.8.2.2 yamt 1207 1.8.2.2 yamt s = splhigh(); 1208 1.8.2.2 yamt radeonfb_put32(sc, RADEON_MM_INDEX, idx); 1209 1.8.2.2 yamt radeonfb_put32(sc, RADEON_MM_DATA, val); 1210 1.8.2.2 yamt splx(s); 1211 1.8.2.2 yamt } 1212 1.8.2.2 yamt 1213 1.8.2.2 yamt void 1214 1.8.2.2 yamt radeonfb_maskindex(struct radeonfb_softc *sc, uint32_t idx, 1215 1.8.2.2 yamt uint32_t andmask, uint32_t ormask) 1216 1.8.2.2 yamt { 1217 1.8.2.2 yamt int s; 1218 1.8.2.2 yamt uint32_t val; 1219 1.8.2.2 yamt 1220 1.8.2.2 yamt s = splhigh(); 1221 1.8.2.2 yamt radeonfb_put32(sc, RADEON_MM_INDEX, idx); 1222 1.8.2.2 yamt val = radeonfb_get32(sc, RADEON_MM_DATA); 1223 1.8.2.2 yamt val = (val & andmask) | ormask; 1224 1.8.2.2 yamt radeonfb_put32(sc, RADEON_MM_DATA, val); 1225 1.8.2.2 yamt splx(s); 1226 1.8.2.2 yamt } 1227 1.8.2.2 yamt 1228 1.8.2.2 yamt uint32_t 1229 1.8.2.2 yamt radeonfb_getpll(struct radeonfb_softc *sc, uint32_t idx) 1230 1.8.2.2 yamt { 1231 1.8.2.2 yamt int s; 1232 1.8.2.2 yamt uint32_t val; 1233 1.8.2.2 yamt 1234 1.8.2.2 yamt s = splhigh(); 1235 1.8.2.2 yamt radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, idx & 0x3f); 1236 1.8.2.2 yamt val = radeonfb_get32(sc, RADEON_CLOCK_CNTL_DATA); 1237 1.8.2.2 yamt if (HAS_R300CG(sc)) 1238 1.8.2.2 yamt radeonfb_r300cg_workaround(sc); 1239 1.8.2.2 yamt splx(s); 1240 1.8.2.2 yamt 1241 1.8.2.2 yamt return (val); 1242 1.8.2.2 yamt } 1243 1.8.2.2 yamt 1244 1.8.2.2 yamt void 1245 1.8.2.2 yamt radeonfb_putpll(struct radeonfb_softc *sc, uint32_t idx, uint32_t val) 1246 1.8.2.2 yamt { 1247 1.8.2.2 yamt int s; 1248 1.8.2.2 yamt 1249 1.8.2.2 yamt s = splhigh(); 1250 1.8.2.2 yamt radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, (idx & 0x3f) | 1251 1.8.2.2 yamt RADEON_PLL_WR_EN); 1252 1.8.2.2 yamt radeonfb_put32(sc, RADEON_CLOCK_CNTL_DATA, val); 1253 1.8.2.2 yamt radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, 0); 1254 1.8.2.2 yamt splx(s); 1255 1.8.2.2 yamt } 1256 1.8.2.2 yamt 1257 1.8.2.2 yamt void 1258 1.8.2.2 yamt radeonfb_maskpll(struct radeonfb_softc *sc, uint32_t idx, 1259 1.8.2.2 yamt uint32_t andmask, uint32_t ormask) 1260 1.8.2.2 yamt { 1261 1.8.2.2 yamt int s; 1262 1.8.2.2 yamt uint32_t val; 1263 1.8.2.2 yamt 1264 1.8.2.2 yamt s = splhigh(); 1265 1.8.2.2 yamt radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, (idx & 0x3f) | 1266 1.8.2.2 yamt RADEON_PLL_WR_EN); 1267 1.8.2.2 yamt val = radeonfb_get32(sc, RADEON_CLOCK_CNTL_DATA); 1268 1.8.2.2 yamt val = (val & andmask) | ormask; 1269 1.8.2.2 yamt radeonfb_put32(sc, RADEON_CLOCK_CNTL_DATA, val); 1270 1.8.2.2 yamt radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, 0); 1271 1.8.2.2 yamt splx(s); 1272 1.8.2.2 yamt } 1273 1.8.2.2 yamt 1274 1.8.2.2 yamt int 1275 1.8.2.2 yamt radeonfb_scratch_test(struct radeonfb_softc *sc, int reg, uint32_t v) 1276 1.8.2.2 yamt { 1277 1.8.2.2 yamt uint32_t saved; 1278 1.8.2.2 yamt 1279 1.8.2.2 yamt saved = GET32(sc, reg); 1280 1.8.2.2 yamt PUT32(sc, reg, v); 1281 1.8.2.2 yamt if (GET32(sc, reg) != v) { 1282 1.8.2.2 yamt return -1; 1283 1.8.2.2 yamt } 1284 1.8.2.2 yamt PUT32(sc, reg, saved); 1285 1.8.2.2 yamt return 0; 1286 1.8.2.2 yamt } 1287 1.8.2.2 yamt 1288 1.8.2.2 yamt uintmax_t 1289 1.8.2.2 yamt radeonfb_getprop_num(struct radeonfb_softc *sc, const char *name, 1290 1.8.2.2 yamt uintmax_t defval) 1291 1.8.2.2 yamt { 1292 1.8.2.2 yamt prop_number_t pn; 1293 1.8.2.2 yamt pn = prop_dictionary_get(device_properties(&sc->sc_dev), name); 1294 1.8.2.2 yamt if (pn == NULL) { 1295 1.8.2.2 yamt return defval; 1296 1.8.2.2 yamt } 1297 1.8.2.2 yamt KASSERT(prop_object_type(pn) == PROP_TYPE_NUMBER); 1298 1.8.2.2 yamt return (prop_number_integer_value(pn)); 1299 1.8.2.2 yamt } 1300 1.8.2.2 yamt 1301 1.8.2.2 yamt int 1302 1.8.2.2 yamt radeonfb_getclocks(struct radeonfb_softc *sc) 1303 1.8.2.2 yamt { 1304 1.8.2.2 yamt bus_addr_t ptr; 1305 1.8.2.2 yamt int refclk = 0; 1306 1.8.2.2 yamt int refdiv = 0; 1307 1.8.2.2 yamt int minpll = 0; 1308 1.8.2.2 yamt int maxpll = 0; 1309 1.8.2.2 yamt 1310 1.8.2.2 yamt /* load initial property values if port/board provides them */ 1311 1.8.2.2 yamt refclk = radeonfb_getprop_num(sc, "refclk", 0) & 0xffff; 1312 1.8.2.2 yamt refdiv = radeonfb_getprop_num(sc, "refdiv", 0) & 0xffff; 1313 1.8.2.2 yamt minpll = radeonfb_getprop_num(sc, "minpll", 0) & 0xffffffffU; 1314 1.8.2.2 yamt maxpll = radeonfb_getprop_num(sc, "maxpll", 0) & 0xffffffffU; 1315 1.8.2.2 yamt 1316 1.8.2.2 yamt if (refclk && refdiv && minpll && maxpll) 1317 1.8.2.2 yamt goto dontprobe; 1318 1.8.2.2 yamt 1319 1.8.2.2 yamt if (!sc->sc_biossz) { 1320 1.8.2.2 yamt /* no BIOS */ 1321 1.8.2.2 yamt aprint_verbose("%s: No video BIOS, using default clocks\n", 1322 1.8.2.2 yamt XNAME(sc)); 1323 1.8.2.2 yamt if (IS_IGP(sc)) 1324 1.8.2.2 yamt refclk = refclk ? refclk : 1432; 1325 1.8.2.2 yamt else 1326 1.8.2.2 yamt refclk = refclk ? refclk : 2700; 1327 1.8.2.2 yamt refdiv = refdiv ? refdiv : 12; 1328 1.8.2.2 yamt minpll = minpll ? minpll : 12500; 1329 1.8.2.2 yamt maxpll = maxpll ? maxpll : 35000; 1330 1.8.2.2 yamt } else if (IS_ATOM(sc)) { 1331 1.8.2.2 yamt /* ATOM BIOS */ 1332 1.8.2.2 yamt ptr = GETBIOS16(sc, 0x48); 1333 1.8.2.2 yamt ptr = GETBIOS16(sc, ptr + 32); /* aka MasterDataStart */ 1334 1.8.2.2 yamt ptr = GETBIOS16(sc, ptr + 12); /* pll info block */ 1335 1.8.2.2 yamt refclk = refclk ? refclk : GETBIOS16(sc, ptr + 82); 1336 1.8.2.2 yamt minpll = minpll ? minpll : GETBIOS16(sc, ptr + 78); 1337 1.8.2.2 yamt maxpll = maxpll ? maxpll : GETBIOS16(sc, ptr + 32); 1338 1.8.2.2 yamt /* 1339 1.8.2.2 yamt * ATOM BIOS doesn't supply a reference divider, so we 1340 1.8.2.2 yamt * have to probe for it. 1341 1.8.2.2 yamt */ 1342 1.8.2.2 yamt if (refdiv < 2) 1343 1.8.2.2 yamt refdiv = GETPLL(sc, RADEON_PPLL_REF_DIV) & 1344 1.8.2.2 yamt RADEON_PPLL_REF_DIV_MASK; 1345 1.8.2.2 yamt /* 1346 1.8.2.2 yamt * if probe is zero, just assume one that should work 1347 1.8.2.2 yamt * for most parts 1348 1.8.2.2 yamt */ 1349 1.8.2.2 yamt if (refdiv < 2) 1350 1.8.2.2 yamt refdiv = 12; 1351 1.8.2.2 yamt 1352 1.8.2.2 yamt } else { 1353 1.8.2.2 yamt /* Legacy BIOS */ 1354 1.8.2.2 yamt ptr = GETBIOS16(sc, 0x48); 1355 1.8.2.2 yamt ptr = GETBIOS16(sc, ptr + 0x30); 1356 1.8.2.2 yamt refclk = refclk ? refclk : GETBIOS16(sc, ptr + 0x0E); 1357 1.8.2.2 yamt refdiv = refdiv ? refdiv : GETBIOS16(sc, ptr + 0x10); 1358 1.8.2.2 yamt minpll = minpll ? minpll : GETBIOS32(sc, ptr + 0x12); 1359 1.8.2.2 yamt maxpll = maxpll ? maxpll : GETBIOS32(sc, ptr + 0x16); 1360 1.8.2.2 yamt } 1361 1.8.2.2 yamt 1362 1.8.2.2 yamt 1363 1.8.2.2 yamt dontprobe: 1364 1.8.2.2 yamt sc->sc_refclk = refclk * 10; 1365 1.8.2.2 yamt sc->sc_refdiv = refdiv; 1366 1.8.2.2 yamt sc->sc_minpll = minpll * 10; 1367 1.8.2.2 yamt sc->sc_maxpll = maxpll * 10; 1368 1.8.2.2 yamt return 0; 1369 1.8.2.2 yamt } 1370 1.8.2.2 yamt 1371 1.8.2.2 yamt int 1372 1.8.2.2 yamt radeonfb_calc_dividers(struct radeonfb_softc *sc, uint32_t dotclock, 1373 1.8.2.2 yamt uint32_t *postdivbit, uint32_t *feedbackdiv) 1374 1.8.2.2 yamt { 1375 1.8.2.2 yamt int i; 1376 1.8.2.2 yamt uint32_t outfreq; 1377 1.8.2.2 yamt int div; 1378 1.8.2.2 yamt 1379 1.8.2.2 yamt DPRINTF(("dot clock: %u\n", dotclock)); 1380 1.8.2.2 yamt for (i = 0; (div = radeonfb_dividers[i].divider) != 0; i++) { 1381 1.8.2.2 yamt outfreq = div * dotclock; 1382 1.8.2.2 yamt if ((outfreq >= sc->sc_minpll) && 1383 1.8.2.2 yamt (outfreq <= sc->sc_maxpll)) { 1384 1.8.2.2 yamt DPRINTF(("outfreq: %u\n", outfreq)); 1385 1.8.2.2 yamt *postdivbit = 1386 1.8.2.2 yamt ((uint32_t)radeonfb_dividers[i].mask << 16); 1387 1.8.2.2 yamt DPRINTF(("post divider: %d (mask %x)\n", div, 1388 1.8.2.2 yamt *postdivbit)); 1389 1.8.2.2 yamt break; 1390 1.8.2.2 yamt } 1391 1.8.2.2 yamt } 1392 1.8.2.2 yamt 1393 1.8.2.2 yamt if (div == 0) 1394 1.8.2.2 yamt return 1; 1395 1.8.2.2 yamt 1396 1.8.2.2 yamt *feedbackdiv = DIVIDE(sc->sc_refdiv * outfreq, sc->sc_refclk); 1397 1.8.2.2 yamt DPRINTF(("feedback divider: %d\n", *feedbackdiv)); 1398 1.8.2.2 yamt return 0; 1399 1.8.2.2 yamt } 1400 1.8.2.2 yamt 1401 1.8.2.2 yamt #if 0 1402 1.8.2.2 yamt #ifdef RADEON_DEBUG 1403 1.8.2.2 yamt static void 1404 1.8.2.2 yamt dump_buffer(const char *pfx, void *buffer, unsigned int size) 1405 1.8.2.2 yamt { 1406 1.8.2.2 yamt char asc[17]; 1407 1.8.2.2 yamt unsigned ptr = (unsigned)buffer; 1408 1.8.2.2 yamt char *start = (char *)(ptr & ~0xf); 1409 1.8.2.2 yamt char *end = (char *)(ptr + size); 1410 1.8.2.2 yamt 1411 1.8.2.2 yamt end = (char *)(((unsigned)end + 0xf) & ~0xf); 1412 1.8.2.2 yamt 1413 1.8.2.2 yamt if (pfx == NULL) { 1414 1.8.2.2 yamt pfx = ""; 1415 1.8.2.2 yamt } 1416 1.8.2.2 yamt 1417 1.8.2.2 yamt while (start < end) { 1418 1.8.2.2 yamt unsigned offset = (unsigned)start & 0xf; 1419 1.8.2.2 yamt if (offset == 0) { 1420 1.8.2.2 yamt printf("%s%x: ", pfx, (unsigned)start); 1421 1.8.2.2 yamt } 1422 1.8.2.2 yamt if (((unsigned)start < ptr) || 1423 1.8.2.2 yamt ((unsigned)start >= (ptr + size))) { 1424 1.8.2.2 yamt printf(" "); 1425 1.8.2.2 yamt asc[offset] = ' '; 1426 1.8.2.2 yamt } else { 1427 1.8.2.2 yamt printf("%02x", *(unsigned char *)start); 1428 1.8.2.2 yamt if ((*start >= ' ') && (*start <= '~')) { 1429 1.8.2.2 yamt asc[offset] = *start; 1430 1.8.2.2 yamt } else { 1431 1.8.2.2 yamt asc[offset] = '.'; 1432 1.8.2.2 yamt } 1433 1.8.2.2 yamt } 1434 1.8.2.2 yamt asc[offset + 1] = 0; 1435 1.8.2.2 yamt if (offset % 2) { 1436 1.8.2.2 yamt printf(" "); 1437 1.8.2.2 yamt } 1438 1.8.2.2 yamt if (offset == 15) { 1439 1.8.2.2 yamt printf(" %s\n", asc); 1440 1.8.2.2 yamt } 1441 1.8.2.2 yamt start++; 1442 1.8.2.2 yamt } 1443 1.8.2.2 yamt } 1444 1.8.2.2 yamt #endif 1445 1.8.2.2 yamt #endif 1446 1.8.2.2 yamt 1447 1.8.2.2 yamt int 1448 1.8.2.2 yamt radeonfb_getconnectors(struct radeonfb_softc *sc) 1449 1.8.2.2 yamt { 1450 1.8.2.2 yamt int i; 1451 1.8.2.2 yamt int found = 0; 1452 1.8.2.2 yamt 1453 1.8.2.2 yamt for (i = 0; i < 2; i++) { 1454 1.8.2.2 yamt sc->sc_ports[i].rp_mon_type = RADEON_MT_UNKNOWN; 1455 1.8.2.2 yamt sc->sc_ports[i].rp_ddc_type = RADEON_DDC_NONE; 1456 1.8.2.2 yamt sc->sc_ports[i].rp_dac_type = RADEON_DAC_UNKNOWN; 1457 1.8.2.2 yamt sc->sc_ports[i].rp_conn_type = RADEON_CONN_NONE; 1458 1.8.2.2 yamt sc->sc_ports[i].rp_tmds_type = RADEON_TMDS_UNKNOWN; 1459 1.8.2.2 yamt } 1460 1.8.2.2 yamt 1461 1.8.2.2 yamt /* 1462 1.8.2.2 yamt * This logic is borrowed from Xorg's radeon driver. 1463 1.8.2.2 yamt */ 1464 1.8.2.2 yamt if (!sc->sc_biossz) 1465 1.8.2.2 yamt goto nobios; 1466 1.8.2.2 yamt 1467 1.8.2.2 yamt if (IS_ATOM(sc)) { 1468 1.8.2.2 yamt /* not done yet */ 1469 1.8.2.2 yamt } else { 1470 1.8.2.2 yamt uint16_t ptr; 1471 1.8.2.2 yamt int port = 0; 1472 1.8.2.2 yamt 1473 1.8.2.2 yamt ptr = GETBIOS16(sc, 0x48); 1474 1.8.2.2 yamt ptr = GETBIOS16(sc, ptr + 0x50); 1475 1.8.2.2 yamt for (i = 1; i < 4; i++) { 1476 1.8.2.2 yamt uint16_t entry; 1477 1.8.2.2 yamt uint8_t conn, ddc, dac, tmds; 1478 1.8.2.2 yamt 1479 1.8.2.2 yamt /* 1480 1.8.2.2 yamt * Parse the connector table. From reading the code, 1481 1.8.2.2 yamt * it appears to made up of 16-bit entries for each 1482 1.8.2.2 yamt * connector. The 16-bits are defined as: 1483 1.8.2.2 yamt * 1484 1.8.2.2 yamt * bits 12-15 - connector type (0 == end of table) 1485 1.8.2.2 yamt * bits 8-11 - DDC type 1486 1.8.2.2 yamt * bits 5-7 - ??? 1487 1.8.2.2 yamt * bit 4 - TMDS type (1 = EXT, 0 = INT) 1488 1.8.2.2 yamt * bits 1-3 - ??? 1489 1.8.2.2 yamt * bit 0 - DAC, 1 = TVDAC, 0 = primary 1490 1.8.2.2 yamt */ 1491 1.8.2.2 yamt if (!GETBIOS8(sc, ptr + i * 2) && i > 1) 1492 1.8.2.2 yamt break; 1493 1.8.2.2 yamt entry = GETBIOS16(sc, ptr + i * 2); 1494 1.8.2.2 yamt 1495 1.8.2.2 yamt conn = (entry >> 12) & 0xf; 1496 1.8.2.2 yamt ddc = (entry >> 8) & 0xf; 1497 1.8.2.2 yamt dac = (entry & 0x1) ? RADEON_DAC_TVDAC : 1498 1.8.2.2 yamt RADEON_DAC_PRIMARY; 1499 1.8.2.2 yamt tmds = ((entry >> 4) & 0x1) ? RADEON_TMDS_EXT : 1500 1.8.2.2 yamt RADEON_TMDS_INT; 1501 1.8.2.2 yamt 1502 1.8.2.2 yamt if (conn == RADEON_CONN_NONE) 1503 1.8.2.2 yamt continue; /* no connector */ 1504 1.8.2.2 yamt 1505 1.8.2.2 yamt if ((found > 0) && 1506 1.8.2.2 yamt (sc->sc_ports[port].rp_ddc_type == ddc)) { 1507 1.8.2.2 yamt /* duplicate entry for same connector */ 1508 1.8.2.2 yamt continue; 1509 1.8.2.2 yamt } 1510 1.8.2.2 yamt 1511 1.8.2.2 yamt /* internal DDC_DVI port gets priority */ 1512 1.8.2.2 yamt if ((ddc == RADEON_DDC_DVI) || (port == 1)) 1513 1.8.2.2 yamt port = 0; 1514 1.8.2.2 yamt else 1515 1.8.2.2 yamt port = 1; 1516 1.8.2.2 yamt 1517 1.8.2.2 yamt sc->sc_ports[port].rp_ddc_type = 1518 1.8.2.2 yamt ddc > RADEON_DDC_CRT2 ? RADEON_DDC_NONE : ddc; 1519 1.8.2.2 yamt sc->sc_ports[port].rp_dac_type = dac; 1520 1.8.2.2 yamt sc->sc_ports[port].rp_conn_type = 1521 1.8.2.2 yamt min(conn, RADEON_CONN_UNSUPPORTED) ; 1522 1.8.2.2 yamt 1523 1.8.2.2 yamt sc->sc_ports[port].rp_tmds_type = tmds; 1524 1.8.2.2 yamt 1525 1.8.2.2 yamt if ((conn != RADEON_CONN_DVI_I) && 1526 1.8.2.2 yamt (conn != RADEON_CONN_DVI_D) && 1527 1.8.2.2 yamt (tmds == RADEON_TMDS_INT)) 1528 1.8.2.2 yamt sc->sc_ports[port].rp_tmds_type = 1529 1.8.2.2 yamt RADEON_TMDS_UNKNOWN; 1530 1.8.2.2 yamt 1531 1.8.2.2 yamt found += (port + 1); 1532 1.8.2.2 yamt } 1533 1.8.2.2 yamt } 1534 1.8.2.2 yamt 1535 1.8.2.2 yamt nobios: 1536 1.8.2.2 yamt if (!found) { 1537 1.8.2.2 yamt DPRINTF(("No connector info in BIOS!\n")); 1538 1.8.2.2 yamt /* default, port 0 = internal TMDS, port 1 = CRT */ 1539 1.8.2.2 yamt sc->sc_ports[0].rp_mon_type = RADEON_MT_UNKNOWN; 1540 1.8.2.2 yamt sc->sc_ports[0].rp_ddc_type = RADEON_DDC_DVI; 1541 1.8.2.2 yamt sc->sc_ports[0].rp_dac_type = RADEON_DAC_TVDAC; 1542 1.8.2.2 yamt sc->sc_ports[0].rp_conn_type = RADEON_CONN_DVI_D; 1543 1.8.2.2 yamt sc->sc_ports[0].rp_tmds_type = RADEON_TMDS_INT; 1544 1.8.2.2 yamt 1545 1.8.2.2 yamt sc->sc_ports[1].rp_mon_type = RADEON_MT_UNKNOWN; 1546 1.8.2.2 yamt sc->sc_ports[1].rp_ddc_type = RADEON_DDC_VGA; 1547 1.8.2.2 yamt sc->sc_ports[1].rp_dac_type = RADEON_DAC_PRIMARY; 1548 1.8.2.2 yamt sc->sc_ports[1].rp_conn_type = RADEON_CONN_CRT; 1549 1.8.2.2 yamt sc->sc_ports[1].rp_tmds_type = RADEON_TMDS_EXT; 1550 1.8.2.2 yamt } 1551 1.8.2.2 yamt 1552 1.8.2.2 yamt /* 1553 1.8.2.2 yamt * Fixup for RS300/RS350/RS400 chips, that lack a primary DAC. 1554 1.8.2.2 yamt * these chips should use TVDAC for the VGA port. 1555 1.8.2.2 yamt */ 1556 1.8.2.2 yamt if (HAS_SDAC(sc)) { 1557 1.8.2.2 yamt if (sc->sc_ports[0].rp_conn_type == RADEON_CONN_CRT) { 1558 1.8.2.2 yamt sc->sc_ports[0].rp_dac_type = RADEON_DAC_TVDAC; 1559 1.8.2.2 yamt sc->sc_ports[1].rp_dac_type = RADEON_DAC_PRIMARY; 1560 1.8.2.2 yamt } else { 1561 1.8.2.2 yamt sc->sc_ports[1].rp_dac_type = RADEON_DAC_TVDAC; 1562 1.8.2.2 yamt sc->sc_ports[0].rp_dac_type = RADEON_DAC_PRIMARY; 1563 1.8.2.2 yamt } 1564 1.8.2.2 yamt } else if (!HAS_CRTC2(sc)) { 1565 1.8.2.2 yamt sc->sc_ports[0].rp_dac_type = RADEON_DAC_PRIMARY; 1566 1.8.2.2 yamt } 1567 1.8.2.2 yamt 1568 1.8.2.2 yamt for (i = 0; i < 2; i++) { 1569 1.8.2.2 yamt char edid[128]; 1570 1.8.2.2 yamt uint8_t ddc; 1571 1.8.2.2 yamt struct edid_info *eip = &sc->sc_ports[i].rp_edid; 1572 1.8.2.4 yamt prop_data_t edid_data; 1573 1.8.2.2 yamt 1574 1.8.2.2 yamt DPRINTF(("Port #%d:\n", i)); 1575 1.8.2.2 yamt DPRINTF((" conn = %d\n", sc->sc_ports[i].rp_conn_type)); 1576 1.8.2.2 yamt DPRINTF((" ddc = %d\n", sc->sc_ports[i].rp_ddc_type)); 1577 1.8.2.2 yamt DPRINTF((" dac = %d\n", sc->sc_ports[i].rp_dac_type)); 1578 1.8.2.2 yamt DPRINTF((" tmds = %d\n", sc->sc_ports[i].rp_tmds_type)); 1579 1.8.2.2 yamt 1580 1.8.2.2 yamt sc->sc_ports[i].rp_edid_valid = 0; 1581 1.8.2.4 yamt /* first look for static EDID data */ 1582 1.8.2.4 yamt if ((edid_data = prop_dictionary_get(device_properties( 1583 1.8.2.4 yamt &sc->sc_dev), "EDID")) != NULL) { 1584 1.8.2.4 yamt 1585 1.8.2.4 yamt aprint_normal("%s: using static EDID\n", 1586 1.8.2.4 yamt sc->sc_dev.dv_xname); 1587 1.8.2.4 yamt memcpy(edid, prop_data_data_nocopy(edid_data), 128); 1588 1.8.2.4 yamt if (edid_parse(edid, eip) == 0) { 1589 1.8.2.4 yamt 1590 1.8.2.2 yamt sc->sc_ports[i].rp_edid_valid = 1; 1591 1.8.2.2 yamt edid_print(eip); 1592 1.8.2.2 yamt } 1593 1.8.2.2 yamt } 1594 1.8.2.4 yamt /* if we didn't find any we'll try to talk to the monitor */ 1595 1.8.2.4 yamt if (sc->sc_ports[i].rp_edid_valid != 1) { 1596 1.8.2.4 yamt 1597 1.8.2.4 yamt ddc = sc->sc_ports[i].rp_ddc_type; 1598 1.8.2.4 yamt if (ddc != RADEON_DDC_NONE) { 1599 1.8.2.4 yamt if ((radeonfb_i2c_read_edid(sc, ddc, edid) 1600 1.8.2.4 yamt == 0) && (edid_parse(edid, eip) == 0)) { 1601 1.8.2.4 yamt 1602 1.8.2.4 yamt sc->sc_ports[i].rp_edid_valid = 1; 1603 1.8.2.4 yamt edid_print(eip); 1604 1.8.2.4 yamt } 1605 1.8.2.4 yamt } 1606 1.8.2.4 yamt } 1607 1.8.2.2 yamt } 1608 1.8.2.2 yamt 1609 1.8.2.2 yamt return found; 1610 1.8.2.2 yamt } 1611 1.8.2.2 yamt 1612 1.8.2.2 yamt int 1613 1.8.2.2 yamt radeonfb_gettmds(struct radeonfb_softc *sc) 1614 1.8.2.2 yamt { 1615 1.8.2.2 yamt int i; 1616 1.8.2.2 yamt 1617 1.8.2.2 yamt if (!sc->sc_biossz) { 1618 1.8.2.2 yamt goto nobios; 1619 1.8.2.2 yamt } 1620 1.8.2.2 yamt 1621 1.8.2.2 yamt if (IS_ATOM(sc)) { 1622 1.8.2.2 yamt /* XXX: not done yet */ 1623 1.8.2.2 yamt } else { 1624 1.8.2.2 yamt uint16_t ptr; 1625 1.8.2.2 yamt int n; 1626 1.8.2.2 yamt 1627 1.8.2.2 yamt ptr = GETBIOS16(sc, 0x48); 1628 1.8.2.2 yamt ptr = GETBIOS16(sc, ptr + 0x34); 1629 1.8.2.2 yamt DPRINTF(("DFP table revision %d\n", GETBIOS8(sc, ptr))); 1630 1.8.2.2 yamt if (GETBIOS8(sc, ptr) == 3) { 1631 1.8.2.2 yamt /* revision three table */ 1632 1.8.2.2 yamt n = GETBIOS8(sc, ptr + 5) + 1; 1633 1.8.2.2 yamt n = min(n, 4); 1634 1.8.2.2 yamt 1635 1.8.2.2 yamt memset(sc->sc_tmds_pll, 0, sizeof (sc->sc_tmds_pll)); 1636 1.8.2.2 yamt for (i = 0; i < n; i++) { 1637 1.8.2.2 yamt sc->sc_tmds_pll[i].rtp_pll = GETBIOS32(sc, 1638 1.8.2.2 yamt ptr + i * 10 + 8); 1639 1.8.2.2 yamt sc->sc_tmds_pll[i].rtp_freq = GETBIOS16(sc, 1640 1.8.2.2 yamt ptr + i * 10 + 0x10); 1641 1.8.2.2 yamt DPRINTF(("TMDS_PLL dot clock %d pll %x\n", 1642 1.8.2.2 yamt sc->sc_tmds_pll[i].rtp_freq, 1643 1.8.2.2 yamt sc->sc_tmds_pll[i].rtp_pll)); 1644 1.8.2.2 yamt } 1645 1.8.2.2 yamt return 0; 1646 1.8.2.2 yamt } 1647 1.8.2.2 yamt } 1648 1.8.2.2 yamt 1649 1.8.2.2 yamt nobios: 1650 1.8.2.2 yamt DPRINTF(("no suitable DFP table present\n")); 1651 1.8.2.2 yamt for (i = 0; 1652 1.8.2.2 yamt i < sizeof (radeonfb_tmds_pll) / sizeof (radeonfb_tmds_pll[0]); 1653 1.8.2.2 yamt i++) { 1654 1.8.2.2 yamt int j; 1655 1.8.2.2 yamt 1656 1.8.2.2 yamt if (radeonfb_tmds_pll[i].family != sc->sc_family) 1657 1.8.2.2 yamt continue; 1658 1.8.2.2 yamt 1659 1.8.2.2 yamt for (j = 0; j < 4; j++) { 1660 1.8.2.2 yamt sc->sc_tmds_pll[j] = radeonfb_tmds_pll[i].plls[j]; 1661 1.8.2.2 yamt DPRINTF(("TMDS_PLL dot clock %d pll %x\n", 1662 1.8.2.2 yamt sc->sc_tmds_pll[j].rtp_freq, 1663 1.8.2.2 yamt sc->sc_tmds_pll[j].rtp_pll)); 1664 1.8.2.2 yamt } 1665 1.8.2.2 yamt return 0; 1666 1.8.2.2 yamt } 1667 1.8.2.2 yamt 1668 1.8.2.2 yamt return -1; 1669 1.8.2.2 yamt } 1670 1.8.2.2 yamt 1671 1.8.2.2 yamt const struct videomode * 1672 1.8.2.2 yamt radeonfb_modelookup(const char *name) 1673 1.8.2.2 yamt { 1674 1.8.2.2 yamt int i; 1675 1.8.2.2 yamt 1676 1.8.2.2 yamt for (i = 0; i < videomode_count; i++) 1677 1.8.2.2 yamt if (!strcmp(name, videomode_list[i].name)) 1678 1.8.2.2 yamt return &videomode_list[i]; 1679 1.8.2.2 yamt 1680 1.8.2.2 yamt return NULL; 1681 1.8.2.2 yamt } 1682 1.8.2.2 yamt 1683 1.8.2.2 yamt void 1684 1.8.2.2 yamt radeonfb_pllwriteupdate(struct radeonfb_softc *sc, int crtc) 1685 1.8.2.2 yamt { 1686 1.8.2.2 yamt if (crtc) { 1687 1.8.2.2 yamt while (GETPLL(sc, RADEON_P2PLL_REF_DIV) & 1688 1.8.2.2 yamt RADEON_P2PLL_ATOMIC_UPDATE_R); 1689 1.8.2.2 yamt SETPLL(sc, RADEON_P2PLL_REF_DIV, RADEON_P2PLL_ATOMIC_UPDATE_W); 1690 1.8.2.2 yamt } else { 1691 1.8.2.2 yamt while (GETPLL(sc, RADEON_PPLL_REF_DIV) & 1692 1.8.2.2 yamt RADEON_PPLL_ATOMIC_UPDATE_R); 1693 1.8.2.2 yamt SETPLL(sc, RADEON_PPLL_REF_DIV, RADEON_PPLL_ATOMIC_UPDATE_W); 1694 1.8.2.2 yamt } 1695 1.8.2.2 yamt } 1696 1.8.2.2 yamt 1697 1.8.2.2 yamt void 1698 1.8.2.2 yamt radeonfb_pllwaitatomicread(struct radeonfb_softc *sc, int crtc) 1699 1.8.2.2 yamt { 1700 1.8.2.2 yamt int i; 1701 1.8.2.2 yamt 1702 1.8.2.2 yamt for (i = 10000; i; i--) { 1703 1.8.2.2 yamt if (crtc) { 1704 1.8.2.2 yamt if (GETPLL(sc, RADEON_P2PLL_REF_DIV) & 1705 1.8.2.2 yamt RADEON_P2PLL_ATOMIC_UPDATE_R) 1706 1.8.2.2 yamt break; 1707 1.8.2.2 yamt } else { 1708 1.8.2.2 yamt if (GETPLL(sc, RADEON_PPLL_REF_DIV) & 1709 1.8.2.2 yamt RADEON_PPLL_ATOMIC_UPDATE_R) 1710 1.8.2.2 yamt break; 1711 1.8.2.2 yamt } 1712 1.8.2.2 yamt } 1713 1.8.2.2 yamt } 1714 1.8.2.2 yamt 1715 1.8.2.2 yamt void 1716 1.8.2.2 yamt radeonfb_program_vclk(struct radeonfb_softc *sc, int dotclock, int crtc) 1717 1.8.2.2 yamt { 1718 1.8.2.2 yamt uint32_t pbit = 0; 1719 1.8.2.2 yamt uint32_t feed = 0; 1720 1.8.2.2 yamt uint32_t data; 1721 1.8.2.2 yamt #if 1 1722 1.8.2.2 yamt int i; 1723 1.8.2.2 yamt #endif 1724 1.8.2.2 yamt 1725 1.8.2.2 yamt radeonfb_calc_dividers(sc, dotclock, &pbit, &feed); 1726 1.8.2.2 yamt 1727 1.8.2.2 yamt if (crtc == 0) { 1728 1.8.2.2 yamt 1729 1.8.2.2 yamt /* XXXX: mobility workaround missing */ 1730 1.8.2.2 yamt /* XXXX: R300 stuff missing */ 1731 1.8.2.2 yamt 1732 1.8.2.2 yamt PATCHPLL(sc, RADEON_VCLK_ECP_CNTL, 1733 1.8.2.2 yamt RADEON_VCLK_SRC_SEL_CPUCLK, 1734 1.8.2.2 yamt ~RADEON_VCLK_SRC_SEL_MASK); 1735 1.8.2.2 yamt 1736 1.8.2.2 yamt /* put vclk into reset, use atomic updates */ 1737 1.8.2.2 yamt SETPLL(sc, RADEON_PPLL_CNTL, 1738 1.8.2.2 yamt RADEON_PPLL_REFCLK_SEL | 1739 1.8.2.2 yamt RADEON_PPLL_FBCLK_SEL | 1740 1.8.2.2 yamt RADEON_PPLL_RESET | 1741 1.8.2.2 yamt RADEON_PPLL_ATOMIC_UPDATE_EN | 1742 1.8.2.2 yamt RADEON_PPLL_VGA_ATOMIC_UPDATE_EN); 1743 1.8.2.2 yamt 1744 1.8.2.2 yamt /* select clock 3 */ 1745 1.8.2.2 yamt #if 0 1746 1.8.2.2 yamt PATCH32(sc, RADEON_CLOCK_CNTL_INDEX, RADEON_PLL_DIV_SEL, 1747 1.8.2.2 yamt ~RADEON_PLL_DIV_SEL); 1748 1.8.2.2 yamt #else 1749 1.8.2.2 yamt PATCH32(sc, RADEON_CLOCK_CNTL_INDEX, 0, 1750 1.8.2.2 yamt ~RADEON_PLL_DIV_SEL); 1751 1.8.2.2 yamt #endif 1752 1.8.2.2 yamt 1753 1.8.2.2 yamt /* XXX: R300 family -- program divider differently? */ 1754 1.8.2.2 yamt 1755 1.8.2.2 yamt /* program reference divider */ 1756 1.8.2.2 yamt PATCHPLL(sc, RADEON_PPLL_REF_DIV, sc->sc_refdiv, 1757 1.8.2.2 yamt ~RADEON_PPLL_REF_DIV_MASK); 1758 1.8.2.2 yamt PRINTPLL(RADEON_PPLL_REF_DIV); 1759 1.8.2.2 yamt 1760 1.8.2.2 yamt #if 0 1761 1.8.2.2 yamt data = GETPLL(sc, RADEON_PPLL_DIV_3); 1762 1.8.2.2 yamt data &= ~(RADEON_PPLL_FB3_DIV_MASK | 1763 1.8.2.2 yamt RADEON_PPLL_POST3_DIV_MASK); 1764 1.8.2.2 yamt data |= pbit; 1765 1.8.2.2 yamt data |= (feed & RADEON_PPLL_FB3_DIV_MASK); 1766 1.8.2.2 yamt PUTPLL(sc, RADEON_PPLL_DIV_3, data); 1767 1.8.2.2 yamt #else 1768 1.8.2.2 yamt for (i = 0; i < 4; i++) { 1769 1.8.2.2 yamt } 1770 1.8.2.2 yamt #endif 1771 1.8.2.2 yamt 1772 1.8.2.2 yamt /* use the atomic update */ 1773 1.8.2.2 yamt radeonfb_pllwriteupdate(sc, crtc); 1774 1.8.2.2 yamt 1775 1.8.2.2 yamt /* and wait for it to complete */ 1776 1.8.2.2 yamt radeonfb_pllwaitatomicread(sc, crtc); 1777 1.8.2.2 yamt 1778 1.8.2.2 yamt /* program HTOTAL (why?) */ 1779 1.8.2.2 yamt PUTPLL(sc, RADEON_HTOTAL_CNTL, 0); 1780 1.8.2.2 yamt 1781 1.8.2.2 yamt /* drop reset */ 1782 1.8.2.2 yamt CLRPLL(sc, RADEON_PPLL_CNTL, 1783 1.8.2.2 yamt RADEON_PPLL_RESET | RADEON_PPLL_SLEEP | 1784 1.8.2.2 yamt RADEON_PPLL_ATOMIC_UPDATE_EN | 1785 1.8.2.2 yamt RADEON_PPLL_VGA_ATOMIC_UPDATE_EN); 1786 1.8.2.2 yamt 1787 1.8.2.2 yamt PRINTPLL(RADEON_PPLL_CNTL); 1788 1.8.2.2 yamt 1789 1.8.2.2 yamt /* give clock time to lock */ 1790 1.8.2.2 yamt delay(50000); 1791 1.8.2.2 yamt 1792 1.8.2.2 yamt PATCHPLL(sc, RADEON_VCLK_ECP_CNTL, 1793 1.8.2.2 yamt RADEON_VCLK_SRC_SEL_PPLLCLK, 1794 1.8.2.2 yamt ~RADEON_VCLK_SRC_SEL_MASK); 1795 1.8.2.2 yamt 1796 1.8.2.2 yamt } else { 1797 1.8.2.2 yamt 1798 1.8.2.2 yamt PATCHPLL(sc, RADEON_PIXCLKS_CNTL, 1799 1.8.2.2 yamt RADEON_PIX2CLK_SRC_SEL_CPUCLK, 1800 1.8.2.2 yamt ~RADEON_PIX2CLK_SRC_SEL_MASK); 1801 1.8.2.2 yamt 1802 1.8.2.2 yamt /* put vclk into reset, use atomic updates */ 1803 1.8.2.2 yamt SETPLL(sc, RADEON_P2PLL_CNTL, 1804 1.8.2.2 yamt RADEON_P2PLL_RESET | 1805 1.8.2.2 yamt RADEON_P2PLL_ATOMIC_UPDATE_EN | 1806 1.8.2.2 yamt RADEON_P2PLL_VGA_ATOMIC_UPDATE_EN); 1807 1.8.2.2 yamt 1808 1.8.2.2 yamt /* XXX: R300 family -- program divider differently? */ 1809 1.8.2.2 yamt 1810 1.8.2.2 yamt /* program reference divider */ 1811 1.8.2.2 yamt PATCHPLL(sc, RADEON_P2PLL_REF_DIV, sc->sc_refdiv, 1812 1.8.2.2 yamt ~RADEON_P2PLL_REF_DIV_MASK); 1813 1.8.2.2 yamt 1814 1.8.2.2 yamt /* program feedback and post dividers */ 1815 1.8.2.2 yamt data = GETPLL(sc, RADEON_P2PLL_DIV_0); 1816 1.8.2.2 yamt data &= ~(RADEON_P2PLL_FB0_DIV_MASK | 1817 1.8.2.2 yamt RADEON_P2PLL_POST0_DIV_MASK); 1818 1.8.2.2 yamt data |= pbit; 1819 1.8.2.2 yamt data |= (feed & RADEON_P2PLL_FB0_DIV_MASK); 1820 1.8.2.2 yamt PUTPLL(sc, RADEON_P2PLL_DIV_0, data); 1821 1.8.2.2 yamt 1822 1.8.2.2 yamt /* use the atomic update */ 1823 1.8.2.2 yamt radeonfb_pllwriteupdate(sc, crtc); 1824 1.8.2.2 yamt 1825 1.8.2.2 yamt /* and wait for it to complete */ 1826 1.8.2.2 yamt radeonfb_pllwaitatomicread(sc, crtc); 1827 1.8.2.2 yamt 1828 1.8.2.2 yamt /* program HTOTAL (why?) */ 1829 1.8.2.2 yamt PUTPLL(sc, RADEON_HTOTAL2_CNTL, 0); 1830 1.8.2.2 yamt 1831 1.8.2.2 yamt /* drop reset */ 1832 1.8.2.2 yamt CLRPLL(sc, RADEON_P2PLL_CNTL, 1833 1.8.2.2 yamt RADEON_P2PLL_RESET | RADEON_P2PLL_SLEEP | 1834 1.8.2.2 yamt RADEON_P2PLL_ATOMIC_UPDATE_EN | 1835 1.8.2.2 yamt RADEON_P2PLL_VGA_ATOMIC_UPDATE_EN); 1836 1.8.2.2 yamt 1837 1.8.2.2 yamt /* allow time for clock to lock */ 1838 1.8.2.2 yamt delay(50000); 1839 1.8.2.2 yamt 1840 1.8.2.2 yamt PATCHPLL(sc, RADEON_PIXCLKS_CNTL, 1841 1.8.2.2 yamt RADEON_PIX2CLK_SRC_SEL_P2PLLCLK, 1842 1.8.2.2 yamt ~RADEON_PIX2CLK_SRC_SEL_MASK); 1843 1.8.2.2 yamt } 1844 1.8.2.2 yamt PRINTREG(RADEON_CRTC_MORE_CNTL); 1845 1.8.2.2 yamt } 1846 1.8.2.2 yamt 1847 1.8.2.2 yamt void 1848 1.8.2.2 yamt radeonfb_modeswitch(struct radeonfb_display *dp) 1849 1.8.2.2 yamt { 1850 1.8.2.2 yamt struct radeonfb_softc *sc = dp->rd_softc; 1851 1.8.2.2 yamt int i; 1852 1.8.2.2 yamt 1853 1.8.2.2 yamt /* blank the display while we switch modes */ 1854 1.8.2.2 yamt //radeonfb_blank(dp, 1); 1855 1.8.2.2 yamt 1856 1.8.2.2 yamt #if 0 1857 1.8.2.2 yamt SET32(sc, RADEON_CRTC_EXT_CNTL, 1858 1.8.2.2 yamt RADEON_CRTC_VSYNC_DIS | RADEON_CRTC_HSYNC_DIS | 1859 1.8.2.2 yamt RADEON_CRTC_DISPLAY_DIS /* | RADEON_CRTC_DISP_REQ_EN_B */); 1860 1.8.2.2 yamt #endif 1861 1.8.2.2 yamt 1862 1.8.2.2 yamt /* these registers might get in the way... */ 1863 1.8.2.2 yamt PUT32(sc, RADEON_OVR_CLR, 0); 1864 1.8.2.2 yamt PUT32(sc, RADEON_OVR_WID_LEFT_RIGHT, 0); 1865 1.8.2.2 yamt PUT32(sc, RADEON_OVR_WID_TOP_BOTTOM, 0); 1866 1.8.2.2 yamt PUT32(sc, RADEON_OV0_SCALE_CNTL, 0); 1867 1.8.2.2 yamt PUT32(sc, RADEON_SUBPIC_CNTL, 0); 1868 1.8.2.2 yamt PUT32(sc, RADEON_VIPH_CONTROL, 0); 1869 1.8.2.2 yamt PUT32(sc, RADEON_I2C_CNTL_1, 0); 1870 1.8.2.2 yamt PUT32(sc, RADEON_GEN_INT_CNTL, 0); 1871 1.8.2.2 yamt PUT32(sc, RADEON_CAP0_TRIG_CNTL, 0); 1872 1.8.2.2 yamt PUT32(sc, RADEON_CAP1_TRIG_CNTL, 0); 1873 1.8.2.2 yamt PUT32(sc, RADEON_SURFACE_CNTL, 0); 1874 1.8.2.2 yamt 1875 1.8.2.2 yamt for (i = 0; i < dp->rd_ncrtcs; i++) 1876 1.8.2.2 yamt radeonfb_setcrtc(dp, i); 1877 1.8.2.2 yamt 1878 1.8.2.2 yamt /* activate the display */ 1879 1.8.2.2 yamt //radeonfb_blank(dp, 0); 1880 1.8.2.2 yamt } 1881 1.8.2.2 yamt 1882 1.8.2.2 yamt void 1883 1.8.2.2 yamt radeonfb_setcrtc(struct radeonfb_display *dp, int index) 1884 1.8.2.2 yamt { 1885 1.8.2.2 yamt int crtc; 1886 1.8.2.2 yamt struct videomode *mode; 1887 1.8.2.2 yamt struct radeonfb_softc *sc; 1888 1.8.2.2 yamt struct radeonfb_crtc *cp; 1889 1.8.2.2 yamt uint32_t v; 1890 1.8.2.2 yamt uint32_t gencntl; 1891 1.8.2.2 yamt uint32_t htotaldisp; 1892 1.8.2.2 yamt uint32_t hsyncstrt; 1893 1.8.2.2 yamt uint32_t vtotaldisp; 1894 1.8.2.2 yamt uint32_t vsyncstrt; 1895 1.8.2.2 yamt uint32_t fphsyncstrt; 1896 1.8.2.2 yamt uint32_t fpvsyncstrt; 1897 1.8.2.2 yamt uint32_t fphtotaldisp; 1898 1.8.2.2 yamt uint32_t fpvtotaldisp; 1899 1.8.2.2 yamt uint32_t pitch; 1900 1.8.2.2 yamt 1901 1.8.2.2 yamt sc = dp->rd_softc; 1902 1.8.2.2 yamt cp = &dp->rd_crtcs[index]; 1903 1.8.2.2 yamt crtc = cp->rc_number; 1904 1.8.2.2 yamt mode = &cp->rc_videomode; 1905 1.8.2.2 yamt 1906 1.8.2.2 yamt #if 1 1907 1.8.2.2 yamt pitch = (((dp->rd_virtx * dp->rd_bpp) + ((dp->rd_bpp * 8) - 1)) / 1908 1.8.2.2 yamt (dp->rd_bpp * 8)); 1909 1.8.2.2 yamt #else 1910 1.8.2.2 yamt pitch = (((sc->sc_maxx * sc->sc_maxbpp) + ((sc->sc_maxbpp * 8) - 1)) / 1911 1.8.2.2 yamt (sc->sc_maxbpp * 8)); 1912 1.8.2.2 yamt #endif 1913 1.8.2.2 yamt //pitch = pitch | (pitch << 16); 1914 1.8.2.2 yamt 1915 1.8.2.2 yamt switch (crtc) { 1916 1.8.2.2 yamt case 0: 1917 1.8.2.2 yamt gencntl = RADEON_CRTC_GEN_CNTL; 1918 1.8.2.2 yamt htotaldisp = RADEON_CRTC_H_TOTAL_DISP; 1919 1.8.2.2 yamt hsyncstrt = RADEON_CRTC_H_SYNC_STRT_WID; 1920 1.8.2.2 yamt vtotaldisp = RADEON_CRTC_V_TOTAL_DISP; 1921 1.8.2.2 yamt vsyncstrt = RADEON_CRTC_V_SYNC_STRT_WID; 1922 1.8.2.2 yamt fpvsyncstrt = RADEON_FP_V_SYNC_STRT_WID; 1923 1.8.2.2 yamt fphsyncstrt = RADEON_FP_H_SYNC_STRT_WID; 1924 1.8.2.2 yamt fpvtotaldisp = RADEON_FP_CRTC_V_TOTAL_DISP; 1925 1.8.2.2 yamt fphtotaldisp = RADEON_FP_CRTC_H_TOTAL_DISP; 1926 1.8.2.2 yamt break; 1927 1.8.2.2 yamt case 1: 1928 1.8.2.2 yamt gencntl = RADEON_CRTC2_GEN_CNTL; 1929 1.8.2.2 yamt htotaldisp = RADEON_CRTC2_H_TOTAL_DISP; 1930 1.8.2.2 yamt hsyncstrt = RADEON_CRTC2_H_SYNC_STRT_WID; 1931 1.8.2.2 yamt vtotaldisp = RADEON_CRTC2_V_TOTAL_DISP; 1932 1.8.2.2 yamt vsyncstrt = RADEON_CRTC2_V_SYNC_STRT_WID; 1933 1.8.2.2 yamt fpvsyncstrt = RADEON_FP_V2_SYNC_STRT_WID; 1934 1.8.2.2 yamt fphsyncstrt = RADEON_FP_H2_SYNC_STRT_WID; 1935 1.8.2.2 yamt fpvtotaldisp = RADEON_FP_CRTC2_V_TOTAL_DISP; 1936 1.8.2.2 yamt fphtotaldisp = RADEON_FP_CRTC2_H_TOTAL_DISP; 1937 1.8.2.2 yamt break; 1938 1.8.2.2 yamt default: 1939 1.8.2.2 yamt panic("Bad CRTC!"); 1940 1.8.2.2 yamt break; 1941 1.8.2.2 yamt } 1942 1.8.2.2 yamt 1943 1.8.2.2 yamt /* 1944 1.8.2.2 yamt * CRTC_GEN_CNTL - depth, accelerator mode, etc. 1945 1.8.2.2 yamt */ 1946 1.8.2.2 yamt /* only bother with 32bpp and 8bpp */ 1947 1.8.2.2 yamt v = dp->rd_format << RADEON_CRTC_PIX_WIDTH_SHIFT; 1948 1.8.2.2 yamt 1949 1.8.2.2 yamt if (crtc == 1) { 1950 1.8.2.2 yamt v |= RADEON_CRTC2_CRT2_ON | RADEON_CRTC2_EN; 1951 1.8.2.2 yamt } else { 1952 1.8.2.2 yamt v |= RADEON_CRTC_EXT_DISP_EN | RADEON_CRTC_EN; 1953 1.8.2.2 yamt } 1954 1.8.2.2 yamt 1955 1.8.2.2 yamt if (mode->flags & VID_DBLSCAN) 1956 1.8.2.2 yamt v |= RADEON_CRTC2_DBL_SCAN_EN; 1957 1.8.2.2 yamt 1958 1.8.2.2 yamt if (mode->flags & VID_INTERLACE) 1959 1.8.2.2 yamt v |= RADEON_CRTC2_INTERLACE_EN; 1960 1.8.2.2 yamt 1961 1.8.2.2 yamt if (mode->flags & VID_CSYNC) { 1962 1.8.2.2 yamt v |= RADEON_CRTC2_CSYNC_EN; 1963 1.8.2.2 yamt if (crtc == 1) 1964 1.8.2.2 yamt v |= RADEON_CRTC2_VSYNC_TRISTAT; 1965 1.8.2.2 yamt } 1966 1.8.2.2 yamt 1967 1.8.2.2 yamt PUT32(sc, gencntl, v); 1968 1.8.2.2 yamt DPRINTF(("CRTC%s_GEN_CNTL = %08x\n", crtc ? "2" : "", v)); 1969 1.8.2.2 yamt 1970 1.8.2.2 yamt /* 1971 1.8.2.2 yamt * CRTC_EXT_CNTL - preserve disable flags, set ATI linear and EXT_CNT 1972 1.8.2.2 yamt */ 1973 1.8.2.2 yamt v = GET32(sc, RADEON_CRTC_EXT_CNTL); 1974 1.8.2.2 yamt if (crtc == 0) { 1975 1.8.2.2 yamt v &= (RADEON_CRTC_VSYNC_DIS | RADEON_CRTC_HSYNC_DIS | 1976 1.8.2.2 yamt RADEON_CRTC_DISPLAY_DIS); 1977 1.8.2.2 yamt v |= RADEON_XCRT_CNT_EN | RADEON_VGA_ATI_LINEAR; 1978 1.8.2.2 yamt if (mode->flags & VID_CSYNC) 1979 1.8.2.2 yamt v |= RADEON_CRTC_VSYNC_TRISTAT; 1980 1.8.2.2 yamt } 1981 1.8.2.2 yamt /* unconditional turn on CRT, in case first CRTC is DFP */ 1982 1.8.2.2 yamt v |= RADEON_CRTC_CRT_ON; 1983 1.8.2.2 yamt PUT32(sc, RADEON_CRTC_EXT_CNTL, v); 1984 1.8.2.2 yamt PRINTREG(RADEON_CRTC_EXT_CNTL); 1985 1.8.2.2 yamt 1986 1.8.2.2 yamt /* 1987 1.8.2.2 yamt * H_TOTAL_DISP 1988 1.8.2.2 yamt */ 1989 1.8.2.2 yamt v = ((mode->hdisplay / 8) - 1) << 16; 1990 1.8.2.2 yamt v |= (mode->htotal / 8) - 1; 1991 1.8.2.2 yamt PUT32(sc, htotaldisp, v); 1992 1.8.2.2 yamt DPRINTF(("CRTC%s_H_TOTAL_DISP = %08x\n", crtc ? "2" : "", v)); 1993 1.8.2.2 yamt PUT32(sc, fphtotaldisp, v); 1994 1.8.2.2 yamt DPRINTF(("FP_H%s_TOTAL_DISP = %08x\n", crtc ? "2" : "", v)); 1995 1.8.2.2 yamt 1996 1.8.2.2 yamt /* 1997 1.8.2.2 yamt * H_SYNC_STRT_WID 1998 1.8.2.2 yamt */ 1999 1.8.2.2 yamt v = (((mode->hsync_end - mode->hsync_start) / 8) << 16); 2000 1.8.2.2 yamt v |= mode->hsync_start; 2001 1.8.2.2 yamt if (mode->flags & VID_NHSYNC) 2002 1.8.2.2 yamt v |= RADEON_CRTC_H_SYNC_POL; 2003 1.8.2.2 yamt PUT32(sc, hsyncstrt, v); 2004 1.8.2.2 yamt DPRINTF(("CRTC%s_H_SYNC_STRT_WID = %08x\n", crtc ? "2" : "", v)); 2005 1.8.2.2 yamt PUT32(sc, fphsyncstrt, v); 2006 1.8.2.2 yamt DPRINTF(("FP_H%s_SYNC_STRT_WID = %08x\n", crtc ? "2" : "", v)); 2007 1.8.2.2 yamt 2008 1.8.2.2 yamt /* 2009 1.8.2.2 yamt * V_TOTAL_DISP 2010 1.8.2.2 yamt */ 2011 1.8.2.2 yamt v = ((mode->vdisplay - 1) << 16); 2012 1.8.2.2 yamt v |= (mode->vtotal - 1); 2013 1.8.2.2 yamt PUT32(sc, vtotaldisp, v); 2014 1.8.2.2 yamt DPRINTF(("CRTC%s_V_TOTAL_DISP = %08x\n", crtc ? "2" : "", v)); 2015 1.8.2.2 yamt PUT32(sc, fpvtotaldisp, v); 2016 1.8.2.2 yamt DPRINTF(("FP_V%s_TOTAL_DISP = %08x\n", crtc ? "2" : "", v)); 2017 1.8.2.2 yamt 2018 1.8.2.2 yamt /* 2019 1.8.2.2 yamt * V_SYNC_STRT_WID 2020 1.8.2.2 yamt */ 2021 1.8.2.2 yamt v = ((mode->vsync_end - mode->vsync_start) << 16); 2022 1.8.2.2 yamt v |= (mode->vsync_start - 1); 2023 1.8.2.2 yamt if (mode->flags & VID_NVSYNC) 2024 1.8.2.2 yamt v |= RADEON_CRTC_V_SYNC_POL; 2025 1.8.2.2 yamt PUT32(sc, vsyncstrt, v); 2026 1.8.2.2 yamt DPRINTF(("CRTC%s_V_SYNC_STRT_WID = %08x\n", crtc ? "2" : "", v)); 2027 1.8.2.2 yamt PUT32(sc, fpvsyncstrt, v); 2028 1.8.2.2 yamt DPRINTF(("FP_V%s_SYNC_STRT_WID = %08x\n", crtc ? "2" : "", v)); 2029 1.8.2.2 yamt 2030 1.8.2.2 yamt radeonfb_program_vclk(sc, mode->dot_clock, crtc); 2031 1.8.2.2 yamt 2032 1.8.2.2 yamt switch (crtc) { 2033 1.8.2.2 yamt case 0: 2034 1.8.2.2 yamt PUT32(sc, RADEON_CRTC_OFFSET, 0); 2035 1.8.2.2 yamt PUT32(sc, RADEON_CRTC_OFFSET_CNTL, 0); 2036 1.8.2.2 yamt PUT32(sc, RADEON_CRTC_PITCH, pitch); 2037 1.8.2.2 yamt CLR32(sc, RADEON_DISP_MERGE_CNTL, RADEON_DISP_RGB_OFFSET_EN); 2038 1.8.2.2 yamt 2039 1.8.2.2 yamt CLR32(sc, RADEON_CRTC_EXT_CNTL, 2040 1.8.2.2 yamt RADEON_CRTC_VSYNC_DIS | RADEON_CRTC_HSYNC_DIS | 2041 1.8.2.2 yamt RADEON_CRTC_DISPLAY_DIS /* | RADEON_CRTC_DISP_REQ_EN_B */); 2042 1.8.2.2 yamt CLR32(sc, RADEON_CRTC_GEN_CNTL, RADEON_CRTC_DISP_REQ_EN_B); 2043 1.8.2.2 yamt PRINTREG(RADEON_CRTC_EXT_CNTL); 2044 1.8.2.2 yamt PRINTREG(RADEON_CRTC_GEN_CNTL); 2045 1.8.2.2 yamt PRINTREG(RADEON_CLOCK_CNTL_INDEX); 2046 1.8.2.2 yamt break; 2047 1.8.2.2 yamt 2048 1.8.2.2 yamt case 1: 2049 1.8.2.2 yamt PUT32(sc, RADEON_CRTC2_OFFSET, 0); 2050 1.8.2.2 yamt PUT32(sc, RADEON_CRTC2_OFFSET_CNTL, 0); 2051 1.8.2.2 yamt PUT32(sc, RADEON_CRTC2_PITCH, pitch); 2052 1.8.2.2 yamt CLR32(sc, RADEON_DISP2_MERGE_CNTL, RADEON_DISP2_RGB_OFFSET_EN); 2053 1.8.2.2 yamt CLR32(sc, RADEON_CRTC2_GEN_CNTL, 2054 1.8.2.2 yamt RADEON_CRTC2_VSYNC_DIS | 2055 1.8.2.2 yamt RADEON_CRTC2_HSYNC_DIS | 2056 1.8.2.2 yamt RADEON_CRTC2_DISP_DIS | RADEON_CRTC2_DISP_REQ_EN_B); 2057 1.8.2.2 yamt PRINTREG(RADEON_CRTC2_GEN_CNTL); 2058 1.8.2.2 yamt break; 2059 1.8.2.2 yamt } 2060 1.8.2.2 yamt } 2061 1.8.2.2 yamt 2062 1.8.2.2 yamt int 2063 1.8.2.2 yamt radeonfb_isblank(struct radeonfb_display *dp) 2064 1.8.2.2 yamt { 2065 1.8.2.2 yamt uint32_t reg, mask; 2066 1.8.2.2 yamt 2067 1.8.2.2 yamt if (dp->rd_crtcs[0].rc_number) { 2068 1.8.2.2 yamt reg = RADEON_CRTC2_GEN_CNTL; 2069 1.8.2.2 yamt mask = RADEON_CRTC2_DISP_DIS; 2070 1.8.2.2 yamt } else { 2071 1.8.2.2 yamt reg = RADEON_CRTC_EXT_CNTL; 2072 1.8.2.2 yamt mask = RADEON_CRTC_DISPLAY_DIS; 2073 1.8.2.2 yamt } 2074 1.8.2.2 yamt return ((GET32(dp->rd_softc, reg) & mask) ? 1 : 0); 2075 1.8.2.2 yamt } 2076 1.8.2.2 yamt 2077 1.8.2.2 yamt void 2078 1.8.2.2 yamt radeonfb_blank(struct radeonfb_display *dp, int blank) 2079 1.8.2.2 yamt { 2080 1.8.2.2 yamt struct radeonfb_softc *sc = dp->rd_softc; 2081 1.8.2.2 yamt uint32_t reg, mask; 2082 1.8.2.2 yamt uint32_t fpreg, fpval; 2083 1.8.2.2 yamt int i; 2084 1.8.2.2 yamt 2085 1.8.2.2 yamt for (i = 0; i < dp->rd_ncrtcs; i++) { 2086 1.8.2.2 yamt 2087 1.8.2.2 yamt if (dp->rd_crtcs[i].rc_number) { 2088 1.8.2.2 yamt reg = RADEON_CRTC2_GEN_CNTL; 2089 1.8.2.2 yamt mask = RADEON_CRTC2_DISP_DIS; 2090 1.8.2.2 yamt fpreg = RADEON_FP2_GEN_CNTL; 2091 1.8.2.2 yamt fpval = RADEON_FP2_ON; 2092 1.8.2.2 yamt } else { 2093 1.8.2.2 yamt reg = RADEON_CRTC_EXT_CNTL; 2094 1.8.2.2 yamt mask = RADEON_CRTC_DISPLAY_DIS; 2095 1.8.2.2 yamt fpreg = RADEON_FP_GEN_CNTL; 2096 1.8.2.2 yamt fpval = RADEON_FP_FPON; 2097 1.8.2.2 yamt } 2098 1.8.2.2 yamt 2099 1.8.2.2 yamt if (blank) { 2100 1.8.2.2 yamt SET32(sc, reg, mask); 2101 1.8.2.2 yamt CLR32(sc, fpreg, fpval); 2102 1.8.2.2 yamt } else { 2103 1.8.2.2 yamt CLR32(sc, reg, mask); 2104 1.8.2.2 yamt SET32(sc, fpreg, fpval); 2105 1.8.2.2 yamt } 2106 1.8.2.2 yamt } 2107 1.8.2.2 yamt PRINTREG(RADEON_FP_GEN_CNTL); 2108 1.8.2.2 yamt PRINTREG(RADEON_FP2_GEN_CNTL); 2109 1.8.2.2 yamt } 2110 1.8.2.2 yamt 2111 1.8.2.2 yamt void 2112 1.8.2.2 yamt radeonfb_init_screen(void *cookie, struct vcons_screen *scr, int existing, 2113 1.8.2.2 yamt long *defattr) 2114 1.8.2.2 yamt { 2115 1.8.2.2 yamt struct radeonfb_display *dp = cookie; 2116 1.8.2.2 yamt struct rasops_info *ri = &scr->scr_ri; 2117 1.8.2.2 yamt 2118 1.8.2.2 yamt /* initialize font subsystem */ 2119 1.8.2.2 yamt wsfont_init(); 2120 1.8.2.2 yamt 2121 1.8.2.2 yamt DPRINTF(("init screen called, existing %d\n", existing)); 2122 1.8.2.2 yamt 2123 1.8.2.2 yamt ri->ri_depth = dp->rd_bpp; 2124 1.8.2.2 yamt ri->ri_width = dp->rd_virtx; 2125 1.8.2.2 yamt ri->ri_height = dp->rd_virty; 2126 1.8.2.2 yamt ri->ri_stride = dp->rd_stride; 2127 1.8.2.2 yamt ri->ri_flg = RI_CENTER; 2128 1.8.2.2 yamt ri->ri_bits = (void *)dp->rd_fbptr; 2129 1.8.2.2 yamt 2130 1.8.2.2 yamt /* XXX: 32 bpp only */ 2131 1.8.2.2 yamt /* this is rgb in "big-endian order..." */ 2132 1.8.2.2 yamt ri->ri_rnum = 8; 2133 1.8.2.2 yamt ri->ri_gnum = 8; 2134 1.8.2.2 yamt ri->ri_bnum = 8; 2135 1.8.2.2 yamt ri->ri_rpos = 16; 2136 1.8.2.2 yamt ri->ri_gpos = 8; 2137 1.8.2.2 yamt ri->ri_bpos = 0; 2138 1.8.2.2 yamt 2139 1.8.2.2 yamt if (existing) { 2140 1.8.2.2 yamt ri->ri_flg |= RI_CLEAR; 2141 1.8.2.2 yamt 2142 1.8.2.2 yamt /* start a modeswitch now */ 2143 1.8.2.2 yamt radeonfb_modeswitch(dp); 2144 1.8.2.2 yamt } 2145 1.8.2.2 yamt 2146 1.8.2.2 yamt /* 2147 1.8.2.2 yamt * XXX: font selection should be based on properties, with some 2148 1.8.2.2 yamt * normal/reasonable default. 2149 1.8.2.2 yamt */ 2150 1.8.2.2 yamt ri->ri_caps = WSSCREEN_WSCOLORS; 2151 1.8.2.2 yamt 2152 1.8.2.2 yamt /* initialize and look for an initial font */ 2153 1.8.2.2 yamt rasops_init(ri, dp->rd_virty/8, dp->rd_virtx/8); 2154 1.8.2.2 yamt 2155 1.8.2.2 yamt rasops_reconfig(ri, dp->rd_virty / ri->ri_font->fontheight, 2156 1.8.2.2 yamt dp->rd_virtx / ri->ri_font->fontwidth); 2157 1.8.2.2 yamt 2158 1.8.2.2 yamt /* enable acceleration */ 2159 1.8.2.2 yamt ri->ri_ops.copyrows = radeonfb_copyrows; 2160 1.8.2.2 yamt ri->ri_ops.copycols = radeonfb_copycols; 2161 1.8.2.2 yamt ri->ri_ops.eraserows = radeonfb_eraserows; 2162 1.8.2.2 yamt ri->ri_ops.erasecols = radeonfb_erasecols; 2163 1.8.2.2 yamt ri->ri_ops.allocattr = radeonfb_allocattr; 2164 1.8.2.2 yamt if (!IS_R300(dp->rd_softc)) { 2165 1.8.2.2 yamt ri->ri_ops.putchar = radeonfb_putchar; 2166 1.8.2.2 yamt } 2167 1.8.2.2 yamt ri->ri_ops.cursor = radeonfb_cursor; 2168 1.8.2.2 yamt } 2169 1.8.2.2 yamt 2170 1.8.2.2 yamt void 2171 1.8.2.2 yamt radeonfb_set_fbloc(struct radeonfb_softc *sc) 2172 1.8.2.2 yamt { 2173 1.8.2.2 yamt uint32_t gen, ext, gen2 = 0; 2174 1.8.2.2 yamt uint32_t agploc, aperbase, apersize, mcfbloc; 2175 1.8.2.2 yamt 2176 1.8.2.2 yamt gen = GET32(sc, RADEON_CRTC_GEN_CNTL); 2177 1.8.2.2 yamt ext = GET32(sc, RADEON_CRTC_EXT_CNTL); 2178 1.8.2.2 yamt agploc = GET32(sc, RADEON_MC_AGP_LOCATION); 2179 1.8.2.2 yamt aperbase = GET32(sc, RADEON_CONFIG_APER_0_BASE); 2180 1.8.2.2 yamt apersize = GET32(sc, RADEON_CONFIG_APER_SIZE); 2181 1.8.2.2 yamt 2182 1.8.2.2 yamt PUT32(sc, RADEON_CRTC_GEN_CNTL, gen | RADEON_CRTC_DISP_REQ_EN_B); 2183 1.8.2.2 yamt PUT32(sc, RADEON_CRTC_EXT_CNTL, ext | RADEON_CRTC_DISPLAY_DIS); 2184 1.8.2.2 yamt //PUT32(sc, RADEON_CRTC_GEN_CNTL, gen | RADEON_CRTC_DISPLAY_DIS); 2185 1.8.2.2 yamt //PUT32(sc, RADEON_CRTC_EXT_CNTL, ext | RADEON_CRTC_DISP_REQ_EN_B); 2186 1.8.2.2 yamt 2187 1.8.2.2 yamt if (HAS_CRTC2(sc)) { 2188 1.8.2.2 yamt gen2 = GET32(sc, RADEON_CRTC2_GEN_CNTL); 2189 1.8.2.2 yamt PUT32(sc, RADEON_CRTC2_GEN_CNTL, 2190 1.8.2.2 yamt gen2 | RADEON_CRTC2_DISP_REQ_EN_B); 2191 1.8.2.2 yamt } 2192 1.8.2.2 yamt 2193 1.8.2.2 yamt delay(100000); 2194 1.8.2.2 yamt 2195 1.8.2.2 yamt mcfbloc = (aperbase >> 16) | 2196 1.8.2.2 yamt ((aperbase + (apersize - 1)) & 0xffff0000); 2197 1.8.2.2 yamt 2198 1.8.2.2 yamt sc->sc_aperbase = (mcfbloc & 0xffff) << 16; 2199 1.8.2.2 yamt sc->sc_memsz = apersize; 2200 1.8.2.2 yamt 2201 1.8.2.2 yamt if (((agploc & 0xffff) << 16) != 2202 1.8.2.2 yamt ((mcfbloc & 0xffff0000U) + 0x10000)) { 2203 1.8.2.2 yamt agploc = mcfbloc & 0xffff0000U; 2204 1.8.2.2 yamt agploc |= ((agploc + 0x10000) >> 16); 2205 1.8.2.2 yamt } 2206 1.8.2.2 yamt 2207 1.8.2.2 yamt PUT32(sc, RADEON_HOST_PATH_CNTL, 0); 2208 1.8.2.2 yamt 2209 1.8.2.2 yamt PUT32(sc, RADEON_MC_FB_LOCATION, mcfbloc); 2210 1.8.2.2 yamt PUT32(sc, RADEON_MC_AGP_LOCATION, agploc); 2211 1.8.2.2 yamt 2212 1.8.2.2 yamt DPRINTF(("aperbase = %u\n", aperbase)); 2213 1.8.2.2 yamt PRINTREG(RADEON_MC_FB_LOCATION); 2214 1.8.2.2 yamt PRINTREG(RADEON_MC_AGP_LOCATION); 2215 1.8.2.2 yamt 2216 1.8.2.2 yamt PUT32(sc, RADEON_DISPLAY_BASE_ADDR, sc->sc_aperbase); 2217 1.8.2.2 yamt 2218 1.8.2.2 yamt if (HAS_CRTC2(sc)) 2219 1.8.2.2 yamt PUT32(sc, RADEON_DISPLAY2_BASE_ADDR, sc->sc_aperbase); 2220 1.8.2.2 yamt 2221 1.8.2.2 yamt PUT32(sc, RADEON_OV0_BASE_ADDR, sc->sc_aperbase); 2222 1.8.2.2 yamt 2223 1.8.2.2 yamt #if 0 2224 1.8.2.2 yamt /* XXX: what is this AGP garbage? :-) */ 2225 1.8.2.2 yamt PUT32(sc, RADEON_AGP_CNTL, 0x00100000); 2226 1.8.2.2 yamt #endif 2227 1.8.2.2 yamt 2228 1.8.2.2 yamt delay(100000); 2229 1.8.2.2 yamt 2230 1.8.2.2 yamt PUT32(sc, RADEON_CRTC_GEN_CNTL, gen); 2231 1.8.2.2 yamt PUT32(sc, RADEON_CRTC_EXT_CNTL, ext); 2232 1.8.2.2 yamt 2233 1.8.2.2 yamt if (HAS_CRTC2(sc)) 2234 1.8.2.2 yamt PUT32(sc, RADEON_CRTC2_GEN_CNTL, gen2); 2235 1.8.2.2 yamt } 2236 1.8.2.2 yamt 2237 1.8.2.2 yamt void 2238 1.8.2.2 yamt radeonfb_init_misc(struct radeonfb_softc *sc) 2239 1.8.2.2 yamt { 2240 1.8.2.2 yamt PUT32(sc, RADEON_BUS_CNTL, 2241 1.8.2.2 yamt RADEON_BUS_MASTER_DIS | 2242 1.8.2.2 yamt RADEON_BUS_PREFETCH_MODE_ACT | 2243 1.8.2.2 yamt RADEON_BUS_PCI_READ_RETRY_EN | 2244 1.8.2.2 yamt RADEON_BUS_PCI_WRT_RETRY_EN | 2245 1.8.2.2 yamt (3 << RADEON_BUS_RETRY_WS_SHIFT) | 2246 1.8.2.2 yamt RADEON_BUS_MSTR_RD_MULT | 2247 1.8.2.2 yamt RADEON_BUS_MSTR_RD_LINE | 2248 1.8.2.2 yamt RADEON_BUS_RD_DISCARD_EN | 2249 1.8.2.2 yamt RADEON_BUS_MSTR_DISCONNECT_EN | 2250 1.8.2.2 yamt RADEON_BUS_READ_BURST); 2251 1.8.2.2 yamt 2252 1.8.2.2 yamt PUT32(sc, RADEON_BUS_CNTL1, 0xf0); 2253 1.8.2.2 yamt /* PUT32(sc, RADEON_SEPROM_CNTL1, 0x09ff0000); */ 2254 1.8.2.2 yamt PUT32(sc, RADEON_FCP_CNTL, RADEON_FCP0_SRC_GND); 2255 1.8.2.2 yamt PUT32(sc, RADEON_RBBM_CNTL, 2256 1.8.2.2 yamt (3 << RADEON_RB_SETTLE_SHIFT) | 2257 1.8.2.2 yamt (4 << RADEON_ABORTCLKS_HI_SHIFT) | 2258 1.8.2.2 yamt (4 << RADEON_ABORTCLKS_CP_SHIFT) | 2259 1.8.2.2 yamt (4 << RADEON_ABORTCLKS_CFIFO_SHIFT)); 2260 1.8.2.2 yamt 2261 1.8.2.2 yamt /* XXX: figure out what these mean! */ 2262 1.8.2.2 yamt PUT32(sc, RADEON_AGP_CNTL, 0x00100000); 2263 1.8.2.2 yamt PUT32(sc, RADEON_HOST_PATH_CNTL, 0); 2264 1.8.2.2 yamt //PUT32(sc, RADEON_DISP_MISC_CNTL, 0x5bb00400); 2265 1.8.2.2 yamt 2266 1.8.2.2 yamt PUT32(sc, RADEON_GEN_INT_CNTL, 0); 2267 1.8.2.2 yamt PUT32(sc, RADEON_GEN_INT_STATUS, GET32(sc, RADEON_GEN_INT_STATUS)); 2268 1.8.2.2 yamt } 2269 1.8.2.2 yamt 2270 1.8.2.2 yamt /* 2271 1.8.2.2 yamt * This loads a linear color map for true color. 2272 1.8.2.2 yamt */ 2273 1.8.2.2 yamt void 2274 1.8.2.2 yamt radeonfb_init_palette(struct radeonfb_softc *sc, int crtc) 2275 1.8.2.2 yamt { 2276 1.8.2.2 yamt int i; 2277 1.8.2.2 yamt uint32_t vclk; 2278 1.8.2.2 yamt 2279 1.8.2.2 yamt #define DAC_WIDTH ((1 << 10) - 1) 2280 1.8.2.2 yamt #define CLUT_WIDTH ((1 << 8) - 1) 2281 1.8.2.2 yamt #define CLUT_COLOR(i) ((i * DAC_WIDTH * 2 / CLUT_WIDTH + 1) / 2) 2282 1.8.2.2 yamt 2283 1.8.2.2 yamt vclk = GETPLL(sc, RADEON_VCLK_ECP_CNTL); 2284 1.8.2.2 yamt PUTPLL(sc, RADEON_VCLK_ECP_CNTL, vclk & ~RADEON_PIXCLK_DAC_ALWAYS_ONb); 2285 1.8.2.2 yamt 2286 1.8.2.2 yamt if (crtc) 2287 1.8.2.2 yamt SET32(sc, RADEON_DAC_CNTL2, RADEON_DAC2_PALETTE_ACC_CTL); 2288 1.8.2.2 yamt else 2289 1.8.2.2 yamt CLR32(sc, RADEON_DAC_CNTL2, RADEON_DAC2_PALETTE_ACC_CTL); 2290 1.8.2.2 yamt 2291 1.8.2.2 yamt PUT32(sc, RADEON_PALETTE_INDEX, 0); 2292 1.8.2.2 yamt for (i = 0; i <= CLUT_WIDTH; ++i) { 2293 1.8.2.2 yamt PUT32(sc, RADEON_PALETTE_30_DATA, 2294 1.8.2.2 yamt (CLUT_COLOR(i) << 10) | 2295 1.8.2.2 yamt (CLUT_COLOR(i) << 20) | 2296 1.8.2.2 yamt (CLUT_COLOR(i))); 2297 1.8.2.2 yamt } 2298 1.8.2.2 yamt 2299 1.8.2.2 yamt CLR32(sc, RADEON_DAC_CNTL2, RADEON_DAC2_PALETTE_ACC_CTL); 2300 1.8.2.2 yamt PRINTREG(RADEON_DAC_CNTL2); 2301 1.8.2.2 yamt 2302 1.8.2.2 yamt PUTPLL(sc, RADEON_VCLK_ECP_CNTL, vclk); 2303 1.8.2.2 yamt } 2304 1.8.2.2 yamt 2305 1.8.2.2 yamt /* 2306 1.8.2.2 yamt * Bugs in some R300 hardware requires this when accessing CLOCK_CNTL_INDEX. 2307 1.8.2.2 yamt */ 2308 1.8.2.2 yamt void 2309 1.8.2.2 yamt radeonfb_r300cg_workaround(struct radeonfb_softc *sc) 2310 1.8.2.2 yamt { 2311 1.8.2.2 yamt uint32_t tmp, save; 2312 1.8.2.2 yamt 2313 1.8.2.2 yamt save = GET32(sc, RADEON_CLOCK_CNTL_INDEX); 2314 1.8.2.2 yamt tmp = save & ~(0x3f | RADEON_PLL_WR_EN); 2315 1.8.2.2 yamt PUT32(sc, RADEON_CLOCK_CNTL_INDEX, tmp); 2316 1.8.2.2 yamt tmp = GET32(sc, RADEON_CLOCK_CNTL_DATA); 2317 1.8.2.2 yamt PUT32(sc, RADEON_CLOCK_CNTL_INDEX, save); 2318 1.8.2.2 yamt } 2319 1.8.2.2 yamt 2320 1.8.2.2 yamt /* 2321 1.8.2.2 yamt * Acceleration entry points. 2322 1.8.2.2 yamt */ 2323 1.8.2.2 yamt static void 2324 1.8.2.2 yamt radeonfb_putchar(void *cookie, int row, int col, u_int c, long attr) 2325 1.8.2.2 yamt { 2326 1.8.2.2 yamt struct rasops_info *ri = cookie; 2327 1.8.2.2 yamt struct vcons_screen *scr = ri->ri_hw; 2328 1.8.2.2 yamt struct radeonfb_display *dp = scr->scr_cookie; 2329 1.8.2.2 yamt uint32_t x, y, w, h; 2330 1.8.2.2 yamt uint32_t bg, fg; 2331 1.8.2.2 yamt uint8_t *data; 2332 1.8.2.2 yamt 2333 1.8.2.2 yamt if (dp->rd_wsmode != WSDISPLAYIO_MODE_EMUL) 2334 1.8.2.2 yamt return; 2335 1.8.2.2 yamt 2336 1.8.2.2 yamt if (!CHAR_IN_FONT(c, ri->ri_font)) 2337 1.8.2.2 yamt return; 2338 1.8.2.2 yamt 2339 1.8.2.2 yamt w = ri->ri_font->fontwidth; 2340 1.8.2.2 yamt h = ri->ri_font->fontheight; 2341 1.8.2.2 yamt 2342 1.8.2.2 yamt bg = ri->ri_devcmap[(attr >> 16) & 0xf]; 2343 1.8.2.2 yamt fg = ri->ri_devcmap[(attr >> 24) & 0xf]; 2344 1.8.2.2 yamt 2345 1.8.2.2 yamt x = ri->ri_xorigin + col * w; 2346 1.8.2.2 yamt y = ri->ri_yorigin + row * h; 2347 1.8.2.2 yamt 2348 1.8.2.2 yamt if (c == 0x20) { 2349 1.8.2.2 yamt radeonfb_rectfill(dp, x, y, w, h, bg); 2350 1.8.2.2 yamt } else { 2351 1.8.2.2 yamt data = (uint8_t *)ri->ri_font->data + 2352 1.8.2.2 yamt (c - ri->ri_font->firstchar) * ri->ri_fontscale; 2353 1.8.2.2 yamt 2354 1.8.2.2 yamt radeonfb_setup_mono(dp, x, y, w, h, fg, bg); 2355 1.8.2.2 yamt radeonfb_feed_bytes(dp, ri->ri_fontscale, data); 2356 1.8.2.2 yamt } 2357 1.8.2.2 yamt } 2358 1.8.2.2 yamt 2359 1.8.2.2 yamt static void 2360 1.8.2.2 yamt radeonfb_eraserows(void *cookie, int row, int nrows, long fillattr) 2361 1.8.2.2 yamt { 2362 1.8.2.2 yamt struct rasops_info *ri = cookie; 2363 1.8.2.2 yamt struct vcons_screen *scr = ri->ri_hw; 2364 1.8.2.2 yamt struct radeonfb_display *dp = scr->scr_cookie; 2365 1.8.2.2 yamt uint32_t x, y, w, h, fg, bg, ul; 2366 1.8.2.2 yamt 2367 1.8.2.2 yamt /* XXX: check for full emulation mode? */ 2368 1.8.2.2 yamt if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 2369 1.8.2.2 yamt x = ri->ri_xorigin; 2370 1.8.2.2 yamt y = ri->ri_yorigin + ri->ri_font->fontheight * row; 2371 1.8.2.2 yamt w = ri->ri_emuwidth; 2372 1.8.2.2 yamt h = ri->ri_font->fontheight * nrows; 2373 1.8.2.2 yamt 2374 1.8.2.2 yamt rasops_unpack_attr(fillattr, &fg, &bg, &ul); 2375 1.8.2.2 yamt radeonfb_rectfill(dp, x, y, w, h, ri->ri_devcmap[bg & 0xf]); 2376 1.8.2.2 yamt } 2377 1.8.2.2 yamt } 2378 1.8.2.2 yamt 2379 1.8.2.2 yamt static void 2380 1.8.2.2 yamt radeonfb_copyrows(void *cookie, int srcrow, int dstrow, int nrows) 2381 1.8.2.2 yamt { 2382 1.8.2.2 yamt struct rasops_info *ri = cookie; 2383 1.8.2.2 yamt struct vcons_screen *scr = ri->ri_hw; 2384 1.8.2.2 yamt struct radeonfb_display *dp = scr->scr_cookie; 2385 1.8.2.2 yamt uint32_t x, ys, yd, w, h; 2386 1.8.2.2 yamt 2387 1.8.2.2 yamt if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 2388 1.8.2.2 yamt x = ri->ri_xorigin; 2389 1.8.2.2 yamt ys = ri->ri_yorigin + ri->ri_font->fontheight * srcrow; 2390 1.8.2.2 yamt yd = ri->ri_yorigin + ri->ri_font->fontheight * dstrow; 2391 1.8.2.2 yamt w = ri->ri_emuwidth; 2392 1.8.2.2 yamt h = ri->ri_font->fontheight * nrows; 2393 1.8.2.2 yamt radeonfb_bitblt(dp, x, ys, x, yd, w, h, 2394 1.8.2.2 yamt RADEON_ROP3_S, 0xffffffff); 2395 1.8.2.2 yamt } 2396 1.8.2.2 yamt } 2397 1.8.2.2 yamt 2398 1.8.2.2 yamt static void 2399 1.8.2.2 yamt radeonfb_copycols(void *cookie, int row, int srccol, int dstcol, int ncols) 2400 1.8.2.2 yamt { 2401 1.8.2.2 yamt struct rasops_info *ri = cookie; 2402 1.8.2.2 yamt struct vcons_screen *scr = ri->ri_hw; 2403 1.8.2.2 yamt struct radeonfb_display *dp = scr->scr_cookie; 2404 1.8.2.2 yamt uint32_t xs, xd, y, w, h; 2405 1.8.2.2 yamt 2406 1.8.2.2 yamt if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 2407 1.8.2.2 yamt xs = ri->ri_xorigin + ri->ri_font->fontwidth * srccol; 2408 1.8.2.2 yamt xd = ri->ri_xorigin + ri->ri_font->fontwidth * dstcol; 2409 1.8.2.2 yamt y = ri->ri_yorigin + ri->ri_font->fontheight * row; 2410 1.8.2.2 yamt w = ri->ri_font->fontwidth * ncols; 2411 1.8.2.2 yamt h = ri->ri_font->fontheight; 2412 1.8.2.2 yamt radeonfb_bitblt(dp, xs, y, xd, y, w, h, 2413 1.8.2.2 yamt RADEON_ROP3_S, 0xffffffff); 2414 1.8.2.2 yamt } 2415 1.8.2.2 yamt } 2416 1.8.2.2 yamt 2417 1.8.2.2 yamt static void 2418 1.8.2.2 yamt radeonfb_erasecols(void *cookie, int row, int startcol, int ncols, 2419 1.8.2.2 yamt long fillattr) 2420 1.8.2.2 yamt { 2421 1.8.2.2 yamt struct rasops_info *ri = cookie; 2422 1.8.2.2 yamt struct vcons_screen *scr = ri->ri_hw; 2423 1.8.2.2 yamt struct radeonfb_display *dp = scr->scr_cookie; 2424 1.8.2.2 yamt uint32_t x, y, w, h, fg, bg, ul; 2425 1.8.2.2 yamt 2426 1.8.2.2 yamt if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 2427 1.8.2.2 yamt x = ri->ri_xorigin + ri->ri_font->fontwidth * startcol; 2428 1.8.2.2 yamt y = ri->ri_yorigin + ri->ri_font->fontheight * row; 2429 1.8.2.2 yamt w = ri->ri_font->fontwidth * ncols; 2430 1.8.2.2 yamt h = ri->ri_font->fontheight; 2431 1.8.2.2 yamt 2432 1.8.2.2 yamt rasops_unpack_attr(fillattr, &fg, &bg, &ul); 2433 1.8.2.2 yamt radeonfb_rectfill(dp, x, y, w, h, ri->ri_devcmap[bg & 0xf]); 2434 1.8.2.2 yamt } 2435 1.8.2.2 yamt } 2436 1.8.2.2 yamt 2437 1.8.2.2 yamt static void 2438 1.8.2.2 yamt radeonfb_cursor(void *cookie, int on, int row, int col) 2439 1.8.2.2 yamt { 2440 1.8.2.2 yamt struct rasops_info *ri = cookie; 2441 1.8.2.2 yamt struct vcons_screen *scr = ri->ri_hw; 2442 1.8.2.2 yamt struct radeonfb_display *dp = scr->scr_cookie; 2443 1.8.2.2 yamt int x, y, wi, he; 2444 1.8.2.2 yamt 2445 1.8.2.2 yamt wi = ri->ri_font->fontwidth; 2446 1.8.2.2 yamt he = ri->ri_font->fontheight; 2447 1.8.2.2 yamt 2448 1.8.2.2 yamt if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 2449 1.8.2.2 yamt x = ri->ri_ccol * wi + ri->ri_xorigin; 2450 1.8.2.2 yamt y = ri->ri_crow * he + ri->ri_yorigin; 2451 1.8.2.2 yamt /* first turn off the old cursor */ 2452 1.8.2.2 yamt if (ri->ri_flg & RI_CURSOR) { 2453 1.8.2.2 yamt radeonfb_bitblt(dp, x, y, x, y, wi, he, 2454 1.8.2.2 yamt RADEON_ROP3_Dn, 0xffffffff); 2455 1.8.2.2 yamt ri->ri_flg &= ~RI_CURSOR; 2456 1.8.2.2 yamt } 2457 1.8.2.2 yamt ri->ri_crow = row; 2458 1.8.2.2 yamt ri->ri_ccol = col; 2459 1.8.2.2 yamt /* then (possibly) turn on the new one */ 2460 1.8.2.2 yamt if (on) { 2461 1.8.2.2 yamt x = ri->ri_ccol * wi + ri->ri_xorigin; 2462 1.8.2.2 yamt y = ri->ri_crow * he + ri->ri_yorigin; 2463 1.8.2.2 yamt radeonfb_bitblt(dp, x, y, x, y, wi, he, 2464 1.8.2.2 yamt RADEON_ROP3_Dn, 0xffffffff); 2465 1.8.2.2 yamt ri->ri_flg |= RI_CURSOR; 2466 1.8.2.2 yamt } 2467 1.8.2.2 yamt } else { 2468 1.8.2.2 yamt scr->scr_ri.ri_crow = row; 2469 1.8.2.2 yamt scr->scr_ri.ri_ccol = col; 2470 1.8.2.2 yamt scr->scr_ri.ri_flg &= ~RI_CURSOR; 2471 1.8.2.2 yamt } 2472 1.8.2.2 yamt } 2473 1.8.2.2 yamt 2474 1.8.2.2 yamt static int 2475 1.8.2.2 yamt radeonfb_allocattr(void *cookie, int fg, int bg, int flags, long *attrp) 2476 1.8.2.2 yamt { 2477 1.8.2.2 yamt if ((fg == 0) && (bg == 0)) { 2478 1.8.2.2 yamt fg = WS_DEFAULT_FG; 2479 1.8.2.2 yamt bg = WS_DEFAULT_BG; 2480 1.8.2.2 yamt } 2481 1.8.2.2 yamt *attrp = ((fg & 0xf) << 24) | ((bg & 0xf) << 16) | (flags & 0xff) << 8; 2482 1.8.2.2 yamt return 0; 2483 1.8.2.2 yamt } 2484 1.8.2.2 yamt 2485 1.8.2.2 yamt /* 2486 1.8.2.2 yamt * Underlying acceleration support. 2487 1.8.2.2 yamt */ 2488 1.8.2.2 yamt static void 2489 1.8.2.2 yamt radeonfb_setup_mono(struct radeonfb_display *dp, int xd, int yd, int width, 2490 1.8.2.2 yamt int height, uint32_t fg, uint32_t bg) 2491 1.8.2.2 yamt { 2492 1.8.2.2 yamt struct radeonfb_softc *sc = dp->rd_softc; 2493 1.8.2.2 yamt uint32_t gmc; 2494 1.8.2.2 yamt uint32_t padded_width = (width+7) & 0xfff8; 2495 1.8.2.2 yamt uint32_t topleft, bottomright; 2496 1.8.2.2 yamt 2497 1.8.2.2 yamt gmc = dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT; 2498 1.8.2.2 yamt 2499 1.8.2.2 yamt if (width != padded_width) { 2500 1.8.2.2 yamt 2501 1.8.2.2 yamt radeonfb_wait_fifo(sc, 2); 2502 1.8.2.2 yamt topleft = ((yd << 16) & 0x1fff0000) | (xd & 0x1fff); 2503 1.8.2.2 yamt bottomright = (((yd + height) << 16) & 0x1fff0000) | 2504 1.8.2.2 yamt ((xd + width) & 0x1fff); 2505 1.8.2.2 yamt PUT32(sc, RADEON_SC_TOP_LEFT, topleft); 2506 1.8.2.2 yamt PUT32(sc, RADEON_SC_BOTTOM_RIGHT, bottomright); 2507 1.8.2.2 yamt } 2508 1.8.2.2 yamt 2509 1.8.2.2 yamt radeonfb_wait_fifo(sc, 5); 2510 1.8.2.2 yamt 2511 1.8.2.2 yamt PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 2512 1.8.2.2 yamt RADEON_GMC_BRUSH_NONE | 2513 1.8.2.2 yamt RADEON_GMC_SRC_DATATYPE_MONO_FG_BG | 2514 1.8.2.2 yamt //RADEON_GMC_BYTE_LSB_TO_MSB | 2515 1.8.2.2 yamt RADEON_GMC_DST_CLIPPING | 2516 1.8.2.2 yamt RADEON_ROP3_S | 2517 1.8.2.2 yamt RADEON_DP_SRC_SOURCE_HOST_DATA | 2518 1.8.2.2 yamt RADEON_GMC_CLR_CMP_CNTL_DIS | 2519 1.8.2.2 yamt RADEON_GMC_WR_MSK_DIS | 2520 1.8.2.2 yamt gmc); 2521 1.8.2.2 yamt 2522 1.8.2.2 yamt PUT32(sc, RADEON_DP_SRC_FRGD_CLR, fg); 2523 1.8.2.2 yamt PUT32(sc, RADEON_DP_SRC_BKGD_CLR, bg); 2524 1.8.2.2 yamt 2525 1.8.2.2 yamt PUT32(sc, RADEON_DST_X_Y, (xd << 16) | yd); 2526 1.8.2.2 yamt PUT32(sc, RADEON_DST_WIDTH_HEIGHT, (padded_width << 16) | height); 2527 1.8.2.2 yamt 2528 1.8.2.2 yamt } 2529 1.8.2.2 yamt 2530 1.8.2.2 yamt static void 2531 1.8.2.2 yamt radeonfb_feed_bytes(struct radeonfb_display *dp, int count, uint8_t *data) 2532 1.8.2.2 yamt { 2533 1.8.2.2 yamt struct radeonfb_softc *sc = dp->rd_softc; 2534 1.8.2.2 yamt int i; 2535 1.8.2.2 yamt uint32_t latch = 0; 2536 1.8.2.2 yamt int shift = 0; 2537 1.8.2.2 yamt 2538 1.8.2.2 yamt for (i = 0; i < count; i++) { 2539 1.8.2.2 yamt latch |= (data[i] << shift); 2540 1.8.2.2 yamt if (shift == 24) { 2541 1.8.2.2 yamt radeonfb_wait_fifo(sc, 1); 2542 1.8.2.2 yamt PUT32(sc, RADEON_HOST_DATA0, latch); 2543 1.8.2.2 yamt latch = 0; 2544 1.8.2.2 yamt shift = 0; 2545 1.8.2.2 yamt } else 2546 1.8.2.2 yamt shift += 8; 2547 1.8.2.2 yamt } 2548 1.8.2.2 yamt if (shift != 0) { 2549 1.8.2.2 yamt radeonfb_wait_fifo(sc, 1); 2550 1.8.2.2 yamt PUT32(sc, RADEON_HOST_DATA0, latch); 2551 1.8.2.2 yamt } 2552 1.8.2.2 yamt radeonfb_unclip(sc); 2553 1.8.2.2 yamt } 2554 1.8.2.2 yamt 2555 1.8.2.2 yamt static void 2556 1.8.2.2 yamt radeonfb_rectfill(struct radeonfb_display *dp, int dstx, int dsty, 2557 1.8.2.2 yamt int width, int height, uint32_t color) 2558 1.8.2.2 yamt { 2559 1.8.2.2 yamt struct radeonfb_softc *sc = dp->rd_softc; 2560 1.8.2.2 yamt uint32_t gmc; 2561 1.8.2.2 yamt 2562 1.8.2.2 yamt gmc = dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT; 2563 1.8.2.2 yamt 2564 1.8.2.2 yamt radeonfb_wait_fifo(sc, 6); 2565 1.8.2.2 yamt 2566 1.8.2.2 yamt PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 2567 1.8.2.2 yamt RADEON_GMC_BRUSH_SOLID_COLOR | 2568 1.8.2.2 yamt RADEON_GMC_SRC_DATATYPE_COLOR | 2569 1.8.2.2 yamt RADEON_GMC_CLR_CMP_CNTL_DIS | 2570 1.8.2.2 yamt RADEON_ROP3_P | gmc); 2571 1.8.2.2 yamt 2572 1.8.2.2 yamt PUT32(sc, RADEON_DP_BRUSH_FRGD_CLR, color); 2573 1.8.2.2 yamt PUT32(sc, RADEON_DP_WRITE_MASK, 0xffffffff); 2574 1.8.2.2 yamt PUT32(sc, RADEON_DP_CNTL, 2575 1.8.2.2 yamt RADEON_DST_X_LEFT_TO_RIGHT | 2576 1.8.2.2 yamt RADEON_DST_Y_TOP_TO_BOTTOM); 2577 1.8.2.2 yamt PUT32(sc, RADEON_DST_Y_X, (dsty << 16) | dstx); 2578 1.8.2.2 yamt PUT32(sc, RADEON_DST_WIDTH_HEIGHT, (width << 16) | (height)); 2579 1.8.2.2 yamt 2580 1.8.2.2 yamt /* 2581 1.8.2.2 yamt * XXX: we don't wait for the fifo to empty -- that would slow 2582 1.8.2.2 yamt * things down! The linux radeonfb driver waits, but xfree doesn't 2583 1.8.2.2 yamt */ 2584 1.8.2.2 yamt /* XXX: for now we do, to make it safe for direct drawing */ 2585 1.8.2.2 yamt radeonfb_engine_idle(sc); 2586 1.8.2.2 yamt } 2587 1.8.2.2 yamt 2588 1.8.2.2 yamt static void 2589 1.8.2.2 yamt radeonfb_bitblt(struct radeonfb_display *dp, int srcx, int srcy, 2590 1.8.2.2 yamt int dstx, int dsty, int width, int height, int rop, uint32_t mask) 2591 1.8.2.2 yamt { 2592 1.8.2.2 yamt struct radeonfb_softc *sc = dp->rd_softc; 2593 1.8.2.2 yamt uint32_t gmc; 2594 1.8.2.2 yamt uint32_t dir; 2595 1.8.2.2 yamt 2596 1.8.2.2 yamt if (dsty < srcy) { 2597 1.8.2.2 yamt dir = RADEON_DST_Y_TOP_TO_BOTTOM; 2598 1.8.2.2 yamt } else { 2599 1.8.2.2 yamt srcy += height - 1; 2600 1.8.2.2 yamt dsty += height - 1; 2601 1.8.2.2 yamt dir = 0; 2602 1.8.2.2 yamt } 2603 1.8.2.2 yamt if (dstx < srcx) { 2604 1.8.2.2 yamt dir |= RADEON_DST_X_LEFT_TO_RIGHT; 2605 1.8.2.2 yamt } else { 2606 1.8.2.2 yamt srcx += width - 1; 2607 1.8.2.2 yamt dstx += width - 1; 2608 1.8.2.2 yamt } 2609 1.8.2.2 yamt 2610 1.8.2.2 yamt gmc = dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT; 2611 1.8.2.2 yamt 2612 1.8.2.2 yamt radeonfb_wait_fifo(sc, 6); 2613 1.8.2.2 yamt 2614 1.8.2.2 yamt PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 2615 1.8.2.2 yamt //RADEON_GMC_SRC_CLIPPING | 2616 1.8.2.2 yamt RADEON_GMC_BRUSH_SOLID_COLOR | 2617 1.8.2.2 yamt RADEON_GMC_SRC_DATATYPE_COLOR | 2618 1.8.2.2 yamt RADEON_GMC_CLR_CMP_CNTL_DIS | 2619 1.8.2.2 yamt RADEON_DP_SRC_SOURCE_MEMORY | 2620 1.8.2.2 yamt rop | gmc); 2621 1.8.2.2 yamt 2622 1.8.2.2 yamt PUT32(sc, RADEON_DP_WRITE_MASK, mask); 2623 1.8.2.2 yamt PUT32(sc, RADEON_DP_CNTL, dir); 2624 1.8.2.2 yamt PUT32(sc, RADEON_SRC_Y_X, (srcy << 16) | srcx); 2625 1.8.2.2 yamt PUT32(sc, RADEON_DST_Y_X, (dsty << 16) | dstx); 2626 1.8.2.2 yamt PUT32(sc, RADEON_DST_WIDTH_HEIGHT, (width << 16) | (height)); 2627 1.8.2.2 yamt 2628 1.8.2.2 yamt /* 2629 1.8.2.2 yamt * XXX: we don't wait for the fifo to empty -- that would slow 2630 1.8.2.2 yamt * things down! The linux radeonfb driver waits, but xfree doesn't 2631 1.8.2.2 yamt */ 2632 1.8.2.2 yamt /* XXX: for now we do, to make it safe for direct drawing */ 2633 1.8.2.2 yamt radeonfb_engine_idle(sc); 2634 1.8.2.2 yamt } 2635 1.8.2.2 yamt 2636 1.8.2.2 yamt static void 2637 1.8.2.2 yamt radeonfb_engine_idle(struct radeonfb_softc *sc) 2638 1.8.2.2 yamt { 2639 1.8.2.2 yamt int i; 2640 1.8.2.2 yamt 2641 1.8.2.2 yamt radeonfb_wait_fifo(sc, 64); 2642 1.8.2.2 yamt for (i = RADEON_TIMEOUT; i; i--) { 2643 1.8.2.2 yamt if ((GET32(sc, RADEON_RBBM_STATUS) & 2644 1.8.2.2 yamt RADEON_RBBM_ACTIVE) == 0) { 2645 1.8.2.2 yamt radeonfb_engine_flush(sc); 2646 1.8.2.2 yamt break; 2647 1.8.2.2 yamt } 2648 1.8.2.2 yamt } 2649 1.8.2.2 yamt } 2650 1.8.2.2 yamt 2651 1.8.2.2 yamt static void 2652 1.8.2.2 yamt radeonfb_wait_fifo(struct radeonfb_softc *sc, int n) 2653 1.8.2.2 yamt { 2654 1.8.2.2 yamt int i; 2655 1.8.2.2 yamt 2656 1.8.2.2 yamt for (i = RADEON_TIMEOUT; i; i--) { 2657 1.8.2.2 yamt if ((GET32(sc, RADEON_RBBM_STATUS) & 2658 1.8.2.2 yamt RADEON_RBBM_FIFOCNT_MASK) >= n) 2659 1.8.2.2 yamt return; 2660 1.8.2.2 yamt } 2661 1.8.2.2 yamt #ifdef DIAGNOSTIC 2662 1.8.2.2 yamt if (!i) 2663 1.8.2.2 yamt printf("%s: timed out waiting for fifo (%x)\n", 2664 1.8.2.2 yamt XNAME(sc), GET32(sc, RADEON_RBBM_STATUS)); 2665 1.8.2.2 yamt #endif 2666 1.8.2.2 yamt } 2667 1.8.2.2 yamt 2668 1.8.2.2 yamt static void 2669 1.8.2.2 yamt radeonfb_engine_flush(struct radeonfb_softc *sc) 2670 1.8.2.2 yamt { 2671 1.8.2.2 yamt int i; 2672 1.8.2.2 yamt SET32(sc, RADEON_RB2D_DSTCACHE_CTLSTAT, RADEON_RB2D_DC_FLUSH_ALL); 2673 1.8.2.2 yamt for (i = RADEON_TIMEOUT; i; i--) { 2674 1.8.2.2 yamt if ((GET32(sc, RADEON_RB2D_DSTCACHE_CTLSTAT) & 2675 1.8.2.2 yamt RADEON_RB2D_DC_BUSY) == 0) 2676 1.8.2.2 yamt break; 2677 1.8.2.2 yamt } 2678 1.8.2.2 yamt #ifdef DIAGNOSTIC 2679 1.8.2.2 yamt if (!i) 2680 1.8.2.2 yamt printf("%s: engine flush timed out!\n", XNAME(sc)); 2681 1.8.2.2 yamt #endif 2682 1.8.2.2 yamt } 2683 1.8.2.2 yamt 2684 1.8.2.2 yamt static inline void 2685 1.8.2.2 yamt radeonfb_unclip(struct radeonfb_softc *sc) 2686 1.8.2.2 yamt { 2687 1.8.2.2 yamt 2688 1.8.2.2 yamt radeonfb_wait_fifo(sc, 2); 2689 1.8.2.2 yamt PUT32(sc, RADEON_SC_TOP_LEFT, 0); 2690 1.8.2.2 yamt PUT32(sc, RADEON_SC_BOTTOM_RIGHT, 0x1fff1fff); 2691 1.8.2.2 yamt } 2692 1.8.2.2 yamt 2693 1.8.2.2 yamt static void 2694 1.8.2.2 yamt radeonfb_engine_init(struct radeonfb_display *dp) 2695 1.8.2.2 yamt { 2696 1.8.2.2 yamt struct radeonfb_softc *sc = dp->rd_softc; 2697 1.8.2.2 yamt uint32_t pitch; 2698 1.8.2.2 yamt 2699 1.8.2.2 yamt /* no 3D */ 2700 1.8.2.2 yamt PUT32(sc, RADEON_RB3D_CNTL, 0); 2701 1.8.2.2 yamt 2702 1.8.2.2 yamt radeonfb_engine_reset(sc); 2703 1.8.2.2 yamt pitch = ((dp->rd_virtx * (dp->rd_bpp / 8) + 0x3f)) >> 6; 2704 1.8.2.2 yamt //pitch = ((sc->sc_maxx * (sc->sc_maxbpp / 8) + 0x3f)) >> 6; 2705 1.8.2.2 yamt 2706 1.8.2.2 yamt radeonfb_wait_fifo(sc, 1); 2707 1.8.2.2 yamt if (!IS_R300(sc)) 2708 1.8.2.2 yamt PUT32(sc, RADEON_RB2D_DSTCACHE_MODE, 0); 2709 1.8.2.2 yamt 2710 1.8.2.2 yamt radeonfb_wait_fifo(sc, 3); 2711 1.8.2.2 yamt PUT32(sc, RADEON_DEFAULT_PITCH_OFFSET, 2712 1.8.2.2 yamt (pitch << 22) | (sc->sc_aperbase >> 10)); 2713 1.8.2.2 yamt 2714 1.8.2.2 yamt 2715 1.8.2.2 yamt PUT32(sc, RADEON_DST_PITCH_OFFSET, 2716 1.8.2.2 yamt (pitch << 22) | (sc->sc_aperbase >> 10)); 2717 1.8.2.2 yamt PUT32(sc, RADEON_SRC_PITCH_OFFSET, 2718 1.8.2.2 yamt (pitch << 22) | (sc->sc_aperbase >> 10)); 2719 1.8.2.2 yamt 2720 1.8.2.2 yamt radeonfb_wait_fifo(sc, 1); 2721 1.8.2.2 yamt #if _BYTE_ORDER == _BIG_ENDIAN 2722 1.8.2.2 yamt SET32(sc, RADEON_DP_DATATYPE, RADEON_HOST_BIG_ENDIAN_EN); 2723 1.8.2.2 yamt #else 2724 1.8.2.2 yamt CLR32(sc, RADEON_DP_DATATYPE, RADEON_HOST_BIG_ENDIAN_EN); 2725 1.8.2.2 yamt #endif 2726 1.8.2.2 yamt 2727 1.8.2.2 yamt /* default scissors -- no clipping */ 2728 1.8.2.2 yamt radeonfb_wait_fifo(sc, 1); 2729 1.8.2.2 yamt PUT32(sc, RADEON_DEFAULT_SC_BOTTOM_RIGHT, 2730 1.8.2.2 yamt RADEON_DEFAULT_SC_RIGHT_MAX | RADEON_DEFAULT_SC_BOTTOM_MAX); 2731 1.8.2.2 yamt 2732 1.8.2.2 yamt radeonfb_wait_fifo(sc, 1); 2733 1.8.2.2 yamt PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 2734 1.8.2.2 yamt (dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT) | 2735 1.8.2.2 yamt RADEON_GMC_CLR_CMP_CNTL_DIS | 2736 1.8.2.2 yamt RADEON_GMC_BRUSH_SOLID_COLOR | 2737 1.8.2.2 yamt RADEON_GMC_SRC_DATATYPE_COLOR); 2738 1.8.2.2 yamt 2739 1.8.2.2 yamt radeonfb_wait_fifo(sc, 7); 2740 1.8.2.2 yamt PUT32(sc, RADEON_DST_LINE_START, 0); 2741 1.8.2.2 yamt PUT32(sc, RADEON_DST_LINE_END, 0); 2742 1.8.2.2 yamt PUT32(sc, RADEON_DP_BRUSH_FRGD_CLR, 0xffffffff); 2743 1.8.2.2 yamt PUT32(sc, RADEON_DP_BRUSH_BKGD_CLR, 0); 2744 1.8.2.2 yamt PUT32(sc, RADEON_DP_SRC_FRGD_CLR, 0xffffffff); 2745 1.8.2.2 yamt PUT32(sc, RADEON_DP_SRC_BKGD_CLR, 0); 2746 1.8.2.2 yamt PUT32(sc, RADEON_DP_WRITE_MASK, 0xffffffff); 2747 1.8.2.2 yamt 2748 1.8.2.2 yamt radeonfb_engine_idle(sc); 2749 1.8.2.2 yamt } 2750 1.8.2.2 yamt 2751 1.8.2.2 yamt static void 2752 1.8.2.2 yamt radeonfb_engine_reset(struct radeonfb_softc *sc) 2753 1.8.2.2 yamt { 2754 1.8.2.2 yamt uint32_t hpc, rbbm, mclkcntl, clkindex; 2755 1.8.2.2 yamt 2756 1.8.2.2 yamt radeonfb_engine_flush(sc); 2757 1.8.2.2 yamt 2758 1.8.2.2 yamt clkindex = GET32(sc, RADEON_CLOCK_CNTL_INDEX); 2759 1.8.2.2 yamt if (HAS_R300CG(sc)) 2760 1.8.2.2 yamt radeonfb_r300cg_workaround(sc); 2761 1.8.2.2 yamt mclkcntl = GETPLL(sc, RADEON_MCLK_CNTL); 2762 1.8.2.2 yamt 2763 1.8.2.2 yamt /* 2764 1.8.2.2 yamt * According to comments in XFree code, resetting the HDP via 2765 1.8.2.2 yamt * the RBBM_SOFT_RESET can cause bad behavior on some systems. 2766 1.8.2.2 yamt * So we use HOST_PATH_CNTL instead. 2767 1.8.2.2 yamt */ 2768 1.8.2.2 yamt 2769 1.8.2.2 yamt hpc = GET32(sc, RADEON_HOST_PATH_CNTL); 2770 1.8.2.2 yamt rbbm = GET32(sc, RADEON_RBBM_SOFT_RESET); 2771 1.8.2.2 yamt if (IS_R300(sc)) { 2772 1.8.2.2 yamt PUT32(sc, RADEON_RBBM_SOFT_RESET, rbbm | 2773 1.8.2.2 yamt RADEON_SOFT_RESET_CP | 2774 1.8.2.2 yamt RADEON_SOFT_RESET_HI | 2775 1.8.2.2 yamt RADEON_SOFT_RESET_E2); 2776 1.8.2.2 yamt GET32(sc, RADEON_RBBM_SOFT_RESET); 2777 1.8.2.2 yamt PUT32(sc, RADEON_RBBM_SOFT_RESET, 0); 2778 1.8.2.2 yamt /* 2779 1.8.2.2 yamt * XXX: this bit is not defined in any ATI docs I have, 2780 1.8.2.2 yamt * nor in the XFree code, but XFree does it. Why? 2781 1.8.2.2 yamt */ 2782 1.8.2.2 yamt SET32(sc, RADEON_RB2D_DSTCACHE_MODE, (1<<17)); 2783 1.8.2.2 yamt } else { 2784 1.8.2.2 yamt PUT32(sc, RADEON_RBBM_SOFT_RESET, rbbm | 2785 1.8.2.2 yamt RADEON_SOFT_RESET_CP | 2786 1.8.2.2 yamt RADEON_SOFT_RESET_SE | 2787 1.8.2.2 yamt RADEON_SOFT_RESET_RE | 2788 1.8.2.2 yamt RADEON_SOFT_RESET_PP | 2789 1.8.2.2 yamt RADEON_SOFT_RESET_E2 | 2790 1.8.2.2 yamt RADEON_SOFT_RESET_RB); 2791 1.8.2.2 yamt GET32(sc, RADEON_RBBM_SOFT_RESET); 2792 1.8.2.2 yamt PUT32(sc, RADEON_RBBM_SOFT_RESET, rbbm & 2793 1.8.2.2 yamt ~(RADEON_SOFT_RESET_CP | 2794 1.8.2.2 yamt RADEON_SOFT_RESET_SE | 2795 1.8.2.2 yamt RADEON_SOFT_RESET_RE | 2796 1.8.2.2 yamt RADEON_SOFT_RESET_PP | 2797 1.8.2.2 yamt RADEON_SOFT_RESET_E2 | 2798 1.8.2.2 yamt RADEON_SOFT_RESET_RB)); 2799 1.8.2.2 yamt GET32(sc, RADEON_RBBM_SOFT_RESET); 2800 1.8.2.2 yamt } 2801 1.8.2.2 yamt 2802 1.8.2.2 yamt PUT32(sc, RADEON_HOST_PATH_CNTL, hpc | RADEON_HDP_SOFT_RESET); 2803 1.8.2.2 yamt GET32(sc, RADEON_HOST_PATH_CNTL); 2804 1.8.2.2 yamt PUT32(sc, RADEON_HOST_PATH_CNTL, hpc); 2805 1.8.2.2 yamt 2806 1.8.2.2 yamt if (IS_R300(sc)) 2807 1.8.2.2 yamt PUT32(sc, RADEON_RBBM_SOFT_RESET, rbbm); 2808 1.8.2.2 yamt 2809 1.8.2.2 yamt PUT32(sc, RADEON_CLOCK_CNTL_INDEX, clkindex); 2810 1.8.2.2 yamt PUTPLL(sc, RADEON_MCLK_CNTL, mclkcntl); 2811 1.8.2.2 yamt 2812 1.8.2.2 yamt if (HAS_R300CG(sc)) 2813 1.8.2.2 yamt radeonfb_r300cg_workaround(sc); 2814 1.8.2.2 yamt } 2815 1.8.2.2 yamt 2816 1.8.2.2 yamt static int 2817 1.8.2.2 yamt radeonfb_set_curpos(struct radeonfb_display *dp, struct wsdisplay_curpos *pos) 2818 1.8.2.2 yamt { 2819 1.8.2.2 yamt int x, y; 2820 1.8.2.2 yamt 2821 1.8.2.2 yamt x = pos->x; 2822 1.8.2.2 yamt y = pos->y; 2823 1.8.2.2 yamt 2824 1.8.2.2 yamt /* 2825 1.8.2.2 yamt * This doesn't let a cursor move off the screen. I'm not 2826 1.8.2.2 yamt * sure if this will have negative effects for e.g. Xinerama. 2827 1.8.2.2 yamt * I'd guess Xinerama handles it by changing the cursor shape, 2828 1.8.2.2 yamt * but that needs verification. 2829 1.8.2.2 yamt */ 2830 1.8.2.2 yamt if (x >= dp->rd_virtx) 2831 1.8.2.2 yamt x = dp->rd_virtx - 1; 2832 1.8.2.2 yamt if (x < 0) 2833 1.8.2.2 yamt x = 0; 2834 1.8.2.2 yamt if (y >= dp->rd_virty) 2835 1.8.2.2 yamt y = dp->rd_virty - 1; 2836 1.8.2.2 yamt if (y < 0) 2837 1.8.2.2 yamt y = 0; 2838 1.8.2.2 yamt 2839 1.8.2.2 yamt dp->rd_cursor.rc_pos.x = x; 2840 1.8.2.2 yamt dp->rd_cursor.rc_pos.y = y; 2841 1.8.2.2 yamt 2842 1.8.2.2 yamt radeonfb_cursor_position(dp); 2843 1.8.2.2 yamt return 0; 2844 1.8.2.2 yamt } 2845 1.8.2.2 yamt 2846 1.8.2.2 yamt static int 2847 1.8.2.2 yamt radeonfb_set_cursor(struct radeonfb_display *dp, struct wsdisplay_cursor *wc) 2848 1.8.2.2 yamt { 2849 1.8.2.2 yamt unsigned flags; 2850 1.8.2.2 yamt 2851 1.8.2.2 yamt uint8_t r[2], g[2], b[2]; 2852 1.8.2.2 yamt unsigned index, count; 2853 1.8.2.2 yamt int i, err; 2854 1.8.2.2 yamt int pitch, size; 2855 1.8.2.2 yamt struct radeonfb_cursor nc; 2856 1.8.2.2 yamt 2857 1.8.2.2 yamt flags = wc->which; 2858 1.8.2.2 yamt 2859 1.8.2.2 yamt /* copy old values */ 2860 1.8.2.2 yamt nc = dp->rd_cursor; 2861 1.8.2.2 yamt 2862 1.8.2.2 yamt if (flags & WSDISPLAY_CURSOR_DOCMAP) { 2863 1.8.2.2 yamt index = wc->cmap.index; 2864 1.8.2.2 yamt count = wc->cmap.count; 2865 1.8.2.2 yamt 2866 1.8.2.2 yamt if (index >= 2 || (index + count) > 2) 2867 1.8.2.2 yamt return EINVAL; 2868 1.8.2.2 yamt 2869 1.8.2.2 yamt err = copyin(wc->cmap.red, &r[index], count); 2870 1.8.2.2 yamt if (err) 2871 1.8.2.2 yamt return err; 2872 1.8.2.2 yamt err = copyin(wc->cmap.green, &g[index], count); 2873 1.8.2.2 yamt if (err) 2874 1.8.2.2 yamt return err; 2875 1.8.2.2 yamt err = copyin(wc->cmap.blue, &b[index], count); 2876 1.8.2.2 yamt if (err) 2877 1.8.2.2 yamt return err; 2878 1.8.2.2 yamt 2879 1.8.2.2 yamt for (i = index; i < index + count; i++) { 2880 1.8.2.2 yamt nc.rc_cmap[i] = 2881 1.8.2.2 yamt (r[i] << 16) + (g[i] << 8) + (b[i] << 0); 2882 1.8.2.2 yamt } 2883 1.8.2.2 yamt } 2884 1.8.2.2 yamt 2885 1.8.2.2 yamt if (flags & WSDISPLAY_CURSOR_DOSHAPE) { 2886 1.8.2.2 yamt if ((wc->size.x > RADEON_CURSORMAXX) || 2887 1.8.2.2 yamt (wc->size.y > RADEON_CURSORMAXY)) 2888 1.8.2.2 yamt return EINVAL; 2889 1.8.2.2 yamt 2890 1.8.2.2 yamt /* figure bytes per line */ 2891 1.8.2.2 yamt pitch = (wc->size.x + 7) / 8; 2892 1.8.2.2 yamt size = pitch * wc->size.y; 2893 1.8.2.2 yamt 2894 1.8.2.2 yamt /* clear the old cursor and mask */ 2895 1.8.2.2 yamt memset(nc.rc_image, 0, 512); 2896 1.8.2.2 yamt memset(nc.rc_mask, 0, 512); 2897 1.8.2.2 yamt 2898 1.8.2.2 yamt nc.rc_size = wc->size; 2899 1.8.2.2 yamt 2900 1.8.2.2 yamt if ((err = copyin(wc->image, nc.rc_image, size)) != 0) 2901 1.8.2.2 yamt return err; 2902 1.8.2.2 yamt 2903 1.8.2.2 yamt if ((err = copyin(wc->mask, nc.rc_mask, size)) != 0) 2904 1.8.2.2 yamt return err; 2905 1.8.2.2 yamt } 2906 1.8.2.2 yamt 2907 1.8.2.2 yamt if (flags & WSDISPLAY_CURSOR_DOHOT) { 2908 1.8.2.2 yamt nc.rc_hot = wc->hot; 2909 1.8.2.2 yamt if (nc.rc_hot.x >= nc.rc_size.x) 2910 1.8.2.2 yamt nc.rc_hot.x = nc.rc_size.x - 1; 2911 1.8.2.2 yamt if (nc.rc_hot.y >= nc.rc_size.y) 2912 1.8.2.2 yamt nc.rc_hot.y = nc.rc_size.y - 1; 2913 1.8.2.2 yamt } 2914 1.8.2.2 yamt 2915 1.8.2.2 yamt if (flags & WSDISPLAY_CURSOR_DOPOS) { 2916 1.8.2.2 yamt nc.rc_pos = wc->pos; 2917 1.8.2.2 yamt if (nc.rc_pos.x >= dp->rd_virtx) 2918 1.8.2.2 yamt nc.rc_pos.x = dp->rd_virtx - 1; 2919 1.8.2.2 yamt #if 0 2920 1.8.2.2 yamt if (nc.rc_pos.x < 0) 2921 1.8.2.2 yamt nc.rc_pos.x = 0; 2922 1.8.2.2 yamt #endif 2923 1.8.2.2 yamt if (nc.rc_pos.y >= dp->rd_virty) 2924 1.8.2.2 yamt nc.rc_pos.y = dp->rd_virty - 1; 2925 1.8.2.2 yamt #if 0 2926 1.8.2.2 yamt if (nc.rc_pos.y < 0) 2927 1.8.2.2 yamt nc.rc_pos.y = 0; 2928 1.8.2.2 yamt #endif 2929 1.8.2.2 yamt } 2930 1.8.2.2 yamt if (flags & WSDISPLAY_CURSOR_DOCUR) { 2931 1.8.2.2 yamt nc.rc_visible = wc->enable; 2932 1.8.2.2 yamt } 2933 1.8.2.2 yamt 2934 1.8.2.2 yamt dp->rd_cursor = nc; 2935 1.8.2.2 yamt radeonfb_cursor_update(dp, wc->which); 2936 1.8.2.2 yamt 2937 1.8.2.2 yamt return 0; 2938 1.8.2.2 yamt } 2939 1.8.2.2 yamt 2940 1.8.2.2 yamt /* 2941 1.8.2.2 yamt * Change the cursor shape. Call this with the cursor locked to avoid 2942 1.8.2.2 yamt * flickering/tearing. 2943 1.8.2.2 yamt */ 2944 1.8.2.2 yamt static void 2945 1.8.2.2 yamt radeonfb_cursor_shape(struct radeonfb_display *dp) 2946 1.8.2.2 yamt { 2947 1.8.2.2 yamt uint8_t and[512], xor[512]; 2948 1.8.2.2 yamt int i, j, src, dst, pitch; 2949 1.8.2.2 yamt const uint8_t *msk = dp->rd_cursor.rc_mask; 2950 1.8.2.2 yamt const uint8_t *img = dp->rd_cursor.rc_image; 2951 1.8.2.2 yamt 2952 1.8.2.2 yamt /* 2953 1.8.2.2 yamt * Radeon cursor data interleaves one line of AND data followed 2954 1.8.2.2 yamt * by a line of XOR data. (Each line corresponds to a whole hardware 2955 1.8.2.2 yamt * pitch - i.e. 64 pixels or 8 bytes.) 2956 1.8.2.2 yamt * 2957 1.8.2.2 yamt * The cursor is displayed using the following table: 2958 1.8.2.2 yamt * 2959 1.8.2.2 yamt * AND XOR Result 2960 1.8.2.2 yamt * ---------------------- 2961 1.8.2.2 yamt * 0 0 Cursor color 0 2962 1.8.2.2 yamt * 0 1 Cursor color 1 2963 1.8.2.2 yamt * 1 0 Transparent 2964 1.8.2.2 yamt * 1 1 Complement of background 2965 1.8.2.2 yamt * 2966 1.8.2.2 yamt * Our masks are therefore different from what we were passed. 2967 1.8.2.2 yamt * Passed in, I'm assuming the data represents either color 0 or 1, 2968 1.8.2.2 yamt * and a mask, so the passed in table looks like: 2969 1.8.2.2 yamt * 2970 1.8.2.2 yamt * IMG Mask Result 2971 1.8.2.2 yamt * ----------------------- 2972 1.8.2.2 yamt * 0 0 Transparent 2973 1.8.2.2 yamt * 0 1 Cursor color 0 2974 1.8.2.2 yamt * 1 0 Transparent 2975 1.8.2.2 yamt * 1 1 Cursor color 1 2976 1.8.2.2 yamt * 2977 1.8.2.2 yamt * IF mask bit == 1, AND = 0, XOR = color. 2978 1.8.2.2 yamt * IF mask bit == 0, AND = 1, XOR = 0. 2979 1.8.2.2 yamt * 2980 1.8.2.2 yamt * hence: AND = ~(mask); XOR = color & ~(mask); 2981 1.8.2.2 yamt */ 2982 1.8.2.2 yamt 2983 1.8.2.2 yamt pitch = ((dp->rd_cursor.rc_size.x + 7) / 8); 2984 1.8.2.2 yamt 2985 1.8.2.2 yamt /* start by assuming all bits are transparent */ 2986 1.8.2.2 yamt memset(and, 0xff, 512); 2987 1.8.2.2 yamt memset(xor, 0x00, 512); 2988 1.8.2.2 yamt 2989 1.8.2.2 yamt src = 0; 2990 1.8.2.2 yamt dst = 0; 2991 1.8.2.2 yamt for (i = 0; i < 64; i++) { 2992 1.8.2.2 yamt for (j = 0; j < 64; j += 8) { 2993 1.8.2.2 yamt if ((i < dp->rd_cursor.rc_size.y) && 2994 1.8.2.2 yamt (j < dp->rd_cursor.rc_size.x)) { 2995 1.8.2.2 yamt 2996 1.8.2.2 yamt /* take care to leave odd bits alone */ 2997 1.8.2.2 yamt and[dst] &= ~(msk[src]); 2998 1.8.2.2 yamt xor[dst] = img[src] & msk[src]; 2999 1.8.2.2 yamt src++; 3000 1.8.2.2 yamt } 3001 1.8.2.2 yamt dst++; 3002 1.8.2.2 yamt } 3003 1.8.2.2 yamt } 3004 1.8.2.2 yamt 3005 1.8.2.2 yamt /* copy the image into place */ 3006 1.8.2.2 yamt for (i = 0; i < 64; i++) { 3007 1.8.2.2 yamt memcpy((uint8_t *)dp->rd_curptr + (i * 16), 3008 1.8.2.2 yamt &and[i * 8], 8); 3009 1.8.2.2 yamt memcpy((uint8_t *)dp->rd_curptr + (i * 16) + 8, 3010 1.8.2.2 yamt &xor[i * 8], 8); 3011 1.8.2.2 yamt } 3012 1.8.2.2 yamt } 3013 1.8.2.2 yamt 3014 1.8.2.2 yamt static void 3015 1.8.2.2 yamt radeonfb_cursor_position(struct radeonfb_display *dp) 3016 1.8.2.2 yamt { 3017 1.8.2.2 yamt struct radeonfb_softc *sc = dp->rd_softc; 3018 1.8.2.2 yamt uint32_t offset, hvoff, hvpos; /* registers */ 3019 1.8.2.2 yamt uint32_t coff; /* cursor offset */ 3020 1.8.2.2 yamt int i, x, y, xoff, yoff, crtcoff; 3021 1.8.2.2 yamt 3022 1.8.2.2 yamt /* 3023 1.8.2.2 yamt * XXX: this also needs to handle pan/scan 3024 1.8.2.2 yamt */ 3025 1.8.2.2 yamt for (i = 0; i < dp->rd_ncrtcs; i++) { 3026 1.8.2.2 yamt 3027 1.8.2.2 yamt struct radeonfb_crtc *rcp = &dp->rd_crtcs[i]; 3028 1.8.2.2 yamt 3029 1.8.2.2 yamt if (rcp->rc_number) { 3030 1.8.2.2 yamt offset = RADEON_CUR2_OFFSET; 3031 1.8.2.2 yamt hvoff = RADEON_CUR2_HORZ_VERT_OFF; 3032 1.8.2.2 yamt hvpos = RADEON_CUR2_HORZ_VERT_POSN; 3033 1.8.2.2 yamt crtcoff = RADEON_CRTC2_OFFSET; 3034 1.8.2.2 yamt } else { 3035 1.8.2.2 yamt offset = RADEON_CUR_OFFSET; 3036 1.8.2.2 yamt hvoff = RADEON_CUR_HORZ_VERT_OFF; 3037 1.8.2.2 yamt hvpos = RADEON_CUR_HORZ_VERT_POSN; 3038 1.8.2.2 yamt crtcoff = RADEON_CRTC_OFFSET; 3039 1.8.2.2 yamt } 3040 1.8.2.2 yamt 3041 1.8.2.2 yamt x = dp->rd_cursor.rc_pos.x; 3042 1.8.2.2 yamt y = dp->rd_cursor.rc_pos.y; 3043 1.8.2.2 yamt 3044 1.8.2.2 yamt while (y < rcp->rc_yoffset) { 3045 1.8.2.2 yamt rcp->rc_yoffset -= RADEON_PANINCREMENT; 3046 1.8.2.2 yamt } 3047 1.8.2.2 yamt while (y >= (rcp->rc_yoffset + rcp->rc_videomode.vdisplay)) { 3048 1.8.2.2 yamt rcp->rc_yoffset += RADEON_PANINCREMENT; 3049 1.8.2.2 yamt } 3050 1.8.2.2 yamt while (x < rcp->rc_xoffset) { 3051 1.8.2.2 yamt rcp->rc_xoffset -= RADEON_PANINCREMENT; 3052 1.8.2.2 yamt } 3053 1.8.2.2 yamt while (x >= (rcp->rc_xoffset + rcp->rc_videomode.hdisplay)) { 3054 1.8.2.2 yamt rcp->rc_xoffset += RADEON_PANINCREMENT; 3055 1.8.2.2 yamt } 3056 1.8.2.2 yamt 3057 1.8.2.2 yamt /* adjust for the cursor's hotspot */ 3058 1.8.2.2 yamt x -= dp->rd_cursor.rc_hot.x; 3059 1.8.2.2 yamt y -= dp->rd_cursor.rc_hot.y; 3060 1.8.2.2 yamt xoff = yoff = 0; 3061 1.8.2.2 yamt 3062 1.8.2.2 yamt if (x >= dp->rd_virtx) 3063 1.8.2.2 yamt x = dp->rd_virtx - 1; 3064 1.8.2.2 yamt if (y >= dp->rd_virty) 3065 1.8.2.2 yamt y = dp->rd_virty - 1; 3066 1.8.2.2 yamt 3067 1.8.2.2 yamt /* now adjust cursor so it is relative to viewport */ 3068 1.8.2.2 yamt x -= rcp->rc_xoffset; 3069 1.8.2.2 yamt y -= rcp->rc_yoffset; 3070 1.8.2.2 yamt 3071 1.8.2.2 yamt /* 3072 1.8.2.2 yamt * no need to check for fall off, because we should 3073 1.8.2.2 yamt * never move off the screen entirely! 3074 1.8.2.2 yamt */ 3075 1.8.2.2 yamt coff = 0; 3076 1.8.2.2 yamt if (x < 0) { 3077 1.8.2.2 yamt xoff = -x; 3078 1.8.2.2 yamt x = 0; 3079 1.8.2.2 yamt } 3080 1.8.2.2 yamt if (y < 0) { 3081 1.8.2.2 yamt yoff = -y; 3082 1.8.2.2 yamt y = 0; 3083 1.8.2.2 yamt coff = (yoff * 2) * 8; 3084 1.8.2.2 yamt } 3085 1.8.2.2 yamt 3086 1.8.2.2 yamt /* pan the display */ 3087 1.8.2.2 yamt PUT32(sc, crtcoff, (rcp->rc_yoffset * dp->rd_stride) + 3088 1.8.2.2 yamt rcp->rc_xoffset); 3089 1.8.2.2 yamt 3090 1.8.2.2 yamt PUT32(sc, offset, (dp->rd_curoff + coff) | RADEON_CUR_LOCK); 3091 1.8.2.2 yamt PUT32(sc, hvoff, (xoff << 16) | (yoff) | RADEON_CUR_LOCK); 3092 1.8.2.2 yamt /* NB: this unlocks the cursor */ 3093 1.8.2.2 yamt PUT32(sc, hvpos, (x << 16) | y); 3094 1.8.2.2 yamt } 3095 1.8.2.2 yamt } 3096 1.8.2.2 yamt 3097 1.8.2.2 yamt static void 3098 1.8.2.2 yamt radeonfb_cursor_visible(struct radeonfb_display *dp) 3099 1.8.2.2 yamt { 3100 1.8.2.2 yamt int i; 3101 1.8.2.2 yamt uint32_t gencntl, bit; 3102 1.8.2.2 yamt 3103 1.8.2.2 yamt for (i = 0; i < dp->rd_ncrtcs; i++) { 3104 1.8.2.2 yamt if (dp->rd_crtcs[i].rc_number) { 3105 1.8.2.2 yamt gencntl = RADEON_CRTC2_GEN_CNTL; 3106 1.8.2.2 yamt bit = RADEON_CRTC2_CUR_EN; 3107 1.8.2.2 yamt } else { 3108 1.8.2.2 yamt gencntl = RADEON_CRTC_GEN_CNTL; 3109 1.8.2.2 yamt bit = RADEON_CRTC_CUR_EN; 3110 1.8.2.2 yamt } 3111 1.8.2.2 yamt 3112 1.8.2.2 yamt if (dp->rd_cursor.rc_visible) 3113 1.8.2.2 yamt SET32(dp->rd_softc, gencntl, bit); 3114 1.8.2.2 yamt else 3115 1.8.2.2 yamt CLR32(dp->rd_softc, gencntl, bit); 3116 1.8.2.2 yamt } 3117 1.8.2.2 yamt } 3118 1.8.2.2 yamt 3119 1.8.2.2 yamt static void 3120 1.8.2.2 yamt radeonfb_cursor_cmap(struct radeonfb_display *dp) 3121 1.8.2.2 yamt { 3122 1.8.2.2 yamt int i; 3123 1.8.2.2 yamt uint32_t c0reg, c1reg; 3124 1.8.2.2 yamt struct radeonfb_softc *sc = dp->rd_softc; 3125 1.8.2.2 yamt 3126 1.8.2.2 yamt for (i = 0; i < dp->rd_ncrtcs; i++) { 3127 1.8.2.2 yamt if (dp->rd_crtcs[i].rc_number) { 3128 1.8.2.2 yamt c0reg = RADEON_CUR2_CLR0; 3129 1.8.2.2 yamt c1reg = RADEON_CUR2_CLR1; 3130 1.8.2.2 yamt } else { 3131 1.8.2.2 yamt c0reg = RADEON_CUR_CLR0; 3132 1.8.2.2 yamt c1reg = RADEON_CUR_CLR1; 3133 1.8.2.2 yamt } 3134 1.8.2.2 yamt 3135 1.8.2.2 yamt PUT32(sc, c0reg, dp->rd_cursor.rc_cmap[0]); 3136 1.8.2.2 yamt PUT32(sc, c1reg, dp->rd_cursor.rc_cmap[1]); 3137 1.8.2.2 yamt } 3138 1.8.2.2 yamt } 3139 1.8.2.2 yamt 3140 1.8.2.2 yamt static void 3141 1.8.2.2 yamt radeonfb_cursor_update(struct radeonfb_display *dp, unsigned which) 3142 1.8.2.2 yamt { 3143 1.8.2.2 yamt struct radeonfb_softc *sc; 3144 1.8.2.2 yamt int i; 3145 1.8.2.2 yamt 3146 1.8.2.2 yamt sc = dp->rd_softc; 3147 1.8.2.2 yamt for (i = 0; i < dp->rd_ncrtcs; i++) { 3148 1.8.2.2 yamt if (dp->rd_crtcs[i].rc_number) { 3149 1.8.2.2 yamt SET32(sc, RADEON_CUR2_OFFSET, RADEON_CUR_LOCK); 3150 1.8.2.2 yamt } else { 3151 1.8.2.2 yamt SET32(sc, RADEON_CUR_OFFSET,RADEON_CUR_LOCK); 3152 1.8.2.2 yamt } 3153 1.8.2.2 yamt } 3154 1.8.2.2 yamt 3155 1.8.2.2 yamt if (which & WSDISPLAY_CURSOR_DOCMAP) 3156 1.8.2.2 yamt radeonfb_cursor_cmap(dp); 3157 1.8.2.2 yamt 3158 1.8.2.2 yamt if (which & WSDISPLAY_CURSOR_DOSHAPE) 3159 1.8.2.2 yamt radeonfb_cursor_shape(dp); 3160 1.8.2.2 yamt 3161 1.8.2.2 yamt if (which & WSDISPLAY_CURSOR_DOCUR) 3162 1.8.2.2 yamt radeonfb_cursor_visible(dp); 3163 1.8.2.2 yamt 3164 1.8.2.2 yamt /* this one is unconditional, because it updates other stuff */ 3165 1.8.2.2 yamt radeonfb_cursor_position(dp); 3166 1.8.2.2 yamt } 3167 1.8.2.2 yamt 3168 1.8.2.2 yamt static struct videomode * 3169 1.8.2.2 yamt radeonfb_best_refresh(struct videomode *m1, struct videomode *m2) 3170 1.8.2.2 yamt { 3171 1.8.2.2 yamt int r1, r2; 3172 1.8.2.2 yamt 3173 1.8.2.2 yamt /* otherwise pick the higher refresh rate */ 3174 1.8.2.2 yamt r1 = DIVIDE(DIVIDE(m1->dot_clock, m1->htotal), m1->vtotal); 3175 1.8.2.2 yamt r2 = DIVIDE(DIVIDE(m2->dot_clock, m2->htotal), m2->vtotal); 3176 1.8.2.2 yamt 3177 1.8.2.2 yamt return (r1 < r2 ? m2 : m1); 3178 1.8.2.2 yamt } 3179 1.8.2.2 yamt 3180 1.8.2.2 yamt static const struct videomode * 3181 1.8.2.3 yamt radeonfb_port_mode(struct radeonfb_softc *sc, struct radeonfb_port *rp, 3182 1.8.2.3 yamt int x, int y) 3183 1.8.2.2 yamt { 3184 1.8.2.2 yamt struct edid_info *ep = &rp->rp_edid; 3185 1.8.2.2 yamt struct videomode *vmp = NULL; 3186 1.8.2.2 yamt int i; 3187 1.8.2.2 yamt 3188 1.8.2.2 yamt if (!rp->rp_edid_valid) { 3189 1.8.2.2 yamt /* fallback to safe mode */ 3190 1.8.2.3 yamt return radeonfb_modelookup(sc->sc_defaultmode); 3191 1.8.2.2 yamt } 3192 1.8.2.2 yamt 3193 1.8.2.2 yamt /* always choose the preferred mode first! */ 3194 1.8.2.2 yamt if (ep->edid_preferred_mode) { 3195 1.8.2.2 yamt 3196 1.8.2.2 yamt /* XXX: add auto-stretching support for native mode */ 3197 1.8.2.2 yamt 3198 1.8.2.2 yamt /* this may want panning to occur, btw */ 3199 1.8.2.2 yamt if ((ep->edid_preferred_mode->hdisplay <= x) && 3200 1.8.2.2 yamt (ep->edid_preferred_mode->vdisplay <= y)) 3201 1.8.2.2 yamt return ep->edid_preferred_mode; 3202 1.8.2.2 yamt } 3203 1.8.2.2 yamt 3204 1.8.2.2 yamt for (i = 0; i < ep->edid_nmodes; i++) { 3205 1.8.2.2 yamt /* 3206 1.8.2.2 yamt * We elect to pick a resolution that is too large for 3207 1.8.2.2 yamt * the monitor than one that is too small. This means 3208 1.8.2.2 yamt * that we will prefer to pan rather than to try to 3209 1.8.2.2 yamt * center a smaller display on a larger screen. In 3210 1.8.2.2 yamt * practice, this shouldn't matter because if a 3211 1.8.2.2 yamt * monitor can support a larger resolution, it can 3212 1.8.2.2 yamt * probably also support the smaller. A specific 3213 1.8.2.2 yamt * exception is fixed format panels, but hopefully 3214 1.8.2.2 yamt * they are properly dealt with by the "autostretch" 3215 1.8.2.2 yamt * logic above. 3216 1.8.2.2 yamt */ 3217 1.8.2.2 yamt if ((ep->edid_modes[i].hdisplay > x) || 3218 1.8.2.2 yamt (ep->edid_modes[i].vdisplay > y)) { 3219 1.8.2.2 yamt continue; 3220 1.8.2.2 yamt } 3221 1.8.2.2 yamt 3222 1.8.2.2 yamt /* 3223 1.8.2.2 yamt * at this point, the display mode is no larger than 3224 1.8.2.2 yamt * what we've requested. 3225 1.8.2.2 yamt */ 3226 1.8.2.2 yamt if (vmp == NULL) 3227 1.8.2.2 yamt vmp = &ep->edid_modes[i]; 3228 1.8.2.2 yamt 3229 1.8.2.2 yamt /* eliminate smaller modes */ 3230 1.8.2.2 yamt if ((vmp->hdisplay >= ep->edid_modes[i].hdisplay) || 3231 1.8.2.2 yamt (vmp->vdisplay >= ep->edid_modes[i].vdisplay)) 3232 1.8.2.2 yamt continue; 3233 1.8.2.2 yamt 3234 1.8.2.2 yamt if ((vmp->hdisplay < ep->edid_modes[i].hdisplay) || 3235 1.8.2.2 yamt (vmp->vdisplay < ep->edid_modes[i].vdisplay)) { 3236 1.8.2.2 yamt vmp = &ep->edid_modes[i]; 3237 1.8.2.2 yamt continue; 3238 1.8.2.2 yamt } 3239 1.8.2.2 yamt 3240 1.8.2.2 yamt KASSERT(vmp->hdisplay == ep->edid_modes[i].hdisplay); 3241 1.8.2.2 yamt KASSERT(vmp->vdisplay == ep->edid_modes[i].vdisplay); 3242 1.8.2.2 yamt 3243 1.8.2.2 yamt vmp = radeonfb_best_refresh(vmp, &ep->edid_modes[i]); 3244 1.8.2.2 yamt } 3245 1.8.2.2 yamt 3246 1.8.2.3 yamt return (vmp ? vmp : radeonfb_modelookup(sc->sc_defaultmode)); 3247 1.8.2.2 yamt } 3248 1.8.2.2 yamt 3249 1.8.2.2 yamt static int 3250 1.8.2.2 yamt radeonfb_hasres(struct videomode *list, int nlist, int x, int y) 3251 1.8.2.2 yamt { 3252 1.8.2.2 yamt int i; 3253 1.8.2.2 yamt 3254 1.8.2.2 yamt for (i = 0; i < nlist; i++) { 3255 1.8.2.2 yamt if ((x == list[i].hdisplay) && 3256 1.8.2.2 yamt (y == list[i].vdisplay)) { 3257 1.8.2.2 yamt return 1; 3258 1.8.2.2 yamt } 3259 1.8.2.2 yamt } 3260 1.8.2.2 yamt return 0; 3261 1.8.2.2 yamt } 3262 1.8.2.2 yamt 3263 1.8.2.2 yamt static void 3264 1.8.2.2 yamt radeonfb_pickres(struct radeonfb_display *dp, uint16_t *x, uint16_t *y, 3265 1.8.2.2 yamt int pan) 3266 1.8.2.2 yamt { 3267 1.8.2.2 yamt struct radeonfb_port *rp; 3268 1.8.2.2 yamt struct edid_info *ep; 3269 1.8.2.2 yamt int i, j; 3270 1.8.2.2 yamt 3271 1.8.2.2 yamt *x = 0; 3272 1.8.2.2 yamt *y = 0; 3273 1.8.2.2 yamt 3274 1.8.2.2 yamt if (pan) { 3275 1.8.2.2 yamt for (i = 0; i < dp->rd_ncrtcs; i++) { 3276 1.8.2.2 yamt rp = dp->rd_crtcs[i].rc_port; 3277 1.8.2.2 yamt ep = &rp->rp_edid; 3278 1.8.2.2 yamt if (!rp->rp_edid_valid) { 3279 1.8.2.2 yamt /* monitor not present */ 3280 1.8.2.2 yamt continue; 3281 1.8.2.2 yamt } 3282 1.8.2.2 yamt 3283 1.8.2.2 yamt /* 3284 1.8.2.2 yamt * For now we are ignoring "conflict" that 3285 1.8.2.2 yamt * could occur when mixing some modes like 3286 1.8.2.2 yamt * 1280x1024 and 1400x800. It isn't clear 3287 1.8.2.2 yamt * which is better, so the first one wins. 3288 1.8.2.2 yamt */ 3289 1.8.2.2 yamt for (j = 0; j < ep->edid_nmodes; j++) { 3290 1.8.2.2 yamt /* 3291 1.8.2.2 yamt * ignore resolutions that are too big for 3292 1.8.2.2 yamt * the radeon 3293 1.8.2.2 yamt */ 3294 1.8.2.2 yamt if (ep->edid_modes[j].hdisplay > 3295 1.8.2.2 yamt dp->rd_softc->sc_maxx) 3296 1.8.2.2 yamt continue; 3297 1.8.2.2 yamt if (ep->edid_modes[j].vdisplay > 3298 1.8.2.2 yamt dp->rd_softc->sc_maxy) 3299 1.8.2.2 yamt continue; 3300 1.8.2.2 yamt 3301 1.8.2.2 yamt /* 3302 1.8.2.2 yamt * pick largest resolution, the 3303 1.8.2.2 yamt * smaller monitor will pan 3304 1.8.2.2 yamt */ 3305 1.8.2.2 yamt if ((ep->edid_modes[j].hdisplay >= *x) && 3306 1.8.2.2 yamt (ep->edid_modes[j].vdisplay >= *y)) { 3307 1.8.2.2 yamt *x = ep->edid_modes[j].hdisplay; 3308 1.8.2.2 yamt *y = ep->edid_modes[j].vdisplay; 3309 1.8.2.2 yamt } 3310 1.8.2.2 yamt } 3311 1.8.2.2 yamt } 3312 1.8.2.2 yamt 3313 1.8.2.2 yamt } else { 3314 1.8.2.2 yamt struct videomode modes[64]; 3315 1.8.2.2 yamt int nmodes = 0; 3316 1.8.2.2 yamt int valid = 0; 3317 1.8.2.2 yamt 3318 1.8.2.2 yamt for (i = 0; i < dp->rd_ncrtcs; i++) { 3319 1.8.2.2 yamt /* 3320 1.8.2.2 yamt * pick the largest resolution in common. 3321 1.8.2.2 yamt */ 3322 1.8.2.2 yamt rp = dp->rd_crtcs[i].rc_port; 3323 1.8.2.2 yamt ep = &rp->rp_edid; 3324 1.8.2.2 yamt 3325 1.8.2.2 yamt if (!rp->rp_edid_valid) 3326 1.8.2.2 yamt continue; 3327 1.8.2.2 yamt 3328 1.8.2.2 yamt if (!valid) { 3329 1.8.2.2 yamt /* initialize starting list */ 3330 1.8.2.2 yamt for (j = 0; j < ep->edid_nmodes; j++) { 3331 1.8.2.2 yamt /* 3332 1.8.2.2 yamt * ignore resolutions that are 3333 1.8.2.2 yamt * too big for the radeon 3334 1.8.2.2 yamt */ 3335 1.8.2.2 yamt if (ep->edid_modes[j].hdisplay > 3336 1.8.2.2 yamt dp->rd_softc->sc_maxx) 3337 1.8.2.2 yamt continue; 3338 1.8.2.2 yamt if (ep->edid_modes[j].vdisplay > 3339 1.8.2.2 yamt dp->rd_softc->sc_maxy) 3340 1.8.2.2 yamt continue; 3341 1.8.2.2 yamt 3342 1.8.2.2 yamt modes[nmodes] = ep->edid_modes[j]; 3343 1.8.2.2 yamt nmodes++; 3344 1.8.2.2 yamt } 3345 1.8.2.2 yamt valid = 1; 3346 1.8.2.2 yamt } else { 3347 1.8.2.2 yamt /* merge into preexisting list */ 3348 1.8.2.2 yamt for (j = 0; j < nmodes; j++) { 3349 1.8.2.2 yamt if (!radeonfb_hasres(ep->edid_modes, 3350 1.8.2.2 yamt ep->edid_nmodes, 3351 1.8.2.2 yamt modes[j].hdisplay, 3352 1.8.2.2 yamt modes[j].vdisplay)) { 3353 1.8.2.2 yamt modes[j] = modes[nmodes]; 3354 1.8.2.2 yamt j--; 3355 1.8.2.2 yamt nmodes--; 3356 1.8.2.2 yamt } 3357 1.8.2.2 yamt } 3358 1.8.2.2 yamt } 3359 1.8.2.2 yamt } 3360 1.8.2.2 yamt 3361 1.8.2.2 yamt /* now we have to pick from the merged list */ 3362 1.8.2.2 yamt for (i = 0; i < nmodes; i++) { 3363 1.8.2.2 yamt if ((modes[i].hdisplay >= *x) && 3364 1.8.2.2 yamt (modes[i].vdisplay >= *y)) { 3365 1.8.2.2 yamt *x = modes[i].hdisplay; 3366 1.8.2.2 yamt *y = modes[i].vdisplay; 3367 1.8.2.2 yamt } 3368 1.8.2.2 yamt } 3369 1.8.2.2 yamt } 3370 1.8.2.2 yamt 3371 1.8.2.2 yamt if ((*x == 0) || (*y == 0)) { 3372 1.8.2.2 yamt /* fallback to safe mode */ 3373 1.8.2.2 yamt *x = 640; 3374 1.8.2.2 yamt *y = 480; 3375 1.8.2.2 yamt } 3376 1.8.2.2 yamt } 3377 1.8.2.3 yamt 3378 1.8.2.4 yamt /* 3379 1.8.2.4 yamt * backlight levels are linear on: 3380 1.8.2.4 yamt * - RV200, RV250, RV280, RV350 3381 1.8.2.4 yamt * - but NOT on PowerBook4,3 6,3 6,5 3382 1.8.2.4 yamt * according to Linux' radeonfb 3383 1.8.2.4 yamt */ 3384 1.8.2.3 yamt 3385 1.8.2.3 yamt /* Get the current backlight level for the display. */ 3386 1.8.2.3 yamt 3387 1.8.2.3 yamt static int 3388 1.8.2.3 yamt radeonfb_get_backlight(struct radeonfb_display *dp) 3389 1.8.2.3 yamt { 3390 1.8.2.3 yamt int s; 3391 1.8.2.3 yamt uint32_t level; 3392 1.8.2.3 yamt 3393 1.8.2.3 yamt s = spltty(); 3394 1.8.2.3 yamt 3395 1.8.2.3 yamt level = radeonfb_get32(dp->rd_softc, RADEON_LVDS_GEN_CNTL); 3396 1.8.2.3 yamt level &= RADEON_LVDS_BL_MOD_LEV_MASK; 3397 1.8.2.3 yamt level >>= RADEON_LVDS_BL_MOD_LEV_SHIFT; 3398 1.8.2.3 yamt 3399 1.8.2.3 yamt /* 3400 1.8.2.3 yamt * On some chips, we should negate the backlight level. 3401 1.8.2.3 yamt * XXX Find out on which chips. 3402 1.8.2.3 yamt */ 3403 1.8.2.4 yamt if (dp->rd_softc->sc_flags & RFB_INV_BLIGHT) 3404 1.8.2.3 yamt level = RADEONFB_BACKLIGHT_MAX - level; 3405 1.8.2.3 yamt 3406 1.8.2.3 yamt splx(s); 3407 1.8.2.3 yamt 3408 1.8.2.3 yamt return level; 3409 1.8.2.3 yamt } 3410 1.8.2.3 yamt 3411 1.8.2.3 yamt /* Set the backlight to the given level for the display. */ 3412 1.8.2.3 yamt 3413 1.8.2.3 yamt static int 3414 1.8.2.3 yamt radeonfb_set_backlight(struct radeonfb_display *dp, int level) 3415 1.8.2.3 yamt { 3416 1.8.2.3 yamt struct radeonfb_softc *sc; 3417 1.8.2.3 yamt int rlevel, s; 3418 1.8.2.3 yamt uint32_t lvds; 3419 1.8.2.3 yamt 3420 1.8.2.3 yamt s = spltty(); 3421 1.8.2.3 yamt 3422 1.8.2.3 yamt if (level < 0) 3423 1.8.2.3 yamt level = 0; 3424 1.8.2.3 yamt else if (level >= RADEONFB_BACKLIGHT_MAX) 3425 1.8.2.3 yamt level = RADEONFB_BACKLIGHT_MAX; 3426 1.8.2.3 yamt 3427 1.8.2.3 yamt sc = dp->rd_softc; 3428 1.8.2.3 yamt 3429 1.8.2.3 yamt /* On some chips, we should negate the backlight level. */ 3430 1.8.2.4 yamt if (dp->rd_softc->sc_flags & RFB_INV_BLIGHT) { 3431 1.8.2.3 yamt rlevel = RADEONFB_BACKLIGHT_MAX - level; 3432 1.8.2.4 yamt } else 3433 1.8.2.3 yamt rlevel = level; 3434 1.8.2.3 yamt 3435 1.8.2.3 yamt callout_stop(&dp->rd_bl_lvds_co); 3436 1.8.2.3 yamt radeonfb_engine_idle(sc); 3437 1.8.2.3 yamt 3438 1.8.2.3 yamt /* 3439 1.8.2.3 yamt * Turn off the display if the backlight is set to 0, since the 3440 1.8.2.3 yamt * display is useless without backlight anyway. 3441 1.8.2.3 yamt */ 3442 1.8.2.3 yamt if (level == 0) 3443 1.8.2.3 yamt radeonfb_blank(dp, 1); 3444 1.8.2.3 yamt else if (radeonfb_get_backlight(dp) == 0) 3445 1.8.2.3 yamt radeonfb_blank(dp, 0); 3446 1.8.2.3 yamt 3447 1.8.2.3 yamt lvds = radeonfb_get32(sc, RADEON_LVDS_GEN_CNTL); 3448 1.8.2.3 yamt lvds &= ~RADEON_LVDS_DISPLAY_DIS; 3449 1.8.2.3 yamt if (!(lvds & RADEON_LVDS_BLON) || !(lvds & RADEON_LVDS_ON)) { 3450 1.8.2.3 yamt lvds |= dp->rd_bl_lvds_val & RADEON_LVDS_DIGON; 3451 1.8.2.3 yamt lvds |= RADEON_LVDS_BLON | RADEON_LVDS_EN; 3452 1.8.2.3 yamt radeonfb_put32(sc, RADEON_LVDS_GEN_CNTL, lvds); 3453 1.8.2.3 yamt lvds &= ~RADEON_LVDS_BL_MOD_LEV_MASK; 3454 1.8.2.3 yamt lvds |= rlevel << RADEON_LVDS_BL_MOD_LEV_SHIFT; 3455 1.8.2.3 yamt lvds |= RADEON_LVDS_ON; 3456 1.8.2.3 yamt lvds |= dp->rd_bl_lvds_val & RADEON_LVDS_BL_MOD_EN; 3457 1.8.2.3 yamt } else { 3458 1.8.2.3 yamt lvds &= ~RADEON_LVDS_BL_MOD_LEV_MASK; 3459 1.8.2.3 yamt lvds |= rlevel << RADEON_LVDS_BL_MOD_LEV_SHIFT; 3460 1.8.2.3 yamt radeonfb_put32(sc, RADEON_LVDS_GEN_CNTL, lvds); 3461 1.8.2.3 yamt } 3462 1.8.2.3 yamt 3463 1.8.2.3 yamt dp->rd_bl_lvds_val &= ~RADEON_LVDS_STATE_MASK; 3464 1.8.2.3 yamt dp->rd_bl_lvds_val |= lvds & RADEON_LVDS_STATE_MASK; 3465 1.8.2.3 yamt /* XXX What is the correct delay? */ 3466 1.8.2.3 yamt callout_schedule(&dp->rd_bl_lvds_co, 200 * hz); 3467 1.8.2.3 yamt 3468 1.8.2.3 yamt splx(s); 3469 1.8.2.3 yamt 3470 1.8.2.3 yamt return 0; 3471 1.8.2.3 yamt } 3472 1.8.2.3 yamt 3473 1.8.2.3 yamt /* 3474 1.8.2.3 yamt * Callout function for delayed operations on the LVDS_GEN_CNTL register. 3475 1.8.2.3 yamt * Set the delayed bits in the register, and clear the stored delayed 3476 1.8.2.3 yamt * value. 3477 1.8.2.3 yamt */ 3478 1.8.2.3 yamt 3479 1.8.2.3 yamt static void radeonfb_lvds_callout(void *arg) 3480 1.8.2.3 yamt { 3481 1.8.2.3 yamt struct radeonfb_display *dp = arg; 3482 1.8.2.3 yamt int s; 3483 1.8.2.3 yamt 3484 1.8.2.3 yamt s = splhigh(); 3485 1.8.2.3 yamt 3486 1.8.2.3 yamt radeonfb_mask32(dp->rd_softc, RADEON_LVDS_GEN_CNTL, ~0, 3487 1.8.2.3 yamt dp->rd_bl_lvds_val); 3488 1.8.2.3 yamt dp->rd_bl_lvds_val = 0; 3489 1.8.2.3 yamt 3490 1.8.2.3 yamt splx(s); 3491 1.8.2.3 yamt } 3492
Indexes created Sun Oct 19 16:10:00 GMT 2025