radeonfb.c revision 1.101
1 /* $NetBSD: radeonfb.c,v 1.101 2019/03/20 23:05:18 macallan Exp $ */ 2 3 /*- 4 * Copyright (c) 2006 Itronix Inc. 5 * All rights reserved. 6 * 7 * Written by Garrett D'Amore for Itronix Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. The name of Itronix Inc. may not be used to endorse 18 * or promote products derived from this software without specific 19 * prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY ITRONIX INC. ``AS IS'' AND ANY EXPRESS 22 * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 23 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL ITRONIX INC. BE LIABLE FOR ANY 25 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE 27 * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 29 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 30 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 31 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * ATI Technologies Inc. ("ATI") has not assisted in the creation of, and 36 * does not endorse, this software. ATI will not be responsible or liable 37 * for any actual or alleged damage or loss caused by or in connection with 38 * the use of or reliance on this software. 39 */ 40 41 /* 42 * Portions of this code were taken from XFree86's Radeon driver, which bears 43 * this notice: 44 * 45 * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and 46 * VA Linux Systems Inc., Fremont, California. 47 * 48 * All Rights Reserved. 49 * 50 * Permission is hereby granted, free of charge, to any person obtaining 51 * a copy of this software and associated documentation files (the 52 * "Software"), to deal in the Software without restriction, including 53 * without limitation on the rights to use, copy, modify, merge, 54 * publish, distribute, sublicense, and/or sell copies of the Software, 55 * and to permit persons to whom the Software is furnished to do so, 56 * subject to the following conditions: 57 * 58 * The above copyright notice and this permission notice (including the 59 * next paragraph) shall be included in all copies or substantial 60 * portions of the Software. 61 * 62 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 63 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 64 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 65 * NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR 66 * THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 67 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 68 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 69 * DEALINGS IN THE SOFTWARE. 70 */ 71 72 #include <sys/cdefs.h> 73 __KERNEL_RCSID(0, "$NetBSD: radeonfb.c,v 1.101 2019/03/20 23:05:18 macallan Exp $"); 74 75 #include <sys/param.h> 76 #include <sys/systm.h> 77 #include <sys/device.h> 78 #include <sys/malloc.h> 79 #include <sys/bus.h> 80 #include <sys/kernel.h> 81 #include <sys/lwp.h> 82 #include <sys/kauth.h> 83 84 #include <dev/wscons/wsdisplayvar.h> 85 #include <dev/wscons/wsconsio.h> 86 #include <dev/wsfont/wsfont.h> 87 #include <dev/rasops/rasops.h> 88 #include <dev/videomode/videomode.h> 89 #include <dev/videomode/edidvar.h> 90 #include <dev/wscons/wsdisplay_vconsvar.h> 91 #include <dev/pci/wsdisplay_pci.h> 92 #include <dev/wscons/wsdisplay_glyphcachevar.h> 93 94 #include <dev/pci/pcidevs.h> 95 #include <dev/pci/pcireg.h> 96 #include <dev/pci/pcivar.h> 97 #include <dev/pci/pciio.h> 98 #include <dev/pci/radeonfbreg.h> 99 #include <dev/pci/radeonfbvar.h> 100 #include "opt_radeonfb.h" 101 #include "opt_vcons.h" 102 103 #ifdef RADEONFB_DEPTH_32 104 #define RADEONFB_DEFAULT_DEPTH 32 105 #else 106 #define RADEONFB_DEFAULT_DEPTH 8 107 #endif 108 109 static int radeonfb_match(device_t, cfdata_t, void *); 110 static void radeonfb_attach(device_t, device_t, void *); 111 static int radeonfb_ioctl(void *, void *, unsigned long, void *, int, 112 struct lwp *); 113 static paddr_t radeonfb_mmap(void *, void *, off_t, int); 114 static int radeonfb_scratch_test(struct radeonfb_softc *, int, uint32_t); 115 static void radeonfb_loadbios(struct radeonfb_softc *, 116 const struct pci_attach_args *); 117 118 static uintmax_t radeonfb_getprop_num(struct radeonfb_softc *, const char *, 119 uintmax_t); 120 static int radeonfb_getclocks(struct radeonfb_softc *); 121 static int radeonfb_gettmds(struct radeonfb_softc *); 122 static int radeonfb_calc_dividers(struct radeonfb_softc *, uint32_t, 123 uint32_t *, uint32_t *, int); 124 /* flags for radeonfb_calc_dividers */ 125 #define NO_ODD_FBDIV 1 126 127 static int radeonfb_getconnectors(struct radeonfb_softc *); 128 static const struct videomode *radeonfb_modelookup(const char *); 129 static void radeonfb_init_screen(void *, struct vcons_screen *, int, long *); 130 static void radeonfb_pllwriteupdate(struct radeonfb_softc *, int); 131 static void radeonfb_pllwaitatomicread(struct radeonfb_softc *, int); 132 static void radeonfb_program_vclk(struct radeonfb_softc *, int, int, int); 133 static void radeonfb_modeswitch(struct radeonfb_display *); 134 static void radeonfb_setcrtc(struct radeonfb_display *, int); 135 static void radeonfb_init_misc(struct radeonfb_softc *); 136 static void radeonfb_set_fbloc(struct radeonfb_softc *); 137 static void radeonfb_init_palette(struct radeonfb_display *); 138 static void radeonfb_r300cg_workaround(struct radeonfb_softc *); 139 140 static int radeonfb_isblank(struct radeonfb_display *); 141 static void radeonfb_blank(struct radeonfb_display *, int); 142 static int radeonfb_set_cursor(struct radeonfb_display *, 143 struct wsdisplay_cursor *); 144 static int radeonfb_set_curpos(struct radeonfb_display *, 145 struct wsdisplay_curpos *); 146 static void radeonfb_putpal(struct radeonfb_display *, int, int, int, int); 147 static int radeonfb_putcmap(struct radeonfb_display *, struct wsdisplay_cmap *); 148 static int radeonfb_getcmap(struct radeonfb_display *, struct wsdisplay_cmap *); 149 150 /* acceleration support */ 151 static void radeonfb_rectfill(struct radeonfb_display *, int dstx, int dsty, 152 int width, int height, uint32_t color); 153 static void radeonfb_rectfill_a(void *, int, int, int, int, long); 154 static void radeonfb_bitblt(void *, int srcx, int srcy, 155 int dstx, int dsty, int width, int height, int rop); 156 157 /* hw cursor support */ 158 static void radeonfb_cursor_cmap(struct radeonfb_display *); 159 static void radeonfb_cursor_shape(struct radeonfb_display *); 160 static void radeonfb_cursor_position(struct radeonfb_display *); 161 static void radeonfb_cursor_visible(struct radeonfb_display *); 162 static void radeonfb_cursor_update(struct radeonfb_display *, unsigned); 163 164 static inline void radeonfb_wait_fifo(struct radeonfb_softc *, int); 165 static void radeonfb_engine_idle(struct radeonfb_softc *); 166 static void radeonfb_engine_flush(struct radeonfb_softc *); 167 static void radeonfb_engine_reset(struct radeonfb_softc *); 168 static void radeonfb_engine_init(struct radeonfb_display *); 169 static inline void radeonfb_unclip(struct radeonfb_softc *) __unused; 170 171 static void radeonfb_eraserows(void *, int, int, long); 172 static void radeonfb_erasecols(void *, int, int, int, long); 173 static void radeonfb_copyrows(void *, int, int, int); 174 static void radeonfb_copycols(void *, int, int, int, int); 175 static void radeonfb_cursor(void *, int, int, int); 176 static void radeonfb_putchar(void *, int, int, unsigned, long); 177 static void radeonfb_putchar_aa32(void *, int, int, unsigned, long); 178 static void radeonfb_putchar_aa8(void *, int, int, unsigned, long); 179 #ifndef RADEONFB_ALWAYS_ACCEL_PUTCHAR 180 static void radeonfb_putchar_wrapper(void *, int, int, unsigned, long); 181 #endif 182 183 static int radeonfb_set_backlight(struct radeonfb_display *, int); 184 static int radeonfb_get_backlight(struct radeonfb_display *); 185 static void radeonfb_switch_backlight(struct radeonfb_display *, int); 186 static void radeonfb_lvds_callout(void *); 187 188 static void radeonfb_brightness_up(device_t); 189 static void radeonfb_brightness_down(device_t); 190 191 static struct videomode *radeonfb_best_refresh(struct videomode *, 192 struct videomode *); 193 static void radeonfb_pickres(struct radeonfb_display *, uint16_t *, 194 uint16_t *, int); 195 static const struct videomode *radeonfb_port_mode(struct radeonfb_softc *, 196 struct radeonfb_port *, int, int); 197 198 static int radeonfb_drm_print(void *, const char *); 199 200 #ifdef RADEONFB_DEBUG 201 int radeon_debug = 1; 202 #define DPRINTF(x) \ 203 if (radeon_debug) printf x 204 #define PRINTREG(r) DPRINTF((#r " = %08x\n", GET32(sc, r))) 205 #define PRINTPLL(r) DPRINTF((#r " = %08x\n", GETPLL(sc, r))) 206 #else 207 #define DPRINTF(x) 208 #define PRINTREG(r) 209 #define PRINTPLL(r) 210 #endif 211 212 #define ROUNDUP(x,y) (((x) + ((y) - 1)) & ~((y) - 1)) 213 214 #ifndef RADEON_DEFAULT_MODE 215 /* any reasonably modern display should handle this */ 216 #define RADEON_DEFAULT_MODE "1024x768x60" 217 #endif 218 219 extern const u_char rasops_cmap[768]; 220 221 const char *radeonfb_default_mode = RADEON_DEFAULT_MODE; 222 223 static struct { 224 int size; /* minimum memory size (MB) */ 225 int maxx; /* maximum x dimension */ 226 int maxy; /* maximum y dimension */ 227 int maxbpp; /* maximum bpp */ 228 int maxdisp; /* maximum logical display count */ 229 } radeonfb_limits[] = { 230 { 32, 2048, 1536, 32, 2 }, 231 { 16, 1600, 1200, 32, 2 }, 232 { 8, 1600, 1200, 32, 1 }, 233 { 0, 0, 0, 0, 0 }, 234 }; 235 236 static struct wsscreen_descr radeonfb_stdscreen = { 237 "fb", /* name */ 238 0, 0, /* ncols, nrows */ 239 NULL, /* textops */ 240 8, 16, /* fontwidth, fontheight */ 241 WSSCREEN_WSCOLORS | WSSCREEN_UNDERLINE | WSSCREEN_RESIZE, /* capabilities */ 242 0, /* modecookie */ 243 }; 244 245 struct wsdisplay_accessops radeonfb_accessops = { 246 radeonfb_ioctl, 247 radeonfb_mmap, 248 NULL, /* vcons_alloc_screen */ 249 NULL, /* vcons_free_screen */ 250 NULL, /* vcons_show_screen */ 251 NULL, /* load_font */ 252 NULL, /* pollc */ 253 NULL, /* scroll */ 254 }; 255 256 static struct { 257 uint16_t devid; 258 uint16_t family; 259 uint16_t flags; 260 } radeonfb_devices[] = 261 { 262 /* R100 family */ 263 { PCI_PRODUCT_ATI_RADEON_R100_QD, RADEON_R100, 0 }, 264 { PCI_PRODUCT_ATI_RADEON_R100_QE, RADEON_R100, 0 }, 265 { PCI_PRODUCT_ATI_RADEON_R100_QF, RADEON_R100, 0 }, 266 { PCI_PRODUCT_ATI_RADEON_R100_QG, RADEON_R100, 0 }, 267 268 /* RV100 family */ 269 { PCI_PRODUCT_ATI_RADEON_RV100_LY, RADEON_RV100, RFB_MOB }, 270 { PCI_PRODUCT_ATI_RADEON_RV100_LZ, RADEON_RV100, RFB_MOB }, 271 { PCI_PRODUCT_ATI_RADEON_RV100_QY, RADEON_RV100, 0 }, 272 { PCI_PRODUCT_ATI_RADEON_RV100_QZ, RADEON_RV100, 0 }, 273 274 /* RS100 family */ 275 { PCI_PRODUCT_ATI_RADEON_RS100_4136, RADEON_RS100, 0 }, 276 { PCI_PRODUCT_ATI_RADEON_RS100_4336, RADEON_RS100, RFB_MOB }, 277 278 /* RS200/RS250 family */ 279 { PCI_PRODUCT_ATI_RADEON_RS200_4337, RADEON_RS200, RFB_MOB }, 280 { PCI_PRODUCT_ATI_RADEON_RS200_A7, RADEON_RS200, 0 }, 281 { PCI_PRODUCT_ATI_RADEON_RS250_B7, RADEON_RS200, RFB_MOB }, 282 { PCI_PRODUCT_ATI_RADEON_RS250_D7, RADEON_RS200, 0 }, 283 284 /* R200 family */ 285 /* add more R200 products? , 5148 */ 286 { PCI_PRODUCT_ATI_RADEON_R200_BB, RADEON_R200, 0 }, 287 { PCI_PRODUCT_ATI_RADEON_R200_BC, RADEON_R200, 0 }, 288 { PCI_PRODUCT_ATI_RADEON_R200_QH, RADEON_R200, 0 }, 289 { PCI_PRODUCT_ATI_RADEON_R200_QL, RADEON_R200, 0 }, 290 { PCI_PRODUCT_ATI_RADEON_R200_QM, RADEON_R200, 0 }, 291 292 /* RV200 family */ 293 { PCI_PRODUCT_ATI_RADEON_RV200_LW, RADEON_RV200, RFB_MOB }, 294 { PCI_PRODUCT_ATI_RADEON_RV200_LX, RADEON_RV200, RFB_MOB }, 295 { PCI_PRODUCT_ATI_RADEON_RV200_QW, RADEON_RV200, 0 }, 296 { PCI_PRODUCT_ATI_RADEON_RV200_QX, RADEON_RV200, 0 }, 297 298 /* RV250 family */ 299 { PCI_PRODUCT_ATI_RADEON_RV250_4966, RADEON_RV250, 0 }, 300 { PCI_PRODUCT_ATI_RADEON_RV250_4967, RADEON_RV250, 0 }, 301 { PCI_PRODUCT_ATI_RADEON_RV250_4C64, RADEON_RV250, RFB_MOB }, 302 { PCI_PRODUCT_ATI_RADEON_RV250_4C66, RADEON_RV250, RFB_MOB }, 303 { PCI_PRODUCT_ATI_RADEON_RV250_4C67, RADEON_RV250, RFB_MOB }, 304 305 /* RS300 family */ 306 { PCI_PRODUCT_ATI_RADEON_RS300_X5, RADEON_RS300, 0 }, 307 { PCI_PRODUCT_ATI_RADEON_RS300_X4, RADEON_RS300, 0 }, 308 { PCI_PRODUCT_ATI_RADEON_RS300_7834, RADEON_RS300, 0 }, 309 { PCI_PRODUCT_ATI_RADEON_RS300_7835, RADEON_RS300, RFB_MOB }, 310 311 /* RV280 family */ 312 { PCI_PRODUCT_ATI_RADEON_RV280_5960, RADEON_RV280, 0 }, 313 { PCI_PRODUCT_ATI_RADEON_RV280_5961, RADEON_RV280, 0 }, 314 { PCI_PRODUCT_ATI_RADEON_RV280_5962, RADEON_RV280, 0 }, 315 { PCI_PRODUCT_ATI_RADEON_RV280_5963, RADEON_RV280, 0 }, 316 { PCI_PRODUCT_ATI_RADEON_RV280_5964, RADEON_RV280, 0 }, 317 { PCI_PRODUCT_ATI_RADEON_RV280_5C61, RADEON_RV280, RFB_MOB }, 318 { PCI_PRODUCT_ATI_RADEON_RV280_5C63, RADEON_RV280, RFB_MOB }, 319 320 /* R300 family */ 321 { PCI_PRODUCT_ATI_RADEON_R300_AD, RADEON_R300, 0 }, 322 { PCI_PRODUCT_ATI_RADEON_R300_AE, RADEON_R300, 0 }, 323 { PCI_PRODUCT_ATI_RADEON_R300_AF, RADEON_R300, 0 }, 324 { PCI_PRODUCT_ATI_RADEON_R300_AG, RADEON_R300, 0 }, 325 { PCI_PRODUCT_ATI_RADEON_R300_ND, RADEON_R300, 0 }, 326 { PCI_PRODUCT_ATI_RADEON_R300_NE, RADEON_R300, 0 }, 327 { PCI_PRODUCT_ATI_RADEON_R300_NF, RADEON_R300, 0 }, 328 { PCI_PRODUCT_ATI_RADEON_R300_NG, RADEON_R300, 0 }, 329 330 /* RV350/RV360 family */ 331 { PCI_PRODUCT_ATI_RADEON_RV350_AP, RADEON_RV350, 0 }, 332 { PCI_PRODUCT_ATI_RADEON_RV350_AQ, RADEON_RV350, 0 }, 333 { PCI_PRODUCT_ATI_RADEON_RV360_AR, RADEON_RV350, 0 }, 334 { PCI_PRODUCT_ATI_RADEON_RV350_AS, RADEON_RV350, 0 }, 335 { PCI_PRODUCT_ATI_RADEON_RV350_AT, RADEON_RV350, 0 }, 336 { PCI_PRODUCT_ATI_RADEON_RV350_AV, RADEON_RV350, 0 }, 337 { PCI_PRODUCT_ATI_RADEON_RV350_NP, RADEON_RV350, RFB_MOB }, 338 { PCI_PRODUCT_ATI_RADEON_RV350_NQ, RADEON_RV350, RFB_MOB }, 339 { PCI_PRODUCT_ATI_RADEON_RV350_NR, RADEON_RV350, RFB_MOB }, 340 { PCI_PRODUCT_ATI_RADEON_RV350_NS, RADEON_RV350, RFB_MOB }, 341 { PCI_PRODUCT_ATI_RADEON_RV350_NT, RADEON_RV350, RFB_MOB }, 342 { PCI_PRODUCT_ATI_RADEON_RV350_NV, RADEON_RV350, RFB_MOB }, 343 344 /* R350/R360 family */ 345 { PCI_PRODUCT_ATI_RADEON_R350_AH, RADEON_R350, 0 }, 346 { PCI_PRODUCT_ATI_RADEON_R350_AI, RADEON_R350, 0 }, 347 { PCI_PRODUCT_ATI_RADEON_R350_AJ, RADEON_R350, 0 }, 348 { PCI_PRODUCT_ATI_RADEON_R350_AK, RADEON_R350, 0 }, 349 { PCI_PRODUCT_ATI_RADEON_R350_NH, RADEON_R350, 0 }, 350 { PCI_PRODUCT_ATI_RADEON_R350_NI, RADEON_R350, 0 }, 351 { PCI_PRODUCT_ATI_RADEON_R350_NK, RADEON_R350, 0 }, 352 { PCI_PRODUCT_ATI_RADEON_R360_NJ, RADEON_R350, 0 }, 353 354 /* RV380/RV370 family */ 355 { PCI_PRODUCT_ATI_RADEON_RV380_3150, RADEON_RV380, RFB_MOB }, 356 { PCI_PRODUCT_ATI_RADEON_RV380_3154, RADEON_RV380, RFB_MOB }, 357 { PCI_PRODUCT_ATI_RADEON_RV380_3E50, RADEON_RV380, 0 }, 358 { PCI_PRODUCT_ATI_RADEON_RV380_3E54, RADEON_RV380, 0 }, 359 { PCI_PRODUCT_ATI_RADEON_RV370_5460, RADEON_RV380, RFB_MOB }, 360 { PCI_PRODUCT_ATI_RADEON_RV370_5464, RADEON_RV380, RFB_MOB }, 361 { PCI_PRODUCT_ATI_RADEON_RV370_5B60, RADEON_RV380, 0 }, 362 { PCI_PRODUCT_ATI_RADEON_RV370_5B63, RADEON_RV380, 0 }, 363 { PCI_PRODUCT_ATI_RADEON_RV370_5B64, RADEON_RV380, 0 }, 364 { PCI_PRODUCT_ATI_RADEON_RV370_5B65, RADEON_RV380, 0 }, 365 366 #if notyet 367 /* R420/R423 family */ 368 { PCI_PRODUCT_ATI_RADEON_R420_JH, RADEON_R420, 0 }, 369 { PCI_PRODUCT_ATI_RADEON_R420_JI, RADEON_R420, 0 }, 370 { PCI_PRODUCT_ATI_RADEON_R420_JJ, RADEON_R420, 0 }, 371 { PCI_PRODUCT_ATI_RADEON_R420_JK, RADEON_R420, 0 }, 372 { PCI_PRODUCT_ATI_RADEON_R420_JL, RADEON_R420, 0 }, 373 { PCI_PRODUCT_ATI_RADEON_R420_JM, RADEON_R420, 0 }, 374 { PCI_PRODUCT_ATI_RADEON_R420_JN, RADEON_R420, RFB_MOB }, 375 { PCI_PRODUCT_ATI_RADEON_R420_JP, RADEON_R420, 0 }, 376 { PCI_PRODUCT_ATI_RADEON_R423_UH, RADEON_R420, 0 }, 377 { PCI_PRODUCT_ATI_RADEON_R423_UI, RADEON_R420, 0 }, 378 { PCI_PRODUCT_ATI_RADEON_R423_UJ, RADEON_R420, 0 }, 379 { PCI_PRODUCT_ATI_RADEON_R423_UK, RADEON_R420, 0 }, 380 { PCI_PRODUCT_ATI_RADEON_R423_UQ, RADEON_R420, 0 }, 381 { PCI_PRODUCT_ATI_RADEON_R423_UR, RADEON_R420, 0 }, 382 { PCI_PRODUCT_ATI_RADEON_R423_UT, RADEON_R420, 0 }, 383 { PCI_PRODUCT_ATI_RADEON_R423_5D57, RADEON_R420, 0 }, 384 { PCI_PRODUCT_ATI_RADEON_R430_554F, RADEON_R420, 0 }, 385 386 /* R5xx family */ 387 { 0x7240, RADEON_R420, 0 }, 388 #endif 389 { 0, 0, 0 } 390 }; 391 392 static struct { 393 int divider; 394 int mask; 395 } radeonfb_dividers[] = { 396 { 16, 5 }, 397 { 12, 7 }, 398 { 8, 3 }, 399 { 6, 6 }, 400 { 4, 2 }, 401 { 3, 4 }, 402 { 2, 1 }, 403 { 1, 0 }, 404 { 0, 0 } 405 }; 406 407 /* 408 * This table taken from X11. 409 */ 410 static const struct { 411 int family; 412 struct radeon_tmds_pll plls[4]; 413 } radeonfb_tmds_pll[] = { 414 { RADEON_R100, {{12000, 0xa1b}, {-1, 0xa3f}}}, 415 { RADEON_RV100, {{12000, 0xa1b}, {-1, 0xa3f}}}, 416 { RADEON_RS100, {{0, 0}}}, 417 { RADEON_RV200, {{15000, 0xa1b}, {-1, 0xa3f}}}, 418 { RADEON_RS200, {{15000, 0xa1b}, {-1, 0xa3f}}}, 419 { RADEON_R200, {{15000, 0xa1b}, {-1, 0xa3f}}}, 420 { RADEON_RV250, {{15500, 0x81b}, {-1, 0x83f}}}, 421 { RADEON_RS300, {{0, 0}}}, 422 { RADEON_RV280, {{13000, 0x400f4}, {15000, 0x400f7}, {-1, 0x40111}}}, 423 { RADEON_R300, {{-1, 0xb01cb}}}, 424 { RADEON_R350, {{-1, 0xb01cb}}}, 425 { RADEON_RV350, {{15000, 0xb0155}, {-1, 0xb01cb}}}, 426 { RADEON_RV380, {{15000, 0xb0155}, {-1, 0xb01cb}}}, 427 { RADEON_R420, {{-1, 0xb01cb}}}, 428 }; 429 430 #define RADEONFB_BACKLIGHT_MAX 255 /* Maximum backlight level. */ 431 432 433 CFATTACH_DECL_NEW(radeonfb, sizeof (struct radeonfb_softc), 434 radeonfb_match, radeonfb_attach, NULL, NULL); 435 436 static int 437 radeonfb_match(device_t parent, cfdata_t match, void *aux) 438 { 439 const struct pci_attach_args *pa = aux; 440 int i; 441 442 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_ATI) 443 return 0; 444 445 for (i = 0; radeonfb_devices[i].devid; i++) { 446 if (PCI_PRODUCT(pa->pa_id) == radeonfb_devices[i].devid) 447 return 100; /* high to defeat VGA/VESA */ 448 } 449 450 return 0; 451 } 452 453 static void 454 radeonfb_attach(device_t parent, device_t dev, void *aux) 455 { 456 struct radeonfb_softc *sc = device_private(dev); 457 const struct pci_attach_args *pa = aux; 458 const char *mptr; 459 bus_size_t bsz; 460 pcireg_t screg; 461 int i, j, fg, bg, ul, flags; 462 uint32_t v; 463 464 sc->sc_dev = dev; 465 sc->sc_id = pa->pa_id; 466 for (i = 0; radeonfb_devices[i].devid; i++) { 467 if (PCI_PRODUCT(sc->sc_id) == radeonfb_devices[i].devid) 468 break; 469 } 470 471 pci_aprint_devinfo(pa, NULL); 472 473 DPRINTF(("%s", prop_dictionary_externalize(device_properties(dev)))); 474 475 KASSERT(radeonfb_devices[i].devid != 0); 476 sc->sc_pt = pa->pa_tag; 477 sc->sc_iot = pa->pa_iot; 478 sc->sc_pc = pa->pa_pc; 479 sc->sc_family = radeonfb_devices[i].family; 480 sc->sc_flags = radeonfb_devices[i].flags; 481 482 /* enable memory and IO access */ 483 screg = pci_conf_read(sc->sc_pc, sc->sc_pt, PCI_COMMAND_STATUS_REG); 484 screg |= PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE; 485 pci_conf_write(sc->sc_pc, sc->sc_pt, PCI_COMMAND_STATUS_REG, screg); 486 487 /* 488 * Some flags are general to entire chip families, and rather 489 * than clutter up the table with them, we go ahead and set 490 * them here. 491 */ 492 switch (sc->sc_family) { 493 case RADEON_RS100: 494 case RADEON_RS200: 495 sc->sc_flags |= RFB_IGP | RFB_RV100; 496 break; 497 498 case RADEON_RV100: 499 case RADEON_RV200: 500 case RADEON_RV250: 501 case RADEON_RV280: 502 sc->sc_flags |= RFB_RV100; 503 break; 504 505 case RADEON_RS300: 506 sc->sc_flags |= RFB_SDAC | RFB_IGP | RFB_RV100; 507 break; 508 509 case RADEON_R300: 510 case RADEON_RV350: 511 case RADEON_R350: 512 case RADEON_RV380: 513 case RADEON_R420: 514 /* newer chips */ 515 sc->sc_flags |= RFB_R300; 516 break; 517 518 case RADEON_R100: 519 sc->sc_flags |= RFB_NCRTC2; 520 break; 521 } 522 523 if ((sc->sc_family == RADEON_RV200) || 524 (sc->sc_family == RADEON_RV250) || 525 (sc->sc_family == RADEON_RV280) || 526 (sc->sc_family == RADEON_RV350)) { 527 bool inverted = 0; 528 /* backlight level is linear */ 529 DPRINTF(("found RV* chip, backlight is supposedly linear\n")); 530 prop_dictionary_get_bool(device_properties(sc->sc_dev), 531 "backlight_level_reverted", &inverted); 532 if (inverted) { 533 DPRINTF(("nope, it's inverted\n")); 534 sc->sc_flags |= RFB_INV_BLIGHT; 535 } 536 } else 537 sc->sc_flags |= RFB_INV_BLIGHT; 538 539 /* 540 * XXX: to support true multihead, this must change. 541 */ 542 sc->sc_ndisplays = 1; 543 544 /* XXX: */ 545 if (!HAS_CRTC2(sc)) { 546 sc->sc_ndisplays = 1; 547 } 548 549 if (pci_mapreg_map(pa, RADEON_MAPREG_MMIO, PCI_MAPREG_TYPE_MEM, 0, 550 &sc->sc_regt, &sc->sc_regh, &sc->sc_regaddr, 551 &sc->sc_regsz) != 0) { 552 aprint_error("%s: unable to map registers!\n", XNAME(sc)); 553 goto error; 554 } 555 556 if (pci_mapreg_info(sc->sc_pc, sc->sc_pt, PCI_MAPREG_ROM, 557 PCI_MAPREG_TYPE_ROM, &sc->sc_romaddr, &sc->sc_romsz, &flags) != 0) 558 { 559 aprint_error("%s: unable to find ROM!\n", XNAME(sc)); 560 goto error; 561 } 562 sc->sc_romt = sc->sc_memt; 563 564 sc->sc_mapped = TRUE; 565 566 /* scratch register test... */ 567 if (radeonfb_scratch_test(sc, RADEON_BIOS_0_SCRATCH, 0x55555555) || 568 radeonfb_scratch_test(sc, RADEON_BIOS_0_SCRATCH, 0xaaaaaaaa)) { 569 aprint_error("%s: scratch register test failed!\n", XNAME(sc)); 570 goto error; 571 } 572 573 PRINTREG(RADEON_CRTC_EXT_CNTL); 574 PRINTREG(RADEON_CRTC_GEN_CNTL); 575 PRINTREG(RADEON_CRTC2_GEN_CNTL); 576 PRINTREG(RADEON_DISP_OUTPUT_CNTL); 577 PRINTREG(RADEON_DAC_CNTL2); 578 PRINTREG(RADEON_BIOS_4_SCRATCH); 579 PRINTREG(RADEON_FP_GEN_CNTL); 580 sc->sc_fp_gen_cntl = GET32(sc, RADEON_FP_GEN_CNTL); 581 PRINTREG(RADEON_FP2_GEN_CNTL); 582 PRINTREG(RADEON_TMDS_CNTL); 583 PRINTREG(RADEON_TMDS_TRANSMITTER_CNTL); 584 PRINTREG(RADEON_TMDS_PLL_CNTL); 585 PRINTREG(RADEON_LVDS_GEN_CNTL); 586 PRINTREG(RADEON_DISP_HW_DEBUG); 587 PRINTREG(RADEON_PIXCLKS_CNTL); 588 PRINTREG(RADEON_CRTC_H_SYNC_STRT_WID); 589 PRINTREG(RADEON_FP_H_SYNC_STRT_WID); 590 PRINTREG(RADEON_CRTC2_H_SYNC_STRT_WID); 591 PRINTREG(RADEON_FP_H2_SYNC_STRT_WID); 592 593 /* 594 * XXX 595 * This was if (IS_RV100()), which is set for all pre-R3xx chips. 596 * I suspect this only makes sense on Sun XVR-100 with firmware that doesn't 597 * support DVI, so for now let's restrict it to only actual RV100 598 */ 599 if (sc->sc_family == RADEON_RV100) 600 PUT32(sc, RADEON_TMDS_PLL_CNTL, 0xa27); 601 602 /* XXX 603 * according to xf86-video-radeon R3xx has this bit backwards 604 */ 605 if (IS_R300(sc)) { 606 PATCH32(sc, RADEON_TMDS_TRANSMITTER_CNTL, 607 0, 608 ~(RADEON_TMDS_TRANSMITTER_PLLEN | RADEON_TMDS_TRANSMITTER_PLLRST)); 609 } else { 610 PATCH32(sc, RADEON_TMDS_TRANSMITTER_CNTL, 611 RADEON_TMDS_TRANSMITTER_PLLEN, 612 ~(RADEON_TMDS_TRANSMITTER_PLLEN | RADEON_TMDS_TRANSMITTER_PLLRST)); 613 } 614 615 radeonfb_i2c_init(sc); 616 617 radeonfb_loadbios(sc, pa); 618 619 #ifdef RADEONFB_BIOS_INIT 620 if (radeonfb_bios_init(sc)) { 621 aprint_error("%s: BIOS inititialization failed\n", XNAME(sc)); 622 } 623 #endif 624 625 if (radeonfb_getclocks(sc)) { 626 aprint_error("%s: Unable to get reference clocks from BIOS\n", 627 XNAME(sc)); 628 goto error; 629 } 630 631 if (radeonfb_gettmds(sc)) { 632 aprint_error("%s: Unable to identify TMDS PLL settings\n", 633 XNAME(sc)); 634 goto error; 635 } 636 637 aprint_verbose("%s: refclk = %d.%03d MHz, refdiv = %d " 638 "minpll = %d, maxpll = %d\n", XNAME(sc), 639 (int)sc->sc_refclk / 1000, (int)sc->sc_refclk % 1000, 640 (int)sc->sc_refdiv, (int)sc->sc_minpll, (int)sc->sc_maxpll); 641 642 radeonfb_getconnectors(sc); 643 644 radeonfb_set_fbloc(sc); 645 646 /* 64 MB should be enough -- more just wastes map entries */ 647 if (sc->sc_memsz > (64 << 20)) 648 sc->sc_memsz = (64 << 20); 649 650 for (i = 0; radeonfb_limits[i].size; i++) { 651 if (sc->sc_memsz >= radeonfb_limits[i].size) { 652 sc->sc_maxx = radeonfb_limits[i].maxx; 653 sc->sc_maxy = radeonfb_limits[i].maxy; 654 sc->sc_maxbpp = radeonfb_limits[i].maxbpp; 655 /* framebuffer offset, start at a 4K page */ 656 sc->sc_fboffset = sc->sc_memsz / 657 radeonfb_limits[i].maxdisp; 658 /* 659 * we use the fbsize to figure out where we can store 660 * things like cursor data. 661 */ 662 sc->sc_fbsize = 663 ROUNDUP(ROUNDUP(sc->sc_maxx * sc->sc_maxbpp / 8 , 664 RADEON_STRIDEALIGN) * sc->sc_maxy, 665 4096); 666 break; 667 } 668 } 669 670 671 radeonfb_init_misc(sc); 672 673 /* program the DAC wirings */ 674 for (i = 0; i < (HAS_CRTC2(sc) ? 2 : 1); i++) { 675 switch (sc->sc_ports[i].rp_dac_type) { 676 case RADEON_DAC_PRIMARY: 677 PATCH32(sc, RADEON_DAC_CNTL2, 678 i ? RADEON_DAC2_DAC_CLK_SEL : 0, 679 ~RADEON_DAC2_DAC_CLK_SEL); 680 break; 681 case RADEON_DAC_TVDAC: 682 /* we always use the TVDAC to drive a secondary analog 683 * CRT for now. if we ever support TV-out this will 684 * have to change. 685 */ 686 SET32(sc, RADEON_DAC_CNTL2, 687 RADEON_DAC2_DAC2_CLK_SEL); 688 PATCH32(sc, RADEON_DISP_HW_DEBUG, 689 i ? 0 : RADEON_CRT2_DISP1_SEL, 690 ~RADEON_CRT2_DISP1_SEL); 691 /* we're using CRTC2 for the 2nd port */ 692 if (sc->sc_ports[i].rp_number == 1) { 693 PATCH32(sc, RADEON_DISP_OUTPUT_CNTL, 694 RADEON_DISP_DAC2_SOURCE_CRTC2, 695 ~RADEON_DISP_DAC2_SOURCE_MASK); 696 } 697 698 break; 699 } 700 DPRINTF(("%s: port %d tmds type %d\n", __func__, i, 701 sc->sc_ports[i].rp_tmds_type)); 702 switch (sc->sc_ports[i].rp_tmds_type) { 703 case RADEON_TMDS_INT: 704 /* point FP0 at the CRTC this port uses */ 705 DPRINTF(("%s: plugging internal TMDS into CRTC %d\n", 706 __func__, sc->sc_ports[i].rp_number)); 707 if (IS_R300(sc)) { 708 PATCH32(sc, RADEON_FP_GEN_CNTL, 709 sc->sc_ports[i].rp_number ? 710 R200_FP_SOURCE_SEL_CRTC2 : 711 R200_FP_SOURCE_SEL_CRTC1, 712 ~R200_FP_SOURCE_SEL_MASK); 713 } else { 714 PATCH32(sc, RADEON_FP_GEN_CNTL, 715 sc->sc_ports[i].rp_number ? 716 RADEON_FP_SEL_CRTC2 : 717 RADEON_FP_SEL_CRTC1, 718 ~RADEON_FP_SEL_MASK); 719 } 720 break; 721 case RADEON_TMDS_EXT: 722 /* point FP2 at the CRTC this port uses */ 723 DPRINTF(("%s: plugging external TMDS into CRTC %d\n", 724 __func__, sc->sc_ports[i].rp_number)); 725 if (IS_R300(sc)) { 726 PATCH32(sc, RADEON_FP2_GEN_CNTL, 727 sc->sc_ports[i].rp_number ? 728 R200_FP2_SOURCE_SEL_CRTC2 : 729 R200_FP2_SOURCE_SEL_CRTC1, 730 ~R200_FP2_SOURCE_SEL_CRTC2); 731 } else { 732 PATCH32(sc, RADEON_FP2_GEN_CNTL, 733 sc->sc_ports[i].rp_number ? 734 RADEON_FP2_SRC_SEL_CRTC2 : 735 RADEON_FP2_SRC_SEL_CRTC1, 736 ~RADEON_FP2_SRC_SEL_CRTC2); 737 } 738 break; 739 } 740 } 741 PRINTREG(RADEON_DAC_CNTL2); 742 PRINTREG(RADEON_DISP_HW_DEBUG); 743 744 PRINTREG(RADEON_DAC_CNTL); 745 /* other DAC programming */ 746 v = GET32(sc, RADEON_DAC_CNTL); 747 v &= (RADEON_DAC_RANGE_CNTL_MASK | RADEON_DAC_BLANKING); 748 v |= RADEON_DAC_MASK_ALL | RADEON_DAC_8BIT_EN; 749 PUT32(sc, RADEON_DAC_CNTL, v); 750 PRINTREG(RADEON_DAC_CNTL); 751 752 /* XXX: this may need more investigation */ 753 PUT32(sc, RADEON_TV_DAC_CNTL, 0x00280203); 754 PRINTREG(RADEON_TV_DAC_CNTL); 755 756 /* enable TMDS */ 757 SET32(sc, RADEON_FP_GEN_CNTL, 758 RADEON_FP_TMDS_EN | 759 RADEON_FP_CRTC_DONT_SHADOW_VPAR | 760 RADEON_FP_CRTC_DONT_SHADOW_HEND); 761 /* 762 * XXX 763 * no idea why this is necessary - if I do not clear this bit on my 764 * iBook G4 the screen remains black, even though it's already clear. 765 * It needs to be set on my Sun XVR-100 for the DVI port to work 766 * TODO: 767 * see if this is still necessary now that CRTCs, DACs and outputs are 768 * getting wired up in a halfway sane way 769 */ 770 if (sc->sc_fp_gen_cntl & RADEON_FP_SEL_CRTC2) { 771 SET32(sc, RADEON_FP_GEN_CNTL, RADEON_FP_SEL_CRTC2); 772 } else { 773 CLR32(sc, RADEON_FP_GEN_CNTL, RADEON_FP_SEL_CRTC2); 774 } 775 776 /* 777 * we use bus_space_map instead of pci_mapreg, because we don't 778 * need the full aperature space. no point in wasting virtual 779 * address space we don't intend to use, right? 780 */ 781 if ((sc->sc_memsz < (4096 * 1024)) || 782 (pci_mapreg_info(sc->sc_pc, sc->sc_pt, RADEON_MAPREG_VRAM, 783 PCI_MAPREG_TYPE_MEM, &sc->sc_memaddr, &bsz, NULL) != 0) || 784 (bsz < sc->sc_memsz)) { 785 sc->sc_memsz = 0; 786 aprint_error("%s: Bad frame buffer configuration\n", 787 XNAME(sc)); 788 goto error; 789 } 790 791 sc->sc_memt = pa->pa_memt; 792 if (bus_space_map(sc->sc_memt, sc->sc_memaddr, sc->sc_memsz, 793 BUS_SPACE_MAP_LINEAR, &sc->sc_memh) != 0) { 794 sc->sc_memsz = 0; 795 aprint_error("%s: Unable to map frame buffer\n", XNAME(sc)); 796 goto error; 797 } 798 799 aprint_normal("%s: %d MB aperture at 0x%08x, " 800 "%d KB registers at 0x%08x\n", XNAME(sc), 801 (int)sc->sc_memsz >> 20, (unsigned)sc->sc_memaddr, 802 (int)sc->sc_regsz >> 10, (unsigned)sc->sc_regaddr); 803 804 /* setup default video mode from devprop (allows PROM override) */ 805 sc->sc_defaultmode = radeonfb_default_mode; 806 if (prop_dictionary_get_cstring_nocopy(device_properties(sc->sc_dev), 807 "videomode", &mptr)) { 808 809 strncpy(sc->sc_modebuf, mptr, sizeof(sc->sc_modebuf)); 810 sc->sc_defaultmode = sc->sc_modebuf; 811 } 812 813 /* initialize some basic display parameters */ 814 for (i = 0; i < sc->sc_ndisplays; i++) { 815 struct radeonfb_display *dp = &sc->sc_displays[i]; 816 struct rasops_info *ri; 817 long defattr; 818 struct wsemuldisplaydev_attach_args aa; 819 820 /* 821 * Figure out how many "displays" (desktops) we are going to 822 * support. If more than one, then each CRTC gets its own 823 * programming. 824 * 825 * XXX: this code needs to change to support mergedfb. 826 * XXX: would be nice to allow this to be overridden 827 */ 828 if (HAS_CRTC2(sc) && (sc->sc_ndisplays == 1)) { 829 DPRINTF(("dual crtcs!\n")); 830 dp->rd_ncrtcs = 2; 831 dp->rd_crtcs[0].rc_port = 832 &sc->sc_ports[0]; 833 dp->rd_crtcs[0].rc_number = sc->sc_ports[0].rp_number; 834 dp->rd_crtcs[1].rc_port = 835 &sc->sc_ports[1]; 836 dp->rd_crtcs[1].rc_number = sc->sc_ports[1].rp_number; 837 } else { 838 dp->rd_ncrtcs = 1; 839 dp->rd_crtcs[0].rc_port = 840 &sc->sc_ports[i]; 841 dp->rd_crtcs[0].rc_number = sc->sc_ports[i].rp_number; 842 } 843 844 dp->rd_softc = sc; 845 dp->rd_wsmode = WSDISPLAYIO_MODE_EMUL; 846 dp->rd_bpp = RADEONFB_DEFAULT_DEPTH; /* XXX */ 847 848 /* for text mode, we pick a resolution that won't 849 * require panning */ 850 radeonfb_pickres(dp, &dp->rd_virtx, &dp->rd_virty, 0); 851 852 aprint_normal("%s: display %d: " 853 "initial virtual resolution %dx%d at %d bpp\n", 854 XNAME(sc), i, dp->rd_virtx, dp->rd_virty, dp->rd_bpp); 855 aprint_normal_dev(sc->sc_dev, "using %d MB per display\n", 856 sc->sc_fboffset >> 20); 857 /* now select the *video mode* that we will use */ 858 for (j = 0; j < dp->rd_ncrtcs; j++) { 859 const struct videomode *vmp; 860 vmp = radeonfb_port_mode(sc, dp->rd_crtcs[j].rc_port, 861 dp->rd_virtx, dp->rd_virty); 862 863 /* 864 * virtual resolution should be at least as high as 865 * physical 866 */ 867 if (dp->rd_virtx < vmp->hdisplay || 868 dp->rd_virty < vmp->vdisplay) { 869 dp->rd_virtx = vmp->hdisplay; 870 dp->rd_virty = vmp->vdisplay; 871 } 872 873 dp->rd_crtcs[j].rc_videomode = *vmp; 874 printf("%s: port %d: physical %dx%d %dHz\n", 875 XNAME(sc), j, vmp->hdisplay, vmp->vdisplay, 876 DIVIDE(DIVIDE(vmp->dot_clock * 1000, 877 vmp->htotal), vmp->vtotal)); 878 } 879 880 /* N.B.: radeon wants 64-byte aligned stride */ 881 dp->rd_stride = dp->rd_virtx * dp->rd_bpp / 8; 882 dp->rd_stride = ROUNDUP(dp->rd_stride, RADEON_STRIDEALIGN); 883 DPRINTF(("stride: %d %d\n", dp->rd_stride, dp->rd_virtx)); 884 885 dp->rd_offset = sc->sc_fboffset * i; 886 dp->rd_fbptr = (vaddr_t)bus_space_vaddr(sc->sc_memt, 887 sc->sc_memh) + dp->rd_offset; 888 dp->rd_curoff = sc->sc_fboffset - 4096; /* 4KB cursor space */ 889 dp->rd_curptr = dp->rd_fbptr + dp->rd_curoff; 890 891 DPRINTF(("fpbtr = %p\n", (void *)dp->rd_fbptr)); 892 893 switch (dp->rd_bpp) { 894 case 8: 895 dp->rd_format = 2; 896 break; 897 case 32: 898 dp->rd_format = 6; 899 break; 900 default: 901 aprint_error("%s: bad depth %d\n", XNAME(sc), 902 dp->rd_bpp); 903 goto error; 904 } 905 906 DPRINTF(("init engine\n")); 907 /* XXX: this seems suspicious - per display engine 908 initialization? */ 909 radeonfb_engine_init(dp); 910 911 /* copy the template into place */ 912 dp->rd_wsscreens_storage[0] = radeonfb_stdscreen; 913 dp->rd_wsscreens = dp->rd_wsscreens_storage; 914 915 /* and make up the list */ 916 dp->rd_wsscreenlist.nscreens = 1; 917 dp->rd_wsscreenlist.screens = (void *)&dp->rd_wsscreens; 918 919 vcons_init(&dp->rd_vd, dp, dp->rd_wsscreens, 920 &radeonfb_accessops); 921 922 dp->rd_vd.init_screen = radeonfb_init_screen; 923 924 #ifdef RADEONFB_DEBUG 925 dp->rd_virty -= 200; 926 #endif 927 928 dp->rd_console = 0; 929 prop_dictionary_get_bool(device_properties(sc->sc_dev), 930 "is_console", &dp->rd_console); 931 932 dp->rd_vscreen.scr_flags |= VCONS_SCREEN_IS_STATIC; 933 934 935 vcons_init_screen(&dp->rd_vd, &dp->rd_vscreen, 936 dp->rd_console, &defattr); 937 938 ri = &dp->rd_vscreen.scr_ri; 939 940 /* clear the screen */ 941 rasops_unpack_attr(defattr, &fg, &bg, &ul); 942 dp->rd_bg = ri->ri_devcmap[bg & 0xf]; 943 radeonfb_rectfill(dp, 0, 0, ri->ri_width, ri->ri_height, 944 dp->rd_bg); 945 946 dp->rd_wsscreens->textops = &ri->ri_ops; 947 dp->rd_wsscreens->capabilities = ri->ri_caps; 948 dp->rd_wsscreens->nrows = ri->ri_rows; 949 dp->rd_wsscreens->ncols = ri->ri_cols; 950 951 #ifdef SPLASHSCREEN 952 dp->rd_splash.si_depth = ri->ri_depth; 953 dp->rd_splash.si_bits = ri->ri_bits; 954 dp->rd_splash.si_hwbits = ri->ri_hwbits; 955 dp->rd_splash.si_width = ri->ri_width; 956 dp->rd_splash.si_height = ri->ri_height; 957 dp->rd_splash.si_stride = ri->ri_stride; 958 dp->rd_splash.si_fillrect = NULL; 959 #endif 960 dp->rd_gc.gc_bitblt = radeonfb_bitblt; 961 dp->rd_gc.gc_rectfill = radeonfb_rectfill_a; 962 dp->rd_gc.gc_rop = RADEON_ROP3_S; 963 dp->rd_gc.gc_blitcookie = dp; 964 /* 965 * use memory between framebuffer and cursor area as glyph 966 * cache, cap at 4096 lines 967 */ 968 glyphcache_init(&dp->rd_gc, dp->rd_virty + 4, 969 uimin(4096, 970 (dp->rd_curoff / dp->rd_stride) - (dp->rd_virty + 4)), 971 dp->rd_virtx, 972 ri->ri_font->fontwidth, 973 ri->ri_font->fontheight, 974 defattr); 975 dp->rd_vd.show_screen_cookie = &dp->rd_gc; 976 dp->rd_vd.show_screen_cb = glyphcache_adapt; 977 978 if (dp->rd_console) { 979 980 radeonfb_modeswitch(dp); 981 wsdisplay_cnattach(dp->rd_wsscreens, ri, 0, 0, 982 defattr); 983 #ifdef SPLASHSCREEN 984 if (splash_render(&dp->rd_splash, 985 SPLASH_F_CENTER|SPLASH_F_FILL) == 0) 986 SCREEN_DISABLE_DRAWING(&dp->rd_vscreen); 987 else 988 #endif 989 vcons_replay_msgbuf(&dp->rd_vscreen); 990 } else { 991 992 /* 993 * since we're not the console we can postpone 994 * the rest until someone actually allocates a 995 * screen for us. but we do clear the screen 996 * at least. 997 */ 998 memset(ri->ri_bits, 0, 1024); 999 1000 radeonfb_modeswitch(dp); 1001 #ifdef SPLASHSCREEN 1002 if (splash_render(&dp->rd_splash, 1003 SPLASH_F_CENTER|SPLASH_F_FILL) == 0) 1004 SCREEN_DISABLE_DRAWING(&dp->rd_vscreen); 1005 #endif 1006 } 1007 1008 aa.console = dp->rd_console; 1009 aa.scrdata = &dp->rd_wsscreenlist; 1010 aa.accessops = &radeonfb_accessops; 1011 aa.accesscookie = &dp->rd_vd; 1012 1013 config_found(sc->sc_dev, &aa, wsemuldisplaydevprint); 1014 1015 radeonfb_blank(dp, 0); 1016 1017 /* Initialise delayed lvds operations for backlight. */ 1018 callout_init(&dp->rd_bl_lvds_co, 0); 1019 callout_setfunc(&dp->rd_bl_lvds_co, 1020 radeonfb_lvds_callout, dp); 1021 dp->rd_bl_on = 1; 1022 dp->rd_bl_level = radeonfb_get_backlight(dp); 1023 radeonfb_set_backlight(dp, dp->rd_bl_level); 1024 } 1025 1026 for (i = 0; i < RADEON_NDISPLAYS; i++) 1027 radeonfb_init_palette(&sc->sc_displays[i]); 1028 1029 if (HAS_CRTC2(sc)) { 1030 CLR32(sc, RADEON_CRTC2_GEN_CNTL, RADEON_CRTC2_DISP_DIS); 1031 } 1032 1033 CLR32(sc, RADEON_CRTC_EXT_CNTL, RADEON_CRTC_DISPLAY_DIS); 1034 SET32(sc, RADEON_FP_GEN_CNTL, RADEON_FP_FPON); 1035 pmf_event_register(dev, PMFE_DISPLAY_BRIGHTNESS_UP, 1036 radeonfb_brightness_up, TRUE); 1037 pmf_event_register(dev, PMFE_DISPLAY_BRIGHTNESS_DOWN, 1038 radeonfb_brightness_down, TRUE); 1039 1040 /* 1041 * if we attach a DRM we need to unmap registers in 1042 * WSDISPLAYIO_MODE_MAPPED, since this keeps us from doing things like 1043 * screen blanking we only do it if needed 1044 */ 1045 sc->sc_needs_unmap = 1046 (config_found_ia(dev, "drm", aux, radeonfb_drm_print) != 0); 1047 DPRINTF(("needs_unmap: %d\n", sc->sc_needs_unmap)); 1048 1049 PRINTREG(RADEON_CRTC_EXT_CNTL); 1050 PRINTREG(RADEON_CRTC_GEN_CNTL); 1051 PRINTREG(RADEON_CRTC2_GEN_CNTL); 1052 PRINTREG(RADEON_DISP_OUTPUT_CNTL); 1053 PRINTREG(RADEON_DAC_CNTL2); 1054 PRINTREG(RADEON_FP_GEN_CNTL); 1055 PRINTREG(RADEON_FP2_GEN_CNTL); 1056 PRINTREG(RADEON_TMDS_CNTL); 1057 PRINTREG(RADEON_TMDS_TRANSMITTER_CNTL); 1058 PRINTREG(RADEON_TMDS_PLL_CNTL); 1059 PRINTREG(RADEON_PIXCLKS_CNTL); 1060 1061 return; 1062 1063 error: 1064 if (sc->sc_biossz) 1065 free(sc->sc_bios, M_DEVBUF); 1066 1067 if (sc->sc_regsz) 1068 bus_space_unmap(sc->sc_regt, sc->sc_regh, sc->sc_regsz); 1069 1070 if (sc->sc_memsz) 1071 bus_space_unmap(sc->sc_memt, sc->sc_memh, sc->sc_memsz); 1072 } 1073 1074 static void 1075 radeonfb_map(struct radeonfb_softc *sc) 1076 { 1077 if (!sc->sc_mapped) { 1078 if (bus_space_map(sc->sc_regt, sc->sc_regaddr, sc->sc_regsz, 0, 1079 &sc->sc_regh) != 0) { 1080 aprint_error_dev(sc->sc_dev, 1081 "unable to map registers!\n"); 1082 return; 1083 } 1084 if (bus_space_map(sc->sc_memt, sc->sc_memaddr, sc->sc_memsz, 1085 BUS_SPACE_MAP_LINEAR, &sc->sc_memh) != 0) { 1086 sc->sc_memsz = 0; 1087 aprint_error_dev(sc->sc_dev, 1088 "Unable to map frame buffer\n"); 1089 return; 1090 } 1091 sc->sc_mapped = TRUE; 1092 } 1093 } 1094 1095 static void 1096 radeonfb_unmap(struct radeonfb_softc *sc) 1097 { 1098 if (!sc->sc_needs_unmap) 1099 return; 1100 1101 if (sc->sc_mapped) { 1102 bus_space_unmap(sc->sc_regt, sc->sc_regh, sc->sc_regsz); 1103 bus_space_unmap(sc->sc_memt, sc->sc_memh, sc->sc_memsz); 1104 sc->sc_mapped = FALSE; 1105 } 1106 } 1107 1108 static int 1109 radeonfb_drm_print(void *aux, const char *pnp) 1110 { 1111 if (pnp) 1112 aprint_normal("drm at %s", pnp); 1113 return (UNCONF); 1114 } 1115 1116 int 1117 radeonfb_ioctl(void *v, void *vs, 1118 unsigned long cmd, void *d, int flag, struct lwp *l) 1119 { 1120 struct vcons_data *vd; 1121 struct radeonfb_display *dp; 1122 struct radeonfb_softc *sc; 1123 struct wsdisplay_param *param; 1124 struct vcons_screen *ms; 1125 1126 vd = (struct vcons_data *)v; 1127 ms = vd->active; 1128 dp = (struct radeonfb_display *)vd->cookie; 1129 sc = dp->rd_softc; 1130 1131 /* can't do these without registers being mapped */ 1132 if (!sc->sc_mapped) { 1133 switch (cmd) { 1134 case WSDISPLAYIO_GVIDEO: 1135 case WSDISPLAYIO_SVIDEO: 1136 case WSDISPLAYIO_GETCMAP: 1137 case WSDISPLAYIO_PUTCMAP: 1138 case WSDISPLAYIO_SCURSOR: 1139 case WSDISPLAYIO_GCURPOS: 1140 case WSDISPLAYIO_SCURPOS: 1141 case WSDISPLAYIO_SETPARAM: 1142 return EINVAL; 1143 } 1144 } 1145 1146 switch (cmd) { 1147 case WSDISPLAYIO_GTYPE: 1148 *(unsigned *)d = WSDISPLAY_TYPE_PCIMISC; 1149 return 0; 1150 1151 case WSDISPLAYIO_GINFO: 1152 if (vd->active != NULL) { 1153 struct wsdisplay_fbinfo *fb; 1154 fb = (struct wsdisplay_fbinfo *)d; 1155 fb->width = dp->rd_virtx; 1156 fb->height = dp->rd_virty; 1157 fb->depth = dp->rd_bpp; 1158 fb->cmsize = 256; 1159 return 0; 1160 } else 1161 return ENODEV; 1162 case WSDISPLAYIO_GVIDEO: 1163 if (radeonfb_isblank(dp)) 1164 *(unsigned *)d = WSDISPLAYIO_VIDEO_OFF; 1165 else 1166 *(unsigned *)d = WSDISPLAYIO_VIDEO_ON; 1167 return 0; 1168 1169 case WSDISPLAYIO_SVIDEO: 1170 radeonfb_blank(dp, 1171 (*(unsigned int *)d == WSDISPLAYIO_VIDEO_OFF)); 1172 radeonfb_switch_backlight(dp, 1173 (*(unsigned int *)d == WSDISPLAYIO_VIDEO_ON)); 1174 return 0; 1175 1176 case WSDISPLAYIO_GETCMAP: 1177 if (dp->rd_bpp == 8) 1178 return radeonfb_getcmap(dp, 1179 (struct wsdisplay_cmap *)d); 1180 return EINVAL; 1181 1182 case WSDISPLAYIO_PUTCMAP: 1183 if (dp->rd_bpp == 8) 1184 return radeonfb_putcmap(dp, 1185 (struct wsdisplay_cmap *)d); 1186 return EINVAL; 1187 1188 case WSDISPLAYIO_LINEBYTES: 1189 *(unsigned *)d = dp->rd_stride; 1190 return 0; 1191 1192 case WSDISPLAYIO_SMODE: 1193 if (*(int *)d != dp->rd_wsmode) { 1194 dp->rd_wsmode = *(int *)d; 1195 if ((dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) || 1196 (dp->rd_wsmode == WSDISPLAYIO_MODE_DUMBFB)) 1197 radeonfb_map(sc); 1198 1199 if ((dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) && 1200 (dp->rd_vd.active)) { 1201 radeonfb_engine_init(dp); 1202 glyphcache_wipe(&dp->rd_gc); 1203 radeonfb_init_palette(dp); 1204 radeonfb_modeswitch(dp); 1205 radeonfb_rectfill(dp, 0, 0, dp->rd_virtx, 1206 dp->rd_virty, dp->rd_bg); 1207 vcons_redraw_screen(dp->rd_vd.active); 1208 } 1209 if (dp->rd_wsmode == WSDISPLAYIO_MODE_MAPPED) 1210 radeonfb_unmap(sc); 1211 } 1212 return 0; 1213 1214 case WSDISPLAYIO_GCURMAX: 1215 ((struct wsdisplay_curpos *)d)->x = RADEON_CURSORMAXX; 1216 ((struct wsdisplay_curpos *)d)->y = RADEON_CURSORMAXY; 1217 return 0; 1218 1219 case WSDISPLAYIO_SCURSOR: 1220 return radeonfb_set_cursor(dp, (struct wsdisplay_cursor *)d); 1221 1222 case WSDISPLAYIO_GCURSOR: 1223 return EPASSTHROUGH; 1224 1225 case WSDISPLAYIO_GCURPOS: 1226 ((struct wsdisplay_curpos *)d)->x = dp->rd_cursor.rc_pos.x; 1227 ((struct wsdisplay_curpos *)d)->y = dp->rd_cursor.rc_pos.y; 1228 return 0; 1229 1230 case WSDISPLAYIO_SCURPOS: 1231 return radeonfb_set_curpos(dp, (struct wsdisplay_curpos *)d); 1232 1233 case WSDISPLAYIO_SSPLASH: 1234 #if defined(SPLASHSCREEN) 1235 if (*(int *)d == 1) { 1236 SCREEN_DISABLE_DRAWING(&dp->rd_vscreen); 1237 splash_render(&dp->rd_splash, 1238 SPLASH_F_CENTER|SPLASH_F_FILL); 1239 } else 1240 SCREEN_ENABLE_DRAWING(&dp->rd_vscreen); 1241 return 0; 1242 #else 1243 return ENODEV; 1244 #endif 1245 case WSDISPLAYIO_GETPARAM: 1246 param = (struct wsdisplay_param *)d; 1247 switch (param->param) { 1248 case WSDISPLAYIO_PARAM_BRIGHTNESS: 1249 param->min = 0; 1250 param->max = 255; 1251 param->curval = dp->rd_bl_level; 1252 return 0; 1253 case WSDISPLAYIO_PARAM_BACKLIGHT: 1254 param->min = 0; 1255 param->max = RADEONFB_BACKLIGHT_MAX; 1256 param->curval = dp->rd_bl_on; 1257 return 0; 1258 } 1259 return EPASSTHROUGH; 1260 1261 case WSDISPLAYIO_SETPARAM: 1262 param = (struct wsdisplay_param *)d; 1263 switch (param->param) { 1264 case WSDISPLAYIO_PARAM_BRIGHTNESS: 1265 radeonfb_set_backlight(dp, param->curval); 1266 return 0; 1267 case WSDISPLAYIO_PARAM_BACKLIGHT: 1268 radeonfb_switch_backlight(dp, param->curval); 1269 return 0; 1270 } 1271 return EPASSTHROUGH; 1272 1273 /* PCI config read/write passthrough. */ 1274 case PCI_IOC_CFGREAD: 1275 case PCI_IOC_CFGWRITE: 1276 return pci_devioctl(sc->sc_pc, sc->sc_pt, cmd, d, flag, l); 1277 1278 case WSDISPLAYIO_GET_BUSID: 1279 return wsdisplayio_busid_pci(sc->sc_dev, sc->sc_pc, 1280 sc->sc_pt, d); 1281 1282 case WSDISPLAYIO_GET_EDID: { 1283 struct wsdisplayio_edid_info *ei = d; 1284 return wsdisplayio_get_edid(sc->sc_dev, ei); 1285 } 1286 1287 case WSDISPLAYIO_GET_FBINFO: { 1288 struct wsdisplayio_fbinfo *fbi = d; 1289 return wsdisplayio_get_fbinfo(&ms->scr_ri, fbi); 1290 } 1291 1292 default: 1293 return EPASSTHROUGH; 1294 } 1295 } 1296 1297 paddr_t 1298 radeonfb_mmap(void *v, void *vs, off_t offset, int prot) 1299 { 1300 struct vcons_data *vd; 1301 struct radeonfb_display *dp; 1302 struct radeonfb_softc *sc; 1303 paddr_t pa; 1304 1305 vd = (struct vcons_data *)v; 1306 dp = (struct radeonfb_display *)vd->cookie; 1307 sc = dp->rd_softc; 1308 1309 if ((offset >= 0) && (offset < (dp->rd_virty * dp->rd_stride))) { 1310 pa = bus_space_mmap(sc->sc_memt, 1311 sc->sc_memaddr + dp->rd_offset + offset, 0, 1312 prot, BUS_SPACE_MAP_LINEAR); 1313 return pa; 1314 } 1315 1316 /* 1317 * restrict all other mappings to processes with superuser privileges 1318 * or the kernel itself 1319 */ 1320 if (kauth_authorize_machdep(kauth_cred_get(), KAUTH_MACHDEP_UNMANAGEDMEM, 1321 NULL, NULL, NULL, NULL) != 0) { 1322 aprint_error_dev(sc->sc_dev, "mmap() rejected.\n"); 1323 return -1; 1324 } 1325 1326 if ((offset >= sc->sc_regaddr) && 1327 (offset < sc->sc_regaddr + sc->sc_regsz)) { 1328 return bus_space_mmap(sc->sc_regt, offset, 0, prot, 1329 BUS_SPACE_MAP_LINEAR); 1330 } 1331 1332 if ((offset >= sc->sc_memaddr) && 1333 (offset < sc->sc_memaddr + sc->sc_memsz)) { 1334 return bus_space_mmap(sc->sc_memt, offset, 0, prot, 1335 BUS_SPACE_MAP_LINEAR); 1336 } 1337 1338 if ((offset >= sc->sc_romaddr) && 1339 (offset < sc->sc_romaddr + sc->sc_romsz)) { 1340 return bus_space_mmap(sc->sc_memt, offset, 0, prot, 1341 BUS_SPACE_MAP_LINEAR); 1342 } 1343 1344 #ifdef PCI_MAGIC_IO_RANGE 1345 /* allow mapping of IO space */ 1346 if ((offset >= PCI_MAGIC_IO_RANGE) && 1347 (offset < PCI_MAGIC_IO_RANGE + 0x10000)) { 1348 pa = bus_space_mmap(sc->sc_iot, offset - PCI_MAGIC_IO_RANGE, 1349 0, prot, 0); 1350 return pa; 1351 } 1352 #endif /* PCI_MAGIC_IO_RANGE */ 1353 1354 return -1; 1355 } 1356 1357 static void 1358 radeonfb_loadbios(struct radeonfb_softc *sc, const struct pci_attach_args *pa) 1359 { 1360 bus_space_tag_t romt; 1361 bus_space_handle_t romh, biosh; 1362 bus_size_t romsz; 1363 bus_addr_t ptr; 1364 uint32_t busctl, crtcg, crtc2g = 0, viphctl, seprom, extc; 1365 int bios_voodoo = 0; 1366 1367 if (pci_mapreg_map(pa, PCI_MAPREG_ROM, PCI_MAPREG_TYPE_ROM, 1368 BUS_SPACE_MAP_PREFETCHABLE, &romt, &romh, NULL, &romsz) != 0) { 1369 aprint_verbose("%s: unable to map BIOS!\n", XNAME(sc)); 1370 return; 1371 } 1372 1373 pci_find_rom(pa, romt, romh, romsz, PCI_ROM_CODE_TYPE_X86, &biosh, 1374 &sc->sc_biossz); 1375 if (sc->sc_biossz != 0) goto foundit; 1376 1377 aprint_verbose("trying to read disabled BIOS...\n"); 1378 1379 bios_voodoo = 1; 1380 seprom = radeonfb_get32(sc, RADEON_SEPROM_CNTL1); 1381 radeonfb_put32(sc, RADEON_SEPROM_CNTL1, 1382 (seprom & ~RADEON_SCK_PRESCALE_MASK) | 1383 (0xc << RADEON_SCK_PRESCALE_SHIFT)); 1384 viphctl = radeonfb_get32(sc, RADEON_VIPH_CONTROL); 1385 radeonfb_put32(sc, RADEON_VIPH_CONTROL, viphctl & ~RADEON_VIPH_EN); 1386 busctl = radeonfb_get32(sc, RADEON_BUS_CNTL); 1387 radeonfb_put32(sc, RADEON_BUS_CNTL, busctl & ~RADEON_BUS_BIOS_DIS_ROM); 1388 crtcg = radeonfb_get32(sc, RADEON_CRTC_GEN_CNTL); 1389 radeonfb_put32(sc, RADEON_CRTC_GEN_CNTL, ((crtcg & ~RADEON_CRTC_EN) | 1390 (RADEON_CRTC_DISP_REQ_EN_B | 1391 RADEON_CRTC_EXT_DISP_EN))); 1392 if (HAS_CRTC2(sc)) { 1393 crtc2g = radeonfb_get32(sc, RADEON_CRTC2_GEN_CNTL); 1394 radeonfb_put32(sc, RADEON_CRTC2_GEN_CNTL, 1395 (crtc2g & ~RADEON_CRTC2_EN) | 1396 RADEON_CRTC2_DISP_REQ_EN_B); 1397 } 1398 extc = radeonfb_get32(sc, RADEON_CRTC_EXT_CNTL); 1399 radeonfb_put32(sc, RADEON_CRTC_EXT_CNTL, (extc & ~RADEON_CRTC_CRT_ON) | 1400 (RADEON_CRTC_SYNC_TRISTAT | 1401 RADEON_CRTC_DISPLAY_DIS)); 1402 pci_find_rom(pa, romt, romh, romsz, PCI_ROM_CODE_TYPE_X86, &biosh, 1403 &sc->sc_biossz); 1404 if (sc->sc_biossz != 0) printf("found disabled BIOS\n"); 1405 1406 foundit: 1407 sc->sc_bios = malloc(sc->sc_biossz, M_DEVBUF, M_WAITOK); 1408 bus_space_read_region_1(romt, biosh, 0, sc->sc_bios, sc->sc_biossz); 1409 1410 if (bios_voodoo != 0) { 1411 radeonfb_put32(sc, RADEON_CRTC_EXT_CNTL, extc); 1412 if (HAS_CRTC2(sc)) { 1413 radeonfb_put32(sc, RADEON_CRTC2_GEN_CNTL, crtc2g); 1414 } 1415 radeonfb_put32(sc, RADEON_CRTC_GEN_CNTL, crtcg); 1416 radeonfb_put32(sc, RADEON_BUS_CNTL, busctl); 1417 radeonfb_put32(sc, RADEON_VIPH_CONTROL, viphctl); 1418 radeonfb_put32(sc, RADEON_SEPROM_CNTL1, seprom); 1419 } 1420 1421 /* unmap the PCI expansion rom */ 1422 bus_space_unmap(romt, romh, romsz); 1423 1424 /* turn off rom decoder now */ 1425 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM, 1426 pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM) & 1427 ~PCI_MAPREG_ROM_ENABLE); 1428 1429 DPRINTF(("BIOS %08x\n", *(uint32_t *)sc->sc_bios)); 1430 1431 ptr = GETBIOS16(sc, 0x48); 1432 if ((GETBIOS32(sc, ptr + 4) == 0x41544f4d /* "ATOM" */) || 1433 (GETBIOS32(sc, ptr + 4) == 0x4d4f5441 /* "MOTA" */)) { 1434 sc->sc_flags |= RFB_ATOM; 1435 } 1436 1437 if (sc->sc_biossz > 0) { 1438 aprint_verbose("%s: Found %d KB %s BIOS\n", XNAME(sc), 1439 (unsigned)sc->sc_biossz >> 10, 1440 IS_ATOM(sc) ? "ATOM" : "Legacy"); 1441 } 1442 } 1443 1444 1445 uint32_t 1446 radeonfb_get32(struct radeonfb_softc *sc, uint32_t reg) 1447 { 1448 1449 return bus_space_read_4(sc->sc_regt, sc->sc_regh, reg); 1450 } 1451 1452 void 1453 radeonfb_put32(struct radeonfb_softc *sc, uint32_t reg, uint32_t val) 1454 { 1455 1456 bus_space_write_4(sc->sc_regt, sc->sc_regh, reg, val); 1457 } 1458 1459 void 1460 radeonfb_put32s(struct radeonfb_softc *sc, uint32_t reg, uint32_t val) 1461 { 1462 1463 bus_space_write_stream_4(sc->sc_regt, sc->sc_regh, reg, val); 1464 } 1465 1466 void 1467 radeonfb_mask32(struct radeonfb_softc *sc, uint32_t reg, 1468 uint32_t andmask, uint32_t ormask) 1469 { 1470 int s; 1471 uint32_t val; 1472 1473 s = splhigh(); 1474 val = radeonfb_get32(sc, reg); 1475 val = (val & andmask) | ormask; 1476 radeonfb_put32(sc, reg, val); 1477 splx(s); 1478 } 1479 1480 uint32_t 1481 radeonfb_getindex(struct radeonfb_softc *sc, uint32_t idx) 1482 { 1483 int s; 1484 uint32_t val; 1485 1486 s = splhigh(); 1487 radeonfb_put32(sc, RADEON_MM_INDEX, idx); 1488 val = radeonfb_get32(sc, RADEON_MM_DATA); 1489 splx(s); 1490 1491 return (val); 1492 } 1493 1494 void 1495 radeonfb_putindex(struct radeonfb_softc *sc, uint32_t idx, uint32_t val) 1496 { 1497 int s; 1498 1499 s = splhigh(); 1500 radeonfb_put32(sc, RADEON_MM_INDEX, idx); 1501 radeonfb_put32(sc, RADEON_MM_DATA, val); 1502 splx(s); 1503 } 1504 1505 void 1506 radeonfb_maskindex(struct radeonfb_softc *sc, uint32_t idx, 1507 uint32_t andmask, uint32_t ormask) 1508 { 1509 int s; 1510 uint32_t val; 1511 1512 s = splhigh(); 1513 radeonfb_put32(sc, RADEON_MM_INDEX, idx); 1514 val = radeonfb_get32(sc, RADEON_MM_DATA); 1515 val = (val & andmask) | ormask; 1516 radeonfb_put32(sc, RADEON_MM_DATA, val); 1517 splx(s); 1518 } 1519 1520 uint32_t 1521 radeonfb_getpll(struct radeonfb_softc *sc, uint32_t idx) 1522 { 1523 int s; 1524 uint32_t val; 1525 1526 s = splhigh(); 1527 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, (idx & 0x3f)); 1528 val = radeonfb_get32(sc, RADEON_CLOCK_CNTL_DATA); 1529 if (HAS_R300CG(sc)) 1530 radeonfb_r300cg_workaround(sc); 1531 splx(s); 1532 1533 return (val); 1534 } 1535 1536 void 1537 radeonfb_putpll(struct radeonfb_softc *sc, uint32_t idx, uint32_t val) 1538 { 1539 int s; 1540 1541 s = splhigh(); 1542 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, (idx & 0x3f) | 1543 RADEON_PLL_WR_EN); 1544 radeonfb_put32(sc, RADEON_CLOCK_CNTL_DATA, val); 1545 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, 0); 1546 splx(s); 1547 } 1548 1549 void 1550 radeonfb_maskpll(struct radeonfb_softc *sc, uint32_t idx, 1551 uint32_t andmask, uint32_t ormask) 1552 { 1553 int s; 1554 uint32_t val; 1555 1556 s = splhigh(); 1557 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, (idx & 0x3f) | 1558 RADEON_PLL_WR_EN); 1559 val = radeonfb_get32(sc, RADEON_CLOCK_CNTL_DATA); 1560 val = (val & andmask) | ormask; 1561 radeonfb_put32(sc, RADEON_CLOCK_CNTL_DATA, val); 1562 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, 0); 1563 splx(s); 1564 } 1565 1566 int 1567 radeonfb_scratch_test(struct radeonfb_softc *sc, int reg, uint32_t v) 1568 { 1569 uint32_t saved; 1570 1571 saved = GET32(sc, reg); 1572 PUT32(sc, reg, v); 1573 if (GET32(sc, reg) != v) { 1574 return -1; 1575 } 1576 PUT32(sc, reg, saved); 1577 return 0; 1578 } 1579 1580 uintmax_t 1581 radeonfb_getprop_num(struct radeonfb_softc *sc, const char *name, 1582 uintmax_t defval) 1583 { 1584 prop_number_t pn; 1585 pn = prop_dictionary_get(device_properties(sc->sc_dev), name); 1586 if (pn == NULL) { 1587 return defval; 1588 } 1589 KASSERT(prop_object_type(pn) == PROP_TYPE_NUMBER); 1590 return (prop_number_integer_value(pn)); 1591 } 1592 1593 int 1594 radeonfb_getclocks(struct radeonfb_softc *sc) 1595 { 1596 bus_addr_t ptr; 1597 int refclk = 0; 1598 int refdiv = 0; 1599 int minpll = 0; 1600 int maxpll = 0; 1601 1602 /* load initial property values if port/board provides them */ 1603 refclk = radeonfb_getprop_num(sc, "refclk", 0) & 0xffff; 1604 refdiv = radeonfb_getprop_num(sc, "refdiv", 0) & 0xffff; 1605 minpll = radeonfb_getprop_num(sc, "minpll", 0) & 0xffffffffU; 1606 maxpll = radeonfb_getprop_num(sc, "maxpll", 0) & 0xffffffffU; 1607 1608 PRINTPLL(RADEON_PPLL_REF_DIV); 1609 PRINTPLL(RADEON_PPLL_DIV_0); 1610 PRINTPLL(RADEON_PPLL_DIV_1); 1611 PRINTPLL(RADEON_PPLL_DIV_2); 1612 PRINTPLL(RADEON_PPLL_DIV_3); 1613 PRINTREG(RADEON_CLOCK_CNTL_INDEX); 1614 PRINTPLL(RADEON_P2PLL_REF_DIV); 1615 PRINTPLL(RADEON_P2PLL_DIV_0); 1616 1617 if (refclk && refdiv && minpll && maxpll) 1618 goto dontprobe; 1619 1620 if (!sc->sc_biossz) { 1621 /* no BIOS */ 1622 aprint_verbose("%s: No video BIOS, using default clocks\n", 1623 XNAME(sc)); 1624 if (IS_IGP(sc)) 1625 refclk = refclk ? refclk : 1432; 1626 else 1627 refclk = refclk ? refclk : 2700; 1628 refdiv = refdiv ? refdiv : 12; 1629 minpll = minpll ? minpll : 12500; 1630 /* XXX 1631 * Need to check if the firmware or something programmed a 1632 * higher value than this, and if so, bump it. 1633 * The RV280 in my iBook is unhappy if the PLL input is less 1634 * than 360MHz 1635 */ 1636 maxpll = maxpll ? maxpll : 40000/*35000*/; 1637 } else if (IS_ATOM(sc)) { 1638 /* ATOM BIOS */ 1639 ptr = GETBIOS16(sc, 0x48); 1640 ptr = GETBIOS16(sc, ptr + 32); /* aka MasterDataStart */ 1641 ptr = GETBIOS16(sc, ptr + 12); /* pll info block */ 1642 refclk = refclk ? refclk : GETBIOS16(sc, ptr + 82); 1643 minpll = minpll ? minpll : GETBIOS16(sc, ptr + 78); 1644 maxpll = maxpll ? maxpll : GETBIOS16(sc, ptr + 32); 1645 /* 1646 * ATOM BIOS doesn't supply a reference divider, so we 1647 * have to probe for it. 1648 */ 1649 if (refdiv < 2) 1650 refdiv = GETPLL(sc, RADEON_PPLL_REF_DIV) & 1651 RADEON_PPLL_REF_DIV_MASK; 1652 /* 1653 * if probe is zero, just assume one that should work 1654 * for most parts 1655 */ 1656 if (refdiv < 2) 1657 refdiv = 12; 1658 1659 } else { 1660 uint32_t tmp = GETPLL(sc, RADEON_PPLL_REF_DIV); 1661 /* Legacy BIOS */ 1662 ptr = GETBIOS16(sc, 0x48); 1663 ptr = GETBIOS16(sc, ptr + 0x30); 1664 if (IS_R300(sc)) { 1665 refdiv = refdiv ? refdiv : 1666 (tmp & R300_PPLL_REF_DIV_ACC_MASK) >> 1667 R300_PPLL_REF_DIV_ACC_SHIFT; 1668 } else { 1669 refdiv = refdiv ? refdiv : 1670 tmp & RADEON_PPLL_REF_DIV_MASK; 1671 } 1672 refclk = refclk ? refclk : GETBIOS16(sc, ptr + 0x0E); 1673 refdiv = refdiv ? refdiv : GETBIOS16(sc, ptr + 0x10); 1674 minpll = minpll ? minpll : GETBIOS32(sc, ptr + 0x12); 1675 maxpll = maxpll ? maxpll : GETBIOS32(sc, ptr + 0x16); 1676 } 1677 1678 1679 dontprobe: 1680 sc->sc_refclk = refclk * 10; 1681 sc->sc_refdiv = refdiv; 1682 sc->sc_minpll = minpll * 10; 1683 sc->sc_maxpll = maxpll * 10; 1684 return 0; 1685 } 1686 1687 int 1688 radeonfb_calc_dividers(struct radeonfb_softc *sc, uint32_t dotclock, 1689 uint32_t *postdivbit, uint32_t *feedbackdiv, int flags) 1690 { 1691 int i; 1692 uint32_t outfreq; 1693 int div; 1694 1695 DPRINTF(("dot clock: %u\n", dotclock)); 1696 for (i = 0; (div = radeonfb_dividers[i].divider) != 0; i++) { 1697 1698 if ((flags & NO_ODD_FBDIV) && ((div & 1) != 0)) 1699 continue; 1700 1701 /* 1702 * XXX 1703 * the rv350 in my last generation 14" iBook G4 produces 1704 * garbage with dividers > 4. No idea if this is a hardware 1705 * limitation or an error in the divider table. 1706 */ 1707 if ((sc->sc_family == RADEON_RV350) && (div > 4)) 1708 continue; 1709 1710 outfreq = div * dotclock; 1711 if ((outfreq >= sc->sc_minpll) && 1712 (outfreq <= sc->sc_maxpll)) { 1713 DPRINTF(("outfreq: %u\n", outfreq)); 1714 *postdivbit = 1715 ((uint32_t)radeonfb_dividers[i].mask << 16); 1716 DPRINTF(("post divider: %d (mask %x)\n", div, 1717 *postdivbit)); 1718 break; 1719 } 1720 } 1721 1722 if (div == 0) 1723 return 1; 1724 1725 *feedbackdiv = DIVIDE(sc->sc_refdiv * outfreq, sc->sc_refclk); 1726 DPRINTF(("feedback divider: %d\n", *feedbackdiv)); 1727 return 0; 1728 } 1729 1730 #if 0 1731 #ifdef RADEONFB_DEBUG 1732 static void 1733 dump_buffer(const char *pfx, void *buffer, unsigned int size) 1734 { 1735 char asc[17]; 1736 unsigned ptr = (unsigned)buffer; 1737 char *start = (char *)(ptr & ~0xf); 1738 char *end = (char *)(ptr + size); 1739 1740 end = (char *)(((unsigned)end + 0xf) & ~0xf); 1741 1742 if (pfx == NULL) { 1743 pfx = ""; 1744 } 1745 1746 while (start < end) { 1747 unsigned offset = (unsigned)start & 0xf; 1748 if (offset == 0) { 1749 printf("%s%x: ", pfx, (unsigned)start); 1750 } 1751 if (((unsigned)start < ptr) || 1752 ((unsigned)start >= (ptr + size))) { 1753 printf(" "); 1754 asc[offset] = ' '; 1755 } else { 1756 printf("%02x", *(unsigned char *)start); 1757 if ((*start >= ' ') && (*start <= '~')) { 1758 asc[offset] = *start; 1759 } else { 1760 asc[offset] = '.'; 1761 } 1762 } 1763 asc[offset + 1] = 0; 1764 if (offset % 2) { 1765 printf(" "); 1766 } 1767 if (offset == 15) { 1768 printf(" %s\n", asc); 1769 } 1770 start++; 1771 } 1772 } 1773 #endif 1774 #endif 1775 1776 int 1777 radeonfb_getconnectors(struct radeonfb_softc *sc) 1778 { 1779 int i; 1780 int found = 0; 1781 1782 for (i = 0; i < 2; i++) { 1783 sc->sc_ports[i].rp_mon_type = RADEON_MT_UNKNOWN; 1784 sc->sc_ports[i].rp_ddc_type = RADEON_DDC_NONE; 1785 sc->sc_ports[i].rp_dac_type = RADEON_DAC_UNKNOWN; 1786 sc->sc_ports[i].rp_conn_type = RADEON_CONN_NONE; 1787 sc->sc_ports[i].rp_tmds_type = RADEON_TMDS_UNKNOWN; 1788 } 1789 1790 /* 1791 * This logic is borrowed from Xorg's radeon driver. 1792 */ 1793 if (!sc->sc_biossz) 1794 goto nobios; 1795 1796 if (IS_ATOM(sc)) { 1797 /* not done yet */ 1798 } else { 1799 uint16_t ptr; 1800 int port = 0; 1801 1802 ptr = GETBIOS16(sc, 0x48); 1803 ptr = GETBIOS16(sc, ptr + 0x50); 1804 for (i = 1; i < 4; i++) { 1805 uint16_t entry; 1806 uint8_t conn, ddc, dac, tmds; 1807 1808 /* 1809 * Parse the connector table. From reading the code, 1810 * it appears to made up of 16-bit entries for each 1811 * connector. The 16-bits are defined as: 1812 * 1813 * bits 12-15 - connector type (0 == end of table) 1814 * bits 8-11 - DDC type 1815 * bits 5-7 - ??? 1816 * bit 4 - TMDS type (1 = EXT, 0 = INT) 1817 * bits 1-3 - ??? 1818 * bit 0 - DAC, 1 = TVDAC, 0 = primary 1819 */ 1820 if (!GETBIOS8(sc, ptr + i * 2) && i > 1) 1821 break; 1822 entry = GETBIOS16(sc, ptr + i * 2); 1823 1824 conn = (entry >> 12) & 0xf; 1825 ddc = (entry >> 8) & 0xf; 1826 dac = (entry & 0x1) ? RADEON_DAC_TVDAC : 1827 RADEON_DAC_PRIMARY; 1828 tmds = ((entry >> 4) & 0x1) ? RADEON_TMDS_EXT : 1829 RADEON_TMDS_INT; 1830 1831 if (conn == RADEON_CONN_NONE) 1832 continue; /* no connector */ 1833 1834 /* 1835 * XXX 1836 * both Mac Mini variants have both outputs wired to 1837 * the same connector and share the DDC lines 1838 */ 1839 if ((found > 0) && 1840 (sc->sc_ports[port].rp_ddc_type == ddc)) { 1841 /* duplicate entry for same connector */ 1842 continue; 1843 } 1844 1845 /* internal DDC_DVI port gets priority */ 1846 if ((ddc == RADEON_DDC_DVI) || (port == 1)) 1847 port = 0; 1848 else 1849 port = 1; 1850 1851 sc->sc_ports[port].rp_ddc_type = 1852 ddc > RADEON_DDC_CRT2 ? RADEON_DDC_NONE : ddc; 1853 sc->sc_ports[port].rp_dac_type = dac; 1854 sc->sc_ports[port].rp_conn_type = 1855 uimin(conn, RADEON_CONN_UNSUPPORTED) ; 1856 1857 sc->sc_ports[port].rp_tmds_type = tmds; 1858 1859 if ((conn != RADEON_CONN_DVI_I) && 1860 (conn != RADEON_CONN_DVI_D) && 1861 (tmds == RADEON_TMDS_INT)) 1862 sc->sc_ports[port].rp_tmds_type = 1863 RADEON_TMDS_UNKNOWN; 1864 sc->sc_ports[port].rp_number = i - 1; 1865 1866 found += (port + 1); 1867 } 1868 } 1869 1870 nobios: 1871 if (!found) { 1872 bool dvi_ext = FALSE, dvi_int = FALSE; 1873 DPRINTF(("No connector info in BIOS!\n")); 1874 prop_dictionary_get_bool(device_properties(sc->sc_dev), 1875 "dvi-internal", &dvi_int); 1876 prop_dictionary_get_bool(device_properties(sc->sc_dev), 1877 "dvi-external", &dvi_ext); 1878 if (dvi_ext) { 1879 sc->sc_ports[0].rp_mon_type = RADEON_MT_UNKNOWN; 1880 sc->sc_ports[0].rp_ddc_type = RADEON_DDC_CRT2; 1881 sc->sc_ports[0].rp_dac_type = RADEON_DAC_PRIMARY; 1882 sc->sc_ports[0].rp_conn_type = RADEON_CONN_DVI_I; 1883 sc->sc_ports[0].rp_tmds_type = RADEON_TMDS_EXT; /* output to fp2 */ 1884 sc->sc_ports[0].rp_number = 0; 1885 sc->sc_ports[1].rp_mon_type = RADEON_MT_UNKNOWN; 1886 sc->sc_ports[1].rp_ddc_type = RADEON_DDC_NONE; 1887 sc->sc_ports[1].rp_dac_type = RADEON_DAC_UNKNOWN; 1888 sc->sc_ports[1].rp_conn_type = RADEON_CONN_NONE; 1889 sc->sc_ports[1].rp_tmds_type = RADEON_TMDS_UNKNOWN; 1890 sc->sc_ports[1].rp_number = 1; 1891 } else if (dvi_int) { 1892 sc->sc_ports[0].rp_mon_type = RADEON_MT_UNKNOWN; 1893 sc->sc_ports[0].rp_ddc_type = RADEON_DDC_CRT2; 1894 sc->sc_ports[0].rp_dac_type = RADEON_DAC_PRIMARY; 1895 sc->sc_ports[0].rp_conn_type = RADEON_CONN_DVI_I; 1896 sc->sc_ports[0].rp_tmds_type = RADEON_TMDS_INT; 1897 sc->sc_ports[0].rp_number = 0; 1898 sc->sc_ports[1].rp_mon_type = RADEON_MT_UNKNOWN; 1899 sc->sc_ports[1].rp_ddc_type = RADEON_DDC_NONE; 1900 sc->sc_ports[1].rp_dac_type = RADEON_DAC_UNKNOWN; 1901 sc->sc_ports[1].rp_conn_type = RADEON_CONN_NONE; 1902 sc->sc_ports[1].rp_tmds_type = RADEON_TMDS_UNKNOWN; 1903 sc->sc_ports[1].rp_number = 1; 1904 } else if IS_MOBILITY(sc) { 1905 /* default, port 0 = internal TMDS, port 1 = CRT */ 1906 sc->sc_ports[0].rp_mon_type = RADEON_MT_UNKNOWN; 1907 sc->sc_ports[0].rp_ddc_type = RADEON_DDC_DVI; 1908 sc->sc_ports[0].rp_dac_type = RADEON_DAC_TVDAC; 1909 sc->sc_ports[0].rp_conn_type = RADEON_CONN_DVI_D; 1910 sc->sc_ports[0].rp_tmds_type = RADEON_TMDS_INT; 1911 sc->sc_ports[0].rp_number = 0; 1912 1913 sc->sc_ports[1].rp_mon_type = RADEON_MT_UNKNOWN; 1914 sc->sc_ports[1].rp_ddc_type = RADEON_DDC_VGA; 1915 sc->sc_ports[1].rp_dac_type = RADEON_DAC_PRIMARY; 1916 sc->sc_ports[1].rp_conn_type = RADEON_CONN_CRT; 1917 sc->sc_ports[1].rp_tmds_type = RADEON_TMDS_EXT; 1918 sc->sc_ports[1].rp_number = 1; 1919 } else { 1920 /* default, port 0 = DVI, port 1 = CRT */ 1921 sc->sc_ports[0].rp_mon_type = RADEON_MT_UNKNOWN; 1922 sc->sc_ports[0].rp_ddc_type = RADEON_DDC_DVI; 1923 sc->sc_ports[0].rp_dac_type = RADEON_DAC_TVDAC; 1924 sc->sc_ports[0].rp_conn_type = RADEON_CONN_DVI_D; 1925 sc->sc_ports[0].rp_tmds_type = RADEON_TMDS_INT; 1926 sc->sc_ports[0].rp_number = 1; 1927 1928 sc->sc_ports[1].rp_mon_type = RADEON_MT_UNKNOWN; 1929 sc->sc_ports[1].rp_ddc_type = RADEON_DDC_VGA; 1930 sc->sc_ports[1].rp_dac_type = RADEON_DAC_PRIMARY; 1931 sc->sc_ports[1].rp_conn_type = RADEON_CONN_CRT; 1932 sc->sc_ports[1].rp_tmds_type = RADEON_TMDS_UNKNOWN; 1933 sc->sc_ports[1].rp_number = 0; 1934 } 1935 } 1936 1937 /* 1938 * Fixup for RS300/RS350/RS400 chips, that lack a primary DAC. 1939 * these chips should use TVDAC for the VGA port. 1940 */ 1941 if (HAS_SDAC(sc)) { 1942 if (sc->sc_ports[0].rp_conn_type == RADEON_CONN_CRT) { 1943 sc->sc_ports[0].rp_dac_type = RADEON_DAC_TVDAC; 1944 sc->sc_ports[1].rp_dac_type = RADEON_DAC_PRIMARY; 1945 } else { 1946 sc->sc_ports[1].rp_dac_type = RADEON_DAC_TVDAC; 1947 sc->sc_ports[0].rp_dac_type = RADEON_DAC_PRIMARY; 1948 } 1949 } else if (!HAS_CRTC2(sc)) { 1950 sc->sc_ports[0].rp_dac_type = RADEON_DAC_PRIMARY; 1951 } 1952 1953 for (i = 0; i < 2; i++) { 1954 char edid[128]; 1955 uint8_t ddc; 1956 struct edid_info *eip = &sc->sc_ports[i].rp_edid; 1957 prop_data_t edid_data; 1958 1959 DPRINTF(("Port #%d:\n", i)); 1960 DPRINTF((" conn = %d\n", sc->sc_ports[i].rp_conn_type)); 1961 DPRINTF((" ddc = %d\n", sc->sc_ports[i].rp_ddc_type)); 1962 DPRINTF((" dac = %d\n", sc->sc_ports[i].rp_dac_type)); 1963 DPRINTF((" tmds = %d\n", sc->sc_ports[i].rp_tmds_type)); 1964 DPRINTF((" crtc = %d\n", sc->sc_ports[i].rp_number)); 1965 1966 sc->sc_ports[i].rp_edid_valid = 0; 1967 /* first look for static EDID data */ 1968 if ((edid_data = prop_dictionary_get(device_properties( 1969 sc->sc_dev), "EDID")) != NULL) { 1970 1971 aprint_debug_dev(sc->sc_dev, "using static EDID\n"); 1972 memcpy(edid, prop_data_data_nocopy(edid_data), 128); 1973 if (edid_parse(edid, eip) == 0) { 1974 1975 sc->sc_ports[i].rp_edid_valid = 1; 1976 #ifdef RADEONFB_DEBUG 1977 edid_print(eip); 1978 #endif 1979 } 1980 } 1981 /* if we didn't find any we'll try to talk to the monitor */ 1982 if (sc->sc_ports[i].rp_edid_valid != 1) { 1983 1984 ddc = sc->sc_ports[i].rp_ddc_type; 1985 if (ddc != RADEON_DDC_NONE) { 1986 if ((radeonfb_i2c_read_edid(sc, ddc, edid) 1987 == 0) && (edid_parse(edid, eip) == 0)) { 1988 1989 sc->sc_ports[i].rp_edid_valid = 1; 1990 #ifdef RADEONFB_DEBUG 1991 edid_print(eip); 1992 #endif 1993 } 1994 } 1995 } 1996 } 1997 1998 return found; 1999 } 2000 2001 int 2002 radeonfb_gettmds(struct radeonfb_softc *sc) 2003 { 2004 int i; 2005 2006 if (!sc->sc_biossz) { 2007 goto nobios; 2008 } 2009 2010 if (IS_ATOM(sc)) { 2011 /* XXX: not done yet */ 2012 } else { 2013 uint16_t ptr; 2014 int n; 2015 2016 ptr = GETBIOS16(sc, 0x48); 2017 ptr = GETBIOS16(sc, ptr + 0x34); 2018 DPRINTF(("DFP table revision %d\n", GETBIOS8(sc, ptr))); 2019 if (GETBIOS8(sc, ptr) == 3) { 2020 /* revision three table */ 2021 n = GETBIOS8(sc, ptr + 5) + 1; 2022 n = uimin(n, 4); 2023 2024 memset(sc->sc_tmds_pll, 0, sizeof (sc->sc_tmds_pll)); 2025 for (i = 0; i < n; i++) { 2026 sc->sc_tmds_pll[i].rtp_pll = GETBIOS32(sc, 2027 ptr + i * 10 + 8); 2028 sc->sc_tmds_pll[i].rtp_freq = GETBIOS16(sc, 2029 ptr + i * 10 + 0x10); 2030 DPRINTF(("TMDS_PLL dot clock %d pll %x\n", 2031 sc->sc_tmds_pll[i].rtp_freq, 2032 sc->sc_tmds_pll[i].rtp_pll)); 2033 } 2034 return 0; 2035 } 2036 } 2037 2038 nobios: 2039 DPRINTF(("no suitable DFP table present\n")); 2040 for (i = 0; 2041 i < sizeof (radeonfb_tmds_pll) / sizeof (radeonfb_tmds_pll[0]); 2042 i++) { 2043 int j; 2044 2045 if (radeonfb_tmds_pll[i].family != sc->sc_family) 2046 continue; 2047 2048 for (j = 0; j < 4; j++) { 2049 sc->sc_tmds_pll[j] = radeonfb_tmds_pll[i].plls[j]; 2050 DPRINTF(("TMDS_PLL dot clock %d pll %x\n", 2051 sc->sc_tmds_pll[j].rtp_freq, 2052 sc->sc_tmds_pll[j].rtp_pll)); 2053 } 2054 return 0; 2055 } 2056 2057 return -1; 2058 } 2059 2060 const struct videomode * 2061 radeonfb_modelookup(const char *name) 2062 { 2063 int i; 2064 2065 for (i = 0; i < videomode_count; i++) { 2066 if (!strcmp(name, videomode_list[i].name)) 2067 return &videomode_list[i]; 2068 } 2069 return NULL; 2070 } 2071 2072 void 2073 radeonfb_pllwriteupdate(struct radeonfb_softc *sc, int crtc) 2074 { 2075 if (crtc) { 2076 while (GETPLL(sc, RADEON_P2PLL_REF_DIV) & 2077 RADEON_P2PLL_ATOMIC_UPDATE_R); 2078 SETPLL(sc, RADEON_P2PLL_REF_DIV, RADEON_P2PLL_ATOMIC_UPDATE_W); 2079 } else { 2080 while (GETPLL(sc, RADEON_PPLL_REF_DIV) & 2081 RADEON_PPLL_ATOMIC_UPDATE_R); 2082 SETPLL(sc, RADEON_PPLL_REF_DIV, RADEON_PPLL_ATOMIC_UPDATE_W); 2083 } 2084 } 2085 2086 void 2087 radeonfb_pllwaitatomicread(struct radeonfb_softc *sc, int crtc) 2088 { 2089 int i; 2090 2091 for (i = 10000; i; i--) { 2092 if (crtc) { 2093 if (GETPLL(sc, RADEON_P2PLL_REF_DIV) & 2094 RADEON_P2PLL_ATOMIC_UPDATE_R) 2095 break; 2096 } else { 2097 if (GETPLL(sc, RADEON_PPLL_REF_DIV) & 2098 RADEON_PPLL_ATOMIC_UPDATE_R) 2099 break; 2100 } 2101 } 2102 } 2103 2104 void 2105 radeonfb_program_vclk(struct radeonfb_softc *sc, int dotclock, int crtc, int flags) 2106 { 2107 uint32_t pbit = 0; 2108 uint32_t feed = 0; 2109 uint32_t data, refdiv, div0, r2xxref; 2110 2111 radeonfb_calc_dividers(sc, dotclock, &pbit, &feed, flags); 2112 2113 if (crtc == 0) { 2114 2115 refdiv = GETPLL(sc, RADEON_PPLL_REF_DIV); 2116 2117 /* 2118 * XXX 2119 * the RV350 in my last generation iBook G4 behaves like an 2120 * r2xx here - try to detect that and not screw up the reference 2121 * divider. 2122 * xf86-video-radeon just skips PLL programming altogether 2123 * on iBooks, probably for this reason. 2124 */ 2125 r2xxref = (refdiv & ~RADEON_PPLL_REF_DIV_MASK) | sc->sc_refdiv; 2126 if (IS_R300(sc) && (r2xxref != refdiv)) { 2127 refdiv = (refdiv & ~R300_PPLL_REF_DIV_ACC_MASK) | 2128 (sc->sc_refdiv << R300_PPLL_REF_DIV_ACC_SHIFT); 2129 } else { 2130 refdiv = (refdiv & ~RADEON_PPLL_REF_DIV_MASK) | 2131 sc->sc_refdiv; 2132 } 2133 DPRINTF(("refdiv %08x\n", refdiv)); 2134 div0 = GETPLL(sc, RADEON_PPLL_DIV_0); 2135 DPRINTF(("div0 %08x\n", div0)); 2136 div0 &= ~(RADEON_PPLL_FB3_DIV_MASK | 2137 RADEON_PPLL_POST3_DIV_MASK); 2138 div0 |= pbit; 2139 div0 |= (feed & RADEON_PPLL_FB3_DIV_MASK); 2140 DPRINTF(("div0 %08x\n", div0)); 2141 2142 if ((refdiv == GETPLL(sc, RADEON_PPLL_REF_DIV)) && 2143 (div0 == GETPLL(sc, RADEON_PPLL_DIV_0))) { 2144 /* 2145 * nothing to do here, the PLL is already where we 2146 * want it 2147 */ 2148 PATCH32(sc, RADEON_CLOCK_CNTL_INDEX, 0, 2149 ~RADEON_PLL_DIV_SEL); 2150 aprint_debug_dev(sc->sc_dev, "no need to touch the PLL\n"); 2151 return; 2152 } 2153 2154 /* alright, we do need to reprogram stuff */ 2155 PATCHPLL(sc, RADEON_VCLK_ECP_CNTL, 2156 RADEON_VCLK_SRC_SEL_CPUCLK, 2157 ~RADEON_VCLK_SRC_SEL_MASK); 2158 2159 /* put vclk into reset, use atomic updates */ 2160 SETPLL(sc, RADEON_PPLL_CNTL, 2161 RADEON_PPLL_REFCLK_SEL | 2162 RADEON_PPLL_FBCLK_SEL | 2163 RADEON_PPLL_RESET | 2164 RADEON_PPLL_ATOMIC_UPDATE_EN | 2165 RADEON_PPLL_VGA_ATOMIC_UPDATE_EN); 2166 2167 /* select clock 0 */ 2168 PATCH32(sc, RADEON_CLOCK_CNTL_INDEX, 0, 2169 ~RADEON_PLL_DIV_SEL); 2170 2171 PUTPLL(sc, RADEON_PPLL_REF_DIV, refdiv); 2172 2173 /* xf86-video-radeon does this, not sure why */ 2174 PUTPLL(sc, RADEON_PPLL_DIV_0, div0); 2175 PUTPLL(sc, RADEON_PPLL_DIV_0, div0); 2176 2177 /* use the atomic update */ 2178 radeonfb_pllwriteupdate(sc, crtc); 2179 2180 /* and wait for it to complete */ 2181 radeonfb_pllwaitatomicread(sc, crtc); 2182 2183 /* program HTOTAL (why?) */ 2184 PUTPLL(sc, RADEON_HTOTAL_CNTL, 0); 2185 2186 /* drop reset */ 2187 CLRPLL(sc, RADEON_PPLL_CNTL, 2188 RADEON_PPLL_RESET | RADEON_PPLL_SLEEP | 2189 RADEON_PPLL_ATOMIC_UPDATE_EN | 2190 RADEON_PPLL_VGA_ATOMIC_UPDATE_EN); 2191 2192 PRINTPLL(RADEON_PPLL_CNTL); 2193 PRINTPLL(RADEON_PPLL_REF_DIV); 2194 PRINTPLL(RADEON_PPLL_DIV_3); 2195 2196 /* give clock time to lock */ 2197 delay(50000); 2198 2199 PATCHPLL(sc, RADEON_VCLK_ECP_CNTL, 2200 RADEON_VCLK_SRC_SEL_PPLLCLK, 2201 ~RADEON_VCLK_SRC_SEL_MASK); 2202 2203 } else { 2204 2205 PATCHPLL(sc, RADEON_PIXCLKS_CNTL, 2206 RADEON_PIX2CLK_SRC_SEL_CPUCLK, 2207 ~RADEON_PIX2CLK_SRC_SEL_MASK); 2208 2209 /* put vclk into reset, use atomic updates */ 2210 SETPLL(sc, RADEON_P2PLL_CNTL, 2211 RADEON_P2PLL_RESET | 2212 RADEON_P2PLL_ATOMIC_UPDATE_EN | 2213 RADEON_P2PLL_VGA_ATOMIC_UPDATE_EN); 2214 2215 /* program reference divider */ 2216 PATCHPLL(sc, RADEON_P2PLL_REF_DIV, sc->sc_refdiv, 2217 ~RADEON_P2PLL_REF_DIV_MASK); 2218 2219 /* program feedback and post dividers */ 2220 data = GETPLL(sc, RADEON_P2PLL_DIV_0); 2221 data &= ~(RADEON_P2PLL_FB0_DIV_MASK | 2222 RADEON_P2PLL_POST0_DIV_MASK); 2223 data |= pbit; 2224 data |= (feed & RADEON_P2PLL_FB0_DIV_MASK); 2225 PUTPLL(sc, RADEON_P2PLL_DIV_0, data); 2226 PUTPLL(sc, RADEON_P2PLL_DIV_0, data); 2227 2228 PRINTPLL(RADEON_P2PLL_REF_DIV); 2229 PRINTPLL(RADEON_P2PLL_DIV_0); 2230 2231 /* use the atomic update */ 2232 radeonfb_pllwriteupdate(sc, crtc); 2233 2234 /* and wait for it to complete */ 2235 radeonfb_pllwaitatomicread(sc, crtc); 2236 2237 /* program HTOTAL (why?) */ 2238 PUTPLL(sc, RADEON_HTOTAL2_CNTL, 0); 2239 2240 /* drop reset */ 2241 CLRPLL(sc, RADEON_P2PLL_CNTL, 2242 RADEON_P2PLL_RESET | RADEON_P2PLL_SLEEP | 2243 RADEON_P2PLL_ATOMIC_UPDATE_EN | 2244 RADEON_P2PLL_VGA_ATOMIC_UPDATE_EN); 2245 2246 /* allow time for clock to lock */ 2247 delay(50000); 2248 2249 PATCHPLL(sc, RADEON_PIXCLKS_CNTL, 2250 RADEON_PIX2CLK_SRC_SEL_P2PLLCLK, 2251 ~RADEON_PIX2CLK_SRC_SEL_MASK); 2252 } 2253 PRINTREG(RADEON_CRTC_MORE_CNTL); 2254 } 2255 2256 void 2257 radeonfb_modeswitch(struct radeonfb_display *dp) 2258 { 2259 struct radeonfb_softc *sc = dp->rd_softc; 2260 int i; 2261 2262 /* blank the display while we switch modes */ 2263 radeonfb_blank(dp, 1); 2264 2265 #if 0 2266 SET32(sc, RADEON_CRTC_EXT_CNTL, 2267 RADEON_CRTC_VSYNC_DIS | RADEON_CRTC_HSYNC_DIS | 2268 RADEON_CRTC_DISPLAY_DIS /* | RADEON_CRTC_DISP_REQ_EN_B */); 2269 #endif 2270 2271 /* these registers might get in the way... */ 2272 PUT32(sc, RADEON_OVR_CLR, 0); 2273 PUT32(sc, RADEON_OVR_WID_LEFT_RIGHT, 0); 2274 PUT32(sc, RADEON_OVR_WID_TOP_BOTTOM, 0); 2275 PUT32(sc, RADEON_OV0_SCALE_CNTL, 0); 2276 PUT32(sc, RADEON_SUBPIC_CNTL, 0); 2277 PUT32(sc, RADEON_VIPH_CONTROL, 0); 2278 PUT32(sc, RADEON_I2C_CNTL_1, 0); 2279 PUT32(sc, RADEON_GEN_INT_CNTL, 0); 2280 PUT32(sc, RADEON_CAP0_TRIG_CNTL, 0); 2281 PUT32(sc, RADEON_CAP1_TRIG_CNTL, 0); 2282 /* 2283 * Apple OF hands us R3xx radeons with tiling enabled - explicitly 2284 * disable it here 2285 */ 2286 PUT32(sc, RADEON_SURFACE_CNTL, RADEON_SURF_TRANSLATION_DIS); 2287 2288 for (i = 0; i < dp->rd_ncrtcs; i++) 2289 radeonfb_setcrtc(dp, i); 2290 2291 #if 0 2292 /* 2293 * DVO chip voodoo from xf86-video-radeon 2294 * apparently this is needed for some powerbooks with DVI outputs 2295 */ 2296 2297 uint8_t data[5][2] = {{0x8, 0x030}, {0x9, 0}, {0xa, 0x90}, {0xc, 0x89}, {0x8, 0x3b}}; 2298 int n = 0; 2299 iic_acquire_bus(&sc->sc_i2c[0].ric_controller, 0); 2300 for (i = 0; i < 5; i++) 2301 n += iic_exec(&sc->sc_i2c[0].ric_controller, I2C_OP_WRITE, 0x38, data[i], 2, NULL, 0, 0); 2302 iic_release_bus(&sc->sc_i2c[0].ric_controller, 0); 2303 printf("n = %d\n", n); 2304 #endif 2305 2306 /* activate the display */ 2307 radeonfb_blank(dp, 0); 2308 } 2309 2310 void 2311 radeonfb_setcrtc(struct radeonfb_display *dp, int index) 2312 { 2313 int crtc, flags = 0; 2314 struct videomode *mode; 2315 struct radeonfb_softc *sc; 2316 struct radeonfb_crtc *cp; 2317 uint32_t v; 2318 uint32_t gencntl; 2319 uint32_t htotaldisp; 2320 uint32_t hsyncstrt; 2321 uint32_t vtotaldisp; 2322 uint32_t vsyncstrt; 2323 uint32_t fphsyncstrt; 2324 uint32_t fpvsyncstrt; 2325 uint32_t fphtotaldisp; 2326 uint32_t fpvtotaldisp; 2327 uint32_t pitch; 2328 2329 sc = dp->rd_softc; 2330 2331 if ((sc->sc_ports[index].rp_tmds_type == RADEON_TMDS_INT) || 2332 (sc->sc_ports[index].rp_tmds_type == RADEON_TMDS_EXT)) { 2333 flags |= NO_ODD_FBDIV; 2334 } 2335 2336 cp = &dp->rd_crtcs[index]; 2337 crtc = cp->rc_number; 2338 mode = &cp->rc_videomode; 2339 2340 #if 1 2341 pitch = dp->rd_stride / dp->rd_bpp; 2342 #else 2343 pitch = (((sc->sc_maxx * sc->sc_maxbpp) + ((sc->sc_maxbpp * 8) - 1)) / 2344 (sc->sc_maxbpp * 8)); 2345 #endif 2346 switch (crtc) { 2347 case 0: 2348 gencntl = RADEON_CRTC_GEN_CNTL; 2349 htotaldisp = RADEON_CRTC_H_TOTAL_DISP; 2350 hsyncstrt = RADEON_CRTC_H_SYNC_STRT_WID; 2351 vtotaldisp = RADEON_CRTC_V_TOTAL_DISP; 2352 vsyncstrt = RADEON_CRTC_V_SYNC_STRT_WID; 2353 /* should probably leave those alone on non-LVDS */ 2354 fpvsyncstrt = RADEON_FP_V_SYNC_STRT_WID; 2355 fphsyncstrt = RADEON_FP_H_SYNC_STRT_WID; 2356 fpvtotaldisp = RADEON_FP_CRTC_V_TOTAL_DISP; 2357 fphtotaldisp = RADEON_FP_CRTC_H_TOTAL_DISP; 2358 break; 2359 case 1: 2360 gencntl = RADEON_CRTC2_GEN_CNTL; 2361 htotaldisp = RADEON_CRTC2_H_TOTAL_DISP; 2362 hsyncstrt = RADEON_CRTC2_H_SYNC_STRT_WID; 2363 vtotaldisp = RADEON_CRTC2_V_TOTAL_DISP; 2364 vsyncstrt = RADEON_CRTC2_V_SYNC_STRT_WID; 2365 fpvsyncstrt = RADEON_FP_V2_SYNC_STRT_WID; 2366 fphsyncstrt = RADEON_FP_H2_SYNC_STRT_WID; 2367 /* XXX these registers don't seem to exist */ 2368 fpvtotaldisp = 0;//RADEON_FP_CRTC2_V_TOTAL_DISP; 2369 fphtotaldisp = 0;//RADEON_FP_CRTC2_H_TOTAL_DISP; 2370 break; 2371 default: 2372 panic("Bad CRTC!"); 2373 break; 2374 } 2375 2376 /* 2377 * CRTC_GEN_CNTL - depth, accelerator mode, etc. 2378 */ 2379 /* only bother with 32bpp and 8bpp */ 2380 v = dp->rd_format << RADEON_CRTC_PIX_WIDTH_SHIFT; 2381 2382 if (crtc == 1) { 2383 v |= RADEON_CRTC2_CRT2_ON | RADEON_CRTC2_EN; 2384 } else { 2385 v |= RADEON_CRTC_EXT_DISP_EN | RADEON_CRTC_EN; 2386 } 2387 2388 if (mode->flags & VID_DBLSCAN) 2389 v |= RADEON_CRTC2_DBL_SCAN_EN; 2390 2391 if (mode->flags & VID_INTERLACE) 2392 v |= RADEON_CRTC2_INTERLACE_EN; 2393 2394 if (mode->flags & VID_CSYNC) { 2395 v |= RADEON_CRTC2_CSYNC_EN; 2396 if (crtc == 1) 2397 v |= RADEON_CRTC2_VSYNC_TRISTAT; 2398 } 2399 2400 PUT32(sc, gencntl, v); 2401 DPRINTF(("CRTC%s_GEN_CNTL = %08x\n", crtc ? "2" : "", v)); 2402 2403 /* 2404 * CRTC_EXT_CNTL - preserve disable flags, set ATI linear and EXT_CNT 2405 */ 2406 v = GET32(sc, RADEON_CRTC_EXT_CNTL); 2407 if (crtc == 0) { 2408 v &= (RADEON_CRTC_VSYNC_DIS | RADEON_CRTC_HSYNC_DIS | 2409 RADEON_CRTC_DISPLAY_DIS); 2410 v |= RADEON_XCRT_CNT_EN | RADEON_VGA_ATI_LINEAR; 2411 if (mode->flags & VID_CSYNC) 2412 v |= RADEON_CRTC_VSYNC_TRISTAT; 2413 } 2414 /* unconditional turn on CRT, in case first CRTC is DFP */ 2415 v |= RADEON_CRTC_CRT_ON; 2416 PUT32(sc, RADEON_CRTC_EXT_CNTL, v); 2417 PRINTREG(RADEON_CRTC_EXT_CNTL); 2418 2419 /* 2420 * H_TOTAL_DISP 2421 */ 2422 v = ((mode->hdisplay / 8) - 1) << 16; 2423 v |= (mode->htotal / 8) - 1; 2424 PUT32(sc, htotaldisp, v); 2425 DPRINTF(("CRTC%s_H_TOTAL_DISP = %08x\n", crtc ? "2" : "", v)); 2426 if (fphtotaldisp) { 2427 PUT32(sc, fphtotaldisp, v); 2428 DPRINTF(("FP_H%s_TOTAL_DISP = %08x\n", crtc ? "2" : "", v)); 2429 } 2430 /* 2431 * H_SYNC_STRT_WID 2432 */ 2433 v = (((mode->hsync_end - mode->hsync_start) / 8) << 16); 2434 v |= (mode->hsync_start - 8); /* match xf86-video-radeon */ 2435 if (mode->flags & VID_NHSYNC) 2436 v |= RADEON_CRTC_H_SYNC_POL; 2437 PUT32(sc, hsyncstrt, v); 2438 DPRINTF(("CRTC%s_H_SYNC_STRT_WID = %08x\n", crtc ? "2" : "", v)); 2439 if (fphsyncstrt) { 2440 PUT32(sc, fphsyncstrt, v); 2441 DPRINTF(("FP_H%s_SYNC_STRT_WID = %08x\n", crtc ? "2" : "", v)); 2442 } 2443 2444 /* 2445 * V_TOTAL_DISP 2446 */ 2447 v = ((mode->vdisplay - 1) << 16); 2448 v |= (mode->vtotal - 1); 2449 PUT32(sc, vtotaldisp, v); 2450 DPRINTF(("CRTC%s_V_TOTAL_DISP = %08x\n", crtc ? "2" : "", v)); 2451 if (fpvtotaldisp) { 2452 PUT32(sc, fpvtotaldisp, v); 2453 DPRINTF(("FP_V%s_TOTAL_DISP = %08x\n", crtc ? "2" : "", v)); 2454 } 2455 2456 /* 2457 * V_SYNC_STRT_WID 2458 */ 2459 v = ((mode->vsync_end - mode->vsync_start) << 16); 2460 v |= (mode->vsync_start - 1); 2461 if (mode->flags & VID_NVSYNC) 2462 v |= RADEON_CRTC_V_SYNC_POL; 2463 PUT32(sc, vsyncstrt, v); 2464 DPRINTF(("CRTC%s_V_SYNC_STRT_WID = %08x\n", crtc ? "2" : "", v)); 2465 if (fpvsyncstrt) { 2466 PUT32(sc, fpvsyncstrt, v); 2467 DPRINTF(("FP_V%s_SYNC_STRT_WID = %08x\n", crtc ? "2" : "", v)); 2468 } 2469 2470 radeonfb_program_vclk(sc, mode->dot_clock, crtc, flags); 2471 2472 switch (crtc) { 2473 case 0: 2474 PUT32(sc, RADEON_CRTC_OFFSET, 0); 2475 PUT32(sc, RADEON_CRTC_OFFSET_CNTL, 0); 2476 PUT32(sc, RADEON_CRTC_PITCH, pitch); 2477 CLR32(sc, RADEON_DISP_MERGE_CNTL, RADEON_DISP_RGB_OFFSET_EN); 2478 2479 CLR32(sc, RADEON_CRTC_EXT_CNTL, 2480 RADEON_CRTC_VSYNC_DIS | RADEON_CRTC_HSYNC_DIS | 2481 RADEON_CRTC_DISPLAY_DIS /* | RADEON_CRTC_DISP_REQ_EN_B */); 2482 CLR32(sc, RADEON_CRTC_GEN_CNTL, RADEON_CRTC_DISP_REQ_EN_B); 2483 PRINTREG(RADEON_CRTC_EXT_CNTL); 2484 PRINTREG(RADEON_CRTC_GEN_CNTL); 2485 PRINTREG(RADEON_CLOCK_CNTL_INDEX); 2486 break; 2487 2488 case 1: 2489 PUT32(sc, RADEON_CRTC2_OFFSET, 0); 2490 PUT32(sc, RADEON_CRTC2_OFFSET_CNTL, 0); 2491 PUT32(sc, RADEON_CRTC2_PITCH, pitch); 2492 CLR32(sc, RADEON_DISP2_MERGE_CNTL, RADEON_DISP2_RGB_OFFSET_EN); 2493 CLR32(sc, RADEON_CRTC2_GEN_CNTL, 2494 RADEON_CRTC2_VSYNC_DIS | 2495 RADEON_CRTC2_HSYNC_DIS | 2496 RADEON_CRTC2_DISP_DIS | RADEON_CRTC2_DISP_REQ_EN_B); 2497 PRINTREG(RADEON_CRTC2_GEN_CNTL); 2498 break; 2499 } 2500 } 2501 2502 int 2503 radeonfb_isblank(struct radeonfb_display *dp) 2504 { 2505 uint32_t reg, mask; 2506 2507 if(!dp->rd_softc->sc_mapped) 2508 return 1; 2509 2510 if (dp->rd_crtcs[0].rc_number) { 2511 reg = RADEON_CRTC2_GEN_CNTL; 2512 mask = RADEON_CRTC2_DISP_DIS; 2513 } else { 2514 reg = RADEON_CRTC_EXT_CNTL; 2515 mask = RADEON_CRTC_DISPLAY_DIS; 2516 } 2517 return ((GET32(dp->rd_softc, reg) & mask) ? 1 : 0); 2518 } 2519 2520 void 2521 radeonfb_blank(struct radeonfb_display *dp, int blank) 2522 { 2523 struct radeonfb_softc *sc = dp->rd_softc; 2524 uint32_t reg, mask; 2525 uint32_t fpreg, fpval; 2526 int i; 2527 2528 if (!sc->sc_mapped) 2529 return; 2530 2531 for (i = 0; i < dp->rd_ncrtcs; i++) { 2532 2533 if (dp->rd_crtcs[i].rc_number) { 2534 reg = RADEON_CRTC2_GEN_CNTL; 2535 mask = RADEON_CRTC2_DISP_DIS; 2536 fpreg = RADEON_FP2_GEN_CNTL; 2537 fpval = RADEON_FP2_ON; 2538 } else { 2539 reg = RADEON_CRTC_EXT_CNTL; 2540 mask = RADEON_CRTC_DISPLAY_DIS; 2541 fpreg = RADEON_FP_GEN_CNTL; 2542 fpval = RADEON_FP_FPON; 2543 } 2544 2545 if (blank) { 2546 SET32(sc, reg, mask); 2547 CLR32(sc, fpreg, fpval); 2548 } else { 2549 CLR32(sc, reg, mask); 2550 SET32(sc, fpreg, fpval); 2551 } 2552 } 2553 PRINTREG(RADEON_FP_GEN_CNTL); 2554 PRINTREG(RADEON_FP2_GEN_CNTL); 2555 } 2556 2557 void 2558 radeonfb_init_screen(void *cookie, struct vcons_screen *scr, int existing, 2559 long *defattr) 2560 { 2561 struct radeonfb_display *dp = cookie; 2562 struct rasops_info *ri = &scr->scr_ri; 2563 2564 /* initialize font subsystem */ 2565 wsfont_init(); 2566 2567 scr->scr_flags |= VCONS_LOADFONT; 2568 2569 DPRINTF(("init screen called, existing %d\n", existing)); 2570 2571 ri->ri_depth = dp->rd_bpp; 2572 ri->ri_width = dp->rd_virtx; 2573 ri->ri_height = dp->rd_virty; 2574 ri->ri_stride = dp->rd_stride; 2575 ri->ri_flg = RI_CENTER; 2576 switch (ri->ri_depth) { 2577 case 8: 2578 ri->ri_flg |= RI_ENABLE_ALPHA | RI_8BIT_IS_RGB | RI_PREFER_ALPHA; 2579 break; 2580 case 32: 2581 ri->ri_flg |= RI_ENABLE_ALPHA | RI_PREFER_ALPHA; 2582 /* we run radeons in RGB even on SPARC hardware */ 2583 ri->ri_rnum = 8; 2584 ri->ri_gnum = 8; 2585 ri->ri_bnum = 8; 2586 ri->ri_rpos = 16; 2587 ri->ri_gpos = 8; 2588 ri->ri_bpos = 0; 2589 break; 2590 } 2591 2592 ri->ri_bits = (void *)dp->rd_fbptr; 2593 2594 #ifdef VCONS_DRAW_INTR 2595 scr->scr_flags |= VCONS_DONT_READ; 2596 #endif 2597 2598 if (existing) { 2599 ri->ri_flg |= RI_CLEAR; 2600 2601 /* start a modeswitch now */ 2602 radeonfb_modeswitch(dp); 2603 } 2604 2605 /* 2606 * XXX: font selection should be based on properties, with some 2607 * normal/reasonable default. 2608 */ 2609 2610 /* initialize and look for an initial font */ 2611 rasops_init(ri, 0, 0); 2612 ri->ri_caps = WSSCREEN_UNDERLINE | WSSCREEN_HILIT | 2613 WSSCREEN_WSCOLORS | WSSCREEN_REVERSE | WSSCREEN_RESIZE; 2614 2615 rasops_reconfig(ri, dp->rd_virty / ri->ri_font->fontheight, 2616 dp->rd_virtx / ri->ri_font->fontwidth); 2617 2618 /* enable acceleration */ 2619 dp->rd_putchar = ri->ri_ops.putchar; 2620 ri->ri_ops.copyrows = radeonfb_copyrows; 2621 ri->ri_ops.copycols = radeonfb_copycols; 2622 ri->ri_ops.eraserows = radeonfb_eraserows; 2623 ri->ri_ops.erasecols = radeonfb_erasecols; 2624 /* pick a putchar method based on font and Radeon model */ 2625 if (ri->ri_font->stride < ri->ri_font->fontwidth) { 2626 /* got a bitmap font */ 2627 #ifndef RADEONFB_ALWAYS_ACCEL_PUTCHAR 2628 if (IS_R300(dp->rd_softc)) { 2629 /* 2630 * radeonfb_putchar() doesn't work right on some R3xx 2631 * so we use software drawing here, the wrapper just 2632 * makes sure the engine is idle before scribbling 2633 * into vram 2634 */ 2635 ri->ri_ops.putchar = radeonfb_putchar_wrapper; 2636 } else 2637 #endif 2638 ri->ri_ops.putchar = radeonfb_putchar; 2639 } else { 2640 /* got an alpha font */ 2641 switch(ri->ri_depth) { 2642 case 32: 2643 ri->ri_ops.putchar = radeonfb_putchar_aa32; 2644 break; 2645 case 8: 2646 ri->ri_ops.putchar = radeonfb_putchar_aa8; 2647 break; 2648 default: 2649 /* XXX this should never happen */ 2650 panic("%s: depth is not 8 or 32 but we got an" \ 2651 " alpha font?!", __func__); 2652 } 2653 } 2654 ri->ri_ops.cursor = radeonfb_cursor; 2655 } 2656 2657 void 2658 radeonfb_set_fbloc(struct radeonfb_softc *sc) 2659 { 2660 uint32_t gen, ext, gen2 = 0; 2661 uint32_t agploc, aperbase, apersize, mcfbloc; 2662 2663 gen = GET32(sc, RADEON_CRTC_GEN_CNTL); 2664 /* XXX */ 2665 ext = GET32(sc, RADEON_CRTC_EXT_CNTL) & ~RADEON_CRTC_DISPLAY_DIS; 2666 agploc = GET32(sc, RADEON_MC_AGP_LOCATION); 2667 aperbase = GET32(sc, RADEON_CONFIG_APER_0_BASE); 2668 apersize = GET32(sc, RADEON_CONFIG_APER_SIZE); 2669 2670 PUT32(sc, RADEON_CRTC_GEN_CNTL, gen | RADEON_CRTC_DISP_REQ_EN_B); 2671 PUT32(sc, RADEON_CRTC_EXT_CNTL, ext | RADEON_CRTC_DISPLAY_DIS); 2672 #if 0 2673 PUT32(sc, RADEON_CRTC_GEN_CNTL, gen | RADEON_CRTC_DISPLAY_DIS); 2674 PUT32(sc, RADEON_CRTC_EXT_CNTL, ext | RADEON_CRTC_DISP_REQ_EN_B); 2675 #endif 2676 2677 if (HAS_CRTC2(sc)) { 2678 gen2 = GET32(sc, RADEON_CRTC2_GEN_CNTL); 2679 PUT32(sc, RADEON_CRTC2_GEN_CNTL, 2680 gen2 | RADEON_CRTC2_DISP_REQ_EN_B); 2681 } 2682 2683 delay(100000); 2684 2685 mcfbloc = (aperbase >> 16) | 2686 ((aperbase + (apersize - 1)) & 0xffff0000); 2687 2688 sc->sc_aperbase = (mcfbloc & 0xffff) << 16; 2689 sc->sc_memsz = apersize; 2690 2691 if (((agploc & 0xffff) << 16) != 2692 ((mcfbloc & 0xffff0000U) + 0x10000)) { 2693 agploc = mcfbloc & 0xffff0000U; 2694 agploc |= ((agploc + 0x10000) >> 16); 2695 } 2696 2697 PUT32(sc, RADEON_HOST_PATH_CNTL, 0); 2698 2699 PUT32(sc, RADEON_MC_FB_LOCATION, mcfbloc); 2700 PUT32(sc, RADEON_MC_AGP_LOCATION, agploc); 2701 2702 DPRINTF(("aperbase = %u\n", aperbase)); 2703 PRINTREG(RADEON_MC_FB_LOCATION); 2704 PRINTREG(RADEON_MC_AGP_LOCATION); 2705 2706 PUT32(sc, RADEON_DISPLAY_BASE_ADDR, sc->sc_aperbase); 2707 2708 if (HAS_CRTC2(sc)) 2709 PUT32(sc, RADEON_DISPLAY2_BASE_ADDR, sc->sc_aperbase); 2710 2711 PUT32(sc, RADEON_OV0_BASE_ADDR, sc->sc_aperbase); 2712 2713 #if 0 2714 /* XXX: what is this AGP garbage? :-) */ 2715 PUT32(sc, RADEON_AGP_CNTL, 0x00100000); 2716 #endif 2717 2718 delay(100000); 2719 2720 PUT32(sc, RADEON_CRTC_GEN_CNTL, gen); 2721 PUT32(sc, RADEON_CRTC_EXT_CNTL, ext); 2722 2723 if (HAS_CRTC2(sc)) 2724 PUT32(sc, RADEON_CRTC2_GEN_CNTL, gen2); 2725 } 2726 2727 void 2728 radeonfb_init_misc(struct radeonfb_softc *sc) 2729 { 2730 PUT32(sc, RADEON_BUS_CNTL, 2731 RADEON_BUS_MASTER_DIS | 2732 RADEON_BUS_PREFETCH_MODE_ACT | 2733 RADEON_BUS_PCI_READ_RETRY_EN | 2734 RADEON_BUS_PCI_WRT_RETRY_EN | 2735 (3 << RADEON_BUS_RETRY_WS_SHIFT) | 2736 RADEON_BUS_MSTR_RD_MULT | 2737 RADEON_BUS_MSTR_RD_LINE | 2738 RADEON_BUS_RD_DISCARD_EN | 2739 RADEON_BUS_MSTR_DISCONNECT_EN | 2740 RADEON_BUS_READ_BURST); 2741 2742 PUT32(sc, RADEON_BUS_CNTL1, 0xf0); 2743 /* PUT32(sc, RADEON_SEPROM_CNTL1, 0x09ff0000); */ 2744 PUT32(sc, RADEON_FCP_CNTL, RADEON_FCP0_SRC_GND); 2745 PUT32(sc, RADEON_RBBM_CNTL, 2746 (3 << RADEON_RB_SETTLE_SHIFT) | 2747 (4 << RADEON_ABORTCLKS_HI_SHIFT) | 2748 (4 << RADEON_ABORTCLKS_CP_SHIFT) | 2749 (4 << RADEON_ABORTCLKS_CFIFO_SHIFT)); 2750 2751 /* XXX: figure out what these mean! */ 2752 PUT32(sc, RADEON_AGP_CNTL, 0x00100000); 2753 PUT32(sc, RADEON_HOST_PATH_CNTL, 0); 2754 #if 0 2755 PUT32(sc, RADEON_DISP_MISC_CNTL, 0x5bb00400); 2756 #endif 2757 2758 PUT32(sc, RADEON_GEN_INT_CNTL, 0); 2759 PUT32(sc, RADEON_GEN_INT_STATUS, GET32(sc, RADEON_GEN_INT_STATUS)); 2760 } 2761 2762 static void 2763 radeonfb_putpal(struct radeonfb_display *dp, int idx, int r, int g, int b) 2764 { 2765 struct radeonfb_softc *sc = dp->rd_softc; 2766 int crtc, cc; 2767 uint32_t vclk; 2768 2769 vclk = GETPLL(sc, RADEON_VCLK_ECP_CNTL); 2770 PUTPLL(sc, RADEON_VCLK_ECP_CNTL, vclk & ~RADEON_PIXCLK_DAC_ALWAYS_ONb); 2771 2772 /* initialize the palette for every CRTC used by this display */ 2773 for (cc = 0; cc < dp->rd_ncrtcs; cc++) { 2774 crtc = dp->rd_crtcs[cc].rc_number; 2775 2776 if (crtc) 2777 SET32(sc, RADEON_DAC_CNTL2, RADEON_DAC2_PALETTE_ACC_CTL); 2778 else 2779 CLR32(sc, RADEON_DAC_CNTL2, RADEON_DAC2_PALETTE_ACC_CTL); 2780 2781 PUT32(sc, RADEON_PALETTE_INDEX, idx); 2782 PUT32(sc, RADEON_PALETTE_30_DATA, 2783 (r << 22) | (g << 12) | (b << 2)); 2784 } 2785 2786 PUTPLL(sc, RADEON_VCLK_ECP_CNTL, vclk); 2787 } 2788 2789 /* 2790 * This loads a linear color map for true color. 2791 */ 2792 void 2793 radeonfb_init_palette(struct radeonfb_display *dp) 2794 { 2795 int i; 2796 2797 #define DAC_WIDTH ((1 << 10) - 1) 2798 #define CLUT_WIDTH ((1 << 8) - 1) 2799 #define CLUT_COLOR(i) ((i * DAC_WIDTH * 2 / CLUT_WIDTH + 1) / 2) 2800 2801 if (dp->rd_bpp == 8) { 2802 2803 /* R3G3B2 palette */ 2804 uint32_t tmp, r, g, b; 2805 2806 for (i = 0; i <= CLUT_WIDTH; ++i) { 2807 tmp = i & 0xe0; 2808 2809 /* 2810 * replicate bits so 0xe0 maps to a red value of 0xff 2811 * in order to make white look actually white 2812 */ 2813 tmp |= (tmp >> 3) | (tmp >> 6); 2814 r = tmp; 2815 2816 tmp = (i & 0x1c) << 3; 2817 tmp |= (tmp >> 3) | (tmp >> 6); 2818 g = tmp; 2819 2820 tmp = (i & 0x03) << 6; 2821 tmp |= tmp >> 2; 2822 tmp |= tmp >> 4; 2823 b = tmp; 2824 2825 radeonfb_putpal(dp, i, r, g, b); 2826 } 2827 } else { 2828 /* linear ramp */ 2829 for (i = 0; i <= CLUT_WIDTH; ++i) { 2830 radeonfb_putpal(dp, i, i, i, i); 2831 } 2832 } 2833 } 2834 2835 static int 2836 radeonfb_putcmap(struct radeonfb_display *dp, struct wsdisplay_cmap *cm) 2837 { 2838 u_char *r, *g, *b; 2839 u_int index = cm->index; 2840 u_int count = cm->count; 2841 int i, error; 2842 u_char rbuf[256], gbuf[256], bbuf[256]; 2843 2844 #ifdef GENFB_DEBUG 2845 aprint_debug("putcmap: %d %d\n",index, count); 2846 #endif 2847 if (index >= 256 || count > 256 - index) 2848 return EINVAL; 2849 error = copyin(cm->red, &rbuf[index], count); 2850 if (error) 2851 return error; 2852 error = copyin(cm->green, &gbuf[index], count); 2853 if (error) 2854 return error; 2855 error = copyin(cm->blue, &bbuf[index], count); 2856 if (error) 2857 return error; 2858 2859 memcpy(&dp->rd_cmap_red[index], &rbuf[index], count); 2860 memcpy(&dp->rd_cmap_green[index], &gbuf[index], count); 2861 memcpy(&dp->rd_cmap_blue[index], &bbuf[index], count); 2862 2863 r = &dp->rd_cmap_red[index]; 2864 g = &dp->rd_cmap_green[index]; 2865 b = &dp->rd_cmap_blue[index]; 2866 2867 for (i = 0; i < count; i++) { 2868 radeonfb_putpal(dp, index, *r, *g, *b); 2869 index++; 2870 r++, g++, b++; 2871 } 2872 return 0; 2873 } 2874 2875 static int 2876 radeonfb_getcmap(struct radeonfb_display *dp, struct wsdisplay_cmap *cm) 2877 { 2878 u_int index = cm->index; 2879 u_int count = cm->count; 2880 int error; 2881 2882 if (index >= 256 || count > 256 - index) 2883 return EINVAL; 2884 2885 error = copyout(&dp->rd_cmap_red[index], cm->red, count); 2886 if (error) 2887 return error; 2888 error = copyout(&dp->rd_cmap_green[index], cm->green, count); 2889 if (error) 2890 return error; 2891 error = copyout(&dp->rd_cmap_blue[index], cm->blue, count); 2892 if (error) 2893 return error; 2894 2895 return 0; 2896 } 2897 2898 /* 2899 * Bugs in some R300 hardware requires this when accessing CLOCK_CNTL_INDEX. 2900 */ 2901 void 2902 radeonfb_r300cg_workaround(struct radeonfb_softc *sc) 2903 { 2904 uint32_t tmp, save; 2905 2906 save = GET32(sc, RADEON_CLOCK_CNTL_INDEX); 2907 tmp = save & ~(0x3f | RADEON_PLL_WR_EN); 2908 PUT32(sc, RADEON_CLOCK_CNTL_INDEX, tmp); 2909 tmp = GET32(sc, RADEON_CLOCK_CNTL_DATA); 2910 PUT32(sc, RADEON_CLOCK_CNTL_INDEX, save); 2911 } 2912 2913 /* 2914 * Acceleration entry points. 2915 */ 2916 2917 /* this one draws characters using bitmap fonts */ 2918 static void 2919 radeonfb_putchar(void *cookie, int row, int col, u_int c, long attr) 2920 { 2921 struct rasops_info *ri = cookie; 2922 struct vcons_screen *scr = ri->ri_hw; 2923 struct radeonfb_display *dp = scr->scr_cookie; 2924 struct radeonfb_softc *sc = dp->rd_softc; 2925 struct wsdisplay_font *font = PICK_FONT(ri, c); 2926 uint32_t w, h; 2927 int xd, yd, offset, i; 2928 uint32_t bg, fg, gmc; 2929 uint32_t reg; 2930 uint8_t *data8; 2931 uint16_t *data16; 2932 void *data; 2933 2934 if (dp->rd_wsmode != WSDISPLAYIO_MODE_EMUL) 2935 return; 2936 2937 if (!CHAR_IN_FONT(c, font)) 2938 return; 2939 2940 w = font->fontwidth; 2941 h = font->fontheight; 2942 2943 bg = ri->ri_devcmap[(attr >> 16) & 0xf]; 2944 fg = ri->ri_devcmap[(attr >> 24) & 0xf]; 2945 2946 xd = ri->ri_xorigin + col * w; 2947 yd = ri->ri_yorigin + row * h; 2948 2949 if (c == 0x20) { 2950 radeonfb_rectfill(dp, xd, yd, w, h, bg); 2951 return; 2952 } 2953 data = WSFONT_GLYPH(c, font); 2954 2955 gmc = dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT; 2956 2957 radeonfb_wait_fifo(sc, 9); 2958 2959 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 2960 RADEON_GMC_BRUSH_NONE | 2961 RADEON_GMC_SRC_DATATYPE_MONO_FG_BG | 2962 RADEON_GMC_DST_CLIPPING | 2963 RADEON_ROP3_S | 2964 RADEON_DP_SRC_SOURCE_HOST_DATA | 2965 RADEON_GMC_CLR_CMP_CNTL_DIS | 2966 RADEON_GMC_WR_MSK_DIS | 2967 gmc); 2968 2969 PUT32(sc, RADEON_SC_LEFT, xd); 2970 PUT32(sc, RADEON_SC_RIGHT, xd + w); 2971 PUT32(sc, RADEON_DP_SRC_FRGD_CLR, fg); 2972 PUT32(sc, RADEON_DP_SRC_BKGD_CLR, bg); 2973 PUT32(sc, RADEON_DP_CNTL, 2974 RADEON_DST_X_LEFT_TO_RIGHT | 2975 RADEON_DST_Y_TOP_TO_BOTTOM); 2976 2977 PUT32(sc, RADEON_SRC_X_Y, 0); 2978 offset = 32 - (font->stride << 3); 2979 PUT32(sc, RADEON_DST_X_Y, ((xd - offset) << 16) | yd); 2980 PUT32(sc, RADEON_DST_WIDTH_HEIGHT, (32 << 16) | h); 2981 2982 radeonfb_wait_fifo(sc, h); 2983 switch (font->stride) { 2984 case 1: { 2985 data8 = data; 2986 for (i = 0; i < h; i++) { 2987 reg = *data8; 2988 #if BYTE_ORDER == LITTLE_ENDIAN 2989 reg = reg << 24; 2990 #endif 2991 bus_space_write_stream_4(sc->sc_regt, 2992 sc->sc_regh, RADEON_HOST_DATA0, reg); 2993 data8++; 2994 } 2995 break; 2996 } 2997 case 2: { 2998 data16 = data; 2999 for (i = 0; i < h; i++) { 3000 reg = *data16; 3001 #if BYTE_ORDER == LITTLE_ENDIAN 3002 reg = reg << 16; 3003 #endif 3004 bus_space_write_stream_4(sc->sc_regt, 3005 sc->sc_regh, RADEON_HOST_DATA0, reg); 3006 data16++; 3007 } 3008 break; 3009 } 3010 } 3011 if (attr & 1) 3012 radeonfb_rectfill(dp, xd, yd + h - 2, w, 1, fg); 3013 } 3014 3015 /* ... while this one is for anti-aliased ones */ 3016 static void 3017 radeonfb_putchar_aa32(void *cookie, int row, int col, u_int c, long attr) 3018 { 3019 struct rasops_info *ri = cookie; 3020 struct vcons_screen *scr = ri->ri_hw; 3021 struct radeonfb_display *dp = scr->scr_cookie; 3022 struct radeonfb_softc *sc = dp->rd_softc; 3023 struct wsdisplay_font *font = PICK_FONT(ri, c); 3024 uint32_t bg, fg, gmc; 3025 uint8_t *data; 3026 int w, h, xd, yd; 3027 int i, r, g, b, aval; 3028 int rf, gf, bf, rb, gb, bb; 3029 uint32_t pixel; 3030 int rv; 3031 3032 if (dp->rd_wsmode != WSDISPLAYIO_MODE_EMUL) 3033 return; 3034 3035 if (!CHAR_IN_FONT(c, font)) 3036 return; 3037 3038 w = font->fontwidth; 3039 h = font->fontheight; 3040 3041 bg = ri->ri_devcmap[(attr >> 16) & 0xf]; 3042 fg = ri->ri_devcmap[(attr >> 24) & 0xf]; 3043 3044 xd = ri->ri_xorigin + col * w; 3045 yd = ri->ri_yorigin + row * h; 3046 3047 if (c == 0x20) { 3048 radeonfb_rectfill(dp, xd, yd, w, h, bg); 3049 if (attr & 1) 3050 radeonfb_rectfill(dp, xd, yd + h - 2, w, 1, fg); 3051 return; 3052 } 3053 rv = glyphcache_try(&dp->rd_gc, c, xd, yd, attr); 3054 if (rv == GC_OK) 3055 return; 3056 3057 data = WSFONT_GLYPH(c, font); 3058 3059 gmc = dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT; 3060 3061 radeonfb_wait_fifo(sc, 5); 3062 3063 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 3064 RADEON_GMC_BRUSH_NONE | 3065 RADEON_GMC_SRC_DATATYPE_COLOR | 3066 RADEON_ROP3_S | 3067 RADEON_DP_SRC_SOURCE_HOST_DATA | 3068 RADEON_GMC_CLR_CMP_CNTL_DIS | 3069 RADEON_GMC_WR_MSK_DIS | 3070 gmc); 3071 3072 PUT32(sc, RADEON_DP_CNTL, 3073 RADEON_DST_X_LEFT_TO_RIGHT | 3074 RADEON_DST_Y_TOP_TO_BOTTOM); 3075 3076 PUT32(sc, RADEON_SRC_X_Y, 0); 3077 PUT32(sc, RADEON_DST_X_Y, (xd << 16) | yd); 3078 PUT32(sc, RADEON_DST_WIDTH_HEIGHT, (w << 16) | h); 3079 3080 rf = (fg >> 16) & 0xff; 3081 rb = (bg >> 16) & 0xff; 3082 gf = (fg >> 8) & 0xff; 3083 gb = (bg >> 8) & 0xff; 3084 bf = fg & 0xff; 3085 bb = bg & 0xff; 3086 3087 /* 3088 * I doubt we can upload data faster than even the slowest Radeon 3089 * could process them, especially when doing the alpha blending stuff 3090 * along the way, so just make sure there's some room in the FIFO and 3091 * then hammer away 3092 * As it turns out we can, so make periodic stops to let the FIFO 3093 * drain. 3094 */ 3095 radeonfb_wait_fifo(sc, 20); 3096 for (i = 0; i < ri->ri_fontscale; i++) { 3097 aval = *data; 3098 data++; 3099 if (aval == 0) { 3100 pixel = bg; 3101 } else if (aval == 255) { 3102 pixel = fg; 3103 } else { 3104 r = aval * rf + (255 - aval) * rb; 3105 g = aval * gf + (255 - aval) * gb; 3106 b = aval * bf + (255 - aval) * bb; 3107 pixel = (r & 0xff00) << 8 | 3108 (g & 0xff00) | 3109 (b & 0xff00) >> 8; 3110 } 3111 if (i & 16) 3112 radeonfb_wait_fifo(sc, 20); 3113 PUT32(sc, RADEON_HOST_DATA0, pixel); 3114 } 3115 if (rv == GC_ADD) { 3116 glyphcache_add(&dp->rd_gc, c, xd, yd); 3117 } else if (attr & 1) 3118 radeonfb_rectfill(dp, xd, yd + h - 2, w, 1, fg); 3119 } 3120 3121 static void 3122 radeonfb_putchar_aa8(void *cookie, int row, int col, u_int c, long attr) 3123 { 3124 struct rasops_info *ri = cookie; 3125 struct vcons_screen *scr = ri->ri_hw; 3126 struct radeonfb_display *dp = scr->scr_cookie; 3127 struct radeonfb_softc *sc = dp->rd_softc; 3128 struct wsdisplay_font *font = PICK_FONT(ri, c); 3129 uint32_t bg, fg, latch = 0, bg8, fg8, pixel, gmc; 3130 int i, x, y, wi, he, r, g, b, aval; 3131 int r1, g1, b1, r0, g0, b0, fgo, bgo; 3132 uint8_t *data8; 3133 int rv, cnt; 3134 3135 if (dp->rd_wsmode != WSDISPLAYIO_MODE_EMUL) 3136 return; 3137 3138 if (!CHAR_IN_FONT(c, font)) 3139 return; 3140 3141 wi = font->fontwidth; 3142 he = font->fontheight; 3143 3144 bg = ri->ri_devcmap[(attr >> 16) & 0xf]; 3145 fg = ri->ri_devcmap[(attr >> 24) & 0xf]; 3146 3147 x = ri->ri_xorigin + col * wi; 3148 y = ri->ri_yorigin + row * he; 3149 3150 if (c == 0x20) { 3151 radeonfb_rectfill(dp, x, y, wi, he, bg); 3152 if (attr & 1) 3153 radeonfb_rectfill(dp, x, y + he - 2, wi, 1, fg); 3154 return; 3155 } 3156 rv = glyphcache_try(&dp->rd_gc, c, x, y, attr); 3157 if (rv == GC_OK) 3158 return; 3159 3160 data8 = WSFONT_GLYPH(c, font); 3161 3162 gmc = dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT; 3163 3164 radeonfb_wait_fifo(sc, 5); 3165 3166 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 3167 RADEON_GMC_BRUSH_NONE | 3168 RADEON_GMC_SRC_DATATYPE_COLOR | 3169 RADEON_ROP3_S | 3170 RADEON_DP_SRC_SOURCE_HOST_DATA | 3171 RADEON_GMC_CLR_CMP_CNTL_DIS | 3172 RADEON_GMC_WR_MSK_DIS | 3173 gmc); 3174 3175 PUT32(sc, RADEON_DP_CNTL, 3176 RADEON_DST_X_LEFT_TO_RIGHT | 3177 RADEON_DST_Y_TOP_TO_BOTTOM); 3178 3179 PUT32(sc, RADEON_SRC_X_Y, 0); 3180 PUT32(sc, RADEON_DST_X_Y, (x << 16) | y); 3181 PUT32(sc, RADEON_DST_WIDTH_HEIGHT, (wi << 16) | he); 3182 3183 /* 3184 * we need the RGB colours here, so get offsets into rasops_cmap 3185 */ 3186 fgo = ((attr >> 24) & 0xf) * 3; 3187 bgo = ((attr >> 16) & 0xf) * 3; 3188 3189 r0 = rasops_cmap[bgo]; 3190 r1 = rasops_cmap[fgo]; 3191 g0 = rasops_cmap[bgo + 1]; 3192 g1 = rasops_cmap[fgo + 1]; 3193 b0 = rasops_cmap[bgo + 2]; 3194 b1 = rasops_cmap[fgo + 2]; 3195 #define R3G3B2(r, g, b) ((r & 0xe0) | ((g >> 3) & 0x1c) | (b >> 6)) 3196 bg8 = R3G3B2(r0, g0, b0); 3197 fg8 = R3G3B2(r1, g1, b1); 3198 3199 radeonfb_wait_fifo(sc, 20); 3200 cnt = 0; 3201 for (i = 0; i < ri->ri_fontscale; i++) { 3202 aval = *data8; 3203 if (aval == 0) { 3204 pixel = bg8; 3205 } else if (aval == 255) { 3206 pixel = fg8; 3207 } else { 3208 r = aval * r1 + (255 - aval) * r0; 3209 g = aval * g1 + (255 - aval) * g0; 3210 b = aval * b1 + (255 - aval) * b0; 3211 pixel = ((r & 0xe000) >> 8) | 3212 ((g & 0xe000) >> 11) | 3213 ((b & 0xc000) >> 14); 3214 } 3215 latch |= pixel << (8 * (i & 3)); 3216 /* write in 32bit chunks */ 3217 if ((i & 3) == 3) { 3218 PUT32(sc, RADEON_HOST_DATA0, latch); 3219 /* 3220 * not strictly necessary, old data should be shifted 3221 * out 3222 */ 3223 latch = 0; 3224 cnt++; 3225 if (cnt > 16) { 3226 cnt = 0; 3227 radeonfb_wait_fifo(sc, 20); 3228 } 3229 } 3230 data8++; 3231 } 3232 /* if we have pixels left in latch write them out */ 3233 if ((i & 3) != 0) { 3234 /* 3235 * radeon is weird - apparently leftover pixels are written 3236 * from the middle, not from the left as everything else 3237 */ 3238 PUT32(sc, RADEON_HOST_DATA0, latch); 3239 } 3240 3241 if (rv == GC_ADD) { 3242 glyphcache_add(&dp->rd_gc, c, x, y); 3243 } else 3244 if (attr & 1) 3245 radeonfb_rectfill(dp, x, y + he - 2, wi, 1, fg); 3246 } 3247 3248 /* 3249 * wrapper for software character drawing 3250 * just sync the engine and call rasops*_putchar() 3251 */ 3252 3253 #ifndef RADEONFB_ALWAYS_ACCEL_PUTCHAR 3254 static void 3255 radeonfb_putchar_wrapper(void *cookie, int row, int col, u_int c, long attr) 3256 { 3257 struct rasops_info *ri = cookie; 3258 struct vcons_screen *scr = ri->ri_hw; 3259 struct radeonfb_display *dp = scr->scr_cookie; 3260 3261 radeonfb_engine_idle(dp->rd_softc); 3262 dp->rd_putchar(ri, row, col, c, attr); 3263 } 3264 #endif 3265 3266 static void 3267 radeonfb_eraserows(void *cookie, int row, int nrows, long fillattr) 3268 { 3269 struct rasops_info *ri = cookie; 3270 struct vcons_screen *scr = ri->ri_hw; 3271 struct radeonfb_display *dp = scr->scr_cookie; 3272 uint32_t x, y, w, h, fg, bg, ul; 3273 3274 /* XXX: check for full emulation mode? */ 3275 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 3276 x = ri->ri_xorigin; 3277 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 3278 w = ri->ri_emuwidth; 3279 h = ri->ri_font->fontheight * nrows; 3280 3281 rasops_unpack_attr(fillattr, &fg, &bg, &ul); 3282 radeonfb_rectfill(dp, x, y, w, h, ri->ri_devcmap[bg & 0xf]); 3283 } 3284 } 3285 3286 static void 3287 radeonfb_copyrows(void *cookie, int srcrow, int dstrow, int nrows) 3288 { 3289 struct rasops_info *ri = cookie; 3290 struct vcons_screen *scr = ri->ri_hw; 3291 struct radeonfb_display *dp = scr->scr_cookie; 3292 uint32_t x, ys, yd, w, h; 3293 3294 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 3295 x = ri->ri_xorigin; 3296 ys = ri->ri_yorigin + ri->ri_font->fontheight * srcrow; 3297 yd = ri->ri_yorigin + ri->ri_font->fontheight * dstrow; 3298 w = ri->ri_emuwidth; 3299 h = ri->ri_font->fontheight * nrows; 3300 radeonfb_bitblt(dp, x, ys, x, yd, w, h, 3301 RADEON_ROP3_S); 3302 } 3303 } 3304 3305 static void 3306 radeonfb_copycols(void *cookie, int row, int srccol, int dstcol, int ncols) 3307 { 3308 struct rasops_info *ri = cookie; 3309 struct vcons_screen *scr = ri->ri_hw; 3310 struct radeonfb_display *dp = scr->scr_cookie; 3311 uint32_t xs, xd, y, w, h; 3312 3313 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 3314 xs = ri->ri_xorigin + ri->ri_font->fontwidth * srccol; 3315 xd = ri->ri_xorigin + ri->ri_font->fontwidth * dstcol; 3316 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 3317 w = ri->ri_font->fontwidth * ncols; 3318 h = ri->ri_font->fontheight; 3319 radeonfb_bitblt(dp, xs, y, xd, y, w, h, 3320 RADEON_ROP3_S); 3321 } 3322 } 3323 3324 static void 3325 radeonfb_erasecols(void *cookie, int row, int startcol, int ncols, 3326 long fillattr) 3327 { 3328 struct rasops_info *ri = cookie; 3329 struct vcons_screen *scr = ri->ri_hw; 3330 struct radeonfb_display *dp = scr->scr_cookie; 3331 uint32_t x, y, w, h, fg, bg, ul; 3332 3333 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 3334 x = ri->ri_xorigin + ri->ri_font->fontwidth * startcol; 3335 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 3336 w = ri->ri_font->fontwidth * ncols; 3337 h = ri->ri_font->fontheight; 3338 3339 rasops_unpack_attr(fillattr, &fg, &bg, &ul); 3340 radeonfb_rectfill(dp, x, y, w, h, ri->ri_devcmap[bg & 0xf]); 3341 } 3342 } 3343 3344 static void 3345 radeonfb_cursor(void *cookie, int on, int row, int col) 3346 { 3347 struct rasops_info *ri = cookie; 3348 struct vcons_screen *scr = ri->ri_hw; 3349 struct radeonfb_display *dp = scr->scr_cookie; 3350 int x, y, wi, he; 3351 3352 wi = ri->ri_font->fontwidth; 3353 he = ri->ri_font->fontheight; 3354 3355 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 3356 x = ri->ri_ccol * wi + ri->ri_xorigin; 3357 y = ri->ri_crow * he + ri->ri_yorigin; 3358 /* first turn off the old cursor */ 3359 if (ri->ri_flg & RI_CURSOR) { 3360 radeonfb_bitblt(dp, x, y, x, y, wi, he, 3361 RADEON_ROP3_Dn); 3362 ri->ri_flg &= ~RI_CURSOR; 3363 } 3364 ri->ri_crow = row; 3365 ri->ri_ccol = col; 3366 /* then (possibly) turn on the new one */ 3367 if (on) { 3368 x = ri->ri_ccol * wi + ri->ri_xorigin; 3369 y = ri->ri_crow * he + ri->ri_yorigin; 3370 radeonfb_bitblt(dp, x, y, x, y, wi, he, 3371 RADEON_ROP3_Dn); 3372 ri->ri_flg |= RI_CURSOR; 3373 } 3374 } else { 3375 scr->scr_ri.ri_crow = row; 3376 scr->scr_ri.ri_ccol = col; 3377 scr->scr_ri.ri_flg &= ~RI_CURSOR; 3378 } 3379 } 3380 3381 /* 3382 * Underlying acceleration support. 3383 */ 3384 3385 static void 3386 radeonfb_rectfill(struct radeonfb_display *dp, int dstx, int dsty, 3387 int width, int height, uint32_t color) 3388 { 3389 struct radeonfb_softc *sc = dp->rd_softc; 3390 uint32_t gmc; 3391 3392 gmc = dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT; 3393 3394 radeonfb_wait_fifo(sc, 6); 3395 3396 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 3397 RADEON_GMC_BRUSH_SOLID_COLOR | 3398 RADEON_GMC_SRC_DATATYPE_COLOR | 3399 RADEON_GMC_CLR_CMP_CNTL_DIS | 3400 RADEON_ROP3_P | gmc); 3401 3402 PUT32(sc, RADEON_DP_BRUSH_FRGD_CLR, color); 3403 PUT32(sc, RADEON_DP_WRITE_MASK, 0xffffffff); 3404 PUT32(sc, RADEON_DP_CNTL, 3405 RADEON_DST_X_LEFT_TO_RIGHT | 3406 RADEON_DST_Y_TOP_TO_BOTTOM); 3407 PUT32(sc, RADEON_DST_Y_X, (dsty << 16) | dstx); 3408 PUT32(sc, RADEON_DST_WIDTH_HEIGHT, (width << 16) | (height)); 3409 } 3410 3411 static void 3412 radeonfb_rectfill_a(void *cookie, int dstx, int dsty, 3413 int width, int height, long attr) 3414 { 3415 struct radeonfb_display *dp = cookie; 3416 3417 radeonfb_rectfill(dp, dstx, dsty, width, height, 3418 dp->rd_vscreen.scr_ri.ri_devcmap[(attr >> 24 & 0xf)]); 3419 } 3420 3421 static void 3422 radeonfb_bitblt(void *cookie, int srcx, int srcy, 3423 int dstx, int dsty, int width, int height, int rop) 3424 { 3425 struct radeonfb_display *dp = cookie; 3426 struct radeonfb_softc *sc = dp->rd_softc; 3427 uint32_t gmc; 3428 uint32_t dir; 3429 3430 if (dsty < srcy) { 3431 dir = RADEON_DST_Y_TOP_TO_BOTTOM; 3432 } else { 3433 srcy += height - 1; 3434 dsty += height - 1; 3435 dir = 0; 3436 } 3437 if (dstx < srcx) { 3438 dir |= RADEON_DST_X_LEFT_TO_RIGHT; 3439 } else { 3440 srcx += width - 1; 3441 dstx += width - 1; 3442 } 3443 3444 gmc = dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT; 3445 3446 radeonfb_wait_fifo(sc, 6); 3447 3448 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 3449 RADEON_GMC_BRUSH_SOLID_COLOR | 3450 RADEON_GMC_SRC_DATATYPE_COLOR | 3451 RADEON_GMC_CLR_CMP_CNTL_DIS | 3452 RADEON_DP_SRC_SOURCE_MEMORY | 3453 rop | gmc); 3454 3455 PUT32(sc, RADEON_DP_WRITE_MASK, 0xffffffff); 3456 PUT32(sc, RADEON_DP_CNTL, dir); 3457 PUT32(sc, RADEON_SRC_Y_X, (srcy << 16) | srcx); 3458 PUT32(sc, RADEON_DST_Y_X, (dsty << 16) | dstx); 3459 PUT32(sc, RADEON_DST_WIDTH_HEIGHT, (width << 16) | (height)); 3460 } 3461 3462 static void 3463 radeonfb_engine_idle(struct radeonfb_softc *sc) 3464 { 3465 3466 radeonfb_wait_fifo(sc, 64); 3467 while ((GET32(sc, RADEON_RBBM_STATUS) & 3468 RADEON_RBBM_ACTIVE) != 0); 3469 radeonfb_engine_flush(sc); 3470 } 3471 3472 static inline void 3473 radeonfb_wait_fifo(struct radeonfb_softc *sc, int n) 3474 { 3475 int i; 3476 3477 for (i = RADEON_TIMEOUT; i; i--) { 3478 if ((GET32(sc, RADEON_RBBM_STATUS) & 3479 RADEON_RBBM_FIFOCNT_MASK) >= n) 3480 return; 3481 } 3482 #ifdef DIAGNOSTIC 3483 if (!i) 3484 printf("%s: timed out waiting for fifo (%x)\n", 3485 XNAME(sc), GET32(sc, RADEON_RBBM_STATUS)); 3486 #endif 3487 } 3488 3489 static void 3490 radeonfb_engine_flush(struct radeonfb_softc *sc) 3491 { 3492 int i = 0; 3493 3494 if (IS_R300(sc)) { 3495 SET32(sc, R300_DSTCACHE_CTLSTAT, R300_RB2D_DC_FLUSH_ALL); 3496 while (GET32(sc, R300_DSTCACHE_CTLSTAT) & R300_RB2D_DC_BUSY) { 3497 i++; 3498 } 3499 } else { 3500 SET32(sc, RADEON_RB2D_DSTCACHE_CTLSTAT, 3501 RADEON_RB2D_DC_FLUSH_ALL); 3502 while (GET32(sc, RADEON_RB2D_DSTCACHE_CTLSTAT) & 3503 RADEON_RB2D_DC_BUSY) { 3504 i++; 3505 } 3506 } 3507 #ifdef DIAGNOSTIC 3508 if (i > RADEON_TIMEOUT) 3509 printf("%s: engine flush timed out!\n", XNAME(sc)); 3510 #endif 3511 } 3512 3513 static inline void 3514 radeonfb_unclip(struct radeonfb_softc *sc) 3515 { 3516 3517 radeonfb_wait_fifo(sc, 2); 3518 PUT32(sc, RADEON_SC_TOP_LEFT, 0); 3519 PUT32(sc, RADEON_SC_BOTTOM_RIGHT, 0x1fff1fff); 3520 } 3521 3522 static void 3523 radeonfb_engine_init(struct radeonfb_display *dp) 3524 { 3525 struct radeonfb_softc *sc = dp->rd_softc; 3526 uint32_t pitch; 3527 3528 /* no 3D */ 3529 PUT32(sc, RADEON_RB3D_CNTL, 0); 3530 3531 radeonfb_engine_reset(sc); 3532 pitch = ((dp->rd_virtx * (dp->rd_bpp / 8) + 0x3f)) >> 6; 3533 3534 radeonfb_wait_fifo(sc, 1); 3535 if (!IS_R300(sc)) 3536 PUT32(sc, RADEON_RB2D_DSTCACHE_MODE, 0); 3537 3538 radeonfb_wait_fifo(sc, 3); 3539 PUT32(sc, RADEON_DEFAULT_PITCH_OFFSET, 3540 (pitch << 22) | (sc->sc_aperbase >> 10)); 3541 3542 3543 PUT32(sc, RADEON_DST_PITCH_OFFSET, 3544 (pitch << 22) | (sc->sc_aperbase >> 10)); 3545 PUT32(sc, RADEON_SRC_PITCH_OFFSET, 3546 (pitch << 22) | (sc->sc_aperbase >> 10)); 3547 3548 (void)GET32(sc, RADEON_DP_DATATYPE); 3549 3550 /* default scissors -- no clipping */ 3551 radeonfb_wait_fifo(sc, 1); 3552 PUT32(sc, RADEON_DEFAULT_SC_BOTTOM_RIGHT, 3553 RADEON_DEFAULT_SC_RIGHT_MAX | RADEON_DEFAULT_SC_BOTTOM_MAX); 3554 3555 radeonfb_wait_fifo(sc, 1); 3556 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 3557 (dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT) | 3558 RADEON_GMC_CLR_CMP_CNTL_DIS | 3559 RADEON_GMC_BRUSH_SOLID_COLOR | 3560 RADEON_GMC_SRC_DATATYPE_COLOR); 3561 3562 radeonfb_wait_fifo(sc, 10); 3563 PUT32(sc, RADEON_DST_LINE_START, 0); 3564 PUT32(sc, RADEON_DST_LINE_END, 0); 3565 PUT32(sc, RADEON_DP_BRUSH_FRGD_CLR, 0xffffffff); 3566 PUT32(sc, RADEON_DP_BRUSH_BKGD_CLR, 0); 3567 PUT32(sc, RADEON_DP_SRC_FRGD_CLR, 0xffffffff); 3568 PUT32(sc, RADEON_DP_SRC_BKGD_CLR, 0); 3569 PUT32(sc, RADEON_DP_WRITE_MASK, 0xffffffff); 3570 PUT32(sc, RADEON_SC_TOP_LEFT, 0); 3571 PUT32(sc, RADEON_SC_BOTTOM_RIGHT, 0x1fff1fff); 3572 PUT32(sc, RADEON_AUX_SC_CNTL, 0); 3573 radeonfb_engine_idle(sc); 3574 } 3575 3576 static void 3577 radeonfb_engine_reset(struct radeonfb_softc *sc) 3578 { 3579 uint32_t hpc, rbbm, mclkcntl, clkindex; 3580 3581 radeonfb_engine_flush(sc); 3582 3583 clkindex = GET32(sc, RADEON_CLOCK_CNTL_INDEX); 3584 if (HAS_R300CG(sc)) 3585 radeonfb_r300cg_workaround(sc); 3586 mclkcntl = GETPLL(sc, RADEON_MCLK_CNTL); 3587 3588 /* 3589 * According to comments in XFree code, resetting the HDP via 3590 * the RBBM_SOFT_RESET can cause bad behavior on some systems. 3591 * So we use HOST_PATH_CNTL instead. 3592 */ 3593 3594 hpc = GET32(sc, RADEON_HOST_PATH_CNTL); 3595 rbbm = GET32(sc, RADEON_RBBM_SOFT_RESET); 3596 if (IS_R300(sc)) { 3597 PUT32(sc, RADEON_RBBM_SOFT_RESET, rbbm | 3598 RADEON_SOFT_RESET_CP | 3599 RADEON_SOFT_RESET_HI | 3600 RADEON_SOFT_RESET_E2); 3601 GET32(sc, RADEON_RBBM_SOFT_RESET); 3602 PUT32(sc, RADEON_RBBM_SOFT_RESET, 0); 3603 /* 3604 * XXX: this bit is not defined in any ATI docs I have, 3605 * nor in the XFree code, but XFree does it. Why? 3606 */ 3607 SET32(sc, RADEON_RB2D_DSTCACHE_MODE, (1<<17)); 3608 } else { 3609 PUT32(sc, RADEON_RBBM_SOFT_RESET, rbbm | 3610 RADEON_SOFT_RESET_CP | 3611 RADEON_SOFT_RESET_SE | 3612 RADEON_SOFT_RESET_RE | 3613 RADEON_SOFT_RESET_PP | 3614 RADEON_SOFT_RESET_E2 | 3615 RADEON_SOFT_RESET_RB); 3616 GET32(sc, RADEON_RBBM_SOFT_RESET); 3617 PUT32(sc, RADEON_RBBM_SOFT_RESET, rbbm & 3618 ~(RADEON_SOFT_RESET_CP | 3619 RADEON_SOFT_RESET_SE | 3620 RADEON_SOFT_RESET_RE | 3621 RADEON_SOFT_RESET_PP | 3622 RADEON_SOFT_RESET_E2 | 3623 RADEON_SOFT_RESET_RB)); 3624 GET32(sc, RADEON_RBBM_SOFT_RESET); 3625 } 3626 3627 PUT32(sc, RADEON_HOST_PATH_CNTL, hpc | RADEON_HDP_SOFT_RESET); 3628 GET32(sc, RADEON_HOST_PATH_CNTL); 3629 PUT32(sc, RADEON_HOST_PATH_CNTL, hpc); 3630 3631 if (IS_R300(sc)) 3632 PUT32(sc, RADEON_RBBM_SOFT_RESET, rbbm); 3633 3634 PUT32(sc, RADEON_CLOCK_CNTL_INDEX, clkindex); 3635 PRINTREG(RADEON_CLOCK_CNTL_INDEX); 3636 PUTPLL(sc, RADEON_MCLK_CNTL, mclkcntl); 3637 3638 if (HAS_R300CG(sc)) 3639 radeonfb_r300cg_workaround(sc); 3640 } 3641 3642 static int 3643 radeonfb_set_curpos(struct radeonfb_display *dp, struct wsdisplay_curpos *pos) 3644 { 3645 int x, y; 3646 3647 x = pos->x; 3648 y = pos->y; 3649 3650 /* 3651 * This doesn't let a cursor move off the screen. I'm not 3652 * sure if this will have negative effects for e.g. Xinerama. 3653 * I'd guess Xinerama handles it by changing the cursor shape, 3654 * but that needs verification. 3655 */ 3656 if (x >= dp->rd_virtx) 3657 x = dp->rd_virtx - 1; 3658 if (x < 0) 3659 x = 0; 3660 if (y >= dp->rd_virty) 3661 y = dp->rd_virty - 1; 3662 if (y < 0) 3663 y = 0; 3664 3665 dp->rd_cursor.rc_pos.x = x; 3666 dp->rd_cursor.rc_pos.y = y; 3667 3668 radeonfb_cursor_position(dp); 3669 return 0; 3670 } 3671 3672 static int 3673 radeonfb_set_cursor(struct radeonfb_display *dp, struct wsdisplay_cursor *wc) 3674 { 3675 unsigned flags; 3676 3677 uint8_t r[2], g[2], b[2]; 3678 unsigned index, count; 3679 int i, err; 3680 int pitch, size; 3681 struct radeonfb_cursor nc; 3682 3683 flags = wc->which; 3684 3685 /* copy old values */ 3686 nc = dp->rd_cursor; 3687 3688 if (flags & WSDISPLAY_CURSOR_DOCMAP) { 3689 index = wc->cmap.index; 3690 count = wc->cmap.count; 3691 3692 if (index >= 2 || count > 2 - index) 3693 return EINVAL; 3694 3695 err = copyin(wc->cmap.red, &r[index], count); 3696 if (err) 3697 return err; 3698 err = copyin(wc->cmap.green, &g[index], count); 3699 if (err) 3700 return err; 3701 err = copyin(wc->cmap.blue, &b[index], count); 3702 if (err) 3703 return err; 3704 3705 for (i = index; i < index + count; i++) { 3706 nc.rc_cmap[i] = 3707 (r[i] << 16) + (g[i] << 8) + (b[i] << 0); 3708 } 3709 } 3710 3711 if (flags & WSDISPLAY_CURSOR_DOSHAPE) { 3712 if ((wc->size.x > RADEON_CURSORMAXX) || 3713 (wc->size.y > RADEON_CURSORMAXY)) 3714 return EINVAL; 3715 3716 /* figure bytes per line */ 3717 pitch = (wc->size.x + 7) / 8; 3718 size = pitch * wc->size.y; 3719 3720 /* clear the old cursor and mask */ 3721 memset(nc.rc_image, 0, 512); 3722 memset(nc.rc_mask, 0, 512); 3723 3724 nc.rc_size = wc->size; 3725 3726 if ((err = copyin(wc->image, nc.rc_image, size)) != 0) 3727 return err; 3728 3729 if ((err = copyin(wc->mask, nc.rc_mask, size)) != 0) 3730 return err; 3731 } 3732 3733 if (flags & WSDISPLAY_CURSOR_DOHOT) { 3734 nc.rc_hot = wc->hot; 3735 if (nc.rc_hot.x >= nc.rc_size.x) 3736 nc.rc_hot.x = nc.rc_size.x - 1; 3737 if (nc.rc_hot.y >= nc.rc_size.y) 3738 nc.rc_hot.y = nc.rc_size.y - 1; 3739 } 3740 3741 if (flags & WSDISPLAY_CURSOR_DOPOS) { 3742 nc.rc_pos = wc->pos; 3743 if (nc.rc_pos.x >= dp->rd_virtx) 3744 nc.rc_pos.x = dp->rd_virtx - 1; 3745 #if 0 3746 if (nc.rc_pos.x < 0) 3747 nc.rc_pos.x = 0; 3748 #endif 3749 if (nc.rc_pos.y >= dp->rd_virty) 3750 nc.rc_pos.y = dp->rd_virty - 1; 3751 #if 0 3752 if (nc.rc_pos.y < 0) 3753 nc.rc_pos.y = 0; 3754 #endif 3755 } 3756 if (flags & WSDISPLAY_CURSOR_DOCUR) { 3757 nc.rc_visible = wc->enable; 3758 } 3759 3760 dp->rd_cursor = nc; 3761 radeonfb_cursor_update(dp, wc->which); 3762 3763 return 0; 3764 } 3765 3766 static uint8_t 3767 radeonfb_backwards(uint8_t d) 3768 { 3769 uint8_t l; 3770 3771 l = d << 7; 3772 l |= ((d & 0x02) << 5); 3773 l |= ((d & 0x04) << 3); 3774 l |= ((d & 0x08) << 1); 3775 l |= ((d & 0x10) >> 1); 3776 l |= ((d & 0x20) >> 3); 3777 l |= ((d & 0x40) >> 5); 3778 l |= ((d & 0x80) >> 7); 3779 return l; 3780 } 3781 3782 /* 3783 * Change the cursor shape. Call this with the cursor locked to avoid 3784 * flickering/tearing. 3785 */ 3786 static void 3787 radeonfb_cursor_shape(struct radeonfb_display *dp) 3788 { 3789 uint8_t and[512], xor[512]; 3790 int i, j, src, dst /* , pitch */; 3791 const uint8_t *msk = dp->rd_cursor.rc_mask; 3792 const uint8_t *img = dp->rd_cursor.rc_image; 3793 3794 /* 3795 * Radeon cursor data interleaves one line of AND data followed 3796 * by a line of XOR data. (Each line corresponds to a whole hardware 3797 * pitch - i.e. 64 pixels or 8 bytes.) 3798 * 3799 * The cursor is displayed using the following table: 3800 * 3801 * AND XOR Result 3802 * ---------------------- 3803 * 0 0 Cursor color 0 3804 * 0 1 Cursor color 1 3805 * 1 0 Transparent 3806 * 1 1 Complement of background 3807 * 3808 * Our masks are therefore different from what we were passed. 3809 * Passed in, I'm assuming the data represents either color 0 or 1, 3810 * and a mask, so the passed in table looks like: 3811 * 3812 * IMG Mask Result 3813 * ----------------------- 3814 * 0 0 Transparent 3815 * 0 1 Cursor color 0 3816 * 1 0 Transparent 3817 * 1 1 Cursor color 1 3818 * 3819 * IF mask bit == 1, AND = 0, XOR = color. 3820 * IF mask bit == 0, AND = 1, XOR = 0. 3821 * 3822 * hence: AND = ~(mask); XOR = color & ~(mask); 3823 */ 3824 3825 /* pitch = ((dp->rd_cursor.rc_size.x + 7) / 8); */ 3826 3827 /* start by assuming all bits are transparent */ 3828 memset(and, 0xff, 512); 3829 memset(xor, 0x00, 512); 3830 3831 src = 0; 3832 dst = 0; 3833 for (i = 0; i < 64; i++) { 3834 for (j = 0; j < 64; j += 8) { 3835 if ((i < dp->rd_cursor.rc_size.y) && 3836 (j < dp->rd_cursor.rc_size.x)) { 3837 3838 /* take care to leave odd bits alone */ 3839 and[dst] &= ~(msk[src]); 3840 xor[dst] = img[src] & msk[src]; 3841 src++; 3842 } 3843 dst++; 3844 } 3845 } 3846 3847 for (i = 0; i < 512; i++) { 3848 and[i] = radeonfb_backwards(and[i]); 3849 xor[i] = radeonfb_backwards(xor[i]); 3850 } 3851 3852 /* copy the image into place */ 3853 for (i = 0; i < 64; i++) { 3854 memcpy((uint8_t *)dp->rd_curptr + (i * 16), 3855 &and[i * 8], 8); 3856 memcpy((uint8_t *)dp->rd_curptr + (i * 16) + 8, 3857 &xor[i * 8], 8); 3858 } 3859 } 3860 3861 static void 3862 radeonfb_cursor_position(struct radeonfb_display *dp) 3863 { 3864 struct radeonfb_softc *sc = dp->rd_softc; 3865 uint32_t offset, hvoff, hvpos; /* registers */ 3866 uint32_t coff; /* cursor offset */ 3867 int i, x, y, xoff, yoff, crtcoff; 3868 3869 /* 3870 * XXX: this also needs to handle pan/scan 3871 */ 3872 for (i = 0; i < dp->rd_ncrtcs; i++) { 3873 3874 struct radeonfb_crtc *rcp = &dp->rd_crtcs[i]; 3875 3876 if (rcp->rc_number) { 3877 offset = RADEON_CUR2_OFFSET; 3878 hvoff = RADEON_CUR2_HORZ_VERT_OFF; 3879 hvpos = RADEON_CUR2_HORZ_VERT_POSN; 3880 crtcoff = RADEON_CRTC2_OFFSET; 3881 } else { 3882 offset = RADEON_CUR_OFFSET; 3883 hvoff = RADEON_CUR_HORZ_VERT_OFF; 3884 hvpos = RADEON_CUR_HORZ_VERT_POSN; 3885 crtcoff = RADEON_CRTC_OFFSET; 3886 } 3887 3888 x = dp->rd_cursor.rc_pos.x; 3889 y = dp->rd_cursor.rc_pos.y; 3890 3891 while (y < rcp->rc_yoffset) { 3892 rcp->rc_yoffset -= RADEON_PANINCREMENT; 3893 } 3894 while (y >= (rcp->rc_yoffset + rcp->rc_videomode.vdisplay)) { 3895 rcp->rc_yoffset += RADEON_PANINCREMENT; 3896 } 3897 while (x < rcp->rc_xoffset) { 3898 rcp->rc_xoffset -= RADEON_PANINCREMENT; 3899 } 3900 while (x >= (rcp->rc_xoffset + rcp->rc_videomode.hdisplay)) { 3901 rcp->rc_xoffset += RADEON_PANINCREMENT; 3902 } 3903 3904 /* adjust for the cursor's hotspot */ 3905 x -= dp->rd_cursor.rc_hot.x; 3906 y -= dp->rd_cursor.rc_hot.y; 3907 xoff = yoff = 0; 3908 3909 if (x >= dp->rd_virtx) 3910 x = dp->rd_virtx - 1; 3911 if (y >= dp->rd_virty) 3912 y = dp->rd_virty - 1; 3913 3914 /* now adjust cursor so it is relative to viewport */ 3915 x -= rcp->rc_xoffset; 3916 y -= rcp->rc_yoffset; 3917 3918 /* 3919 * no need to check for fall off, because we should 3920 * never move off the screen entirely! 3921 */ 3922 coff = 0; 3923 if (x < 0) { 3924 xoff = -x; 3925 x = 0; 3926 } 3927 if (y < 0) { 3928 yoff = -y; 3929 y = 0; 3930 coff = (yoff * 2) * 8; 3931 } 3932 3933 /* pan the display */ 3934 PUT32(sc, crtcoff, (rcp->rc_yoffset * dp->rd_stride) + 3935 rcp->rc_xoffset); 3936 3937 PUT32(sc, offset, (dp->rd_curoff + coff) | RADEON_CUR_LOCK); 3938 PUT32(sc, hvoff, (xoff << 16) | (yoff) | RADEON_CUR_LOCK); 3939 /* NB: this unlocks the cursor */ 3940 PUT32(sc, hvpos, (x << 16) | y); 3941 } 3942 } 3943 3944 static void 3945 radeonfb_cursor_visible(struct radeonfb_display *dp) 3946 { 3947 int i; 3948 uint32_t gencntl, bit; 3949 3950 for (i = 0; i < dp->rd_ncrtcs; i++) { 3951 if (dp->rd_crtcs[i].rc_number) { 3952 gencntl = RADEON_CRTC2_GEN_CNTL; 3953 bit = RADEON_CRTC2_CUR_EN; 3954 } else { 3955 gencntl = RADEON_CRTC_GEN_CNTL; 3956 bit = RADEON_CRTC_CUR_EN; 3957 } 3958 3959 if (dp->rd_cursor.rc_visible) 3960 SET32(dp->rd_softc, gencntl, bit); 3961 else 3962 CLR32(dp->rd_softc, gencntl, bit); 3963 } 3964 } 3965 3966 static void 3967 radeonfb_cursor_cmap(struct radeonfb_display *dp) 3968 { 3969 int i; 3970 uint32_t c0reg, c1reg; 3971 struct radeonfb_softc *sc = dp->rd_softc; 3972 3973 for (i = 0; i < dp->rd_ncrtcs; i++) { 3974 if (dp->rd_crtcs[i].rc_number) { 3975 c0reg = RADEON_CUR2_CLR0; 3976 c1reg = RADEON_CUR2_CLR1; 3977 } else { 3978 c0reg = RADEON_CUR_CLR0; 3979 c1reg = RADEON_CUR_CLR1; 3980 } 3981 3982 PUT32(sc, c0reg, dp->rd_cursor.rc_cmap[0]); 3983 PUT32(sc, c1reg, dp->rd_cursor.rc_cmap[1]); 3984 } 3985 } 3986 3987 static void 3988 radeonfb_cursor_update(struct radeonfb_display *dp, unsigned which) 3989 { 3990 struct radeonfb_softc *sc; 3991 int i; 3992 3993 sc = dp->rd_softc; 3994 for (i = 0; i < dp->rd_ncrtcs; i++) { 3995 if (dp->rd_crtcs[i].rc_number) { 3996 SET32(sc, RADEON_CUR2_OFFSET, RADEON_CUR_LOCK); 3997 } else { 3998 SET32(sc, RADEON_CUR_OFFSET,RADEON_CUR_LOCK); 3999 } 4000 } 4001 4002 if (which & WSDISPLAY_CURSOR_DOCMAP) 4003 radeonfb_cursor_cmap(dp); 4004 4005 if (which & WSDISPLAY_CURSOR_DOSHAPE) 4006 radeonfb_cursor_shape(dp); 4007 4008 if (which & WSDISPLAY_CURSOR_DOCUR) 4009 radeonfb_cursor_visible(dp); 4010 4011 /* this one is unconditional, because it updates other stuff */ 4012 radeonfb_cursor_position(dp); 4013 } 4014 4015 static struct videomode * 4016 radeonfb_best_refresh(struct videomode *m1, struct videomode *m2) 4017 { 4018 int r1, r2; 4019 4020 /* otherwise pick the higher refresh rate */ 4021 r1 = DIVIDE(DIVIDE(m1->dot_clock, m1->htotal), m1->vtotal); 4022 r2 = DIVIDE(DIVIDE(m2->dot_clock, m2->htotal), m2->vtotal); 4023 4024 return (r1 < r2 ? m2 : m1); 4025 } 4026 4027 static const struct videomode * 4028 radeonfb_port_mode(struct radeonfb_softc *sc, struct radeonfb_port *rp, 4029 int x, int y) 4030 { 4031 struct edid_info *ep = &rp->rp_edid; 4032 struct videomode *vmp = NULL; 4033 int i; 4034 4035 if (!rp->rp_edid_valid) { 4036 /* fallback to safe mode */ 4037 return radeonfb_modelookup(sc->sc_defaultmode); 4038 } 4039 4040 /* always choose the preferred mode first! */ 4041 if (ep->edid_preferred_mode) { 4042 4043 /* XXX: add auto-stretching support for native mode */ 4044 4045 /* this may want panning to occur, btw */ 4046 if ((ep->edid_preferred_mode->hdisplay <= x) && 4047 (ep->edid_preferred_mode->vdisplay <= y)) 4048 return ep->edid_preferred_mode; 4049 } 4050 4051 for (i = 0; i < ep->edid_nmodes; i++) { 4052 /* 4053 * We elect to pick a resolution that is too large for 4054 * the monitor than one that is too small. This means 4055 * that we will prefer to pan rather than to try to 4056 * center a smaller display on a larger screen. In 4057 * practice, this shouldn't matter because if a 4058 * monitor can support a larger resolution, it can 4059 * probably also support the smaller. A specific 4060 * exception is fixed format panels, but hopefully 4061 * they are properly dealt with by the "autostretch" 4062 * logic above. 4063 */ 4064 if ((ep->edid_modes[i].hdisplay > x) || 4065 (ep->edid_modes[i].vdisplay > y)) { 4066 continue; 4067 } 4068 4069 /* 4070 * at this point, the display mode is no larger than 4071 * what we've requested. 4072 */ 4073 if (vmp == NULL) 4074 vmp = &ep->edid_modes[i]; 4075 4076 /* eliminate smaller modes */ 4077 if ((vmp->hdisplay >= ep->edid_modes[i].hdisplay) || 4078 (vmp->vdisplay >= ep->edid_modes[i].vdisplay)) 4079 continue; 4080 4081 if ((vmp->hdisplay < ep->edid_modes[i].hdisplay) || 4082 (vmp->vdisplay < ep->edid_modes[i].vdisplay)) { 4083 vmp = &ep->edid_modes[i]; 4084 continue; 4085 } 4086 4087 KASSERT(vmp->hdisplay == ep->edid_modes[i].hdisplay); 4088 KASSERT(vmp->vdisplay == ep->edid_modes[i].vdisplay); 4089 4090 vmp = radeonfb_best_refresh(vmp, &ep->edid_modes[i]); 4091 } 4092 4093 return (vmp ? vmp : radeonfb_modelookup(sc->sc_defaultmode)); 4094 } 4095 4096 static int 4097 radeonfb_hasres(struct videomode *list, int nlist, int x, int y) 4098 { 4099 int i; 4100 4101 for (i = 0; i < nlist; i++) { 4102 if ((x == list[i].hdisplay) && 4103 (y == list[i].vdisplay)) { 4104 return 1; 4105 } 4106 } 4107 return 0; 4108 } 4109 4110 static void 4111 radeonfb_pickres(struct radeonfb_display *dp, uint16_t *x, uint16_t *y, 4112 int pan) 4113 { 4114 struct radeonfb_port *rp; 4115 struct edid_info *ep; 4116 int i, j; 4117 4118 *x = 0; 4119 *y = 0; 4120 4121 if (pan) { 4122 for (i = 0; i < dp->rd_ncrtcs; i++) { 4123 rp = dp->rd_crtcs[i].rc_port; 4124 ep = &rp->rp_edid; 4125 if (!rp->rp_edid_valid) { 4126 /* monitor not present */ 4127 continue; 4128 } 4129 4130 /* 4131 * For now we are ignoring "conflict" that 4132 * could occur when mixing some modes like 4133 * 1280x1024 and 1400x800. It isn't clear 4134 * which is better, so the first one wins. 4135 */ 4136 for (j = 0; j < ep->edid_nmodes; j++) { 4137 /* 4138 * ignore resolutions that are too big for 4139 * the radeon 4140 */ 4141 if (ep->edid_modes[j].hdisplay > 4142 dp->rd_softc->sc_maxx) 4143 continue; 4144 if (ep->edid_modes[j].vdisplay > 4145 dp->rd_softc->sc_maxy) 4146 continue; 4147 4148 /* 4149 * pick largest resolution, the 4150 * smaller monitor will pan 4151 */ 4152 if ((ep->edid_modes[j].hdisplay >= *x) && 4153 (ep->edid_modes[j].vdisplay >= *y)) { 4154 *x = ep->edid_modes[j].hdisplay; 4155 *y = ep->edid_modes[j].vdisplay; 4156 } 4157 } 4158 } 4159 4160 } else { 4161 struct videomode modes[64]; 4162 int nmodes = 0; 4163 int valid = 0; 4164 4165 for (i = 0; i < dp->rd_ncrtcs; i++) { 4166 /* 4167 * pick the largest resolution in common. 4168 */ 4169 rp = dp->rd_crtcs[i].rc_port; 4170 ep = &rp->rp_edid; 4171 4172 if (!rp->rp_edid_valid) 4173 continue; 4174 4175 if (!valid) { 4176 /* 4177 * Pick the preferred mode for this port 4178 * if available. 4179 */ 4180 if (ep->edid_preferred_mode) { 4181 struct videomode *vmp = 4182 ep->edid_preferred_mode; 4183 4184 if ((vmp->hdisplay <= 4185 dp->rd_softc->sc_maxx) && 4186 (vmp->vdisplay <= 4187 dp->rd_softc->sc_maxy)) 4188 modes[nmodes++] = *vmp; 4189 } else { 4190 4191 /* initialize starting list */ 4192 for (j = 0; j < ep->edid_nmodes; j++) { 4193 /* 4194 * ignore resolutions that are 4195 * too big for the radeon 4196 */ 4197 if (ep->edid_modes[j].hdisplay > 4198 dp->rd_softc->sc_maxx) 4199 continue; 4200 if (ep->edid_modes[j].vdisplay > 4201 dp->rd_softc->sc_maxy) 4202 continue; 4203 4204 modes[nmodes] = 4205 ep->edid_modes[j]; 4206 nmodes++; 4207 } 4208 } 4209 valid = 1; 4210 } else { 4211 /* merge into preexisting list */ 4212 for (j = 0; j < nmodes; j++) { 4213 if (!radeonfb_hasres(ep->edid_modes, 4214 ep->edid_nmodes, 4215 modes[j].hdisplay, 4216 modes[j].vdisplay)) { 4217 modes[j] = modes[nmodes]; 4218 j--; 4219 nmodes--; 4220 } 4221 } 4222 } 4223 } 4224 4225 /* now we have to pick from the merged list */ 4226 for (i = 0; i < nmodes; i++) { 4227 if ((modes[i].hdisplay >= *x) && 4228 (modes[i].vdisplay >= *y)) { 4229 *x = modes[i].hdisplay; 4230 *y = modes[i].vdisplay; 4231 } 4232 } 4233 } 4234 4235 if ((*x == 0) || (*y == 0)) { 4236 /* fallback to safe mode */ 4237 *x = 640; 4238 *y = 480; 4239 } 4240 } 4241 4242 /* 4243 * backlight levels are linear on: 4244 * - RV200, RV250, RV280, RV350 4245 * - but NOT on PowerBook4,3 6,3 6,5 4246 * according to Linux' radeonfb 4247 */ 4248 4249 /* Get the current backlight level for the display. */ 4250 4251 static int 4252 radeonfb_get_backlight(struct radeonfb_display *dp) 4253 { 4254 int s; 4255 uint32_t level; 4256 4257 s = spltty(); 4258 4259 level = radeonfb_get32(dp->rd_softc, RADEON_LVDS_GEN_CNTL); 4260 level &= RADEON_LVDS_BL_MOD_LEV_MASK; 4261 level >>= RADEON_LVDS_BL_MOD_LEV_SHIFT; 4262 4263 /* 4264 * On some chips, we should negate the backlight level. 4265 * XXX Find out on which chips. 4266 */ 4267 if (dp->rd_softc->sc_flags & RFB_INV_BLIGHT) 4268 level = RADEONFB_BACKLIGHT_MAX - level; 4269 4270 splx(s); 4271 4272 return level; 4273 } 4274 4275 /* Set the backlight to the given level for the display. */ 4276 static void 4277 radeonfb_switch_backlight(struct radeonfb_display *dp, int on) 4278 { 4279 if (dp->rd_bl_on == on) 4280 return; 4281 dp->rd_bl_on = on; 4282 radeonfb_set_backlight(dp, dp->rd_bl_level); 4283 } 4284 4285 static int 4286 radeonfb_set_backlight(struct radeonfb_display *dp, int level) 4287 { 4288 struct radeonfb_softc *sc = dp->rd_softc; 4289 int rlevel, s; 4290 uint32_t lvds; 4291 4292 if(!sc->sc_mapped) 4293 return 0; 4294 4295 s = spltty(); 4296 4297 dp->rd_bl_level = level; 4298 if (dp->rd_bl_on == 0) 4299 level = 0; 4300 4301 if (level < 0) 4302 level = 0; 4303 else if (level >= RADEONFB_BACKLIGHT_MAX) 4304 level = RADEONFB_BACKLIGHT_MAX; 4305 4306 /* On some chips, we should negate the backlight level. */ 4307 if (dp->rd_softc->sc_flags & RFB_INV_BLIGHT) { 4308 rlevel = RADEONFB_BACKLIGHT_MAX - level; 4309 } else 4310 rlevel = level; 4311 4312 callout_stop(&dp->rd_bl_lvds_co); 4313 radeonfb_engine_idle(sc); 4314 4315 /* 4316 * Turn off the display if the backlight is set to 0, since the 4317 * display is useless without backlight anyway. 4318 */ 4319 if (level == 0) 4320 radeonfb_blank(dp, 1); 4321 else if (radeonfb_get_backlight(dp) == 0) 4322 radeonfb_blank(dp, 0); 4323 4324 lvds = radeonfb_get32(sc, RADEON_LVDS_GEN_CNTL); 4325 lvds &= ~RADEON_LVDS_DISPLAY_DIS; 4326 if (!(lvds & RADEON_LVDS_BLON) || !(lvds & RADEON_LVDS_ON)) { 4327 lvds |= dp->rd_bl_lvds_val & RADEON_LVDS_DIGON; 4328 lvds |= RADEON_LVDS_BLON | RADEON_LVDS_EN; 4329 radeonfb_put32(sc, RADEON_LVDS_GEN_CNTL, lvds); 4330 lvds &= ~RADEON_LVDS_BL_MOD_LEV_MASK; 4331 lvds |= rlevel << RADEON_LVDS_BL_MOD_LEV_SHIFT; 4332 lvds |= RADEON_LVDS_ON; 4333 lvds |= dp->rd_bl_lvds_val & RADEON_LVDS_BL_MOD_EN; 4334 } else { 4335 lvds &= ~RADEON_LVDS_BL_MOD_LEV_MASK; 4336 lvds |= rlevel << RADEON_LVDS_BL_MOD_LEV_SHIFT; 4337 radeonfb_put32(sc, RADEON_LVDS_GEN_CNTL, lvds); 4338 } 4339 4340 dp->rd_bl_lvds_val &= ~RADEON_LVDS_STATE_MASK; 4341 dp->rd_bl_lvds_val |= lvds & RADEON_LVDS_STATE_MASK; 4342 /* XXX What is the correct delay? */ 4343 callout_schedule(&dp->rd_bl_lvds_co, 200 * hz); 4344 4345 splx(s); 4346 4347 return 0; 4348 } 4349 4350 /* 4351 * Callout function for delayed operations on the LVDS_GEN_CNTL register. 4352 * Set the delayed bits in the register, and clear the stored delayed 4353 * value. 4354 */ 4355 4356 static void radeonfb_lvds_callout(void *arg) 4357 { 4358 struct radeonfb_display *dp = arg; 4359 int s; 4360 4361 s = splhigh(); 4362 4363 radeonfb_mask32(dp->rd_softc, RADEON_LVDS_GEN_CNTL, ~0, 4364 dp->rd_bl_lvds_val); 4365 dp->rd_bl_lvds_val = 0; 4366 4367 splx(s); 4368 } 4369 4370 static void 4371 radeonfb_brightness_up(device_t dev) 4372 { 4373 struct radeonfb_softc *sc = device_private(dev); 4374 struct radeonfb_display *dp = &sc->sc_displays[0]; 4375 int level; 4376 4377 /* we assume the main display is the first one - need a better way */ 4378 if (sc->sc_ndisplays < 1) return; 4379 /* make sure pushing the hotkeys always has an effect */ 4380 dp->rd_bl_on = 1; 4381 level = dp->rd_bl_level; 4382 level = uimin(RADEONFB_BACKLIGHT_MAX, level + 5); 4383 radeonfb_set_backlight(dp, level); 4384 } 4385 4386 static void 4387 radeonfb_brightness_down(device_t dev) 4388 { 4389 struct radeonfb_softc *sc = device_private(dev); 4390 struct radeonfb_display *dp = &sc->sc_displays[0]; 4391 int level; 4392 4393 /* we assume the main display is the first one - need a better way */ 4394 if (sc->sc_ndisplays < 1) return; 4395 /* make sure pushing the hotkeys always has an effect */ 4396 dp->rd_bl_on = 1; 4397 level = dp->rd_bl_level; 4398 level = uimax(0, level - 5); 4399 radeonfb_set_backlight(dp, level); 4400 } 4401
Indexes created Wed Sep 24 02:09:48 GMT 2025