radeonfb.c revision 1.105
1 /* $NetBSD: radeonfb.c,v 1.105 2019/08/15 00:50:11 rin Exp $ */ 2 3 /*- 4 * Copyright (c) 2006 Itronix Inc. 5 * All rights reserved. 6 * 7 * Written by Garrett D'Amore for Itronix Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. The name of Itronix Inc. may not be used to endorse 18 * or promote products derived from this software without specific 19 * prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY ITRONIX INC. ``AS IS'' AND ANY EXPRESS 22 * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 23 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL ITRONIX INC. BE LIABLE FOR ANY 25 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE 27 * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 29 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 30 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 31 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * ATI Technologies Inc. ("ATI") has not assisted in the creation of, and 36 * does not endorse, this software. ATI will not be responsible or liable 37 * for any actual or alleged damage or loss caused by or in connection with 38 * the use of or reliance on this software. 39 */ 40 41 /* 42 * Portions of this code were taken from XFree86's Radeon driver, which bears 43 * this notice: 44 * 45 * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and 46 * VA Linux Systems Inc., Fremont, California. 47 * 48 * All Rights Reserved. 49 * 50 * Permission is hereby granted, free of charge, to any person obtaining 51 * a copy of this software and associated documentation files (the 52 * "Software"), to deal in the Software without restriction, including 53 * without limitation on the rights to use, copy, modify, merge, 54 * publish, distribute, sublicense, and/or sell copies of the Software, 55 * and to permit persons to whom the Software is furnished to do so, 56 * subject to the following conditions: 57 * 58 * The above copyright notice and this permission notice (including the 59 * next paragraph) shall be included in all copies or substantial 60 * portions of the Software. 61 * 62 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 63 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 64 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 65 * NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR 66 * THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 67 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 68 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 69 * DEALINGS IN THE SOFTWARE. 70 */ 71 72 #include <sys/cdefs.h> 73 __KERNEL_RCSID(0, "$NetBSD: radeonfb.c,v 1.105 2019/08/15 00:50:11 rin Exp $"); 74 75 #include <sys/param.h> 76 #include <sys/systm.h> 77 #include <sys/device.h> 78 #include <sys/malloc.h> 79 #include <sys/bus.h> 80 #include <sys/kernel.h> 81 #include <sys/lwp.h> 82 #include <sys/kauth.h> 83 84 #include <dev/wscons/wsdisplayvar.h> 85 #include <dev/wscons/wsconsio.h> 86 #include <dev/wsfont/wsfont.h> 87 #include <dev/rasops/rasops.h> 88 #include <dev/videomode/videomode.h> 89 #include <dev/videomode/edidvar.h> 90 #include <dev/wscons/wsdisplay_vconsvar.h> 91 #include <dev/pci/wsdisplay_pci.h> 92 #include <dev/wscons/wsdisplay_glyphcachevar.h> 93 94 #include <dev/pci/pcidevs.h> 95 #include <dev/pci/pcireg.h> 96 #include <dev/pci/pcivar.h> 97 #include <dev/pci/pciio.h> 98 #include <dev/pci/radeonfbreg.h> 99 #include <dev/pci/radeonfbvar.h> 100 #include "opt_radeonfb.h" 101 #include "opt_vcons.h" 102 103 #ifdef RADEONFB_DEPTH_32 104 #define RADEONFB_DEFAULT_DEPTH 32 105 #else 106 #define RADEONFB_DEFAULT_DEPTH 8 107 #endif 108 109 static int radeonfb_match(device_t, cfdata_t, void *); 110 static void radeonfb_attach(device_t, device_t, void *); 111 static int radeonfb_ioctl(void *, void *, unsigned long, void *, int, 112 struct lwp *); 113 static paddr_t radeonfb_mmap(void *, void *, off_t, int); 114 static int radeonfb_scratch_test(struct radeonfb_softc *, int, uint32_t); 115 static void radeonfb_loadbios(struct radeonfb_softc *, 116 const struct pci_attach_args *); 117 118 static uintmax_t radeonfb_getprop_num(struct radeonfb_softc *, const char *, 119 uintmax_t); 120 static int radeonfb_getclocks(struct radeonfb_softc *); 121 static int radeonfb_gettmds(struct radeonfb_softc *); 122 static int radeonfb_calc_dividers(struct radeonfb_softc *, uint32_t, 123 uint32_t *, uint32_t *, int); 124 /* flags for radeonfb_calc_dividers */ 125 #define NO_ODD_FBDIV 1 126 127 static int radeonfb_getconnectors(struct radeonfb_softc *); 128 static const struct videomode *radeonfb_modelookup(const char *); 129 static void radeonfb_init_screen(void *, struct vcons_screen *, int, long *); 130 static void radeonfb_pllwriteupdate(struct radeonfb_softc *, int); 131 static void radeonfb_pllwaitatomicread(struct radeonfb_softc *, int); 132 static void radeonfb_program_vclk(struct radeonfb_softc *, int, int, int); 133 static void radeonfb_modeswitch(struct radeonfb_display *); 134 static void radeonfb_setcrtc(struct radeonfb_display *, int); 135 static void radeonfb_init_misc(struct radeonfb_softc *); 136 static void radeonfb_set_fbloc(struct radeonfb_softc *); 137 static void radeonfb_init_palette(struct radeonfb_display *); 138 static void radeonfb_r300cg_workaround(struct radeonfb_softc *); 139 140 static int radeonfb_isblank(struct radeonfb_display *); 141 static void radeonfb_blank(struct radeonfb_display *, int); 142 static int radeonfb_set_cursor(struct radeonfb_display *, 143 struct wsdisplay_cursor *); 144 static int radeonfb_set_curpos(struct radeonfb_display *, 145 struct wsdisplay_curpos *); 146 static void radeonfb_putpal(struct radeonfb_display *, int, int, int, int); 147 static int radeonfb_putcmap(struct radeonfb_display *, struct wsdisplay_cmap *); 148 static int radeonfb_getcmap(struct radeonfb_display *, struct wsdisplay_cmap *); 149 150 /* acceleration support */ 151 static void radeonfb_rectfill(struct radeonfb_display *, int dstx, int dsty, 152 int width, int height, uint32_t color); 153 static void radeonfb_rectfill_a(void *, int, int, int, int, long); 154 static void radeonfb_bitblt(void *, int srcx, int srcy, 155 int dstx, int dsty, int width, int height, int rop); 156 157 /* hw cursor support */ 158 static void radeonfb_cursor_cmap(struct radeonfb_display *); 159 static void radeonfb_cursor_shape(struct radeonfb_display *); 160 static void radeonfb_cursor_position(struct radeonfb_display *); 161 static void radeonfb_cursor_visible(struct radeonfb_display *); 162 static void radeonfb_cursor_update(struct radeonfb_display *, unsigned); 163 164 static inline void radeonfb_wait_fifo(struct radeonfb_softc *, int); 165 static void radeonfb_engine_idle(struct radeonfb_softc *); 166 static void radeonfb_engine_flush(struct radeonfb_softc *); 167 static void radeonfb_engine_reset(struct radeonfb_softc *); 168 static void radeonfb_engine_init(struct radeonfb_display *); 169 static inline void radeonfb_unclip(struct radeonfb_softc *) __unused; 170 171 static void radeonfb_eraserows(void *, int, int, long); 172 static void radeonfb_erasecols(void *, int, int, int, long); 173 static void radeonfb_copyrows(void *, int, int, int); 174 static void radeonfb_copycols(void *, int, int, int, int); 175 static void radeonfb_cursor(void *, int, int, int); 176 static void radeonfb_putchar(void *, int, int, unsigned, long); 177 static void radeonfb_putchar_aa32(void *, int, int, unsigned, long); 178 static void radeonfb_putchar_aa8(void *, int, int, unsigned, long); 179 #ifndef RADEONFB_ALWAYS_ACCEL_PUTCHAR 180 static void radeonfb_putchar_wrapper(void *, int, int, unsigned, long); 181 #endif 182 183 static int radeonfb_set_backlight(struct radeonfb_display *, int); 184 static int radeonfb_get_backlight(struct radeonfb_display *); 185 static void radeonfb_switch_backlight(struct radeonfb_display *, int); 186 static void radeonfb_lvds_callout(void *); 187 188 static void radeonfb_brightness_up(device_t); 189 static void radeonfb_brightness_down(device_t); 190 191 static struct videomode *radeonfb_best_refresh(struct videomode *, 192 struct videomode *); 193 static void radeonfb_pickres(struct radeonfb_display *, uint16_t *, 194 uint16_t *, int); 195 static const struct videomode *radeonfb_port_mode(struct radeonfb_softc *, 196 struct radeonfb_port *, int, int); 197 198 static int radeonfb_drm_print(void *, const char *); 199 200 #ifdef RADEONFB_DEBUG 201 int radeon_debug = 1; 202 #define DPRINTF(x) \ 203 if (radeon_debug) printf x 204 #define PRINTREG(r) DPRINTF((#r " = %08x\n", GET32(sc, r))) 205 #define PRINTPLL(r) DPRINTF((#r " = %08x\n", GETPLL(sc, r))) 206 #else 207 #define DPRINTF(x) 208 #define PRINTREG(r) 209 #define PRINTPLL(r) 210 #endif 211 212 #define ROUNDUP(x,y) (((x) + ((y) - 1)) & ~((y) - 1)) 213 214 #ifndef RADEON_DEFAULT_MODE 215 /* any reasonably modern display should handle this */ 216 #define RADEON_DEFAULT_MODE "1024x768x60" 217 #endif 218 219 extern const u_char rasops_cmap[768]; 220 221 const char *radeonfb_default_mode = RADEON_DEFAULT_MODE; 222 223 static struct { 224 int size; /* minimum memory size (MB) */ 225 int maxx; /* maximum x dimension */ 226 int maxy; /* maximum y dimension */ 227 int maxbpp; /* maximum bpp */ 228 int maxdisp; /* maximum logical display count */ 229 } radeonfb_limits[] = { 230 { 32, 2048, 1536, 32, 2 }, 231 { 16, 1600, 1200, 32, 2 }, 232 { 8, 1600, 1200, 32, 1 }, 233 { 0, 0, 0, 0, 0 }, 234 }; 235 236 static struct wsscreen_descr radeonfb_stdscreen = { 237 "fb", /* name */ 238 0, 0, /* ncols, nrows */ 239 NULL, /* textops */ 240 8, 16, /* fontwidth, fontheight */ 241 WSSCREEN_WSCOLORS | WSSCREEN_UNDERLINE | WSSCREEN_RESIZE, /* capabilities */ 242 0, /* modecookie */ 243 }; 244 245 struct wsdisplay_accessops radeonfb_accessops = { 246 radeonfb_ioctl, 247 radeonfb_mmap, 248 NULL, /* vcons_alloc_screen */ 249 NULL, /* vcons_free_screen */ 250 NULL, /* vcons_show_screen */ 251 NULL, /* load_font */ 252 NULL, /* pollc */ 253 NULL, /* scroll */ 254 }; 255 256 static struct { 257 uint16_t devid; 258 uint16_t family; 259 uint16_t flags; 260 } radeonfb_devices[] = 261 { 262 /* R100 family */ 263 { PCI_PRODUCT_ATI_RADEON_R100_QD, RADEON_R100, 0 }, 264 { PCI_PRODUCT_ATI_RADEON_R100_QE, RADEON_R100, 0 }, 265 { PCI_PRODUCT_ATI_RADEON_R100_QF, RADEON_R100, 0 }, 266 { PCI_PRODUCT_ATI_RADEON_R100_QG, RADEON_R100, 0 }, 267 268 /* RV100 family */ 269 { PCI_PRODUCT_ATI_RADEON_RV100_LY, RADEON_RV100, RFB_MOB }, 270 { PCI_PRODUCT_ATI_RADEON_RV100_LZ, RADEON_RV100, RFB_MOB }, 271 { PCI_PRODUCT_ATI_RADEON_RV100_QY, RADEON_RV100, 0 }, 272 { PCI_PRODUCT_ATI_RADEON_RV100_QZ, RADEON_RV100, 0 }, 273 274 /* RS100 family */ 275 { PCI_PRODUCT_ATI_RADEON_RS100_4136, RADEON_RS100, 0 }, 276 { PCI_PRODUCT_ATI_RADEON_RS100_4336, RADEON_RS100, RFB_MOB }, 277 278 /* RS200/RS250 family */ 279 { PCI_PRODUCT_ATI_RADEON_RS200_4337, RADEON_RS200, RFB_MOB }, 280 { PCI_PRODUCT_ATI_RADEON_RS200_A7, RADEON_RS200, 0 }, 281 { PCI_PRODUCT_ATI_RADEON_RS250_B7, RADEON_RS200, RFB_MOB }, 282 { PCI_PRODUCT_ATI_RADEON_RS250_D7, RADEON_RS200, 0 }, 283 284 /* R200 family */ 285 /* add more R200 products? , 5148 */ 286 { PCI_PRODUCT_ATI_RADEON_R200_BB, RADEON_R200, 0 }, 287 { PCI_PRODUCT_ATI_RADEON_R200_BC, RADEON_R200, 0 }, 288 { PCI_PRODUCT_ATI_RADEON_R200_QH, RADEON_R200, 0 }, 289 { PCI_PRODUCT_ATI_RADEON_R200_QL, RADEON_R200, 0 }, 290 { PCI_PRODUCT_ATI_RADEON_R200_QM, RADEON_R200, 0 }, 291 292 /* RV200 family */ 293 { PCI_PRODUCT_ATI_RADEON_RV200_LW, RADEON_RV200, RFB_MOB }, 294 { PCI_PRODUCT_ATI_RADEON_RV200_LX, RADEON_RV200, RFB_MOB }, 295 { PCI_PRODUCT_ATI_RADEON_RV200_QW, RADEON_RV200, 0 }, 296 { PCI_PRODUCT_ATI_RADEON_RV200_QX, RADEON_RV200, 0 }, 297 298 /* RV250 family */ 299 { PCI_PRODUCT_ATI_RADEON_RV250_4966, RADEON_RV250, 0 }, 300 { PCI_PRODUCT_ATI_RADEON_RV250_4967, RADEON_RV250, 0 }, 301 { PCI_PRODUCT_ATI_RADEON_RV250_4C64, RADEON_RV250, RFB_MOB }, 302 { PCI_PRODUCT_ATI_RADEON_RV250_4C66, RADEON_RV250, RFB_MOB }, 303 { PCI_PRODUCT_ATI_RADEON_RV250_4C67, RADEON_RV250, RFB_MOB }, 304 305 /* RS300 family */ 306 { PCI_PRODUCT_ATI_RADEON_RS300_X5, RADEON_RS300, 0 }, 307 { PCI_PRODUCT_ATI_RADEON_RS300_X4, RADEON_RS300, 0 }, 308 { PCI_PRODUCT_ATI_RADEON_RS300_7834, RADEON_RS300, 0 }, 309 { PCI_PRODUCT_ATI_RADEON_RS300_7835, RADEON_RS300, RFB_MOB }, 310 311 /* RV280 family */ 312 { PCI_PRODUCT_ATI_RADEON_RV280_5960, RADEON_RV280, 0 }, 313 { PCI_PRODUCT_ATI_RADEON_RV280_5961, RADEON_RV280, 0 }, 314 { PCI_PRODUCT_ATI_RADEON_RV280_5962, RADEON_RV280, 0 }, 315 { PCI_PRODUCT_ATI_RADEON_RV280_5963, RADEON_RV280, 0 }, 316 { PCI_PRODUCT_ATI_RADEON_RV280_5964, RADEON_RV280, 0 }, 317 { PCI_PRODUCT_ATI_RADEON_RV280_5C61, RADEON_RV280, RFB_MOB }, 318 { PCI_PRODUCT_ATI_RADEON_RV280_5C63, RADEON_RV280, RFB_MOB }, 319 320 /* R300 family */ 321 { PCI_PRODUCT_ATI_RADEON_R300_AD, RADEON_R300, 0 }, 322 { PCI_PRODUCT_ATI_RADEON_R300_AE, RADEON_R300, 0 }, 323 { PCI_PRODUCT_ATI_RADEON_R300_AF, RADEON_R300, 0 }, 324 { PCI_PRODUCT_ATI_RADEON_R300_AG, RADEON_R300, 0 }, 325 { PCI_PRODUCT_ATI_RADEON_R300_ND, RADEON_R300, 0 }, 326 { PCI_PRODUCT_ATI_RADEON_R300_NE, RADEON_R300, 0 }, 327 { PCI_PRODUCT_ATI_RADEON_R300_NF, RADEON_R300, 0 }, 328 { PCI_PRODUCT_ATI_RADEON_R300_NG, RADEON_R300, 0 }, 329 330 /* RV350/RV360 family */ 331 { PCI_PRODUCT_ATI_RADEON_RV350_AP, RADEON_RV350, 0 }, 332 { PCI_PRODUCT_ATI_RADEON_RV350_AQ, RADEON_RV350, 0 }, 333 { PCI_PRODUCT_ATI_RADEON_RV360_AR, RADEON_RV350, 0 }, 334 { PCI_PRODUCT_ATI_RADEON_RV350_AS, RADEON_RV350, 0 }, 335 { PCI_PRODUCT_ATI_RADEON_RV350_AT, RADEON_RV350, 0 }, 336 { PCI_PRODUCT_ATI_RADEON_RV350_AV, RADEON_RV350, 0 }, 337 { PCI_PRODUCT_ATI_RADEON_RV350_NP, RADEON_RV350, RFB_MOB }, 338 { PCI_PRODUCT_ATI_RADEON_RV350_NQ, RADEON_RV350, RFB_MOB }, 339 { PCI_PRODUCT_ATI_RADEON_RV350_NR, RADEON_RV350, RFB_MOB }, 340 { PCI_PRODUCT_ATI_RADEON_RV350_NS, RADEON_RV350, RFB_MOB }, 341 { PCI_PRODUCT_ATI_RADEON_RV350_NT, RADEON_RV350, RFB_MOB }, 342 { PCI_PRODUCT_ATI_RADEON_RV350_NV, RADEON_RV350, RFB_MOB }, 343 344 /* R350/R360 family */ 345 { PCI_PRODUCT_ATI_RADEON_R350_AH, RADEON_R350, 0 }, 346 { PCI_PRODUCT_ATI_RADEON_R350_AI, RADEON_R350, 0 }, 347 { PCI_PRODUCT_ATI_RADEON_R350_AJ, RADEON_R350, 0 }, 348 { PCI_PRODUCT_ATI_RADEON_R350_AK, RADEON_R350, 0 }, 349 { PCI_PRODUCT_ATI_RADEON_R350_NH, RADEON_R350, 0 }, 350 { PCI_PRODUCT_ATI_RADEON_R350_NI, RADEON_R350, 0 }, 351 { PCI_PRODUCT_ATI_RADEON_R350_NK, RADEON_R350, 0 }, 352 { PCI_PRODUCT_ATI_RADEON_R360_NJ, RADEON_R350, 0 }, 353 354 /* RV380/RV370 family */ 355 { PCI_PRODUCT_ATI_RADEON_RV380_3150, RADEON_RV380, RFB_MOB }, 356 { PCI_PRODUCT_ATI_RADEON_RV380_3154, RADEON_RV380, RFB_MOB }, 357 { PCI_PRODUCT_ATI_RADEON_RV380_3E50, RADEON_RV380, 0 }, 358 { PCI_PRODUCT_ATI_RADEON_RV380_3E54, RADEON_RV380, 0 }, 359 { PCI_PRODUCT_ATI_RADEON_RV370_5460, RADEON_RV380, RFB_MOB }, 360 { PCI_PRODUCT_ATI_RADEON_RV370_5464, RADEON_RV380, RFB_MOB }, 361 { PCI_PRODUCT_ATI_RADEON_RV370_5B60, RADEON_RV380, 0 }, 362 { PCI_PRODUCT_ATI_RADEON_RV370_5B63, RADEON_RV380, 0 }, 363 { PCI_PRODUCT_ATI_RADEON_RV370_5B64, RADEON_RV380, 0 }, 364 { PCI_PRODUCT_ATI_RADEON_RV370_5B65, RADEON_RV380, 0 }, 365 366 #if notyet 367 /* R420/R423 family */ 368 { PCI_PRODUCT_ATI_RADEON_R420_JH, RADEON_R420, 0 }, 369 { PCI_PRODUCT_ATI_RADEON_R420_JI, RADEON_R420, 0 }, 370 { PCI_PRODUCT_ATI_RADEON_R420_JJ, RADEON_R420, 0 }, 371 { PCI_PRODUCT_ATI_RADEON_R420_JK, RADEON_R420, 0 }, 372 { PCI_PRODUCT_ATI_RADEON_R420_JL, RADEON_R420, 0 }, 373 { PCI_PRODUCT_ATI_RADEON_R420_JM, RADEON_R420, 0 }, 374 { PCI_PRODUCT_ATI_RADEON_R420_JN, RADEON_R420, RFB_MOB }, 375 { PCI_PRODUCT_ATI_RADEON_R420_JP, RADEON_R420, 0 }, 376 { PCI_PRODUCT_ATI_RADEON_R423_UH, RADEON_R420, 0 }, 377 { PCI_PRODUCT_ATI_RADEON_R423_UI, RADEON_R420, 0 }, 378 { PCI_PRODUCT_ATI_RADEON_R423_UJ, RADEON_R420, 0 }, 379 { PCI_PRODUCT_ATI_RADEON_R423_UK, RADEON_R420, 0 }, 380 { PCI_PRODUCT_ATI_RADEON_R423_UQ, RADEON_R420, 0 }, 381 { PCI_PRODUCT_ATI_RADEON_R423_UR, RADEON_R420, 0 }, 382 { PCI_PRODUCT_ATI_RADEON_R423_UT, RADEON_R420, 0 }, 383 { PCI_PRODUCT_ATI_RADEON_R423_5D57, RADEON_R420, 0 }, 384 { PCI_PRODUCT_ATI_RADEON_R430_554F, RADEON_R420, 0 }, 385 386 /* R5xx family */ 387 { 0x7240, RADEON_R420, 0 }, 388 #endif 389 { 0, 0, 0 } 390 }; 391 392 static struct { 393 int divider; 394 int mask; 395 } radeonfb_dividers[] = { 396 { 16, 5 }, 397 { 12, 7 }, 398 { 8, 3 }, 399 { 6, 6 }, 400 { 4, 2 }, 401 { 3, 4 }, 402 { 2, 1 }, 403 { 1, 0 }, 404 { 0, 0 } 405 }; 406 407 /* 408 * This table taken from X11. 409 */ 410 static const struct { 411 int family; 412 struct radeon_tmds_pll plls[4]; 413 } radeonfb_tmds_pll[] = { 414 { RADEON_R100, {{12000, 0xa1b}, {-1, 0xa3f}}}, 415 { RADEON_RV100, {{12000, 0xa1b}, {-1, 0xa3f}}}, 416 { RADEON_RS100, {{0, 0}}}, 417 { RADEON_RV200, {{15000, 0xa1b}, {-1, 0xa3f}}}, 418 { RADEON_RS200, {{15000, 0xa1b}, {-1, 0xa3f}}}, 419 { RADEON_R200, {{15000, 0xa1b}, {-1, 0xa3f}}}, 420 { RADEON_RV250, {{15500, 0x81b}, {-1, 0x83f}}}, 421 { RADEON_RS300, {{0, 0}}}, 422 { RADEON_RV280, {{13000, 0x400f4}, {15000, 0x400f7}, {-1, 0x40111}}}, 423 { RADEON_R300, {{-1, 0xb01cb}}}, 424 { RADEON_R350, {{-1, 0xb01cb}}}, 425 { RADEON_RV350, {{15000, 0xb0155}, {-1, 0xb01cb}}}, 426 { RADEON_RV380, {{15000, 0xb0155}, {-1, 0xb01cb}}}, 427 { RADEON_R420, {{-1, 0xb01cb}}}, 428 }; 429 430 #define RADEONFB_BACKLIGHT_MAX 255 /* Maximum backlight level. */ 431 432 433 CFATTACH_DECL_NEW(radeonfb, sizeof (struct radeonfb_softc), 434 radeonfb_match, radeonfb_attach, NULL, NULL); 435 436 static int 437 radeonfb_match(device_t parent, cfdata_t match, void *aux) 438 { 439 const struct pci_attach_args *pa = aux; 440 int i; 441 442 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_ATI) 443 return 0; 444 445 for (i = 0; radeonfb_devices[i].devid; i++) { 446 if (PCI_PRODUCT(pa->pa_id) == radeonfb_devices[i].devid) 447 return 100; /* high to defeat VGA/VESA */ 448 } 449 450 return 0; 451 } 452 453 static void 454 radeonfb_attach(device_t parent, device_t dev, void *aux) 455 { 456 struct radeonfb_softc *sc = device_private(dev); 457 const struct pci_attach_args *pa = aux; 458 const char *mptr; 459 bus_size_t bsz; 460 pcireg_t screg; 461 int i, j, fg, bg, ul, flags; 462 uint32_t v; 463 464 sc->sc_dev = dev; 465 sc->sc_id = pa->pa_id; 466 for (i = 0; radeonfb_devices[i].devid; i++) { 467 if (PCI_PRODUCT(sc->sc_id) == radeonfb_devices[i].devid) 468 break; 469 } 470 471 pci_aprint_devinfo(pa, NULL); 472 473 DPRINTF(("%s", prop_dictionary_externalize(device_properties(dev)))); 474 475 KASSERT(radeonfb_devices[i].devid != 0); 476 sc->sc_pt = pa->pa_tag; 477 sc->sc_iot = pa->pa_iot; 478 sc->sc_pc = pa->pa_pc; 479 sc->sc_family = radeonfb_devices[i].family; 480 sc->sc_flags = radeonfb_devices[i].flags; 481 sc->sc_bios = NULL; 482 sc->sc_biossz = 0; 483 484 /* enable memory and IO access */ 485 screg = pci_conf_read(sc->sc_pc, sc->sc_pt, PCI_COMMAND_STATUS_REG); 486 screg |= PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE; 487 pci_conf_write(sc->sc_pc, sc->sc_pt, PCI_COMMAND_STATUS_REG, screg); 488 489 /* 490 * Some flags are general to entire chip families, and rather 491 * than clutter up the table with them, we go ahead and set 492 * them here. 493 */ 494 switch (sc->sc_family) { 495 case RADEON_RS100: 496 case RADEON_RS200: 497 sc->sc_flags |= RFB_IGP | RFB_RV100; 498 break; 499 500 case RADEON_RV100: 501 case RADEON_RV200: 502 case RADEON_RV250: 503 case RADEON_RV280: 504 sc->sc_flags |= RFB_RV100; 505 break; 506 507 case RADEON_RS300: 508 sc->sc_flags |= RFB_SDAC | RFB_IGP | RFB_RV100; 509 break; 510 511 case RADEON_R300: 512 case RADEON_RV350: 513 case RADEON_R350: 514 case RADEON_RV380: 515 case RADEON_R420: 516 /* newer chips */ 517 sc->sc_flags |= RFB_R300; 518 break; 519 520 case RADEON_R100: 521 sc->sc_flags |= RFB_NCRTC2; 522 break; 523 } 524 525 if ((sc->sc_family == RADEON_RV200) || 526 (sc->sc_family == RADEON_RV250) || 527 (sc->sc_family == RADEON_RV280) || 528 (sc->sc_family == RADEON_RV350)) { 529 bool inverted = 0; 530 /* backlight level is linear */ 531 DPRINTF(("found RV* chip, backlight is supposedly linear\n")); 532 prop_dictionary_get_bool(device_properties(sc->sc_dev), 533 "backlight_level_reverted", &inverted); 534 if (inverted) { 535 DPRINTF(("nope, it's inverted\n")); 536 sc->sc_flags |= RFB_INV_BLIGHT; 537 } 538 } else 539 sc->sc_flags |= RFB_INV_BLIGHT; 540 541 /* 542 * XXX: to support true multihead, this must change. 543 */ 544 sc->sc_ndisplays = 1; 545 546 /* XXX: */ 547 if (!HAS_CRTC2(sc)) { 548 sc->sc_ndisplays = 1; 549 } 550 551 if (pci_mapreg_map(pa, RADEON_MAPREG_MMIO, PCI_MAPREG_TYPE_MEM, 0, 552 &sc->sc_regt, &sc->sc_regh, &sc->sc_regaddr, 553 &sc->sc_regsz) != 0) { 554 aprint_error("%s: unable to map registers!\n", XNAME(sc)); 555 goto error; 556 } 557 558 if (pci_mapreg_info(sc->sc_pc, sc->sc_pt, PCI_MAPREG_ROM, 559 PCI_MAPREG_TYPE_ROM, &sc->sc_romaddr, &sc->sc_romsz, &flags) != 0) 560 { 561 aprint_error("%s: unable to find ROM!\n", XNAME(sc)); 562 goto error; 563 } 564 sc->sc_romt = sc->sc_memt; 565 566 sc->sc_mapped = TRUE; 567 568 /* scratch register test... */ 569 if (radeonfb_scratch_test(sc, RADEON_BIOS_0_SCRATCH, 0x55555555) || 570 radeonfb_scratch_test(sc, RADEON_BIOS_0_SCRATCH, 0xaaaaaaaa)) { 571 aprint_error("%s: scratch register test failed!\n", XNAME(sc)); 572 goto error; 573 } 574 575 PRINTREG(RADEON_CRTC_EXT_CNTL); 576 PRINTREG(RADEON_CRTC_GEN_CNTL); 577 PRINTREG(RADEON_CRTC2_GEN_CNTL); 578 PRINTREG(RADEON_DISP_OUTPUT_CNTL); 579 PRINTREG(RADEON_DAC_CNTL2); 580 PRINTREG(RADEON_BIOS_4_SCRATCH); 581 PRINTREG(RADEON_FP_GEN_CNTL); 582 sc->sc_fp_gen_cntl = GET32(sc, RADEON_FP_GEN_CNTL); 583 PRINTREG(RADEON_FP2_GEN_CNTL); 584 PRINTREG(RADEON_TMDS_CNTL); 585 PRINTREG(RADEON_TMDS_TRANSMITTER_CNTL); 586 PRINTREG(RADEON_TMDS_PLL_CNTL); 587 PRINTREG(RADEON_LVDS_GEN_CNTL); 588 PRINTREG(RADEON_DISP_HW_DEBUG); 589 PRINTREG(RADEON_PIXCLKS_CNTL); 590 PRINTREG(RADEON_CRTC_H_SYNC_STRT_WID); 591 PRINTREG(RADEON_FP_H_SYNC_STRT_WID); 592 PRINTREG(RADEON_CRTC2_H_SYNC_STRT_WID); 593 PRINTREG(RADEON_FP_H2_SYNC_STRT_WID); 594 595 /* 596 * XXX 597 * This was if (IS_RV100()), which is set for all pre-R3xx chips. 598 * I suspect this only makes sense on Sun XVR-100 with firmware that doesn't 599 * support DVI, so for now let's restrict it to only actual RV100 600 */ 601 if (sc->sc_family == RADEON_RV100) 602 PUT32(sc, RADEON_TMDS_PLL_CNTL, 0xa27); 603 604 /* XXX 605 * according to xf86-video-radeon R3xx has this bit backwards 606 */ 607 if (IS_R300(sc)) { 608 PATCH32(sc, RADEON_TMDS_TRANSMITTER_CNTL, 609 0, 610 ~(RADEON_TMDS_TRANSMITTER_PLLEN | RADEON_TMDS_TRANSMITTER_PLLRST)); 611 } else { 612 PATCH32(sc, RADEON_TMDS_TRANSMITTER_CNTL, 613 RADEON_TMDS_TRANSMITTER_PLLEN, 614 ~(RADEON_TMDS_TRANSMITTER_PLLEN | RADEON_TMDS_TRANSMITTER_PLLRST)); 615 } 616 617 radeonfb_i2c_init(sc); 618 619 radeonfb_loadbios(sc, pa); 620 621 #ifdef RADEONFB_BIOS_INIT 622 if (radeonfb_bios_init(sc)) { 623 aprint_error("%s: BIOS inititialization failed\n", XNAME(sc)); 624 } 625 #endif 626 627 if (radeonfb_getclocks(sc)) { 628 aprint_error("%s: Unable to get reference clocks from BIOS\n", 629 XNAME(sc)); 630 goto error; 631 } 632 633 if (radeonfb_gettmds(sc)) { 634 aprint_error("%s: Unable to identify TMDS PLL settings\n", 635 XNAME(sc)); 636 goto error; 637 } 638 639 aprint_verbose("%s: refclk = %d.%03d MHz, refdiv = %d " 640 "minpll = %d, maxpll = %d\n", XNAME(sc), 641 (int)sc->sc_refclk / 1000, (int)sc->sc_refclk % 1000, 642 (int)sc->sc_refdiv, (int)sc->sc_minpll, (int)sc->sc_maxpll); 643 644 radeonfb_getconnectors(sc); 645 646 radeonfb_set_fbloc(sc); 647 648 /* 64 MB should be enough -- more just wastes map entries */ 649 if (sc->sc_memsz > (64 << 20)) 650 sc->sc_memsz = (64 << 20); 651 652 for (i = 0; radeonfb_limits[i].size; i++) { 653 if (sc->sc_memsz >= radeonfb_limits[i].size) { 654 sc->sc_maxx = radeonfb_limits[i].maxx; 655 sc->sc_maxy = radeonfb_limits[i].maxy; 656 sc->sc_maxbpp = radeonfb_limits[i].maxbpp; 657 /* framebuffer offset, start at a 4K page */ 658 sc->sc_fboffset = sc->sc_memsz / 659 radeonfb_limits[i].maxdisp; 660 /* 661 * we use the fbsize to figure out where we can store 662 * things like cursor data. 663 */ 664 sc->sc_fbsize = 665 ROUNDUP(ROUNDUP(sc->sc_maxx * sc->sc_maxbpp / 8 , 666 RADEON_STRIDEALIGN) * sc->sc_maxy, 667 4096); 668 break; 669 } 670 } 671 672 673 radeonfb_init_misc(sc); 674 675 /* program the DAC wirings */ 676 for (i = 0; i < (HAS_CRTC2(sc) ? 2 : 1); i++) { 677 switch (sc->sc_ports[i].rp_dac_type) { 678 case RADEON_DAC_PRIMARY: 679 PATCH32(sc, RADEON_DAC_CNTL2, 680 i ? RADEON_DAC2_DAC_CLK_SEL : 0, 681 ~RADEON_DAC2_DAC_CLK_SEL); 682 break; 683 case RADEON_DAC_TVDAC: 684 /* we always use the TVDAC to drive a secondary analog 685 * CRT for now. if we ever support TV-out this will 686 * have to change. 687 */ 688 SET32(sc, RADEON_DAC_CNTL2, 689 RADEON_DAC2_DAC2_CLK_SEL); 690 PATCH32(sc, RADEON_DISP_HW_DEBUG, 691 i ? 0 : RADEON_CRT2_DISP1_SEL, 692 ~RADEON_CRT2_DISP1_SEL); 693 /* we're using CRTC2 for the 2nd port */ 694 if (sc->sc_ports[i].rp_number == 1) { 695 PATCH32(sc, RADEON_DISP_OUTPUT_CNTL, 696 RADEON_DISP_DAC2_SOURCE_CRTC2, 697 ~RADEON_DISP_DAC2_SOURCE_MASK); 698 } 699 700 break; 701 } 702 DPRINTF(("%s: port %d tmds type %d\n", __func__, i, 703 sc->sc_ports[i].rp_tmds_type)); 704 switch (sc->sc_ports[i].rp_tmds_type) { 705 case RADEON_TMDS_INT: 706 /* point FP0 at the CRTC this port uses */ 707 DPRINTF(("%s: plugging internal TMDS into CRTC %d\n", 708 __func__, sc->sc_ports[i].rp_number)); 709 if (IS_R300(sc)) { 710 PATCH32(sc, RADEON_FP_GEN_CNTL, 711 sc->sc_ports[i].rp_number ? 712 R200_FP_SOURCE_SEL_CRTC2 : 713 R200_FP_SOURCE_SEL_CRTC1, 714 ~R200_FP_SOURCE_SEL_MASK); 715 } else { 716 PATCH32(sc, RADEON_FP_GEN_CNTL, 717 sc->sc_ports[i].rp_number ? 718 RADEON_FP_SEL_CRTC2 : 719 RADEON_FP_SEL_CRTC1, 720 ~RADEON_FP_SEL_MASK); 721 } 722 break; 723 case RADEON_TMDS_EXT: 724 /* point FP2 at the CRTC this port uses */ 725 DPRINTF(("%s: plugging external TMDS into CRTC %d\n", 726 __func__, sc->sc_ports[i].rp_number)); 727 if (IS_R300(sc)) { 728 PATCH32(sc, RADEON_FP2_GEN_CNTL, 729 sc->sc_ports[i].rp_number ? 730 R200_FP2_SOURCE_SEL_CRTC2 : 731 R200_FP2_SOURCE_SEL_CRTC1, 732 ~R200_FP2_SOURCE_SEL_CRTC2); 733 } else { 734 PATCH32(sc, RADEON_FP2_GEN_CNTL, 735 sc->sc_ports[i].rp_number ? 736 RADEON_FP2_SRC_SEL_CRTC2 : 737 RADEON_FP2_SRC_SEL_CRTC1, 738 ~RADEON_FP2_SRC_SEL_CRTC2); 739 } 740 break; 741 } 742 } 743 PRINTREG(RADEON_DAC_CNTL2); 744 PRINTREG(RADEON_DISP_HW_DEBUG); 745 746 PRINTREG(RADEON_DAC_CNTL); 747 /* other DAC programming */ 748 v = GET32(sc, RADEON_DAC_CNTL); 749 v &= (RADEON_DAC_RANGE_CNTL_MASK | RADEON_DAC_BLANKING); 750 v |= RADEON_DAC_MASK_ALL | RADEON_DAC_8BIT_EN; 751 PUT32(sc, RADEON_DAC_CNTL, v); 752 PRINTREG(RADEON_DAC_CNTL); 753 754 /* XXX: this may need more investigation */ 755 PUT32(sc, RADEON_TV_DAC_CNTL, 0x00280203); 756 PRINTREG(RADEON_TV_DAC_CNTL); 757 758 /* enable TMDS */ 759 SET32(sc, RADEON_FP_GEN_CNTL, 760 RADEON_FP_TMDS_EN | 761 RADEON_FP_CRTC_DONT_SHADOW_VPAR | 762 RADEON_FP_CRTC_DONT_SHADOW_HEND); 763 /* 764 * XXX 765 * no idea why this is necessary - if I do not clear this bit on my 766 * iBook G4 the screen remains black, even though it's already clear. 767 * It needs to be set on my Sun XVR-100 for the DVI port to work 768 * TODO: 769 * see if this is still necessary now that CRTCs, DACs and outputs are 770 * getting wired up in a halfway sane way 771 */ 772 if (sc->sc_fp_gen_cntl & RADEON_FP_SEL_CRTC2) { 773 SET32(sc, RADEON_FP_GEN_CNTL, RADEON_FP_SEL_CRTC2); 774 } else { 775 CLR32(sc, RADEON_FP_GEN_CNTL, RADEON_FP_SEL_CRTC2); 776 } 777 778 /* 779 * we use bus_space_map instead of pci_mapreg, because we don't 780 * need the full aperature space. no point in wasting virtual 781 * address space we don't intend to use, right? 782 */ 783 if ((sc->sc_memsz < (4096 * 1024)) || 784 (pci_mapreg_info(sc->sc_pc, sc->sc_pt, RADEON_MAPREG_VRAM, 785 PCI_MAPREG_TYPE_MEM, &sc->sc_memaddr, &bsz, NULL) != 0) || 786 (bsz < sc->sc_memsz)) { 787 sc->sc_memsz = 0; 788 aprint_error("%s: Bad frame buffer configuration\n", 789 XNAME(sc)); 790 goto error; 791 } 792 793 sc->sc_memt = pa->pa_memt; 794 if (bus_space_map(sc->sc_memt, sc->sc_memaddr, sc->sc_memsz, 795 BUS_SPACE_MAP_LINEAR, &sc->sc_memh) != 0) { 796 sc->sc_memsz = 0; 797 aprint_error("%s: Unable to map frame buffer\n", XNAME(sc)); 798 goto error; 799 } 800 801 aprint_normal("%s: %d MB aperture at 0x%08x, " 802 "%d KB registers at 0x%08x\n", XNAME(sc), 803 (int)sc->sc_memsz >> 20, (unsigned)sc->sc_memaddr, 804 (int)sc->sc_regsz >> 10, (unsigned)sc->sc_regaddr); 805 806 /* setup default video mode from devprop (allows PROM override) */ 807 sc->sc_defaultmode = radeonfb_default_mode; 808 if (prop_dictionary_get_cstring_nocopy(device_properties(sc->sc_dev), 809 "videomode", &mptr)) { 810 811 strncpy(sc->sc_modebuf, mptr, sizeof(sc->sc_modebuf)); 812 sc->sc_defaultmode = sc->sc_modebuf; 813 } 814 815 /* initialize some basic display parameters */ 816 for (i = 0; i < sc->sc_ndisplays; i++) { 817 struct radeonfb_display *dp = &sc->sc_displays[i]; 818 struct rasops_info *ri; 819 long defattr; 820 struct wsemuldisplaydev_attach_args aa; 821 822 /* 823 * Figure out how many "displays" (desktops) we are going to 824 * support. If more than one, then each CRTC gets its own 825 * programming. 826 * 827 * XXX: this code needs to change to support mergedfb. 828 * XXX: would be nice to allow this to be overridden 829 */ 830 if (HAS_CRTC2(sc) && (sc->sc_ndisplays == 1)) { 831 DPRINTF(("dual crtcs!\n")); 832 dp->rd_ncrtcs = 2; 833 dp->rd_crtcs[0].rc_port = 834 &sc->sc_ports[0]; 835 dp->rd_crtcs[0].rc_number = sc->sc_ports[0].rp_number; 836 dp->rd_crtcs[1].rc_port = 837 &sc->sc_ports[1]; 838 dp->rd_crtcs[1].rc_number = sc->sc_ports[1].rp_number; 839 } else { 840 dp->rd_ncrtcs = 1; 841 dp->rd_crtcs[0].rc_port = 842 &sc->sc_ports[i]; 843 dp->rd_crtcs[0].rc_number = sc->sc_ports[i].rp_number; 844 } 845 846 dp->rd_softc = sc; 847 dp->rd_wsmode = WSDISPLAYIO_MODE_EMUL; 848 dp->rd_bpp = RADEONFB_DEFAULT_DEPTH; /* XXX */ 849 850 /* for text mode, we pick a resolution that won't 851 * require panning */ 852 radeonfb_pickres(dp, &dp->rd_virtx, &dp->rd_virty, 0); 853 854 aprint_normal("%s: display %d: " 855 "initial virtual resolution %dx%d at %d bpp\n", 856 XNAME(sc), i, dp->rd_virtx, dp->rd_virty, dp->rd_bpp); 857 aprint_normal_dev(sc->sc_dev, "using %d MB per display\n", 858 sc->sc_fboffset >> 20); 859 /* now select the *video mode* that we will use */ 860 for (j = 0; j < dp->rd_ncrtcs; j++) { 861 const struct videomode *vmp; 862 vmp = radeonfb_port_mode(sc, dp->rd_crtcs[j].rc_port, 863 dp->rd_virtx, dp->rd_virty); 864 865 /* 866 * virtual resolution should be at least as high as 867 * physical 868 */ 869 if (dp->rd_virtx < vmp->hdisplay || 870 dp->rd_virty < vmp->vdisplay) { 871 dp->rd_virtx = vmp->hdisplay; 872 dp->rd_virty = vmp->vdisplay; 873 } 874 875 dp->rd_crtcs[j].rc_videomode = *vmp; 876 printf("%s: port %d: physical %dx%d %dHz\n", 877 XNAME(sc), j, vmp->hdisplay, vmp->vdisplay, 878 DIVIDE(DIVIDE(vmp->dot_clock * 1000, 879 vmp->htotal), vmp->vtotal)); 880 } 881 882 /* N.B.: radeon wants 64-byte aligned stride */ 883 dp->rd_stride = dp->rd_virtx * dp->rd_bpp / 8; 884 dp->rd_stride = ROUNDUP(dp->rd_stride, RADEON_STRIDEALIGN); 885 DPRINTF(("stride: %d %d\n", dp->rd_stride, dp->rd_virtx)); 886 887 dp->rd_offset = sc->sc_fboffset * i; 888 dp->rd_fbptr = (vaddr_t)bus_space_vaddr(sc->sc_memt, 889 sc->sc_memh) + dp->rd_offset; 890 dp->rd_curoff = sc->sc_fboffset - 4096; /* 4KB cursor space */ 891 dp->rd_curptr = dp->rd_fbptr + dp->rd_curoff; 892 893 DPRINTF(("fpbtr = %p\n", (void *)dp->rd_fbptr)); 894 895 switch (dp->rd_bpp) { 896 case 8: 897 dp->rd_format = 2; 898 break; 899 case 32: 900 dp->rd_format = 6; 901 break; 902 default: 903 aprint_error("%s: bad depth %d\n", XNAME(sc), 904 dp->rd_bpp); 905 goto error; 906 } 907 908 DPRINTF(("init engine\n")); 909 /* XXX: this seems suspicious - per display engine 910 initialization? */ 911 radeonfb_engine_init(dp); 912 913 /* copy the template into place */ 914 dp->rd_wsscreens_storage[0] = radeonfb_stdscreen; 915 dp->rd_wsscreens = dp->rd_wsscreens_storage; 916 917 /* and make up the list */ 918 dp->rd_wsscreenlist.nscreens = 1; 919 dp->rd_wsscreenlist.screens = (void *)&dp->rd_wsscreens; 920 921 vcons_init(&dp->rd_vd, dp, dp->rd_wsscreens, 922 &radeonfb_accessops); 923 924 dp->rd_vd.init_screen = radeonfb_init_screen; 925 926 #ifdef RADEONFB_DEBUG 927 dp->rd_virty -= 200; 928 #endif 929 930 dp->rd_console = 0; 931 prop_dictionary_get_bool(device_properties(sc->sc_dev), 932 "is_console", &dp->rd_console); 933 934 dp->rd_vscreen.scr_flags |= VCONS_SCREEN_IS_STATIC; 935 936 937 vcons_init_screen(&dp->rd_vd, &dp->rd_vscreen, 938 dp->rd_console, &defattr); 939 940 ri = &dp->rd_vscreen.scr_ri; 941 942 /* clear the screen */ 943 rasops_unpack_attr(defattr, &fg, &bg, &ul); 944 dp->rd_bg = ri->ri_devcmap[bg & 0xf]; 945 radeonfb_rectfill(dp, 0, 0, ri->ri_width, ri->ri_height, 946 dp->rd_bg); 947 948 dp->rd_wsscreens->textops = &ri->ri_ops; 949 dp->rd_wsscreens->capabilities = ri->ri_caps; 950 dp->rd_wsscreens->nrows = ri->ri_rows; 951 dp->rd_wsscreens->ncols = ri->ri_cols; 952 953 #ifdef SPLASHSCREEN 954 dp->rd_splash.si_depth = ri->ri_depth; 955 dp->rd_splash.si_bits = ri->ri_bits; 956 dp->rd_splash.si_hwbits = ri->ri_hwbits; 957 dp->rd_splash.si_width = ri->ri_width; 958 dp->rd_splash.si_height = ri->ri_height; 959 dp->rd_splash.si_stride = ri->ri_stride; 960 dp->rd_splash.si_fillrect = NULL; 961 #endif 962 dp->rd_gc.gc_bitblt = radeonfb_bitblt; 963 dp->rd_gc.gc_rectfill = radeonfb_rectfill_a; 964 dp->rd_gc.gc_rop = RADEON_ROP3_S; 965 dp->rd_gc.gc_blitcookie = dp; 966 /* 967 * use memory between framebuffer and cursor area as glyph 968 * cache, cap at 4096 lines 969 */ 970 glyphcache_init(&dp->rd_gc, dp->rd_virty + 4, 971 uimin(4096, 972 (dp->rd_curoff / dp->rd_stride) - (dp->rd_virty + 4)), 973 dp->rd_virtx, 974 ri->ri_font->fontwidth, 975 ri->ri_font->fontheight, 976 defattr); 977 dp->rd_vd.show_screen_cookie = &dp->rd_gc; 978 dp->rd_vd.show_screen_cb = glyphcache_adapt; 979 980 if (dp->rd_console) { 981 982 radeonfb_modeswitch(dp); 983 wsdisplay_cnattach(dp->rd_wsscreens, ri, 0, 0, 984 defattr); 985 #ifdef SPLASHSCREEN 986 if (splash_render(&dp->rd_splash, 987 SPLASH_F_CENTER|SPLASH_F_FILL) == 0) 988 SCREEN_DISABLE_DRAWING(&dp->rd_vscreen); 989 else 990 #endif 991 vcons_replay_msgbuf(&dp->rd_vscreen); 992 } else { 993 994 /* 995 * since we're not the console we can postpone 996 * the rest until someone actually allocates a 997 * screen for us. but we do clear the screen 998 * at least. 999 */ 1000 memset(ri->ri_bits, 0, 1024); 1001 1002 radeonfb_modeswitch(dp); 1003 #ifdef SPLASHSCREEN 1004 if (splash_render(&dp->rd_splash, 1005 SPLASH_F_CENTER|SPLASH_F_FILL) == 0) 1006 SCREEN_DISABLE_DRAWING(&dp->rd_vscreen); 1007 #endif 1008 } 1009 1010 aa.console = dp->rd_console; 1011 aa.scrdata = &dp->rd_wsscreenlist; 1012 aa.accessops = &radeonfb_accessops; 1013 aa.accesscookie = &dp->rd_vd; 1014 1015 config_found(sc->sc_dev, &aa, wsemuldisplaydevprint); 1016 1017 radeonfb_blank(dp, 0); 1018 1019 /* Initialise delayed lvds operations for backlight. */ 1020 callout_init(&dp->rd_bl_lvds_co, 0); 1021 callout_setfunc(&dp->rd_bl_lvds_co, 1022 radeonfb_lvds_callout, dp); 1023 dp->rd_bl_on = 1; 1024 dp->rd_bl_level = radeonfb_get_backlight(dp); 1025 radeonfb_set_backlight(dp, dp->rd_bl_level); 1026 } 1027 1028 for (i = 0; i < RADEON_NDISPLAYS; i++) 1029 radeonfb_init_palette(&sc->sc_displays[i]); 1030 1031 if (HAS_CRTC2(sc)) { 1032 CLR32(sc, RADEON_CRTC2_GEN_CNTL, RADEON_CRTC2_DISP_DIS); 1033 } 1034 1035 CLR32(sc, RADEON_CRTC_EXT_CNTL, RADEON_CRTC_DISPLAY_DIS); 1036 SET32(sc, RADEON_FP_GEN_CNTL, RADEON_FP_FPON); 1037 pmf_event_register(dev, PMFE_DISPLAY_BRIGHTNESS_UP, 1038 radeonfb_brightness_up, TRUE); 1039 pmf_event_register(dev, PMFE_DISPLAY_BRIGHTNESS_DOWN, 1040 radeonfb_brightness_down, TRUE); 1041 1042 /* 1043 * if we attach a DRM we need to unmap registers in 1044 * WSDISPLAYIO_MODE_MAPPED, since this keeps us from doing things like 1045 * screen blanking we only do it if needed 1046 */ 1047 sc->sc_needs_unmap = 1048 (config_found_ia(dev, "drm", aux, radeonfb_drm_print) != 0); 1049 DPRINTF(("needs_unmap: %d\n", sc->sc_needs_unmap)); 1050 1051 PRINTREG(RADEON_CRTC_EXT_CNTL); 1052 PRINTREG(RADEON_CRTC_GEN_CNTL); 1053 PRINTREG(RADEON_CRTC2_GEN_CNTL); 1054 PRINTREG(RADEON_DISP_OUTPUT_CNTL); 1055 PRINTREG(RADEON_DAC_CNTL2); 1056 PRINTREG(RADEON_FP_GEN_CNTL); 1057 PRINTREG(RADEON_FP2_GEN_CNTL); 1058 PRINTREG(RADEON_TMDS_CNTL); 1059 PRINTREG(RADEON_TMDS_TRANSMITTER_CNTL); 1060 PRINTREG(RADEON_TMDS_PLL_CNTL); 1061 PRINTREG(RADEON_PIXCLKS_CNTL); 1062 1063 return; 1064 1065 error: 1066 if (sc->sc_biossz) 1067 free(sc->sc_bios, M_DEVBUF); 1068 1069 if (sc->sc_regsz) 1070 bus_space_unmap(sc->sc_regt, sc->sc_regh, sc->sc_regsz); 1071 1072 if (sc->sc_memsz) 1073 bus_space_unmap(sc->sc_memt, sc->sc_memh, sc->sc_memsz); 1074 } 1075 1076 static void 1077 radeonfb_map(struct radeonfb_softc *sc) 1078 { 1079 if (!sc->sc_mapped) { 1080 if (bus_space_map(sc->sc_regt, sc->sc_regaddr, sc->sc_regsz, 0, 1081 &sc->sc_regh) != 0) { 1082 aprint_error_dev(sc->sc_dev, 1083 "unable to map registers!\n"); 1084 return; 1085 } 1086 if (bus_space_map(sc->sc_memt, sc->sc_memaddr, sc->sc_memsz, 1087 BUS_SPACE_MAP_LINEAR, &sc->sc_memh) != 0) { 1088 sc->sc_memsz = 0; 1089 aprint_error_dev(sc->sc_dev, 1090 "Unable to map frame buffer\n"); 1091 return; 1092 } 1093 sc->sc_mapped = TRUE; 1094 } 1095 } 1096 1097 static void 1098 radeonfb_unmap(struct radeonfb_softc *sc) 1099 { 1100 if (!sc->sc_needs_unmap) 1101 return; 1102 1103 if (sc->sc_mapped) { 1104 bus_space_unmap(sc->sc_regt, sc->sc_regh, sc->sc_regsz); 1105 bus_space_unmap(sc->sc_memt, sc->sc_memh, sc->sc_memsz); 1106 sc->sc_mapped = FALSE; 1107 } 1108 } 1109 1110 static int 1111 radeonfb_drm_print(void *aux, const char *pnp) 1112 { 1113 if (pnp) 1114 aprint_normal("drm at %s", pnp); 1115 return (UNCONF); 1116 } 1117 1118 int 1119 radeonfb_ioctl(void *v, void *vs, 1120 unsigned long cmd, void *d, int flag, struct lwp *l) 1121 { 1122 struct vcons_data *vd; 1123 struct radeonfb_display *dp; 1124 struct radeonfb_softc *sc; 1125 struct wsdisplay_param *param; 1126 struct vcons_screen *ms; 1127 1128 vd = (struct vcons_data *)v; 1129 ms = vd->active; 1130 dp = (struct radeonfb_display *)vd->cookie; 1131 sc = dp->rd_softc; 1132 1133 /* can't do these without registers being mapped */ 1134 if (!sc->sc_mapped) { 1135 switch (cmd) { 1136 case WSDISPLAYIO_GVIDEO: 1137 case WSDISPLAYIO_SVIDEO: 1138 case WSDISPLAYIO_GETCMAP: 1139 case WSDISPLAYIO_PUTCMAP: 1140 case WSDISPLAYIO_SCURSOR: 1141 case WSDISPLAYIO_GCURPOS: 1142 case WSDISPLAYIO_SCURPOS: 1143 case WSDISPLAYIO_SETPARAM: 1144 return EINVAL; 1145 } 1146 } 1147 1148 switch (cmd) { 1149 case WSDISPLAYIO_GTYPE: 1150 *(unsigned *)d = WSDISPLAY_TYPE_PCIMISC; 1151 return 0; 1152 1153 case WSDISPLAYIO_GINFO: 1154 if (vd->active != NULL) { 1155 struct wsdisplay_fbinfo *fb; 1156 fb = (struct wsdisplay_fbinfo *)d; 1157 fb->width = dp->rd_virtx; 1158 fb->height = dp->rd_virty; 1159 fb->depth = dp->rd_bpp; 1160 fb->cmsize = 256; 1161 return 0; 1162 } else 1163 return ENODEV; 1164 case WSDISPLAYIO_GVIDEO: 1165 if (radeonfb_isblank(dp)) 1166 *(unsigned *)d = WSDISPLAYIO_VIDEO_OFF; 1167 else 1168 *(unsigned *)d = WSDISPLAYIO_VIDEO_ON; 1169 return 0; 1170 1171 case WSDISPLAYIO_SVIDEO: 1172 radeonfb_blank(dp, 1173 (*(unsigned int *)d == WSDISPLAYIO_VIDEO_OFF)); 1174 radeonfb_switch_backlight(dp, 1175 (*(unsigned int *)d == WSDISPLAYIO_VIDEO_ON)); 1176 return 0; 1177 1178 case WSDISPLAYIO_GETCMAP: 1179 if (dp->rd_bpp == 8) 1180 return radeonfb_getcmap(dp, 1181 (struct wsdisplay_cmap *)d); 1182 return EINVAL; 1183 1184 case WSDISPLAYIO_PUTCMAP: 1185 if (dp->rd_bpp == 8) 1186 return radeonfb_putcmap(dp, 1187 (struct wsdisplay_cmap *)d); 1188 return EINVAL; 1189 1190 case WSDISPLAYIO_LINEBYTES: 1191 *(unsigned *)d = dp->rd_stride; 1192 return 0; 1193 1194 case WSDISPLAYIO_SMODE: 1195 if (*(int *)d != dp->rd_wsmode) { 1196 dp->rd_wsmode = *(int *)d; 1197 if ((dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) || 1198 (dp->rd_wsmode == WSDISPLAYIO_MODE_DUMBFB)) 1199 radeonfb_map(sc); 1200 1201 if ((dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) && 1202 (dp->rd_vd.active)) { 1203 radeonfb_engine_init(dp); 1204 glyphcache_wipe(&dp->rd_gc); 1205 radeonfb_init_palette(dp); 1206 radeonfb_modeswitch(dp); 1207 radeonfb_rectfill(dp, 0, 0, dp->rd_virtx, 1208 dp->rd_virty, dp->rd_bg); 1209 vcons_redraw_screen(dp->rd_vd.active); 1210 } 1211 if (dp->rd_wsmode == WSDISPLAYIO_MODE_MAPPED) 1212 radeonfb_unmap(sc); 1213 } 1214 return 0; 1215 1216 case WSDISPLAYIO_GCURMAX: 1217 ((struct wsdisplay_curpos *)d)->x = RADEON_CURSORMAXX; 1218 ((struct wsdisplay_curpos *)d)->y = RADEON_CURSORMAXY; 1219 return 0; 1220 1221 case WSDISPLAYIO_SCURSOR: 1222 return radeonfb_set_cursor(dp, (struct wsdisplay_cursor *)d); 1223 1224 case WSDISPLAYIO_GCURSOR: 1225 return EPASSTHROUGH; 1226 1227 case WSDISPLAYIO_GCURPOS: 1228 ((struct wsdisplay_curpos *)d)->x = dp->rd_cursor.rc_pos.x; 1229 ((struct wsdisplay_curpos *)d)->y = dp->rd_cursor.rc_pos.y; 1230 return 0; 1231 1232 case WSDISPLAYIO_SCURPOS: 1233 return radeonfb_set_curpos(dp, (struct wsdisplay_curpos *)d); 1234 1235 case WSDISPLAYIO_SSPLASH: 1236 #if defined(SPLASHSCREEN) 1237 if (*(int *)d == 1) { 1238 SCREEN_DISABLE_DRAWING(&dp->rd_vscreen); 1239 splash_render(&dp->rd_splash, 1240 SPLASH_F_CENTER|SPLASH_F_FILL); 1241 } else 1242 SCREEN_ENABLE_DRAWING(&dp->rd_vscreen); 1243 return 0; 1244 #else 1245 return ENODEV; 1246 #endif 1247 case WSDISPLAYIO_GETPARAM: 1248 param = (struct wsdisplay_param *)d; 1249 switch (param->param) { 1250 case WSDISPLAYIO_PARAM_BRIGHTNESS: 1251 param->min = 0; 1252 param->max = 255; 1253 param->curval = dp->rd_bl_level; 1254 return 0; 1255 case WSDISPLAYIO_PARAM_BACKLIGHT: 1256 param->min = 0; 1257 param->max = RADEONFB_BACKLIGHT_MAX; 1258 param->curval = dp->rd_bl_on; 1259 return 0; 1260 } 1261 return EPASSTHROUGH; 1262 1263 case WSDISPLAYIO_SETPARAM: 1264 param = (struct wsdisplay_param *)d; 1265 switch (param->param) { 1266 case WSDISPLAYIO_PARAM_BRIGHTNESS: 1267 radeonfb_set_backlight(dp, param->curval); 1268 return 0; 1269 case WSDISPLAYIO_PARAM_BACKLIGHT: 1270 radeonfb_switch_backlight(dp, param->curval); 1271 return 0; 1272 } 1273 return EPASSTHROUGH; 1274 1275 /* PCI config read/write passthrough. */ 1276 case PCI_IOC_CFGREAD: 1277 case PCI_IOC_CFGWRITE: 1278 return pci_devioctl(sc->sc_pc, sc->sc_pt, cmd, d, flag, l); 1279 1280 case WSDISPLAYIO_GET_BUSID: 1281 return wsdisplayio_busid_pci(sc->sc_dev, sc->sc_pc, 1282 sc->sc_pt, d); 1283 1284 case WSDISPLAYIO_GET_EDID: { 1285 struct wsdisplayio_edid_info *ei = d; 1286 return wsdisplayio_get_edid(sc->sc_dev, ei); 1287 } 1288 1289 case WSDISPLAYIO_GET_FBINFO: { 1290 struct wsdisplayio_fbinfo *fbi = d; 1291 return wsdisplayio_get_fbinfo(&ms->scr_ri, fbi); 1292 } 1293 1294 default: 1295 return EPASSTHROUGH; 1296 } 1297 } 1298 1299 paddr_t 1300 radeonfb_mmap(void *v, void *vs, off_t offset, int prot) 1301 { 1302 struct vcons_data *vd; 1303 struct radeonfb_display *dp; 1304 struct radeonfb_softc *sc; 1305 paddr_t pa; 1306 1307 vd = (struct vcons_data *)v; 1308 dp = (struct radeonfb_display *)vd->cookie; 1309 sc = dp->rd_softc; 1310 1311 if ((offset >= 0) && (offset < (dp->rd_virty * dp->rd_stride))) { 1312 pa = bus_space_mmap(sc->sc_memt, 1313 sc->sc_memaddr + dp->rd_offset + offset, 0, 1314 prot, BUS_SPACE_MAP_LINEAR); 1315 return pa; 1316 } 1317 1318 /* 1319 * restrict all other mappings to processes with superuser privileges 1320 * or the kernel itself 1321 */ 1322 if (kauth_authorize_machdep(kauth_cred_get(), KAUTH_MACHDEP_UNMANAGEDMEM, 1323 NULL, NULL, NULL, NULL) != 0) { 1324 aprint_error_dev(sc->sc_dev, "mmap() rejected.\n"); 1325 return -1; 1326 } 1327 1328 if ((offset >= sc->sc_regaddr) && 1329 (offset < sc->sc_regaddr + sc->sc_regsz)) { 1330 return bus_space_mmap(sc->sc_regt, offset, 0, prot, 1331 BUS_SPACE_MAP_LINEAR); 1332 } 1333 1334 if ((offset >= sc->sc_memaddr) && 1335 (offset < sc->sc_memaddr + sc->sc_memsz)) { 1336 return bus_space_mmap(sc->sc_memt, offset, 0, prot, 1337 BUS_SPACE_MAP_LINEAR); 1338 } 1339 1340 if ((offset >= sc->sc_romaddr) && 1341 (offset < sc->sc_romaddr + sc->sc_romsz)) { 1342 return bus_space_mmap(sc->sc_memt, offset, 0, prot, 1343 BUS_SPACE_MAP_LINEAR); 1344 } 1345 1346 #ifdef PCI_MAGIC_IO_RANGE 1347 /* allow mapping of IO space */ 1348 if ((offset >= PCI_MAGIC_IO_RANGE) && 1349 (offset < PCI_MAGIC_IO_RANGE + 0x10000)) { 1350 pa = bus_space_mmap(sc->sc_iot, offset - PCI_MAGIC_IO_RANGE, 1351 0, prot, 0); 1352 return pa; 1353 } 1354 #endif /* PCI_MAGIC_IO_RANGE */ 1355 1356 return -1; 1357 } 1358 1359 static void 1360 radeonfb_loadbios(struct radeonfb_softc *sc, const struct pci_attach_args *pa) 1361 { 1362 bus_space_tag_t romt; 1363 bus_space_handle_t romh, biosh; 1364 bus_size_t romsz; 1365 bus_addr_t ptr; 1366 uint32_t busctl, crtcg, crtc2g = 0, viphctl, seprom, extc; 1367 int bios_voodoo = 0; 1368 1369 if (pci_mapreg_map(pa, PCI_MAPREG_ROM, PCI_MAPREG_TYPE_ROM, 1370 BUS_SPACE_MAP_PREFETCHABLE, &romt, &romh, NULL, &romsz) != 0) { 1371 aprint_verbose("%s: unable to map BIOS!\n", XNAME(sc)); 1372 return; 1373 } 1374 1375 pci_find_rom(pa, romt, romh, romsz, PCI_ROM_CODE_TYPE_X86, &biosh, 1376 &sc->sc_biossz); 1377 if (sc->sc_biossz != 0) goto foundit; 1378 1379 aprint_verbose("trying to read disabled BIOS...\n"); 1380 1381 bios_voodoo = 1; 1382 seprom = radeonfb_get32(sc, RADEON_SEPROM_CNTL1); 1383 radeonfb_put32(sc, RADEON_SEPROM_CNTL1, 1384 (seprom & ~RADEON_SCK_PRESCALE_MASK) | 1385 (0xc << RADEON_SCK_PRESCALE_SHIFT)); 1386 viphctl = radeonfb_get32(sc, RADEON_VIPH_CONTROL); 1387 radeonfb_put32(sc, RADEON_VIPH_CONTROL, viphctl & ~RADEON_VIPH_EN); 1388 busctl = radeonfb_get32(sc, RADEON_BUS_CNTL); 1389 radeonfb_put32(sc, RADEON_BUS_CNTL, busctl & ~RADEON_BUS_BIOS_DIS_ROM); 1390 crtcg = radeonfb_get32(sc, RADEON_CRTC_GEN_CNTL); 1391 radeonfb_put32(sc, RADEON_CRTC_GEN_CNTL, ((crtcg & ~RADEON_CRTC_EN) | 1392 (RADEON_CRTC_DISP_REQ_EN_B | 1393 RADEON_CRTC_EXT_DISP_EN))); 1394 if (HAS_CRTC2(sc)) { 1395 crtc2g = radeonfb_get32(sc, RADEON_CRTC2_GEN_CNTL); 1396 radeonfb_put32(sc, RADEON_CRTC2_GEN_CNTL, 1397 (crtc2g & ~RADEON_CRTC2_EN) | 1398 RADEON_CRTC2_DISP_REQ_EN_B); 1399 } 1400 extc = radeonfb_get32(sc, RADEON_CRTC_EXT_CNTL); 1401 radeonfb_put32(sc, RADEON_CRTC_EXT_CNTL, (extc & ~RADEON_CRTC_CRT_ON) | 1402 (RADEON_CRTC_SYNC_TRISTAT | 1403 RADEON_CRTC_DISPLAY_DIS)); 1404 pci_find_rom(pa, romt, romh, romsz, PCI_ROM_CODE_TYPE_X86, &biosh, 1405 &sc->sc_biossz); 1406 1407 foundit: 1408 if (sc->sc_biossz > 0) { 1409 sc->sc_bios = malloc(sc->sc_biossz, M_DEVBUF, M_WAITOK); 1410 bus_space_read_region_1(romt, biosh, 0, sc->sc_bios, 1411 sc->sc_biossz); 1412 } 1413 1414 if (bios_voodoo != 0) { 1415 radeonfb_put32(sc, RADEON_CRTC_EXT_CNTL, extc); 1416 if (HAS_CRTC2(sc)) { 1417 radeonfb_put32(sc, RADEON_CRTC2_GEN_CNTL, crtc2g); 1418 } 1419 radeonfb_put32(sc, RADEON_CRTC_GEN_CNTL, crtcg); 1420 radeonfb_put32(sc, RADEON_BUS_CNTL, busctl); 1421 radeonfb_put32(sc, RADEON_VIPH_CONTROL, viphctl); 1422 radeonfb_put32(sc, RADEON_SEPROM_CNTL1, seprom); 1423 } 1424 1425 /* unmap the PCI expansion rom */ 1426 bus_space_unmap(romt, romh, romsz); 1427 1428 /* turn off rom decoder now */ 1429 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM, 1430 pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM) & 1431 ~PCI_MAPREG_ROM_ENABLE); 1432 1433 if (sc->sc_biossz > 0) { 1434 ptr = GETBIOS16(sc, 0x48); 1435 if ((GETBIOS32(sc, ptr + 4) == 0x41544f4d /* "ATOM" */) || 1436 (GETBIOS32(sc, ptr + 4) == 0x4d4f5441 /* "MOTA" */)) { 1437 sc->sc_flags |= RFB_ATOM; 1438 } 1439 1440 aprint_verbose("%s: Found %d KB %s BIOS\n", XNAME(sc), 1441 (unsigned)sc->sc_biossz >> 10, 1442 IS_ATOM(sc) ? "ATOM" : "Legacy"); 1443 } 1444 } 1445 1446 1447 uint32_t 1448 radeonfb_get32(struct radeonfb_softc *sc, uint32_t reg) 1449 { 1450 1451 return bus_space_read_4(sc->sc_regt, sc->sc_regh, reg); 1452 } 1453 1454 void 1455 radeonfb_put32(struct radeonfb_softc *sc, uint32_t reg, uint32_t val) 1456 { 1457 1458 bus_space_write_4(sc->sc_regt, sc->sc_regh, reg, val); 1459 } 1460 1461 void 1462 radeonfb_put32s(struct radeonfb_softc *sc, uint32_t reg, uint32_t val) 1463 { 1464 1465 bus_space_write_stream_4(sc->sc_regt, sc->sc_regh, reg, val); 1466 } 1467 1468 void 1469 radeonfb_mask32(struct radeonfb_softc *sc, uint32_t reg, 1470 uint32_t andmask, uint32_t ormask) 1471 { 1472 int s; 1473 uint32_t val; 1474 1475 s = splhigh(); 1476 val = radeonfb_get32(sc, reg); 1477 val = (val & andmask) | ormask; 1478 radeonfb_put32(sc, reg, val); 1479 splx(s); 1480 } 1481 1482 uint32_t 1483 radeonfb_getindex(struct radeonfb_softc *sc, uint32_t idx) 1484 { 1485 int s; 1486 uint32_t val; 1487 1488 s = splhigh(); 1489 radeonfb_put32(sc, RADEON_MM_INDEX, idx); 1490 val = radeonfb_get32(sc, RADEON_MM_DATA); 1491 splx(s); 1492 1493 return (val); 1494 } 1495 1496 void 1497 radeonfb_putindex(struct radeonfb_softc *sc, uint32_t idx, uint32_t val) 1498 { 1499 int s; 1500 1501 s = splhigh(); 1502 radeonfb_put32(sc, RADEON_MM_INDEX, idx); 1503 radeonfb_put32(sc, RADEON_MM_DATA, val); 1504 splx(s); 1505 } 1506 1507 void 1508 radeonfb_maskindex(struct radeonfb_softc *sc, uint32_t idx, 1509 uint32_t andmask, uint32_t ormask) 1510 { 1511 int s; 1512 uint32_t val; 1513 1514 s = splhigh(); 1515 radeonfb_put32(sc, RADEON_MM_INDEX, idx); 1516 val = radeonfb_get32(sc, RADEON_MM_DATA); 1517 val = (val & andmask) | ormask; 1518 radeonfb_put32(sc, RADEON_MM_DATA, val); 1519 splx(s); 1520 } 1521 1522 uint32_t 1523 radeonfb_getpll(struct radeonfb_softc *sc, uint32_t idx) 1524 { 1525 int s; 1526 uint32_t val; 1527 1528 s = splhigh(); 1529 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, (idx & 0x3f)); 1530 val = radeonfb_get32(sc, RADEON_CLOCK_CNTL_DATA); 1531 if (HAS_R300CG(sc)) 1532 radeonfb_r300cg_workaround(sc); 1533 splx(s); 1534 1535 return (val); 1536 } 1537 1538 void 1539 radeonfb_putpll(struct radeonfb_softc *sc, uint32_t idx, uint32_t val) 1540 { 1541 int s; 1542 1543 s = splhigh(); 1544 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, (idx & 0x3f) | 1545 RADEON_PLL_WR_EN); 1546 radeonfb_put32(sc, RADEON_CLOCK_CNTL_DATA, val); 1547 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, 0); 1548 splx(s); 1549 } 1550 1551 void 1552 radeonfb_maskpll(struct radeonfb_softc *sc, uint32_t idx, 1553 uint32_t andmask, uint32_t ormask) 1554 { 1555 int s; 1556 uint32_t val; 1557 1558 s = splhigh(); 1559 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, (idx & 0x3f) | 1560 RADEON_PLL_WR_EN); 1561 val = radeonfb_get32(sc, RADEON_CLOCK_CNTL_DATA); 1562 val = (val & andmask) | ormask; 1563 radeonfb_put32(sc, RADEON_CLOCK_CNTL_DATA, val); 1564 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, 0); 1565 splx(s); 1566 } 1567 1568 int 1569 radeonfb_scratch_test(struct radeonfb_softc *sc, int reg, uint32_t v) 1570 { 1571 uint32_t saved; 1572 1573 saved = GET32(sc, reg); 1574 PUT32(sc, reg, v); 1575 if (GET32(sc, reg) != v) { 1576 return -1; 1577 } 1578 PUT32(sc, reg, saved); 1579 return 0; 1580 } 1581 1582 uintmax_t 1583 radeonfb_getprop_num(struct radeonfb_softc *sc, const char *name, 1584 uintmax_t defval) 1585 { 1586 prop_number_t pn; 1587 pn = prop_dictionary_get(device_properties(sc->sc_dev), name); 1588 if (pn == NULL) { 1589 return defval; 1590 } 1591 KASSERT(prop_object_type(pn) == PROP_TYPE_NUMBER); 1592 return (prop_number_integer_value(pn)); 1593 } 1594 1595 int 1596 radeonfb_getclocks(struct radeonfb_softc *sc) 1597 { 1598 bus_addr_t ptr; 1599 int refclk = 0; 1600 int refdiv = 0; 1601 int minpll = 0; 1602 int maxpll = 0; 1603 1604 /* load initial property values if port/board provides them */ 1605 refclk = radeonfb_getprop_num(sc, "refclk", 0) & 0xffff; 1606 refdiv = radeonfb_getprop_num(sc, "refdiv", 0) & 0xffff; 1607 minpll = radeonfb_getprop_num(sc, "minpll", 0) & 0xffffffffU; 1608 maxpll = radeonfb_getprop_num(sc, "maxpll", 0) & 0xffffffffU; 1609 1610 PRINTPLL(RADEON_PPLL_REF_DIV); 1611 PRINTPLL(RADEON_PPLL_DIV_0); 1612 PRINTPLL(RADEON_PPLL_DIV_1); 1613 PRINTPLL(RADEON_PPLL_DIV_2); 1614 PRINTPLL(RADEON_PPLL_DIV_3); 1615 PRINTREG(RADEON_CLOCK_CNTL_INDEX); 1616 PRINTPLL(RADEON_P2PLL_REF_DIV); 1617 PRINTPLL(RADEON_P2PLL_DIV_0); 1618 1619 if (refclk && refdiv && minpll && maxpll) 1620 goto dontprobe; 1621 1622 if (!sc->sc_biossz) { 1623 /* no BIOS */ 1624 aprint_verbose("%s: No video BIOS, using default clocks\n", 1625 XNAME(sc)); 1626 if (IS_IGP(sc)) 1627 refclk = refclk ? refclk : 1432; 1628 else 1629 refclk = refclk ? refclk : 2700; 1630 refdiv = refdiv ? refdiv : 12; 1631 minpll = minpll ? minpll : 12500; 1632 /* XXX 1633 * Need to check if the firmware or something programmed a 1634 * higher value than this, and if so, bump it. 1635 * The RV280 in my iBook is unhappy if the PLL input is less 1636 * than 360MHz 1637 */ 1638 maxpll = maxpll ? maxpll : 40000/*35000*/; 1639 } else if (IS_ATOM(sc)) { 1640 /* ATOM BIOS */ 1641 ptr = GETBIOS16(sc, 0x48); 1642 ptr = GETBIOS16(sc, ptr + 32); /* aka MasterDataStart */ 1643 ptr = GETBIOS16(sc, ptr + 12); /* pll info block */ 1644 refclk = refclk ? refclk : GETBIOS16(sc, ptr + 82); 1645 minpll = minpll ? minpll : GETBIOS16(sc, ptr + 78); 1646 maxpll = maxpll ? maxpll : GETBIOS16(sc, ptr + 32); 1647 /* 1648 * ATOM BIOS doesn't supply a reference divider, so we 1649 * have to probe for it. 1650 */ 1651 if (refdiv < 2) 1652 refdiv = GETPLL(sc, RADEON_PPLL_REF_DIV) & 1653 RADEON_PPLL_REF_DIV_MASK; 1654 /* 1655 * if probe is zero, just assume one that should work 1656 * for most parts 1657 */ 1658 if (refdiv < 2) 1659 refdiv = 12; 1660 1661 } else { 1662 uint32_t tmp = GETPLL(sc, RADEON_PPLL_REF_DIV); 1663 /* Legacy BIOS */ 1664 ptr = GETBIOS16(sc, 0x48); 1665 ptr = GETBIOS16(sc, ptr + 0x30); 1666 if (IS_R300(sc)) { 1667 refdiv = refdiv ? refdiv : 1668 (tmp & R300_PPLL_REF_DIV_ACC_MASK) >> 1669 R300_PPLL_REF_DIV_ACC_SHIFT; 1670 } else { 1671 refdiv = refdiv ? refdiv : 1672 tmp & RADEON_PPLL_REF_DIV_MASK; 1673 } 1674 refclk = refclk ? refclk : GETBIOS16(sc, ptr + 0x0E); 1675 refdiv = refdiv ? refdiv : GETBIOS16(sc, ptr + 0x10); 1676 minpll = minpll ? minpll : GETBIOS32(sc, ptr + 0x12); 1677 maxpll = maxpll ? maxpll : GETBIOS32(sc, ptr + 0x16); 1678 } 1679 1680 1681 dontprobe: 1682 sc->sc_refclk = refclk * 10; 1683 sc->sc_refdiv = refdiv; 1684 sc->sc_minpll = minpll * 10; 1685 sc->sc_maxpll = maxpll * 10; 1686 return 0; 1687 } 1688 1689 int 1690 radeonfb_calc_dividers(struct radeonfb_softc *sc, uint32_t dotclock, 1691 uint32_t *postdivbit, uint32_t *feedbackdiv, int flags) 1692 { 1693 int i; 1694 uint32_t outfreq; 1695 int div; 1696 1697 DPRINTF(("dot clock: %u\n", dotclock)); 1698 for (i = 0; (div = radeonfb_dividers[i].divider) != 0; i++) { 1699 1700 if ((flags & NO_ODD_FBDIV) && ((div & 1) != 0)) 1701 continue; 1702 1703 /* 1704 * XXX 1705 * the rv350 in my last generation 14" iBook G4 produces 1706 * garbage with dividers > 4. No idea if this is a hardware 1707 * limitation or an error in the divider table. 1708 */ 1709 if ((sc->sc_family == RADEON_RV350) && (div > 4)) 1710 continue; 1711 1712 outfreq = div * dotclock; 1713 if ((outfreq >= sc->sc_minpll) && 1714 (outfreq <= sc->sc_maxpll)) { 1715 DPRINTF(("outfreq: %u\n", outfreq)); 1716 *postdivbit = 1717 ((uint32_t)radeonfb_dividers[i].mask << 16); 1718 DPRINTF(("post divider: %d (mask %x)\n", div, 1719 *postdivbit)); 1720 break; 1721 } 1722 } 1723 1724 if (div == 0) 1725 return 1; 1726 1727 *feedbackdiv = DIVIDE(sc->sc_refdiv * outfreq, sc->sc_refclk); 1728 DPRINTF(("feedback divider: %d\n", *feedbackdiv)); 1729 return 0; 1730 } 1731 1732 #if 0 1733 #ifdef RADEONFB_DEBUG 1734 static void 1735 dump_buffer(const char *pfx, void *buffer, unsigned int size) 1736 { 1737 char asc[17]; 1738 unsigned ptr = (unsigned)buffer; 1739 char *start = (char *)(ptr & ~0xf); 1740 char *end = (char *)(ptr + size); 1741 1742 end = (char *)(((unsigned)end + 0xf) & ~0xf); 1743 1744 if (pfx == NULL) { 1745 pfx = ""; 1746 } 1747 1748 while (start < end) { 1749 unsigned offset = (unsigned)start & 0xf; 1750 if (offset == 0) { 1751 printf("%s%x: ", pfx, (unsigned)start); 1752 } 1753 if (((unsigned)start < ptr) || 1754 ((unsigned)start >= (ptr + size))) { 1755 printf(" "); 1756 asc[offset] = ' '; 1757 } else { 1758 printf("%02x", *(unsigned char *)start); 1759 if ((*start >= ' ') && (*start <= '~')) { 1760 asc[offset] = *start; 1761 } else { 1762 asc[offset] = '.'; 1763 } 1764 } 1765 asc[offset + 1] = 0; 1766 if (offset % 2) { 1767 printf(" "); 1768 } 1769 if (offset == 15) { 1770 printf(" %s\n", asc); 1771 } 1772 start++; 1773 } 1774 } 1775 #endif 1776 #endif 1777 1778 int 1779 radeonfb_getconnectors(struct radeonfb_softc *sc) 1780 { 1781 int i; 1782 int found = 0; 1783 1784 for (i = 0; i < 2; i++) { 1785 sc->sc_ports[i].rp_mon_type = RADEON_MT_UNKNOWN; 1786 sc->sc_ports[i].rp_ddc_type = RADEON_DDC_NONE; 1787 sc->sc_ports[i].rp_dac_type = RADEON_DAC_UNKNOWN; 1788 sc->sc_ports[i].rp_conn_type = RADEON_CONN_NONE; 1789 sc->sc_ports[i].rp_tmds_type = RADEON_TMDS_UNKNOWN; 1790 } 1791 1792 /* 1793 * This logic is borrowed from Xorg's radeon driver. 1794 */ 1795 if (!sc->sc_biossz) 1796 goto nobios; 1797 1798 if (IS_ATOM(sc)) { 1799 /* not done yet */ 1800 } else { 1801 uint16_t ptr; 1802 int port = 0; 1803 1804 ptr = GETBIOS16(sc, 0x48); 1805 ptr = GETBIOS16(sc, ptr + 0x50); 1806 for (i = 1; i < 4; i++) { 1807 uint16_t entry; 1808 uint8_t conn, ddc, dac, tmds; 1809 1810 /* 1811 * Parse the connector table. From reading the code, 1812 * it appears to made up of 16-bit entries for each 1813 * connector. The 16-bits are defined as: 1814 * 1815 * bits 12-15 - connector type (0 == end of table) 1816 * bits 8-11 - DDC type 1817 * bits 5-7 - ??? 1818 * bit 4 - TMDS type (1 = EXT, 0 = INT) 1819 * bits 1-3 - ??? 1820 * bit 0 - DAC, 1 = TVDAC, 0 = primary 1821 */ 1822 if (!GETBIOS8(sc, ptr + i * 2) && i > 1) 1823 break; 1824 entry = GETBIOS16(sc, ptr + i * 2); 1825 1826 conn = (entry >> 12) & 0xf; 1827 ddc = (entry >> 8) & 0xf; 1828 dac = (entry & 0x1) ? RADEON_DAC_TVDAC : 1829 RADEON_DAC_PRIMARY; 1830 tmds = ((entry >> 4) & 0x1) ? RADEON_TMDS_EXT : 1831 RADEON_TMDS_INT; 1832 1833 if (conn == RADEON_CONN_NONE) 1834 continue; /* no connector */ 1835 1836 /* 1837 * XXX 1838 * both Mac Mini variants have both outputs wired to 1839 * the same connector and share the DDC lines 1840 */ 1841 if ((found > 0) && 1842 (sc->sc_ports[port].rp_ddc_type == ddc)) { 1843 /* duplicate entry for same connector */ 1844 continue; 1845 } 1846 1847 /* internal DDC_DVI port gets priority */ 1848 if ((ddc == RADEON_DDC_DVI) || (port == 1)) 1849 port = 0; 1850 else 1851 port = 1; 1852 1853 sc->sc_ports[port].rp_ddc_type = 1854 ddc > RADEON_DDC_CRT2 ? RADEON_DDC_NONE : ddc; 1855 sc->sc_ports[port].rp_dac_type = dac; 1856 sc->sc_ports[port].rp_conn_type = 1857 uimin(conn, RADEON_CONN_UNSUPPORTED) ; 1858 1859 sc->sc_ports[port].rp_tmds_type = tmds; 1860 1861 if ((conn != RADEON_CONN_DVI_I) && 1862 (conn != RADEON_CONN_DVI_D) && 1863 (tmds == RADEON_TMDS_INT)) 1864 sc->sc_ports[port].rp_tmds_type = 1865 RADEON_TMDS_UNKNOWN; 1866 sc->sc_ports[port].rp_number = i - 1; 1867 1868 found += (port + 1); 1869 } 1870 } 1871 1872 nobios: 1873 if (!found) { 1874 bool dvi_ext = FALSE, dvi_int = FALSE; 1875 DPRINTF(("No connector info in BIOS!\n")); 1876 prop_dictionary_get_bool(device_properties(sc->sc_dev), 1877 "dvi-internal", &dvi_int); 1878 prop_dictionary_get_bool(device_properties(sc->sc_dev), 1879 "dvi-external", &dvi_ext); 1880 if (dvi_ext) { 1881 sc->sc_ports[0].rp_mon_type = RADEON_MT_UNKNOWN; 1882 sc->sc_ports[0].rp_ddc_type = RADEON_DDC_CRT2; 1883 sc->sc_ports[0].rp_dac_type = RADEON_DAC_PRIMARY; 1884 sc->sc_ports[0].rp_conn_type = RADEON_CONN_DVI_I; 1885 sc->sc_ports[0].rp_tmds_type = RADEON_TMDS_EXT; /* output to fp2 */ 1886 sc->sc_ports[0].rp_number = 0; 1887 sc->sc_ports[1].rp_mon_type = RADEON_MT_UNKNOWN; 1888 sc->sc_ports[1].rp_ddc_type = RADEON_DDC_NONE; 1889 sc->sc_ports[1].rp_dac_type = RADEON_DAC_UNKNOWN; 1890 sc->sc_ports[1].rp_conn_type = RADEON_CONN_NONE; 1891 sc->sc_ports[1].rp_tmds_type = RADEON_TMDS_UNKNOWN; 1892 sc->sc_ports[1].rp_number = 1; 1893 } else if (dvi_int) { 1894 sc->sc_ports[0].rp_mon_type = RADEON_MT_UNKNOWN; 1895 sc->sc_ports[0].rp_ddc_type = RADEON_DDC_CRT2; 1896 sc->sc_ports[0].rp_dac_type = RADEON_DAC_PRIMARY; 1897 sc->sc_ports[0].rp_conn_type = RADEON_CONN_DVI_I; 1898 sc->sc_ports[0].rp_tmds_type = RADEON_TMDS_INT; 1899 sc->sc_ports[0].rp_number = 0; 1900 sc->sc_ports[1].rp_mon_type = RADEON_MT_UNKNOWN; 1901 sc->sc_ports[1].rp_ddc_type = RADEON_DDC_NONE; 1902 sc->sc_ports[1].rp_dac_type = RADEON_DAC_UNKNOWN; 1903 sc->sc_ports[1].rp_conn_type = RADEON_CONN_NONE; 1904 sc->sc_ports[1].rp_tmds_type = RADEON_TMDS_UNKNOWN; 1905 sc->sc_ports[1].rp_number = 1; 1906 } else if IS_MOBILITY(sc) { 1907 /* default, port 0 = internal TMDS, port 1 = CRT */ 1908 sc->sc_ports[0].rp_mon_type = RADEON_MT_UNKNOWN; 1909 sc->sc_ports[0].rp_ddc_type = RADEON_DDC_DVI; 1910 sc->sc_ports[0].rp_dac_type = RADEON_DAC_TVDAC; 1911 sc->sc_ports[0].rp_conn_type = RADEON_CONN_DVI_D; 1912 sc->sc_ports[0].rp_tmds_type = RADEON_TMDS_INT; 1913 sc->sc_ports[0].rp_number = 0; 1914 1915 sc->sc_ports[1].rp_mon_type = RADEON_MT_UNKNOWN; 1916 sc->sc_ports[1].rp_ddc_type = RADEON_DDC_VGA; 1917 sc->sc_ports[1].rp_dac_type = RADEON_DAC_PRIMARY; 1918 sc->sc_ports[1].rp_conn_type = RADEON_CONN_CRT; 1919 sc->sc_ports[1].rp_tmds_type = RADEON_TMDS_EXT; 1920 sc->sc_ports[1].rp_number = 1; 1921 } else { 1922 /* default, port 0 = DVI, port 1 = CRT */ 1923 sc->sc_ports[0].rp_mon_type = RADEON_MT_UNKNOWN; 1924 sc->sc_ports[0].rp_ddc_type = RADEON_DDC_DVI; 1925 sc->sc_ports[0].rp_dac_type = RADEON_DAC_TVDAC; 1926 sc->sc_ports[0].rp_conn_type = RADEON_CONN_DVI_D; 1927 sc->sc_ports[0].rp_tmds_type = RADEON_TMDS_INT; 1928 sc->sc_ports[0].rp_number = 0; 1929 1930 sc->sc_ports[1].rp_mon_type = RADEON_MT_UNKNOWN; 1931 sc->sc_ports[1].rp_ddc_type = RADEON_DDC_VGA; 1932 sc->sc_ports[1].rp_dac_type = RADEON_DAC_PRIMARY; 1933 sc->sc_ports[1].rp_conn_type = RADEON_CONN_CRT; 1934 sc->sc_ports[1].rp_tmds_type = RADEON_TMDS_UNKNOWN; 1935 sc->sc_ports[1].rp_number = 1; 1936 } 1937 } 1938 1939 /* 1940 * Fixup for RS300/RS350/RS400 chips, that lack a primary DAC. 1941 * these chips should use TVDAC for the VGA port. 1942 */ 1943 if (HAS_SDAC(sc)) { 1944 if (sc->sc_ports[0].rp_conn_type == RADEON_CONN_CRT) { 1945 sc->sc_ports[0].rp_dac_type = RADEON_DAC_TVDAC; 1946 sc->sc_ports[1].rp_dac_type = RADEON_DAC_PRIMARY; 1947 } else { 1948 sc->sc_ports[1].rp_dac_type = RADEON_DAC_TVDAC; 1949 sc->sc_ports[0].rp_dac_type = RADEON_DAC_PRIMARY; 1950 } 1951 } else if (!HAS_CRTC2(sc)) { 1952 sc->sc_ports[0].rp_dac_type = RADEON_DAC_PRIMARY; 1953 } 1954 1955 for (i = 0; i < 2; i++) { 1956 char edid[128]; 1957 uint8_t ddc; 1958 struct edid_info *eip = &sc->sc_ports[i].rp_edid; 1959 prop_data_t edid_data; 1960 1961 DPRINTF(("Port #%d:\n", i)); 1962 DPRINTF((" conn = %d\n", sc->sc_ports[i].rp_conn_type)); 1963 DPRINTF((" ddc = %d\n", sc->sc_ports[i].rp_ddc_type)); 1964 DPRINTF((" dac = %d\n", sc->sc_ports[i].rp_dac_type)); 1965 DPRINTF((" tmds = %d\n", sc->sc_ports[i].rp_tmds_type)); 1966 DPRINTF((" crtc = %d\n", sc->sc_ports[i].rp_number)); 1967 1968 sc->sc_ports[i].rp_edid_valid = 0; 1969 /* first look for static EDID data */ 1970 if ((edid_data = prop_dictionary_get(device_properties( 1971 sc->sc_dev), "EDID")) != NULL) { 1972 1973 aprint_debug_dev(sc->sc_dev, "using static EDID\n"); 1974 memcpy(edid, prop_data_data_nocopy(edid_data), 128); 1975 if (edid_parse(edid, eip) == 0) { 1976 1977 sc->sc_ports[i].rp_edid_valid = 1; 1978 #ifdef RADEONFB_DEBUG 1979 edid_print(eip); 1980 #endif 1981 } 1982 } 1983 /* if we didn't find any we'll try to talk to the monitor */ 1984 if (sc->sc_ports[i].rp_edid_valid != 1) { 1985 1986 ddc = sc->sc_ports[i].rp_ddc_type; 1987 if (ddc != RADEON_DDC_NONE) { 1988 if ((radeonfb_i2c_read_edid(sc, ddc, edid) 1989 == 0) && (edid_parse(edid, eip) == 0)) { 1990 1991 sc->sc_ports[i].rp_edid_valid = 1; 1992 #ifdef RADEONFB_DEBUG 1993 edid_print(eip); 1994 #endif 1995 } 1996 } 1997 } 1998 } 1999 2000 return found; 2001 } 2002 2003 int 2004 radeonfb_gettmds(struct radeonfb_softc *sc) 2005 { 2006 int i; 2007 2008 if (!sc->sc_biossz) { 2009 goto nobios; 2010 } 2011 2012 if (IS_ATOM(sc)) { 2013 /* XXX: not done yet */ 2014 } else { 2015 uint16_t ptr; 2016 int n; 2017 2018 ptr = GETBIOS16(sc, 0x48); 2019 ptr = GETBIOS16(sc, ptr + 0x34); 2020 DPRINTF(("DFP table revision %d\n", GETBIOS8(sc, ptr))); 2021 if (GETBIOS8(sc, ptr) == 3) { 2022 /* revision three table */ 2023 n = GETBIOS8(sc, ptr + 5) + 1; 2024 n = uimin(n, 4); 2025 2026 memset(sc->sc_tmds_pll, 0, sizeof (sc->sc_tmds_pll)); 2027 for (i = 0; i < n; i++) { 2028 sc->sc_tmds_pll[i].rtp_pll = GETBIOS32(sc, 2029 ptr + i * 10 + 8); 2030 sc->sc_tmds_pll[i].rtp_freq = GETBIOS16(sc, 2031 ptr + i * 10 + 0x10); 2032 DPRINTF(("TMDS_PLL dot clock %d pll %x\n", 2033 sc->sc_tmds_pll[i].rtp_freq, 2034 sc->sc_tmds_pll[i].rtp_pll)); 2035 } 2036 return 0; 2037 } 2038 } 2039 2040 nobios: 2041 DPRINTF(("no suitable DFP table present\n")); 2042 for (i = 0; 2043 i < sizeof (radeonfb_tmds_pll) / sizeof (radeonfb_tmds_pll[0]); 2044 i++) { 2045 int j; 2046 2047 if (radeonfb_tmds_pll[i].family != sc->sc_family) 2048 continue; 2049 2050 for (j = 0; j < 4; j++) { 2051 sc->sc_tmds_pll[j] = radeonfb_tmds_pll[i].plls[j]; 2052 DPRINTF(("TMDS_PLL dot clock %d pll %x\n", 2053 sc->sc_tmds_pll[j].rtp_freq, 2054 sc->sc_tmds_pll[j].rtp_pll)); 2055 } 2056 return 0; 2057 } 2058 2059 return -1; 2060 } 2061 2062 const struct videomode * 2063 radeonfb_modelookup(const char *name) 2064 { 2065 int i; 2066 2067 for (i = 0; i < videomode_count; i++) { 2068 if (!strcmp(name, videomode_list[i].name)) 2069 return &videomode_list[i]; 2070 } 2071 return NULL; 2072 } 2073 2074 void 2075 radeonfb_pllwriteupdate(struct radeonfb_softc *sc, int crtc) 2076 { 2077 if (crtc) { 2078 while (GETPLL(sc, RADEON_P2PLL_REF_DIV) & 2079 RADEON_P2PLL_ATOMIC_UPDATE_R); 2080 SETPLL(sc, RADEON_P2PLL_REF_DIV, RADEON_P2PLL_ATOMIC_UPDATE_W); 2081 } else { 2082 while (GETPLL(sc, RADEON_PPLL_REF_DIV) & 2083 RADEON_PPLL_ATOMIC_UPDATE_R); 2084 SETPLL(sc, RADEON_PPLL_REF_DIV, RADEON_PPLL_ATOMIC_UPDATE_W); 2085 } 2086 } 2087 2088 void 2089 radeonfb_pllwaitatomicread(struct radeonfb_softc *sc, int crtc) 2090 { 2091 int i; 2092 2093 for (i = 10000; i; i--) { 2094 if (crtc) { 2095 if (GETPLL(sc, RADEON_P2PLL_REF_DIV) & 2096 RADEON_P2PLL_ATOMIC_UPDATE_R) 2097 break; 2098 } else { 2099 if (GETPLL(sc, RADEON_PPLL_REF_DIV) & 2100 RADEON_PPLL_ATOMIC_UPDATE_R) 2101 break; 2102 } 2103 } 2104 } 2105 2106 void 2107 radeonfb_program_vclk(struct radeonfb_softc *sc, int dotclock, int crtc, int flags) 2108 { 2109 uint32_t pbit = 0; 2110 uint32_t feed = 0; 2111 uint32_t data, refdiv, div0, r2xxref; 2112 2113 radeonfb_calc_dividers(sc, dotclock, &pbit, &feed, flags); 2114 2115 if (crtc == 0) { 2116 2117 refdiv = GETPLL(sc, RADEON_PPLL_REF_DIV); 2118 2119 /* 2120 * XXX 2121 * the RV350 in my last generation iBook G4 behaves like an 2122 * r2xx here - try to detect that and not screw up the reference 2123 * divider. 2124 * xf86-video-radeon just skips PLL programming altogether 2125 * on iBooks, probably for this reason. 2126 */ 2127 r2xxref = (refdiv & ~RADEON_PPLL_REF_DIV_MASK) | sc->sc_refdiv; 2128 if (IS_R300(sc) && (r2xxref != refdiv)) { 2129 refdiv = (refdiv & ~R300_PPLL_REF_DIV_ACC_MASK) | 2130 (sc->sc_refdiv << R300_PPLL_REF_DIV_ACC_SHIFT); 2131 } else { 2132 refdiv = (refdiv & ~RADEON_PPLL_REF_DIV_MASK) | 2133 sc->sc_refdiv; 2134 } 2135 DPRINTF(("refdiv %08x\n", refdiv)); 2136 div0 = GETPLL(sc, RADEON_PPLL_DIV_0); 2137 DPRINTF(("div0 %08x\n", div0)); 2138 div0 &= ~(RADEON_PPLL_FB3_DIV_MASK | 2139 RADEON_PPLL_POST3_DIV_MASK); 2140 div0 |= pbit; 2141 div0 |= (feed & RADEON_PPLL_FB3_DIV_MASK); 2142 DPRINTF(("div0 %08x\n", div0)); 2143 2144 if ((refdiv == GETPLL(sc, RADEON_PPLL_REF_DIV)) && 2145 (div0 == GETPLL(sc, RADEON_PPLL_DIV_0))) { 2146 /* 2147 * nothing to do here, the PLL is already where we 2148 * want it 2149 */ 2150 PATCH32(sc, RADEON_CLOCK_CNTL_INDEX, 0, 2151 ~RADEON_PLL_DIV_SEL); 2152 aprint_debug_dev(sc->sc_dev, "no need to touch the PLL\n"); 2153 return; 2154 } 2155 2156 /* alright, we do need to reprogram stuff */ 2157 PATCHPLL(sc, RADEON_VCLK_ECP_CNTL, 2158 RADEON_VCLK_SRC_SEL_CPUCLK, 2159 ~RADEON_VCLK_SRC_SEL_MASK); 2160 2161 /* put vclk into reset, use atomic updates */ 2162 SETPLL(sc, RADEON_PPLL_CNTL, 2163 RADEON_PPLL_REFCLK_SEL | 2164 RADEON_PPLL_FBCLK_SEL | 2165 RADEON_PPLL_RESET | 2166 RADEON_PPLL_ATOMIC_UPDATE_EN | 2167 RADEON_PPLL_VGA_ATOMIC_UPDATE_EN); 2168 2169 /* select clock 0 */ 2170 PATCH32(sc, RADEON_CLOCK_CNTL_INDEX, 0, 2171 ~RADEON_PLL_DIV_SEL); 2172 2173 PUTPLL(sc, RADEON_PPLL_REF_DIV, refdiv); 2174 2175 /* xf86-video-radeon does this, not sure why */ 2176 PUTPLL(sc, RADEON_PPLL_DIV_0, div0); 2177 PUTPLL(sc, RADEON_PPLL_DIV_0, div0); 2178 2179 /* use the atomic update */ 2180 radeonfb_pllwriteupdate(sc, crtc); 2181 2182 /* and wait for it to complete */ 2183 radeonfb_pllwaitatomicread(sc, crtc); 2184 2185 /* program HTOTAL (why?) */ 2186 PUTPLL(sc, RADEON_HTOTAL_CNTL, 0); 2187 2188 /* drop reset */ 2189 CLRPLL(sc, RADEON_PPLL_CNTL, 2190 RADEON_PPLL_RESET | RADEON_PPLL_SLEEP | 2191 RADEON_PPLL_ATOMIC_UPDATE_EN | 2192 RADEON_PPLL_VGA_ATOMIC_UPDATE_EN); 2193 2194 PRINTPLL(RADEON_PPLL_CNTL); 2195 PRINTPLL(RADEON_PPLL_REF_DIV); 2196 PRINTPLL(RADEON_PPLL_DIV_3); 2197 2198 /* give clock time to lock */ 2199 delay(50000); 2200 2201 PATCHPLL(sc, RADEON_VCLK_ECP_CNTL, 2202 RADEON_VCLK_SRC_SEL_PPLLCLK, 2203 ~RADEON_VCLK_SRC_SEL_MASK); 2204 2205 } else { 2206 2207 PATCHPLL(sc, RADEON_PIXCLKS_CNTL, 2208 RADEON_PIX2CLK_SRC_SEL_CPUCLK, 2209 ~RADEON_PIX2CLK_SRC_SEL_MASK); 2210 2211 /* put vclk into reset, use atomic updates */ 2212 SETPLL(sc, RADEON_P2PLL_CNTL, 2213 RADEON_P2PLL_RESET | 2214 RADEON_P2PLL_ATOMIC_UPDATE_EN | 2215 RADEON_P2PLL_VGA_ATOMIC_UPDATE_EN); 2216 2217 /* program reference divider */ 2218 PATCHPLL(sc, RADEON_P2PLL_REF_DIV, sc->sc_refdiv, 2219 ~RADEON_P2PLL_REF_DIV_MASK); 2220 2221 /* program feedback and post dividers */ 2222 data = GETPLL(sc, RADEON_P2PLL_DIV_0); 2223 data &= ~(RADEON_P2PLL_FB0_DIV_MASK | 2224 RADEON_P2PLL_POST0_DIV_MASK); 2225 data |= pbit; 2226 data |= (feed & RADEON_P2PLL_FB0_DIV_MASK); 2227 PUTPLL(sc, RADEON_P2PLL_DIV_0, data); 2228 PUTPLL(sc, RADEON_P2PLL_DIV_0, data); 2229 2230 PRINTPLL(RADEON_P2PLL_REF_DIV); 2231 PRINTPLL(RADEON_P2PLL_DIV_0); 2232 2233 /* use the atomic update */ 2234 radeonfb_pllwriteupdate(sc, crtc); 2235 2236 /* and wait for it to complete */ 2237 radeonfb_pllwaitatomicread(sc, crtc); 2238 2239 /* program HTOTAL (why?) */ 2240 PUTPLL(sc, RADEON_HTOTAL2_CNTL, 0); 2241 2242 /* drop reset */ 2243 CLRPLL(sc, RADEON_P2PLL_CNTL, 2244 RADEON_P2PLL_RESET | RADEON_P2PLL_SLEEP | 2245 RADEON_P2PLL_ATOMIC_UPDATE_EN | 2246 RADEON_P2PLL_VGA_ATOMIC_UPDATE_EN); 2247 2248 /* allow time for clock to lock */ 2249 delay(50000); 2250 2251 PATCHPLL(sc, RADEON_PIXCLKS_CNTL, 2252 RADEON_PIX2CLK_SRC_SEL_P2PLLCLK, 2253 ~RADEON_PIX2CLK_SRC_SEL_MASK); 2254 } 2255 PRINTREG(RADEON_CRTC_MORE_CNTL); 2256 } 2257 2258 void 2259 radeonfb_modeswitch(struct radeonfb_display *dp) 2260 { 2261 struct radeonfb_softc *sc = dp->rd_softc; 2262 int i; 2263 2264 /* blank the display while we switch modes */ 2265 radeonfb_blank(dp, 1); 2266 2267 #if 0 2268 SET32(sc, RADEON_CRTC_EXT_CNTL, 2269 RADEON_CRTC_VSYNC_DIS | RADEON_CRTC_HSYNC_DIS | 2270 RADEON_CRTC_DISPLAY_DIS /* | RADEON_CRTC_DISP_REQ_EN_B */); 2271 #endif 2272 2273 /* these registers might get in the way... */ 2274 PUT32(sc, RADEON_OVR_CLR, 0); 2275 PUT32(sc, RADEON_OVR_WID_LEFT_RIGHT, 0); 2276 PUT32(sc, RADEON_OVR_WID_TOP_BOTTOM, 0); 2277 PUT32(sc, RADEON_OV0_SCALE_CNTL, 0); 2278 PUT32(sc, RADEON_SUBPIC_CNTL, 0); 2279 PUT32(sc, RADEON_VIPH_CONTROL, 0); 2280 PUT32(sc, RADEON_I2C_CNTL_1, 0); 2281 PUT32(sc, RADEON_GEN_INT_CNTL, 0); 2282 PUT32(sc, RADEON_CAP0_TRIG_CNTL, 0); 2283 PUT32(sc, RADEON_CAP1_TRIG_CNTL, 0); 2284 /* 2285 * Apple OF hands us R3xx radeons with tiling enabled - explicitly 2286 * disable it here 2287 */ 2288 PUT32(sc, RADEON_SURFACE_CNTL, RADEON_SURF_TRANSLATION_DIS); 2289 2290 for (i = 0; i < dp->rd_ncrtcs; i++) 2291 radeonfb_setcrtc(dp, i); 2292 2293 #if 0 2294 /* 2295 * DVO chip voodoo from xf86-video-radeon 2296 * apparently this is needed for some powerbooks with DVI outputs 2297 */ 2298 2299 uint8_t data[5][2] = {{0x8, 0x030}, {0x9, 0}, {0xa, 0x90}, {0xc, 0x89}, {0x8, 0x3b}}; 2300 int n = 0; 2301 iic_acquire_bus(&sc->sc_i2c[0].ric_controller, 0); 2302 for (i = 0; i < 5; i++) 2303 n += iic_exec(&sc->sc_i2c[0].ric_controller, I2C_OP_WRITE, 0x38, data[i], 2, NULL, 0, 0); 2304 iic_release_bus(&sc->sc_i2c[0].ric_controller, 0); 2305 printf("n = %d\n", n); 2306 #endif 2307 2308 /* activate the display */ 2309 radeonfb_blank(dp, 0); 2310 } 2311 2312 void 2313 radeonfb_setcrtc(struct radeonfb_display *dp, int index) 2314 { 2315 int crtc, flags = 0; 2316 struct videomode *mode; 2317 struct radeonfb_softc *sc; 2318 struct radeonfb_crtc *cp; 2319 uint32_t v; 2320 uint32_t gencntl; 2321 uint32_t htotaldisp; 2322 uint32_t hsyncstrt; 2323 uint32_t vtotaldisp; 2324 uint32_t vsyncstrt; 2325 uint32_t fphsyncstrt; 2326 uint32_t fpvsyncstrt; 2327 uint32_t fphtotaldisp; 2328 uint32_t fpvtotaldisp; 2329 uint32_t pitch; 2330 2331 sc = dp->rd_softc; 2332 2333 if ((sc->sc_ports[index].rp_tmds_type == RADEON_TMDS_INT) || 2334 (sc->sc_ports[index].rp_tmds_type == RADEON_TMDS_EXT)) { 2335 flags |= NO_ODD_FBDIV; 2336 } 2337 2338 cp = &dp->rd_crtcs[index]; 2339 crtc = cp->rc_number; 2340 mode = &cp->rc_videomode; 2341 2342 #if 1 2343 pitch = dp->rd_stride / dp->rd_bpp; 2344 #else 2345 pitch = (((sc->sc_maxx * sc->sc_maxbpp) + ((sc->sc_maxbpp * 8) - 1)) / 2346 (sc->sc_maxbpp * 8)); 2347 #endif 2348 switch (crtc) { 2349 case 0: 2350 gencntl = RADEON_CRTC_GEN_CNTL; 2351 htotaldisp = RADEON_CRTC_H_TOTAL_DISP; 2352 hsyncstrt = RADEON_CRTC_H_SYNC_STRT_WID; 2353 vtotaldisp = RADEON_CRTC_V_TOTAL_DISP; 2354 vsyncstrt = RADEON_CRTC_V_SYNC_STRT_WID; 2355 /* should probably leave those alone on non-LVDS */ 2356 fpvsyncstrt = RADEON_FP_V_SYNC_STRT_WID; 2357 fphsyncstrt = RADEON_FP_H_SYNC_STRT_WID; 2358 fpvtotaldisp = RADEON_FP_CRTC_V_TOTAL_DISP; 2359 fphtotaldisp = RADEON_FP_CRTC_H_TOTAL_DISP; 2360 break; 2361 case 1: 2362 gencntl = RADEON_CRTC2_GEN_CNTL; 2363 htotaldisp = RADEON_CRTC2_H_TOTAL_DISP; 2364 hsyncstrt = RADEON_CRTC2_H_SYNC_STRT_WID; 2365 vtotaldisp = RADEON_CRTC2_V_TOTAL_DISP; 2366 vsyncstrt = RADEON_CRTC2_V_SYNC_STRT_WID; 2367 fpvsyncstrt = RADEON_FP_V2_SYNC_STRT_WID; 2368 fphsyncstrt = RADEON_FP_H2_SYNC_STRT_WID; 2369 /* XXX these registers don't seem to exist */ 2370 fpvtotaldisp = 0;//RADEON_FP_CRTC2_V_TOTAL_DISP; 2371 fphtotaldisp = 0;//RADEON_FP_CRTC2_H_TOTAL_DISP; 2372 break; 2373 default: 2374 panic("Bad CRTC!"); 2375 break; 2376 } 2377 2378 /* 2379 * CRTC_GEN_CNTL - depth, accelerator mode, etc. 2380 */ 2381 /* only bother with 32bpp and 8bpp */ 2382 v = dp->rd_format << RADEON_CRTC_PIX_WIDTH_SHIFT; 2383 2384 if (crtc == 1) { 2385 v |= RADEON_CRTC2_CRT2_ON | RADEON_CRTC2_EN; 2386 } else { 2387 v |= RADEON_CRTC_EXT_DISP_EN | RADEON_CRTC_EN; 2388 } 2389 2390 if (mode->flags & VID_DBLSCAN) 2391 v |= RADEON_CRTC2_DBL_SCAN_EN; 2392 2393 if (mode->flags & VID_INTERLACE) 2394 v |= RADEON_CRTC2_INTERLACE_EN; 2395 2396 if (mode->flags & VID_CSYNC) { 2397 v |= RADEON_CRTC2_CSYNC_EN; 2398 if (crtc == 1) 2399 v |= RADEON_CRTC2_VSYNC_TRISTAT; 2400 } 2401 2402 PUT32(sc, gencntl, v); 2403 DPRINTF(("CRTC%s_GEN_CNTL = %08x\n", crtc ? "2" : "", v)); 2404 2405 /* 2406 * CRTC_EXT_CNTL - preserve disable flags, set ATI linear and EXT_CNT 2407 */ 2408 v = GET32(sc, RADEON_CRTC_EXT_CNTL); 2409 if (crtc == 0) { 2410 v &= (RADEON_CRTC_VSYNC_DIS | RADEON_CRTC_HSYNC_DIS | 2411 RADEON_CRTC_DISPLAY_DIS); 2412 v |= RADEON_XCRT_CNT_EN | RADEON_VGA_ATI_LINEAR; 2413 if (mode->flags & VID_CSYNC) 2414 v |= RADEON_CRTC_VSYNC_TRISTAT; 2415 } 2416 /* unconditional turn on CRT, in case first CRTC is DFP */ 2417 v |= RADEON_CRTC_CRT_ON; 2418 PUT32(sc, RADEON_CRTC_EXT_CNTL, v); 2419 PRINTREG(RADEON_CRTC_EXT_CNTL); 2420 2421 /* 2422 * H_TOTAL_DISP 2423 */ 2424 v = ((mode->hdisplay / 8) - 1) << 16; 2425 v |= (mode->htotal / 8) - 1; 2426 PUT32(sc, htotaldisp, v); 2427 DPRINTF(("CRTC%s_H_TOTAL_DISP = %08x\n", crtc ? "2" : "", v)); 2428 if (fphtotaldisp) { 2429 PUT32(sc, fphtotaldisp, v); 2430 DPRINTF(("FP_H%s_TOTAL_DISP = %08x\n", crtc ? "2" : "", v)); 2431 } 2432 /* 2433 * H_SYNC_STRT_WID 2434 */ 2435 v = (((mode->hsync_end - mode->hsync_start) / 8) << 16); 2436 v |= (mode->hsync_start - 8); /* match xf86-video-radeon */ 2437 if (mode->flags & VID_NHSYNC) 2438 v |= RADEON_CRTC_H_SYNC_POL; 2439 PUT32(sc, hsyncstrt, v); 2440 DPRINTF(("CRTC%s_H_SYNC_STRT_WID = %08x\n", crtc ? "2" : "", v)); 2441 if (fphsyncstrt) { 2442 PUT32(sc, fphsyncstrt, v); 2443 DPRINTF(("FP_H%s_SYNC_STRT_WID = %08x\n", crtc ? "2" : "", v)); 2444 } 2445 2446 /* 2447 * V_TOTAL_DISP 2448 */ 2449 v = ((mode->vdisplay - 1) << 16); 2450 v |= (mode->vtotal - 1); 2451 PUT32(sc, vtotaldisp, v); 2452 DPRINTF(("CRTC%s_V_TOTAL_DISP = %08x\n", crtc ? "2" : "", v)); 2453 if (fpvtotaldisp) { 2454 PUT32(sc, fpvtotaldisp, v); 2455 DPRINTF(("FP_V%s_TOTAL_DISP = %08x\n", crtc ? "2" : "", v)); 2456 } 2457 2458 /* 2459 * V_SYNC_STRT_WID 2460 */ 2461 v = ((mode->vsync_end - mode->vsync_start) << 16); 2462 v |= (mode->vsync_start - 1); 2463 if (mode->flags & VID_NVSYNC) 2464 v |= RADEON_CRTC_V_SYNC_POL; 2465 PUT32(sc, vsyncstrt, v); 2466 DPRINTF(("CRTC%s_V_SYNC_STRT_WID = %08x\n", crtc ? "2" : "", v)); 2467 if (fpvsyncstrt) { 2468 PUT32(sc, fpvsyncstrt, v); 2469 DPRINTF(("FP_V%s_SYNC_STRT_WID = %08x\n", crtc ? "2" : "", v)); 2470 } 2471 2472 radeonfb_program_vclk(sc, mode->dot_clock, crtc, flags); 2473 2474 switch (crtc) { 2475 case 0: 2476 PUT32(sc, RADEON_CRTC_OFFSET, 0); 2477 PUT32(sc, RADEON_CRTC_OFFSET_CNTL, 0); 2478 PUT32(sc, RADEON_CRTC_PITCH, pitch); 2479 CLR32(sc, RADEON_DISP_MERGE_CNTL, RADEON_DISP_RGB_OFFSET_EN); 2480 2481 CLR32(sc, RADEON_CRTC_EXT_CNTL, 2482 RADEON_CRTC_VSYNC_DIS | RADEON_CRTC_HSYNC_DIS | 2483 RADEON_CRTC_DISPLAY_DIS /* | RADEON_CRTC_DISP_REQ_EN_B */); 2484 CLR32(sc, RADEON_CRTC_GEN_CNTL, RADEON_CRTC_DISP_REQ_EN_B); 2485 PRINTREG(RADEON_CRTC_EXT_CNTL); 2486 PRINTREG(RADEON_CRTC_GEN_CNTL); 2487 PRINTREG(RADEON_CLOCK_CNTL_INDEX); 2488 break; 2489 2490 case 1: 2491 PUT32(sc, RADEON_CRTC2_OFFSET, 0); 2492 PUT32(sc, RADEON_CRTC2_OFFSET_CNTL, 0); 2493 PUT32(sc, RADEON_CRTC2_PITCH, pitch); 2494 CLR32(sc, RADEON_DISP2_MERGE_CNTL, RADEON_DISP2_RGB_OFFSET_EN); 2495 CLR32(sc, RADEON_CRTC2_GEN_CNTL, 2496 RADEON_CRTC2_VSYNC_DIS | 2497 RADEON_CRTC2_HSYNC_DIS | 2498 RADEON_CRTC2_DISP_DIS | RADEON_CRTC2_DISP_REQ_EN_B); 2499 PRINTREG(RADEON_CRTC2_GEN_CNTL); 2500 break; 2501 } 2502 } 2503 2504 int 2505 radeonfb_isblank(struct radeonfb_display *dp) 2506 { 2507 uint32_t reg, mask; 2508 2509 if(!dp->rd_softc->sc_mapped) 2510 return 1; 2511 2512 if (dp->rd_crtcs[0].rc_number) { 2513 reg = RADEON_CRTC2_GEN_CNTL; 2514 mask = RADEON_CRTC2_DISP_DIS; 2515 } else { 2516 reg = RADEON_CRTC_EXT_CNTL; 2517 mask = RADEON_CRTC_DISPLAY_DIS; 2518 } 2519 return ((GET32(dp->rd_softc, reg) & mask) ? 1 : 0); 2520 } 2521 2522 void 2523 radeonfb_blank(struct radeonfb_display *dp, int blank) 2524 { 2525 struct radeonfb_softc *sc = dp->rd_softc; 2526 uint32_t reg, mask; 2527 uint32_t fpreg, fpval; 2528 int i; 2529 2530 if (!sc->sc_mapped) 2531 return; 2532 2533 for (i = 0; i < dp->rd_ncrtcs; i++) { 2534 2535 if (dp->rd_crtcs[i].rc_number) { 2536 reg = RADEON_CRTC2_GEN_CNTL; 2537 mask = RADEON_CRTC2_DISP_DIS; 2538 fpreg = RADEON_FP2_GEN_CNTL; 2539 fpval = RADEON_FP2_ON; 2540 } else { 2541 reg = RADEON_CRTC_EXT_CNTL; 2542 mask = RADEON_CRTC_DISPLAY_DIS; 2543 fpreg = RADEON_FP_GEN_CNTL; 2544 fpval = RADEON_FP_FPON; 2545 } 2546 2547 if (blank) { 2548 SET32(sc, reg, mask); 2549 CLR32(sc, fpreg, fpval); 2550 } else { 2551 CLR32(sc, reg, mask); 2552 SET32(sc, fpreg, fpval); 2553 } 2554 } 2555 PRINTREG(RADEON_FP_GEN_CNTL); 2556 PRINTREG(RADEON_FP2_GEN_CNTL); 2557 } 2558 2559 void 2560 radeonfb_init_screen(void *cookie, struct vcons_screen *scr, int existing, 2561 long *defattr) 2562 { 2563 struct radeonfb_display *dp = cookie; 2564 struct rasops_info *ri = &scr->scr_ri; 2565 2566 /* initialize font subsystem */ 2567 wsfont_init(); 2568 2569 scr->scr_flags |= VCONS_LOADFONT; 2570 2571 DPRINTF(("init screen called, existing %d\n", existing)); 2572 2573 ri->ri_depth = dp->rd_bpp; 2574 ri->ri_width = dp->rd_virtx; 2575 ri->ri_height = dp->rd_virty; 2576 ri->ri_stride = dp->rd_stride; 2577 ri->ri_flg = RI_CENTER; 2578 switch (ri->ri_depth) { 2579 case 8: 2580 ri->ri_flg |= RI_ENABLE_ALPHA | RI_8BIT_IS_RGB | RI_PREFER_ALPHA; 2581 break; 2582 case 32: 2583 ri->ri_flg |= RI_ENABLE_ALPHA | RI_PREFER_ALPHA; 2584 /* we run radeons in RGB even on SPARC hardware */ 2585 ri->ri_rnum = 8; 2586 ri->ri_gnum = 8; 2587 ri->ri_bnum = 8; 2588 ri->ri_rpos = 16; 2589 ri->ri_gpos = 8; 2590 ri->ri_bpos = 0; 2591 break; 2592 } 2593 2594 ri->ri_bits = (void *)dp->rd_fbptr; 2595 2596 #ifdef VCONS_DRAW_INTR 2597 scr->scr_flags |= VCONS_DONT_READ; 2598 #endif 2599 2600 if (existing) { 2601 ri->ri_flg |= RI_CLEAR; 2602 2603 /* start a modeswitch now */ 2604 radeonfb_modeswitch(dp); 2605 } 2606 2607 /* 2608 * XXX: font selection should be based on properties, with some 2609 * normal/reasonable default. 2610 */ 2611 2612 /* initialize and look for an initial font */ 2613 rasops_init(ri, 0, 0); 2614 ri->ri_caps = WSSCREEN_UNDERLINE | WSSCREEN_HILIT | 2615 WSSCREEN_WSCOLORS | WSSCREEN_REVERSE | WSSCREEN_RESIZE; 2616 2617 rasops_reconfig(ri, dp->rd_virty / ri->ri_font->fontheight, 2618 dp->rd_virtx / ri->ri_font->fontwidth); 2619 2620 /* enable acceleration */ 2621 dp->rd_putchar = ri->ri_ops.putchar; 2622 ri->ri_ops.copyrows = radeonfb_copyrows; 2623 ri->ri_ops.copycols = radeonfb_copycols; 2624 ri->ri_ops.eraserows = radeonfb_eraserows; 2625 ri->ri_ops.erasecols = radeonfb_erasecols; 2626 /* pick a putchar method based on font and Radeon model */ 2627 if (ri->ri_font->stride < ri->ri_font->fontwidth) { 2628 /* got a bitmap font */ 2629 #ifndef RADEONFB_ALWAYS_ACCEL_PUTCHAR 2630 if (IS_R300(dp->rd_softc)) { 2631 /* 2632 * radeonfb_putchar() doesn't work right on some R3xx 2633 * so we use software drawing here, the wrapper just 2634 * makes sure the engine is idle before scribbling 2635 * into vram 2636 */ 2637 ri->ri_ops.putchar = radeonfb_putchar_wrapper; 2638 } else 2639 #endif 2640 ri->ri_ops.putchar = radeonfb_putchar; 2641 } else { 2642 /* got an alpha font */ 2643 switch(ri->ri_depth) { 2644 case 32: 2645 ri->ri_ops.putchar = radeonfb_putchar_aa32; 2646 break; 2647 case 8: 2648 ri->ri_ops.putchar = radeonfb_putchar_aa8; 2649 break; 2650 default: 2651 /* XXX this should never happen */ 2652 panic("%s: depth is not 8 or 32 but we got an" \ 2653 " alpha font?!", __func__); 2654 } 2655 } 2656 ri->ri_ops.cursor = radeonfb_cursor; 2657 } 2658 2659 void 2660 radeonfb_set_fbloc(struct radeonfb_softc *sc) 2661 { 2662 uint32_t gen, ext, gen2 = 0; 2663 uint32_t agploc, aperbase, apersize, mcfbloc; 2664 2665 gen = GET32(sc, RADEON_CRTC_GEN_CNTL); 2666 /* XXX */ 2667 ext = GET32(sc, RADEON_CRTC_EXT_CNTL) & ~RADEON_CRTC_DISPLAY_DIS; 2668 agploc = GET32(sc, RADEON_MC_AGP_LOCATION); 2669 aperbase = GET32(sc, RADEON_CONFIG_APER_0_BASE); 2670 apersize = GET32(sc, RADEON_CONFIG_APER_SIZE); 2671 2672 PUT32(sc, RADEON_CRTC_GEN_CNTL, gen | RADEON_CRTC_DISP_REQ_EN_B); 2673 PUT32(sc, RADEON_CRTC_EXT_CNTL, ext | RADEON_CRTC_DISPLAY_DIS); 2674 #if 0 2675 PUT32(sc, RADEON_CRTC_GEN_CNTL, gen | RADEON_CRTC_DISPLAY_DIS); 2676 PUT32(sc, RADEON_CRTC_EXT_CNTL, ext | RADEON_CRTC_DISP_REQ_EN_B); 2677 #endif 2678 2679 if (HAS_CRTC2(sc)) { 2680 gen2 = GET32(sc, RADEON_CRTC2_GEN_CNTL); 2681 PUT32(sc, RADEON_CRTC2_GEN_CNTL, 2682 gen2 | RADEON_CRTC2_DISP_REQ_EN_B); 2683 } 2684 2685 delay(100000); 2686 2687 mcfbloc = (aperbase >> 16) | 2688 ((aperbase + (apersize - 1)) & 0xffff0000); 2689 2690 sc->sc_aperbase = (mcfbloc & 0xffff) << 16; 2691 sc->sc_memsz = apersize; 2692 2693 if (((agploc & 0xffff) << 16) != 2694 ((mcfbloc & 0xffff0000U) + 0x10000)) { 2695 agploc = mcfbloc & 0xffff0000U; 2696 agploc |= ((agploc + 0x10000) >> 16); 2697 } 2698 2699 PUT32(sc, RADEON_HOST_PATH_CNTL, 0); 2700 2701 PUT32(sc, RADEON_MC_FB_LOCATION, mcfbloc); 2702 PUT32(sc, RADEON_MC_AGP_LOCATION, agploc); 2703 2704 DPRINTF(("aperbase = %u\n", aperbase)); 2705 PRINTREG(RADEON_MC_FB_LOCATION); 2706 PRINTREG(RADEON_MC_AGP_LOCATION); 2707 2708 PUT32(sc, RADEON_DISPLAY_BASE_ADDR, sc->sc_aperbase); 2709 2710 if (HAS_CRTC2(sc)) 2711 PUT32(sc, RADEON_DISPLAY2_BASE_ADDR, sc->sc_aperbase); 2712 2713 PUT32(sc, RADEON_OV0_BASE_ADDR, sc->sc_aperbase); 2714 2715 #if 0 2716 /* XXX: what is this AGP garbage? :-) */ 2717 PUT32(sc, RADEON_AGP_CNTL, 0x00100000); 2718 #endif 2719 2720 delay(100000); 2721 2722 PUT32(sc, RADEON_CRTC_GEN_CNTL, gen); 2723 PUT32(sc, RADEON_CRTC_EXT_CNTL, ext); 2724 2725 if (HAS_CRTC2(sc)) 2726 PUT32(sc, RADEON_CRTC2_GEN_CNTL, gen2); 2727 } 2728 2729 void 2730 radeonfb_init_misc(struct radeonfb_softc *sc) 2731 { 2732 PUT32(sc, RADEON_BUS_CNTL, 2733 RADEON_BUS_MASTER_DIS | 2734 RADEON_BUS_PREFETCH_MODE_ACT | 2735 RADEON_BUS_PCI_READ_RETRY_EN | 2736 RADEON_BUS_PCI_WRT_RETRY_EN | 2737 (3 << RADEON_BUS_RETRY_WS_SHIFT) | 2738 RADEON_BUS_MSTR_RD_MULT | 2739 RADEON_BUS_MSTR_RD_LINE | 2740 RADEON_BUS_RD_DISCARD_EN | 2741 RADEON_BUS_MSTR_DISCONNECT_EN | 2742 RADEON_BUS_READ_BURST); 2743 2744 PUT32(sc, RADEON_BUS_CNTL1, 0xf0); 2745 /* PUT32(sc, RADEON_SEPROM_CNTL1, 0x09ff0000); */ 2746 PUT32(sc, RADEON_FCP_CNTL, RADEON_FCP0_SRC_GND); 2747 PUT32(sc, RADEON_RBBM_CNTL, 2748 (3 << RADEON_RB_SETTLE_SHIFT) | 2749 (4 << RADEON_ABORTCLKS_HI_SHIFT) | 2750 (4 << RADEON_ABORTCLKS_CP_SHIFT) | 2751 (4 << RADEON_ABORTCLKS_CFIFO_SHIFT)); 2752 2753 /* XXX: figure out what these mean! */ 2754 PUT32(sc, RADEON_AGP_CNTL, 0x00100000); 2755 PUT32(sc, RADEON_HOST_PATH_CNTL, 0); 2756 #if 0 2757 PUT32(sc, RADEON_DISP_MISC_CNTL, 0x5bb00400); 2758 #endif 2759 2760 PUT32(sc, RADEON_GEN_INT_CNTL, 0); 2761 PUT32(sc, RADEON_GEN_INT_STATUS, GET32(sc, RADEON_GEN_INT_STATUS)); 2762 } 2763 2764 static void 2765 radeonfb_putpal(struct radeonfb_display *dp, int idx, int r, int g, int b) 2766 { 2767 struct radeonfb_softc *sc = dp->rd_softc; 2768 int crtc, cc; 2769 uint32_t vclk; 2770 2771 vclk = GETPLL(sc, RADEON_VCLK_ECP_CNTL); 2772 PUTPLL(sc, RADEON_VCLK_ECP_CNTL, vclk & ~RADEON_PIXCLK_DAC_ALWAYS_ONb); 2773 2774 /* initialize the palette for every CRTC used by this display */ 2775 for (cc = 0; cc < dp->rd_ncrtcs; cc++) { 2776 crtc = dp->rd_crtcs[cc].rc_number; 2777 2778 if (crtc) 2779 SET32(sc, RADEON_DAC_CNTL2, RADEON_DAC2_PALETTE_ACC_CTL); 2780 else 2781 CLR32(sc, RADEON_DAC_CNTL2, RADEON_DAC2_PALETTE_ACC_CTL); 2782 2783 PUT32(sc, RADEON_PALETTE_INDEX, idx); 2784 PUT32(sc, RADEON_PALETTE_30_DATA, 2785 (r << 22) | (g << 12) | (b << 2)); 2786 } 2787 2788 PUTPLL(sc, RADEON_VCLK_ECP_CNTL, vclk); 2789 } 2790 2791 /* 2792 * This loads a linear color map for true color. 2793 */ 2794 void 2795 radeonfb_init_palette(struct radeonfb_display *dp) 2796 { 2797 int i; 2798 2799 #define DAC_WIDTH ((1 << 10) - 1) 2800 #define CLUT_WIDTH ((1 << 8) - 1) 2801 #define CLUT_COLOR(i) ((i * DAC_WIDTH * 2 / CLUT_WIDTH + 1) / 2) 2802 2803 if (dp->rd_bpp == 8) { 2804 2805 /* R3G3B2 palette */ 2806 uint32_t tmp, r, g, b; 2807 2808 for (i = 0; i <= CLUT_WIDTH; ++i) { 2809 tmp = i & 0xe0; 2810 2811 /* 2812 * replicate bits so 0xe0 maps to a red value of 0xff 2813 * in order to make white look actually white 2814 */ 2815 tmp |= (tmp >> 3) | (tmp >> 6); 2816 r = tmp; 2817 2818 tmp = (i & 0x1c) << 3; 2819 tmp |= (tmp >> 3) | (tmp >> 6); 2820 g = tmp; 2821 2822 tmp = (i & 0x03) << 6; 2823 tmp |= tmp >> 2; 2824 tmp |= tmp >> 4; 2825 b = tmp; 2826 2827 radeonfb_putpal(dp, i, r, g, b); 2828 } 2829 } else { 2830 /* linear ramp */ 2831 for (i = 0; i <= CLUT_WIDTH; ++i) { 2832 radeonfb_putpal(dp, i, i, i, i); 2833 } 2834 } 2835 } 2836 2837 static int 2838 radeonfb_putcmap(struct radeonfb_display *dp, struct wsdisplay_cmap *cm) 2839 { 2840 u_char *r, *g, *b; 2841 u_int index = cm->index; 2842 u_int count = cm->count; 2843 int i, error; 2844 u_char rbuf[256], gbuf[256], bbuf[256]; 2845 2846 #ifdef GENFB_DEBUG 2847 aprint_debug("putcmap: %d %d\n",index, count); 2848 #endif 2849 if (index >= 256 || count > 256 - index) 2850 return EINVAL; 2851 error = copyin(cm->red, &rbuf[index], count); 2852 if (error) 2853 return error; 2854 error = copyin(cm->green, &gbuf[index], count); 2855 if (error) 2856 return error; 2857 error = copyin(cm->blue, &bbuf[index], count); 2858 if (error) 2859 return error; 2860 2861 memcpy(&dp->rd_cmap_red[index], &rbuf[index], count); 2862 memcpy(&dp->rd_cmap_green[index], &gbuf[index], count); 2863 memcpy(&dp->rd_cmap_blue[index], &bbuf[index], count); 2864 2865 r = &dp->rd_cmap_red[index]; 2866 g = &dp->rd_cmap_green[index]; 2867 b = &dp->rd_cmap_blue[index]; 2868 2869 for (i = 0; i < count; i++) { 2870 radeonfb_putpal(dp, index, *r, *g, *b); 2871 index++; 2872 r++, g++, b++; 2873 } 2874 return 0; 2875 } 2876 2877 static int 2878 radeonfb_getcmap(struct radeonfb_display *dp, struct wsdisplay_cmap *cm) 2879 { 2880 u_int index = cm->index; 2881 u_int count = cm->count; 2882 int error; 2883 2884 if (index >= 256 || count > 256 - index) 2885 return EINVAL; 2886 2887 error = copyout(&dp->rd_cmap_red[index], cm->red, count); 2888 if (error) 2889 return error; 2890 error = copyout(&dp->rd_cmap_green[index], cm->green, count); 2891 if (error) 2892 return error; 2893 error = copyout(&dp->rd_cmap_blue[index], cm->blue, count); 2894 if (error) 2895 return error; 2896 2897 return 0; 2898 } 2899 2900 /* 2901 * Bugs in some R300 hardware requires this when accessing CLOCK_CNTL_INDEX. 2902 */ 2903 void 2904 radeonfb_r300cg_workaround(struct radeonfb_softc *sc) 2905 { 2906 uint32_t tmp, save; 2907 2908 save = GET32(sc, RADEON_CLOCK_CNTL_INDEX); 2909 tmp = save & ~(0x3f | RADEON_PLL_WR_EN); 2910 PUT32(sc, RADEON_CLOCK_CNTL_INDEX, tmp); 2911 tmp = GET32(sc, RADEON_CLOCK_CNTL_DATA); 2912 PUT32(sc, RADEON_CLOCK_CNTL_INDEX, save); 2913 } 2914 2915 /* 2916 * Acceleration entry points. 2917 */ 2918 2919 /* this one draws characters using bitmap fonts */ 2920 static void 2921 radeonfb_putchar(void *cookie, int row, int col, u_int c, long attr) 2922 { 2923 struct rasops_info *ri = cookie; 2924 struct vcons_screen *scr = ri->ri_hw; 2925 struct radeonfb_display *dp = scr->scr_cookie; 2926 struct radeonfb_softc *sc = dp->rd_softc; 2927 struct wsdisplay_font *font = PICK_FONT(ri, c); 2928 uint32_t w, h; 2929 int xd, yd, offset, i; 2930 uint32_t bg, fg, gmc; 2931 uint32_t reg; 2932 uint8_t *data8; 2933 uint16_t *data16; 2934 uint32_t *data32; 2935 void *data; 2936 2937 if (dp->rd_wsmode != WSDISPLAYIO_MODE_EMUL) 2938 return; 2939 2940 if (!CHAR_IN_FONT(c, font)) 2941 return; 2942 2943 w = font->fontwidth; 2944 h = font->fontheight; 2945 2946 bg = ri->ri_devcmap[(attr >> 16) & 0xf]; 2947 fg = ri->ri_devcmap[(attr >> 24) & 0xf]; 2948 2949 xd = ri->ri_xorigin + col * w; 2950 yd = ri->ri_yorigin + row * h; 2951 2952 if (c == 0x20) { 2953 radeonfb_rectfill(dp, xd, yd, w, h, bg); 2954 return; 2955 } 2956 data = WSFONT_GLYPH(c, font); 2957 2958 gmc = dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT; 2959 2960 radeonfb_wait_fifo(sc, 9); 2961 2962 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 2963 RADEON_GMC_BRUSH_NONE | 2964 RADEON_GMC_SRC_DATATYPE_MONO_FG_BG | 2965 RADEON_GMC_DST_CLIPPING | 2966 RADEON_ROP3_S | 2967 RADEON_DP_SRC_SOURCE_HOST_DATA | 2968 RADEON_GMC_CLR_CMP_CNTL_DIS | 2969 RADEON_GMC_WR_MSK_DIS | 2970 gmc); 2971 2972 PUT32(sc, RADEON_SC_LEFT, xd); 2973 PUT32(sc, RADEON_SC_RIGHT, xd + w); 2974 PUT32(sc, RADEON_DP_SRC_FRGD_CLR, fg); 2975 PUT32(sc, RADEON_DP_SRC_BKGD_CLR, bg); 2976 PUT32(sc, RADEON_DP_CNTL, 2977 RADEON_DST_X_LEFT_TO_RIGHT | 2978 RADEON_DST_Y_TOP_TO_BOTTOM); 2979 2980 PUT32(sc, RADEON_SRC_X_Y, 0); 2981 offset = 32 - (font->stride << 3); 2982 PUT32(sc, RADEON_DST_X_Y, ((xd - offset) << 16) | yd); 2983 PUT32(sc, RADEON_DST_WIDTH_HEIGHT, (32 << 16) | h); 2984 2985 radeonfb_wait_fifo(sc, h); 2986 switch (font->stride) { 2987 case 1: { 2988 data8 = data; 2989 for (i = 0; i < h; i++) { 2990 reg = *data8; 2991 #if BYTE_ORDER == LITTLE_ENDIAN 2992 reg = reg << 24; 2993 #endif 2994 bus_space_write_stream_4(sc->sc_regt, 2995 sc->sc_regh, RADEON_HOST_DATA0, reg); 2996 data8++; 2997 } 2998 break; 2999 } 3000 case 2: { 3001 data16 = data; 3002 for (i = 0; i < h; i++) { 3003 reg = *data16; 3004 #if BYTE_ORDER == LITTLE_ENDIAN 3005 reg = reg << 16; 3006 #endif 3007 bus_space_write_stream_4(sc->sc_regt, 3008 sc->sc_regh, RADEON_HOST_DATA0, reg); 3009 data16++; 3010 } 3011 break; 3012 } 3013 case 4: { 3014 data32 = data; 3015 for (i = 0; i < h; i++) { 3016 reg = *data32; 3017 bus_space_write_stream_4(sc->sc_regt, 3018 sc->sc_regh, RADEON_HOST_DATA0, reg); 3019 data32++; 3020 } 3021 break; 3022 } 3023 } 3024 if (attr & 1) 3025 radeonfb_rectfill(dp, xd, yd + h - 2, w, 1, fg); 3026 } 3027 3028 /* ... while this one is for anti-aliased ones */ 3029 static void 3030 radeonfb_putchar_aa32(void *cookie, int row, int col, u_int c, long attr) 3031 { 3032 struct rasops_info *ri = cookie; 3033 struct vcons_screen *scr = ri->ri_hw; 3034 struct radeonfb_display *dp = scr->scr_cookie; 3035 struct radeonfb_softc *sc = dp->rd_softc; 3036 struct wsdisplay_font *font = PICK_FONT(ri, c); 3037 uint32_t bg, fg, gmc; 3038 uint8_t *data; 3039 int w, h, xd, yd; 3040 int i, r, g, b, aval; 3041 int rf, gf, bf, rb, gb, bb; 3042 uint32_t pixel; 3043 int rv; 3044 3045 if (dp->rd_wsmode != WSDISPLAYIO_MODE_EMUL) 3046 return; 3047 3048 if (!CHAR_IN_FONT(c, font)) 3049 return; 3050 3051 w = font->fontwidth; 3052 h = font->fontheight; 3053 3054 bg = ri->ri_devcmap[(attr >> 16) & 0xf]; 3055 fg = ri->ri_devcmap[(attr >> 24) & 0xf]; 3056 3057 xd = ri->ri_xorigin + col * w; 3058 yd = ri->ri_yorigin + row * h; 3059 3060 if (c == 0x20) { 3061 radeonfb_rectfill(dp, xd, yd, w, h, bg); 3062 if (attr & 1) 3063 radeonfb_rectfill(dp, xd, yd + h - 2, w, 1, fg); 3064 return; 3065 } 3066 rv = glyphcache_try(&dp->rd_gc, c, xd, yd, attr); 3067 if (rv == GC_OK) 3068 return; 3069 3070 data = WSFONT_GLYPH(c, font); 3071 3072 gmc = dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT; 3073 3074 radeonfb_wait_fifo(sc, 5); 3075 3076 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 3077 RADEON_GMC_BRUSH_NONE | 3078 RADEON_GMC_SRC_DATATYPE_COLOR | 3079 RADEON_ROP3_S | 3080 RADEON_DP_SRC_SOURCE_HOST_DATA | 3081 RADEON_GMC_CLR_CMP_CNTL_DIS | 3082 RADEON_GMC_WR_MSK_DIS | 3083 gmc); 3084 3085 PUT32(sc, RADEON_DP_CNTL, 3086 RADEON_DST_X_LEFT_TO_RIGHT | 3087 RADEON_DST_Y_TOP_TO_BOTTOM); 3088 3089 PUT32(sc, RADEON_SRC_X_Y, 0); 3090 PUT32(sc, RADEON_DST_X_Y, (xd << 16) | yd); 3091 PUT32(sc, RADEON_DST_WIDTH_HEIGHT, (w << 16) | h); 3092 3093 rf = (fg >> 16) & 0xff; 3094 rb = (bg >> 16) & 0xff; 3095 gf = (fg >> 8) & 0xff; 3096 gb = (bg >> 8) & 0xff; 3097 bf = fg & 0xff; 3098 bb = bg & 0xff; 3099 3100 /* 3101 * I doubt we can upload data faster than even the slowest Radeon 3102 * could process them, especially when doing the alpha blending stuff 3103 * along the way, so just make sure there's some room in the FIFO and 3104 * then hammer away 3105 * As it turns out we can, so make periodic stops to let the FIFO 3106 * drain. 3107 */ 3108 radeonfb_wait_fifo(sc, 20); 3109 for (i = 0; i < ri->ri_fontscale; i++) { 3110 aval = *data; 3111 data++; 3112 if (aval == 0) { 3113 pixel = bg; 3114 } else if (aval == 255) { 3115 pixel = fg; 3116 } else { 3117 r = aval * rf + (255 - aval) * rb; 3118 g = aval * gf + (255 - aval) * gb; 3119 b = aval * bf + (255 - aval) * bb; 3120 pixel = (r & 0xff00) << 8 | 3121 (g & 0xff00) | 3122 (b & 0xff00) >> 8; 3123 } 3124 if (i & 16) 3125 radeonfb_wait_fifo(sc, 20); 3126 PUT32(sc, RADEON_HOST_DATA0, pixel); 3127 } 3128 if (rv == GC_ADD) { 3129 glyphcache_add(&dp->rd_gc, c, xd, yd); 3130 } else if (attr & 1) 3131 radeonfb_rectfill(dp, xd, yd + h - 2, w, 1, fg); 3132 } 3133 3134 static void 3135 radeonfb_putchar_aa8(void *cookie, int row, int col, u_int c, long attr) 3136 { 3137 struct rasops_info *ri = cookie; 3138 struct vcons_screen *scr = ri->ri_hw; 3139 struct radeonfb_display *dp = scr->scr_cookie; 3140 struct radeonfb_softc *sc = dp->rd_softc; 3141 struct wsdisplay_font *font = PICK_FONT(ri, c); 3142 uint32_t bg, fg, latch = 0, bg8, fg8, pixel, gmc; 3143 int i, x, y, wi, he, r, g, b, aval; 3144 int r1, g1, b1, r0, g0, b0, fgo, bgo; 3145 uint8_t *data8; 3146 int rv, cnt; 3147 3148 if (dp->rd_wsmode != WSDISPLAYIO_MODE_EMUL) 3149 return; 3150 3151 if (!CHAR_IN_FONT(c, font)) 3152 return; 3153 3154 wi = font->fontwidth; 3155 he = font->fontheight; 3156 3157 bg = ri->ri_devcmap[(attr >> 16) & 0xf]; 3158 fg = ri->ri_devcmap[(attr >> 24) & 0xf]; 3159 3160 x = ri->ri_xorigin + col * wi; 3161 y = ri->ri_yorigin + row * he; 3162 3163 if (c == 0x20) { 3164 radeonfb_rectfill(dp, x, y, wi, he, bg); 3165 if (attr & 1) 3166 radeonfb_rectfill(dp, x, y + he - 2, wi, 1, fg); 3167 return; 3168 } 3169 rv = glyphcache_try(&dp->rd_gc, c, x, y, attr); 3170 if (rv == GC_OK) 3171 return; 3172 3173 data8 = WSFONT_GLYPH(c, font); 3174 3175 gmc = dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT; 3176 3177 radeonfb_wait_fifo(sc, 5); 3178 3179 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 3180 RADEON_GMC_BRUSH_NONE | 3181 RADEON_GMC_SRC_DATATYPE_COLOR | 3182 RADEON_ROP3_S | 3183 RADEON_DP_SRC_SOURCE_HOST_DATA | 3184 RADEON_GMC_CLR_CMP_CNTL_DIS | 3185 RADEON_GMC_WR_MSK_DIS | 3186 gmc); 3187 3188 PUT32(sc, RADEON_DP_CNTL, 3189 RADEON_DST_X_LEFT_TO_RIGHT | 3190 RADEON_DST_Y_TOP_TO_BOTTOM); 3191 3192 PUT32(sc, RADEON_SRC_X_Y, 0); 3193 PUT32(sc, RADEON_DST_X_Y, (x << 16) | y); 3194 PUT32(sc, RADEON_DST_WIDTH_HEIGHT, (wi << 16) | he); 3195 3196 /* 3197 * we need the RGB colours here, so get offsets into rasops_cmap 3198 */ 3199 fgo = ((attr >> 24) & 0xf) * 3; 3200 bgo = ((attr >> 16) & 0xf) * 3; 3201 3202 r0 = rasops_cmap[bgo]; 3203 r1 = rasops_cmap[fgo]; 3204 g0 = rasops_cmap[bgo + 1]; 3205 g1 = rasops_cmap[fgo + 1]; 3206 b0 = rasops_cmap[bgo + 2]; 3207 b1 = rasops_cmap[fgo + 2]; 3208 #define R3G3B2(r, g, b) ((r & 0xe0) | ((g >> 3) & 0x1c) | (b >> 6)) 3209 bg8 = R3G3B2(r0, g0, b0); 3210 fg8 = R3G3B2(r1, g1, b1); 3211 3212 radeonfb_wait_fifo(sc, 20); 3213 cnt = 0; 3214 for (i = 0; i < ri->ri_fontscale; i++) { 3215 aval = *data8; 3216 if (aval == 0) { 3217 pixel = bg8; 3218 } else if (aval == 255) { 3219 pixel = fg8; 3220 } else { 3221 r = aval * r1 + (255 - aval) * r0; 3222 g = aval * g1 + (255 - aval) * g0; 3223 b = aval * b1 + (255 - aval) * b0; 3224 pixel = ((r & 0xe000) >> 8) | 3225 ((g & 0xe000) >> 11) | 3226 ((b & 0xc000) >> 14); 3227 } 3228 latch |= pixel << (8 * (i & 3)); 3229 /* write in 32bit chunks */ 3230 if ((i & 3) == 3) { 3231 PUT32(sc, RADEON_HOST_DATA0, latch); 3232 /* 3233 * not strictly necessary, old data should be shifted 3234 * out 3235 */ 3236 latch = 0; 3237 cnt++; 3238 if (cnt > 16) { 3239 cnt = 0; 3240 radeonfb_wait_fifo(sc, 20); 3241 } 3242 } 3243 data8++; 3244 } 3245 /* if we have pixels left in latch write them out */ 3246 if ((i & 3) != 0) { 3247 /* 3248 * radeon is weird - apparently leftover pixels are written 3249 * from the middle, not from the left as everything else 3250 */ 3251 PUT32(sc, RADEON_HOST_DATA0, latch); 3252 } 3253 3254 if (rv == GC_ADD) { 3255 glyphcache_add(&dp->rd_gc, c, x, y); 3256 } else 3257 if (attr & 1) 3258 radeonfb_rectfill(dp, x, y + he - 2, wi, 1, fg); 3259 } 3260 3261 /* 3262 * wrapper for software character drawing 3263 * just sync the engine and call rasops*_putchar() 3264 */ 3265 3266 #ifndef RADEONFB_ALWAYS_ACCEL_PUTCHAR 3267 static void 3268 radeonfb_putchar_wrapper(void *cookie, int row, int col, u_int c, long attr) 3269 { 3270 struct rasops_info *ri = cookie; 3271 struct vcons_screen *scr = ri->ri_hw; 3272 struct radeonfb_display *dp = scr->scr_cookie; 3273 3274 radeonfb_engine_idle(dp->rd_softc); 3275 dp->rd_putchar(ri, row, col, c, attr); 3276 } 3277 #endif 3278 3279 static void 3280 radeonfb_eraserows(void *cookie, int row, int nrows, long fillattr) 3281 { 3282 struct rasops_info *ri = cookie; 3283 struct vcons_screen *scr = ri->ri_hw; 3284 struct radeonfb_display *dp = scr->scr_cookie; 3285 uint32_t x, y, w, h, fg, bg, ul; 3286 3287 /* XXX: check for full emulation mode? */ 3288 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 3289 x = ri->ri_xorigin; 3290 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 3291 w = ri->ri_emuwidth; 3292 h = ri->ri_font->fontheight * nrows; 3293 3294 rasops_unpack_attr(fillattr, &fg, &bg, &ul); 3295 radeonfb_rectfill(dp, x, y, w, h, ri->ri_devcmap[bg & 0xf]); 3296 } 3297 } 3298 3299 static void 3300 radeonfb_copyrows(void *cookie, int srcrow, int dstrow, int nrows) 3301 { 3302 struct rasops_info *ri = cookie; 3303 struct vcons_screen *scr = ri->ri_hw; 3304 struct radeonfb_display *dp = scr->scr_cookie; 3305 uint32_t x, ys, yd, w, h; 3306 3307 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 3308 x = ri->ri_xorigin; 3309 ys = ri->ri_yorigin + ri->ri_font->fontheight * srcrow; 3310 yd = ri->ri_yorigin + ri->ri_font->fontheight * dstrow; 3311 w = ri->ri_emuwidth; 3312 h = ri->ri_font->fontheight * nrows; 3313 radeonfb_bitblt(dp, x, ys, x, yd, w, h, 3314 RADEON_ROP3_S); 3315 } 3316 } 3317 3318 static void 3319 radeonfb_copycols(void *cookie, int row, int srccol, int dstcol, int ncols) 3320 { 3321 struct rasops_info *ri = cookie; 3322 struct vcons_screen *scr = ri->ri_hw; 3323 struct radeonfb_display *dp = scr->scr_cookie; 3324 uint32_t xs, xd, y, w, h; 3325 3326 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 3327 xs = ri->ri_xorigin + ri->ri_font->fontwidth * srccol; 3328 xd = ri->ri_xorigin + ri->ri_font->fontwidth * dstcol; 3329 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 3330 w = ri->ri_font->fontwidth * ncols; 3331 h = ri->ri_font->fontheight; 3332 radeonfb_bitblt(dp, xs, y, xd, y, w, h, 3333 RADEON_ROP3_S); 3334 } 3335 } 3336 3337 static void 3338 radeonfb_erasecols(void *cookie, int row, int startcol, int ncols, 3339 long fillattr) 3340 { 3341 struct rasops_info *ri = cookie; 3342 struct vcons_screen *scr = ri->ri_hw; 3343 struct radeonfb_display *dp = scr->scr_cookie; 3344 uint32_t x, y, w, h, fg, bg, ul; 3345 3346 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 3347 x = ri->ri_xorigin + ri->ri_font->fontwidth * startcol; 3348 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 3349 w = ri->ri_font->fontwidth * ncols; 3350 h = ri->ri_font->fontheight; 3351 3352 rasops_unpack_attr(fillattr, &fg, &bg, &ul); 3353 radeonfb_rectfill(dp, x, y, w, h, ri->ri_devcmap[bg & 0xf]); 3354 } 3355 } 3356 3357 static void 3358 radeonfb_cursor(void *cookie, int on, int row, int col) 3359 { 3360 struct rasops_info *ri = cookie; 3361 struct vcons_screen *scr = ri->ri_hw; 3362 struct radeonfb_display *dp = scr->scr_cookie; 3363 int x, y, wi, he; 3364 3365 wi = ri->ri_font->fontwidth; 3366 he = ri->ri_font->fontheight; 3367 3368 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 3369 x = ri->ri_ccol * wi + ri->ri_xorigin; 3370 y = ri->ri_crow * he + ri->ri_yorigin; 3371 /* first turn off the old cursor */ 3372 if (ri->ri_flg & RI_CURSOR) { 3373 radeonfb_bitblt(dp, x, y, x, y, wi, he, 3374 RADEON_ROP3_Dn); 3375 ri->ri_flg &= ~RI_CURSOR; 3376 } 3377 ri->ri_crow = row; 3378 ri->ri_ccol = col; 3379 /* then (possibly) turn on the new one */ 3380 if (on) { 3381 x = ri->ri_ccol * wi + ri->ri_xorigin; 3382 y = ri->ri_crow * he + ri->ri_yorigin; 3383 radeonfb_bitblt(dp, x, y, x, y, wi, he, 3384 RADEON_ROP3_Dn); 3385 ri->ri_flg |= RI_CURSOR; 3386 } 3387 } else { 3388 scr->scr_ri.ri_crow = row; 3389 scr->scr_ri.ri_ccol = col; 3390 scr->scr_ri.ri_flg &= ~RI_CURSOR; 3391 } 3392 } 3393 3394 /* 3395 * Underlying acceleration support. 3396 */ 3397 3398 static void 3399 radeonfb_rectfill(struct radeonfb_display *dp, int dstx, int dsty, 3400 int width, int height, uint32_t color) 3401 { 3402 struct radeonfb_softc *sc = dp->rd_softc; 3403 uint32_t gmc; 3404 3405 gmc = dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT; 3406 3407 radeonfb_wait_fifo(sc, 6); 3408 3409 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 3410 RADEON_GMC_BRUSH_SOLID_COLOR | 3411 RADEON_GMC_SRC_DATATYPE_COLOR | 3412 RADEON_GMC_CLR_CMP_CNTL_DIS | 3413 RADEON_ROP3_P | gmc); 3414 3415 PUT32(sc, RADEON_DP_BRUSH_FRGD_CLR, color); 3416 PUT32(sc, RADEON_DP_WRITE_MASK, 0xffffffff); 3417 PUT32(sc, RADEON_DP_CNTL, 3418 RADEON_DST_X_LEFT_TO_RIGHT | 3419 RADEON_DST_Y_TOP_TO_BOTTOM); 3420 PUT32(sc, RADEON_DST_Y_X, (dsty << 16) | dstx); 3421 PUT32(sc, RADEON_DST_WIDTH_HEIGHT, (width << 16) | (height)); 3422 } 3423 3424 static void 3425 radeonfb_rectfill_a(void *cookie, int dstx, int dsty, 3426 int width, int height, long attr) 3427 { 3428 struct radeonfb_display *dp = cookie; 3429 3430 radeonfb_rectfill(dp, dstx, dsty, width, height, 3431 dp->rd_vscreen.scr_ri.ri_devcmap[(attr >> 24 & 0xf)]); 3432 } 3433 3434 static void 3435 radeonfb_bitblt(void *cookie, int srcx, int srcy, 3436 int dstx, int dsty, int width, int height, int rop) 3437 { 3438 struct radeonfb_display *dp = cookie; 3439 struct radeonfb_softc *sc = dp->rd_softc; 3440 uint32_t gmc; 3441 uint32_t dir; 3442 3443 if (dsty < srcy) { 3444 dir = RADEON_DST_Y_TOP_TO_BOTTOM; 3445 } else { 3446 srcy += height - 1; 3447 dsty += height - 1; 3448 dir = 0; 3449 } 3450 if (dstx < srcx) { 3451 dir |= RADEON_DST_X_LEFT_TO_RIGHT; 3452 } else { 3453 srcx += width - 1; 3454 dstx += width - 1; 3455 } 3456 3457 gmc = dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT; 3458 3459 radeonfb_wait_fifo(sc, 6); 3460 3461 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 3462 RADEON_GMC_BRUSH_SOLID_COLOR | 3463 RADEON_GMC_SRC_DATATYPE_COLOR | 3464 RADEON_GMC_CLR_CMP_CNTL_DIS | 3465 RADEON_DP_SRC_SOURCE_MEMORY | 3466 rop | gmc); 3467 3468 PUT32(sc, RADEON_DP_WRITE_MASK, 0xffffffff); 3469 PUT32(sc, RADEON_DP_CNTL, dir); 3470 PUT32(sc, RADEON_SRC_Y_X, (srcy << 16) | srcx); 3471 PUT32(sc, RADEON_DST_Y_X, (dsty << 16) | dstx); 3472 PUT32(sc, RADEON_DST_WIDTH_HEIGHT, (width << 16) | (height)); 3473 } 3474 3475 static void 3476 radeonfb_engine_idle(struct radeonfb_softc *sc) 3477 { 3478 3479 radeonfb_wait_fifo(sc, 64); 3480 while ((GET32(sc, RADEON_RBBM_STATUS) & 3481 RADEON_RBBM_ACTIVE) != 0); 3482 radeonfb_engine_flush(sc); 3483 } 3484 3485 static inline void 3486 radeonfb_wait_fifo(struct radeonfb_softc *sc, int n) 3487 { 3488 int i; 3489 3490 for (i = RADEON_TIMEOUT; i; i--) { 3491 if ((GET32(sc, RADEON_RBBM_STATUS) & 3492 RADEON_RBBM_FIFOCNT_MASK) >= n) 3493 return; 3494 } 3495 #ifdef DIAGNOSTIC 3496 if (!i) 3497 printf("%s: timed out waiting for fifo (%x)\n", 3498 XNAME(sc), GET32(sc, RADEON_RBBM_STATUS)); 3499 #endif 3500 } 3501 3502 static void 3503 radeonfb_engine_flush(struct radeonfb_softc *sc) 3504 { 3505 int i = 0; 3506 3507 if (IS_R300(sc)) { 3508 SET32(sc, R300_DSTCACHE_CTLSTAT, R300_RB2D_DC_FLUSH_ALL); 3509 while (GET32(sc, R300_DSTCACHE_CTLSTAT) & R300_RB2D_DC_BUSY) { 3510 i++; 3511 } 3512 } else { 3513 SET32(sc, RADEON_RB2D_DSTCACHE_CTLSTAT, 3514 RADEON_RB2D_DC_FLUSH_ALL); 3515 while (GET32(sc, RADEON_RB2D_DSTCACHE_CTLSTAT) & 3516 RADEON_RB2D_DC_BUSY) { 3517 i++; 3518 } 3519 } 3520 #ifdef DIAGNOSTIC 3521 if (i > RADEON_TIMEOUT) 3522 printf("%s: engine flush timed out!\n", XNAME(sc)); 3523 #endif 3524 } 3525 3526 static inline void 3527 radeonfb_unclip(struct radeonfb_softc *sc) 3528 { 3529 3530 radeonfb_wait_fifo(sc, 2); 3531 PUT32(sc, RADEON_SC_TOP_LEFT, 0); 3532 PUT32(sc, RADEON_SC_BOTTOM_RIGHT, 0x1fff1fff); 3533 } 3534 3535 static void 3536 radeonfb_engine_init(struct radeonfb_display *dp) 3537 { 3538 struct radeonfb_softc *sc = dp->rd_softc; 3539 uint32_t pitch; 3540 3541 /* no 3D */ 3542 PUT32(sc, RADEON_RB3D_CNTL, 0); 3543 3544 radeonfb_engine_reset(sc); 3545 pitch = ((dp->rd_virtx * (dp->rd_bpp / 8) + 0x3f)) >> 6; 3546 3547 radeonfb_wait_fifo(sc, 1); 3548 if (!IS_R300(sc)) 3549 PUT32(sc, RADEON_RB2D_DSTCACHE_MODE, 0); 3550 3551 radeonfb_wait_fifo(sc, 3); 3552 PUT32(sc, RADEON_DEFAULT_PITCH_OFFSET, 3553 (pitch << 22) | (sc->sc_aperbase >> 10)); 3554 3555 3556 PUT32(sc, RADEON_DST_PITCH_OFFSET, 3557 (pitch << 22) | (sc->sc_aperbase >> 10)); 3558 PUT32(sc, RADEON_SRC_PITCH_OFFSET, 3559 (pitch << 22) | (sc->sc_aperbase >> 10)); 3560 3561 (void)GET32(sc, RADEON_DP_DATATYPE); 3562 3563 /* default scissors -- no clipping */ 3564 radeonfb_wait_fifo(sc, 1); 3565 PUT32(sc, RADEON_DEFAULT_SC_BOTTOM_RIGHT, 3566 RADEON_DEFAULT_SC_RIGHT_MAX | RADEON_DEFAULT_SC_BOTTOM_MAX); 3567 3568 radeonfb_wait_fifo(sc, 1); 3569 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 3570 (dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT) | 3571 RADEON_GMC_CLR_CMP_CNTL_DIS | 3572 RADEON_GMC_BRUSH_SOLID_COLOR | 3573 RADEON_GMC_SRC_DATATYPE_COLOR); 3574 3575 radeonfb_wait_fifo(sc, 10); 3576 PUT32(sc, RADEON_DST_LINE_START, 0); 3577 PUT32(sc, RADEON_DST_LINE_END, 0); 3578 PUT32(sc, RADEON_DP_BRUSH_FRGD_CLR, 0xffffffff); 3579 PUT32(sc, RADEON_DP_BRUSH_BKGD_CLR, 0); 3580 PUT32(sc, RADEON_DP_SRC_FRGD_CLR, 0xffffffff); 3581 PUT32(sc, RADEON_DP_SRC_BKGD_CLR, 0); 3582 PUT32(sc, RADEON_DP_WRITE_MASK, 0xffffffff); 3583 PUT32(sc, RADEON_SC_TOP_LEFT, 0); 3584 PUT32(sc, RADEON_SC_BOTTOM_RIGHT, 0x1fff1fff); 3585 PUT32(sc, RADEON_AUX_SC_CNTL, 0); 3586 radeonfb_engine_idle(sc); 3587 } 3588 3589 static void 3590 radeonfb_engine_reset(struct radeonfb_softc *sc) 3591 { 3592 uint32_t hpc, rbbm, mclkcntl, clkindex; 3593 3594 radeonfb_engine_flush(sc); 3595 3596 clkindex = GET32(sc, RADEON_CLOCK_CNTL_INDEX); 3597 if (HAS_R300CG(sc)) 3598 radeonfb_r300cg_workaround(sc); 3599 mclkcntl = GETPLL(sc, RADEON_MCLK_CNTL); 3600 3601 /* 3602 * According to comments in XFree code, resetting the HDP via 3603 * the RBBM_SOFT_RESET can cause bad behavior on some systems. 3604 * So we use HOST_PATH_CNTL instead. 3605 */ 3606 3607 hpc = GET32(sc, RADEON_HOST_PATH_CNTL); 3608 rbbm = GET32(sc, RADEON_RBBM_SOFT_RESET); 3609 if (IS_R300(sc)) { 3610 PUT32(sc, RADEON_RBBM_SOFT_RESET, rbbm | 3611 RADEON_SOFT_RESET_CP | 3612 RADEON_SOFT_RESET_HI | 3613 RADEON_SOFT_RESET_E2); 3614 GET32(sc, RADEON_RBBM_SOFT_RESET); 3615 PUT32(sc, RADEON_RBBM_SOFT_RESET, 0); 3616 /* 3617 * XXX: this bit is not defined in any ATI docs I have, 3618 * nor in the XFree code, but XFree does it. Why? 3619 */ 3620 SET32(sc, RADEON_RB2D_DSTCACHE_MODE, (1<<17)); 3621 } else { 3622 PUT32(sc, RADEON_RBBM_SOFT_RESET, rbbm | 3623 RADEON_SOFT_RESET_CP | 3624 RADEON_SOFT_RESET_SE | 3625 RADEON_SOFT_RESET_RE | 3626 RADEON_SOFT_RESET_PP | 3627 RADEON_SOFT_RESET_E2 | 3628 RADEON_SOFT_RESET_RB); 3629 GET32(sc, RADEON_RBBM_SOFT_RESET); 3630 PUT32(sc, RADEON_RBBM_SOFT_RESET, rbbm & 3631 ~(RADEON_SOFT_RESET_CP | 3632 RADEON_SOFT_RESET_SE | 3633 RADEON_SOFT_RESET_RE | 3634 RADEON_SOFT_RESET_PP | 3635 RADEON_SOFT_RESET_E2 | 3636 RADEON_SOFT_RESET_RB)); 3637 GET32(sc, RADEON_RBBM_SOFT_RESET); 3638 } 3639 3640 PUT32(sc, RADEON_HOST_PATH_CNTL, hpc | RADEON_HDP_SOFT_RESET); 3641 GET32(sc, RADEON_HOST_PATH_CNTL); 3642 PUT32(sc, RADEON_HOST_PATH_CNTL, hpc); 3643 3644 if (IS_R300(sc)) 3645 PUT32(sc, RADEON_RBBM_SOFT_RESET, rbbm); 3646 3647 PUT32(sc, RADEON_CLOCK_CNTL_INDEX, clkindex); 3648 PRINTREG(RADEON_CLOCK_CNTL_INDEX); 3649 PUTPLL(sc, RADEON_MCLK_CNTL, mclkcntl); 3650 3651 if (HAS_R300CG(sc)) 3652 radeonfb_r300cg_workaround(sc); 3653 } 3654 3655 static int 3656 radeonfb_set_curpos(struct radeonfb_display *dp, struct wsdisplay_curpos *pos) 3657 { 3658 int x, y; 3659 3660 x = pos->x; 3661 y = pos->y; 3662 3663 /* 3664 * This doesn't let a cursor move off the screen. I'm not 3665 * sure if this will have negative effects for e.g. Xinerama. 3666 * I'd guess Xinerama handles it by changing the cursor shape, 3667 * but that needs verification. 3668 */ 3669 if (x >= dp->rd_virtx) 3670 x = dp->rd_virtx - 1; 3671 if (x < 0) 3672 x = 0; 3673 if (y >= dp->rd_virty) 3674 y = dp->rd_virty - 1; 3675 if (y < 0) 3676 y = 0; 3677 3678 dp->rd_cursor.rc_pos.x = x; 3679 dp->rd_cursor.rc_pos.y = y; 3680 3681 radeonfb_cursor_position(dp); 3682 return 0; 3683 } 3684 3685 static int 3686 radeonfb_set_cursor(struct radeonfb_display *dp, struct wsdisplay_cursor *wc) 3687 { 3688 unsigned flags; 3689 3690 uint8_t r[2], g[2], b[2]; 3691 unsigned index, count; 3692 int i, err; 3693 int pitch, size; 3694 struct radeonfb_cursor nc; 3695 3696 flags = wc->which; 3697 3698 /* copy old values */ 3699 nc = dp->rd_cursor; 3700 3701 if (flags & WSDISPLAY_CURSOR_DOCMAP) { 3702 index = wc->cmap.index; 3703 count = wc->cmap.count; 3704 3705 if (index >= 2 || count > 2 - index) 3706 return EINVAL; 3707 3708 err = copyin(wc->cmap.red, &r[index], count); 3709 if (err) 3710 return err; 3711 err = copyin(wc->cmap.green, &g[index], count); 3712 if (err) 3713 return err; 3714 err = copyin(wc->cmap.blue, &b[index], count); 3715 if (err) 3716 return err; 3717 3718 for (i = index; i < index + count; i++) { 3719 nc.rc_cmap[i] = 3720 (r[i] << 16) + (g[i] << 8) + (b[i] << 0); 3721 } 3722 } 3723 3724 if (flags & WSDISPLAY_CURSOR_DOSHAPE) { 3725 if ((wc->size.x > RADEON_CURSORMAXX) || 3726 (wc->size.y > RADEON_CURSORMAXY)) 3727 return EINVAL; 3728 3729 /* figure bytes per line */ 3730 pitch = (wc->size.x + 7) / 8; 3731 size = pitch * wc->size.y; 3732 3733 /* clear the old cursor and mask */ 3734 memset(nc.rc_image, 0, 512); 3735 memset(nc.rc_mask, 0, 512); 3736 3737 nc.rc_size = wc->size; 3738 3739 if ((err = copyin(wc->image, nc.rc_image, size)) != 0) 3740 return err; 3741 3742 if ((err = copyin(wc->mask, nc.rc_mask, size)) != 0) 3743 return err; 3744 } 3745 3746 if (flags & WSDISPLAY_CURSOR_DOHOT) { 3747 nc.rc_hot = wc->hot; 3748 if (nc.rc_hot.x >= nc.rc_size.x) 3749 nc.rc_hot.x = nc.rc_size.x - 1; 3750 if (nc.rc_hot.y >= nc.rc_size.y) 3751 nc.rc_hot.y = nc.rc_size.y - 1; 3752 } 3753 3754 if (flags & WSDISPLAY_CURSOR_DOPOS) { 3755 nc.rc_pos = wc->pos; 3756 if (nc.rc_pos.x >= dp->rd_virtx) 3757 nc.rc_pos.x = dp->rd_virtx - 1; 3758 #if 0 3759 if (nc.rc_pos.x < 0) 3760 nc.rc_pos.x = 0; 3761 #endif 3762 if (nc.rc_pos.y >= dp->rd_virty) 3763 nc.rc_pos.y = dp->rd_virty - 1; 3764 #if 0 3765 if (nc.rc_pos.y < 0) 3766 nc.rc_pos.y = 0; 3767 #endif 3768 } 3769 if (flags & WSDISPLAY_CURSOR_DOCUR) { 3770 nc.rc_visible = wc->enable; 3771 } 3772 3773 dp->rd_cursor = nc; 3774 radeonfb_cursor_update(dp, wc->which); 3775 3776 return 0; 3777 } 3778 3779 static uint8_t 3780 radeonfb_backwards(uint8_t d) 3781 { 3782 uint8_t l; 3783 3784 l = d << 7; 3785 l |= ((d & 0x02) << 5); 3786 l |= ((d & 0x04) << 3); 3787 l |= ((d & 0x08) << 1); 3788 l |= ((d & 0x10) >> 1); 3789 l |= ((d & 0x20) >> 3); 3790 l |= ((d & 0x40) >> 5); 3791 l |= ((d & 0x80) >> 7); 3792 return l; 3793 } 3794 3795 /* 3796 * Change the cursor shape. Call this with the cursor locked to avoid 3797 * flickering/tearing. 3798 */ 3799 static void 3800 radeonfb_cursor_shape(struct radeonfb_display *dp) 3801 { 3802 uint8_t and[512], xor[512]; 3803 int i, j, src, dst /* , pitch */; 3804 const uint8_t *msk = dp->rd_cursor.rc_mask; 3805 const uint8_t *img = dp->rd_cursor.rc_image; 3806 3807 /* 3808 * Radeon cursor data interleaves one line of AND data followed 3809 * by a line of XOR data. (Each line corresponds to a whole hardware 3810 * pitch - i.e. 64 pixels or 8 bytes.) 3811 * 3812 * The cursor is displayed using the following table: 3813 * 3814 * AND XOR Result 3815 * ---------------------- 3816 * 0 0 Cursor color 0 3817 * 0 1 Cursor color 1 3818 * 1 0 Transparent 3819 * 1 1 Complement of background 3820 * 3821 * Our masks are therefore different from what we were passed. 3822 * Passed in, I'm assuming the data represents either color 0 or 1, 3823 * and a mask, so the passed in table looks like: 3824 * 3825 * IMG Mask Result 3826 * ----------------------- 3827 * 0 0 Transparent 3828 * 0 1 Cursor color 0 3829 * 1 0 Transparent 3830 * 1 1 Cursor color 1 3831 * 3832 * IF mask bit == 1, AND = 0, XOR = color. 3833 * IF mask bit == 0, AND = 1, XOR = 0. 3834 * 3835 * hence: AND = ~(mask); XOR = color & ~(mask); 3836 */ 3837 3838 /* pitch = ((dp->rd_cursor.rc_size.x + 7) / 8); */ 3839 3840 /* start by assuming all bits are transparent */ 3841 memset(and, 0xff, 512); 3842 memset(xor, 0x00, 512); 3843 3844 src = 0; 3845 dst = 0; 3846 for (i = 0; i < 64; i++) { 3847 for (j = 0; j < 64; j += 8) { 3848 if ((i < dp->rd_cursor.rc_size.y) && 3849 (j < dp->rd_cursor.rc_size.x)) { 3850 3851 /* take care to leave odd bits alone */ 3852 and[dst] &= ~(msk[src]); 3853 xor[dst] = img[src] & msk[src]; 3854 src++; 3855 } 3856 dst++; 3857 } 3858 } 3859 3860 for (i = 0; i < 512; i++) { 3861 and[i] = radeonfb_backwards(and[i]); 3862 xor[i] = radeonfb_backwards(xor[i]); 3863 } 3864 3865 /* copy the image into place */ 3866 for (i = 0; i < 64; i++) { 3867 memcpy((uint8_t *)dp->rd_curptr + (i * 16), 3868 &and[i * 8], 8); 3869 memcpy((uint8_t *)dp->rd_curptr + (i * 16) + 8, 3870 &xor[i * 8], 8); 3871 } 3872 } 3873 3874 static void 3875 radeonfb_cursor_position(struct radeonfb_display *dp) 3876 { 3877 struct radeonfb_softc *sc = dp->rd_softc; 3878 uint32_t offset, hvoff, hvpos; /* registers */ 3879 uint32_t coff; /* cursor offset */ 3880 int i, x, y, xoff, yoff, crtcoff; 3881 3882 /* 3883 * XXX: this also needs to handle pan/scan 3884 */ 3885 for (i = 0; i < dp->rd_ncrtcs; i++) { 3886 3887 struct radeonfb_crtc *rcp = &dp->rd_crtcs[i]; 3888 3889 if (rcp->rc_number) { 3890 offset = RADEON_CUR2_OFFSET; 3891 hvoff = RADEON_CUR2_HORZ_VERT_OFF; 3892 hvpos = RADEON_CUR2_HORZ_VERT_POSN; 3893 crtcoff = RADEON_CRTC2_OFFSET; 3894 } else { 3895 offset = RADEON_CUR_OFFSET; 3896 hvoff = RADEON_CUR_HORZ_VERT_OFF; 3897 hvpos = RADEON_CUR_HORZ_VERT_POSN; 3898 crtcoff = RADEON_CRTC_OFFSET; 3899 } 3900 3901 x = dp->rd_cursor.rc_pos.x; 3902 y = dp->rd_cursor.rc_pos.y; 3903 3904 while (y < rcp->rc_yoffset) { 3905 rcp->rc_yoffset -= RADEON_PANINCREMENT; 3906 } 3907 while (y >= (rcp->rc_yoffset + rcp->rc_videomode.vdisplay)) { 3908 rcp->rc_yoffset += RADEON_PANINCREMENT; 3909 } 3910 while (x < rcp->rc_xoffset) { 3911 rcp->rc_xoffset -= RADEON_PANINCREMENT; 3912 } 3913 while (x >= (rcp->rc_xoffset + rcp->rc_videomode.hdisplay)) { 3914 rcp->rc_xoffset += RADEON_PANINCREMENT; 3915 } 3916 3917 /* adjust for the cursor's hotspot */ 3918 x -= dp->rd_cursor.rc_hot.x; 3919 y -= dp->rd_cursor.rc_hot.y; 3920 xoff = yoff = 0; 3921 3922 if (x >= dp->rd_virtx) 3923 x = dp->rd_virtx - 1; 3924 if (y >= dp->rd_virty) 3925 y = dp->rd_virty - 1; 3926 3927 /* now adjust cursor so it is relative to viewport */ 3928 x -= rcp->rc_xoffset; 3929 y -= rcp->rc_yoffset; 3930 3931 /* 3932 * no need to check for fall off, because we should 3933 * never move off the screen entirely! 3934 */ 3935 coff = 0; 3936 if (x < 0) { 3937 xoff = -x; 3938 x = 0; 3939 } 3940 if (y < 0) { 3941 yoff = -y; 3942 y = 0; 3943 coff = (yoff * 2) * 8; 3944 } 3945 3946 /* pan the display */ 3947 PUT32(sc, crtcoff, (rcp->rc_yoffset * dp->rd_stride) + 3948 rcp->rc_xoffset); 3949 3950 PUT32(sc, offset, (dp->rd_curoff + coff) | RADEON_CUR_LOCK); 3951 PUT32(sc, hvoff, (xoff << 16) | (yoff) | RADEON_CUR_LOCK); 3952 /* NB: this unlocks the cursor */ 3953 PUT32(sc, hvpos, (x << 16) | y); 3954 } 3955 } 3956 3957 static void 3958 radeonfb_cursor_visible(struct radeonfb_display *dp) 3959 { 3960 int i; 3961 uint32_t gencntl, bit; 3962 3963 for (i = 0; i < dp->rd_ncrtcs; i++) { 3964 if (dp->rd_crtcs[i].rc_number) { 3965 gencntl = RADEON_CRTC2_GEN_CNTL; 3966 bit = RADEON_CRTC2_CUR_EN; 3967 } else { 3968 gencntl = RADEON_CRTC_GEN_CNTL; 3969 bit = RADEON_CRTC_CUR_EN; 3970 } 3971 3972 if (dp->rd_cursor.rc_visible) 3973 SET32(dp->rd_softc, gencntl, bit); 3974 else 3975 CLR32(dp->rd_softc, gencntl, bit); 3976 } 3977 } 3978 3979 static void 3980 radeonfb_cursor_cmap(struct radeonfb_display *dp) 3981 { 3982 int i; 3983 uint32_t c0reg, c1reg; 3984 struct radeonfb_softc *sc = dp->rd_softc; 3985 3986 for (i = 0; i < dp->rd_ncrtcs; i++) { 3987 if (dp->rd_crtcs[i].rc_number) { 3988 c0reg = RADEON_CUR2_CLR0; 3989 c1reg = RADEON_CUR2_CLR1; 3990 } else { 3991 c0reg = RADEON_CUR_CLR0; 3992 c1reg = RADEON_CUR_CLR1; 3993 } 3994 3995 PUT32(sc, c0reg, dp->rd_cursor.rc_cmap[0]); 3996 PUT32(sc, c1reg, dp->rd_cursor.rc_cmap[1]); 3997 } 3998 } 3999 4000 static void 4001 radeonfb_cursor_update(struct radeonfb_display *dp, unsigned which) 4002 { 4003 struct radeonfb_softc *sc; 4004 int i; 4005 4006 sc = dp->rd_softc; 4007 for (i = 0; i < dp->rd_ncrtcs; i++) { 4008 if (dp->rd_crtcs[i].rc_number) { 4009 SET32(sc, RADEON_CUR2_OFFSET, RADEON_CUR_LOCK); 4010 } else { 4011 SET32(sc, RADEON_CUR_OFFSET,RADEON_CUR_LOCK); 4012 } 4013 } 4014 4015 if (which & WSDISPLAY_CURSOR_DOCMAP) 4016 radeonfb_cursor_cmap(dp); 4017 4018 if (which & WSDISPLAY_CURSOR_DOSHAPE) 4019 radeonfb_cursor_shape(dp); 4020 4021 if (which & WSDISPLAY_CURSOR_DOCUR) 4022 radeonfb_cursor_visible(dp); 4023 4024 /* this one is unconditional, because it updates other stuff */ 4025 radeonfb_cursor_position(dp); 4026 } 4027 4028 static struct videomode * 4029 radeonfb_best_refresh(struct videomode *m1, struct videomode *m2) 4030 { 4031 int r1, r2; 4032 4033 /* otherwise pick the higher refresh rate */ 4034 r1 = DIVIDE(DIVIDE(m1->dot_clock, m1->htotal), m1->vtotal); 4035 r2 = DIVIDE(DIVIDE(m2->dot_clock, m2->htotal), m2->vtotal); 4036 4037 return (r1 < r2 ? m2 : m1); 4038 } 4039 4040 static const struct videomode * 4041 radeonfb_port_mode(struct radeonfb_softc *sc, struct radeonfb_port *rp, 4042 int x, int y) 4043 { 4044 struct edid_info *ep = &rp->rp_edid; 4045 struct videomode *vmp = NULL; 4046 int i; 4047 4048 if (!rp->rp_edid_valid) { 4049 /* fallback to safe mode */ 4050 return radeonfb_modelookup(sc->sc_defaultmode); 4051 } 4052 4053 /* always choose the preferred mode first! */ 4054 if (ep->edid_preferred_mode) { 4055 4056 /* XXX: add auto-stretching support for native mode */ 4057 4058 /* this may want panning to occur, btw */ 4059 if ((ep->edid_preferred_mode->hdisplay <= x) && 4060 (ep->edid_preferred_mode->vdisplay <= y)) 4061 return ep->edid_preferred_mode; 4062 } 4063 4064 for (i = 0; i < ep->edid_nmodes; i++) { 4065 /* 4066 * We elect to pick a resolution that is too large for 4067 * the monitor than one that is too small. This means 4068 * that we will prefer to pan rather than to try to 4069 * center a smaller display on a larger screen. In 4070 * practice, this shouldn't matter because if a 4071 * monitor can support a larger resolution, it can 4072 * probably also support the smaller. A specific 4073 * exception is fixed format panels, but hopefully 4074 * they are properly dealt with by the "autostretch" 4075 * logic above. 4076 */ 4077 if ((ep->edid_modes[i].hdisplay > x) || 4078 (ep->edid_modes[i].vdisplay > y)) { 4079 continue; 4080 } 4081 4082 /* 4083 * at this point, the display mode is no larger than 4084 * what we've requested. 4085 */ 4086 if (vmp == NULL) 4087 vmp = &ep->edid_modes[i]; 4088 4089 /* eliminate smaller modes */ 4090 if ((vmp->hdisplay >= ep->edid_modes[i].hdisplay) || 4091 (vmp->vdisplay >= ep->edid_modes[i].vdisplay)) 4092 continue; 4093 4094 if ((vmp->hdisplay < ep->edid_modes[i].hdisplay) || 4095 (vmp->vdisplay < ep->edid_modes[i].vdisplay)) { 4096 vmp = &ep->edid_modes[i]; 4097 continue; 4098 } 4099 4100 KASSERT(vmp->hdisplay == ep->edid_modes[i].hdisplay); 4101 KASSERT(vmp->vdisplay == ep->edid_modes[i].vdisplay); 4102 4103 vmp = radeonfb_best_refresh(vmp, &ep->edid_modes[i]); 4104 } 4105 4106 return (vmp ? vmp : radeonfb_modelookup(sc->sc_defaultmode)); 4107 } 4108 4109 static int 4110 radeonfb_hasres(struct videomode *list, int nlist, int x, int y) 4111 { 4112 int i; 4113 4114 for (i = 0; i < nlist; i++) { 4115 if ((x == list[i].hdisplay) && 4116 (y == list[i].vdisplay)) { 4117 return 1; 4118 } 4119 } 4120 return 0; 4121 } 4122 4123 static void 4124 radeonfb_pickres(struct radeonfb_display *dp, uint16_t *x, uint16_t *y, 4125 int pan) 4126 { 4127 struct radeonfb_port *rp; 4128 struct edid_info *ep; 4129 int i, j; 4130 4131 *x = 0; 4132 *y = 0; 4133 4134 if (pan) { 4135 for (i = 0; i < dp->rd_ncrtcs; i++) { 4136 rp = dp->rd_crtcs[i].rc_port; 4137 ep = &rp->rp_edid; 4138 if (!rp->rp_edid_valid) { 4139 /* monitor not present */ 4140 continue; 4141 } 4142 4143 /* 4144 * For now we are ignoring "conflict" that 4145 * could occur when mixing some modes like 4146 * 1280x1024 and 1400x800. It isn't clear 4147 * which is better, so the first one wins. 4148 */ 4149 for (j = 0; j < ep->edid_nmodes; j++) { 4150 /* 4151 * ignore resolutions that are too big for 4152 * the radeon 4153 */ 4154 if (ep->edid_modes[j].hdisplay > 4155 dp->rd_softc->sc_maxx) 4156 continue; 4157 if (ep->edid_modes[j].vdisplay > 4158 dp->rd_softc->sc_maxy) 4159 continue; 4160 4161 /* 4162 * pick largest resolution, the 4163 * smaller monitor will pan 4164 */ 4165 if ((ep->edid_modes[j].hdisplay >= *x) && 4166 (ep->edid_modes[j].vdisplay >= *y)) { 4167 *x = ep->edid_modes[j].hdisplay; 4168 *y = ep->edid_modes[j].vdisplay; 4169 } 4170 } 4171 } 4172 4173 } else { 4174 struct videomode modes[64]; 4175 int nmodes = 0; 4176 int valid = 0; 4177 4178 for (i = 0; i < dp->rd_ncrtcs; i++) { 4179 /* 4180 * pick the largest resolution in common. 4181 */ 4182 rp = dp->rd_crtcs[i].rc_port; 4183 ep = &rp->rp_edid; 4184 4185 if (!rp->rp_edid_valid) 4186 continue; 4187 4188 if (!valid) { 4189 /* 4190 * Pick the preferred mode for this port 4191 * if available. 4192 */ 4193 if (ep->edid_preferred_mode) { 4194 struct videomode *vmp = 4195 ep->edid_preferred_mode; 4196 4197 if ((vmp->hdisplay <= 4198 dp->rd_softc->sc_maxx) && 4199 (vmp->vdisplay <= 4200 dp->rd_softc->sc_maxy)) 4201 modes[nmodes++] = *vmp; 4202 } else { 4203 4204 /* initialize starting list */ 4205 for (j = 0; j < ep->edid_nmodes; j++) { 4206 /* 4207 * ignore resolutions that are 4208 * too big for the radeon 4209 */ 4210 if (ep->edid_modes[j].hdisplay > 4211 dp->rd_softc->sc_maxx) 4212 continue; 4213 if (ep->edid_modes[j].vdisplay > 4214 dp->rd_softc->sc_maxy) 4215 continue; 4216 4217 modes[nmodes] = 4218 ep->edid_modes[j]; 4219 nmodes++; 4220 } 4221 } 4222 valid = 1; 4223 } else { 4224 /* merge into preexisting list */ 4225 for (j = 0; j < nmodes; j++) { 4226 if (!radeonfb_hasres(ep->edid_modes, 4227 ep->edid_nmodes, 4228 modes[j].hdisplay, 4229 modes[j].vdisplay)) { 4230 modes[j] = modes[nmodes]; 4231 j--; 4232 nmodes--; 4233 } 4234 } 4235 } 4236 } 4237 4238 /* now we have to pick from the merged list */ 4239 for (i = 0; i < nmodes; i++) { 4240 if ((modes[i].hdisplay >= *x) && 4241 (modes[i].vdisplay >= *y)) { 4242 *x = modes[i].hdisplay; 4243 *y = modes[i].vdisplay; 4244 } 4245 } 4246 } 4247 4248 if ((*x == 0) || (*y == 0)) { 4249 /* fallback to safe mode */ 4250 *x = 640; 4251 *y = 480; 4252 } 4253 } 4254 4255 /* 4256 * backlight levels are linear on: 4257 * - RV200, RV250, RV280, RV350 4258 * - but NOT on PowerBook4,3 6,3 6,5 4259 * according to Linux' radeonfb 4260 */ 4261 4262 /* Get the current backlight level for the display. */ 4263 4264 static int 4265 radeonfb_get_backlight(struct radeonfb_display *dp) 4266 { 4267 int s; 4268 uint32_t level; 4269 4270 s = spltty(); 4271 4272 level = radeonfb_get32(dp->rd_softc, RADEON_LVDS_GEN_CNTL); 4273 level &= RADEON_LVDS_BL_MOD_LEV_MASK; 4274 level >>= RADEON_LVDS_BL_MOD_LEV_SHIFT; 4275 4276 /* 4277 * On some chips, we should negate the backlight level. 4278 * XXX Find out on which chips. 4279 */ 4280 if (dp->rd_softc->sc_flags & RFB_INV_BLIGHT) 4281 level = RADEONFB_BACKLIGHT_MAX - level; 4282 4283 splx(s); 4284 4285 return level; 4286 } 4287 4288 /* Set the backlight to the given level for the display. */ 4289 static void 4290 radeonfb_switch_backlight(struct radeonfb_display *dp, int on) 4291 { 4292 if (dp->rd_bl_on == on) 4293 return; 4294 dp->rd_bl_on = on; 4295 radeonfb_set_backlight(dp, dp->rd_bl_level); 4296 } 4297 4298 static int 4299 radeonfb_set_backlight(struct radeonfb_display *dp, int level) 4300 { 4301 struct radeonfb_softc *sc = dp->rd_softc; 4302 int rlevel, s; 4303 uint32_t lvds; 4304 4305 if(!sc->sc_mapped) 4306 return 0; 4307 4308 s = spltty(); 4309 4310 dp->rd_bl_level = level; 4311 if (dp->rd_bl_on == 0) 4312 level = 0; 4313 4314 if (level < 0) 4315 level = 0; 4316 else if (level >= RADEONFB_BACKLIGHT_MAX) 4317 level = RADEONFB_BACKLIGHT_MAX; 4318 4319 /* On some chips, we should negate the backlight level. */ 4320 if (dp->rd_softc->sc_flags & RFB_INV_BLIGHT) { 4321 rlevel = RADEONFB_BACKLIGHT_MAX - level; 4322 } else 4323 rlevel = level; 4324 4325 callout_stop(&dp->rd_bl_lvds_co); 4326 radeonfb_engine_idle(sc); 4327 4328 /* 4329 * Turn off the display if the backlight is set to 0, since the 4330 * display is useless without backlight anyway. 4331 */ 4332 if (level == 0) 4333 radeonfb_blank(dp, 1); 4334 else if (radeonfb_get_backlight(dp) == 0) 4335 radeonfb_blank(dp, 0); 4336 4337 lvds = radeonfb_get32(sc, RADEON_LVDS_GEN_CNTL); 4338 lvds &= ~RADEON_LVDS_DISPLAY_DIS; 4339 if (!(lvds & RADEON_LVDS_BLON) || !(lvds & RADEON_LVDS_ON)) { 4340 lvds |= dp->rd_bl_lvds_val & RADEON_LVDS_DIGON; 4341 lvds |= RADEON_LVDS_BLON | RADEON_LVDS_EN; 4342 radeonfb_put32(sc, RADEON_LVDS_GEN_CNTL, lvds); 4343 lvds &= ~RADEON_LVDS_BL_MOD_LEV_MASK; 4344 lvds |= rlevel << RADEON_LVDS_BL_MOD_LEV_SHIFT; 4345 lvds |= RADEON_LVDS_ON; 4346 lvds |= dp->rd_bl_lvds_val & RADEON_LVDS_BL_MOD_EN; 4347 } else { 4348 lvds &= ~RADEON_LVDS_BL_MOD_LEV_MASK; 4349 lvds |= rlevel << RADEON_LVDS_BL_MOD_LEV_SHIFT; 4350 radeonfb_put32(sc, RADEON_LVDS_GEN_CNTL, lvds); 4351 } 4352 4353 dp->rd_bl_lvds_val &= ~RADEON_LVDS_STATE_MASK; 4354 dp->rd_bl_lvds_val |= lvds & RADEON_LVDS_STATE_MASK; 4355 /* XXX What is the correct delay? */ 4356 callout_schedule(&dp->rd_bl_lvds_co, 200 * hz); 4357 4358 splx(s); 4359 4360 return 0; 4361 } 4362 4363 /* 4364 * Callout function for delayed operations on the LVDS_GEN_CNTL register. 4365 * Set the delayed bits in the register, and clear the stored delayed 4366 * value. 4367 */ 4368 4369 static void radeonfb_lvds_callout(void *arg) 4370 { 4371 struct radeonfb_display *dp = arg; 4372 int s; 4373 4374 s = splhigh(); 4375 4376 radeonfb_mask32(dp->rd_softc, RADEON_LVDS_GEN_CNTL, ~0, 4377 dp->rd_bl_lvds_val); 4378 dp->rd_bl_lvds_val = 0; 4379 4380 splx(s); 4381 } 4382 4383 static void 4384 radeonfb_brightness_up(device_t dev) 4385 { 4386 struct radeonfb_softc *sc = device_private(dev); 4387 struct radeonfb_display *dp = &sc->sc_displays[0]; 4388 int level; 4389 4390 /* we assume the main display is the first one - need a better way */ 4391 if (sc->sc_ndisplays < 1) return; 4392 /* make sure pushing the hotkeys always has an effect */ 4393 dp->rd_bl_on = 1; 4394 level = dp->rd_bl_level; 4395 level = uimin(RADEONFB_BACKLIGHT_MAX, level + 5); 4396 radeonfb_set_backlight(dp, level); 4397 } 4398 4399 static void 4400 radeonfb_brightness_down(device_t dev) 4401 { 4402 struct radeonfb_softc *sc = device_private(dev); 4403 struct radeonfb_display *dp = &sc->sc_displays[0]; 4404 int level; 4405 4406 /* we assume the main display is the first one - need a better way */ 4407 if (sc->sc_ndisplays < 1) return; 4408 /* make sure pushing the hotkeys always has an effect */ 4409 dp->rd_bl_on = 1; 4410 level = dp->rd_bl_level; 4411 level = uimax(0, level - 5); 4412 radeonfb_set_backlight(dp, level); 4413 } 4414
Indexes created Thu Sep 25 16:09:42 GMT 2025