radeonfb.c revision 1.110
1 /* $NetBSD: radeonfb.c,v 1.110 2020/09/28 05:43:58 macallan Exp $ */ 2 3 /*- 4 * Copyright (c) 2006 Itronix Inc. 5 * All rights reserved. 6 * 7 * Written by Garrett D'Amore for Itronix Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. The name of Itronix Inc. may not be used to endorse 18 * or promote products derived from this software without specific 19 * prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY ITRONIX INC. ``AS IS'' AND ANY EXPRESS 22 * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 23 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL ITRONIX INC. BE LIABLE FOR ANY 25 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE 27 * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 29 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 30 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 31 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * ATI Technologies Inc. ("ATI") has not assisted in the creation of, and 36 * does not endorse, this software. ATI will not be responsible or liable 37 * for any actual or alleged damage or loss caused by or in connection with 38 * the use of or reliance on this software. 39 */ 40 41 /* 42 * Portions of this code were taken from XFree86's Radeon driver, which bears 43 * this notice: 44 * 45 * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and 46 * VA Linux Systems Inc., Fremont, California. 47 * 48 * All Rights Reserved. 49 * 50 * Permission is hereby granted, free of charge, to any person obtaining 51 * a copy of this software and associated documentation files (the 52 * "Software"), to deal in the Software without restriction, including 53 * without limitation on the rights to use, copy, modify, merge, 54 * publish, distribute, sublicense, and/or sell copies of the Software, 55 * and to permit persons to whom the Software is furnished to do so, 56 * subject to the following conditions: 57 * 58 * The above copyright notice and this permission notice (including the 59 * next paragraph) shall be included in all copies or substantial 60 * portions of the Software. 61 * 62 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 63 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 64 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 65 * NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR 66 * THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 67 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 68 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 69 * DEALINGS IN THE SOFTWARE. 70 */ 71 72 #include <sys/cdefs.h> 73 __KERNEL_RCSID(0, "$NetBSD: radeonfb.c,v 1.110 2020/09/28 05:43:58 macallan Exp $"); 74 75 #include <sys/param.h> 76 #include <sys/systm.h> 77 #include <sys/device.h> 78 #include <sys/malloc.h> 79 #include <sys/bus.h> 80 #include <sys/kernel.h> 81 #include <sys/lwp.h> 82 #include <sys/kauth.h> 83 #include <sys/kmem.h> 84 85 #include <dev/wscons/wsdisplayvar.h> 86 #include <dev/wscons/wsconsio.h> 87 #include <dev/wsfont/wsfont.h> 88 #include <dev/rasops/rasops.h> 89 #include <dev/videomode/videomode.h> 90 #include <dev/videomode/edidvar.h> 91 #include <dev/wscons/wsdisplay_vconsvar.h> 92 #include <dev/pci/wsdisplay_pci.h> 93 #include <dev/wscons/wsdisplay_glyphcachevar.h> 94 95 #include <dev/pci/pcidevs.h> 96 #include <dev/pci/pcireg.h> 97 #include <dev/pci/pcivar.h> 98 #include <dev/pci/pciio.h> 99 #include <dev/pci/radeonfbreg.h> 100 #include <dev/pci/radeonfbvar.h> 101 #include "opt_radeonfb.h" 102 #include "opt_vcons.h" 103 104 #ifdef RADEONFB_DEPTH_32 105 #define RADEONFB_DEFAULT_DEPTH 32 106 #else 107 #define RADEONFB_DEFAULT_DEPTH 8 108 #endif 109 110 static int radeonfb_match(device_t, cfdata_t, void *); 111 static void radeonfb_attach(device_t, device_t, void *); 112 static int radeonfb_ioctl(void *, void *, unsigned long, void *, int, 113 struct lwp *); 114 static paddr_t radeonfb_mmap(void *, void *, off_t, int); 115 static int radeonfb_scratch_test(struct radeonfb_softc *, int, uint32_t); 116 static void radeonfb_loadbios(struct radeonfb_softc *, 117 const struct pci_attach_args *); 118 119 static uintmax_t radeonfb_getprop_num(struct radeonfb_softc *, const char *, 120 uintmax_t); 121 static int radeonfb_getclocks(struct radeonfb_softc *); 122 static int radeonfb_gettmds(struct radeonfb_softc *); 123 static int radeonfb_calc_dividers(struct radeonfb_softc *, uint32_t, 124 uint32_t *, uint32_t *, int); 125 /* flags for radeonfb_calc_dividers */ 126 #define NO_ODD_FBDIV 1 127 128 static int radeonfb_getconnectors(struct radeonfb_softc *); 129 static const struct videomode *radeonfb_modelookup(const char *); 130 static void radeonfb_init_screen(void *, struct vcons_screen *, int, long *); 131 static void radeonfb_pllwriteupdate(struct radeonfb_softc *, int); 132 static void radeonfb_pllwaitatomicread(struct radeonfb_softc *, int); 133 static void radeonfb_program_vclk(struct radeonfb_softc *, int, int, int); 134 static void radeonfb_modeswitch(struct radeonfb_display *); 135 static void radeonfb_setcrtc(struct radeonfb_display *, int); 136 static void radeonfb_init_misc(struct radeonfb_softc *); 137 static void radeonfb_set_fbloc(struct radeonfb_softc *); 138 static void radeonfb_init_palette(struct radeonfb_display *); 139 static void radeonfb_r300cg_workaround(struct radeonfb_softc *); 140 141 static int radeonfb_isblank(struct radeonfb_display *); 142 static void radeonfb_blank(struct radeonfb_display *, int); 143 static int radeonfb_set_cursor(struct radeonfb_display *, 144 struct wsdisplay_cursor *); 145 static int radeonfb_set_curpos(struct radeonfb_display *, 146 struct wsdisplay_curpos *); 147 static void radeonfb_putpal(struct radeonfb_display *, int, int, int, int); 148 static int radeonfb_putcmap(struct radeonfb_display *, struct wsdisplay_cmap *); 149 static int radeonfb_getcmap(struct radeonfb_display *, struct wsdisplay_cmap *); 150 151 /* acceleration support */ 152 static void radeonfb_rectfill(struct radeonfb_display *, int dstx, int dsty, 153 int width, int height, uint32_t color); 154 static void radeonfb_rectfill_a(void *, int, int, int, int, long); 155 static void radeonfb_bitblt(void *, int srcx, int srcy, 156 int dstx, int dsty, int width, int height, int rop); 157 158 /* hw cursor support */ 159 static void radeonfb_cursor_cmap(struct radeonfb_display *); 160 static void radeonfb_cursor_shape(struct radeonfb_display *); 161 static void radeonfb_cursor_position(struct radeonfb_display *); 162 static void radeonfb_cursor_visible(struct radeonfb_display *); 163 static void radeonfb_cursor_update(struct radeonfb_display *, unsigned); 164 165 static inline void radeonfb_wait_fifo(struct radeonfb_softc *, int); 166 static void radeonfb_engine_idle(struct radeonfb_softc *); 167 static void radeonfb_engine_flush(struct radeonfb_softc *); 168 static void radeonfb_engine_reset(struct radeonfb_softc *); 169 static void radeonfb_engine_init(struct radeonfb_display *); 170 static inline void radeonfb_unclip(struct radeonfb_softc *) __unused; 171 172 static void radeonfb_eraserows(void *, int, int, long); 173 static void radeonfb_erasecols(void *, int, int, int, long); 174 static void radeonfb_copyrows(void *, int, int, int); 175 static void radeonfb_copycols(void *, int, int, int, int); 176 static void radeonfb_cursor(void *, int, int, int); 177 static void radeonfb_putchar(void *, int, int, unsigned, long); 178 static void radeonfb_putchar_aa32(void *, int, int, unsigned, long); 179 static void radeonfb_putchar_aa8(void *, int, int, unsigned, long); 180 #ifndef RADEONFB_ALWAYS_ACCEL_PUTCHAR 181 static void radeonfb_putchar_wrapper(void *, int, int, unsigned, long); 182 #endif 183 184 static int radeonfb_set_backlight(struct radeonfb_display *, int); 185 static int radeonfb_get_backlight(struct radeonfb_display *); 186 static void radeonfb_switch_backlight(struct radeonfb_display *, int); 187 static void radeonfb_lvds_callout(void *); 188 189 static void radeonfb_brightness_up(device_t); 190 static void radeonfb_brightness_down(device_t); 191 192 static struct videomode *radeonfb_best_refresh(struct videomode *, 193 struct videomode *); 194 static void radeonfb_pickres(struct radeonfb_display *, uint16_t *, 195 uint16_t *, int); 196 static const struct videomode *radeonfb_port_mode(struct radeonfb_softc *, 197 struct radeonfb_port *, int, int); 198 199 static int radeonfb_drm_print(void *, const char *); 200 201 #ifdef RADEONFB_DEBUG 202 int radeon_debug = 1; 203 #define DPRINTF(x) \ 204 if (radeon_debug) printf x 205 #define PRINTREG(r) DPRINTF((#r " = %08x\n", GET32(sc, r))) 206 #define PRINTPLL(r) DPRINTF((#r " = %08x\n", GETPLL(sc, r))) 207 #else 208 #define DPRINTF(x) 209 #define PRINTREG(r) 210 #define PRINTPLL(r) 211 #endif 212 213 #define ROUNDUP(x,y) (((x) + ((y) - 1)) & ~((y) - 1)) 214 215 #ifndef RADEON_DEFAULT_MODE 216 /* any reasonably modern display should handle this */ 217 #define RADEON_DEFAULT_MODE "1024x768x60" 218 #endif 219 220 extern const u_char rasops_cmap[768]; 221 222 const char *radeonfb_default_mode = RADEON_DEFAULT_MODE; 223 224 static struct { 225 int size; /* minimum memory size (MB) */ 226 int maxx; /* maximum x dimension */ 227 int maxy; /* maximum y dimension */ 228 int maxbpp; /* maximum bpp */ 229 int maxdisp; /* maximum logical display count */ 230 } radeonfb_limits[] = { 231 { 32, 2048, 1536, 32, 2 }, 232 { 16, 1600, 1200, 32, 2 }, 233 { 8, 1600, 1200, 32, 1 }, 234 { 0, 0, 0, 0, 0 }, 235 }; 236 237 static struct wsscreen_descr radeonfb_stdscreen = { 238 "fb", /* name */ 239 0, 0, /* ncols, nrows */ 240 NULL, /* textops */ 241 8, 16, /* fontwidth, fontheight */ 242 WSSCREEN_WSCOLORS | WSSCREEN_UNDERLINE | WSSCREEN_RESIZE, /* capabilities */ 243 0, /* modecookie */ 244 }; 245 246 struct wsdisplay_accessops radeonfb_accessops = { 247 radeonfb_ioctl, 248 radeonfb_mmap, 249 NULL, /* vcons_alloc_screen */ 250 NULL, /* vcons_free_screen */ 251 NULL, /* vcons_show_screen */ 252 NULL, /* load_font */ 253 NULL, /* pollc */ 254 NULL, /* scroll */ 255 }; 256 257 static struct { 258 uint16_t devid; 259 uint16_t family; 260 uint16_t flags; 261 } radeonfb_devices[] = 262 { 263 /* R100 family */ 264 { PCI_PRODUCT_ATI_RADEON_R100_QD, RADEON_R100, 0 }, 265 { PCI_PRODUCT_ATI_RADEON_R100_QE, RADEON_R100, 0 }, 266 { PCI_PRODUCT_ATI_RADEON_R100_QF, RADEON_R100, 0 }, 267 { PCI_PRODUCT_ATI_RADEON_R100_QG, RADEON_R100, 0 }, 268 269 /* RV100 family */ 270 { PCI_PRODUCT_ATI_RADEON_RV100_LY, RADEON_RV100, RFB_MOB }, 271 { PCI_PRODUCT_ATI_RADEON_RV100_LZ, RADEON_RV100, RFB_MOB }, 272 { PCI_PRODUCT_ATI_RADEON_RV100_QY, RADEON_RV100, 0 }, 273 { PCI_PRODUCT_ATI_RADEON_RV100_QZ, RADEON_RV100, 0 }, 274 275 /* RS100 family */ 276 { PCI_PRODUCT_ATI_RADEON_RS100_4136, RADEON_RS100, 0 }, 277 { PCI_PRODUCT_ATI_RADEON_RS100_4336, RADEON_RS100, RFB_MOB }, 278 279 /* RS200/RS250 family */ 280 { PCI_PRODUCT_ATI_RADEON_RS200_4337, RADEON_RS200, RFB_MOB }, 281 { PCI_PRODUCT_ATI_RADEON_RS200_A7, RADEON_RS200, 0 }, 282 { PCI_PRODUCT_ATI_RADEON_RS250_B7, RADEON_RS200, RFB_MOB }, 283 { PCI_PRODUCT_ATI_RADEON_RS250_D7, RADEON_RS200, 0 }, 284 285 /* R200 family */ 286 /* add more R200 products? , 5148 */ 287 { PCI_PRODUCT_ATI_RADEON_R200_BB, RADEON_R200, 0 }, 288 { PCI_PRODUCT_ATI_RADEON_R200_BC, RADEON_R200, 0 }, 289 { PCI_PRODUCT_ATI_RADEON_R200_QH, RADEON_R200, 0 }, 290 { PCI_PRODUCT_ATI_RADEON_R200_QL, RADEON_R200, 0 }, 291 { PCI_PRODUCT_ATI_RADEON_R200_QM, RADEON_R200, 0 }, 292 293 /* RV200 family */ 294 { PCI_PRODUCT_ATI_RADEON_RV200_LW, RADEON_RV200, RFB_MOB }, 295 { PCI_PRODUCT_ATI_RADEON_RV200_LX, RADEON_RV200, RFB_MOB }, 296 { PCI_PRODUCT_ATI_RADEON_RV200_QW, RADEON_RV200, 0 }, 297 { PCI_PRODUCT_ATI_RADEON_RV200_QX, RADEON_RV200, 0 }, 298 299 /* RV250 family */ 300 { PCI_PRODUCT_ATI_RADEON_RV250_4966, RADEON_RV250, 0 }, 301 { PCI_PRODUCT_ATI_RADEON_RV250_4967, RADEON_RV250, 0 }, 302 { PCI_PRODUCT_ATI_RADEON_RV250_4C64, RADEON_RV250, RFB_MOB }, 303 { PCI_PRODUCT_ATI_RADEON_RV250_4C66, RADEON_RV250, RFB_MOB }, 304 { PCI_PRODUCT_ATI_RADEON_RV250_4C67, RADEON_RV250, RFB_MOB }, 305 306 /* RS300 family */ 307 { PCI_PRODUCT_ATI_RADEON_RS300_X5, RADEON_RS300, 0 }, 308 { PCI_PRODUCT_ATI_RADEON_RS300_X4, RADEON_RS300, 0 }, 309 { PCI_PRODUCT_ATI_RADEON_RS300_7834, RADEON_RS300, 0 }, 310 { PCI_PRODUCT_ATI_RADEON_RS300_7835, RADEON_RS300, RFB_MOB }, 311 312 /* RV280 family */ 313 { PCI_PRODUCT_ATI_RADEON_RV280_5960, RADEON_RV280, 0 }, 314 { PCI_PRODUCT_ATI_RADEON_RV280_5961, RADEON_RV280, 0 }, 315 { PCI_PRODUCT_ATI_RADEON_RV280_5962, RADEON_RV280, 0 }, 316 { PCI_PRODUCT_ATI_RADEON_RV280_5963, RADEON_RV280, 0 }, 317 { PCI_PRODUCT_ATI_RADEON_RV280_5964, RADEON_RV280, 0 }, 318 { PCI_PRODUCT_ATI_RADEON_RV280_5C61, RADEON_RV280, RFB_MOB }, 319 { PCI_PRODUCT_ATI_RADEON_RV280_5C63, RADEON_RV280, RFB_MOB }, 320 321 /* R300 family */ 322 { PCI_PRODUCT_ATI_RADEON_R300_AD, RADEON_R300, 0 }, 323 { PCI_PRODUCT_ATI_RADEON_R300_AE, RADEON_R300, 0 }, 324 { PCI_PRODUCT_ATI_RADEON_R300_AF, RADEON_R300, 0 }, 325 { PCI_PRODUCT_ATI_RADEON_R300_AG, RADEON_R300, 0 }, 326 { PCI_PRODUCT_ATI_RADEON_R300_ND, RADEON_R300, 0 }, 327 { PCI_PRODUCT_ATI_RADEON_R300_NE, RADEON_R300, 0 }, 328 { PCI_PRODUCT_ATI_RADEON_R300_NF, RADEON_R300, 0 }, 329 { PCI_PRODUCT_ATI_RADEON_R300_NG, RADEON_R300, 0 }, 330 331 /* RV350/RV360 family */ 332 { PCI_PRODUCT_ATI_RADEON_RV350_AP, RADEON_RV350, 0 }, 333 { PCI_PRODUCT_ATI_RADEON_RV350_AQ, RADEON_RV350, 0 }, 334 { PCI_PRODUCT_ATI_RADEON_RV360_AR, RADEON_RV350, 0 }, 335 { PCI_PRODUCT_ATI_RADEON_RV350_AS, RADEON_RV350, 0 }, 336 { PCI_PRODUCT_ATI_RADEON_RV350_AT, RADEON_RV350, 0 }, 337 { PCI_PRODUCT_ATI_RADEON_RV350_AV, RADEON_RV350, 0 }, 338 { PCI_PRODUCT_ATI_RADEON_RV350_NP, RADEON_RV350, RFB_MOB }, 339 { PCI_PRODUCT_ATI_RADEON_RV350_NQ, RADEON_RV350, RFB_MOB }, 340 { PCI_PRODUCT_ATI_RADEON_RV350_NR, RADEON_RV350, RFB_MOB }, 341 { PCI_PRODUCT_ATI_RADEON_RV350_NS, RADEON_RV350, RFB_MOB }, 342 { PCI_PRODUCT_ATI_RADEON_RV350_NT, RADEON_RV350, RFB_MOB }, 343 { PCI_PRODUCT_ATI_RADEON_RV350_NV, RADEON_RV350, RFB_MOB }, 344 345 /* R350/R360 family */ 346 { PCI_PRODUCT_ATI_RADEON_R350_AH, RADEON_R350, 0 }, 347 { PCI_PRODUCT_ATI_RADEON_R350_AI, RADEON_R350, 0 }, 348 { PCI_PRODUCT_ATI_RADEON_R350_AJ, RADEON_R350, 0 }, 349 { PCI_PRODUCT_ATI_RADEON_R350_AK, RADEON_R350, 0 }, 350 { PCI_PRODUCT_ATI_RADEON_R350_NH, RADEON_R350, 0 }, 351 { PCI_PRODUCT_ATI_RADEON_R350_NI, RADEON_R350, 0 }, 352 { PCI_PRODUCT_ATI_RADEON_R350_NK, RADEON_R350, 0 }, 353 { PCI_PRODUCT_ATI_RADEON_R360_NJ, RADEON_R350, 0 }, 354 355 /* RV380/RV370 family */ 356 { PCI_PRODUCT_ATI_RADEON_RV380_3150, RADEON_RV380, RFB_MOB }, 357 { PCI_PRODUCT_ATI_RADEON_RV380_3154, RADEON_RV380, RFB_MOB }, 358 { PCI_PRODUCT_ATI_RADEON_RV380_3E50, RADEON_RV380, 0 }, 359 { PCI_PRODUCT_ATI_RADEON_RV380_3E54, RADEON_RV380, 0 }, 360 { PCI_PRODUCT_ATI_RADEON_RV370_5460, RADEON_RV380, RFB_MOB }, 361 { PCI_PRODUCT_ATI_RADEON_RV370_5464, RADEON_RV380, RFB_MOB }, 362 { PCI_PRODUCT_ATI_RADEON_RV370_5B60, RADEON_RV380, 0 }, 363 { PCI_PRODUCT_ATI_RADEON_RV370_5B63, RADEON_RV380, 0 }, 364 { PCI_PRODUCT_ATI_RADEON_RV370_5B64, RADEON_RV380, 0 }, 365 { PCI_PRODUCT_ATI_RADEON_RV370_5B65, RADEON_RV380, 0 }, 366 367 #if notyet 368 /* R420/R423 family */ 369 { PCI_PRODUCT_ATI_RADEON_R420_JH, RADEON_R420, 0 }, 370 { PCI_PRODUCT_ATI_RADEON_R420_JI, RADEON_R420, 0 }, 371 { PCI_PRODUCT_ATI_RADEON_R420_JJ, RADEON_R420, 0 }, 372 { PCI_PRODUCT_ATI_RADEON_R420_JK, RADEON_R420, 0 }, 373 { PCI_PRODUCT_ATI_RADEON_R420_JL, RADEON_R420, 0 }, 374 { PCI_PRODUCT_ATI_RADEON_R420_JM, RADEON_R420, 0 }, 375 { PCI_PRODUCT_ATI_RADEON_R420_JN, RADEON_R420, RFB_MOB }, 376 { PCI_PRODUCT_ATI_RADEON_R420_JP, RADEON_R420, 0 }, 377 { PCI_PRODUCT_ATI_RADEON_R423_UH, RADEON_R420, 0 }, 378 { PCI_PRODUCT_ATI_RADEON_R423_UI, RADEON_R420, 0 }, 379 { PCI_PRODUCT_ATI_RADEON_R423_UJ, RADEON_R420, 0 }, 380 { PCI_PRODUCT_ATI_RADEON_R423_UK, RADEON_R420, 0 }, 381 { PCI_PRODUCT_ATI_RADEON_R423_UQ, RADEON_R420, 0 }, 382 { PCI_PRODUCT_ATI_RADEON_R423_UR, RADEON_R420, 0 }, 383 { PCI_PRODUCT_ATI_RADEON_R423_UT, RADEON_R420, 0 }, 384 { PCI_PRODUCT_ATI_RADEON_R423_5D57, RADEON_R420, 0 }, 385 { PCI_PRODUCT_ATI_RADEON_R430_554F, RADEON_R420, 0 }, 386 #endif 387 388 /* R5xx family */ 389 { 0x7240, RADEON_R580, RFB_IS_AVIVO }, 390 { 0, 0, 0 } 391 }; 392 393 static struct { 394 int divider; 395 int mask; 396 } radeonfb_dividers[] = { 397 { 16, 5 }, 398 { 12, 7 }, 399 { 8, 3 }, 400 { 6, 6 }, 401 { 4, 2 }, 402 { 3, 4 }, 403 { 2, 1 }, 404 { 1, 0 }, 405 { 0, 0 } 406 }; 407 408 /* 409 * This table taken from X11. 410 */ 411 static const struct { 412 int family; 413 struct radeon_tmds_pll plls[4]; 414 } radeonfb_tmds_pll[] = { 415 { RADEON_R100, {{12000, 0xa1b}, {-1, 0xa3f}}}, 416 { RADEON_RV100, {{12000, 0xa1b}, {-1, 0xa3f}}}, 417 { RADEON_RS100, {{0, 0}}}, 418 { RADEON_RV200, {{15000, 0xa1b}, {-1, 0xa3f}}}, 419 { RADEON_RS200, {{15000, 0xa1b}, {-1, 0xa3f}}}, 420 { RADEON_R200, {{15000, 0xa1b}, {-1, 0xa3f}}}, 421 { RADEON_RV250, {{15500, 0x81b}, {-1, 0x83f}}}, 422 { RADEON_RS300, {{0, 0}}}, 423 { RADEON_RV280, {{13000, 0x400f4}, {15000, 0x400f7}, {-1, 0x40111}}}, 424 { RADEON_R300, {{-1, 0xb01cb}}}, 425 { RADEON_R350, {{-1, 0xb01cb}}}, 426 { RADEON_RV350, {{15000, 0xb0155}, {-1, 0xb01cb}}}, 427 { RADEON_RV380, {{15000, 0xb0155}, {-1, 0xb01cb}}}, 428 { RADEON_R420, {{-1, 0xb01cb}}}, 429 { RADEON_R580, {{-1, 0xb01cb}}}, /* XXX likely bogus */ 430 }; 431 432 #define RADEONFB_BACKLIGHT_MAX 255 /* Maximum backlight level. */ 433 434 435 CFATTACH_DECL_NEW(radeonfb, sizeof (struct radeonfb_softc), 436 radeonfb_match, radeonfb_attach, NULL, NULL); 437 438 static int 439 radeonfb_match(device_t parent, cfdata_t match, void *aux) 440 { 441 const struct pci_attach_args *pa = aux; 442 int i; 443 444 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_ATI) 445 return 0; 446 447 for (i = 0; radeonfb_devices[i].devid; i++) { 448 if (PCI_PRODUCT(pa->pa_id) == radeonfb_devices[i].devid) 449 return 100; /* high to defeat VGA/VESA */ 450 } 451 452 return 0; 453 } 454 455 static void 456 radeonfb_attach(device_t parent, device_t dev, void *aux) 457 { 458 struct radeonfb_softc *sc = device_private(dev); 459 const struct pci_attach_args *pa = aux; 460 const char *mptr; 461 bus_size_t bsz; 462 pcireg_t screg; 463 int i, j, fg, bg, ul, flags; 464 uint32_t v; 465 466 sc->sc_dev = dev; 467 sc->sc_id = pa->pa_id; 468 for (i = 0; radeonfb_devices[i].devid; i++) { 469 if (PCI_PRODUCT(sc->sc_id) == radeonfb_devices[i].devid) 470 break; 471 } 472 473 pci_aprint_devinfo(pa, NULL); 474 475 DPRINTF(("%s", prop_dictionary_externalize(device_properties(dev)))); 476 477 KASSERT(radeonfb_devices[i].devid != 0); 478 sc->sc_pt = pa->pa_tag; 479 sc->sc_iot = pa->pa_iot; 480 sc->sc_pc = pa->pa_pc; 481 sc->sc_family = radeonfb_devices[i].family; 482 sc->sc_flags = radeonfb_devices[i].flags; 483 sc->sc_bios = NULL; 484 sc->sc_biossz = 0; 485 486 /* enable memory and IO access */ 487 screg = pci_conf_read(sc->sc_pc, sc->sc_pt, PCI_COMMAND_STATUS_REG); 488 screg |= PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE; 489 pci_conf_write(sc->sc_pc, sc->sc_pt, PCI_COMMAND_STATUS_REG, screg); 490 491 /* 492 * Some flags are general to entire chip families, and rather 493 * than clutter up the table with them, we go ahead and set 494 * them here. 495 */ 496 switch (sc->sc_family) { 497 case RADEON_RS100: 498 case RADEON_RS200: 499 sc->sc_flags |= RFB_IGP | RFB_RV100; 500 break; 501 502 case RADEON_RV100: 503 case RADEON_RV200: 504 case RADEON_RV250: 505 case RADEON_RV280: 506 sc->sc_flags |= RFB_RV100; 507 break; 508 509 case RADEON_RS300: 510 sc->sc_flags |= RFB_SDAC | RFB_IGP | RFB_RV100; 511 break; 512 513 case RADEON_R300: 514 case RADEON_RV350: 515 case RADEON_R350: 516 case RADEON_RV380: 517 case RADEON_R420: 518 case RADEON_R580: 519 /* newer chips */ 520 sc->sc_flags |= RFB_R300; 521 break; 522 523 case RADEON_R100: 524 sc->sc_flags |= RFB_NCRTC2; 525 break; 526 } 527 528 if ((sc->sc_family == RADEON_RV200) || 529 (sc->sc_family == RADEON_RV250) || 530 (sc->sc_family == RADEON_RV280) || 531 (sc->sc_family == RADEON_RV350)) { 532 bool inverted = 0; 533 /* backlight level is linear */ 534 DPRINTF(("found RV* chip, backlight is supposedly linear\n")); 535 prop_dictionary_get_bool(device_properties(sc->sc_dev), 536 "backlight_level_reverted", &inverted); 537 if (inverted) { 538 DPRINTF(("nope, it's inverted\n")); 539 sc->sc_flags |= RFB_INV_BLIGHT; 540 } 541 } else 542 sc->sc_flags |= RFB_INV_BLIGHT; 543 544 /* 545 * XXX: to support true multihead, this must change. 546 */ 547 sc->sc_ndisplays = 1; 548 549 /* XXX: */ 550 if (!HAS_CRTC2(sc)) { 551 sc->sc_ndisplays = 1; 552 } 553 554 if (pci_mapreg_map(pa, RADEON_MAPREG_MMIO, PCI_MAPREG_TYPE_MEM, 0, 555 &sc->sc_regt, &sc->sc_regh, &sc->sc_regaddr, 556 &sc->sc_regsz) != 0) { 557 aprint_error("%s: unable to map registers!\n", XNAME(sc)); 558 goto error; 559 } 560 561 if (pci_mapreg_info(sc->sc_pc, sc->sc_pt, PCI_MAPREG_ROM, 562 PCI_MAPREG_TYPE_ROM, &sc->sc_romaddr, &sc->sc_romsz, &flags) != 0) 563 { 564 aprint_error("%s: unable to find ROM!\n", XNAME(sc)); 565 goto error; 566 } 567 sc->sc_romt = sc->sc_memt; 568 569 sc->sc_mapped = TRUE; 570 571 /* scratch register test... */ 572 if (radeonfb_scratch_test(sc, RADEON_BIOS_0_SCRATCH, 0x55555555) || 573 radeonfb_scratch_test(sc, RADEON_BIOS_0_SCRATCH, 0xaaaaaaaa)) { 574 aprint_error("%s: scratch register test failed!\n", XNAME(sc)); 575 goto error; 576 } 577 578 PRINTREG(RADEON_CRTC_EXT_CNTL); 579 PRINTREG(RADEON_CRTC_GEN_CNTL); 580 PRINTREG(RADEON_CRTC2_GEN_CNTL); 581 PRINTREG(RADEON_DISP_OUTPUT_CNTL); 582 PRINTREG(RADEON_DAC_CNTL2); 583 PRINTREG(RADEON_BIOS_4_SCRATCH); 584 PRINTREG(RADEON_FP_GEN_CNTL); 585 sc->sc_fp_gen_cntl = GET32(sc, RADEON_FP_GEN_CNTL); 586 PRINTREG(RADEON_FP2_GEN_CNTL); 587 PRINTREG(RADEON_TMDS_CNTL); 588 PRINTREG(RADEON_TMDS_TRANSMITTER_CNTL); 589 PRINTREG(RADEON_TMDS_PLL_CNTL); 590 PRINTREG(RADEON_LVDS_GEN_CNTL); 591 PRINTREG(RADEON_DISP_HW_DEBUG); 592 if (!IS_AVIVO(sc)) { 593 PRINTREG(RADEON_PIXCLKS_CNTL); 594 PRINTREG(RADEON_CRTC_H_SYNC_STRT_WID); 595 PRINTREG(RADEON_FP_H_SYNC_STRT_WID); 596 PRINTREG(RADEON_CRTC2_H_SYNC_STRT_WID); 597 PRINTREG(RADEON_FP_H2_SYNC_STRT_WID); 598 } 599 /* 600 * XXX 601 * This was if (IS_RV100()), which is set for all pre-R3xx chips. 602 * I suspect this only makes sense on Sun XVR-100 with firmware that doesn't 603 * support DVI, so for now let's restrict it to only actual RV100 604 */ 605 if (sc->sc_family == RADEON_RV100) 606 PUT32(sc, RADEON_TMDS_PLL_CNTL, 0xa27); 607 608 /* XXX 609 * according to xf86-video-radeon R3xx has this bit backwards 610 */ 611 if (IS_R300(sc)) { 612 PATCH32(sc, RADEON_TMDS_TRANSMITTER_CNTL, 613 0, 614 ~(RADEON_TMDS_TRANSMITTER_PLLEN | RADEON_TMDS_TRANSMITTER_PLLRST)); 615 } else { 616 PATCH32(sc, RADEON_TMDS_TRANSMITTER_CNTL, 617 RADEON_TMDS_TRANSMITTER_PLLEN, 618 ~(RADEON_TMDS_TRANSMITTER_PLLEN | RADEON_TMDS_TRANSMITTER_PLLRST)); 619 } 620 621 radeonfb_i2c_init(sc); 622 623 radeonfb_loadbios(sc, pa); 624 625 #ifdef RADEONFB_BIOS_INIT 626 if (radeonfb_bios_init(sc)) { 627 aprint_error("%s: BIOS inititialization failed\n", XNAME(sc)); 628 } 629 #endif 630 631 if (radeonfb_getclocks(sc)) { 632 aprint_error("%s: Unable to get reference clocks from BIOS\n", 633 XNAME(sc)); 634 goto error; 635 } 636 637 if (radeonfb_gettmds(sc)) { 638 aprint_error("%s: Unable to identify TMDS PLL settings\n", 639 XNAME(sc)); 640 goto error; 641 } 642 643 aprint_verbose("%s: refclk = %d.%03d MHz, refdiv = %d " 644 "minpll = %d, maxpll = %d\n", XNAME(sc), 645 (int)sc->sc_refclk / 1000, (int)sc->sc_refclk % 1000, 646 (int)sc->sc_refdiv, (int)sc->sc_minpll, (int)sc->sc_maxpll); 647 648 radeonfb_getconnectors(sc); 649 650 radeonfb_set_fbloc(sc); 651 652 /* 64 MB should be enough -- more just wastes map entries */ 653 if (sc->sc_memsz > (64 << 20)) 654 sc->sc_memsz = (64 << 20); 655 656 for (i = 0; radeonfb_limits[i].size; i++) { 657 if (sc->sc_memsz >= radeonfb_limits[i].size) { 658 sc->sc_maxx = radeonfb_limits[i].maxx; 659 sc->sc_maxy = radeonfb_limits[i].maxy; 660 sc->sc_maxbpp = radeonfb_limits[i].maxbpp; 661 /* framebuffer offset, start at a 4K page */ 662 sc->sc_fboffset = sc->sc_memsz / 663 radeonfb_limits[i].maxdisp; 664 /* 665 * we use the fbsize to figure out where we can store 666 * things like cursor data. 667 */ 668 sc->sc_fbsize = 669 ROUNDUP(ROUNDUP(sc->sc_maxx * sc->sc_maxbpp / 8 , 670 RADEON_STRIDEALIGN) * sc->sc_maxy, 671 4096); 672 break; 673 } 674 } 675 676 677 radeonfb_init_misc(sc); 678 679 /* program the DAC wirings */ 680 for (i = 0; i < (HAS_CRTC2(sc) ? 2 : 1); i++) { 681 switch (sc->sc_ports[i].rp_dac_type) { 682 case RADEON_DAC_PRIMARY: 683 PATCH32(sc, RADEON_DAC_CNTL2, 684 i ? RADEON_DAC2_DAC_CLK_SEL : 0, 685 ~RADEON_DAC2_DAC_CLK_SEL); 686 break; 687 case RADEON_DAC_TVDAC: 688 /* we always use the TVDAC to drive a secondary analog 689 * CRT for now. if we ever support TV-out this will 690 * have to change. 691 */ 692 SET32(sc, RADEON_DAC_CNTL2, 693 RADEON_DAC2_DAC2_CLK_SEL); 694 PATCH32(sc, RADEON_DISP_HW_DEBUG, 695 i ? 0 : RADEON_CRT2_DISP1_SEL, 696 ~RADEON_CRT2_DISP1_SEL); 697 /* we're using CRTC2 for the 2nd port */ 698 if (sc->sc_ports[i].rp_number == 1) { 699 PATCH32(sc, RADEON_DISP_OUTPUT_CNTL, 700 RADEON_DISP_DAC2_SOURCE_CRTC2, 701 ~RADEON_DISP_DAC2_SOURCE_MASK); 702 } 703 704 break; 705 } 706 DPRINTF(("%s: port %d tmds type %d\n", __func__, i, 707 sc->sc_ports[i].rp_tmds_type)); 708 switch (sc->sc_ports[i].rp_tmds_type) { 709 case RADEON_TMDS_INT: 710 /* point FP0 at the CRTC this port uses */ 711 DPRINTF(("%s: plugging internal TMDS into CRTC %d\n", 712 __func__, sc->sc_ports[i].rp_number)); 713 if (IS_R300(sc)) { 714 PATCH32(sc, RADEON_FP_GEN_CNTL, 715 sc->sc_ports[i].rp_number ? 716 R200_FP_SOURCE_SEL_CRTC2 : 717 R200_FP_SOURCE_SEL_CRTC1, 718 ~R200_FP_SOURCE_SEL_MASK); 719 } else { 720 PATCH32(sc, RADEON_FP_GEN_CNTL, 721 sc->sc_ports[i].rp_number ? 722 RADEON_FP_SEL_CRTC2 : 723 RADEON_FP_SEL_CRTC1, 724 ~RADEON_FP_SEL_MASK); 725 } 726 break; 727 case RADEON_TMDS_EXT: 728 /* point FP2 at the CRTC this port uses */ 729 DPRINTF(("%s: plugging external TMDS into CRTC %d\n", 730 __func__, sc->sc_ports[i].rp_number)); 731 if (IS_R300(sc)) { 732 PATCH32(sc, RADEON_FP2_GEN_CNTL, 733 sc->sc_ports[i].rp_number ? 734 R200_FP2_SOURCE_SEL_CRTC2 : 735 R200_FP2_SOURCE_SEL_CRTC1, 736 ~R200_FP2_SOURCE_SEL_CRTC2); 737 } else { 738 PATCH32(sc, RADEON_FP2_GEN_CNTL, 739 sc->sc_ports[i].rp_number ? 740 RADEON_FP2_SRC_SEL_CRTC2 : 741 RADEON_FP2_SRC_SEL_CRTC1, 742 ~RADEON_FP2_SRC_SEL_CRTC2); 743 } 744 break; 745 } 746 } 747 PRINTREG(RADEON_DAC_CNTL2); 748 PRINTREG(RADEON_DISP_HW_DEBUG); 749 750 PRINTREG(RADEON_DAC_CNTL); 751 /* other DAC programming */ 752 v = GET32(sc, RADEON_DAC_CNTL); 753 v &= (RADEON_DAC_RANGE_CNTL_MASK | RADEON_DAC_BLANKING); 754 v |= RADEON_DAC_MASK_ALL | RADEON_DAC_8BIT_EN; 755 PUT32(sc, RADEON_DAC_CNTL, v); 756 PRINTREG(RADEON_DAC_CNTL); 757 758 /* XXX: this may need more investigation */ 759 PUT32(sc, RADEON_TV_DAC_CNTL, 0x00280203); 760 PRINTREG(RADEON_TV_DAC_CNTL); 761 762 /* enable TMDS */ 763 SET32(sc, RADEON_FP_GEN_CNTL, 764 RADEON_FP_TMDS_EN | 765 RADEON_FP_CRTC_DONT_SHADOW_VPAR | 766 RADEON_FP_CRTC_DONT_SHADOW_HEND); 767 /* 768 * XXX 769 * no idea why this is necessary - if I do not clear this bit on my 770 * iBook G4 the screen remains black, even though it's already clear. 771 * It needs to be set on my Sun XVR-100 for the DVI port to work 772 * TODO: 773 * see if this is still necessary now that CRTCs, DACs and outputs are 774 * getting wired up in a halfway sane way 775 */ 776 if (sc->sc_fp_gen_cntl & RADEON_FP_SEL_CRTC2) { 777 SET32(sc, RADEON_FP_GEN_CNTL, RADEON_FP_SEL_CRTC2); 778 } else { 779 CLR32(sc, RADEON_FP_GEN_CNTL, RADEON_FP_SEL_CRTC2); 780 } 781 782 /* 783 * we use bus_space_map instead of pci_mapreg, because we don't 784 * need the full aperature space. no point in wasting virtual 785 * address space we don't intend to use, right? 786 */ 787 if ((sc->sc_memsz < (4096 * 1024)) || 788 (pci_mapreg_info(sc->sc_pc, sc->sc_pt, RADEON_MAPREG_VRAM, 789 PCI_MAPREG_TYPE_MEM, &sc->sc_memaddr, &bsz, NULL) != 0) || 790 (bsz < sc->sc_memsz)) { 791 sc->sc_memsz = 0; 792 aprint_error("%s: Bad frame buffer configuration\n", 793 XNAME(sc)); 794 goto error; 795 } 796 797 sc->sc_memt = pa->pa_memt; 798 if (bus_space_map(sc->sc_memt, sc->sc_memaddr, sc->sc_memsz, 799 BUS_SPACE_MAP_LINEAR, &sc->sc_memh) != 0) { 800 sc->sc_memsz = 0; 801 aprint_error("%s: Unable to map frame buffer\n", XNAME(sc)); 802 goto error; 803 } 804 805 aprint_normal("%s: %d MB aperture at 0x%08x, " 806 "%d KB registers at 0x%08x\n", XNAME(sc), 807 (int)sc->sc_memsz >> 20, (unsigned)sc->sc_memaddr, 808 (int)sc->sc_regsz >> 10, (unsigned)sc->sc_regaddr); 809 810 /* setup default video mode from devprop (allows PROM override) */ 811 sc->sc_defaultmode = radeonfb_default_mode; 812 if (prop_dictionary_get_cstring_nocopy(device_properties(sc->sc_dev), 813 "videomode", &mptr)) { 814 815 strncpy(sc->sc_modebuf, mptr, sizeof(sc->sc_modebuf)); 816 sc->sc_defaultmode = sc->sc_modebuf; 817 } 818 819 /* initialize some basic display parameters */ 820 for (i = 0; i < sc->sc_ndisplays; i++) { 821 struct radeonfb_display *dp = &sc->sc_displays[i]; 822 struct rasops_info *ri; 823 long defattr; 824 struct wsemuldisplaydev_attach_args aa; 825 826 /* 827 * Figure out how many "displays" (desktops) we are going to 828 * support. If more than one, then each CRTC gets its own 829 * programming. 830 * 831 * XXX: this code needs to change to support mergedfb. 832 * XXX: would be nice to allow this to be overridden 833 */ 834 if (HAS_CRTC2(sc) && (sc->sc_ndisplays == 1)) { 835 DPRINTF(("dual crtcs!\n")); 836 dp->rd_ncrtcs = 2; 837 dp->rd_crtcs[0].rc_port = 838 &sc->sc_ports[0]; 839 dp->rd_crtcs[0].rc_number = sc->sc_ports[0].rp_number; 840 dp->rd_crtcs[1].rc_port = 841 &sc->sc_ports[1]; 842 dp->rd_crtcs[1].rc_number = sc->sc_ports[1].rp_number; 843 } else { 844 dp->rd_ncrtcs = 1; 845 dp->rd_crtcs[0].rc_port = 846 &sc->sc_ports[i]; 847 dp->rd_crtcs[0].rc_number = sc->sc_ports[i].rp_number; 848 } 849 850 dp->rd_softc = sc; 851 dp->rd_wsmode = WSDISPLAYIO_MODE_EMUL; 852 dp->rd_bpp = RADEONFB_DEFAULT_DEPTH; /* XXX */ 853 854 /* for text mode, we pick a resolution that won't 855 * require panning */ 856 radeonfb_pickres(dp, &dp->rd_virtx, &dp->rd_virty, 0); 857 858 aprint_normal("%s: display %d: " 859 "initial virtual resolution %dx%d at %d bpp\n", 860 XNAME(sc), i, dp->rd_virtx, dp->rd_virty, dp->rd_bpp); 861 aprint_normal_dev(sc->sc_dev, "using %d MB per display\n", 862 sc->sc_fboffset >> 20); 863 /* now select the *video mode* that we will use */ 864 for (j = 0; j < dp->rd_ncrtcs; j++) { 865 const struct videomode *vmp; 866 vmp = radeonfb_port_mode(sc, dp->rd_crtcs[j].rc_port, 867 dp->rd_virtx, dp->rd_virty); 868 869 /* 870 * virtual resolution should be at least as high as 871 * physical 872 */ 873 if (dp->rd_virtx < vmp->hdisplay || 874 dp->rd_virty < vmp->vdisplay) { 875 dp->rd_virtx = vmp->hdisplay; 876 dp->rd_virty = vmp->vdisplay; 877 } 878 879 dp->rd_crtcs[j].rc_videomode = *vmp; 880 printf("%s: port %d: physical %dx%d %dHz\n", 881 XNAME(sc), j, vmp->hdisplay, vmp->vdisplay, 882 DIVIDE(DIVIDE(vmp->dot_clock * 1000, 883 vmp->htotal), vmp->vtotal)); 884 } 885 886 /* N.B.: radeon wants 64-byte aligned stride */ 887 dp->rd_stride = dp->rd_virtx * dp->rd_bpp / 8; 888 dp->rd_stride = ROUNDUP(dp->rd_stride, RADEON_STRIDEALIGN); 889 890 dp->rd_offset = sc->sc_fboffset * i; 891 dp->rd_fbptr = (vaddr_t)bus_space_vaddr(sc->sc_memt, 892 sc->sc_memh) + dp->rd_offset; 893 dp->rd_curoff = sc->sc_fboffset - 16384; /* 16KB cursor space */ 894 dp->rd_curptr = dp->rd_fbptr + dp->rd_curoff; 895 896 DPRINTF(("fpbtr = %p\n", (void *)dp->rd_fbptr)); 897 898 switch (dp->rd_bpp) { 899 case 8: 900 dp->rd_format = 2; 901 break; 902 case 32: 903 dp->rd_format = 6; 904 break; 905 default: 906 aprint_error("%s: bad depth %d\n", XNAME(sc), 907 dp->rd_bpp); 908 goto error; 909 } 910 DPRINTF(("init engine\n")); 911 /* XXX: this seems suspicious - per display engine 912 initialization? */ 913 914 radeonfb_modeswitch(dp); 915 radeonfb_engine_init(dp); 916 917 /* copy the template into place */ 918 dp->rd_wsscreens_storage[0] = radeonfb_stdscreen; 919 dp->rd_wsscreens = dp->rd_wsscreens_storage; 920 921 /* and make up the list */ 922 dp->rd_wsscreenlist.nscreens = 1; 923 dp->rd_wsscreenlist.screens = (void *)&dp->rd_wsscreens; 924 925 vcons_init(&dp->rd_vd, dp, dp->rd_wsscreens, 926 &radeonfb_accessops); 927 928 dp->rd_vd.init_screen = radeonfb_init_screen; 929 930 #ifdef RADEONFB_DEBUG 931 dp->rd_virty -= 200; 932 #endif 933 934 dp->rd_console = 0; 935 prop_dictionary_get_bool(device_properties(sc->sc_dev), 936 "is_console", &dp->rd_console); 937 938 dp->rd_vscreen.scr_flags |= VCONS_SCREEN_IS_STATIC; 939 940 941 vcons_init_screen(&dp->rd_vd, &dp->rd_vscreen, 942 dp->rd_console, &defattr); 943 944 ri = &dp->rd_vscreen.scr_ri; 945 946 /* clear the screen */ 947 rasops_unpack_attr(defattr, &fg, &bg, &ul); 948 dp->rd_bg = ri->ri_devcmap[bg & 0xf]; 949 radeonfb_rectfill(dp, 0, 0, ri->ri_width, ri->ri_height, 950 dp->rd_bg); 951 952 dp->rd_wsscreens->textops = &ri->ri_ops; 953 dp->rd_wsscreens->capabilities = ri->ri_caps; 954 dp->rd_wsscreens->nrows = ri->ri_rows; 955 dp->rd_wsscreens->ncols = ri->ri_cols; 956 957 #ifdef SPLASHSCREEN 958 dp->rd_splash.si_depth = ri->ri_depth; 959 dp->rd_splash.si_bits = ri->ri_bits; 960 dp->rd_splash.si_hwbits = ri->ri_hwbits; 961 dp->rd_splash.si_width = ri->ri_width; 962 dp->rd_splash.si_height = ri->ri_height; 963 dp->rd_splash.si_stride = ri->ri_stride; 964 dp->rd_splash.si_fillrect = NULL; 965 #endif 966 dp->rd_gc.gc_bitblt = radeonfb_bitblt; 967 dp->rd_gc.gc_rectfill = radeonfb_rectfill_a; 968 dp->rd_gc.gc_rop = RADEON_ROP3_S; 969 dp->rd_gc.gc_blitcookie = dp; 970 /* 971 * use memory between framebuffer and cursor area as glyph 972 * cache, cap at 4096 lines 973 */ 974 glyphcache_init(&dp->rd_gc, dp->rd_virty + 4, 975 uimin(4096, 976 (dp->rd_curoff / dp->rd_stride) - (dp->rd_virty + 4)), 977 dp->rd_virtx, 978 ri->ri_font->fontwidth, 979 ri->ri_font->fontheight, 980 defattr); 981 dp->rd_vd.show_screen_cookie = &dp->rd_gc; 982 dp->rd_vd.show_screen_cb = glyphcache_adapt; 983 984 if (dp->rd_console) { 985 986 wsdisplay_cnattach(dp->rd_wsscreens, ri, 0, 0, 987 defattr); 988 #ifdef SPLASHSCREEN 989 if (splash_render(&dp->rd_splash, 990 SPLASH_F_CENTER|SPLASH_F_FILL) == 0) 991 SCREEN_DISABLE_DRAWING(&dp->rd_vscreen); 992 else 993 #endif 994 vcons_replay_msgbuf(&dp->rd_vscreen); 995 } else { 996 997 /* 998 * since we're not the console we can postpone 999 * the rest until someone actually allocates a 1000 * screen for us. but we do clear the screen 1001 * at least. 1002 */ 1003 memset(ri->ri_bits, 0, 1024); 1004 1005 #ifdef SPLASHSCREEN 1006 if (splash_render(&dp->rd_splash, 1007 SPLASH_F_CENTER|SPLASH_F_FILL) == 0) 1008 SCREEN_DISABLE_DRAWING(&dp->rd_vscreen); 1009 #endif 1010 } 1011 1012 aa.console = dp->rd_console; 1013 aa.scrdata = &dp->rd_wsscreenlist; 1014 aa.accessops = &radeonfb_accessops; 1015 aa.accesscookie = &dp->rd_vd; 1016 1017 config_found(sc->sc_dev, &aa, wsemuldisplaydevprint); 1018 1019 radeonfb_blank(dp, 0); 1020 1021 /* Initialise delayed lvds operations for backlight. */ 1022 callout_init(&dp->rd_bl_lvds_co, 0); 1023 callout_setfunc(&dp->rd_bl_lvds_co, 1024 radeonfb_lvds_callout, dp); 1025 1026 dp->rd_bl_on = 1; 1027 if (sc->sc_flags & RFB_MOB) { 1028 dp->rd_bl_level = radeonfb_get_backlight(dp); 1029 } else 1030 dp->rd_bl_level = 128; 1031 1032 radeonfb_set_backlight(dp, dp->rd_bl_level); 1033 } 1034 for (i = 0; i < RADEON_NDISPLAYS; i++) 1035 radeonfb_init_palette(&sc->sc_displays[i]); 1036 1037 if (HAS_CRTC2(sc) && !IS_AVIVO(sc)) { 1038 CLR32(sc, RADEON_CRTC2_GEN_CNTL, RADEON_CRTC2_DISP_DIS); 1039 } 1040 1041 if (!IS_AVIVO(sc)) { 1042 CLR32(sc, RADEON_CRTC_EXT_CNTL, RADEON_CRTC_DISPLAY_DIS); 1043 SET32(sc, RADEON_FP_GEN_CNTL, RADEON_FP_FPON); 1044 } 1045 1046 pmf_event_register(dev, PMFE_DISPLAY_BRIGHTNESS_UP, 1047 radeonfb_brightness_up, TRUE); 1048 pmf_event_register(dev, PMFE_DISPLAY_BRIGHTNESS_DOWN, 1049 radeonfb_brightness_down, TRUE); 1050 1051 /* 1052 * if we attach a DRM we need to unmap registers in 1053 * WSDISPLAYIO_MODE_MAPPED, since this keeps us from doing things like 1054 * screen blanking we only do it if needed 1055 */ 1056 sc->sc_needs_unmap = 1057 (config_found_ia(dev, "drm", aux, radeonfb_drm_print) != 0); 1058 DPRINTF(("needs_unmap: %d\n", sc->sc_needs_unmap)); 1059 1060 if (!IS_AVIVO(sc)) { 1061 PRINTREG(RADEON_CRTC_EXT_CNTL); 1062 PRINTREG(RADEON_CRTC_GEN_CNTL); 1063 PRINTREG(RADEON_CRTC2_GEN_CNTL); 1064 PRINTREG(RADEON_DISP_OUTPUT_CNTL); 1065 PRINTREG(RADEON_DAC_CNTL2); 1066 PRINTREG(RADEON_FP_GEN_CNTL); 1067 PRINTREG(RADEON_FP2_GEN_CNTL); 1068 PRINTREG(RADEON_TMDS_CNTL); 1069 PRINTREG(RADEON_TMDS_TRANSMITTER_CNTL); 1070 PRINTREG(RADEON_TMDS_PLL_CNTL); 1071 PRINTREG(RADEON_PIXCLKS_CNTL); 1072 } 1073 return; 1074 1075 error: 1076 if (sc->sc_biossz) 1077 free(sc->sc_bios, M_DEVBUF); 1078 1079 if (sc->sc_regsz) 1080 bus_space_unmap(sc->sc_regt, sc->sc_regh, sc->sc_regsz); 1081 1082 if (sc->sc_memsz) 1083 bus_space_unmap(sc->sc_memt, sc->sc_memh, sc->sc_memsz); 1084 } 1085 1086 static void 1087 radeonfb_map(struct radeonfb_softc *sc) 1088 { 1089 if (!sc->sc_mapped) { 1090 if (bus_space_map(sc->sc_regt, sc->sc_regaddr, sc->sc_regsz, 0, 1091 &sc->sc_regh) != 0) { 1092 aprint_error_dev(sc->sc_dev, 1093 "unable to map registers!\n"); 1094 return; 1095 } 1096 if (bus_space_map(sc->sc_memt, sc->sc_memaddr, sc->sc_memsz, 1097 BUS_SPACE_MAP_LINEAR, &sc->sc_memh) != 0) { 1098 sc->sc_memsz = 0; 1099 aprint_error_dev(sc->sc_dev, 1100 "Unable to map frame buffer\n"); 1101 return; 1102 } 1103 sc->sc_mapped = TRUE; 1104 } 1105 } 1106 1107 static void 1108 radeonfb_unmap(struct radeonfb_softc *sc) 1109 { 1110 if (!sc->sc_needs_unmap) 1111 return; 1112 1113 if (sc->sc_mapped) { 1114 bus_space_unmap(sc->sc_regt, sc->sc_regh, sc->sc_regsz); 1115 bus_space_unmap(sc->sc_memt, sc->sc_memh, sc->sc_memsz); 1116 sc->sc_mapped = FALSE; 1117 } 1118 } 1119 1120 static int 1121 radeonfb_drm_print(void *aux, const char *pnp) 1122 { 1123 if (pnp) 1124 aprint_normal("drm at %s", pnp); 1125 return (UNCONF); 1126 } 1127 1128 int 1129 radeonfb_ioctl(void *v, void *vs, 1130 unsigned long cmd, void *d, int flag, struct lwp *l) 1131 { 1132 struct vcons_data *vd; 1133 struct radeonfb_display *dp; 1134 struct radeonfb_softc *sc; 1135 struct wsdisplay_param *param; 1136 struct vcons_screen *ms; 1137 1138 vd = (struct vcons_data *)v; 1139 ms = vd->active; 1140 dp = (struct radeonfb_display *)vd->cookie; 1141 sc = dp->rd_softc; 1142 1143 /* can't do these without registers being mapped */ 1144 if (!sc->sc_mapped) { 1145 switch (cmd) { 1146 case WSDISPLAYIO_GVIDEO: 1147 case WSDISPLAYIO_SVIDEO: 1148 case WSDISPLAYIO_GETCMAP: 1149 case WSDISPLAYIO_PUTCMAP: 1150 case WSDISPLAYIO_SCURSOR: 1151 case WSDISPLAYIO_GCURPOS: 1152 case WSDISPLAYIO_SCURPOS: 1153 case WSDISPLAYIO_SETPARAM: 1154 return EINVAL; 1155 } 1156 } 1157 1158 switch (cmd) { 1159 case WSDISPLAYIO_GTYPE: 1160 *(unsigned *)d = WSDISPLAY_TYPE_PCIMISC; 1161 return 0; 1162 1163 case WSDISPLAYIO_GINFO: 1164 if (vd->active != NULL) { 1165 struct wsdisplay_fbinfo *fb; 1166 fb = (struct wsdisplay_fbinfo *)d; 1167 fb->width = dp->rd_virtx; 1168 fb->height = dp->rd_virty; 1169 fb->depth = dp->rd_bpp; 1170 fb->cmsize = 256; 1171 return 0; 1172 } else 1173 return ENODEV; 1174 case WSDISPLAYIO_GVIDEO: 1175 if (radeonfb_isblank(dp)) 1176 *(unsigned *)d = WSDISPLAYIO_VIDEO_OFF; 1177 else 1178 *(unsigned *)d = WSDISPLAYIO_VIDEO_ON; 1179 return 0; 1180 1181 case WSDISPLAYIO_SVIDEO: 1182 if (dp->rd_wsmode != WSDISPLAYIO_MODE_MAPPED) { 1183 radeonfb_blank(dp, 1184 (*(unsigned int *)d == WSDISPLAYIO_VIDEO_OFF)); 1185 radeonfb_switch_backlight(dp, 1186 (*(unsigned int *)d == WSDISPLAYIO_VIDEO_ON)); 1187 } 1188 pmf_event_inject(NULL, 1189 (*(unsigned int *)d == WSDISPLAYIO_VIDEO_ON) ? 1190 PMFE_DISPLAY_ON : PMFE_DISPLAY_OFF); 1191 return 0; 1192 1193 case WSDISPLAYIO_GETCMAP: 1194 if (dp->rd_bpp == 8) 1195 return radeonfb_getcmap(dp, 1196 (struct wsdisplay_cmap *)d); 1197 return EINVAL; 1198 1199 case WSDISPLAYIO_PUTCMAP: 1200 if (dp->rd_bpp == 8) 1201 return radeonfb_putcmap(dp, 1202 (struct wsdisplay_cmap *)d); 1203 return EINVAL; 1204 1205 case WSDISPLAYIO_LINEBYTES: 1206 *(unsigned *)d = dp->rd_stride; 1207 return 0; 1208 1209 case WSDISPLAYIO_SMODE: 1210 if (*(int *)d != dp->rd_wsmode) { 1211 dp->rd_wsmode = *(int *)d; 1212 if ((dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) || 1213 (dp->rd_wsmode == WSDISPLAYIO_MODE_DUMBFB)) 1214 radeonfb_map(sc); 1215 1216 if ((dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) && 1217 (dp->rd_vd.active)) { 1218 radeonfb_engine_init(dp); 1219 glyphcache_wipe(&dp->rd_gc); 1220 radeonfb_init_palette(dp); 1221 radeonfb_modeswitch(dp); 1222 radeonfb_rectfill(dp, 0, 0, dp->rd_virtx, 1223 dp->rd_virty, dp->rd_bg); 1224 vcons_redraw_screen(dp->rd_vd.active); 1225 } 1226 if (dp->rd_wsmode == WSDISPLAYIO_MODE_MAPPED) 1227 radeonfb_unmap(sc); 1228 } 1229 return 0; 1230 1231 case WSDISPLAYIO_GCURMAX: 1232 ((struct wsdisplay_curpos *)d)->x = RADEON_CURSORMAXX; 1233 ((struct wsdisplay_curpos *)d)->y = RADEON_CURSORMAXY; 1234 return 0; 1235 1236 case WSDISPLAYIO_SCURSOR: 1237 return radeonfb_set_cursor(dp, (struct wsdisplay_cursor *)d); 1238 1239 case WSDISPLAYIO_GCURSOR: 1240 return EPASSTHROUGH; 1241 1242 case WSDISPLAYIO_GCURPOS: 1243 ((struct wsdisplay_curpos *)d)->x = dp->rd_cursor.rc_pos.x; 1244 ((struct wsdisplay_curpos *)d)->y = dp->rd_cursor.rc_pos.y; 1245 return 0; 1246 1247 case WSDISPLAYIO_SCURPOS: 1248 return radeonfb_set_curpos(dp, (struct wsdisplay_curpos *)d); 1249 1250 case WSDISPLAYIO_SSPLASH: 1251 #if defined(SPLASHSCREEN) 1252 if (*(int *)d == 1) { 1253 SCREEN_DISABLE_DRAWING(&dp->rd_vscreen); 1254 splash_render(&dp->rd_splash, 1255 SPLASH_F_CENTER|SPLASH_F_FILL); 1256 } else 1257 SCREEN_ENABLE_DRAWING(&dp->rd_vscreen); 1258 return 0; 1259 #else 1260 return ENODEV; 1261 #endif 1262 case WSDISPLAYIO_GETPARAM: 1263 param = (struct wsdisplay_param *)d; 1264 switch (param->param) { 1265 case WSDISPLAYIO_PARAM_BRIGHTNESS: 1266 param->min = 0; 1267 param->max = 255; 1268 param->curval = dp->rd_bl_level; 1269 return 0; 1270 case WSDISPLAYIO_PARAM_BACKLIGHT: 1271 param->min = 0; 1272 param->max = RADEONFB_BACKLIGHT_MAX; 1273 param->curval = dp->rd_bl_on; 1274 return 0; 1275 } 1276 return EPASSTHROUGH; 1277 1278 case WSDISPLAYIO_SETPARAM: 1279 param = (struct wsdisplay_param *)d; 1280 switch (param->param) { 1281 case WSDISPLAYIO_PARAM_BRIGHTNESS: 1282 radeonfb_set_backlight(dp, param->curval); 1283 return 0; 1284 case WSDISPLAYIO_PARAM_BACKLIGHT: 1285 radeonfb_switch_backlight(dp, param->curval); 1286 return 0; 1287 } 1288 return EPASSTHROUGH; 1289 1290 /* PCI config read/write passthrough. */ 1291 case PCI_IOC_CFGREAD: 1292 case PCI_IOC_CFGWRITE: 1293 return pci_devioctl(sc->sc_pc, sc->sc_pt, cmd, d, flag, l); 1294 1295 case WSDISPLAYIO_GET_BUSID: 1296 return wsdisplayio_busid_pci(sc->sc_dev, sc->sc_pc, 1297 sc->sc_pt, d); 1298 1299 case WSDISPLAYIO_GET_EDID: { 1300 struct wsdisplayio_edid_info *ei = d; 1301 return wsdisplayio_get_edid(sc->sc_dev, ei); 1302 } 1303 1304 case WSDISPLAYIO_GET_FBINFO: { 1305 struct wsdisplayio_fbinfo *fbi = d; 1306 return wsdisplayio_get_fbinfo(&ms->scr_ri, fbi); 1307 } 1308 1309 default: 1310 return EPASSTHROUGH; 1311 } 1312 } 1313 1314 paddr_t 1315 radeonfb_mmap(void *v, void *vs, off_t offset, int prot) 1316 { 1317 struct vcons_data *vd; 1318 struct radeonfb_display *dp; 1319 struct radeonfb_softc *sc; 1320 paddr_t pa; 1321 1322 vd = (struct vcons_data *)v; 1323 dp = (struct radeonfb_display *)vd->cookie; 1324 sc = dp->rd_softc; 1325 1326 if ((offset >= 0) && (offset < (dp->rd_virty * dp->rd_stride))) { 1327 pa = bus_space_mmap(sc->sc_memt, 1328 sc->sc_memaddr + dp->rd_offset + offset, 0, 1329 prot, BUS_SPACE_MAP_LINEAR); 1330 return pa; 1331 } 1332 1333 /* 1334 * restrict all other mappings to processes with superuser privileges 1335 * or the kernel itself 1336 */ 1337 if (kauth_authorize_machdep(kauth_cred_get(), KAUTH_MACHDEP_UNMANAGEDMEM, 1338 NULL, NULL, NULL, NULL) != 0) { 1339 aprint_error_dev(sc->sc_dev, "mmap() rejected.\n"); 1340 return -1; 1341 } 1342 1343 if ((offset >= sc->sc_regaddr) && 1344 (offset < sc->sc_regaddr + sc->sc_regsz)) { 1345 return bus_space_mmap(sc->sc_regt, offset, 0, prot, 1346 BUS_SPACE_MAP_LINEAR); 1347 } 1348 1349 if ((offset >= sc->sc_memaddr) && 1350 (offset < sc->sc_memaddr + sc->sc_memsz)) { 1351 return bus_space_mmap(sc->sc_memt, offset, 0, prot, 1352 BUS_SPACE_MAP_LINEAR); 1353 } 1354 1355 if ((offset >= sc->sc_romaddr) && 1356 (offset < sc->sc_romaddr + sc->sc_romsz)) { 1357 return bus_space_mmap(sc->sc_memt, offset, 0, prot, 1358 BUS_SPACE_MAP_LINEAR); 1359 } 1360 1361 #ifdef PCI_MAGIC_IO_RANGE 1362 /* allow mapping of IO space */ 1363 if ((offset >= PCI_MAGIC_IO_RANGE) && 1364 (offset < PCI_MAGIC_IO_RANGE + 0x10000)) { 1365 pa = bus_space_mmap(sc->sc_iot, offset - PCI_MAGIC_IO_RANGE, 1366 0, prot, 0); 1367 return pa; 1368 } 1369 #endif /* PCI_MAGIC_IO_RANGE */ 1370 1371 return -1; 1372 } 1373 1374 static void 1375 radeonfb_loadbios(struct radeonfb_softc *sc, const struct pci_attach_args *pa) 1376 { 1377 bus_space_tag_t romt; 1378 bus_space_handle_t romh, biosh; 1379 bus_size_t romsz; 1380 bus_addr_t ptr; 1381 uint32_t busctl, crtcg, crtc2g = 0, viphctl, seprom, extc; 1382 int bios_voodoo = 0; 1383 1384 if (pci_mapreg_map(pa, PCI_MAPREG_ROM, PCI_MAPREG_TYPE_ROM, 1385 BUS_SPACE_MAP_PREFETCHABLE, &romt, &romh, NULL, &romsz) != 0) { 1386 aprint_verbose("%s: unable to map BIOS!\n", XNAME(sc)); 1387 return; 1388 } 1389 1390 pci_find_rom(pa, romt, romh, romsz, PCI_ROM_CODE_TYPE_X86, &biosh, 1391 &sc->sc_biossz); 1392 if (sc->sc_biossz != 0) goto foundit; 1393 1394 aprint_verbose("trying to read disabled BIOS...\n"); 1395 1396 bios_voodoo = 1; 1397 seprom = radeonfb_get32(sc, RADEON_SEPROM_CNTL1); 1398 radeonfb_put32(sc, RADEON_SEPROM_CNTL1, 1399 (seprom & ~RADEON_SCK_PRESCALE_MASK) | 1400 (0xc << RADEON_SCK_PRESCALE_SHIFT)); 1401 viphctl = radeonfb_get32(sc, RADEON_VIPH_CONTROL); 1402 radeonfb_put32(sc, RADEON_VIPH_CONTROL, viphctl & ~RADEON_VIPH_EN); 1403 busctl = radeonfb_get32(sc, RADEON_BUS_CNTL); 1404 radeonfb_put32(sc, RADEON_BUS_CNTL, busctl & ~RADEON_BUS_BIOS_DIS_ROM); 1405 crtcg = radeonfb_get32(sc, RADEON_CRTC_GEN_CNTL); 1406 radeonfb_put32(sc, RADEON_CRTC_GEN_CNTL, ((crtcg & ~RADEON_CRTC_EN) | 1407 (RADEON_CRTC_DISP_REQ_EN_B | 1408 RADEON_CRTC_EXT_DISP_EN))); 1409 if (HAS_CRTC2(sc)) { 1410 crtc2g = radeonfb_get32(sc, RADEON_CRTC2_GEN_CNTL); 1411 radeonfb_put32(sc, RADEON_CRTC2_GEN_CNTL, 1412 (crtc2g & ~RADEON_CRTC2_EN) | 1413 RADEON_CRTC2_DISP_REQ_EN_B); 1414 } 1415 extc = radeonfb_get32(sc, RADEON_CRTC_EXT_CNTL); 1416 radeonfb_put32(sc, RADEON_CRTC_EXT_CNTL, (extc & ~RADEON_CRTC_CRT_ON) | 1417 (RADEON_CRTC_SYNC_TRISTAT | 1418 RADEON_CRTC_DISPLAY_DIS)); 1419 pci_find_rom(pa, romt, romh, romsz, PCI_ROM_CODE_TYPE_X86, &biosh, 1420 &sc->sc_biossz); 1421 1422 foundit: 1423 if (sc->sc_biossz > 0) { 1424 sc->sc_bios = malloc(sc->sc_biossz, M_DEVBUF, M_WAITOK); 1425 bus_space_read_region_1(romt, biosh, 0, sc->sc_bios, 1426 sc->sc_biossz); 1427 } 1428 1429 if (bios_voodoo != 0) { 1430 radeonfb_put32(sc, RADEON_CRTC_EXT_CNTL, extc); 1431 if (HAS_CRTC2(sc)) { 1432 radeonfb_put32(sc, RADEON_CRTC2_GEN_CNTL, crtc2g); 1433 } 1434 radeonfb_put32(sc, RADEON_CRTC_GEN_CNTL, crtcg); 1435 radeonfb_put32(sc, RADEON_BUS_CNTL, busctl); 1436 radeonfb_put32(sc, RADEON_VIPH_CONTROL, viphctl); 1437 radeonfb_put32(sc, RADEON_SEPROM_CNTL1, seprom); 1438 } 1439 1440 /* unmap the PCI expansion rom */ 1441 bus_space_unmap(romt, romh, romsz); 1442 1443 /* turn off rom decoder now */ 1444 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM, 1445 pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM) & 1446 ~PCI_MAPREG_ROM_ENABLE); 1447 1448 if (sc->sc_biossz > 0) { 1449 ptr = GETBIOS16(sc, 0x48); 1450 if ((GETBIOS32(sc, ptr + 4) == 0x41544f4d /* "ATOM" */) || 1451 (GETBIOS32(sc, ptr + 4) == 0x4d4f5441 /* "MOTA" */)) { 1452 sc->sc_flags |= RFB_ATOM; 1453 } 1454 1455 aprint_verbose("%s: Found %d KB %s BIOS\n", XNAME(sc), 1456 (unsigned)sc->sc_biossz >> 10, 1457 IS_ATOM(sc) ? "ATOM" : "Legacy"); 1458 } 1459 } 1460 1461 1462 uint32_t 1463 radeonfb_get32(struct radeonfb_softc *sc, uint32_t reg) 1464 { 1465 1466 return bus_space_read_4(sc->sc_regt, sc->sc_regh, reg); 1467 } 1468 1469 void 1470 radeonfb_put32(struct radeonfb_softc *sc, uint32_t reg, uint32_t val) 1471 { 1472 1473 bus_space_write_4(sc->sc_regt, sc->sc_regh, reg, val); 1474 } 1475 1476 void 1477 radeonfb_put32s(struct radeonfb_softc *sc, uint32_t reg, uint32_t val) 1478 { 1479 1480 bus_space_write_stream_4(sc->sc_regt, sc->sc_regh, reg, val); 1481 } 1482 1483 void 1484 radeonfb_mask32(struct radeonfb_softc *sc, uint32_t reg, 1485 uint32_t andmask, uint32_t ormask) 1486 { 1487 int s; 1488 uint32_t val; 1489 1490 s = splhigh(); 1491 val = radeonfb_get32(sc, reg); 1492 val = (val & andmask) | ormask; 1493 radeonfb_put32(sc, reg, val); 1494 splx(s); 1495 } 1496 1497 uint32_t 1498 radeonfb_getindex(struct radeonfb_softc *sc, uint32_t idx) 1499 { 1500 int s; 1501 uint32_t val; 1502 1503 s = splhigh(); 1504 radeonfb_put32(sc, RADEON_MM_INDEX, idx); 1505 val = radeonfb_get32(sc, RADEON_MM_DATA); 1506 splx(s); 1507 1508 return (val); 1509 } 1510 1511 void 1512 radeonfb_putindex(struct radeonfb_softc *sc, uint32_t idx, uint32_t val) 1513 { 1514 int s; 1515 1516 s = splhigh(); 1517 radeonfb_put32(sc, RADEON_MM_INDEX, idx); 1518 radeonfb_put32(sc, RADEON_MM_DATA, val); 1519 splx(s); 1520 } 1521 1522 void 1523 radeonfb_maskindex(struct radeonfb_softc *sc, uint32_t idx, 1524 uint32_t andmask, uint32_t ormask) 1525 { 1526 int s; 1527 uint32_t val; 1528 1529 s = splhigh(); 1530 radeonfb_put32(sc, RADEON_MM_INDEX, idx); 1531 val = radeonfb_get32(sc, RADEON_MM_DATA); 1532 val = (val & andmask) | ormask; 1533 radeonfb_put32(sc, RADEON_MM_DATA, val); 1534 splx(s); 1535 } 1536 1537 uint32_t 1538 radeonfb_getpll(struct radeonfb_softc *sc, uint32_t idx) 1539 { 1540 int s; 1541 uint32_t val; 1542 1543 s = splhigh(); 1544 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, (idx & 0x3f)); 1545 val = radeonfb_get32(sc, RADEON_CLOCK_CNTL_DATA); 1546 if (HAS_R300CG(sc)) 1547 radeonfb_r300cg_workaround(sc); 1548 splx(s); 1549 1550 return (val); 1551 } 1552 1553 void 1554 radeonfb_putpll(struct radeonfb_softc *sc, uint32_t idx, uint32_t val) 1555 { 1556 int s; 1557 1558 s = splhigh(); 1559 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, (idx & 0x3f) | 1560 RADEON_PLL_WR_EN); 1561 radeonfb_put32(sc, RADEON_CLOCK_CNTL_DATA, val); 1562 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, 0); 1563 splx(s); 1564 } 1565 1566 void 1567 radeonfb_maskpll(struct radeonfb_softc *sc, uint32_t idx, 1568 uint32_t andmask, uint32_t ormask) 1569 { 1570 int s; 1571 uint32_t val; 1572 1573 s = splhigh(); 1574 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, (idx & 0x3f) | 1575 RADEON_PLL_WR_EN); 1576 val = radeonfb_get32(sc, RADEON_CLOCK_CNTL_DATA); 1577 val = (val & andmask) | ormask; 1578 radeonfb_put32(sc, RADEON_CLOCK_CNTL_DATA, val); 1579 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, 0); 1580 splx(s); 1581 } 1582 1583 int 1584 radeonfb_scratch_test(struct radeonfb_softc *sc, int reg, uint32_t v) 1585 { 1586 uint32_t saved; 1587 1588 saved = GET32(sc, reg); 1589 PUT32(sc, reg, v); 1590 if (GET32(sc, reg) != v) { 1591 return -1; 1592 } 1593 PUT32(sc, reg, saved); 1594 return 0; 1595 } 1596 1597 uintmax_t 1598 radeonfb_getprop_num(struct radeonfb_softc *sc, const char *name, 1599 uintmax_t defval) 1600 { 1601 prop_number_t pn; 1602 pn = prop_dictionary_get(device_properties(sc->sc_dev), name); 1603 if (pn == NULL) { 1604 return defval; 1605 } 1606 KASSERT(prop_object_type(pn) == PROP_TYPE_NUMBER); 1607 return prop_number_unsigned_value(pn); 1608 } 1609 1610 int 1611 radeonfb_getclocks(struct radeonfb_softc *sc) 1612 { 1613 bus_addr_t ptr; 1614 int refclk = 0; 1615 int refdiv = 0; 1616 int minpll = 0; 1617 int maxpll = 0; 1618 1619 /* load initial property values if port/board provides them */ 1620 refclk = radeonfb_getprop_num(sc, "refclk", 0) & 0xffff; 1621 refdiv = radeonfb_getprop_num(sc, "refdiv", 0) & 0xffff; 1622 minpll = radeonfb_getprop_num(sc, "minpll", 0) & 0xffffffffU; 1623 maxpll = radeonfb_getprop_num(sc, "maxpll", 0) & 0xffffffffU; 1624 1625 PRINTPLL(RADEON_PPLL_REF_DIV); 1626 PRINTPLL(RADEON_PPLL_DIV_0); 1627 PRINTPLL(RADEON_PPLL_DIV_1); 1628 PRINTPLL(RADEON_PPLL_DIV_2); 1629 PRINTPLL(RADEON_PPLL_DIV_3); 1630 PRINTREG(RADEON_CLOCK_CNTL_INDEX); 1631 PRINTPLL(RADEON_P2PLL_REF_DIV); 1632 PRINTPLL(RADEON_P2PLL_DIV_0); 1633 1634 if (refclk && refdiv && minpll && maxpll) 1635 goto dontprobe; 1636 1637 if (!sc->sc_biossz) { 1638 /* no BIOS */ 1639 aprint_verbose("%s: No video BIOS, using default clocks\n", 1640 XNAME(sc)); 1641 if (IS_IGP(sc)) 1642 refclk = refclk ? refclk : 1432; 1643 else 1644 refclk = refclk ? refclk : 2700; 1645 refdiv = refdiv ? refdiv : 12; 1646 minpll = minpll ? minpll : 12500; 1647 /* XXX 1648 * Need to check if the firmware or something programmed a 1649 * higher value than this, and if so, bump it. 1650 * The RV280 in my iBook is unhappy if the PLL input is less 1651 * than 360MHz 1652 */ 1653 maxpll = maxpll ? maxpll : 40000/*35000*/; 1654 } else if (IS_ATOM(sc)) { 1655 /* ATOM BIOS */ 1656 ptr = GETBIOS16(sc, 0x48); 1657 ptr = GETBIOS16(sc, ptr + 32); /* aka MasterDataStart */ 1658 ptr = GETBIOS16(sc, ptr + 12); /* pll info block */ 1659 refclk = refclk ? refclk : GETBIOS16(sc, ptr + 82); 1660 minpll = minpll ? minpll : GETBIOS16(sc, ptr + 78); 1661 maxpll = maxpll ? maxpll : GETBIOS16(sc, ptr + 32); 1662 /* 1663 * ATOM BIOS doesn't supply a reference divider, so we 1664 * have to probe for it. 1665 */ 1666 if (refdiv < 2) 1667 refdiv = GETPLL(sc, RADEON_PPLL_REF_DIV) & 1668 RADEON_PPLL_REF_DIV_MASK; 1669 /* 1670 * if probe is zero, just assume one that should work 1671 * for most parts 1672 */ 1673 if (refdiv < 2) 1674 refdiv = 12; 1675 1676 } else { 1677 uint32_t tmp = GETPLL(sc, RADEON_PPLL_REF_DIV); 1678 /* Legacy BIOS */ 1679 ptr = GETBIOS16(sc, 0x48); 1680 ptr = GETBIOS16(sc, ptr + 0x30); 1681 if (IS_R300(sc)) { 1682 refdiv = refdiv ? refdiv : 1683 (tmp & R300_PPLL_REF_DIV_ACC_MASK) >> 1684 R300_PPLL_REF_DIV_ACC_SHIFT; 1685 } else { 1686 refdiv = refdiv ? refdiv : 1687 tmp & RADEON_PPLL_REF_DIV_MASK; 1688 } 1689 refclk = refclk ? refclk : GETBIOS16(sc, ptr + 0x0E); 1690 refdiv = refdiv ? refdiv : GETBIOS16(sc, ptr + 0x10); 1691 minpll = minpll ? minpll : GETBIOS32(sc, ptr + 0x12); 1692 maxpll = maxpll ? maxpll : GETBIOS32(sc, ptr + 0x16); 1693 } 1694 1695 1696 dontprobe: 1697 sc->sc_refclk = refclk * 10; 1698 sc->sc_refdiv = refdiv; 1699 sc->sc_minpll = minpll * 10; 1700 sc->sc_maxpll = maxpll * 10; 1701 return 0; 1702 } 1703 1704 int 1705 radeonfb_calc_dividers(struct radeonfb_softc *sc, uint32_t dotclock, 1706 uint32_t *postdivbit, uint32_t *feedbackdiv, int flags) 1707 { 1708 int i; 1709 uint32_t outfreq; 1710 int div; 1711 1712 DPRINTF(("dot clock: %u\n", dotclock)); 1713 for (i = 0; (div = radeonfb_dividers[i].divider) != 0; i++) { 1714 1715 if ((flags & NO_ODD_FBDIV) && ((div & 1) != 0)) 1716 continue; 1717 1718 /* 1719 * XXX 1720 * the rv350 in my last generation 14" iBook G4 produces 1721 * garbage with dividers > 4. No idea if this is a hardware 1722 * limitation or an error in the divider table. 1723 */ 1724 if ((sc->sc_family == RADEON_RV350) && (div > 4)) 1725 continue; 1726 1727 outfreq = div * dotclock; 1728 if ((outfreq >= sc->sc_minpll) && 1729 (outfreq <= sc->sc_maxpll)) { 1730 DPRINTF(("outfreq: %u\n", outfreq)); 1731 *postdivbit = 1732 ((uint32_t)radeonfb_dividers[i].mask << 16); 1733 DPRINTF(("post divider: %d (mask %x)\n", div, 1734 *postdivbit)); 1735 break; 1736 } 1737 } 1738 1739 if (div == 0) 1740 return 1; 1741 1742 *feedbackdiv = DIVIDE(sc->sc_refdiv * outfreq, sc->sc_refclk); 1743 DPRINTF(("feedback divider: %d\n", *feedbackdiv)); 1744 return 0; 1745 } 1746 1747 #if 0 1748 #ifdef RADEONFB_DEBUG 1749 static void 1750 dump_buffer(const char *pfx, void *buffer, unsigned int size) 1751 { 1752 char asc[17]; 1753 unsigned ptr = (unsigned)buffer; 1754 char *start = (char *)(ptr & ~0xf); 1755 char *end = (char *)(ptr + size); 1756 1757 end = (char *)(((unsigned)end + 0xf) & ~0xf); 1758 1759 if (pfx == NULL) { 1760 pfx = ""; 1761 } 1762 1763 while (start < end) { 1764 unsigned offset = (unsigned)start & 0xf; 1765 if (offset == 0) { 1766 printf("%s%x: ", pfx, (unsigned)start); 1767 } 1768 if (((unsigned)start < ptr) || 1769 ((unsigned)start >= (ptr + size))) { 1770 printf(" "); 1771 asc[offset] = ' '; 1772 } else { 1773 printf("%02x", *(unsigned char *)start); 1774 if ((*start >= ' ') && (*start <= '~')) { 1775 asc[offset] = *start; 1776 } else { 1777 asc[offset] = '.'; 1778 } 1779 } 1780 asc[offset + 1] = 0; 1781 if (offset % 2) { 1782 printf(" "); 1783 } 1784 if (offset == 15) { 1785 printf(" %s\n", asc); 1786 } 1787 start++; 1788 } 1789 } 1790 #endif 1791 #endif 1792 1793 int 1794 radeonfb_getconnectors(struct radeonfb_softc *sc) 1795 { 1796 int i; 1797 int found = 0; 1798 1799 for (i = 0; i < 2; i++) { 1800 sc->sc_ports[i].rp_mon_type = RADEON_MT_UNKNOWN; 1801 sc->sc_ports[i].rp_ddc_type = RADEON_DDC_NONE; 1802 sc->sc_ports[i].rp_dac_type = RADEON_DAC_UNKNOWN; 1803 sc->sc_ports[i].rp_conn_type = RADEON_CONN_NONE; 1804 sc->sc_ports[i].rp_tmds_type = RADEON_TMDS_UNKNOWN; 1805 } 1806 1807 /* 1808 * This logic is borrowed from Xorg's radeon driver. 1809 */ 1810 if (!sc->sc_biossz) 1811 goto nobios; 1812 1813 if (IS_ATOM(sc)) { 1814 /* not done yet */ 1815 } else { 1816 uint16_t ptr; 1817 int port = 0; 1818 1819 ptr = GETBIOS16(sc, 0x48); 1820 ptr = GETBIOS16(sc, ptr + 0x50); 1821 for (i = 1; i < 4; i++) { 1822 uint16_t entry; 1823 uint8_t conn, ddc, dac, tmds; 1824 1825 /* 1826 * Parse the connector table. From reading the code, 1827 * it appears to made up of 16-bit entries for each 1828 * connector. The 16-bits are defined as: 1829 * 1830 * bits 12-15 - connector type (0 == end of table) 1831 * bits 8-11 - DDC type 1832 * bits 5-7 - ??? 1833 * bit 4 - TMDS type (1 = EXT, 0 = INT) 1834 * bits 1-3 - ??? 1835 * bit 0 - DAC, 1 = TVDAC, 0 = primary 1836 */ 1837 if (!GETBIOS8(sc, ptr + i * 2) && i > 1) 1838 break; 1839 entry = GETBIOS16(sc, ptr + i * 2); 1840 1841 conn = (entry >> 12) & 0xf; 1842 ddc = (entry >> 8) & 0xf; 1843 dac = (entry & 0x1) ? RADEON_DAC_TVDAC : 1844 RADEON_DAC_PRIMARY; 1845 tmds = ((entry >> 4) & 0x1) ? RADEON_TMDS_EXT : 1846 RADEON_TMDS_INT; 1847 1848 if (conn == RADEON_CONN_NONE) 1849 continue; /* no connector */ 1850 1851 /* 1852 * XXX 1853 * both Mac Mini variants have both outputs wired to 1854 * the same connector and share the DDC lines 1855 */ 1856 if ((found > 0) && 1857 (sc->sc_ports[port].rp_ddc_type == ddc)) { 1858 /* duplicate entry for same connector */ 1859 continue; 1860 } 1861 1862 /* internal DDC_DVI port gets priority */ 1863 if ((ddc == RADEON_DDC_DVI) || (port == 1)) 1864 port = 0; 1865 else 1866 port = 1; 1867 1868 sc->sc_ports[port].rp_ddc_type = 1869 ddc > RADEON_DDC_CRT2 ? RADEON_DDC_NONE : ddc; 1870 sc->sc_ports[port].rp_dac_type = dac; 1871 sc->sc_ports[port].rp_conn_type = 1872 uimin(conn, RADEON_CONN_UNSUPPORTED) ; 1873 1874 sc->sc_ports[port].rp_tmds_type = tmds; 1875 1876 if ((conn != RADEON_CONN_DVI_I) && 1877 (conn != RADEON_CONN_DVI_D) && 1878 (tmds == RADEON_TMDS_INT)) 1879 sc->sc_ports[port].rp_tmds_type = 1880 RADEON_TMDS_UNKNOWN; 1881 sc->sc_ports[port].rp_number = i - 1; 1882 1883 found += (port + 1); 1884 } 1885 } 1886 1887 nobios: 1888 if (!found) { 1889 bool dvi_ext = FALSE, dvi_int = FALSE; 1890 DPRINTF(("No connector info in BIOS!\n")); 1891 prop_dictionary_get_bool(device_properties(sc->sc_dev), 1892 "dvi-internal", &dvi_int); 1893 prop_dictionary_get_bool(device_properties(sc->sc_dev), 1894 "dvi-external", &dvi_ext); 1895 if (dvi_ext) { 1896 sc->sc_ports[0].rp_mon_type = RADEON_MT_UNKNOWN; 1897 sc->sc_ports[0].rp_ddc_type = RADEON_DDC_CRT2; 1898 sc->sc_ports[0].rp_dac_type = RADEON_DAC_PRIMARY; 1899 sc->sc_ports[0].rp_conn_type = RADEON_CONN_DVI_I; 1900 sc->sc_ports[0].rp_tmds_type = RADEON_TMDS_EXT; /* output to fp2 */ 1901 sc->sc_ports[0].rp_number = 0; 1902 sc->sc_ports[1].rp_mon_type = RADEON_MT_UNKNOWN; 1903 sc->sc_ports[1].rp_ddc_type = RADEON_DDC_NONE; 1904 sc->sc_ports[1].rp_dac_type = RADEON_DAC_UNKNOWN; 1905 sc->sc_ports[1].rp_conn_type = RADEON_CONN_NONE; 1906 sc->sc_ports[1].rp_tmds_type = RADEON_TMDS_UNKNOWN; 1907 sc->sc_ports[1].rp_number = 1; 1908 } else if (dvi_int) { 1909 sc->sc_ports[0].rp_mon_type = RADEON_MT_UNKNOWN; 1910 sc->sc_ports[0].rp_ddc_type = RADEON_DDC_CRT2; 1911 sc->sc_ports[0].rp_dac_type = RADEON_DAC_PRIMARY; 1912 sc->sc_ports[0].rp_conn_type = RADEON_CONN_DVI_I; 1913 sc->sc_ports[0].rp_tmds_type = RADEON_TMDS_INT; 1914 sc->sc_ports[0].rp_number = 0; 1915 sc->sc_ports[1].rp_mon_type = RADEON_MT_UNKNOWN; 1916 sc->sc_ports[1].rp_ddc_type = RADEON_DDC_NONE; 1917 sc->sc_ports[1].rp_dac_type = RADEON_DAC_UNKNOWN; 1918 sc->sc_ports[1].rp_conn_type = RADEON_CONN_NONE; 1919 sc->sc_ports[1].rp_tmds_type = RADEON_TMDS_UNKNOWN; 1920 sc->sc_ports[1].rp_number = 1; 1921 } else if IS_MOBILITY(sc) { 1922 /* default, port 0 = internal TMDS, port 1 = CRT */ 1923 sc->sc_ports[0].rp_mon_type = RADEON_MT_UNKNOWN; 1924 sc->sc_ports[0].rp_ddc_type = RADEON_DDC_DVI; 1925 sc->sc_ports[0].rp_dac_type = RADEON_DAC_TVDAC; 1926 sc->sc_ports[0].rp_conn_type = RADEON_CONN_DVI_D; 1927 sc->sc_ports[0].rp_tmds_type = RADEON_TMDS_INT; 1928 sc->sc_ports[0].rp_number = 0; 1929 1930 sc->sc_ports[1].rp_mon_type = RADEON_MT_UNKNOWN; 1931 sc->sc_ports[1].rp_ddc_type = RADEON_DDC_VGA; 1932 sc->sc_ports[1].rp_dac_type = RADEON_DAC_PRIMARY; 1933 sc->sc_ports[1].rp_conn_type = RADEON_CONN_CRT; 1934 sc->sc_ports[1].rp_tmds_type = RADEON_TMDS_EXT; 1935 sc->sc_ports[1].rp_number = 1; 1936 } else { 1937 /* default, port 0 = DVI, port 1 = CRT */ 1938 sc->sc_ports[0].rp_mon_type = RADEON_MT_UNKNOWN; 1939 sc->sc_ports[0].rp_ddc_type = RADEON_DDC_DVI; 1940 sc->sc_ports[0].rp_dac_type = RADEON_DAC_TVDAC; 1941 sc->sc_ports[0].rp_conn_type = RADEON_CONN_DVI_D; 1942 sc->sc_ports[0].rp_tmds_type = RADEON_TMDS_INT; 1943 sc->sc_ports[0].rp_number = 0; 1944 1945 sc->sc_ports[1].rp_mon_type = RADEON_MT_UNKNOWN; 1946 sc->sc_ports[1].rp_ddc_type = RADEON_DDC_VGA; 1947 sc->sc_ports[1].rp_dac_type = RADEON_DAC_PRIMARY; 1948 sc->sc_ports[1].rp_conn_type = RADEON_CONN_CRT; 1949 sc->sc_ports[1].rp_tmds_type = RADEON_TMDS_UNKNOWN; 1950 sc->sc_ports[1].rp_number = 1; 1951 } 1952 } 1953 1954 /* 1955 * Fixup for RS300/RS350/RS400 chips, that lack a primary DAC. 1956 * these chips should use TVDAC for the VGA port. 1957 */ 1958 if (HAS_SDAC(sc)) { 1959 if (sc->sc_ports[0].rp_conn_type == RADEON_CONN_CRT) { 1960 sc->sc_ports[0].rp_dac_type = RADEON_DAC_TVDAC; 1961 sc->sc_ports[1].rp_dac_type = RADEON_DAC_PRIMARY; 1962 } else { 1963 sc->sc_ports[1].rp_dac_type = RADEON_DAC_TVDAC; 1964 sc->sc_ports[0].rp_dac_type = RADEON_DAC_PRIMARY; 1965 } 1966 } else if (!HAS_CRTC2(sc)) { 1967 sc->sc_ports[0].rp_dac_type = RADEON_DAC_PRIMARY; 1968 } 1969 1970 for (i = 0; i < 2; i++) { 1971 char edid[128]; 1972 uint8_t ddc; 1973 struct edid_info *eip = &sc->sc_ports[i].rp_edid; 1974 prop_data_t edid_data; 1975 1976 DPRINTF(("Port #%d:\n", i)); 1977 DPRINTF((" conn = %d\n", sc->sc_ports[i].rp_conn_type)); 1978 DPRINTF((" ddc = %d\n", sc->sc_ports[i].rp_ddc_type)); 1979 DPRINTF((" dac = %d\n", sc->sc_ports[i].rp_dac_type)); 1980 DPRINTF((" tmds = %d\n", sc->sc_ports[i].rp_tmds_type)); 1981 DPRINTF((" crtc = %d\n", sc->sc_ports[i].rp_number)); 1982 1983 sc->sc_ports[i].rp_edid_valid = 0; 1984 /* first look for static EDID data */ 1985 if ((edid_data = prop_dictionary_get(device_properties( 1986 sc->sc_dev), "EDID")) != NULL) { 1987 1988 aprint_debug_dev(sc->sc_dev, "using static EDID\n"); 1989 memcpy(edid, prop_data_value(edid_data), 128); 1990 if (edid_parse(edid, eip) == 0) { 1991 1992 sc->sc_ports[i].rp_edid_valid = 1; 1993 #ifdef RADEONFB_DEBUG 1994 edid_print(eip); 1995 #endif 1996 } 1997 } 1998 /* if we didn't find any we'll try to talk to the monitor */ 1999 if (sc->sc_ports[i].rp_edid_valid != 1) { 2000 2001 ddc = sc->sc_ports[i].rp_ddc_type; 2002 if (ddc != RADEON_DDC_NONE) { 2003 if ((radeonfb_i2c_read_edid(sc, ddc, edid) 2004 == 0) && (edid_parse(edid, eip) == 0)) { 2005 2006 sc->sc_ports[i].rp_edid_valid = 1; 2007 #ifdef RADEONFB_DEBUG 2008 edid_print(eip); 2009 #endif 2010 } 2011 } 2012 } 2013 } 2014 2015 return found; 2016 } 2017 2018 int 2019 radeonfb_gettmds(struct radeonfb_softc *sc) 2020 { 2021 int i; 2022 2023 if (!sc->sc_biossz) { 2024 goto nobios; 2025 } 2026 2027 if (IS_ATOM(sc)) { 2028 /* XXX: not done yet */ 2029 } else { 2030 uint16_t ptr; 2031 int n; 2032 2033 ptr = GETBIOS16(sc, 0x48); 2034 ptr = GETBIOS16(sc, ptr + 0x34); 2035 DPRINTF(("DFP table revision %d\n", GETBIOS8(sc, ptr))); 2036 if (GETBIOS8(sc, ptr) == 3) { 2037 /* revision three table */ 2038 n = GETBIOS8(sc, ptr + 5) + 1; 2039 n = uimin(n, 4); 2040 2041 memset(sc->sc_tmds_pll, 0, sizeof (sc->sc_tmds_pll)); 2042 for (i = 0; i < n; i++) { 2043 sc->sc_tmds_pll[i].rtp_pll = GETBIOS32(sc, 2044 ptr + i * 10 + 8); 2045 sc->sc_tmds_pll[i].rtp_freq = GETBIOS16(sc, 2046 ptr + i * 10 + 0x10); 2047 DPRINTF(("TMDS_PLL dot clock %d pll %x\n", 2048 sc->sc_tmds_pll[i].rtp_freq, 2049 sc->sc_tmds_pll[i].rtp_pll)); 2050 } 2051 return 0; 2052 } 2053 } 2054 2055 nobios: 2056 DPRINTF(("no suitable DFP table present\n")); 2057 for (i = 0; 2058 i < sizeof (radeonfb_tmds_pll) / sizeof (radeonfb_tmds_pll[0]); 2059 i++) { 2060 int j; 2061 2062 if (radeonfb_tmds_pll[i].family != sc->sc_family) 2063 continue; 2064 2065 for (j = 0; j < 4; j++) { 2066 sc->sc_tmds_pll[j] = radeonfb_tmds_pll[i].plls[j]; 2067 DPRINTF(("TMDS_PLL dot clock %d pll %x\n", 2068 sc->sc_tmds_pll[j].rtp_freq, 2069 sc->sc_tmds_pll[j].rtp_pll)); 2070 } 2071 return 0; 2072 } 2073 2074 return -1; 2075 } 2076 2077 const struct videomode * 2078 radeonfb_modelookup(const char *name) 2079 { 2080 int i; 2081 2082 for (i = 0; i < videomode_count; i++) { 2083 if (!strcmp(name, videomode_list[i].name)) 2084 return &videomode_list[i]; 2085 } 2086 return NULL; 2087 } 2088 2089 void 2090 radeonfb_pllwriteupdate(struct radeonfb_softc *sc, int crtc) 2091 { 2092 if (crtc) { 2093 while (GETPLL(sc, RADEON_P2PLL_REF_DIV) & 2094 RADEON_P2PLL_ATOMIC_UPDATE_R); 2095 SETPLL(sc, RADEON_P2PLL_REF_DIV, RADEON_P2PLL_ATOMIC_UPDATE_W); 2096 } else { 2097 while (GETPLL(sc, RADEON_PPLL_REF_DIV) & 2098 RADEON_PPLL_ATOMIC_UPDATE_R); 2099 SETPLL(sc, RADEON_PPLL_REF_DIV, RADEON_PPLL_ATOMIC_UPDATE_W); 2100 } 2101 } 2102 2103 void 2104 radeonfb_pllwaitatomicread(struct radeonfb_softc *sc, int crtc) 2105 { 2106 int i; 2107 2108 for (i = 10000; i; i--) { 2109 if (crtc) { 2110 if (GETPLL(sc, RADEON_P2PLL_REF_DIV) & 2111 RADEON_P2PLL_ATOMIC_UPDATE_R) 2112 break; 2113 } else { 2114 if (GETPLL(sc, RADEON_PPLL_REF_DIV) & 2115 RADEON_PPLL_ATOMIC_UPDATE_R) 2116 break; 2117 } 2118 } 2119 } 2120 2121 void 2122 radeonfb_program_vclk(struct radeonfb_softc *sc, int dotclock, int crtc, int flags) 2123 { 2124 uint32_t pbit = 0; 2125 uint32_t feed = 0; 2126 uint32_t data, refdiv, div0, r2xxref; 2127 2128 radeonfb_calc_dividers(sc, dotclock, &pbit, &feed, flags); 2129 2130 if (crtc == 0) { 2131 2132 refdiv = GETPLL(sc, RADEON_PPLL_REF_DIV); 2133 2134 /* 2135 * XXX 2136 * the RV350 in my last generation iBook G4 behaves like an 2137 * r2xx here - try to detect that and not screw up the reference 2138 * divider. 2139 * xf86-video-radeon just skips PLL programming altogether 2140 * on iBooks, probably for this reason. 2141 */ 2142 r2xxref = (refdiv & ~RADEON_PPLL_REF_DIV_MASK) | sc->sc_refdiv; 2143 if (IS_R300(sc) && (r2xxref != refdiv)) { 2144 refdiv = (refdiv & ~R300_PPLL_REF_DIV_ACC_MASK) | 2145 (sc->sc_refdiv << R300_PPLL_REF_DIV_ACC_SHIFT); 2146 } else { 2147 refdiv = (refdiv & ~RADEON_PPLL_REF_DIV_MASK) | 2148 sc->sc_refdiv; 2149 } 2150 DPRINTF(("refdiv %08x\n", refdiv)); 2151 div0 = GETPLL(sc, RADEON_PPLL_DIV_0); 2152 DPRINTF(("div0 %08x\n", div0)); 2153 div0 &= ~(RADEON_PPLL_FB3_DIV_MASK | 2154 RADEON_PPLL_POST3_DIV_MASK); 2155 div0 |= pbit; 2156 div0 |= (feed & RADEON_PPLL_FB3_DIV_MASK); 2157 DPRINTF(("div0 %08x\n", div0)); 2158 2159 if ((refdiv == GETPLL(sc, RADEON_PPLL_REF_DIV)) && 2160 (div0 == GETPLL(sc, RADEON_PPLL_DIV_0))) { 2161 /* 2162 * nothing to do here, the PLL is already where we 2163 * want it 2164 */ 2165 PATCH32(sc, RADEON_CLOCK_CNTL_INDEX, 0, 2166 ~RADEON_PLL_DIV_SEL); 2167 aprint_debug_dev(sc->sc_dev, "no need to touch the PLL\n"); 2168 return; 2169 } 2170 2171 /* alright, we do need to reprogram stuff */ 2172 PATCHPLL(sc, RADEON_VCLK_ECP_CNTL, 2173 RADEON_VCLK_SRC_SEL_CPUCLK, 2174 ~RADEON_VCLK_SRC_SEL_MASK); 2175 2176 /* put vclk into reset, use atomic updates */ 2177 SETPLL(sc, RADEON_PPLL_CNTL, 2178 RADEON_PPLL_REFCLK_SEL | 2179 RADEON_PPLL_FBCLK_SEL | 2180 RADEON_PPLL_RESET | 2181 RADEON_PPLL_ATOMIC_UPDATE_EN | 2182 RADEON_PPLL_VGA_ATOMIC_UPDATE_EN); 2183 2184 /* select clock 0 */ 2185 PATCH32(sc, RADEON_CLOCK_CNTL_INDEX, 0, 2186 ~RADEON_PLL_DIV_SEL); 2187 2188 PUTPLL(sc, RADEON_PPLL_REF_DIV, refdiv); 2189 2190 /* xf86-video-radeon does this, not sure why */ 2191 PUTPLL(sc, RADEON_PPLL_DIV_0, div0); 2192 PUTPLL(sc, RADEON_PPLL_DIV_0, div0); 2193 2194 /* use the atomic update */ 2195 radeonfb_pllwriteupdate(sc, crtc); 2196 2197 /* and wait for it to complete */ 2198 radeonfb_pllwaitatomicread(sc, crtc); 2199 2200 /* program HTOTAL (why?) */ 2201 PUTPLL(sc, RADEON_HTOTAL_CNTL, 0); 2202 2203 /* drop reset */ 2204 CLRPLL(sc, RADEON_PPLL_CNTL, 2205 RADEON_PPLL_RESET | RADEON_PPLL_SLEEP | 2206 RADEON_PPLL_ATOMIC_UPDATE_EN | 2207 RADEON_PPLL_VGA_ATOMIC_UPDATE_EN); 2208 2209 PRINTPLL(RADEON_PPLL_CNTL); 2210 PRINTPLL(RADEON_PPLL_REF_DIV); 2211 PRINTPLL(RADEON_PPLL_DIV_3); 2212 2213 /* give clock time to lock */ 2214 delay(50000); 2215 2216 PATCHPLL(sc, RADEON_VCLK_ECP_CNTL, 2217 RADEON_VCLK_SRC_SEL_PPLLCLK, 2218 ~RADEON_VCLK_SRC_SEL_MASK); 2219 2220 } else { 2221 2222 PATCHPLL(sc, RADEON_PIXCLKS_CNTL, 2223 RADEON_PIX2CLK_SRC_SEL_CPUCLK, 2224 ~RADEON_PIX2CLK_SRC_SEL_MASK); 2225 2226 /* put vclk into reset, use atomic updates */ 2227 SETPLL(sc, RADEON_P2PLL_CNTL, 2228 RADEON_P2PLL_RESET | 2229 RADEON_P2PLL_ATOMIC_UPDATE_EN | 2230 RADEON_P2PLL_VGA_ATOMIC_UPDATE_EN); 2231 2232 /* program reference divider */ 2233 PATCHPLL(sc, RADEON_P2PLL_REF_DIV, sc->sc_refdiv, 2234 ~RADEON_P2PLL_REF_DIV_MASK); 2235 2236 /* program feedback and post dividers */ 2237 data = GETPLL(sc, RADEON_P2PLL_DIV_0); 2238 data &= ~(RADEON_P2PLL_FB0_DIV_MASK | 2239 RADEON_P2PLL_POST0_DIV_MASK); 2240 data |= pbit; 2241 data |= (feed & RADEON_P2PLL_FB0_DIV_MASK); 2242 PUTPLL(sc, RADEON_P2PLL_DIV_0, data); 2243 PUTPLL(sc, RADEON_P2PLL_DIV_0, data); 2244 2245 PRINTPLL(RADEON_P2PLL_REF_DIV); 2246 PRINTPLL(RADEON_P2PLL_DIV_0); 2247 2248 /* use the atomic update */ 2249 radeonfb_pllwriteupdate(sc, crtc); 2250 2251 /* and wait for it to complete */ 2252 radeonfb_pllwaitatomicread(sc, crtc); 2253 2254 /* program HTOTAL (why?) */ 2255 PUTPLL(sc, RADEON_HTOTAL2_CNTL, 0); 2256 2257 /* drop reset */ 2258 CLRPLL(sc, RADEON_P2PLL_CNTL, 2259 RADEON_P2PLL_RESET | RADEON_P2PLL_SLEEP | 2260 RADEON_P2PLL_ATOMIC_UPDATE_EN | 2261 RADEON_P2PLL_VGA_ATOMIC_UPDATE_EN); 2262 2263 /* allow time for clock to lock */ 2264 delay(50000); 2265 2266 PATCHPLL(sc, RADEON_PIXCLKS_CNTL, 2267 RADEON_PIX2CLK_SRC_SEL_P2PLLCLK, 2268 ~RADEON_PIX2CLK_SRC_SEL_MASK); 2269 } 2270 PRINTREG(RADEON_CRTC_MORE_CNTL); 2271 } 2272 2273 void 2274 radeonfb_modeswitch(struct radeonfb_display *dp) 2275 { 2276 struct radeonfb_softc *sc = dp->rd_softc; 2277 int i; 2278 2279 if (IS_AVIVO(sc)) { 2280 /* 2281 * no actual mode setting yet, we just make sure the CRTCs 2282 * point at the right memory ranges and use the same pitch 2283 * for the drawing engine 2284 */ 2285 if (GET32(sc, AVIVO_D1CRTC_CONTROL) & AVIVO_CRTC_EN) { 2286 CLR32(sc, AVIVO_D1GRPH_CONTROL, AVIVO_D1GRPH_MACRO_ADDRESS_MODE); 2287 dp->rd_stride = GET32(sc, AVIVO_D1GRPH_PITCH); 2288 PUT32(sc, AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS, 0); 2289 } 2290 if (GET32(sc, AVIVO_D2CRTC_CONTROL) & AVIVO_CRTC_EN) { 2291 CLR32(sc, AVIVO_D2GRPH_CONTROL, AVIVO_D1GRPH_MACRO_ADDRESS_MODE); 2292 dp->rd_stride = GET32(sc, AVIVO_D2GRPH_PITCH); 2293 PUT32(sc, AVIVO_D2GRPH_PRIMARY_SURFACE_ADDRESS, 0); 2294 } 2295 return; 2296 } 2297 2298 /* blank the display while we switch modes */ 2299 //radeonfb_blank(dp, 1); 2300 2301 #if 0 2302 SET32(sc, RADEON_CRTC_EXT_CNTL, 2303 RADEON_CRTC_VSYNC_DIS | RADEON_CRTC_HSYNC_DIS | 2304 RADEON_CRTC_DISPLAY_DIS /* | RADEON_CRTC_DISP_REQ_EN_B */); 2305 #endif 2306 2307 /* these registers might get in the way... */ 2308 PUT32(sc, RADEON_OVR_CLR, 0); 2309 PUT32(sc, RADEON_OVR_WID_LEFT_RIGHT, 0); 2310 PUT32(sc, RADEON_OVR_WID_TOP_BOTTOM, 0); 2311 PUT32(sc, RADEON_OV0_SCALE_CNTL, 0); 2312 PUT32(sc, RADEON_SUBPIC_CNTL, 0); 2313 PUT32(sc, RADEON_VIPH_CONTROL, 0); 2314 PUT32(sc, RADEON_I2C_CNTL_1, 0); 2315 PUT32(sc, RADEON_GEN_INT_CNTL, 0); 2316 PUT32(sc, RADEON_CAP0_TRIG_CNTL, 0); 2317 PUT32(sc, RADEON_CAP1_TRIG_CNTL, 0); 2318 2319 for (i = 0; i < dp->rd_ncrtcs; i++) 2320 radeonfb_setcrtc(dp, i); 2321 2322 #if 0 2323 /* 2324 * DVO chip voodoo from xf86-video-radeon 2325 * apparently this is needed for some powerbooks with DVI outputs 2326 */ 2327 2328 uint8_t data[5][2] = {{0x8, 0x030}, {0x9, 0}, {0xa, 0x90}, {0xc, 0x89}, {0x8, 0x3b}}; 2329 int n = 0; 2330 iic_acquire_bus(&sc->sc_i2c[0].ric_controller, 0); 2331 for (i = 0; i < 5; i++) 2332 n += iic_exec(&sc->sc_i2c[0].ric_controller, I2C_OP_WRITE, 0x38, data[i], 2, NULL, 0, 0); 2333 iic_release_bus(&sc->sc_i2c[0].ric_controller, 0); 2334 printf("n = %d\n", n); 2335 #endif 2336 2337 /* activate the display */ 2338 radeonfb_blank(dp, 0); 2339 } 2340 2341 void 2342 radeonfb_setcrtc(struct radeonfb_display *dp, int index) 2343 { 2344 int crtc, flags = 0; 2345 struct videomode *mode; 2346 struct radeonfb_softc *sc; 2347 struct radeonfb_crtc *cp; 2348 uint32_t v, hd, vd; 2349 uint32_t gencntl; 2350 uint32_t htotaldisp; 2351 uint32_t hsyncstrt; 2352 uint32_t vtotaldisp; 2353 uint32_t vsyncstrt; 2354 uint32_t fphsyncstrt; 2355 uint32_t fpvsyncstrt; 2356 uint32_t fphtotaldisp; 2357 uint32_t fpvtotaldisp; 2358 uint32_t pitch; 2359 2360 sc = dp->rd_softc; 2361 2362 if ((sc->sc_ports[index].rp_tmds_type == RADEON_TMDS_INT) || 2363 (sc->sc_ports[index].rp_tmds_type == RADEON_TMDS_EXT)) { 2364 flags |= NO_ODD_FBDIV; 2365 } 2366 2367 cp = &dp->rd_crtcs[index]; 2368 crtc = cp->rc_number; 2369 mode = &cp->rc_videomode; 2370 2371 #if 1 2372 pitch = dp->rd_stride / dp->rd_bpp; 2373 #else 2374 pitch = (((sc->sc_maxx * sc->sc_maxbpp) + ((sc->sc_maxbpp * 8) - 1)) / 2375 (sc->sc_maxbpp * 8)); 2376 #endif 2377 switch (crtc) { 2378 case 0: 2379 gencntl = RADEON_CRTC_GEN_CNTL; 2380 htotaldisp = RADEON_CRTC_H_TOTAL_DISP; 2381 hsyncstrt = RADEON_CRTC_H_SYNC_STRT_WID; 2382 vtotaldisp = RADEON_CRTC_V_TOTAL_DISP; 2383 vsyncstrt = RADEON_CRTC_V_SYNC_STRT_WID; 2384 /* should probably leave those alone on non-LVDS */ 2385 fpvsyncstrt = RADEON_FP_V_SYNC_STRT_WID; 2386 fphsyncstrt = RADEON_FP_H_SYNC_STRT_WID; 2387 fpvtotaldisp = RADEON_FP_CRTC_V_TOTAL_DISP; 2388 fphtotaldisp = RADEON_FP_CRTC_H_TOTAL_DISP; 2389 break; 2390 case 1: 2391 gencntl = RADEON_CRTC2_GEN_CNTL; 2392 htotaldisp = RADEON_CRTC2_H_TOTAL_DISP; 2393 hsyncstrt = RADEON_CRTC2_H_SYNC_STRT_WID; 2394 vtotaldisp = RADEON_CRTC2_V_TOTAL_DISP; 2395 vsyncstrt = RADEON_CRTC2_V_SYNC_STRT_WID; 2396 fpvsyncstrt = RADEON_FP_V2_SYNC_STRT_WID; 2397 fphsyncstrt = RADEON_FP_H2_SYNC_STRT_WID; 2398 /* XXX these registers don't seem to exist */ 2399 fpvtotaldisp = 0;//RADEON_FP_CRTC2_V_TOTAL_DISP; 2400 fphtotaldisp = 0;//RADEON_FP_CRTC2_H_TOTAL_DISP; 2401 break; 2402 default: 2403 panic("Bad CRTC!"); 2404 break; 2405 } 2406 2407 /* 2408 * CRTC_GEN_CNTL - depth, accelerator mode, etc. 2409 */ 2410 /* only bother with 32bpp and 8bpp */ 2411 v = dp->rd_format << RADEON_CRTC_PIX_WIDTH_SHIFT; 2412 2413 if (crtc == 1) { 2414 v |= RADEON_CRTC2_CRT2_ON | RADEON_CRTC2_EN; 2415 } else { 2416 v |= RADEON_CRTC_EXT_DISP_EN | RADEON_CRTC_EN; 2417 } 2418 2419 if (mode->flags & VID_DBLSCAN) 2420 v |= RADEON_CRTC2_DBL_SCAN_EN; 2421 2422 if (mode->flags & VID_INTERLACE) 2423 v |= RADEON_CRTC2_INTERLACE_EN; 2424 2425 if (mode->flags & VID_CSYNC) { 2426 v |= RADEON_CRTC2_CSYNC_EN; 2427 if (crtc == 1) 2428 v |= RADEON_CRTC2_VSYNC_TRISTAT; 2429 } 2430 2431 PUT32(sc, gencntl, v); 2432 DPRINTF(("CRTC%s_GEN_CNTL = %08x\n", crtc ? "2" : "", v)); 2433 2434 /* 2435 * CRTC_EXT_CNTL - preserve disable flags, set ATI linear and EXT_CNT 2436 */ 2437 v = GET32(sc, RADEON_CRTC_EXT_CNTL); 2438 if (crtc == 0) { 2439 v &= (RADEON_CRTC_VSYNC_DIS | RADEON_CRTC_HSYNC_DIS | 2440 RADEON_CRTC_DISPLAY_DIS); 2441 v |= RADEON_XCRT_CNT_EN | RADEON_VGA_ATI_LINEAR; 2442 if (mode->flags & VID_CSYNC) 2443 v |= RADEON_CRTC_VSYNC_TRISTAT; 2444 } 2445 /* unconditional turn on CRT, in case first CRTC is DFP */ 2446 v |= RADEON_CRTC_CRT_ON; 2447 PUT32(sc, RADEON_CRTC_EXT_CNTL, v); 2448 PRINTREG(RADEON_CRTC_EXT_CNTL); 2449 2450 hd = ((GET32(sc, htotaldisp) >> 16) + 1) * 8; 2451 vd = (GET32(sc, vtotaldisp) >> 16) + 1; 2452 DPRINTF(("res %d x %d\n", hd, vd)); 2453 2454 if ((hd != mode->hdisplay) || (vd != mode->vdisplay)) { 2455 2456 /* 2457 * H_TOTAL_DISP 2458 */ 2459 v = ((mode->hdisplay / 8) - 1) << 16; 2460 v |= (mode->htotal / 8) - 1; 2461 PRINTREG(RADEON_CRTC_H_TOTAL_DISP); 2462 PUT32(sc, htotaldisp, v); 2463 DPRINTF(("CRTC%s_H_TOTAL_DISP = %08x\n", crtc ? "2" : "", v)); 2464 if (fphtotaldisp) { 2465 PRINTREG(RADEON_FP_CRTC_H_TOTAL_DISP); 2466 PUT32(sc, fphtotaldisp, v); 2467 DPRINTF(("FP_H%s_TOTAL_DISP = %08x\n", crtc ? "2" : "", v)); 2468 } 2469 /* 2470 * H_SYNC_STRT_WID 2471 */ 2472 v = (((mode->hsync_end - mode->hsync_start) / 8) << 16); 2473 v |= (mode->hsync_start - 8); /* match xf86-video-radeon */ 2474 if (mode->flags & VID_NHSYNC) 2475 v |= RADEON_CRTC_H_SYNC_POL; 2476 PUT32(sc, hsyncstrt, v); 2477 DPRINTF(("CRTC%s_H_SYNC_STRT_WID = %08x\n", crtc ? "2" : "", v)); 2478 if (fphsyncstrt) { 2479 PUT32(sc, fphsyncstrt, v); 2480 DPRINTF(("FP_H%s_SYNC_STRT_WID = %08x\n", crtc ? "2" : "", v)); 2481 } 2482 2483 /* 2484 * V_TOTAL_DISP 2485 */ 2486 v = ((mode->vdisplay - 1) << 16); 2487 v |= (mode->vtotal - 1); 2488 PUT32(sc, vtotaldisp, v); 2489 DPRINTF(("CRTC%s_V_TOTAL_DISP = %08x\n", crtc ? "2" : "", v)); 2490 if (fpvtotaldisp) { 2491 PUT32(sc, fpvtotaldisp, v); 2492 DPRINTF(("FP_V%s_TOTAL_DISP = %08x\n", crtc ? "2" : "", v)); 2493 } 2494 2495 /* 2496 * V_SYNC_STRT_WID 2497 */ 2498 v = ((mode->vsync_end - mode->vsync_start) << 16); 2499 v |= (mode->vsync_start - 1); 2500 if (mode->flags & VID_NVSYNC) 2501 v |= RADEON_CRTC_V_SYNC_POL; 2502 PUT32(sc, vsyncstrt, v); 2503 DPRINTF(("CRTC%s_V_SYNC_STRT_WID = %08x\n", crtc ? "2" : "", v)); 2504 if (fpvsyncstrt) { 2505 PUT32(sc, fpvsyncstrt, v); 2506 DPRINTF(("FP_V%s_SYNC_STRT_WID = %08x\n", crtc ? "2" : "", v)); 2507 } 2508 } 2509 radeonfb_program_vclk(sc, mode->dot_clock, crtc, flags); 2510 2511 switch (crtc) { 2512 case 0: 2513 PUT32(sc, RADEON_CRTC_OFFSET, 0); 2514 PUT32(sc, RADEON_CRTC_OFFSET_CNTL, 0); 2515 PUT32(sc, RADEON_CRTC_PITCH, pitch); 2516 CLR32(sc, RADEON_DISP_MERGE_CNTL, RADEON_DISP_RGB_OFFSET_EN); 2517 2518 CLR32(sc, RADEON_CRTC_EXT_CNTL, 2519 RADEON_CRTC_VSYNC_DIS | RADEON_CRTC_HSYNC_DIS | 2520 RADEON_CRTC_DISPLAY_DIS /* | RADEON_CRTC_DISP_REQ_EN_B */); 2521 CLR32(sc, RADEON_CRTC_GEN_CNTL, RADEON_CRTC_DISP_REQ_EN_B); 2522 PRINTREG(RADEON_CRTC_EXT_CNTL); 2523 PRINTREG(RADEON_CRTC_GEN_CNTL); 2524 PRINTREG(RADEON_CLOCK_CNTL_INDEX); 2525 break; 2526 2527 case 1: 2528 PUT32(sc, RADEON_CRTC2_OFFSET, 0); 2529 PUT32(sc, RADEON_CRTC2_OFFSET_CNTL, 0); 2530 PUT32(sc, RADEON_CRTC2_PITCH, pitch); 2531 CLR32(sc, RADEON_DISP2_MERGE_CNTL, RADEON_DISP2_RGB_OFFSET_EN); 2532 CLR32(sc, RADEON_CRTC2_GEN_CNTL, 2533 RADEON_CRTC2_VSYNC_DIS | 2534 RADEON_CRTC2_HSYNC_DIS | 2535 RADEON_CRTC2_DISP_DIS | RADEON_CRTC2_DISP_REQ_EN_B); 2536 PRINTREG(RADEON_CRTC2_GEN_CNTL); 2537 break; 2538 } 2539 } 2540 2541 int 2542 radeonfb_isblank(struct radeonfb_display *dp) 2543 { 2544 struct radeonfb_softc *sc = dp->rd_softc; 2545 uint32_t reg, mask; 2546 2547 if (IS_AVIVO(sc)) return 0; 2548 2549 if(!dp->rd_softc->sc_mapped) 2550 return 1; 2551 2552 if (dp->rd_crtcs[0].rc_number) { 2553 reg = RADEON_CRTC2_GEN_CNTL; 2554 mask = RADEON_CRTC2_DISP_DIS; 2555 } else { 2556 reg = RADEON_CRTC_EXT_CNTL; 2557 mask = RADEON_CRTC_DISPLAY_DIS; 2558 } 2559 return ((GET32(dp->rd_softc, reg) & mask) ? 1 : 0); 2560 } 2561 2562 void 2563 radeonfb_blank(struct radeonfb_display *dp, int blank) 2564 { 2565 struct radeonfb_softc *sc = dp->rd_softc; 2566 uint32_t reg, mask; 2567 uint32_t fpreg, fpval; 2568 int i; 2569 2570 if(IS_AVIVO(sc)) return; 2571 2572 if (!sc->sc_mapped) 2573 return; 2574 2575 for (i = 0; i < dp->rd_ncrtcs; i++) { 2576 2577 if (dp->rd_crtcs[i].rc_number) { 2578 reg = RADEON_CRTC2_GEN_CNTL; 2579 mask = RADEON_CRTC2_DISP_DIS; 2580 fpreg = RADEON_FP2_GEN_CNTL; 2581 fpval = RADEON_FP2_ON; 2582 } else { 2583 reg = RADEON_CRTC_EXT_CNTL; 2584 mask = RADEON_CRTC_DISPLAY_DIS; 2585 fpreg = RADEON_FP_GEN_CNTL; 2586 fpval = RADEON_FP_FPON; 2587 } 2588 2589 if (blank) { 2590 SET32(sc, reg, mask); 2591 CLR32(sc, fpreg, fpval); 2592 } else { 2593 CLR32(sc, reg, mask); 2594 SET32(sc, fpreg, fpval); 2595 } 2596 } 2597 PRINTREG(RADEON_FP_GEN_CNTL); 2598 PRINTREG(RADEON_FP2_GEN_CNTL); 2599 } 2600 2601 void 2602 radeonfb_init_screen(void *cookie, struct vcons_screen *scr, int existing, 2603 long *defattr) 2604 { 2605 struct radeonfb_display *dp = cookie; 2606 struct rasops_info *ri = &scr->scr_ri; 2607 2608 /* initialize font subsystem */ 2609 wsfont_init(); 2610 2611 scr->scr_flags |= VCONS_LOADFONT; 2612 2613 DPRINTF(("init screen called, existing %d\n", existing)); 2614 2615 ri->ri_depth = dp->rd_bpp; 2616 ri->ri_width = dp->rd_virtx; 2617 ri->ri_height = dp->rd_virty; 2618 ri->ri_stride = dp->rd_stride; 2619 ri->ri_flg = RI_CENTER; 2620 switch (ri->ri_depth) { 2621 case 8: 2622 ri->ri_flg |= RI_ENABLE_ALPHA | RI_8BIT_IS_RGB | RI_PREFER_ALPHA; 2623 break; 2624 case 32: 2625 ri->ri_flg |= RI_ENABLE_ALPHA | RI_PREFER_ALPHA; 2626 /* we run radeons in RGB even on SPARC hardware */ 2627 ri->ri_rnum = 8; 2628 ri->ri_gnum = 8; 2629 ri->ri_bnum = 8; 2630 ri->ri_rpos = 16; 2631 ri->ri_gpos = 8; 2632 ri->ri_bpos = 0; 2633 break; 2634 } 2635 2636 ri->ri_bits = (void *)dp->rd_fbptr; 2637 2638 #ifdef VCONS_DRAW_INTR 2639 scr->scr_flags |= VCONS_DONT_READ; 2640 #endif 2641 2642 if (existing) { 2643 ri->ri_flg |= RI_CLEAR; 2644 2645 /* start a modeswitch now */ 2646 //radeonfb_modeswitch(dp); 2647 } 2648 2649 /* 2650 * XXX: font selection should be based on properties, with some 2651 * normal/reasonable default. 2652 */ 2653 2654 /* initialize and look for an initial font */ 2655 rasops_init(ri, 0, 0); 2656 ri->ri_caps = WSSCREEN_UNDERLINE | WSSCREEN_HILIT | 2657 WSSCREEN_WSCOLORS | WSSCREEN_REVERSE | WSSCREEN_RESIZE; 2658 2659 rasops_reconfig(ri, dp->rd_virty / ri->ri_font->fontheight, 2660 dp->rd_virtx / ri->ri_font->fontwidth); 2661 2662 /* enable acceleration */ 2663 dp->rd_putchar = ri->ri_ops.putchar; 2664 ri->ri_ops.copyrows = radeonfb_copyrows; 2665 ri->ri_ops.copycols = radeonfb_copycols; 2666 ri->ri_ops.eraserows = radeonfb_eraserows; 2667 ri->ri_ops.erasecols = radeonfb_erasecols; 2668 /* pick a putchar method based on font and Radeon model */ 2669 if (ri->ri_font->stride < ri->ri_font->fontwidth) { 2670 /* got a bitmap font */ 2671 #if !defined(RADEONFB_ALWAYS_ACCEL_PUTCHAR) 2672 if (IS_R300(dp->rd_softc) && 0) { 2673 /* 2674 * radeonfb_putchar() doesn't work right on some R3xx 2675 * so we use software drawing here, the wrapper just 2676 * makes sure the engine is idle before scribbling 2677 * into vram 2678 */ 2679 ri->ri_ops.putchar = radeonfb_putchar_wrapper; 2680 } else 2681 #endif 2682 ri->ri_ops.putchar = radeonfb_putchar; 2683 } else { 2684 /* got an alpha font */ 2685 switch(ri->ri_depth) { 2686 case 32: 2687 ri->ri_ops.putchar = radeonfb_putchar_aa32; 2688 break; 2689 case 8: 2690 ri->ri_ops.putchar = radeonfb_putchar_aa8; 2691 break; 2692 default: 2693 /* XXX this should never happen */ 2694 panic("%s: depth is not 8 or 32 but we got an" \ 2695 " alpha font?!", __func__); 2696 } 2697 } 2698 ri->ri_ops.cursor = radeonfb_cursor; 2699 } 2700 2701 static uint32_t 2702 radeonfb_avivo_INMC(struct radeonfb_softc *sc, uint32_t addr) 2703 { 2704 uint32_t data; 2705 2706 PUT32(sc, AVIVO_MC_INDEX, (addr & 0xff) | 0x7f0000); 2707 (void)GET32(sc, AVIVO_MC_INDEX); 2708 data = GET32(sc, AVIVO_MC_DATA); 2709 PUT32(sc, AVIVO_MC_INDEX, 0); 2710 (void)GET32(sc, AVIVO_MC_INDEX); 2711 return data; 2712 } 2713 2714 static void 2715 radeonfb_avivo_OUTMC(struct radeonfb_softc *sc, uint32_t addr, uint32_t data) 2716 { 2717 2718 PUT32(sc, AVIVO_MC_INDEX, (addr & 0xff) | 0x7f0000); 2719 (void)GET32(sc, AVIVO_MC_INDEX); 2720 PUT32(sc, AVIVO_MC_DATA, data); 2721 PUT32(sc, AVIVO_MC_INDEX, 0); 2722 (void)GET32(sc, AVIVO_MC_INDEX); 2723 } 2724 2725 void 2726 radeonfb_set_fbloc(struct radeonfb_softc *sc) 2727 { 2728 uint32_t gen = 0, ext = 0, gen2 = 0; 2729 uint32_t agploc, aperbase, apersize, mcfbloc; 2730 2731 2732 if (IS_AVIVO(sc)) { 2733 agploc = radeonfb_avivo_INMC(sc, R520_MC_AGP_LOCATION); 2734 } else { 2735 gen = GET32(sc, RADEON_CRTC_GEN_CNTL); 2736 /* XXX */ 2737 ext = GET32(sc, RADEON_CRTC_EXT_CNTL) & ~RADEON_CRTC_DISPLAY_DIS; 2738 agploc = GET32(sc, RADEON_MC_AGP_LOCATION); 2739 PUT32(sc, RADEON_CRTC_GEN_CNTL, gen | RADEON_CRTC_DISP_REQ_EN_B); 2740 PUT32(sc, RADEON_CRTC_EXT_CNTL, ext | RADEON_CRTC_DISPLAY_DIS); 2741 #if 0 2742 PUT32(sc, RADEON_CRTC_GEN_CNTL, gen | RADEON_CRTC_DISPLAY_DIS); 2743 PUT32(sc, RADEON_CRTC_EXT_CNTL, ext | RADEON_CRTC_DISP_REQ_EN_B); 2744 #endif 2745 2746 if (HAS_CRTC2(sc)) { 2747 gen2 = GET32(sc, RADEON_CRTC2_GEN_CNTL); 2748 PUT32(sc, RADEON_CRTC2_GEN_CNTL, 2749 gen2 | RADEON_CRTC2_DISP_REQ_EN_B); 2750 } 2751 2752 delay(100000); 2753 } 2754 2755 aperbase = GET32(sc, RADEON_CONFIG_APER_0_BASE); 2756 apersize = GET32(sc, RADEON_CONFIG_APER_SIZE); 2757 2758 2759 mcfbloc = (aperbase >> 16) | 2760 ((aperbase + (apersize - 1)) & 0xffff0000); 2761 2762 sc->sc_aperbase = (mcfbloc & 0xffff) << 16; 2763 sc->sc_memsz = apersize; 2764 DPRINTF(("aperbase = %08x\n", aperbase)); 2765 2766 if (((agploc & 0xffff) << 16) != 2767 ((mcfbloc & 0xffff0000U) + 0x10000)) { 2768 agploc = mcfbloc & 0xffff0000U; 2769 agploc |= ((agploc + 0x10000) >> 16); 2770 } 2771 2772 PUT32(sc, RADEON_HOST_PATH_CNTL, 0); 2773 2774 if (IS_AVIVO(sc)) { 2775 radeonfb_avivo_OUTMC(sc, R520_MC_FB_LOCATION, mcfbloc); 2776 radeonfb_avivo_OUTMC(sc, R520_MC_AGP_LOCATION, agploc); 2777 PRINTREG(AVIVO_HDP_FB_LOCATION); 2778 DPRINTF((" FB loc %08x\n", radeonfb_avivo_INMC(sc, R520_MC_FB_LOCATION))); 2779 DPRINTF(("AGP loc %08x\n", radeonfb_avivo_INMC(sc, R520_MC_AGP_LOCATION))); 2780 } else { 2781 PUT32(sc, RADEON_MC_FB_LOCATION, mcfbloc); 2782 PUT32(sc, RADEON_MC_AGP_LOCATION, agploc); 2783 PRINTREG(RADEON_MC_FB_LOCATION); 2784 PRINTREG(RADEON_MC_AGP_LOCATION); 2785 2786 PUT32(sc, RADEON_DISPLAY_BASE_ADDR, sc->sc_aperbase); 2787 2788 if (HAS_CRTC2(sc)) 2789 PUT32(sc, RADEON_DISPLAY2_BASE_ADDR, sc->sc_aperbase); 2790 2791 PUT32(sc, RADEON_OV0_BASE_ADDR, sc->sc_aperbase); 2792 delay(100000); 2793 2794 PUT32(sc, RADEON_CRTC_GEN_CNTL, gen); 2795 PUT32(sc, RADEON_CRTC_EXT_CNTL, ext); 2796 2797 if (HAS_CRTC2(sc)) 2798 PUT32(sc, RADEON_CRTC2_GEN_CNTL, gen2); 2799 } 2800 #if 0 2801 /* XXX: what is this AGP garbage? :-) */ 2802 PUT32(sc, RADEON_AGP_CNTL, 0x00100000); 2803 #endif 2804 } 2805 2806 void 2807 radeonfb_init_misc(struct radeonfb_softc *sc) 2808 { 2809 PUT32(sc, RADEON_BUS_CNTL, 2810 RADEON_BUS_MASTER_DIS | 2811 RADEON_BUS_PREFETCH_MODE_ACT | 2812 RADEON_BUS_PCI_READ_RETRY_EN | 2813 RADEON_BUS_PCI_WRT_RETRY_EN | 2814 (3 << RADEON_BUS_RETRY_WS_SHIFT) | 2815 RADEON_BUS_MSTR_RD_MULT | 2816 RADEON_BUS_MSTR_RD_LINE | 2817 RADEON_BUS_RD_DISCARD_EN | 2818 RADEON_BUS_MSTR_DISCONNECT_EN | 2819 RADEON_BUS_READ_BURST); 2820 2821 PUT32(sc, RADEON_BUS_CNTL1, 0xf0); 2822 /* PUT32(sc, RADEON_SEPROM_CNTL1, 0x09ff0000); */ 2823 PUT32(sc, RADEON_FCP_CNTL, RADEON_FCP0_SRC_GND); 2824 PUT32(sc, RADEON_RBBM_CNTL, 2825 (3 << RADEON_RB_SETTLE_SHIFT) | 2826 (4 << RADEON_ABORTCLKS_HI_SHIFT) | 2827 (4 << RADEON_ABORTCLKS_CP_SHIFT) | 2828 (4 << RADEON_ABORTCLKS_CFIFO_SHIFT)); 2829 2830 /* XXX: figure out what these mean! */ 2831 PUT32(sc, RADEON_AGP_CNTL, 0x00100000); 2832 PUT32(sc, RADEON_HOST_PATH_CNTL, 0); 2833 #if 0 2834 PUT32(sc, RADEON_DISP_MISC_CNTL, 0x5bb00400); 2835 #endif 2836 2837 PUT32(sc, RADEON_GEN_INT_CNTL, 0); 2838 PUT32(sc, RADEON_GEN_INT_STATUS, GET32(sc, RADEON_GEN_INT_STATUS)); 2839 } 2840 2841 static void 2842 radeonfb_putpal(struct radeonfb_display *dp, int idx, int r, int g, int b) 2843 { 2844 struct radeonfb_softc *sc = dp->rd_softc; 2845 int crtc, cc; 2846 uint32_t vclk; 2847 2848 if (IS_AVIVO(sc)) { 2849 for (cc = 0; cc < dp->rd_ncrtcs; cc++) { 2850 crtc = dp->rd_crtcs[cc].rc_number; 2851 2852 if (crtc) 2853 PUT32(sc, AVIVO_DC_LUT_RW_SELECT, 1); 2854 else 2855 PUT32(sc, AVIVO_DC_LUT_RW_SELECT, 0); 2856 2857 PUT32(sc, AVIVO_DC_LUT_RW_INDEX, idx); 2858 PUT32(sc, AVIVO_DC_LUT_30_COLOR, 2859 (r << 22) | (g << 12) | (b << 2)); 2860 } 2861 2862 } else { 2863 vclk = GETPLL(sc, RADEON_VCLK_ECP_CNTL); 2864 PUTPLL(sc, RADEON_VCLK_ECP_CNTL, 2865 vclk & ~RADEON_PIXCLK_DAC_ALWAYS_ONb); 2866 2867 /* init the palette for every CRTC used by this display */ 2868 for (cc = 0; cc < dp->rd_ncrtcs; cc++) { 2869 crtc = dp->rd_crtcs[cc].rc_number; 2870 2871 if (crtc) 2872 SET32(sc, RADEON_DAC_CNTL2, 2873 RADEON_DAC2_PALETTE_ACC_CTL); 2874 else 2875 CLR32(sc, RADEON_DAC_CNTL2, 2876 RADEON_DAC2_PALETTE_ACC_CTL); 2877 2878 PUT32(sc, RADEON_PALETTE_INDEX, idx); 2879 PUT32(sc, RADEON_PALETTE_30_DATA, 2880 (r << 22) | (g << 12) | (b << 2)); 2881 } 2882 2883 PUTPLL(sc, RADEON_VCLK_ECP_CNTL, vclk); 2884 } 2885 } 2886 2887 /* 2888 * This loads a linear color map for true color. 2889 */ 2890 void 2891 radeonfb_init_palette(struct radeonfb_display *dp) 2892 { 2893 int i; 2894 2895 #define DAC_WIDTH ((1 << 10) - 1) 2896 #define CLUT_WIDTH ((1 << 8) - 1) 2897 #define CLUT_COLOR(i) ((i * DAC_WIDTH * 2 / CLUT_WIDTH + 1) / 2) 2898 2899 if (dp->rd_bpp == 8) { 2900 2901 /* R3G3B2 palette */ 2902 uint32_t tmp, r, g, b; 2903 2904 for (i = 0; i <= CLUT_WIDTH; ++i) { 2905 tmp = i & 0xe0; 2906 2907 /* 2908 * replicate bits so 0xe0 maps to a red value of 0xff 2909 * in order to make white look actually white 2910 */ 2911 tmp |= (tmp >> 3) | (tmp >> 6); 2912 r = tmp; 2913 2914 tmp = (i & 0x1c) << 3; 2915 tmp |= (tmp >> 3) | (tmp >> 6); 2916 g = tmp; 2917 2918 tmp = (i & 0x03) << 6; 2919 tmp |= tmp >> 2; 2920 tmp |= tmp >> 4; 2921 b = tmp; 2922 2923 radeonfb_putpal(dp, i, r, g, b); 2924 } 2925 } else { 2926 /* linear ramp */ 2927 for (i = 0; i <= CLUT_WIDTH; ++i) { 2928 radeonfb_putpal(dp, i, i, i, i); 2929 } 2930 } 2931 } 2932 2933 static int 2934 radeonfb_putcmap(struct radeonfb_display *dp, struct wsdisplay_cmap *cm) 2935 { 2936 u_char *r, *g, *b; 2937 u_int index = cm->index; 2938 u_int count = cm->count; 2939 int i, error; 2940 u_char rbuf[256], gbuf[256], bbuf[256]; 2941 2942 #ifdef GENFB_DEBUG 2943 aprint_debug("putcmap: %d %d\n",index, count); 2944 #endif 2945 if (index >= 256 || count > 256 - index) 2946 return EINVAL; 2947 error = copyin(cm->red, &rbuf[index], count); 2948 if (error) 2949 return error; 2950 error = copyin(cm->green, &gbuf[index], count); 2951 if (error) 2952 return error; 2953 error = copyin(cm->blue, &bbuf[index], count); 2954 if (error) 2955 return error; 2956 2957 memcpy(&dp->rd_cmap_red[index], &rbuf[index], count); 2958 memcpy(&dp->rd_cmap_green[index], &gbuf[index], count); 2959 memcpy(&dp->rd_cmap_blue[index], &bbuf[index], count); 2960 2961 r = &dp->rd_cmap_red[index]; 2962 g = &dp->rd_cmap_green[index]; 2963 b = &dp->rd_cmap_blue[index]; 2964 2965 for (i = 0; i < count; i++) { 2966 radeonfb_putpal(dp, index, *r, *g, *b); 2967 index++; 2968 r++, g++, b++; 2969 } 2970 return 0; 2971 } 2972 2973 static int 2974 radeonfb_getcmap(struct radeonfb_display *dp, struct wsdisplay_cmap *cm) 2975 { 2976 u_int index = cm->index; 2977 u_int count = cm->count; 2978 int error; 2979 2980 if (index >= 256 || count > 256 - index) 2981 return EINVAL; 2982 2983 error = copyout(&dp->rd_cmap_red[index], cm->red, count); 2984 if (error) 2985 return error; 2986 error = copyout(&dp->rd_cmap_green[index], cm->green, count); 2987 if (error) 2988 return error; 2989 error = copyout(&dp->rd_cmap_blue[index], cm->blue, count); 2990 if (error) 2991 return error; 2992 2993 return 0; 2994 } 2995 2996 /* 2997 * Bugs in some R300 hardware requires this when accessing CLOCK_CNTL_INDEX. 2998 */ 2999 void 3000 radeonfb_r300cg_workaround(struct radeonfb_softc *sc) 3001 { 3002 uint32_t tmp, save; 3003 3004 save = GET32(sc, RADEON_CLOCK_CNTL_INDEX); 3005 tmp = save & ~(0x3f | RADEON_PLL_WR_EN); 3006 PUT32(sc, RADEON_CLOCK_CNTL_INDEX, tmp); 3007 tmp = GET32(sc, RADEON_CLOCK_CNTL_DATA); 3008 PUT32(sc, RADEON_CLOCK_CNTL_INDEX, save); 3009 } 3010 3011 /* 3012 * Acceleration entry points. 3013 */ 3014 3015 /* this one draws characters using bitmap fonts */ 3016 static void 3017 radeonfb_putchar(void *cookie, int row, int col, u_int c, long attr) 3018 { 3019 struct rasops_info *ri = cookie; 3020 struct vcons_screen *scr = ri->ri_hw; 3021 struct radeonfb_display *dp = scr->scr_cookie; 3022 struct radeonfb_softc *sc = dp->rd_softc; 3023 struct wsdisplay_font *font = PICK_FONT(ri, c); 3024 uint32_t w, h; 3025 int xd, yd, offset, i; 3026 uint32_t bg, fg, gmc; 3027 uint32_t reg; 3028 uint8_t *data8; 3029 uint16_t *data16; 3030 uint32_t *data32; 3031 void *data; 3032 3033 if (dp->rd_wsmode != WSDISPLAYIO_MODE_EMUL) 3034 return; 3035 3036 if (!CHAR_IN_FONT(c, font)) 3037 return; 3038 3039 w = font->fontwidth; 3040 h = font->fontheight; 3041 3042 bg = ri->ri_devcmap[(attr >> 16) & 0xf]; 3043 fg = ri->ri_devcmap[(attr >> 24) & 0xf]; 3044 3045 xd = ri->ri_xorigin + col * w; 3046 yd = ri->ri_yorigin + row * h; 3047 3048 if (c == 0x20) { 3049 radeonfb_rectfill(dp, xd, yd, w, h, bg); 3050 return; 3051 } 3052 data = WSFONT_GLYPH(c, font); 3053 3054 gmc = dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT; 3055 3056 radeonfb_wait_fifo(sc, 9); 3057 3058 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 3059 RADEON_GMC_BRUSH_NONE | 3060 RADEON_GMC_SRC_DATATYPE_MONO_FG_BG | 3061 RADEON_GMC_DST_CLIPPING | 3062 RADEON_ROP3_S | 3063 RADEON_DP_SRC_SOURCE_HOST_DATA | 3064 RADEON_GMC_CLR_CMP_CNTL_DIS | 3065 RADEON_GMC_WR_MSK_DIS | 3066 gmc); 3067 3068 PUT32(sc, RADEON_SC_LEFT, xd); 3069 PUT32(sc, RADEON_SC_RIGHT, xd + w); 3070 PUT32(sc, RADEON_DP_SRC_FRGD_CLR, fg); 3071 PUT32(sc, RADEON_DP_SRC_BKGD_CLR, bg); 3072 PUT32(sc, RADEON_DP_CNTL, 3073 RADEON_DST_X_LEFT_TO_RIGHT | 3074 RADEON_DST_Y_TOP_TO_BOTTOM); 3075 3076 PUT32(sc, RADEON_SRC_X_Y, 0); 3077 offset = 32 - (font->stride << 3); 3078 PUT32(sc, RADEON_DST_X_Y, ((xd - offset) << 16) | yd); 3079 PUT32(sc, RADEON_DST_WIDTH_HEIGHT, (32 << 16) | h); 3080 3081 radeonfb_wait_fifo(sc, h); 3082 switch (font->stride) { 3083 case 1: { 3084 data8 = data; 3085 for (i = 0; i < h; i++) { 3086 reg = *data8; 3087 #if BYTE_ORDER == LITTLE_ENDIAN 3088 reg = reg << 24; 3089 #endif 3090 bus_space_write_stream_4(sc->sc_regt, 3091 sc->sc_regh, RADEON_HOST_DATA0, reg); 3092 data8++; 3093 } 3094 break; 3095 } 3096 case 2: { 3097 data16 = data; 3098 for (i = 0; i < h; i++) { 3099 reg = *data16; 3100 #if BYTE_ORDER == LITTLE_ENDIAN 3101 reg = reg << 16; 3102 #endif 3103 bus_space_write_stream_4(sc->sc_regt, 3104 sc->sc_regh, RADEON_HOST_DATA0, reg); 3105 data16++; 3106 } 3107 break; 3108 } 3109 case 4: { 3110 data32 = data; 3111 for (i = 0; i < h; i++) { 3112 reg = *data32; 3113 bus_space_write_stream_4(sc->sc_regt, 3114 sc->sc_regh, RADEON_HOST_DATA0, reg); 3115 data32++; 3116 } 3117 break; 3118 } 3119 } 3120 if (attr & 1) 3121 radeonfb_rectfill(dp, xd, yd + h - 2, w, 1, fg); 3122 } 3123 3124 /* ... while this one is for anti-aliased ones */ 3125 static void 3126 radeonfb_putchar_aa32(void *cookie, int row, int col, u_int c, long attr) 3127 { 3128 struct rasops_info *ri = cookie; 3129 struct vcons_screen *scr = ri->ri_hw; 3130 struct radeonfb_display *dp = scr->scr_cookie; 3131 struct radeonfb_softc *sc = dp->rd_softc; 3132 struct wsdisplay_font *font = PICK_FONT(ri, c); 3133 uint32_t bg, fg, gmc; 3134 uint8_t *data; 3135 int w, h, xd, yd; 3136 int i, r, g, b, aval; 3137 int rf, gf, bf, rb, gb, bb; 3138 uint32_t pixel; 3139 int rv; 3140 3141 if (dp->rd_wsmode != WSDISPLAYIO_MODE_EMUL) 3142 return; 3143 3144 if (!CHAR_IN_FONT(c, font)) 3145 return; 3146 3147 w = font->fontwidth; 3148 h = font->fontheight; 3149 3150 bg = ri->ri_devcmap[(attr >> 16) & 0xf]; 3151 fg = ri->ri_devcmap[(attr >> 24) & 0xf]; 3152 3153 xd = ri->ri_xorigin + col * w; 3154 yd = ri->ri_yorigin + row * h; 3155 3156 if (c == 0x20) { 3157 radeonfb_rectfill(dp, xd, yd, w, h, bg); 3158 if (attr & 1) 3159 radeonfb_rectfill(dp, xd, yd + h - 2, w, 1, fg); 3160 return; 3161 } 3162 rv = glyphcache_try(&dp->rd_gc, c, xd, yd, attr); 3163 if (rv == GC_OK) 3164 return; 3165 3166 data = WSFONT_GLYPH(c, font); 3167 3168 gmc = dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT; 3169 3170 radeonfb_wait_fifo(sc, 5); 3171 3172 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 3173 RADEON_GMC_BRUSH_NONE | 3174 RADEON_GMC_SRC_DATATYPE_COLOR | 3175 RADEON_ROP3_S | 3176 RADEON_DP_SRC_SOURCE_HOST_DATA | 3177 RADEON_GMC_CLR_CMP_CNTL_DIS | 3178 RADEON_GMC_WR_MSK_DIS | 3179 gmc); 3180 3181 PUT32(sc, RADEON_DP_CNTL, 3182 RADEON_DST_X_LEFT_TO_RIGHT | 3183 RADEON_DST_Y_TOP_TO_BOTTOM); 3184 3185 PUT32(sc, RADEON_SRC_X_Y, 0); 3186 PUT32(sc, RADEON_DST_X_Y, (xd << 16) | yd); 3187 PUT32(sc, RADEON_DST_WIDTH_HEIGHT, (w << 16) | h); 3188 3189 rf = (fg >> 16) & 0xff; 3190 rb = (bg >> 16) & 0xff; 3191 gf = (fg >> 8) & 0xff; 3192 gb = (bg >> 8) & 0xff; 3193 bf = fg & 0xff; 3194 bb = bg & 0xff; 3195 3196 /* 3197 * I doubt we can upload data faster than even the slowest Radeon 3198 * could process them, especially when doing the alpha blending stuff 3199 * along the way, so just make sure there's some room in the FIFO and 3200 * then hammer away 3201 * As it turns out we can, so make periodic stops to let the FIFO 3202 * drain. 3203 */ 3204 radeonfb_wait_fifo(sc, 20); 3205 for (i = 0; i < ri->ri_fontscale; i++) { 3206 aval = *data; 3207 data++; 3208 if (aval == 0) { 3209 pixel = bg; 3210 } else if (aval == 255) { 3211 pixel = fg; 3212 } else { 3213 r = aval * rf + (255 - aval) * rb; 3214 g = aval * gf + (255 - aval) * gb; 3215 b = aval * bf + (255 - aval) * bb; 3216 pixel = (r & 0xff00) << 8 | 3217 (g & 0xff00) | 3218 (b & 0xff00) >> 8; 3219 } 3220 if (i & 16) 3221 radeonfb_wait_fifo(sc, 20); 3222 PUT32(sc, RADEON_HOST_DATA0, pixel); 3223 } 3224 if (rv == GC_ADD) { 3225 glyphcache_add(&dp->rd_gc, c, xd, yd); 3226 } else if (attr & 1) 3227 radeonfb_rectfill(dp, xd, yd + h - 2, w, 1, fg); 3228 } 3229 3230 static void 3231 radeonfb_putchar_aa8(void *cookie, int row, int col, u_int c, long attr) 3232 { 3233 struct rasops_info *ri = cookie; 3234 struct vcons_screen *scr = ri->ri_hw; 3235 struct radeonfb_display *dp = scr->scr_cookie; 3236 struct radeonfb_softc *sc = dp->rd_softc; 3237 struct wsdisplay_font *font = PICK_FONT(ri, c); 3238 uint32_t bg, fg, latch = 0, bg8, fg8, pixel, gmc; 3239 int i, x, y, wi, he, r, g, b, aval; 3240 int r1, g1, b1, r0, g0, b0, fgo, bgo; 3241 uint8_t *data8; 3242 int rv, cnt; 3243 3244 if (dp->rd_wsmode != WSDISPLAYIO_MODE_EMUL) 3245 return; 3246 3247 if (!CHAR_IN_FONT(c, font)) 3248 return; 3249 3250 wi = font->fontwidth; 3251 he = font->fontheight; 3252 3253 bg = ri->ri_devcmap[(attr >> 16) & 0xf]; 3254 fg = ri->ri_devcmap[(attr >> 24) & 0xf]; 3255 3256 x = ri->ri_xorigin + col * wi; 3257 y = ri->ri_yorigin + row * he; 3258 3259 if (c == 0x20) { 3260 radeonfb_rectfill(dp, x, y, wi, he, bg); 3261 if (attr & 1) 3262 radeonfb_rectfill(dp, x, y + he - 2, wi, 1, fg); 3263 return; 3264 } 3265 rv = glyphcache_try(&dp->rd_gc, c, x, y, attr); 3266 if (rv == GC_OK) 3267 return; 3268 3269 data8 = WSFONT_GLYPH(c, font); 3270 3271 gmc = dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT; 3272 3273 radeonfb_wait_fifo(sc, 5); 3274 3275 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 3276 RADEON_GMC_BRUSH_NONE | 3277 RADEON_GMC_SRC_DATATYPE_COLOR | 3278 RADEON_ROP3_S | 3279 RADEON_DP_SRC_SOURCE_HOST_DATA | 3280 RADEON_GMC_CLR_CMP_CNTL_DIS | 3281 RADEON_GMC_WR_MSK_DIS | 3282 gmc); 3283 3284 PUT32(sc, RADEON_DP_CNTL, 3285 RADEON_DST_X_LEFT_TO_RIGHT | 3286 RADEON_DST_Y_TOP_TO_BOTTOM); 3287 3288 PUT32(sc, RADEON_SRC_X_Y, 0); 3289 PUT32(sc, RADEON_DST_X_Y, (x << 16) | y); 3290 PUT32(sc, RADEON_DST_WIDTH_HEIGHT, (wi << 16) | he); 3291 3292 /* 3293 * we need the RGB colours here, so get offsets into rasops_cmap 3294 */ 3295 fgo = ((attr >> 24) & 0xf) * 3; 3296 bgo = ((attr >> 16) & 0xf) * 3; 3297 3298 r0 = rasops_cmap[bgo]; 3299 r1 = rasops_cmap[fgo]; 3300 g0 = rasops_cmap[bgo + 1]; 3301 g1 = rasops_cmap[fgo + 1]; 3302 b0 = rasops_cmap[bgo + 2]; 3303 b1 = rasops_cmap[fgo + 2]; 3304 #define R3G3B2(r, g, b) ((r & 0xe0) | ((g >> 3) & 0x1c) | (b >> 6)) 3305 bg8 = R3G3B2(r0, g0, b0); 3306 fg8 = R3G3B2(r1, g1, b1); 3307 3308 radeonfb_wait_fifo(sc, 20); 3309 cnt = 0; 3310 for (i = 0; i < ri->ri_fontscale; i++) { 3311 aval = *data8; 3312 if (aval == 0) { 3313 pixel = bg8; 3314 } else if (aval == 255) { 3315 pixel = fg8; 3316 } else { 3317 r = aval * r1 + (255 - aval) * r0; 3318 g = aval * g1 + (255 - aval) * g0; 3319 b = aval * b1 + (255 - aval) * b0; 3320 pixel = ((r & 0xe000) >> 8) | 3321 ((g & 0xe000) >> 11) | 3322 ((b & 0xc000) >> 14); 3323 } 3324 latch |= pixel << (8 * (i & 3)); 3325 /* write in 32bit chunks */ 3326 if ((i & 3) == 3) { 3327 PUT32(sc, RADEON_HOST_DATA0, latch); 3328 /* 3329 * not strictly necessary, old data should be shifted 3330 * out 3331 */ 3332 latch = 0; 3333 cnt++; 3334 if (cnt > 16) { 3335 cnt = 0; 3336 radeonfb_wait_fifo(sc, 20); 3337 } 3338 } 3339 data8++; 3340 } 3341 /* if we have pixels left in latch write them out */ 3342 if ((i & 3) != 0) { 3343 /* 3344 * radeon is weird - apparently leftover pixels are written 3345 * from the middle, not from the left as everything else 3346 */ 3347 PUT32(sc, RADEON_HOST_DATA0, latch); 3348 } 3349 3350 if (rv == GC_ADD) { 3351 glyphcache_add(&dp->rd_gc, c, x, y); 3352 } else 3353 if (attr & 1) 3354 radeonfb_rectfill(dp, x, y + he - 2, wi, 1, fg); 3355 } 3356 3357 /* 3358 * wrapper for software character drawing 3359 * just sync the engine and call rasops*_putchar() 3360 */ 3361 3362 #ifndef RADEONFB_ALWAYS_ACCEL_PUTCHAR 3363 static void 3364 radeonfb_putchar_wrapper(void *cookie, int row, int col, u_int c, long attr) 3365 { 3366 struct rasops_info *ri = cookie; 3367 struct vcons_screen *scr = ri->ri_hw; 3368 struct radeonfb_display *dp = scr->scr_cookie; 3369 3370 radeonfb_engine_idle(dp->rd_softc); 3371 dp->rd_putchar(ri, row, col, c, attr); 3372 } 3373 #endif 3374 3375 static void 3376 radeonfb_eraserows(void *cookie, int row, int nrows, long fillattr) 3377 { 3378 struct rasops_info *ri = cookie; 3379 struct vcons_screen *scr = ri->ri_hw; 3380 struct radeonfb_display *dp = scr->scr_cookie; 3381 uint32_t x, y, w, h, fg, bg, ul; 3382 3383 /* XXX: check for full emulation mode? */ 3384 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 3385 x = ri->ri_xorigin; 3386 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 3387 w = ri->ri_emuwidth; 3388 h = ri->ri_font->fontheight * nrows; 3389 3390 rasops_unpack_attr(fillattr, &fg, &bg, &ul); 3391 radeonfb_rectfill(dp, x, y, w, h, ri->ri_devcmap[bg & 0xf]); 3392 } 3393 } 3394 3395 static void 3396 radeonfb_copyrows(void *cookie, int srcrow, int dstrow, int nrows) 3397 { 3398 struct rasops_info *ri = cookie; 3399 struct vcons_screen *scr = ri->ri_hw; 3400 struct radeonfb_display *dp = scr->scr_cookie; 3401 uint32_t x, ys, yd, w, h; 3402 3403 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 3404 x = ri->ri_xorigin; 3405 ys = ri->ri_yorigin + ri->ri_font->fontheight * srcrow; 3406 yd = ri->ri_yorigin + ri->ri_font->fontheight * dstrow; 3407 w = ri->ri_emuwidth; 3408 h = ri->ri_font->fontheight * nrows; 3409 radeonfb_bitblt(dp, x, ys, x, yd, w, h, 3410 RADEON_ROP3_S); 3411 } 3412 } 3413 3414 static void 3415 radeonfb_copycols(void *cookie, int row, int srccol, int dstcol, int ncols) 3416 { 3417 struct rasops_info *ri = cookie; 3418 struct vcons_screen *scr = ri->ri_hw; 3419 struct radeonfb_display *dp = scr->scr_cookie; 3420 uint32_t xs, xd, y, w, h; 3421 3422 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 3423 xs = ri->ri_xorigin + ri->ri_font->fontwidth * srccol; 3424 xd = ri->ri_xorigin + ri->ri_font->fontwidth * dstcol; 3425 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 3426 w = ri->ri_font->fontwidth * ncols; 3427 h = ri->ri_font->fontheight; 3428 radeonfb_bitblt(dp, xs, y, xd, y, w, h, 3429 RADEON_ROP3_S); 3430 } 3431 } 3432 3433 static void 3434 radeonfb_erasecols(void *cookie, int row, int startcol, int ncols, 3435 long fillattr) 3436 { 3437 struct rasops_info *ri = cookie; 3438 struct vcons_screen *scr = ri->ri_hw; 3439 struct radeonfb_display *dp = scr->scr_cookie; 3440 uint32_t x, y, w, h, fg, bg, ul; 3441 3442 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 3443 x = ri->ri_xorigin + ri->ri_font->fontwidth * startcol; 3444 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 3445 w = ri->ri_font->fontwidth * ncols; 3446 h = ri->ri_font->fontheight; 3447 3448 rasops_unpack_attr(fillattr, &fg, &bg, &ul); 3449 radeonfb_rectfill(dp, x, y, w, h, ri->ri_devcmap[bg & 0xf]); 3450 } 3451 } 3452 3453 static void 3454 radeonfb_cursor(void *cookie, int on, int row, int col) 3455 { 3456 struct rasops_info *ri = cookie; 3457 struct vcons_screen *scr = ri->ri_hw; 3458 struct radeonfb_display *dp = scr->scr_cookie; 3459 int x, y, wi, he; 3460 3461 wi = ri->ri_font->fontwidth; 3462 he = ri->ri_font->fontheight; 3463 3464 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 3465 x = ri->ri_ccol * wi + ri->ri_xorigin; 3466 y = ri->ri_crow * he + ri->ri_yorigin; 3467 /* first turn off the old cursor */ 3468 if (ri->ri_flg & RI_CURSOR) { 3469 radeonfb_bitblt(dp, x, y, x, y, wi, he, 3470 RADEON_ROP3_Dn); 3471 ri->ri_flg &= ~RI_CURSOR; 3472 } 3473 ri->ri_crow = row; 3474 ri->ri_ccol = col; 3475 /* then (possibly) turn on the new one */ 3476 if (on) { 3477 x = ri->ri_ccol * wi + ri->ri_xorigin; 3478 y = ri->ri_crow * he + ri->ri_yorigin; 3479 radeonfb_bitblt(dp, x, y, x, y, wi, he, 3480 RADEON_ROP3_Dn); 3481 ri->ri_flg |= RI_CURSOR; 3482 } 3483 } else { 3484 scr->scr_ri.ri_crow = row; 3485 scr->scr_ri.ri_ccol = col; 3486 scr->scr_ri.ri_flg &= ~RI_CURSOR; 3487 } 3488 } 3489 3490 /* 3491 * Underlying acceleration support. 3492 */ 3493 3494 static void 3495 radeonfb_rectfill(struct radeonfb_display *dp, int dstx, int dsty, 3496 int width, int height, uint32_t color) 3497 { 3498 struct radeonfb_softc *sc = dp->rd_softc; 3499 uint32_t gmc; 3500 3501 gmc = dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT; 3502 3503 radeonfb_wait_fifo(sc, 6); 3504 3505 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 3506 RADEON_GMC_BRUSH_SOLID_COLOR | 3507 RADEON_GMC_SRC_DATATYPE_COLOR | 3508 RADEON_GMC_CLR_CMP_CNTL_DIS | 3509 RADEON_ROP3_P | gmc); 3510 3511 PUT32(sc, RADEON_DP_BRUSH_FRGD_CLR, color); 3512 PUT32(sc, RADEON_DP_WRITE_MASK, 0xffffffff); 3513 PUT32(sc, RADEON_DP_CNTL, 3514 RADEON_DST_X_LEFT_TO_RIGHT | 3515 RADEON_DST_Y_TOP_TO_BOTTOM); 3516 PUT32(sc, RADEON_DST_Y_X, (dsty << 16) | dstx); 3517 PUT32(sc, RADEON_DST_WIDTH_HEIGHT, (width << 16) | (height)); 3518 } 3519 3520 static void 3521 radeonfb_rectfill_a(void *cookie, int dstx, int dsty, 3522 int width, int height, long attr) 3523 { 3524 struct radeonfb_display *dp = cookie; 3525 3526 radeonfb_rectfill(dp, dstx, dsty, width, height, 3527 dp->rd_vscreen.scr_ri.ri_devcmap[(attr >> 24 & 0xf)]); 3528 } 3529 3530 static void 3531 radeonfb_bitblt(void *cookie, int srcx, int srcy, 3532 int dstx, int dsty, int width, int height, int rop) 3533 { 3534 struct radeonfb_display *dp = cookie; 3535 struct radeonfb_softc *sc = dp->rd_softc; 3536 uint32_t gmc; 3537 uint32_t dir; 3538 3539 if (dsty < srcy) { 3540 dir = RADEON_DST_Y_TOP_TO_BOTTOM; 3541 } else { 3542 srcy += height - 1; 3543 dsty += height - 1; 3544 dir = 0; 3545 } 3546 if (dstx < srcx) { 3547 dir |= RADEON_DST_X_LEFT_TO_RIGHT; 3548 } else { 3549 srcx += width - 1; 3550 dstx += width - 1; 3551 } 3552 3553 gmc = dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT; 3554 3555 radeonfb_wait_fifo(sc, 6); 3556 3557 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 3558 RADEON_GMC_BRUSH_NONE | 3559 RADEON_GMC_SRC_DATATYPE_COLOR | 3560 RADEON_GMC_CLR_CMP_CNTL_DIS | 3561 RADEON_DP_SRC_SOURCE_MEMORY | 3562 rop | gmc); 3563 3564 PUT32(sc, RADEON_DP_WRITE_MASK, 0xffffffff); 3565 PUT32(sc, RADEON_DP_CNTL, dir); 3566 PUT32(sc, RADEON_SRC_Y_X, (srcy << 16) | srcx); 3567 PUT32(sc, RADEON_DST_Y_X, (dsty << 16) | dstx); 3568 PUT32(sc, RADEON_DST_WIDTH_HEIGHT, (width << 16) | (height)); 3569 } 3570 3571 static void 3572 radeonfb_engine_idle(struct radeonfb_softc *sc) 3573 { 3574 3575 radeonfb_wait_fifo(sc, 64); 3576 while ((GET32(sc, RADEON_RBBM_STATUS) & 3577 RADEON_RBBM_ACTIVE) != 0); 3578 radeonfb_engine_flush(sc); 3579 } 3580 3581 static inline void 3582 radeonfb_wait_fifo(struct radeonfb_softc *sc, int n) 3583 { 3584 int i; 3585 3586 for (i = RADEON_TIMEOUT; i; i--) { 3587 if ((GET32(sc, RADEON_RBBM_STATUS) & 3588 RADEON_RBBM_FIFOCNT_MASK) >= n) 3589 return; 3590 } 3591 #ifdef RADEONFB_DEBUG 3592 if (!i) 3593 printf("%s: timed out waiting for fifo (%x)\n", 3594 XNAME(sc), GET32(sc, RADEON_RBBM_STATUS)); 3595 #endif 3596 } 3597 3598 static void 3599 radeonfb_engine_flush(struct radeonfb_softc *sc) 3600 { 3601 int i = 0; 3602 3603 if (IS_R300(sc) || IS_AVIVO(sc)) { 3604 SET32(sc, R300_DSTCACHE_CTLSTAT, R300_RB2D_DC_FLUSH_ALL); 3605 while (GET32(sc, R300_DSTCACHE_CTLSTAT) & R300_RB2D_DC_BUSY) { 3606 i++; 3607 } 3608 } else { 3609 SET32(sc, RADEON_RB2D_DSTCACHE_CTLSTAT, 3610 RADEON_RB2D_DC_FLUSH_ALL); 3611 while (GET32(sc, RADEON_RB2D_DSTCACHE_CTLSTAT) & 3612 RADEON_RB2D_DC_BUSY) { 3613 i++; 3614 } 3615 } 3616 #ifdef DIAGNOSTIC 3617 if (i > RADEON_TIMEOUT) 3618 printf("%s: engine flush timed out!\n", XNAME(sc)); 3619 #endif 3620 } 3621 3622 static inline void 3623 radeonfb_unclip(struct radeonfb_softc *sc) 3624 { 3625 3626 radeonfb_wait_fifo(sc, 2); 3627 PUT32(sc, RADEON_SC_TOP_LEFT, 0); 3628 PUT32(sc, RADEON_SC_BOTTOM_RIGHT, 0x1fff1fff); 3629 } 3630 3631 static void 3632 radeonfb_engine_init(struct radeonfb_display *dp) 3633 { 3634 struct radeonfb_softc *sc = dp->rd_softc; 3635 uint32_t pitch; 3636 3637 /* no 3D */ 3638 PUT32(sc, RADEON_RB3D_CNTL, 0); 3639 3640 if (IS_AVIVO(sc)) { 3641 3642 #if 0 3643 /* XXX the xf86-video-radeon does this, causes lockups here */ 3644 psel = GET32(sc, R400_GB_PIPE_SELECT); 3645 PRINTREG(R400_GB_PIPE_SELECT); 3646 DPRINTF(("PLL %08x %08x\n", GETPLL(sc, R500_DYN_SCLK_PWMEM_PIPE), 3647 (1 | ((psel >> 8) & 0xf) << 4))); 3648 PUTPLL(sc, R500_DYN_SCLK_PWMEM_PIPE, (1 | ((psel >> 8) & 0xf) << 4)); 3649 #endif 3650 SET32(sc, RADEON_WAIT_UNTIL, RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN); 3651 SET32(sc, R300_DST_PIPE_CONFIG, R300_PIPE_AUTO_CONFIG); 3652 SET32(sc, R300_RB2D_DSTCACHE_MODE, R300_DC_AUTOFLUSH_ENABLE | 3653 R300_DC_DC_DISABLE_IGNORE_PE); 3654 } 3655 3656 PRINTREG(RADEON_RB3D_CNTL); 3657 PRINTREG(RADEON_DP_GUI_MASTER_CNTL); 3658 PRINTREG(RADEON_RBBM_STATUS); 3659 3660 radeonfb_engine_reset(sc); 3661 PRINTREG(RADEON_RBBM_STATUS); 3662 3663 /* 3664 * Apple OF hands us some radeons with tiling enabled - explicitly 3665 * disable it here 3666 */ 3667 PUT32(sc, RADEON_SURFACE_CNTL, RADEON_SURF_TRANSLATION_DIS); 3668 3669 radeonfb_wait_fifo(sc, 1); 3670 if (!IS_R300(sc) && !IS_AVIVO(sc)) 3671 PUT32(sc, RADEON_RB2D_DSTCACHE_MODE, 0); 3672 3673 radeonfb_wait_fifo(sc, 3); 3674 3675 /* 3676 * XXX 3677 * I strongly suspect this works mostly by accident on !AVIVO 3678 * AVIVO uses all 22 bits for the framebuffer offset, so it can 3679 * address up to 4GB. Older chips probably use bits 20-22 for other 3680 * things and we just so happen to set the right ones by having our 3681 * PCI/AGP space above 0x80000000. 3682 * Either way, r5xx does not work if we set these bits, while older 3683 * chips don't work without. 3684 */ 3685 pitch = (dp->rd_stride + 0x3f) >> 6; 3686 if (IS_AVIVO(sc)) { 3687 pitch = pitch << 22; 3688 } else 3689 pitch = (pitch << 22) | (sc->sc_aperbase >> 10); 3690 3691 PUT32(sc, RADEON_DEFAULT_PITCH_OFFSET, pitch); 3692 PUT32(sc, RADEON_DST_PITCH_OFFSET, pitch); 3693 PUT32(sc, RADEON_SRC_PITCH_OFFSET, pitch); 3694 3695 (void)GET32(sc, RADEON_DP_DATATYPE); 3696 3697 /* default scissors -- no clipping */ 3698 radeonfb_wait_fifo(sc, 1); 3699 PUT32(sc, RADEON_DEFAULT_SC_BOTTOM_RIGHT, 3700 RADEON_DEFAULT_SC_RIGHT_MAX | RADEON_DEFAULT_SC_BOTTOM_MAX); 3701 3702 radeonfb_wait_fifo(sc, 1); 3703 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 3704 (dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT) | 3705 RADEON_GMC_CLR_CMP_CNTL_DIS | 3706 RADEON_GMC_BRUSH_SOLID_COLOR | 3707 RADEON_GMC_SRC_DATATYPE_COLOR); 3708 3709 radeonfb_wait_fifo(sc, 10); 3710 PUT32(sc, RADEON_DST_LINE_START, 0); 3711 PUT32(sc, RADEON_DST_LINE_END, 0); 3712 PUT32(sc, RADEON_DP_BRUSH_FRGD_CLR, 0xffffffff); 3713 PUT32(sc, RADEON_DP_BRUSH_BKGD_CLR, 0); 3714 PUT32(sc, RADEON_DP_SRC_FRGD_CLR, 0xffffffff); 3715 PUT32(sc, RADEON_DP_SRC_BKGD_CLR, 0); 3716 PUT32(sc, RADEON_DP_WRITE_MASK, 0xffffffff); 3717 PUT32(sc, RADEON_SC_TOP_LEFT, 0); 3718 PUT32(sc, RADEON_SC_BOTTOM_RIGHT, 0x1fff1fff); 3719 PUT32(sc, RADEON_AUX_SC_CNTL, 0); 3720 radeonfb_engine_idle(sc); 3721 } 3722 3723 static void 3724 radeonfb_engine_reset(struct radeonfb_softc *sc) 3725 { 3726 uint32_t hpc, rbbm, mclkcntl, clkindex; 3727 3728 radeonfb_engine_flush(sc); 3729 3730 clkindex = GET32(sc, RADEON_CLOCK_CNTL_INDEX); 3731 if (HAS_R300CG(sc)) 3732 radeonfb_r300cg_workaround(sc); 3733 mclkcntl = GETPLL(sc, RADEON_MCLK_CNTL); 3734 3735 /* 3736 * According to comments in XFree code, resetting the HDP via 3737 * the RBBM_SOFT_RESET can cause bad behavior on some systems. 3738 * So we use HOST_PATH_CNTL instead. 3739 */ 3740 3741 hpc = GET32(sc, RADEON_HOST_PATH_CNTL); 3742 rbbm = GET32(sc, RADEON_RBBM_SOFT_RESET); 3743 if (IS_R300(sc) || IS_AVIVO(sc)) { 3744 PUT32(sc, RADEON_RBBM_SOFT_RESET, rbbm | 3745 RADEON_SOFT_RESET_CP | 3746 RADEON_SOFT_RESET_HI | 3747 RADEON_SOFT_RESET_E2); 3748 GET32(sc, RADEON_RBBM_SOFT_RESET); 3749 PUT32(sc, RADEON_RBBM_SOFT_RESET, 0); 3750 /* 3751 * XXX: this bit is not defined in any ATI docs I have, 3752 * nor in the XFree code, but XFree does it. Why? 3753 */ 3754 SET32(sc, RADEON_RB2D_DSTCACHE_MODE, R300_DC_DC_DISABLE_IGNORE_PE); 3755 } else { 3756 PUT32(sc, RADEON_RBBM_SOFT_RESET, rbbm | 3757 RADEON_SOFT_RESET_CP | 3758 RADEON_SOFT_RESET_SE | 3759 RADEON_SOFT_RESET_RE | 3760 RADEON_SOFT_RESET_PP | 3761 RADEON_SOFT_RESET_E2 | 3762 RADEON_SOFT_RESET_RB); 3763 GET32(sc, RADEON_RBBM_SOFT_RESET); 3764 PUT32(sc, RADEON_RBBM_SOFT_RESET, rbbm & 3765 ~(RADEON_SOFT_RESET_CP | 3766 RADEON_SOFT_RESET_SE | 3767 RADEON_SOFT_RESET_RE | 3768 RADEON_SOFT_RESET_PP | 3769 RADEON_SOFT_RESET_E2 | 3770 RADEON_SOFT_RESET_RB)); 3771 GET32(sc, RADEON_RBBM_SOFT_RESET); 3772 } 3773 3774 PUT32(sc, RADEON_HOST_PATH_CNTL, hpc | RADEON_HDP_SOFT_RESET); 3775 GET32(sc, RADEON_HOST_PATH_CNTL); 3776 PUT32(sc, RADEON_HOST_PATH_CNTL, hpc); 3777 3778 if (!IS_R300(sc) && !IS_AVIVO(sc)) 3779 PUT32(sc, RADEON_RBBM_SOFT_RESET, rbbm); 3780 3781 PUT32(sc, RADEON_CLOCK_CNTL_INDEX, clkindex); 3782 PRINTREG(RADEON_CLOCK_CNTL_INDEX); 3783 PUTPLL(sc, RADEON_MCLK_CNTL, mclkcntl); 3784 3785 if (HAS_R300CG(sc)) 3786 radeonfb_r300cg_workaround(sc); 3787 } 3788 3789 static int 3790 radeonfb_set_curpos(struct radeonfb_display *dp, struct wsdisplay_curpos *pos) 3791 { 3792 int x, y; 3793 3794 x = pos->x; 3795 y = pos->y; 3796 3797 /* 3798 * This doesn't let a cursor move off the screen. I'm not 3799 * sure if this will have negative effects for e.g. Xinerama. 3800 * I'd guess Xinerama handles it by changing the cursor shape, 3801 * but that needs verification. 3802 */ 3803 if (x >= dp->rd_virtx) 3804 x = dp->rd_virtx - 1; 3805 if (x < 0) 3806 x = 0; 3807 if (y >= dp->rd_virty) 3808 y = dp->rd_virty - 1; 3809 if (y < 0) 3810 y = 0; 3811 3812 dp->rd_cursor.rc_pos.x = x; 3813 dp->rd_cursor.rc_pos.y = y; 3814 3815 radeonfb_cursor_position(dp); 3816 return 0; 3817 } 3818 3819 static int 3820 radeonfb_set_cursor(struct radeonfb_display *dp, struct wsdisplay_cursor *wc) 3821 { 3822 unsigned flags; 3823 3824 uint8_t r[2], g[2], b[2]; 3825 unsigned index, count; 3826 int i, err; 3827 int pitch, size; 3828 struct radeonfb_cursor *nc = &dp->rd_tempcursor; 3829 3830 flags = wc->which; 3831 3832 /* copy old values */ 3833 memcpy(nc, &dp->rd_cursor, sizeof(struct radeonfb_cursor)); 3834 3835 if (flags & WSDISPLAY_CURSOR_DOCMAP) { 3836 index = wc->cmap.index; 3837 count = wc->cmap.count; 3838 3839 if (index >= 2 || count > 2 - index) 3840 return EINVAL; 3841 3842 err = copyin(wc->cmap.red, &r[index], count); 3843 if (err) 3844 return err; 3845 err = copyin(wc->cmap.green, &g[index], count); 3846 if (err) 3847 return err; 3848 err = copyin(wc->cmap.blue, &b[index], count); 3849 if (err) 3850 return err; 3851 3852 for (i = index; i < index + count; i++) { 3853 nc->rc_cmap[i] = 3854 (r[i] << 16) + (g[i] << 8) + (b[i] << 0); 3855 } 3856 } 3857 3858 if (flags & WSDISPLAY_CURSOR_DOSHAPE) { 3859 if ((wc->size.x > RADEON_CURSORMAXX) || 3860 (wc->size.y > RADEON_CURSORMAXY)) 3861 return EINVAL; 3862 3863 /* figure bytes per line */ 3864 pitch = (wc->size.x + 7) / 8; 3865 size = pitch * wc->size.y; 3866 3867 /* clear the old cursor and mask */ 3868 memset(nc->rc_image, 0, 512); 3869 memset(nc->rc_mask, 0, 512); 3870 3871 nc->rc_size = wc->size; 3872 3873 if ((err = copyin(wc->image, nc->rc_image, size)) != 0) 3874 return err; 3875 3876 if ((err = copyin(wc->mask, nc->rc_mask, size)) != 0) 3877 return err; 3878 } 3879 3880 if (flags & WSDISPLAY_CURSOR_DOHOT) { 3881 nc->rc_hot = wc->hot; 3882 if (nc->rc_hot.x >= nc->rc_size.x) 3883 nc->rc_hot.x = nc->rc_size.x - 1; 3884 if (nc->rc_hot.y >= nc->rc_size.y) 3885 nc->rc_hot.y = nc->rc_size.y - 1; 3886 } 3887 3888 if (flags & WSDISPLAY_CURSOR_DOPOS) { 3889 nc->rc_pos = wc->pos; 3890 if (nc->rc_pos.x >= dp->rd_virtx) 3891 nc->rc_pos.x = dp->rd_virtx - 1; 3892 #if 0 3893 if (nc->rc_pos.x < 0) 3894 nc->rc_pos.x = 0; 3895 #endif 3896 if (nc->rc_pos.y >= dp->rd_virty) 3897 nc->rc_pos.y = dp->rd_virty - 1; 3898 #if 0 3899 if (nc->rc_pos.y < 0) 3900 nc->rc_pos.y = 0; 3901 #endif 3902 } 3903 if (flags & WSDISPLAY_CURSOR_DOCUR) { 3904 nc->rc_visible = wc->enable; 3905 } 3906 3907 memcpy(&dp->rd_cursor, nc, sizeof(struct radeonfb_cursor)); 3908 radeonfb_cursor_update(dp, wc->which); 3909 3910 return 0; 3911 } 3912 3913 static uint8_t 3914 radeonfb_backwards(uint8_t d) 3915 { 3916 uint8_t l; 3917 3918 l = d << 7; 3919 l |= ((d & 0x02) << 5); 3920 l |= ((d & 0x04) << 3); 3921 l |= ((d & 0x08) << 1); 3922 l |= ((d & 0x10) >> 1); 3923 l |= ((d & 0x20) >> 3); 3924 l |= ((d & 0x40) >> 5); 3925 l |= ((d & 0x80) >> 7); 3926 return l; 3927 } 3928 3929 /* 3930 * Change the cursor shape. Call this with the cursor locked to avoid 3931 * flickering/tearing. 3932 */ 3933 static void 3934 radeonfb_cursor_shape(struct radeonfb_display *dp) 3935 { 3936 uint8_t and[512], xor[512]; 3937 int i, j, src, dst /* , pitch */; 3938 const uint8_t *msk = dp->rd_cursor.rc_mask; 3939 const uint8_t *img = dp->rd_cursor.rc_image; 3940 3941 /* 3942 * Radeon cursor data interleaves one line of AND data followed 3943 * by a line of XOR data. (Each line corresponds to a whole hardware 3944 * pitch - i.e. 64 pixels or 8 bytes.) 3945 * 3946 * The cursor is displayed using the following table: 3947 * 3948 * AND XOR Result 3949 * ---------------------- 3950 * 0 0 Cursor color 0 3951 * 0 1 Cursor color 1 3952 * 1 0 Transparent 3953 * 1 1 Complement of background 3954 * 3955 * Our masks are therefore different from what we were passed. 3956 * Passed in, I'm assuming the data represents either color 0 or 1, 3957 * and a mask, so the passed in table looks like: 3958 * 3959 * IMG Mask Result 3960 * ----------------------- 3961 * 0 0 Transparent 3962 * 0 1 Cursor color 0 3963 * 1 0 Transparent 3964 * 1 1 Cursor color 1 3965 * 3966 * IF mask bit == 1, AND = 0, XOR = color. 3967 * IF mask bit == 0, AND = 1, XOR = 0. 3968 * 3969 * hence: AND = ~(mask); XOR = color & ~(mask); 3970 */ 3971 3972 /* pitch = ((dp->rd_cursor.rc_size.x + 7) / 8); */ 3973 3974 /* start by assuming all bits are transparent */ 3975 memset(and, 0xff, 512); 3976 memset(xor, 0x00, 512); 3977 3978 src = 0; 3979 dst = 0; 3980 for (i = 0; i < 64; i++) { 3981 for (j = 0; j < 64; j += 8) { 3982 if ((i < dp->rd_cursor.rc_size.y) && 3983 (j < dp->rd_cursor.rc_size.x)) { 3984 3985 /* take care to leave odd bits alone */ 3986 and[dst] &= ~(msk[src]); 3987 xor[dst] = img[src] & msk[src]; 3988 src++; 3989 } 3990 dst++; 3991 } 3992 } 3993 3994 for (i = 0; i < 512; i++) { 3995 and[i] = radeonfb_backwards(and[i]); 3996 xor[i] = radeonfb_backwards(xor[i]); 3997 } 3998 3999 /* copy the image into place */ 4000 for (i = 0; i < 64; i++) { 4001 memcpy((uint8_t *)dp->rd_curptr + (i * 16), 4002 &and[i * 8], 8); 4003 memcpy((uint8_t *)dp->rd_curptr + (i * 16) + 8, 4004 &xor[i * 8], 8); 4005 } 4006 } 4007 4008 /* 4009 * We use the cursor in 24bit mode on avivo, much simpler than the above. 4010 * Should probably do the same on older radeons 4011 */ 4012 static void 4013 radeonfb_avivo_cursor_shape(struct radeonfb_display *dp) 4014 { 4015 const uint8_t *msk = dp->rd_cursor.rc_mask; 4016 const uint8_t *img = dp->rd_cursor.rc_image; 4017 uint32_t *out = (uint32_t *)dp->rd_curptr; 4018 uint8_t bit; 4019 int i, j, px; 4020 4021 for (i = 0; i < 64 * 8; i++) { 4022 bit = 0x01; 4023 for (j = 0; j < 8; j++) { 4024 px = ((*msk & bit) ? 2 : 0) | ((*img & bit) ? 1 : 0); 4025 switch (px) { 4026 case 0: 4027 case 1: 4028 *out = htole32(0x00000000); 4029 break; 4030 case 2: 4031 *out = htole32(0xff000000 | 4032 dp->rd_cursor.rc_cmap[0]); 4033 break; 4034 case 3: 4035 *out = htole32(0xff000000 | 4036 dp->rd_cursor.rc_cmap[1]); 4037 break; 4038 } 4039 out++; 4040 bit = bit << 1; 4041 } 4042 msk++; 4043 img++; 4044 } 4045 } 4046 4047 static void 4048 radeonfb_cursor_position(struct radeonfb_display *dp) 4049 { 4050 struct radeonfb_softc *sc = dp->rd_softc; 4051 uint32_t offset, hvoff, hvpos; /* registers */ 4052 uint32_t coff; /* cursor offset */ 4053 int i, x, y, xoff, yoff, crtcoff, lock; 4054 4055 /* 4056 * XXX: this also needs to handle pan/scan 4057 */ 4058 for (i = 0; i < dp->rd_ncrtcs; i++) { 4059 4060 struct radeonfb_crtc *rcp = &dp->rd_crtcs[i]; 4061 4062 SET32(sc, AVIVO_D1CUR_UPDATE, AVIVO_D1CURSOR_UPDATE_LOCK); 4063 PUT32(sc, AVIVO_D1CUR_SIZE, 0x003f003f); 4064 if (IS_AVIVO(sc)) { 4065 if (rcp->rc_number) { 4066 offset = AVIVO_D2CUR_SURFACE_ADDRESS; 4067 hvoff = AVIVO_D2CUR_HOT_SPOT; 4068 hvpos = AVIVO_D2CUR_POSITION; 4069 crtcoff = 0/*RADEON_CRTC_OFFSET*/; 4070 } else { 4071 offset = AVIVO_D1CUR_SURFACE_ADDRESS; 4072 hvoff = AVIVO_D1CUR_HOT_SPOT; 4073 hvpos = AVIVO_D1CUR_POSITION; 4074 crtcoff = 0/*RADEON_CRTC_OFFSET*/; 4075 } 4076 lock = 0; 4077 } else { 4078 if (rcp->rc_number) { 4079 offset = RADEON_CUR2_OFFSET; 4080 hvoff = RADEON_CUR2_HORZ_VERT_OFF; 4081 hvpos = RADEON_CUR2_HORZ_VERT_POSN; 4082 crtcoff = RADEON_CRTC2_OFFSET; 4083 } else { 4084 offset = RADEON_CUR_OFFSET; 4085 hvoff = RADEON_CUR_HORZ_VERT_OFF; 4086 hvpos = RADEON_CUR_HORZ_VERT_POSN; 4087 crtcoff = RADEON_CRTC_OFFSET; 4088 } 4089 lock = RADEON_CUR_LOCK; 4090 } 4091 4092 x = dp->rd_cursor.rc_pos.x; 4093 y = dp->rd_cursor.rc_pos.y; 4094 4095 while (y < rcp->rc_yoffset) { 4096 rcp->rc_yoffset -= RADEON_PANINCREMENT; 4097 } 4098 while (y >= (rcp->rc_yoffset + rcp->rc_videomode.vdisplay)) { 4099 rcp->rc_yoffset += RADEON_PANINCREMENT; 4100 } 4101 while (x < rcp->rc_xoffset) { 4102 rcp->rc_xoffset -= RADEON_PANINCREMENT; 4103 } 4104 while (x >= (rcp->rc_xoffset + rcp->rc_videomode.hdisplay)) { 4105 rcp->rc_xoffset += RADEON_PANINCREMENT; 4106 } 4107 4108 /* adjust for the cursor's hotspot */ 4109 x -= dp->rd_cursor.rc_hot.x; 4110 y -= dp->rd_cursor.rc_hot.y; 4111 xoff = yoff = 0; 4112 4113 if (x >= dp->rd_virtx) 4114 x = dp->rd_virtx - 1; 4115 if (y >= dp->rd_virty) 4116 y = dp->rd_virty - 1; 4117 4118 /* now adjust cursor so it is relative to viewport */ 4119 x -= rcp->rc_xoffset; 4120 y -= rcp->rc_yoffset; 4121 4122 /* 4123 * no need to check for fall off, because we should 4124 * never move off the screen entirely! 4125 */ 4126 coff = 0; 4127 if (x < 0) { 4128 xoff = -x; 4129 x = 0; 4130 } 4131 if (y < 0) { 4132 yoff = -y; 4133 y = 0; 4134 coff = (yoff * 2) * 8; 4135 } 4136 4137 /* pan the display */ 4138 if (crtcoff != 0) 4139 PUT32(sc, crtcoff, (rcp->rc_yoffset * dp->rd_stride) + 4140 rcp->rc_xoffset); 4141 4142 PUT32(sc, offset, (dp->rd_curoff + coff) | lock); 4143 PUT32(sc, hvoff, (xoff << 16) | (yoff) | lock); 4144 /* NB: this unlocks the cursor */ 4145 PUT32(sc, hvpos, (x << 16) | y); 4146 if (IS_AVIVO(sc)) 4147 CLR32(sc, AVIVO_D1CUR_UPDATE, AVIVO_D1CURSOR_UPDATE_LOCK); 4148 } 4149 } 4150 4151 static void 4152 radeonfb_cursor_visible(struct radeonfb_display *dp) 4153 { 4154 struct radeonfb_softc *sc = dp->rd_softc; 4155 int i; 4156 uint32_t gencntl, bit; 4157 4158 for (i = 0; i < dp->rd_ncrtcs; i++) { 4159 if (IS_AVIVO(sc)) { 4160 SET32(sc, AVIVO_D1CUR_UPDATE, AVIVO_D1CURSOR_UPDATE_LOCK); 4161 if (dp->rd_crtcs[i].rc_number) { 4162 gencntl = AVIVO_D2CUR_CONTROL; 4163 bit = AVIVO_D1CURSOR_EN | (2 << 8); 4164 } else { 4165 gencntl = AVIVO_D1CUR_CONTROL; 4166 bit = AVIVO_D1CURSOR_EN | (2 << 8); 4167 } 4168 } else { 4169 if (dp->rd_crtcs[i].rc_number) { 4170 gencntl = RADEON_CRTC2_GEN_CNTL; 4171 bit = RADEON_CRTC2_CUR_EN; 4172 } else { 4173 gencntl = RADEON_CRTC_GEN_CNTL; 4174 bit = RADEON_CRTC_CUR_EN; 4175 } 4176 } 4177 if (dp->rd_cursor.rc_visible) 4178 SET32(dp->rd_softc, gencntl, bit); 4179 else 4180 CLR32(dp->rd_softc, gencntl, bit); 4181 if (IS_AVIVO(sc)) 4182 CLR32(sc, AVIVO_D1CUR_UPDATE, AVIVO_D1CURSOR_UPDATE_LOCK); 4183 4184 } 4185 } 4186 4187 static void 4188 radeonfb_cursor_cmap(struct radeonfb_display *dp) 4189 { 4190 int i; 4191 uint32_t c0reg, c1reg; 4192 struct radeonfb_softc *sc = dp->rd_softc; 4193 4194 for (i = 0; i < dp->rd_ncrtcs; i++) { 4195 if (dp->rd_crtcs[i].rc_number) { 4196 c0reg = RADEON_CUR2_CLR0; 4197 c1reg = RADEON_CUR2_CLR1; 4198 } else { 4199 c0reg = RADEON_CUR_CLR0; 4200 c1reg = RADEON_CUR_CLR1; 4201 } 4202 4203 PUT32(sc, c0reg, dp->rd_cursor.rc_cmap[0]); 4204 PUT32(sc, c1reg, dp->rd_cursor.rc_cmap[1]); 4205 } 4206 } 4207 4208 static void 4209 radeonfb_cursor_update(struct radeonfb_display *dp, unsigned which) 4210 { 4211 struct radeonfb_softc *sc; 4212 int i; 4213 4214 sc = dp->rd_softc; 4215 4216 for (i = 0; i < dp->rd_ncrtcs; i++) { 4217 if (dp->rd_crtcs[i].rc_number) { 4218 if (IS_AVIVO(sc)) { 4219 SET32(sc, AVIVO_D2CUR_UPDATE, AVIVO_D1CURSOR_UPDATE_LOCK); 4220 } else 4221 SET32(sc, RADEON_CUR2_OFFSET, RADEON_CUR_LOCK); 4222 } else { 4223 if (IS_AVIVO(sc)) { 4224 SET32(sc, AVIVO_D1CUR_UPDATE, AVIVO_D1CURSOR_UPDATE_LOCK); 4225 } else 4226 SET32(sc, RADEON_CUR_OFFSET,RADEON_CUR_LOCK); 4227 } 4228 } 4229 4230 if (which & WSDISPLAY_CURSOR_DOCMAP) { 4231 if (IS_AVIVO(sc)) { 4232 /* 4233 * we use an ARGB cursor here, so we need to rebuild 4234 * the cursor image every time the palette changes 4235 */ 4236 radeonfb_avivo_cursor_shape(dp); 4237 } else 4238 radeonfb_cursor_cmap(dp); 4239 } 4240 4241 if (which & WSDISPLAY_CURSOR_DOSHAPE) { 4242 if (IS_AVIVO(sc)) { 4243 radeonfb_avivo_cursor_shape(dp); 4244 } else 4245 radeonfb_cursor_shape(dp); 4246 } 4247 4248 if (which & WSDISPLAY_CURSOR_DOCUR) 4249 radeonfb_cursor_visible(dp); 4250 4251 /* this one is unconditional, because it updates other stuff */ 4252 radeonfb_cursor_position(dp); 4253 } 4254 4255 static struct videomode * 4256 radeonfb_best_refresh(struct videomode *m1, struct videomode *m2) 4257 { 4258 int r1, r2; 4259 4260 /* otherwise pick the higher refresh rate */ 4261 r1 = DIVIDE(DIVIDE(m1->dot_clock, m1->htotal), m1->vtotal); 4262 r2 = DIVIDE(DIVIDE(m2->dot_clock, m2->htotal), m2->vtotal); 4263 4264 return (r1 < r2 ? m2 : m1); 4265 } 4266 4267 static const struct videomode * 4268 radeonfb_port_mode(struct radeonfb_softc *sc, struct radeonfb_port *rp, 4269 int x, int y) 4270 { 4271 struct edid_info *ep = &rp->rp_edid; 4272 struct videomode *vmp = NULL; 4273 int i; 4274 4275 if (!rp->rp_edid_valid) { 4276 /* fallback to safe mode */ 4277 return radeonfb_modelookup(sc->sc_defaultmode); 4278 } 4279 4280 /* always choose the preferred mode first! */ 4281 if (ep->edid_preferred_mode) { 4282 4283 /* XXX: add auto-stretching support for native mode */ 4284 4285 /* this may want panning to occur, btw */ 4286 if ((ep->edid_preferred_mode->hdisplay <= x) && 4287 (ep->edid_preferred_mode->vdisplay <= y)) 4288 return ep->edid_preferred_mode; 4289 } 4290 4291 for (i = 0; i < ep->edid_nmodes; i++) { 4292 /* 4293 * We elect to pick a resolution that is too large for 4294 * the monitor than one that is too small. This means 4295 * that we will prefer to pan rather than to try to 4296 * center a smaller display on a larger screen. In 4297 * practice, this shouldn't matter because if a 4298 * monitor can support a larger resolution, it can 4299 * probably also support the smaller. A specific 4300 * exception is fixed format panels, but hopefully 4301 * they are properly dealt with by the "autostretch" 4302 * logic above. 4303 */ 4304 if ((ep->edid_modes[i].hdisplay > x) || 4305 (ep->edid_modes[i].vdisplay > y)) { 4306 continue; 4307 } 4308 4309 /* 4310 * at this point, the display mode is no larger than 4311 * what we've requested. 4312 */ 4313 if (vmp == NULL) 4314 vmp = &ep->edid_modes[i]; 4315 4316 /* eliminate smaller modes */ 4317 if ((vmp->hdisplay >= ep->edid_modes[i].hdisplay) || 4318 (vmp->vdisplay >= ep->edid_modes[i].vdisplay)) 4319 continue; 4320 4321 if ((vmp->hdisplay < ep->edid_modes[i].hdisplay) || 4322 (vmp->vdisplay < ep->edid_modes[i].vdisplay)) { 4323 vmp = &ep->edid_modes[i]; 4324 continue; 4325 } 4326 4327 KASSERT(vmp->hdisplay == ep->edid_modes[i].hdisplay); 4328 KASSERT(vmp->vdisplay == ep->edid_modes[i].vdisplay); 4329 4330 vmp = radeonfb_best_refresh(vmp, &ep->edid_modes[i]); 4331 } 4332 4333 return (vmp ? vmp : radeonfb_modelookup(sc->sc_defaultmode)); 4334 } 4335 4336 static int 4337 radeonfb_hasres(struct videomode *list, int nlist, int x, int y) 4338 { 4339 int i; 4340 4341 for (i = 0; i < nlist; i++) { 4342 if ((x == list[i].hdisplay) && 4343 (y == list[i].vdisplay)) { 4344 return 1; 4345 } 4346 } 4347 return 0; 4348 } 4349 4350 static void 4351 radeonfb_pickres(struct radeonfb_display *dp, uint16_t *x, uint16_t *y, 4352 int pan) 4353 { 4354 struct radeonfb_port *rp; 4355 struct edid_info *ep; 4356 int i, j; 4357 4358 *x = 0; 4359 *y = 0; 4360 4361 if (pan) { 4362 for (i = 0; i < dp->rd_ncrtcs; i++) { 4363 rp = dp->rd_crtcs[i].rc_port; 4364 ep = &rp->rp_edid; 4365 if (!rp->rp_edid_valid) { 4366 /* monitor not present */ 4367 continue; 4368 } 4369 4370 /* 4371 * For now we are ignoring "conflict" that 4372 * could occur when mixing some modes like 4373 * 1280x1024 and 1400x800. It isn't clear 4374 * which is better, so the first one wins. 4375 */ 4376 for (j = 0; j < ep->edid_nmodes; j++) { 4377 /* 4378 * ignore resolutions that are too big for 4379 * the radeon 4380 */ 4381 if (ep->edid_modes[j].hdisplay > 4382 dp->rd_softc->sc_maxx) 4383 continue; 4384 if (ep->edid_modes[j].vdisplay > 4385 dp->rd_softc->sc_maxy) 4386 continue; 4387 4388 /* 4389 * pick largest resolution, the 4390 * smaller monitor will pan 4391 */ 4392 if ((ep->edid_modes[j].hdisplay >= *x) && 4393 (ep->edid_modes[j].vdisplay >= *y)) { 4394 *x = ep->edid_modes[j].hdisplay; 4395 *y = ep->edid_modes[j].vdisplay; 4396 } 4397 } 4398 } 4399 4400 } else { 4401 struct videomode *modes; 4402 size_t smodes; 4403 int nmodes = 0; 4404 int valid = 0; 4405 4406 smodes = sizeof(struct videomode) * 64; 4407 modes = kmem_alloc(smodes, KM_SLEEP); 4408 4409 for (i = 0; i < dp->rd_ncrtcs; i++) { 4410 /* 4411 * pick the largest resolution in common. 4412 */ 4413 rp = dp->rd_crtcs[i].rc_port; 4414 ep = &rp->rp_edid; 4415 4416 if (!rp->rp_edid_valid) 4417 continue; 4418 4419 if (!valid) { 4420 /* 4421 * Pick the preferred mode for this port 4422 * if available. 4423 */ 4424 if (ep->edid_preferred_mode) { 4425 struct videomode *vmp = 4426 ep->edid_preferred_mode; 4427 4428 if ((vmp->hdisplay <= 4429 dp->rd_softc->sc_maxx) && 4430 (vmp->vdisplay <= 4431 dp->rd_softc->sc_maxy)) 4432 modes[nmodes++] = *vmp; 4433 } else { 4434 4435 /* initialize starting list */ 4436 for (j = 0; j < ep->edid_nmodes; j++) { 4437 /* 4438 * ignore resolutions that are 4439 * too big for the radeon 4440 */ 4441 if (ep->edid_modes[j].hdisplay > 4442 dp->rd_softc->sc_maxx) 4443 continue; 4444 if (ep->edid_modes[j].vdisplay > 4445 dp->rd_softc->sc_maxy) 4446 continue; 4447 4448 modes[nmodes] = 4449 ep->edid_modes[j]; 4450 nmodes++; 4451 } 4452 } 4453 valid = 1; 4454 } else { 4455 /* merge into preexisting list */ 4456 for (j = 0; j < nmodes; j++) { 4457 if (!radeonfb_hasres(ep->edid_modes, 4458 ep->edid_nmodes, 4459 modes[j].hdisplay, 4460 modes[j].vdisplay)) { 4461 modes[j] = modes[nmodes]; 4462 j--; 4463 nmodes--; 4464 } 4465 } 4466 } 4467 } 4468 4469 /* now we have to pick from the merged list */ 4470 for (i = 0; i < nmodes; i++) { 4471 if ((modes[i].hdisplay >= *x) && 4472 (modes[i].vdisplay >= *y)) { 4473 *x = modes[i].hdisplay; 4474 *y = modes[i].vdisplay; 4475 } 4476 } 4477 kmem_free(modes, smodes); 4478 4479 } 4480 4481 if ((*x == 0) || (*y == 0)) { 4482 /* fallback to safe mode */ 4483 *x = 640; 4484 *y = 480; 4485 } 4486 } 4487 4488 /* 4489 * backlight levels are linear on: 4490 * - RV200, RV250, RV280, RV350 4491 * - but NOT on PowerBook4,3 6,3 6,5 4492 * according to Linux' radeonfb 4493 */ 4494 4495 /* Get the current backlight level for the display. */ 4496 4497 static int 4498 radeonfb_get_backlight(struct radeonfb_display *dp) 4499 { 4500 int s; 4501 uint32_t level; 4502 4503 s = spltty(); 4504 4505 level = radeonfb_get32(dp->rd_softc, RADEON_LVDS_GEN_CNTL); 4506 level &= RADEON_LVDS_BL_MOD_LEV_MASK; 4507 level >>= RADEON_LVDS_BL_MOD_LEV_SHIFT; 4508 4509 /* 4510 * On some chips, we should negate the backlight level. 4511 * XXX Find out on which chips. 4512 */ 4513 if (dp->rd_softc->sc_flags & RFB_INV_BLIGHT) 4514 level = RADEONFB_BACKLIGHT_MAX - level; 4515 4516 splx(s); 4517 4518 return level; 4519 } 4520 4521 /* Set the backlight to the given level for the display. */ 4522 static void 4523 radeonfb_switch_backlight(struct radeonfb_display *dp, int on) 4524 { 4525 if (dp->rd_bl_on == on) 4526 return; 4527 dp->rd_bl_on = on; 4528 radeonfb_set_backlight(dp, dp->rd_bl_level); 4529 } 4530 4531 static int 4532 radeonfb_set_backlight(struct radeonfb_display *dp, int level) 4533 { 4534 struct radeonfb_softc *sc = dp->rd_softc; 4535 int rlevel, s; 4536 uint32_t lvds; 4537 4538 if(!sc->sc_mapped) 4539 return 0; 4540 4541 s = spltty(); 4542 4543 dp->rd_bl_level = level; 4544 if (dp->rd_bl_on == 0) 4545 level = 0; 4546 4547 if (level < 0) 4548 level = 0; 4549 else if (level >= RADEONFB_BACKLIGHT_MAX) 4550 level = RADEONFB_BACKLIGHT_MAX; 4551 4552 /* On some chips, we should negate the backlight level. */ 4553 if (dp->rd_softc->sc_flags & RFB_INV_BLIGHT) { 4554 rlevel = RADEONFB_BACKLIGHT_MAX - level; 4555 } else 4556 rlevel = level; 4557 4558 callout_stop(&dp->rd_bl_lvds_co); 4559 //radeonfb_engine_idle(sc); 4560 4561 /* 4562 * Turn off the display if the backlight is set to 0, since the 4563 * display is useless without backlight anyway. 4564 */ 4565 if (level == 0) 4566 radeonfb_blank(dp, 1); 4567 else if (radeonfb_get_backlight(dp) == 0) 4568 radeonfb_blank(dp, 0); 4569 4570 lvds = radeonfb_get32(sc, RADEON_LVDS_GEN_CNTL); 4571 lvds &= ~RADEON_LVDS_DISPLAY_DIS; 4572 if (!(lvds & RADEON_LVDS_BLON) || !(lvds & RADEON_LVDS_ON)) { 4573 lvds |= dp->rd_bl_lvds_val & RADEON_LVDS_DIGON; 4574 lvds |= RADEON_LVDS_BLON | RADEON_LVDS_EN; 4575 radeonfb_put32(sc, RADEON_LVDS_GEN_CNTL, lvds); 4576 lvds &= ~RADEON_LVDS_BL_MOD_LEV_MASK; 4577 lvds |= rlevel << RADEON_LVDS_BL_MOD_LEV_SHIFT; 4578 lvds |= RADEON_LVDS_ON; 4579 lvds |= dp->rd_bl_lvds_val & RADEON_LVDS_BL_MOD_EN; 4580 } else { 4581 lvds &= ~RADEON_LVDS_BL_MOD_LEV_MASK; 4582 lvds |= rlevel << RADEON_LVDS_BL_MOD_LEV_SHIFT; 4583 radeonfb_put32(sc, RADEON_LVDS_GEN_CNTL, lvds); 4584 } 4585 4586 dp->rd_bl_lvds_val &= ~RADEON_LVDS_STATE_MASK; 4587 dp->rd_bl_lvds_val |= lvds & RADEON_LVDS_STATE_MASK; 4588 /* XXX What is the correct delay? */ 4589 callout_schedule(&dp->rd_bl_lvds_co, 200 * hz); 4590 4591 splx(s); 4592 4593 return 0; 4594 } 4595 4596 /* 4597 * Callout function for delayed operations on the LVDS_GEN_CNTL register. 4598 * Set the delayed bits in the register, and clear the stored delayed 4599 * value. 4600 */ 4601 4602 static void radeonfb_lvds_callout(void *arg) 4603 { 4604 struct radeonfb_display *dp = arg; 4605 int s; 4606 4607 s = splhigh(); 4608 4609 radeonfb_mask32(dp->rd_softc, RADEON_LVDS_GEN_CNTL, ~0, 4610 dp->rd_bl_lvds_val); 4611 dp->rd_bl_lvds_val = 0; 4612 4613 splx(s); 4614 } 4615 4616 static void 4617 radeonfb_brightness_up(device_t dev) 4618 { 4619 struct radeonfb_softc *sc = device_private(dev); 4620 struct radeonfb_display *dp = &sc->sc_displays[0]; 4621 int level; 4622 4623 /* we assume the main display is the first one - need a better way */ 4624 if (sc->sc_ndisplays < 1) return; 4625 /* make sure pushing the hotkeys always has an effect */ 4626 dp->rd_bl_on = 1; 4627 level = dp->rd_bl_level; 4628 level = uimin(RADEONFB_BACKLIGHT_MAX, level + 5); 4629 radeonfb_set_backlight(dp, level); 4630 } 4631 4632 static void 4633 radeonfb_brightness_down(device_t dev) 4634 { 4635 struct radeonfb_softc *sc = device_private(dev); 4636 struct radeonfb_display *dp = &sc->sc_displays[0]; 4637 int level; 4638 4639 /* we assume the main display is the first one - need a better way */ 4640 if (sc->sc_ndisplays < 1) return; 4641 /* make sure pushing the hotkeys always has an effect */ 4642 dp->rd_bl_on = 1; 4643 level = dp->rd_bl_level; 4644 level = uimax(0, level - 5); 4645 radeonfb_set_backlight(dp, level); 4646 } 4647
Indexes created Mon Sep 29 21:09:56 GMT 2025