radeonfb.c revision 1.112.2.1
1 /* $NetBSD: radeonfb.c,v 1.112.2.1 2021/04/03 22:28:49 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 2006 Itronix Inc. 5 * All rights reserved. 6 * 7 * Written by Garrett D'Amore for Itronix Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. The name of Itronix Inc. may not be used to endorse 18 * or promote products derived from this software without specific 19 * prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY ITRONIX INC. ``AS IS'' AND ANY EXPRESS 22 * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 23 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL ITRONIX INC. BE LIABLE FOR ANY 25 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE 27 * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 29 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 30 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 31 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * ATI Technologies Inc. ("ATI") has not assisted in the creation of, and 36 * does not endorse, this software. ATI will not be responsible or liable 37 * for any actual or alleged damage or loss caused by or in connection with 38 * the use of or reliance on this software. 39 */ 40 41 /* 42 * Portions of this code were taken from XFree86's Radeon driver, which bears 43 * this notice: 44 * 45 * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and 46 * VA Linux Systems Inc., Fremont, California. 47 * 48 * All Rights Reserved. 49 * 50 * Permission is hereby granted, free of charge, to any person obtaining 51 * a copy of this software and associated documentation files (the 52 * "Software"), to deal in the Software without restriction, including 53 * without limitation on the rights to use, copy, modify, merge, 54 * publish, distribute, sublicense, and/or sell copies of the Software, 55 * and to permit persons to whom the Software is furnished to do so, 56 * subject to the following conditions: 57 * 58 * The above copyright notice and this permission notice (including the 59 * next paragraph) shall be included in all copies or substantial 60 * portions of the Software. 61 * 62 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 63 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 64 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 65 * NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR 66 * THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 67 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 68 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 69 * DEALINGS IN THE SOFTWARE. 70 */ 71 72 #include <sys/cdefs.h> 73 __KERNEL_RCSID(0, "$NetBSD: radeonfb.c,v 1.112.2.1 2021/04/03 22:28:49 thorpej Exp $"); 74 75 #include <sys/param.h> 76 #include <sys/systm.h> 77 #include <sys/device.h> 78 #include <sys/malloc.h> 79 #include <sys/bus.h> 80 #include <sys/kernel.h> 81 #include <sys/lwp.h> 82 #include <sys/kauth.h> 83 #include <sys/kmem.h> 84 85 #include <dev/wscons/wsdisplayvar.h> 86 #include <dev/wscons/wsconsio.h> 87 #include <dev/wsfont/wsfont.h> 88 #include <dev/rasops/rasops.h> 89 #include <dev/videomode/videomode.h> 90 #include <dev/videomode/edidvar.h> 91 #include <dev/wscons/wsdisplay_vconsvar.h> 92 #include <dev/pci/wsdisplay_pci.h> 93 #include <dev/wscons/wsdisplay_glyphcachevar.h> 94 95 #include <dev/pci/pcidevs.h> 96 #include <dev/pci/pcireg.h> 97 #include <dev/pci/pcivar.h> 98 #include <dev/pci/pciio.h> 99 #include <dev/pci/radeonfbreg.h> 100 #include <dev/pci/radeonfbvar.h> 101 #include "opt_radeonfb.h" 102 #include "opt_vcons.h" 103 104 #ifdef RADEONFB_DEPTH_32 105 #define RADEONFB_DEFAULT_DEPTH 32 106 #else 107 #define RADEONFB_DEFAULT_DEPTH 8 108 #endif 109 110 static int radeonfb_match(device_t, cfdata_t, void *); 111 static void radeonfb_attach(device_t, device_t, void *); 112 static int radeonfb_ioctl(void *, void *, unsigned long, void *, int, 113 struct lwp *); 114 static paddr_t radeonfb_mmap(void *, void *, off_t, int); 115 static int radeonfb_scratch_test(struct radeonfb_softc *, int, uint32_t); 116 static void radeonfb_loadbios(struct radeonfb_softc *, 117 const struct pci_attach_args *); 118 119 static uintmax_t radeonfb_getprop_num(struct radeonfb_softc *, const char *, 120 uintmax_t); 121 static int radeonfb_getclocks(struct radeonfb_softc *); 122 static int radeonfb_gettmds(struct radeonfb_softc *); 123 static int radeonfb_calc_dividers(struct radeonfb_softc *, uint32_t, 124 uint32_t *, uint32_t *, int); 125 /* flags for radeonfb_calc_dividers */ 126 #define NO_ODD_FBDIV 1 127 128 static int radeonfb_getconnectors(struct radeonfb_softc *); 129 static const struct videomode *radeonfb_modelookup(const char *); 130 static void radeonfb_init_screen(void *, struct vcons_screen *, int, long *); 131 static void radeonfb_pllwriteupdate(struct radeonfb_softc *, int); 132 static void radeonfb_pllwaitatomicread(struct radeonfb_softc *, int); 133 static void radeonfb_program_vclk(struct radeonfb_softc *, int, int, int); 134 static void radeonfb_modeswitch(struct radeonfb_display *); 135 static void radeonfb_setcrtc(struct radeonfb_display *, int); 136 static void radeonfb_init_misc(struct radeonfb_softc *); 137 static void radeonfb_set_fbloc(struct radeonfb_softc *); 138 static void radeonfb_init_palette(struct radeonfb_display *); 139 static void radeonfb_r300cg_workaround(struct radeonfb_softc *); 140 141 static int radeonfb_isblank(struct radeonfb_display *); 142 static void radeonfb_blank(struct radeonfb_display *, int); 143 static int radeonfb_set_cursor(struct radeonfb_display *, 144 struct wsdisplay_cursor *); 145 static int radeonfb_set_curpos(struct radeonfb_display *, 146 struct wsdisplay_curpos *); 147 static void radeonfb_putpal(struct radeonfb_display *, int, int, int, int); 148 static int radeonfb_putcmap(struct radeonfb_display *, struct wsdisplay_cmap *); 149 static int radeonfb_getcmap(struct radeonfb_display *, struct wsdisplay_cmap *); 150 151 /* acceleration support */ 152 static void radeonfb_rectfill(struct radeonfb_display *, int dstx, int dsty, 153 int width, int height, uint32_t color); 154 static void radeonfb_rectfill_a(void *, int, int, int, int, long); 155 static void radeonfb_bitblt(void *, int srcx, int srcy, 156 int dstx, int dsty, int width, int height, int rop); 157 158 /* hw cursor support */ 159 static void radeonfb_cursor_cmap(struct radeonfb_display *); 160 static void radeonfb_cursor_shape(struct radeonfb_display *); 161 static void radeonfb_cursor_position(struct radeonfb_display *); 162 static void radeonfb_cursor_visible(struct radeonfb_display *); 163 static void radeonfb_cursor_update(struct radeonfb_display *, unsigned); 164 165 static inline void radeonfb_wait_fifo(struct radeonfb_softc *, int); 166 static void radeonfb_engine_idle(struct radeonfb_softc *); 167 static void radeonfb_engine_flush(struct radeonfb_softc *); 168 static void radeonfb_engine_reset(struct radeonfb_softc *); 169 static void radeonfb_engine_init(struct radeonfb_display *); 170 static inline void radeonfb_unclip(struct radeonfb_softc *) __unused; 171 172 static void radeonfb_eraserows(void *, int, int, long); 173 static void radeonfb_erasecols(void *, int, int, int, long); 174 static void radeonfb_copyrows(void *, int, int, int); 175 static void radeonfb_copycols(void *, int, int, int, int); 176 static void radeonfb_cursor(void *, int, int, int); 177 static void radeonfb_putchar(void *, int, int, unsigned, long); 178 static void radeonfb_putchar_aa32(void *, int, int, unsigned, long); 179 static void radeonfb_putchar_aa8(void *, int, int, unsigned, long); 180 #ifndef RADEONFB_ALWAYS_ACCEL_PUTCHAR 181 static void radeonfb_putchar_wrapper(void *, int, int, unsigned, long); 182 #endif 183 184 static int radeonfb_set_backlight(struct radeonfb_display *, int); 185 static int radeonfb_get_backlight(struct radeonfb_display *); 186 static void radeonfb_switch_backlight(struct radeonfb_display *, int); 187 static void radeonfb_lvds_callout(void *); 188 189 static void radeonfb_brightness_up(device_t); 190 static void radeonfb_brightness_down(device_t); 191 192 static struct videomode *radeonfb_best_refresh(struct videomode *, 193 struct videomode *); 194 static void radeonfb_pickres(struct radeonfb_display *, uint16_t *, 195 uint16_t *, int); 196 static const struct videomode *radeonfb_port_mode(struct radeonfb_softc *, 197 struct radeonfb_port *, int, int); 198 199 static int radeonfb_drm_print(void *, const char *); 200 201 #ifdef RADEONFB_DEBUG 202 int radeon_debug = 1; 203 #define DPRINTF(x) \ 204 if (radeon_debug) printf x 205 #define PRINTREG(r) DPRINTF((#r " = %08x\n", GET32(sc, r))) 206 #define PRINTPLL(r) DPRINTF((#r " = %08x\n", GETPLL(sc, r))) 207 #else 208 #define DPRINTF(x) 209 #define PRINTREG(r) 210 #define PRINTPLL(r) 211 #endif 212 213 #define ROUNDUP(x,y) (((x) + ((y) - 1)) & ~((y) - 1)) 214 215 #ifndef RADEON_DEFAULT_MODE 216 /* any reasonably modern display should handle this */ 217 #define RADEON_DEFAULT_MODE "1024x768x60" 218 #endif 219 220 extern const u_char rasops_cmap[768]; 221 222 const char *radeonfb_default_mode = RADEON_DEFAULT_MODE; 223 224 static struct { 225 int size; /* minimum memory size (MB) */ 226 int maxx; /* maximum x dimension */ 227 int maxy; /* maximum y dimension */ 228 int maxbpp; /* maximum bpp */ 229 int maxdisp; /* maximum logical display count */ 230 } radeonfb_limits[] = { 231 { 32, 2048, 1536, 32, 2 }, 232 { 16, 1600, 1200, 32, 2 }, 233 { 8, 1600, 1200, 32, 1 }, 234 { 0, 0, 0, 0, 0 }, 235 }; 236 237 static struct wsscreen_descr radeonfb_stdscreen = { 238 "fb", /* name */ 239 0, 0, /* ncols, nrows */ 240 NULL, /* textops */ 241 8, 16, /* fontwidth, fontheight */ 242 WSSCREEN_WSCOLORS | WSSCREEN_UNDERLINE | WSSCREEN_RESIZE, /* capabilities */ 243 0, /* modecookie */ 244 }; 245 246 struct wsdisplay_accessops radeonfb_accessops = { 247 radeonfb_ioctl, 248 radeonfb_mmap, 249 NULL, /* vcons_alloc_screen */ 250 NULL, /* vcons_free_screen */ 251 NULL, /* vcons_show_screen */ 252 NULL, /* load_font */ 253 NULL, /* pollc */ 254 NULL, /* scroll */ 255 }; 256 257 static struct { 258 uint16_t devid; 259 uint16_t family; 260 uint16_t flags; 261 } radeonfb_devices[] = 262 { 263 /* R100 family */ 264 { PCI_PRODUCT_ATI_RADEON_R100_QD, RADEON_R100, 0 }, 265 { PCI_PRODUCT_ATI_RADEON_R100_QE, RADEON_R100, 0 }, 266 { PCI_PRODUCT_ATI_RADEON_R100_QF, RADEON_R100, 0 }, 267 { PCI_PRODUCT_ATI_RADEON_R100_QG, RADEON_R100, 0 }, 268 269 /* RV100 family */ 270 { PCI_PRODUCT_ATI_RADEON_RV100_LY, RADEON_RV100, RFB_MOB }, 271 { PCI_PRODUCT_ATI_RADEON_RV100_LZ, RADEON_RV100, RFB_MOB }, 272 { PCI_PRODUCT_ATI_RADEON_RV100_QY, RADEON_RV100, 0 }, 273 { PCI_PRODUCT_ATI_RADEON_RV100_QZ, RADEON_RV100, 0 }, 274 275 /* RS100 family */ 276 { PCI_PRODUCT_ATI_RADEON_RS100_4136, RADEON_RS100, 0 }, 277 { PCI_PRODUCT_ATI_RADEON_RS100_4336, RADEON_RS100, RFB_MOB }, 278 279 /* RS200/RS250 family */ 280 { PCI_PRODUCT_ATI_RADEON_RS200_4337, RADEON_RS200, RFB_MOB }, 281 { PCI_PRODUCT_ATI_RADEON_RS200_A7, RADEON_RS200, 0 }, 282 { PCI_PRODUCT_ATI_RADEON_RS250_B7, RADEON_RS200, RFB_MOB }, 283 { PCI_PRODUCT_ATI_RADEON_RS250_D7, RADEON_RS200, 0 }, 284 285 /* R200 family */ 286 /* add more R200 products? , 5148 */ 287 { PCI_PRODUCT_ATI_RADEON_R200_BB, RADEON_R200, 0 }, 288 { PCI_PRODUCT_ATI_RADEON_R200_BC, RADEON_R200, 0 }, 289 { PCI_PRODUCT_ATI_RADEON_R200_QH, RADEON_R200, 0 }, 290 { PCI_PRODUCT_ATI_RADEON_R200_QL, RADEON_R200, 0 }, 291 { PCI_PRODUCT_ATI_RADEON_R200_QM, RADEON_R200, 0 }, 292 293 /* RV200 family */ 294 { PCI_PRODUCT_ATI_RADEON_RV200_LW, RADEON_RV200, RFB_MOB }, 295 { PCI_PRODUCT_ATI_RADEON_RV200_LX, RADEON_RV200, RFB_MOB }, 296 { PCI_PRODUCT_ATI_RADEON_RV200_QW, RADEON_RV200, 0 }, 297 { PCI_PRODUCT_ATI_RADEON_RV200_QX, RADEON_RV200, 0 }, 298 299 /* RV250 family */ 300 { PCI_PRODUCT_ATI_RADEON_RV250_4966, RADEON_RV250, 0 }, 301 { PCI_PRODUCT_ATI_RADEON_RV250_4967, RADEON_RV250, 0 }, 302 { PCI_PRODUCT_ATI_RADEON_RV250_4C64, RADEON_RV250, RFB_MOB }, 303 { PCI_PRODUCT_ATI_RADEON_RV250_4C66, RADEON_RV250, RFB_MOB }, 304 { PCI_PRODUCT_ATI_RADEON_RV250_4C67, RADEON_RV250, RFB_MOB }, 305 306 /* RS300 family */ 307 { PCI_PRODUCT_ATI_RADEON_RS300_X5, RADEON_RS300, 0 }, 308 { PCI_PRODUCT_ATI_RADEON_RS300_X4, RADEON_RS300, 0 }, 309 { PCI_PRODUCT_ATI_RADEON_RS300_7834, RADEON_RS300, 0 }, 310 { PCI_PRODUCT_ATI_RADEON_RS300_7835, RADEON_RS300, RFB_MOB }, 311 312 /* RV280 family */ 313 { PCI_PRODUCT_ATI_RADEON_RV280_5960, RADEON_RV280, 0 }, 314 { PCI_PRODUCT_ATI_RADEON_RV280_5961, RADEON_RV280, 0 }, 315 { PCI_PRODUCT_ATI_RADEON_RV280_5962, RADEON_RV280, 0 }, 316 { PCI_PRODUCT_ATI_RADEON_RV280_5963, RADEON_RV280, 0 }, 317 { PCI_PRODUCT_ATI_RADEON_RV280_5964, RADEON_RV280, 0 }, 318 { PCI_PRODUCT_ATI_RADEON_RV280_5C61, RADEON_RV280, RFB_MOB }, 319 { PCI_PRODUCT_ATI_RADEON_RV280_5C63, RADEON_RV280, RFB_MOB }, 320 321 /* R300 family */ 322 { PCI_PRODUCT_ATI_RADEON_R300_AD, RADEON_R300, 0 }, 323 { PCI_PRODUCT_ATI_RADEON_R300_AE, RADEON_R300, 0 }, 324 { PCI_PRODUCT_ATI_RADEON_R300_AF, RADEON_R300, 0 }, 325 { PCI_PRODUCT_ATI_RADEON_R300_AG, RADEON_R300, 0 }, 326 { PCI_PRODUCT_ATI_RADEON_R300_ND, RADEON_R300, 0 }, 327 { PCI_PRODUCT_ATI_RADEON_R300_NE, RADEON_R300, 0 }, 328 { PCI_PRODUCT_ATI_RADEON_R300_NF, RADEON_R300, 0 }, 329 { PCI_PRODUCT_ATI_RADEON_R300_NG, RADEON_R300, 0 }, 330 331 /* RV350/RV360 family */ 332 { PCI_PRODUCT_ATI_RADEON_RV350_AP, RADEON_RV350, 0 }, 333 { PCI_PRODUCT_ATI_RADEON_RV350_AQ, RADEON_RV350, 0 }, 334 { PCI_PRODUCT_ATI_RADEON_RV360_AR, RADEON_RV350, 0 }, 335 { PCI_PRODUCT_ATI_RADEON_RV350_AS, RADEON_RV350, 0 }, 336 { PCI_PRODUCT_ATI_RADEON_RV350_AT, RADEON_RV350, 0 }, 337 { PCI_PRODUCT_ATI_RADEON_RV350_AV, RADEON_RV350, 0 }, 338 { PCI_PRODUCT_ATI_RADEON_RV350_NP, RADEON_RV350, RFB_MOB }, 339 { PCI_PRODUCT_ATI_RADEON_RV350_NQ, RADEON_RV350, RFB_MOB }, 340 { PCI_PRODUCT_ATI_RADEON_RV350_NR, RADEON_RV350, RFB_MOB }, 341 { PCI_PRODUCT_ATI_RADEON_RV350_NS, RADEON_RV350, RFB_MOB }, 342 { PCI_PRODUCT_ATI_RADEON_RV350_NT, RADEON_RV350, RFB_MOB }, 343 { PCI_PRODUCT_ATI_RADEON_RV350_NV, RADEON_RV350, RFB_MOB }, 344 345 /* R350/R360 family */ 346 { PCI_PRODUCT_ATI_RADEON_R350_AH, RADEON_R350, 0 }, 347 { PCI_PRODUCT_ATI_RADEON_R350_AI, RADEON_R350, 0 }, 348 { PCI_PRODUCT_ATI_RADEON_R350_AJ, RADEON_R350, 0 }, 349 { PCI_PRODUCT_ATI_RADEON_R350_AK, RADEON_R350, 0 }, 350 { PCI_PRODUCT_ATI_RADEON_R350_NH, RADEON_R350, 0 }, 351 { PCI_PRODUCT_ATI_RADEON_R350_NI, RADEON_R350, 0 }, 352 { PCI_PRODUCT_ATI_RADEON_R350_NK, RADEON_R350, 0 }, 353 { PCI_PRODUCT_ATI_RADEON_R360_NJ, RADEON_R350, 0 }, 354 355 /* RV380/RV370 family */ 356 { PCI_PRODUCT_ATI_RADEON_RV380_3150, RADEON_RV380, RFB_MOB }, 357 { PCI_PRODUCT_ATI_RADEON_RV380_3154, RADEON_RV380, RFB_MOB }, 358 { PCI_PRODUCT_ATI_RADEON_RV380_3E50, RADEON_RV380, 0 }, 359 { PCI_PRODUCT_ATI_RADEON_RV380_3E54, RADEON_RV380, 0 }, 360 { PCI_PRODUCT_ATI_RADEON_RV370_5460, RADEON_RV380, RFB_MOB }, 361 { PCI_PRODUCT_ATI_RADEON_RV370_5464, RADEON_RV380, RFB_MOB }, 362 { PCI_PRODUCT_ATI_RADEON_RV370_5B60, RADEON_RV380, 0 }, 363 { PCI_PRODUCT_ATI_RADEON_RV370_5B63, RADEON_RV380, 0 }, 364 { PCI_PRODUCT_ATI_RADEON_RV370_5B64, RADEON_RV380, 0 }, 365 { PCI_PRODUCT_ATI_RADEON_RV370_5B65, RADEON_RV380, 0 }, 366 367 #if notyet 368 /* R420/R423 family */ 369 { PCI_PRODUCT_ATI_RADEON_R420_JH, RADEON_R420, 0 }, 370 { PCI_PRODUCT_ATI_RADEON_R420_JI, RADEON_R420, 0 }, 371 { PCI_PRODUCT_ATI_RADEON_R420_JJ, RADEON_R420, 0 }, 372 { PCI_PRODUCT_ATI_RADEON_R420_JK, RADEON_R420, 0 }, 373 { PCI_PRODUCT_ATI_RADEON_R420_JL, RADEON_R420, 0 }, 374 { PCI_PRODUCT_ATI_RADEON_R420_JM, RADEON_R420, 0 }, 375 { PCI_PRODUCT_ATI_RADEON_R420_JN, RADEON_R420, RFB_MOB }, 376 { PCI_PRODUCT_ATI_RADEON_R420_JP, RADEON_R420, 0 }, 377 { PCI_PRODUCT_ATI_RADEON_R423_UH, RADEON_R420, 0 }, 378 { PCI_PRODUCT_ATI_RADEON_R423_UI, RADEON_R420, 0 }, 379 { PCI_PRODUCT_ATI_RADEON_R423_UJ, RADEON_R420, 0 }, 380 { PCI_PRODUCT_ATI_RADEON_R423_UK, RADEON_R420, 0 }, 381 { PCI_PRODUCT_ATI_RADEON_R423_UQ, RADEON_R420, 0 }, 382 { PCI_PRODUCT_ATI_RADEON_R423_UR, RADEON_R420, 0 }, 383 { PCI_PRODUCT_ATI_RADEON_R423_UT, RADEON_R420, 0 }, 384 { PCI_PRODUCT_ATI_RADEON_R423_5D57, RADEON_R420, 0 }, 385 { PCI_PRODUCT_ATI_RADEON_R430_554F, RADEON_R420, 0 }, 386 #endif 387 388 /* R5xx family */ 389 { 0x7240, RADEON_R580, RFB_IS_AVIVO }, 390 { 0, 0, 0 } 391 }; 392 393 static struct { 394 int divider; 395 int mask; 396 } radeonfb_dividers[] = { 397 { 16, 5 }, 398 { 12, 7 }, 399 { 8, 3 }, 400 { 6, 6 }, 401 { 4, 2 }, 402 { 3, 4 }, 403 { 2, 1 }, 404 { 1, 0 }, 405 { 0, 0 } 406 }; 407 408 /* 409 * This table taken from X11. 410 */ 411 static const struct { 412 int family; 413 struct radeon_tmds_pll plls[4]; 414 } radeonfb_tmds_pll[] = { 415 { RADEON_R100, {{12000, 0xa1b}, {-1, 0xa3f}}}, 416 { RADEON_RV100, {{12000, 0xa1b}, {-1, 0xa3f}}}, 417 { RADEON_RS100, {{0, 0}}}, 418 { RADEON_RV200, {{15000, 0xa1b}, {-1, 0xa3f}}}, 419 { RADEON_RS200, {{15000, 0xa1b}, {-1, 0xa3f}}}, 420 { RADEON_R200, {{15000, 0xa1b}, {-1, 0xa3f}}}, 421 { RADEON_RV250, {{15500, 0x81b}, {-1, 0x83f}}}, 422 { RADEON_RS300, {{0, 0}}}, 423 { RADEON_RV280, {{13000, 0x400f4}, {15000, 0x400f7}, {-1, 0x40111}}}, 424 { RADEON_R300, {{-1, 0xb01cb}}}, 425 { RADEON_R350, {{-1, 0xb01cb}}}, 426 { RADEON_RV350, {{15000, 0xb0155}, {-1, 0xb01cb}}}, 427 { RADEON_RV380, {{15000, 0xb0155}, {-1, 0xb01cb}}}, 428 { RADEON_R420, {{-1, 0xb01cb}}}, 429 { RADEON_R580, {{-1, 0xb01cb}}}, /* XXX likely bogus */ 430 }; 431 432 #define RADEONFB_BACKLIGHT_MAX 255 /* Maximum backlight level. */ 433 434 435 CFATTACH_DECL_NEW(radeonfb, sizeof (struct radeonfb_softc), 436 radeonfb_match, radeonfb_attach, NULL, NULL); 437 438 static int 439 radeonfb_match(device_t parent, cfdata_t match, void *aux) 440 { 441 const struct pci_attach_args *pa = aux; 442 int i; 443 444 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_ATI) 445 return 0; 446 447 for (i = 0; radeonfb_devices[i].devid; i++) { 448 if (PCI_PRODUCT(pa->pa_id) == radeonfb_devices[i].devid) 449 return 100; /* high to defeat VGA/VESA */ 450 } 451 452 return 0; 453 } 454 455 static void 456 radeonfb_attach(device_t parent, device_t dev, void *aux) 457 { 458 struct radeonfb_softc *sc = device_private(dev); 459 const struct pci_attach_args *pa = aux; 460 const char *mptr; 461 bus_size_t bsz; 462 pcireg_t screg; 463 int i, j, fg, bg, ul, flags; 464 uint32_t v; 465 466 sc->sc_dev = dev; 467 sc->sc_id = pa->pa_id; 468 for (i = 0; radeonfb_devices[i].devid; i++) { 469 if (PCI_PRODUCT(sc->sc_id) == radeonfb_devices[i].devid) 470 break; 471 } 472 473 pci_aprint_devinfo(pa, NULL); 474 475 DPRINTF(("%s", prop_dictionary_externalize(device_properties(dev)))); 476 477 KASSERT(radeonfb_devices[i].devid != 0); 478 sc->sc_pt = pa->pa_tag; 479 sc->sc_iot = pa->pa_iot; 480 sc->sc_pc = pa->pa_pc; 481 sc->sc_family = radeonfb_devices[i].family; 482 sc->sc_flags = radeonfb_devices[i].flags; 483 sc->sc_bios = NULL; 484 sc->sc_biossz = 0; 485 486 /* enable memory and IO access */ 487 screg = pci_conf_read(sc->sc_pc, sc->sc_pt, PCI_COMMAND_STATUS_REG); 488 screg |= PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE; 489 pci_conf_write(sc->sc_pc, sc->sc_pt, PCI_COMMAND_STATUS_REG, screg); 490 491 /* 492 * Some flags are general to entire chip families, and rather 493 * than clutter up the table with them, we go ahead and set 494 * them here. 495 */ 496 switch (sc->sc_family) { 497 case RADEON_RS100: 498 case RADEON_RS200: 499 sc->sc_flags |= RFB_IGP | RFB_RV100; 500 break; 501 502 case RADEON_RV100: 503 case RADEON_RV200: 504 case RADEON_RV250: 505 case RADEON_RV280: 506 sc->sc_flags |= RFB_RV100; 507 break; 508 509 case RADEON_RS300: 510 sc->sc_flags |= RFB_SDAC | RFB_IGP | RFB_RV100; 511 break; 512 513 case RADEON_R300: 514 case RADEON_RV350: 515 case RADEON_R350: 516 case RADEON_RV380: 517 case RADEON_R420: 518 case RADEON_R580: 519 /* newer chips */ 520 sc->sc_flags |= RFB_R300; 521 break; 522 523 case RADEON_R100: 524 sc->sc_flags |= RFB_NCRTC2; 525 break; 526 } 527 528 if ((sc->sc_family == RADEON_RV200) || 529 (sc->sc_family == RADEON_RV250) || 530 (sc->sc_family == RADEON_RV280) || 531 (sc->sc_family == RADEON_RV350)) { 532 bool inverted = 0; 533 /* backlight level is linear */ 534 DPRINTF(("found RV* chip, backlight is supposedly linear\n")); 535 prop_dictionary_get_bool(device_properties(sc->sc_dev), 536 "backlight_level_reverted", &inverted); 537 if (inverted) { 538 DPRINTF(("nope, it's inverted\n")); 539 sc->sc_flags |= RFB_INV_BLIGHT; 540 } 541 } else 542 sc->sc_flags |= RFB_INV_BLIGHT; 543 544 /* 545 * XXX: to support true multihead, this must change. 546 */ 547 sc->sc_ndisplays = 1; 548 549 /* XXX: */ 550 if (!HAS_CRTC2(sc)) { 551 sc->sc_ndisplays = 1; 552 } 553 554 if (pci_mapreg_map(pa, RADEON_MAPREG_MMIO, PCI_MAPREG_TYPE_MEM, 0, 555 &sc->sc_regt, &sc->sc_regh, &sc->sc_regaddr, 556 &sc->sc_regsz) != 0) { 557 aprint_error("%s: unable to map registers!\n", XNAME(sc)); 558 goto error; 559 } 560 561 if (pci_mapreg_info(sc->sc_pc, sc->sc_pt, PCI_MAPREG_ROM, 562 PCI_MAPREG_TYPE_ROM, &sc->sc_romaddr, &sc->sc_romsz, &flags) != 0) 563 { 564 aprint_error("%s: unable to find ROM!\n", XNAME(sc)); 565 goto error; 566 } 567 sc->sc_romt = sc->sc_memt; 568 569 sc->sc_mapped = TRUE; 570 571 /* scratch register test... */ 572 if (radeonfb_scratch_test(sc, RADEON_BIOS_0_SCRATCH, 0x55555555) || 573 radeonfb_scratch_test(sc, RADEON_BIOS_0_SCRATCH, 0xaaaaaaaa)) { 574 aprint_error("%s: scratch register test failed!\n", XNAME(sc)); 575 goto error; 576 } 577 578 PRINTREG(RADEON_CRTC_EXT_CNTL); 579 PRINTREG(RADEON_CRTC_GEN_CNTL); 580 PRINTREG(RADEON_CRTC2_GEN_CNTL); 581 PRINTREG(RADEON_DISP_OUTPUT_CNTL); 582 PRINTREG(RADEON_DAC_CNTL2); 583 PRINTREG(RADEON_BIOS_4_SCRATCH); 584 PRINTREG(RADEON_FP_GEN_CNTL); 585 sc->sc_fp_gen_cntl = GET32(sc, RADEON_FP_GEN_CNTL); 586 PRINTREG(RADEON_FP2_GEN_CNTL); 587 PRINTREG(RADEON_TMDS_CNTL); 588 PRINTREG(RADEON_TMDS_TRANSMITTER_CNTL); 589 PRINTREG(RADEON_TMDS_PLL_CNTL); 590 PRINTREG(RADEON_LVDS_GEN_CNTL); 591 PRINTREG(RADEON_DISP_HW_DEBUG); 592 if (!IS_AVIVO(sc)) { 593 /* 594 XXX: We can't print this, as it's not correctly aligned 595 PRINTREG(RADEON_PIXCLKS_CNTL); 596 */ 597 PRINTREG(RADEON_CRTC_H_SYNC_STRT_WID); 598 PRINTREG(RADEON_FP_H_SYNC_STRT_WID); 599 PRINTREG(RADEON_CRTC2_H_SYNC_STRT_WID); 600 PRINTREG(RADEON_FP_H2_SYNC_STRT_WID); 601 } 602 /* 603 * XXX 604 * This was if (IS_RV100()), which is set for all pre-R3xx chips. 605 * I suspect this only makes sense on Sun XVR-100 with firmware that doesn't 606 * support DVI, so for now let's restrict it to only actual RV100 607 */ 608 if (sc->sc_family == RADEON_RV100) 609 PUT32(sc, RADEON_TMDS_PLL_CNTL, 0xa27); 610 611 /* XXX 612 * according to xf86-video-radeon R3xx has this bit backwards 613 */ 614 if (IS_R300(sc)) { 615 PATCH32(sc, RADEON_TMDS_TRANSMITTER_CNTL, 616 0, 617 ~(RADEON_TMDS_TRANSMITTER_PLLEN | RADEON_TMDS_TRANSMITTER_PLLRST)); 618 } else { 619 PATCH32(sc, RADEON_TMDS_TRANSMITTER_CNTL, 620 RADEON_TMDS_TRANSMITTER_PLLEN, 621 ~(RADEON_TMDS_TRANSMITTER_PLLEN | RADEON_TMDS_TRANSMITTER_PLLRST)); 622 } 623 624 radeonfb_i2c_init(sc); 625 626 radeonfb_loadbios(sc, pa); 627 628 #ifdef RADEONFB_BIOS_INIT 629 if (radeonfb_bios_init(sc)) { 630 aprint_error("%s: BIOS inititialization failed\n", XNAME(sc)); 631 } 632 #endif 633 634 if (radeonfb_getclocks(sc)) { 635 aprint_error("%s: Unable to get reference clocks from BIOS\n", 636 XNAME(sc)); 637 goto error; 638 } 639 640 if (radeonfb_gettmds(sc)) { 641 aprint_error("%s: Unable to identify TMDS PLL settings\n", 642 XNAME(sc)); 643 goto error; 644 } 645 646 aprint_verbose("%s: refclk = %d.%03d MHz, refdiv = %d " 647 "minpll = %d, maxpll = %d\n", XNAME(sc), 648 (int)sc->sc_refclk / 1000, (int)sc->sc_refclk % 1000, 649 (int)sc->sc_refdiv, (int)sc->sc_minpll, (int)sc->sc_maxpll); 650 651 radeonfb_getconnectors(sc); 652 653 radeonfb_set_fbloc(sc); 654 655 /* 64 MB should be enough -- more just wastes map entries */ 656 if (sc->sc_memsz > (64 << 20)) 657 sc->sc_memsz = (64 << 20); 658 659 for (i = 0; radeonfb_limits[i].size; i++) { 660 if (sc->sc_memsz >= radeonfb_limits[i].size) { 661 sc->sc_maxx = radeonfb_limits[i].maxx; 662 sc->sc_maxy = radeonfb_limits[i].maxy; 663 sc->sc_maxbpp = radeonfb_limits[i].maxbpp; 664 /* framebuffer offset, start at a 4K page */ 665 sc->sc_fboffset = sc->sc_memsz / 666 radeonfb_limits[i].maxdisp; 667 /* 668 * we use the fbsize to figure out where we can store 669 * things like cursor data. 670 */ 671 sc->sc_fbsize = 672 ROUNDUP(ROUNDUP(sc->sc_maxx * sc->sc_maxbpp / 8 , 673 RADEON_STRIDEALIGN) * sc->sc_maxy, 674 4096); 675 break; 676 } 677 } 678 679 680 radeonfb_init_misc(sc); 681 682 /* program the DAC wirings */ 683 for (i = 0; i < (HAS_CRTC2(sc) ? 2 : 1); i++) { 684 switch (sc->sc_ports[i].rp_dac_type) { 685 case RADEON_DAC_PRIMARY: 686 PATCH32(sc, RADEON_DAC_CNTL2, 687 i ? RADEON_DAC2_DAC_CLK_SEL : 0, 688 ~RADEON_DAC2_DAC_CLK_SEL); 689 break; 690 case RADEON_DAC_TVDAC: 691 /* we always use the TVDAC to drive a secondary analog 692 * CRT for now. if we ever support TV-out this will 693 * have to change. 694 */ 695 SET32(sc, RADEON_DAC_CNTL2, 696 RADEON_DAC2_DAC2_CLK_SEL); 697 PATCH32(sc, RADEON_DISP_HW_DEBUG, 698 i ? 0 : RADEON_CRT2_DISP1_SEL, 699 ~RADEON_CRT2_DISP1_SEL); 700 /* we're using CRTC2 for the 2nd port */ 701 if (sc->sc_ports[i].rp_number == 1) { 702 PATCH32(sc, RADEON_DISP_OUTPUT_CNTL, 703 RADEON_DISP_DAC2_SOURCE_CRTC2, 704 ~RADEON_DISP_DAC2_SOURCE_MASK); 705 } 706 707 break; 708 } 709 DPRINTF(("%s: port %d tmds type %d\n", __func__, i, 710 sc->sc_ports[i].rp_tmds_type)); 711 switch (sc->sc_ports[i].rp_tmds_type) { 712 case RADEON_TMDS_INT: 713 /* point FP0 at the CRTC this port uses */ 714 DPRINTF(("%s: plugging internal TMDS into CRTC %d\n", 715 __func__, sc->sc_ports[i].rp_number)); 716 if (IS_R300(sc)) { 717 PATCH32(sc, RADEON_FP_GEN_CNTL, 718 sc->sc_ports[i].rp_number ? 719 R200_FP_SOURCE_SEL_CRTC2 : 720 R200_FP_SOURCE_SEL_CRTC1, 721 ~R200_FP_SOURCE_SEL_MASK); 722 } else { 723 PATCH32(sc, RADEON_FP_GEN_CNTL, 724 sc->sc_ports[i].rp_number ? 725 RADEON_FP_SEL_CRTC2 : 726 RADEON_FP_SEL_CRTC1, 727 ~RADEON_FP_SEL_MASK); 728 } 729 break; 730 case RADEON_TMDS_EXT: 731 /* point FP2 at the CRTC this port uses */ 732 DPRINTF(("%s: plugging external TMDS into CRTC %d\n", 733 __func__, sc->sc_ports[i].rp_number)); 734 if (IS_R300(sc)) { 735 PATCH32(sc, RADEON_FP2_GEN_CNTL, 736 sc->sc_ports[i].rp_number ? 737 R200_FP2_SOURCE_SEL_CRTC2 : 738 R200_FP2_SOURCE_SEL_CRTC1, 739 ~R200_FP2_SOURCE_SEL_CRTC2); 740 } else { 741 PATCH32(sc, RADEON_FP2_GEN_CNTL, 742 sc->sc_ports[i].rp_number ? 743 RADEON_FP2_SRC_SEL_CRTC2 : 744 RADEON_FP2_SRC_SEL_CRTC1, 745 ~RADEON_FP2_SRC_SEL_CRTC2); 746 } 747 break; 748 } 749 } 750 PRINTREG(RADEON_DAC_CNTL2); 751 PRINTREG(RADEON_DISP_HW_DEBUG); 752 753 PRINTREG(RADEON_DAC_CNTL); 754 /* other DAC programming */ 755 v = GET32(sc, RADEON_DAC_CNTL); 756 v &= (RADEON_DAC_RANGE_CNTL_MASK | RADEON_DAC_BLANKING); 757 v |= RADEON_DAC_MASK_ALL | RADEON_DAC_8BIT_EN; 758 PUT32(sc, RADEON_DAC_CNTL, v); 759 PRINTREG(RADEON_DAC_CNTL); 760 761 /* XXX: this may need more investigation */ 762 PUT32(sc, RADEON_TV_DAC_CNTL, 0x00280203); 763 PRINTREG(RADEON_TV_DAC_CNTL); 764 765 /* enable TMDS */ 766 SET32(sc, RADEON_FP_GEN_CNTL, 767 RADEON_FP_TMDS_EN | 768 RADEON_FP_CRTC_DONT_SHADOW_VPAR | 769 RADEON_FP_CRTC_DONT_SHADOW_HEND); 770 /* 771 * XXX 772 * no idea why this is necessary - if I do not clear this bit on my 773 * iBook G4 the screen remains black, even though it's already clear. 774 * It needs to be set on my Sun XVR-100 for the DVI port to work 775 * TODO: 776 * see if this is still necessary now that CRTCs, DACs and outputs are 777 * getting wired up in a halfway sane way 778 */ 779 if (sc->sc_fp_gen_cntl & RADEON_FP_SEL_CRTC2) { 780 SET32(sc, RADEON_FP_GEN_CNTL, RADEON_FP_SEL_CRTC2); 781 } else { 782 CLR32(sc, RADEON_FP_GEN_CNTL, RADEON_FP_SEL_CRTC2); 783 } 784 785 /* 786 * we use bus_space_map instead of pci_mapreg, because we don't 787 * need the full aperature space. no point in wasting virtual 788 * address space we don't intend to use, right? 789 */ 790 if ((sc->sc_memsz < (4096 * 1024)) || 791 (pci_mapreg_info(sc->sc_pc, sc->sc_pt, RADEON_MAPREG_VRAM, 792 PCI_MAPREG_TYPE_MEM, &sc->sc_memaddr, &bsz, NULL) != 0) || 793 (bsz < sc->sc_memsz)) { 794 sc->sc_memsz = 0; 795 aprint_error("%s: Bad frame buffer configuration\n", 796 XNAME(sc)); 797 goto error; 798 } 799 800 sc->sc_memt = pa->pa_memt; 801 if (bus_space_map(sc->sc_memt, sc->sc_memaddr, sc->sc_memsz, 802 BUS_SPACE_MAP_LINEAR, &sc->sc_memh) != 0) { 803 sc->sc_memsz = 0; 804 aprint_error("%s: Unable to map frame buffer\n", XNAME(sc)); 805 goto error; 806 } 807 808 aprint_normal("%s: %d MB aperture at 0x%08x, " 809 "%d KB registers at 0x%08x\n", XNAME(sc), 810 (int)sc->sc_memsz >> 20, (unsigned)sc->sc_memaddr, 811 (int)sc->sc_regsz >> 10, (unsigned)sc->sc_regaddr); 812 813 /* setup default video mode from devprop (allows PROM override) */ 814 sc->sc_defaultmode = radeonfb_default_mode; 815 if (prop_dictionary_get_cstring_nocopy(device_properties(sc->sc_dev), 816 "videomode", &mptr)) { 817 818 strncpy(sc->sc_modebuf, mptr, sizeof(sc->sc_modebuf)); 819 sc->sc_defaultmode = sc->sc_modebuf; 820 } 821 822 /* initialize some basic display parameters */ 823 for (i = 0; i < sc->sc_ndisplays; i++) { 824 struct radeonfb_display *dp = &sc->sc_displays[i]; 825 struct rasops_info *ri; 826 long defattr; 827 struct wsemuldisplaydev_attach_args aa; 828 829 /* 830 * Figure out how many "displays" (desktops) we are going to 831 * support. If more than one, then each CRTC gets its own 832 * programming. 833 * 834 * XXX: this code needs to change to support mergedfb. 835 * XXX: would be nice to allow this to be overridden 836 */ 837 if (HAS_CRTC2(sc) && (sc->sc_ndisplays == 1)) { 838 DPRINTF(("dual crtcs!\n")); 839 dp->rd_ncrtcs = 2; 840 dp->rd_crtcs[0].rc_port = 841 &sc->sc_ports[0]; 842 dp->rd_crtcs[0].rc_number = sc->sc_ports[0].rp_number; 843 dp->rd_crtcs[1].rc_port = 844 &sc->sc_ports[1]; 845 dp->rd_crtcs[1].rc_number = sc->sc_ports[1].rp_number; 846 } else { 847 dp->rd_ncrtcs = 1; 848 dp->rd_crtcs[0].rc_port = 849 &sc->sc_ports[i]; 850 dp->rd_crtcs[0].rc_number = sc->sc_ports[i].rp_number; 851 } 852 853 dp->rd_softc = sc; 854 dp->rd_wsmode = WSDISPLAYIO_MODE_EMUL; 855 dp->rd_bpp = RADEONFB_DEFAULT_DEPTH; /* XXX */ 856 857 /* for text mode, we pick a resolution that won't 858 * require panning */ 859 radeonfb_pickres(dp, &dp->rd_virtx, &dp->rd_virty, 0); 860 861 aprint_normal("%s: display %d: " 862 "initial virtual resolution %dx%d at %d bpp\n", 863 XNAME(sc), i, dp->rd_virtx, dp->rd_virty, dp->rd_bpp); 864 aprint_normal_dev(sc->sc_dev, "using %d MB per display\n", 865 sc->sc_fboffset >> 20); 866 /* now select the *video mode* that we will use */ 867 for (j = 0; j < dp->rd_ncrtcs; j++) { 868 const struct videomode *vmp; 869 vmp = radeonfb_port_mode(sc, dp->rd_crtcs[j].rc_port, 870 dp->rd_virtx, dp->rd_virty); 871 872 /* 873 * virtual resolution should be at least as high as 874 * physical 875 */ 876 if (dp->rd_virtx < vmp->hdisplay || 877 dp->rd_virty < vmp->vdisplay) { 878 dp->rd_virtx = vmp->hdisplay; 879 dp->rd_virty = vmp->vdisplay; 880 } 881 882 dp->rd_crtcs[j].rc_videomode = *vmp; 883 printf("%s: port %d: physical %dx%d %dHz\n", 884 XNAME(sc), j, vmp->hdisplay, vmp->vdisplay, 885 DIVIDE(DIVIDE(vmp->dot_clock * 1000, 886 vmp->htotal), vmp->vtotal)); 887 } 888 889 /* N.B.: radeon wants 64-byte aligned stride */ 890 dp->rd_stride = dp->rd_virtx * dp->rd_bpp / 8; 891 dp->rd_stride = ROUNDUP(dp->rd_stride, RADEON_STRIDEALIGN); 892 893 dp->rd_offset = sc->sc_fboffset * i; 894 dp->rd_fbptr = (vaddr_t)bus_space_vaddr(sc->sc_memt, 895 sc->sc_memh) + dp->rd_offset; 896 dp->rd_curoff = sc->sc_fboffset - 16384; /* 16KB cursor space */ 897 dp->rd_curptr = dp->rd_fbptr + dp->rd_curoff; 898 899 DPRINTF(("fpbtr = %p\n", (void *)dp->rd_fbptr)); 900 901 switch (dp->rd_bpp) { 902 case 8: 903 dp->rd_format = 2; 904 break; 905 case 32: 906 dp->rd_format = 6; 907 break; 908 default: 909 aprint_error("%s: bad depth %d\n", XNAME(sc), 910 dp->rd_bpp); 911 goto error; 912 } 913 DPRINTF(("init engine\n")); 914 /* XXX: this seems suspicious - per display engine 915 initialization? */ 916 917 radeonfb_modeswitch(dp); 918 radeonfb_engine_init(dp); 919 920 /* copy the template into place */ 921 dp->rd_wsscreens_storage[0] = radeonfb_stdscreen; 922 dp->rd_wsscreens = dp->rd_wsscreens_storage; 923 924 /* and make up the list */ 925 dp->rd_wsscreenlist.nscreens = 1; 926 dp->rd_wsscreenlist.screens = (void *)&dp->rd_wsscreens; 927 928 vcons_init(&dp->rd_vd, dp, dp->rd_wsscreens, 929 &radeonfb_accessops); 930 931 dp->rd_vd.init_screen = radeonfb_init_screen; 932 933 dp->rd_console = 0; 934 prop_dictionary_get_bool(device_properties(sc->sc_dev), 935 "is_console", &dp->rd_console); 936 937 dp->rd_vscreen.scr_flags |= VCONS_SCREEN_IS_STATIC; 938 939 940 vcons_init_screen(&dp->rd_vd, &dp->rd_vscreen, 941 dp->rd_console, &defattr); 942 943 ri = &dp->rd_vscreen.scr_ri; 944 945 /* clear the screen */ 946 rasops_unpack_attr(defattr, &fg, &bg, &ul); 947 dp->rd_bg = ri->ri_devcmap[bg & 0xf]; 948 radeonfb_rectfill(dp, 0, 0, ri->ri_width, ri->ri_height, 949 dp->rd_bg); 950 951 dp->rd_wsscreens->textops = &ri->ri_ops; 952 dp->rd_wsscreens->capabilities = ri->ri_caps; 953 dp->rd_wsscreens->nrows = ri->ri_rows; 954 dp->rd_wsscreens->ncols = ri->ri_cols; 955 956 #ifdef SPLASHSCREEN 957 dp->rd_splash.si_depth = ri->ri_depth; 958 dp->rd_splash.si_bits = ri->ri_bits; 959 dp->rd_splash.si_hwbits = ri->ri_hwbits; 960 dp->rd_splash.si_width = ri->ri_width; 961 dp->rd_splash.si_height = ri->ri_height; 962 dp->rd_splash.si_stride = ri->ri_stride; 963 dp->rd_splash.si_fillrect = NULL; 964 #endif 965 dp->rd_gc.gc_bitblt = radeonfb_bitblt; 966 dp->rd_gc.gc_rectfill = radeonfb_rectfill_a; 967 dp->rd_gc.gc_rop = RADEON_ROP3_S; 968 dp->rd_gc.gc_blitcookie = dp; 969 /* 970 * use memory between framebuffer and cursor area as glyph 971 * cache, cap at 4096 lines 972 */ 973 glyphcache_init(&dp->rd_gc, dp->rd_virty + 4, 974 uimin(4096, 975 (dp->rd_curoff / dp->rd_stride) - (dp->rd_virty + 4)), 976 dp->rd_virtx, 977 ri->ri_font->fontwidth, 978 ri->ri_font->fontheight, 979 defattr); 980 dp->rd_vd.show_screen_cookie = &dp->rd_gc; 981 dp->rd_vd.show_screen_cb = glyphcache_adapt; 982 983 if (dp->rd_console) { 984 985 wsdisplay_cnattach(dp->rd_wsscreens, ri, 0, 0, 986 defattr); 987 #ifdef SPLASHSCREEN 988 if (splash_render(&dp->rd_splash, 989 SPLASH_F_CENTER|SPLASH_F_FILL) == 0) 990 SCREEN_DISABLE_DRAWING(&dp->rd_vscreen); 991 else 992 #endif 993 vcons_replay_msgbuf(&dp->rd_vscreen); 994 } else { 995 996 /* 997 * since we're not the console we can postpone 998 * the rest until someone actually allocates a 999 * screen for us. but we do clear the screen 1000 * at least. 1001 */ 1002 memset(ri->ri_bits, 0, 1024); 1003 1004 #ifdef SPLASHSCREEN 1005 if (splash_render(&dp->rd_splash, 1006 SPLASH_F_CENTER|SPLASH_F_FILL) == 0) 1007 SCREEN_DISABLE_DRAWING(&dp->rd_vscreen); 1008 #endif 1009 } 1010 1011 aa.console = dp->rd_console; 1012 aa.scrdata = &dp->rd_wsscreenlist; 1013 aa.accessops = &radeonfb_accessops; 1014 aa.accesscookie = &dp->rd_vd; 1015 1016 config_found(sc->sc_dev, &aa, wsemuldisplaydevprint); 1017 1018 radeonfb_blank(dp, 0); 1019 1020 /* Initialise delayed lvds operations for backlight. */ 1021 callout_init(&dp->rd_bl_lvds_co, 0); 1022 callout_setfunc(&dp->rd_bl_lvds_co, 1023 radeonfb_lvds_callout, dp); 1024 1025 dp->rd_bl_on = 1; 1026 if (sc->sc_flags & RFB_MOB) { 1027 dp->rd_bl_level = radeonfb_get_backlight(dp); 1028 } else 1029 dp->rd_bl_level = 128; 1030 1031 radeonfb_set_backlight(dp, dp->rd_bl_level); 1032 } 1033 for (i = 0; i < RADEON_NDISPLAYS; i++) 1034 radeonfb_init_palette(&sc->sc_displays[i]); 1035 1036 if (HAS_CRTC2(sc) && !IS_AVIVO(sc)) { 1037 CLR32(sc, RADEON_CRTC2_GEN_CNTL, RADEON_CRTC2_DISP_DIS); 1038 } 1039 1040 if (!IS_AVIVO(sc)) { 1041 CLR32(sc, RADEON_CRTC_EXT_CNTL, RADEON_CRTC_DISPLAY_DIS); 1042 SET32(sc, RADEON_FP_GEN_CNTL, RADEON_FP_FPON); 1043 } 1044 1045 pmf_event_register(dev, PMFE_DISPLAY_BRIGHTNESS_UP, 1046 radeonfb_brightness_up, TRUE); 1047 pmf_event_register(dev, PMFE_DISPLAY_BRIGHTNESS_DOWN, 1048 radeonfb_brightness_down, TRUE); 1049 1050 /* 1051 * if we attach a DRM we need to unmap registers in 1052 * WSDISPLAYIO_MODE_MAPPED, since this keeps us from doing things like 1053 * screen blanking we only do it if needed 1054 */ 1055 sc->sc_needs_unmap = 1056 (config_found_ia(dev, "drm", aux, radeonfb_drm_print) != 0); 1057 DPRINTF(("needs_unmap: %d\n", sc->sc_needs_unmap)); 1058 1059 if (!IS_AVIVO(sc)) { 1060 PRINTREG(RADEON_CRTC_EXT_CNTL); 1061 PRINTREG(RADEON_CRTC_GEN_CNTL); 1062 PRINTREG(RADEON_CRTC2_GEN_CNTL); 1063 PRINTREG(RADEON_DISP_OUTPUT_CNTL); 1064 PRINTREG(RADEON_DAC_CNTL2); 1065 PRINTREG(RADEON_FP_GEN_CNTL); 1066 PRINTREG(RADEON_FP2_GEN_CNTL); 1067 PRINTREG(RADEON_TMDS_CNTL); 1068 PRINTREG(RADEON_TMDS_TRANSMITTER_CNTL); 1069 PRINTREG(RADEON_TMDS_PLL_CNTL); 1070 /* 1071 XXX: We can't print this, as it's not correctly aligned 1072 PRINTREG(RADEON_PIXCLKS_CNTL); 1073 */ 1074 } 1075 return; 1076 1077 error: 1078 if (sc->sc_biossz) 1079 free(sc->sc_bios, M_DEVBUF); 1080 1081 if (sc->sc_regsz) 1082 bus_space_unmap(sc->sc_regt, sc->sc_regh, sc->sc_regsz); 1083 1084 if (sc->sc_memsz) 1085 bus_space_unmap(sc->sc_memt, sc->sc_memh, sc->sc_memsz); 1086 } 1087 1088 static void 1089 radeonfb_map(struct radeonfb_softc *sc) 1090 { 1091 if (!sc->sc_mapped) { 1092 if (bus_space_map(sc->sc_regt, sc->sc_regaddr, sc->sc_regsz, 0, 1093 &sc->sc_regh) != 0) { 1094 aprint_error_dev(sc->sc_dev, 1095 "unable to map registers!\n"); 1096 return; 1097 } 1098 if (bus_space_map(sc->sc_memt, sc->sc_memaddr, sc->sc_memsz, 1099 BUS_SPACE_MAP_LINEAR, &sc->sc_memh) != 0) { 1100 sc->sc_memsz = 0; 1101 aprint_error_dev(sc->sc_dev, 1102 "Unable to map frame buffer\n"); 1103 return; 1104 } 1105 sc->sc_mapped = TRUE; 1106 } 1107 } 1108 1109 static void 1110 radeonfb_unmap(struct radeonfb_softc *sc) 1111 { 1112 if (!sc->sc_needs_unmap) 1113 return; 1114 1115 if (sc->sc_mapped) { 1116 bus_space_unmap(sc->sc_regt, sc->sc_regh, sc->sc_regsz); 1117 bus_space_unmap(sc->sc_memt, sc->sc_memh, sc->sc_memsz); 1118 sc->sc_mapped = FALSE; 1119 } 1120 } 1121 1122 static int 1123 radeonfb_drm_print(void *aux, const char *pnp) 1124 { 1125 if (pnp) 1126 aprint_normal("drm at %s", pnp); 1127 return (UNCONF); 1128 } 1129 1130 int 1131 radeonfb_ioctl(void *v, void *vs, 1132 unsigned long cmd, void *d, int flag, struct lwp *l) 1133 { 1134 struct vcons_data *vd; 1135 struct radeonfb_display *dp; 1136 struct radeonfb_softc *sc; 1137 struct wsdisplay_param *param; 1138 struct vcons_screen *ms; 1139 1140 vd = (struct vcons_data *)v; 1141 ms = vd->active; 1142 dp = (struct radeonfb_display *)vd->cookie; 1143 sc = dp->rd_softc; 1144 1145 /* can't do these without registers being mapped */ 1146 if (!sc->sc_mapped) { 1147 switch (cmd) { 1148 case WSDISPLAYIO_GVIDEO: 1149 case WSDISPLAYIO_SVIDEO: 1150 case WSDISPLAYIO_GETCMAP: 1151 case WSDISPLAYIO_PUTCMAP: 1152 case WSDISPLAYIO_SCURSOR: 1153 case WSDISPLAYIO_GCURPOS: 1154 case WSDISPLAYIO_SCURPOS: 1155 case WSDISPLAYIO_SETPARAM: 1156 return EINVAL; 1157 } 1158 } 1159 1160 switch (cmd) { 1161 case WSDISPLAYIO_GTYPE: 1162 *(unsigned *)d = WSDISPLAY_TYPE_PCIMISC; 1163 return 0; 1164 1165 case WSDISPLAYIO_GINFO: 1166 if (vd->active != NULL) { 1167 struct wsdisplay_fbinfo *fb; 1168 fb = (struct wsdisplay_fbinfo *)d; 1169 fb->width = dp->rd_virtx; 1170 fb->height = dp->rd_virty; 1171 fb->depth = dp->rd_bpp; 1172 fb->cmsize = 256; 1173 return 0; 1174 } else 1175 return ENODEV; 1176 case WSDISPLAYIO_GVIDEO: 1177 if (radeonfb_isblank(dp)) 1178 *(unsigned *)d = WSDISPLAYIO_VIDEO_OFF; 1179 else 1180 *(unsigned *)d = WSDISPLAYIO_VIDEO_ON; 1181 return 0; 1182 1183 case WSDISPLAYIO_SVIDEO: 1184 if (dp->rd_wsmode != WSDISPLAYIO_MODE_MAPPED) { 1185 radeonfb_blank(dp, 1186 (*(unsigned int *)d == WSDISPLAYIO_VIDEO_OFF)); 1187 radeonfb_switch_backlight(dp, 1188 (*(unsigned int *)d == WSDISPLAYIO_VIDEO_ON)); 1189 } 1190 pmf_event_inject(NULL, 1191 (*(unsigned int *)d == WSDISPLAYIO_VIDEO_ON) ? 1192 PMFE_DISPLAY_ON : PMFE_DISPLAY_OFF); 1193 return 0; 1194 1195 case WSDISPLAYIO_GETCMAP: 1196 if (dp->rd_bpp == 8) 1197 return radeonfb_getcmap(dp, 1198 (struct wsdisplay_cmap *)d); 1199 return EINVAL; 1200 1201 case WSDISPLAYIO_PUTCMAP: 1202 if (dp->rd_bpp == 8) 1203 return radeonfb_putcmap(dp, 1204 (struct wsdisplay_cmap *)d); 1205 return EINVAL; 1206 1207 case WSDISPLAYIO_LINEBYTES: 1208 *(unsigned *)d = dp->rd_stride; 1209 return 0; 1210 1211 case WSDISPLAYIO_SMODE: 1212 if (*(int *)d != dp->rd_wsmode) { 1213 dp->rd_wsmode = *(int *)d; 1214 if ((dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) || 1215 (dp->rd_wsmode == WSDISPLAYIO_MODE_DUMBFB)) 1216 radeonfb_map(sc); 1217 1218 if ((dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) && 1219 (dp->rd_vd.active)) { 1220 radeonfb_engine_init(dp); 1221 glyphcache_wipe(&dp->rd_gc); 1222 radeonfb_init_palette(dp); 1223 radeonfb_modeswitch(dp); 1224 radeonfb_rectfill(dp, 0, 0, dp->rd_virtx, 1225 dp->rd_virty, dp->rd_bg); 1226 vcons_redraw_screen(dp->rd_vd.active); 1227 } 1228 if (dp->rd_wsmode == WSDISPLAYIO_MODE_MAPPED) 1229 radeonfb_unmap(sc); 1230 } 1231 return 0; 1232 1233 case WSDISPLAYIO_GCURMAX: 1234 ((struct wsdisplay_curpos *)d)->x = RADEON_CURSORMAXX; 1235 ((struct wsdisplay_curpos *)d)->y = RADEON_CURSORMAXY; 1236 return 0; 1237 1238 case WSDISPLAYIO_SCURSOR: 1239 return radeonfb_set_cursor(dp, (struct wsdisplay_cursor *)d); 1240 1241 case WSDISPLAYIO_GCURSOR: 1242 return EPASSTHROUGH; 1243 1244 case WSDISPLAYIO_GCURPOS: 1245 ((struct wsdisplay_curpos *)d)->x = dp->rd_cursor.rc_pos.x; 1246 ((struct wsdisplay_curpos *)d)->y = dp->rd_cursor.rc_pos.y; 1247 return 0; 1248 1249 case WSDISPLAYIO_SCURPOS: 1250 return radeonfb_set_curpos(dp, (struct wsdisplay_curpos *)d); 1251 1252 case WSDISPLAYIO_SSPLASH: 1253 #if defined(SPLASHSCREEN) 1254 if (*(int *)d == 1) { 1255 SCREEN_DISABLE_DRAWING(&dp->rd_vscreen); 1256 splash_render(&dp->rd_splash, 1257 SPLASH_F_CENTER|SPLASH_F_FILL); 1258 } else 1259 SCREEN_ENABLE_DRAWING(&dp->rd_vscreen); 1260 return 0; 1261 #else 1262 return ENODEV; 1263 #endif 1264 case WSDISPLAYIO_GETPARAM: 1265 param = (struct wsdisplay_param *)d; 1266 switch (param->param) { 1267 case WSDISPLAYIO_PARAM_BRIGHTNESS: 1268 param->min = 0; 1269 param->max = 255; 1270 param->curval = dp->rd_bl_level; 1271 return 0; 1272 case WSDISPLAYIO_PARAM_BACKLIGHT: 1273 param->min = 0; 1274 param->max = RADEONFB_BACKLIGHT_MAX; 1275 param->curval = dp->rd_bl_on; 1276 return 0; 1277 } 1278 return EPASSTHROUGH; 1279 1280 case WSDISPLAYIO_SETPARAM: 1281 param = (struct wsdisplay_param *)d; 1282 switch (param->param) { 1283 case WSDISPLAYIO_PARAM_BRIGHTNESS: 1284 radeonfb_set_backlight(dp, param->curval); 1285 return 0; 1286 case WSDISPLAYIO_PARAM_BACKLIGHT: 1287 radeonfb_switch_backlight(dp, param->curval); 1288 return 0; 1289 } 1290 return EPASSTHROUGH; 1291 1292 /* PCI config read/write passthrough. */ 1293 case PCI_IOC_CFGREAD: 1294 case PCI_IOC_CFGWRITE: 1295 return pci_devioctl(sc->sc_pc, sc->sc_pt, cmd, d, flag, l); 1296 1297 case WSDISPLAYIO_GET_BUSID: 1298 return wsdisplayio_busid_pci(sc->sc_dev, sc->sc_pc, 1299 sc->sc_pt, d); 1300 1301 case WSDISPLAYIO_GET_EDID: { 1302 struct wsdisplayio_edid_info *ei = d; 1303 return wsdisplayio_get_edid(sc->sc_dev, ei); 1304 } 1305 1306 case WSDISPLAYIO_GET_FBINFO: { 1307 struct wsdisplayio_fbinfo *fbi = d; 1308 return wsdisplayio_get_fbinfo(&ms->scr_ri, fbi); 1309 } 1310 1311 default: 1312 return EPASSTHROUGH; 1313 } 1314 } 1315 1316 paddr_t 1317 radeonfb_mmap(void *v, void *vs, off_t offset, int prot) 1318 { 1319 struct vcons_data *vd; 1320 struct radeonfb_display *dp; 1321 struct radeonfb_softc *sc; 1322 paddr_t pa; 1323 1324 vd = (struct vcons_data *)v; 1325 dp = (struct radeonfb_display *)vd->cookie; 1326 sc = dp->rd_softc; 1327 1328 if ((offset >= 0) && (offset < (dp->rd_virty * dp->rd_stride))) { 1329 pa = bus_space_mmap(sc->sc_memt, 1330 sc->sc_memaddr + dp->rd_offset + offset, 0, 1331 prot, BUS_SPACE_MAP_LINEAR); 1332 return pa; 1333 } 1334 1335 /* 1336 * restrict all other mappings to processes with superuser privileges 1337 * or the kernel itself 1338 */ 1339 if (kauth_authorize_machdep(kauth_cred_get(), KAUTH_MACHDEP_UNMANAGEDMEM, 1340 NULL, NULL, NULL, NULL) != 0) { 1341 aprint_error_dev(sc->sc_dev, "mmap() rejected.\n"); 1342 return -1; 1343 } 1344 1345 if ((offset >= sc->sc_regaddr) && 1346 (offset < sc->sc_regaddr + sc->sc_regsz)) { 1347 return bus_space_mmap(sc->sc_regt, offset, 0, prot, 1348 BUS_SPACE_MAP_LINEAR); 1349 } 1350 1351 if ((offset >= sc->sc_memaddr) && 1352 (offset < sc->sc_memaddr + sc->sc_memsz)) { 1353 return bus_space_mmap(sc->sc_memt, offset, 0, prot, 1354 BUS_SPACE_MAP_LINEAR); 1355 } 1356 1357 if ((offset >= sc->sc_romaddr) && 1358 (offset < sc->sc_romaddr + sc->sc_romsz)) { 1359 return bus_space_mmap(sc->sc_memt, offset, 0, prot, 1360 BUS_SPACE_MAP_LINEAR); 1361 } 1362 1363 #ifdef PCI_MAGIC_IO_RANGE 1364 /* allow mapping of IO space */ 1365 if ((offset >= PCI_MAGIC_IO_RANGE) && 1366 (offset < PCI_MAGIC_IO_RANGE + 0x10000)) { 1367 pa = bus_space_mmap(sc->sc_iot, offset - PCI_MAGIC_IO_RANGE, 1368 0, prot, 0); 1369 return pa; 1370 } 1371 #endif /* PCI_MAGIC_IO_RANGE */ 1372 1373 return -1; 1374 } 1375 1376 static void 1377 radeonfb_loadbios(struct radeonfb_softc *sc, const struct pci_attach_args *pa) 1378 { 1379 bus_space_tag_t romt; 1380 bus_space_handle_t romh, biosh; 1381 bus_size_t romsz; 1382 bus_addr_t ptr; 1383 uint32_t busctl, crtcg, crtc2g = 0, viphctl, seprom, extc; 1384 int bios_voodoo = 0; 1385 1386 if (pci_mapreg_map(pa, PCI_MAPREG_ROM, PCI_MAPREG_TYPE_ROM, 1387 BUS_SPACE_MAP_PREFETCHABLE, &romt, &romh, NULL, &romsz) != 0) { 1388 aprint_verbose("%s: unable to map BIOS!\n", XNAME(sc)); 1389 return; 1390 } 1391 1392 pci_find_rom(pa, romt, romh, romsz, PCI_ROM_CODE_TYPE_X86, &biosh, 1393 &sc->sc_biossz); 1394 if (sc->sc_biossz != 0) goto foundit; 1395 1396 aprint_verbose("trying to read disabled BIOS...\n"); 1397 1398 bios_voodoo = 1; 1399 seprom = radeonfb_get32(sc, RADEON_SEPROM_CNTL1); 1400 radeonfb_put32(sc, RADEON_SEPROM_CNTL1, 1401 (seprom & ~RADEON_SCK_PRESCALE_MASK) | 1402 (0xc << RADEON_SCK_PRESCALE_SHIFT)); 1403 viphctl = radeonfb_get32(sc, RADEON_VIPH_CONTROL); 1404 radeonfb_put32(sc, RADEON_VIPH_CONTROL, viphctl & ~RADEON_VIPH_EN); 1405 busctl = radeonfb_get32(sc, RADEON_BUS_CNTL); 1406 radeonfb_put32(sc, RADEON_BUS_CNTL, busctl & ~RADEON_BUS_BIOS_DIS_ROM); 1407 crtcg = radeonfb_get32(sc, RADEON_CRTC_GEN_CNTL); 1408 radeonfb_put32(sc, RADEON_CRTC_GEN_CNTL, ((crtcg & ~RADEON_CRTC_EN) | 1409 (RADEON_CRTC_DISP_REQ_EN_B | 1410 RADEON_CRTC_EXT_DISP_EN))); 1411 if (HAS_CRTC2(sc)) { 1412 crtc2g = radeonfb_get32(sc, RADEON_CRTC2_GEN_CNTL); 1413 radeonfb_put32(sc, RADEON_CRTC2_GEN_CNTL, 1414 (crtc2g & ~RADEON_CRTC2_EN) | 1415 RADEON_CRTC2_DISP_REQ_EN_B); 1416 } 1417 extc = radeonfb_get32(sc, RADEON_CRTC_EXT_CNTL); 1418 radeonfb_put32(sc, RADEON_CRTC_EXT_CNTL, (extc & ~RADEON_CRTC_CRT_ON) | 1419 (RADEON_CRTC_SYNC_TRISTAT | 1420 RADEON_CRTC_DISPLAY_DIS)); 1421 pci_find_rom(pa, romt, romh, romsz, PCI_ROM_CODE_TYPE_X86, &biosh, 1422 &sc->sc_biossz); 1423 1424 foundit: 1425 if (sc->sc_biossz > 0) { 1426 sc->sc_bios = malloc(sc->sc_biossz, M_DEVBUF, M_WAITOK); 1427 bus_space_read_region_1(romt, biosh, 0, sc->sc_bios, 1428 sc->sc_biossz); 1429 } 1430 1431 if (bios_voodoo != 0) { 1432 radeonfb_put32(sc, RADEON_CRTC_EXT_CNTL, extc); 1433 if (HAS_CRTC2(sc)) { 1434 radeonfb_put32(sc, RADEON_CRTC2_GEN_CNTL, crtc2g); 1435 } 1436 radeonfb_put32(sc, RADEON_CRTC_GEN_CNTL, crtcg); 1437 radeonfb_put32(sc, RADEON_BUS_CNTL, busctl); 1438 radeonfb_put32(sc, RADEON_VIPH_CONTROL, viphctl); 1439 radeonfb_put32(sc, RADEON_SEPROM_CNTL1, seprom); 1440 } 1441 1442 /* unmap the PCI expansion rom */ 1443 bus_space_unmap(romt, romh, romsz); 1444 1445 /* turn off rom decoder now */ 1446 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM, 1447 pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM) & 1448 ~PCI_MAPREG_ROM_ENABLE); 1449 1450 if (sc->sc_biossz > 0) { 1451 ptr = GETBIOS16(sc, 0x48); 1452 if ((GETBIOS32(sc, ptr + 4) == 0x41544f4d /* "ATOM" */) || 1453 (GETBIOS32(sc, ptr + 4) == 0x4d4f5441 /* "MOTA" */)) { 1454 sc->sc_flags |= RFB_ATOM; 1455 } 1456 1457 aprint_verbose("%s: Found %d KB %s BIOS\n", XNAME(sc), 1458 (unsigned)sc->sc_biossz >> 10, 1459 IS_ATOM(sc) ? "ATOM" : "Legacy"); 1460 } 1461 } 1462 1463 1464 uint32_t 1465 radeonfb_get32(struct radeonfb_softc *sc, uint32_t reg) 1466 { 1467 1468 return bus_space_read_4(sc->sc_regt, sc->sc_regh, reg); 1469 } 1470 1471 void 1472 radeonfb_put32(struct radeonfb_softc *sc, uint32_t reg, uint32_t val) 1473 { 1474 1475 bus_space_write_4(sc->sc_regt, sc->sc_regh, reg, val); 1476 } 1477 1478 void 1479 radeonfb_put32s(struct radeonfb_softc *sc, uint32_t reg, uint32_t val) 1480 { 1481 1482 bus_space_write_stream_4(sc->sc_regt, sc->sc_regh, reg, val); 1483 } 1484 1485 void 1486 radeonfb_mask32(struct radeonfb_softc *sc, uint32_t reg, 1487 uint32_t andmask, uint32_t ormask) 1488 { 1489 int s; 1490 uint32_t val; 1491 1492 s = splhigh(); 1493 val = radeonfb_get32(sc, reg); 1494 val = (val & andmask) | ormask; 1495 radeonfb_put32(sc, reg, val); 1496 splx(s); 1497 } 1498 1499 uint32_t 1500 radeonfb_getindex(struct radeonfb_softc *sc, uint32_t idx) 1501 { 1502 int s; 1503 uint32_t val; 1504 1505 s = splhigh(); 1506 radeonfb_put32(sc, RADEON_MM_INDEX, idx); 1507 val = radeonfb_get32(sc, RADEON_MM_DATA); 1508 splx(s); 1509 1510 return (val); 1511 } 1512 1513 void 1514 radeonfb_putindex(struct radeonfb_softc *sc, uint32_t idx, uint32_t val) 1515 { 1516 int s; 1517 1518 s = splhigh(); 1519 radeonfb_put32(sc, RADEON_MM_INDEX, idx); 1520 radeonfb_put32(sc, RADEON_MM_DATA, val); 1521 splx(s); 1522 } 1523 1524 void 1525 radeonfb_maskindex(struct radeonfb_softc *sc, uint32_t idx, 1526 uint32_t andmask, uint32_t ormask) 1527 { 1528 int s; 1529 uint32_t val; 1530 1531 s = splhigh(); 1532 radeonfb_put32(sc, RADEON_MM_INDEX, idx); 1533 val = radeonfb_get32(sc, RADEON_MM_DATA); 1534 val = (val & andmask) | ormask; 1535 radeonfb_put32(sc, RADEON_MM_DATA, val); 1536 splx(s); 1537 } 1538 1539 uint32_t 1540 radeonfb_getpll(struct radeonfb_softc *sc, uint32_t idx) 1541 { 1542 int s; 1543 uint32_t val; 1544 1545 s = splhigh(); 1546 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, (idx & 0x3f)); 1547 val = radeonfb_get32(sc, RADEON_CLOCK_CNTL_DATA); 1548 if (HAS_R300CG(sc)) 1549 radeonfb_r300cg_workaround(sc); 1550 splx(s); 1551 1552 return (val); 1553 } 1554 1555 void 1556 radeonfb_putpll(struct radeonfb_softc *sc, uint32_t idx, uint32_t val) 1557 { 1558 int s; 1559 1560 s = splhigh(); 1561 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, (idx & 0x3f) | 1562 RADEON_PLL_WR_EN); 1563 radeonfb_put32(sc, RADEON_CLOCK_CNTL_DATA, val); 1564 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, 0); 1565 splx(s); 1566 } 1567 1568 void 1569 radeonfb_maskpll(struct radeonfb_softc *sc, uint32_t idx, 1570 uint32_t andmask, uint32_t ormask) 1571 { 1572 int s; 1573 uint32_t val; 1574 1575 s = splhigh(); 1576 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, (idx & 0x3f) | 1577 RADEON_PLL_WR_EN); 1578 val = radeonfb_get32(sc, RADEON_CLOCK_CNTL_DATA); 1579 val = (val & andmask) | ormask; 1580 radeonfb_put32(sc, RADEON_CLOCK_CNTL_DATA, val); 1581 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, 0); 1582 splx(s); 1583 } 1584 1585 int 1586 radeonfb_scratch_test(struct radeonfb_softc *sc, int reg, uint32_t v) 1587 { 1588 uint32_t saved; 1589 1590 saved = GET32(sc, reg); 1591 PUT32(sc, reg, v); 1592 if (GET32(sc, reg) != v) { 1593 return -1; 1594 } 1595 PUT32(sc, reg, saved); 1596 return 0; 1597 } 1598 1599 uintmax_t 1600 radeonfb_getprop_num(struct radeonfb_softc *sc, const char *name, 1601 uintmax_t defval) 1602 { 1603 prop_number_t pn; 1604 pn = prop_dictionary_get(device_properties(sc->sc_dev), name); 1605 if (pn == NULL) { 1606 return defval; 1607 } 1608 KASSERT(prop_object_type(pn) == PROP_TYPE_NUMBER); 1609 return prop_number_unsigned_value(pn); 1610 } 1611 1612 int 1613 radeonfb_getclocks(struct radeonfb_softc *sc) 1614 { 1615 bus_addr_t ptr; 1616 int refclk = 0; 1617 int refdiv = 0; 1618 int minpll = 0; 1619 int maxpll = 0; 1620 1621 /* load initial property values if port/board provides them */ 1622 refclk = radeonfb_getprop_num(sc, "refclk", 0) & 0xffff; 1623 refdiv = radeonfb_getprop_num(sc, "refdiv", 0) & 0xffff; 1624 minpll = radeonfb_getprop_num(sc, "minpll", 0) & 0xffffffffU; 1625 maxpll = radeonfb_getprop_num(sc, "maxpll", 0) & 0xffffffffU; 1626 1627 PRINTPLL(RADEON_PPLL_REF_DIV); 1628 PRINTPLL(RADEON_PPLL_DIV_0); 1629 PRINTPLL(RADEON_PPLL_DIV_1); 1630 PRINTPLL(RADEON_PPLL_DIV_2); 1631 PRINTPLL(RADEON_PPLL_DIV_3); 1632 PRINTREG(RADEON_CLOCK_CNTL_INDEX); 1633 PRINTPLL(RADEON_P2PLL_REF_DIV); 1634 PRINTPLL(RADEON_P2PLL_DIV_0); 1635 1636 if (refclk && refdiv && minpll && maxpll) 1637 goto dontprobe; 1638 1639 if (!sc->sc_biossz) { 1640 /* no BIOS */ 1641 aprint_verbose("%s: No video BIOS, using default clocks\n", 1642 XNAME(sc)); 1643 if (IS_IGP(sc)) 1644 refclk = refclk ? refclk : 1432; 1645 else 1646 refclk = refclk ? refclk : 2700; 1647 refdiv = refdiv ? refdiv : 12; 1648 minpll = minpll ? minpll : 12500; 1649 /* XXX 1650 * Need to check if the firmware or something programmed a 1651 * higher value than this, and if so, bump it. 1652 * The RV280 in my iBook is unhappy if the PLL input is less 1653 * than 360MHz 1654 */ 1655 maxpll = maxpll ? maxpll : 40000/*35000*/; 1656 } else if (IS_ATOM(sc)) { 1657 /* ATOM BIOS */ 1658 ptr = GETBIOS16(sc, 0x48); 1659 ptr = GETBIOS16(sc, ptr + 32); /* aka MasterDataStart */ 1660 ptr = GETBIOS16(sc, ptr + 12); /* pll info block */ 1661 refclk = refclk ? refclk : GETBIOS16(sc, ptr + 82); 1662 minpll = minpll ? minpll : GETBIOS16(sc, ptr + 78); 1663 maxpll = maxpll ? maxpll : GETBIOS16(sc, ptr + 32); 1664 /* 1665 * ATOM BIOS doesn't supply a reference divider, so we 1666 * have to probe for it. 1667 */ 1668 if (refdiv < 2) 1669 refdiv = GETPLL(sc, RADEON_PPLL_REF_DIV) & 1670 RADEON_PPLL_REF_DIV_MASK; 1671 /* 1672 * if probe is zero, just assume one that should work 1673 * for most parts 1674 */ 1675 if (refdiv < 2) 1676 refdiv = 12; 1677 1678 } else { 1679 uint32_t tmp = GETPLL(sc, RADEON_PPLL_REF_DIV); 1680 /* Legacy BIOS */ 1681 ptr = GETBIOS16(sc, 0x48); 1682 ptr = GETBIOS16(sc, ptr + 0x30); 1683 if (IS_R300(sc)) { 1684 refdiv = refdiv ? refdiv : 1685 (tmp & R300_PPLL_REF_DIV_ACC_MASK) >> 1686 R300_PPLL_REF_DIV_ACC_SHIFT; 1687 } else { 1688 refdiv = refdiv ? refdiv : 1689 tmp & RADEON_PPLL_REF_DIV_MASK; 1690 } 1691 refclk = refclk ? refclk : GETBIOS16(sc, ptr + 0x0E); 1692 refdiv = refdiv ? refdiv : GETBIOS16(sc, ptr + 0x10); 1693 minpll = minpll ? minpll : GETBIOS32(sc, ptr + 0x12); 1694 maxpll = maxpll ? maxpll : GETBIOS32(sc, ptr + 0x16); 1695 } 1696 1697 1698 dontprobe: 1699 sc->sc_refclk = refclk * 10; 1700 sc->sc_refdiv = refdiv; 1701 sc->sc_minpll = minpll * 10; 1702 sc->sc_maxpll = maxpll * 10; 1703 return 0; 1704 } 1705 1706 int 1707 radeonfb_calc_dividers(struct radeonfb_softc *sc, uint32_t dotclock, 1708 uint32_t *postdivbit, uint32_t *feedbackdiv, int flags) 1709 { 1710 int i; 1711 uint32_t outfreq; 1712 int div; 1713 1714 DPRINTF(("dot clock: %u\n", dotclock)); 1715 for (i = 0; (div = radeonfb_dividers[i].divider) != 0; i++) { 1716 1717 if ((flags & NO_ODD_FBDIV) && ((div & 1) != 0)) 1718 continue; 1719 1720 /* 1721 * XXX 1722 * the rv350 in my last generation 14" iBook G4 produces 1723 * garbage with dividers > 4. No idea if this is a hardware 1724 * limitation or an error in the divider table. 1725 */ 1726 if ((sc->sc_family == RADEON_RV350) && (div > 4)) 1727 continue; 1728 1729 outfreq = div * dotclock; 1730 if ((outfreq >= sc->sc_minpll) && 1731 (outfreq <= sc->sc_maxpll)) { 1732 DPRINTF(("outfreq: %u\n", outfreq)); 1733 *postdivbit = 1734 ((uint32_t)radeonfb_dividers[i].mask << 16); 1735 DPRINTF(("post divider: %d (mask %x)\n", div, 1736 *postdivbit)); 1737 break; 1738 } 1739 } 1740 1741 if (div == 0) 1742 return 1; 1743 1744 *feedbackdiv = DIVIDE(sc->sc_refdiv * outfreq, sc->sc_refclk); 1745 DPRINTF(("feedback divider: %d\n", *feedbackdiv)); 1746 return 0; 1747 } 1748 1749 #if 0 1750 #ifdef RADEONFB_DEBUG 1751 static void 1752 dump_buffer(const char *pfx, void *buffer, unsigned int size) 1753 { 1754 char asc[17]; 1755 unsigned ptr = (unsigned)buffer; 1756 char *start = (char *)(ptr & ~0xf); 1757 char *end = (char *)(ptr + size); 1758 1759 end = (char *)(((unsigned)end + 0xf) & ~0xf); 1760 1761 if (pfx == NULL) { 1762 pfx = ""; 1763 } 1764 1765 while (start < end) { 1766 unsigned offset = (unsigned)start & 0xf; 1767 if (offset == 0) { 1768 printf("%s%x: ", pfx, (unsigned)start); 1769 } 1770 if (((unsigned)start < ptr) || 1771 ((unsigned)start >= (ptr + size))) { 1772 printf(" "); 1773 asc[offset] = ' '; 1774 } else { 1775 printf("%02x", *(unsigned char *)start); 1776 if ((*start >= ' ') && (*start <= '~')) { 1777 asc[offset] = *start; 1778 } else { 1779 asc[offset] = '.'; 1780 } 1781 } 1782 asc[offset + 1] = 0; 1783 if (offset % 2) { 1784 printf(" "); 1785 } 1786 if (offset == 15) { 1787 printf(" %s\n", asc); 1788 } 1789 start++; 1790 } 1791 } 1792 #endif 1793 #endif 1794 1795 int 1796 radeonfb_getconnectors(struct radeonfb_softc *sc) 1797 { 1798 int i; 1799 int found = 0; 1800 1801 for (i = 0; i < 2; i++) { 1802 sc->sc_ports[i].rp_mon_type = RADEON_MT_UNKNOWN; 1803 sc->sc_ports[i].rp_ddc_type = RADEON_DDC_NONE; 1804 sc->sc_ports[i].rp_dac_type = RADEON_DAC_UNKNOWN; 1805 sc->sc_ports[i].rp_conn_type = RADEON_CONN_NONE; 1806 sc->sc_ports[i].rp_tmds_type = RADEON_TMDS_UNKNOWN; 1807 } 1808 1809 /* 1810 * This logic is borrowed from Xorg's radeon driver. 1811 */ 1812 if (!sc->sc_biossz) 1813 goto nobios; 1814 1815 if (IS_ATOM(sc)) { 1816 /* not done yet */ 1817 } else { 1818 uint16_t ptr; 1819 int port = 0; 1820 1821 ptr = GETBIOS16(sc, 0x48); 1822 ptr = GETBIOS16(sc, ptr + 0x50); 1823 for (i = 1; i < 4; i++) { 1824 uint16_t entry; 1825 uint8_t conn, ddc, dac, tmds; 1826 1827 /* 1828 * Parse the connector table. From reading the code, 1829 * it appears to made up of 16-bit entries for each 1830 * connector. The 16-bits are defined as: 1831 * 1832 * bits 12-15 - connector type (0 == end of table) 1833 * bits 8-11 - DDC type 1834 * bits 5-7 - ??? 1835 * bit 4 - TMDS type (1 = EXT, 0 = INT) 1836 * bits 1-3 - ??? 1837 * bit 0 - DAC, 1 = TVDAC, 0 = primary 1838 */ 1839 if (!GETBIOS8(sc, ptr + i * 2) && i > 1) 1840 break; 1841 entry = GETBIOS16(sc, ptr + i * 2); 1842 1843 conn = (entry >> 12) & 0xf; 1844 ddc = (entry >> 8) & 0xf; 1845 dac = (entry & 0x1) ? RADEON_DAC_TVDAC : 1846 RADEON_DAC_PRIMARY; 1847 tmds = ((entry >> 4) & 0x1) ? RADEON_TMDS_EXT : 1848 RADEON_TMDS_INT; 1849 1850 if (conn == RADEON_CONN_NONE) 1851 continue; /* no connector */ 1852 1853 /* 1854 * XXX 1855 * both Mac Mini variants have both outputs wired to 1856 * the same connector and share the DDC lines 1857 */ 1858 if ((found > 0) && 1859 (sc->sc_ports[port].rp_ddc_type == ddc)) { 1860 /* duplicate entry for same connector */ 1861 continue; 1862 } 1863 1864 /* internal DDC_DVI port gets priority */ 1865 if ((ddc == RADEON_DDC_DVI) || (port == 1)) 1866 port = 0; 1867 else 1868 port = 1; 1869 1870 sc->sc_ports[port].rp_ddc_type = 1871 ddc > RADEON_DDC_CRT2 ? RADEON_DDC_NONE : ddc; 1872 sc->sc_ports[port].rp_dac_type = dac; 1873 sc->sc_ports[port].rp_conn_type = 1874 uimin(conn, RADEON_CONN_UNSUPPORTED) ; 1875 1876 sc->sc_ports[port].rp_tmds_type = tmds; 1877 1878 if ((conn != RADEON_CONN_DVI_I) && 1879 (conn != RADEON_CONN_DVI_D) && 1880 (tmds == RADEON_TMDS_INT)) 1881 sc->sc_ports[port].rp_tmds_type = 1882 RADEON_TMDS_UNKNOWN; 1883 sc->sc_ports[port].rp_number = i - 1; 1884 1885 found += (port + 1); 1886 } 1887 } 1888 1889 nobios: 1890 if (!found) { 1891 bool dvi_ext = FALSE, dvi_int = FALSE; 1892 DPRINTF(("No connector info in BIOS!\n")); 1893 prop_dictionary_get_bool(device_properties(sc->sc_dev), 1894 "dvi-internal", &dvi_int); 1895 prop_dictionary_get_bool(device_properties(sc->sc_dev), 1896 "dvi-external", &dvi_ext); 1897 if (dvi_ext) { 1898 sc->sc_ports[0].rp_mon_type = RADEON_MT_UNKNOWN; 1899 sc->sc_ports[0].rp_ddc_type = RADEON_DDC_CRT2; 1900 sc->sc_ports[0].rp_dac_type = RADEON_DAC_PRIMARY; 1901 sc->sc_ports[0].rp_conn_type = RADEON_CONN_DVI_I; 1902 sc->sc_ports[0].rp_tmds_type = RADEON_TMDS_EXT; /* output to fp2 */ 1903 sc->sc_ports[0].rp_number = 0; 1904 sc->sc_ports[1].rp_mon_type = RADEON_MT_UNKNOWN; 1905 sc->sc_ports[1].rp_ddc_type = RADEON_DDC_NONE; 1906 sc->sc_ports[1].rp_dac_type = RADEON_DAC_UNKNOWN; 1907 sc->sc_ports[1].rp_conn_type = RADEON_CONN_NONE; 1908 sc->sc_ports[1].rp_tmds_type = RADEON_TMDS_UNKNOWN; 1909 sc->sc_ports[1].rp_number = 1; 1910 } else if (dvi_int) { 1911 sc->sc_ports[0].rp_mon_type = RADEON_MT_UNKNOWN; 1912 sc->sc_ports[0].rp_ddc_type = RADEON_DDC_CRT2; 1913 sc->sc_ports[0].rp_dac_type = RADEON_DAC_PRIMARY; 1914 sc->sc_ports[0].rp_conn_type = RADEON_CONN_DVI_I; 1915 sc->sc_ports[0].rp_tmds_type = RADEON_TMDS_INT; 1916 sc->sc_ports[0].rp_number = 0; 1917 sc->sc_ports[1].rp_mon_type = RADEON_MT_UNKNOWN; 1918 sc->sc_ports[1].rp_ddc_type = RADEON_DDC_NONE; 1919 sc->sc_ports[1].rp_dac_type = RADEON_DAC_UNKNOWN; 1920 sc->sc_ports[1].rp_conn_type = RADEON_CONN_NONE; 1921 sc->sc_ports[1].rp_tmds_type = RADEON_TMDS_UNKNOWN; 1922 sc->sc_ports[1].rp_number = 1; 1923 } else if IS_MOBILITY(sc) { 1924 /* default, port 0 = internal TMDS, port 1 = CRT */ 1925 sc->sc_ports[0].rp_mon_type = RADEON_MT_UNKNOWN; 1926 sc->sc_ports[0].rp_ddc_type = RADEON_DDC_DVI; 1927 sc->sc_ports[0].rp_dac_type = RADEON_DAC_TVDAC; 1928 sc->sc_ports[0].rp_conn_type = RADEON_CONN_DVI_D; 1929 sc->sc_ports[0].rp_tmds_type = RADEON_TMDS_INT; 1930 sc->sc_ports[0].rp_number = 0; 1931 1932 sc->sc_ports[1].rp_mon_type = RADEON_MT_UNKNOWN; 1933 sc->sc_ports[1].rp_ddc_type = RADEON_DDC_VGA; 1934 sc->sc_ports[1].rp_dac_type = RADEON_DAC_PRIMARY; 1935 sc->sc_ports[1].rp_conn_type = RADEON_CONN_CRT; 1936 sc->sc_ports[1].rp_tmds_type = RADEON_TMDS_EXT; 1937 sc->sc_ports[1].rp_number = 1; 1938 } else { 1939 /* default, port 0 = DVI, port 1 = CRT */ 1940 sc->sc_ports[0].rp_mon_type = RADEON_MT_UNKNOWN; 1941 sc->sc_ports[0].rp_ddc_type = RADEON_DDC_DVI; 1942 sc->sc_ports[0].rp_dac_type = RADEON_DAC_TVDAC; 1943 sc->sc_ports[0].rp_conn_type = RADEON_CONN_DVI_D; 1944 sc->sc_ports[0].rp_tmds_type = RADEON_TMDS_INT; 1945 sc->sc_ports[0].rp_number = 0; 1946 1947 sc->sc_ports[1].rp_mon_type = RADEON_MT_UNKNOWN; 1948 sc->sc_ports[1].rp_ddc_type = RADEON_DDC_VGA; 1949 sc->sc_ports[1].rp_dac_type = RADEON_DAC_PRIMARY; 1950 sc->sc_ports[1].rp_conn_type = RADEON_CONN_CRT; 1951 sc->sc_ports[1].rp_tmds_type = RADEON_TMDS_UNKNOWN; 1952 sc->sc_ports[1].rp_number = 1; 1953 } 1954 } 1955 1956 /* 1957 * Fixup for RS300/RS350/RS400 chips, that lack a primary DAC. 1958 * these chips should use TVDAC for the VGA port. 1959 */ 1960 if (HAS_SDAC(sc)) { 1961 if (sc->sc_ports[0].rp_conn_type == RADEON_CONN_CRT) { 1962 sc->sc_ports[0].rp_dac_type = RADEON_DAC_TVDAC; 1963 sc->sc_ports[1].rp_dac_type = RADEON_DAC_PRIMARY; 1964 } else { 1965 sc->sc_ports[1].rp_dac_type = RADEON_DAC_TVDAC; 1966 sc->sc_ports[0].rp_dac_type = RADEON_DAC_PRIMARY; 1967 } 1968 } else if (!HAS_CRTC2(sc)) { 1969 sc->sc_ports[0].rp_dac_type = RADEON_DAC_PRIMARY; 1970 } 1971 1972 for (i = 0; i < 2; i++) { 1973 char edid[128], edid_port_str[7] = "EDID:"; 1974 uint8_t ddc; 1975 struct edid_info *eip = &sc->sc_ports[i].rp_edid; 1976 prop_data_t edid_data; 1977 1978 DPRINTF(("Port #%d:\n", i)); 1979 DPRINTF((" conn = %d\n", sc->sc_ports[i].rp_conn_type)); 1980 DPRINTF((" ddc = %d\n", sc->sc_ports[i].rp_ddc_type)); 1981 DPRINTF((" dac = %d\n", sc->sc_ports[i].rp_dac_type)); 1982 DPRINTF((" tmds = %d\n", sc->sc_ports[i].rp_tmds_type)); 1983 DPRINTF((" crtc = %d\n", sc->sc_ports[i].rp_number)); 1984 1985 sc->sc_ports[i].rp_edid_valid = 0; 1986 /* 1987 * First look for static EDID data 1988 * Try "EDID:port" then "EDID" 1989 */ 1990 snprintf(&edid_port_str[5], 2, "%d", i); 1991 edid_data = prop_dictionary_get(device_properties( 1992 sc->sc_dev), edid_port_str); 1993 if (edid_data == NULL) 1994 edid_data = prop_dictionary_get(device_properties( 1995 sc->sc_dev), "EDID"); 1996 if (edid_data != NULL) { 1997 aprint_debug_dev(sc->sc_dev, "using static EDID\n"); 1998 memcpy(edid, prop_data_value(edid_data), 128); 1999 if (edid_parse(edid, eip) == 0) { 2000 2001 sc->sc_ports[i].rp_edid_valid = 1; 2002 #ifdef RADEONFB_DEBUG 2003 edid_print(eip); 2004 #endif 2005 } 2006 } 2007 /* if we didn't find any we'll try to talk to the monitor */ 2008 if (sc->sc_ports[i].rp_edid_valid != 1) { 2009 2010 ddc = sc->sc_ports[i].rp_ddc_type; 2011 if (ddc != RADEON_DDC_NONE) { 2012 if ((radeonfb_i2c_read_edid(sc, ddc, edid) 2013 == 0) && (edid_parse(edid, eip) == 0)) { 2014 2015 sc->sc_ports[i].rp_edid_valid = 1; 2016 #ifdef RADEONFB_DEBUG 2017 edid_print(eip); 2018 #endif 2019 } 2020 } 2021 } 2022 } 2023 2024 return found; 2025 } 2026 2027 int 2028 radeonfb_gettmds(struct radeonfb_softc *sc) 2029 { 2030 int i; 2031 2032 if (!sc->sc_biossz) { 2033 goto nobios; 2034 } 2035 2036 if (IS_ATOM(sc)) { 2037 /* XXX: not done yet */ 2038 } else { 2039 uint16_t ptr; 2040 int n; 2041 2042 ptr = GETBIOS16(sc, 0x48); 2043 ptr = GETBIOS16(sc, ptr + 0x34); 2044 DPRINTF(("DFP table revision %d\n", GETBIOS8(sc, ptr))); 2045 if (GETBIOS8(sc, ptr) == 3) { 2046 /* revision three table */ 2047 n = GETBIOS8(sc, ptr + 5) + 1; 2048 n = uimin(n, 4); 2049 2050 memset(sc->sc_tmds_pll, 0, sizeof (sc->sc_tmds_pll)); 2051 for (i = 0; i < n; i++) { 2052 sc->sc_tmds_pll[i].rtp_pll = GETBIOS32(sc, 2053 ptr + i * 10 + 8); 2054 sc->sc_tmds_pll[i].rtp_freq = GETBIOS16(sc, 2055 ptr + i * 10 + 0x10); 2056 DPRINTF(("TMDS_PLL dot clock %d pll %x\n", 2057 sc->sc_tmds_pll[i].rtp_freq, 2058 sc->sc_tmds_pll[i].rtp_pll)); 2059 } 2060 return 0; 2061 } 2062 } 2063 2064 nobios: 2065 DPRINTF(("no suitable DFP table present\n")); 2066 for (i = 0; 2067 i < sizeof (radeonfb_tmds_pll) / sizeof (radeonfb_tmds_pll[0]); 2068 i++) { 2069 int j; 2070 2071 if (radeonfb_tmds_pll[i].family != sc->sc_family) 2072 continue; 2073 2074 for (j = 0; j < 4; j++) { 2075 sc->sc_tmds_pll[j] = radeonfb_tmds_pll[i].plls[j]; 2076 DPRINTF(("TMDS_PLL dot clock %d pll %x\n", 2077 sc->sc_tmds_pll[j].rtp_freq, 2078 sc->sc_tmds_pll[j].rtp_pll)); 2079 } 2080 return 0; 2081 } 2082 2083 return -1; 2084 } 2085 2086 const struct videomode * 2087 radeonfb_modelookup(const char *name) 2088 { 2089 int i; 2090 /* Use a default mode in case we don't find a matching mode */ 2091 const char *vm = "1024x768x60"; 2092 const struct videomode *vmp = NULL; 2093 2094 for (i = 0; i < videomode_count; i++) { 2095 if (!strcmp(name, videomode_list[i].name)) 2096 return &videomode_list[i]; 2097 if (!strcmp(vm, videomode_list[i].name)) 2098 vmp = &videomode_list[i]; 2099 } 2100 return vmp; 2101 } 2102 2103 void 2104 radeonfb_pllwriteupdate(struct radeonfb_softc *sc, int crtc) 2105 { 2106 if (crtc) { 2107 while (GETPLL(sc, RADEON_P2PLL_REF_DIV) & 2108 RADEON_P2PLL_ATOMIC_UPDATE_R); 2109 SETPLL(sc, RADEON_P2PLL_REF_DIV, RADEON_P2PLL_ATOMIC_UPDATE_W); 2110 } else { 2111 while (GETPLL(sc, RADEON_PPLL_REF_DIV) & 2112 RADEON_PPLL_ATOMIC_UPDATE_R); 2113 SETPLL(sc, RADEON_PPLL_REF_DIV, RADEON_PPLL_ATOMIC_UPDATE_W); 2114 } 2115 } 2116 2117 void 2118 radeonfb_pllwaitatomicread(struct radeonfb_softc *sc, int crtc) 2119 { 2120 int i; 2121 2122 for (i = 10000; i; i--) { 2123 if (crtc) { 2124 if (GETPLL(sc, RADEON_P2PLL_REF_DIV) & 2125 RADEON_P2PLL_ATOMIC_UPDATE_R) 2126 break; 2127 } else { 2128 if (GETPLL(sc, RADEON_PPLL_REF_DIV) & 2129 RADEON_PPLL_ATOMIC_UPDATE_R) 2130 break; 2131 } 2132 } 2133 } 2134 2135 void 2136 radeonfb_program_vclk(struct radeonfb_softc *sc, int dotclock, int crtc, int flags) 2137 { 2138 uint32_t pbit = 0; 2139 uint32_t feed = 0; 2140 uint32_t data, refdiv, div0, r2xxref; 2141 2142 radeonfb_calc_dividers(sc, dotclock, &pbit, &feed, flags); 2143 2144 if (crtc == 0) { 2145 2146 refdiv = GETPLL(sc, RADEON_PPLL_REF_DIV); 2147 2148 /* 2149 * XXX 2150 * the RV350 in my last generation iBook G4 behaves like an 2151 * r2xx here - try to detect that and not screw up the reference 2152 * divider. 2153 * xf86-video-radeon just skips PLL programming altogether 2154 * on iBooks, probably for this reason. 2155 */ 2156 r2xxref = (refdiv & ~RADEON_PPLL_REF_DIV_MASK) | sc->sc_refdiv; 2157 if (IS_R300(sc) && (r2xxref != refdiv)) { 2158 refdiv = (refdiv & ~R300_PPLL_REF_DIV_ACC_MASK) | 2159 (sc->sc_refdiv << R300_PPLL_REF_DIV_ACC_SHIFT); 2160 } else { 2161 refdiv = (refdiv & ~RADEON_PPLL_REF_DIV_MASK) | 2162 sc->sc_refdiv; 2163 } 2164 DPRINTF(("refdiv %08x\n", refdiv)); 2165 div0 = GETPLL(sc, RADEON_PPLL_DIV_0); 2166 DPRINTF(("div0 %08x\n", div0)); 2167 div0 &= ~(RADEON_PPLL_FB3_DIV_MASK | 2168 RADEON_PPLL_POST3_DIV_MASK); 2169 div0 |= pbit; 2170 div0 |= (feed & RADEON_PPLL_FB3_DIV_MASK); 2171 DPRINTF(("div0 %08x\n", div0)); 2172 2173 if ((refdiv == GETPLL(sc, RADEON_PPLL_REF_DIV)) && 2174 (div0 == GETPLL(sc, RADEON_PPLL_DIV_0))) { 2175 /* 2176 * nothing to do here, the PLL is already where we 2177 * want it 2178 */ 2179 PATCH32(sc, RADEON_CLOCK_CNTL_INDEX, 0, 2180 ~RADEON_PLL_DIV_SEL); 2181 aprint_debug_dev(sc->sc_dev, "no need to touch the PLL\n"); 2182 return; 2183 } 2184 2185 /* alright, we do need to reprogram stuff */ 2186 PATCHPLL(sc, RADEON_VCLK_ECP_CNTL, 2187 RADEON_VCLK_SRC_SEL_CPUCLK, 2188 ~RADEON_VCLK_SRC_SEL_MASK); 2189 2190 /* put vclk into reset, use atomic updates */ 2191 SETPLL(sc, RADEON_PPLL_CNTL, 2192 RADEON_PPLL_REFCLK_SEL | 2193 RADEON_PPLL_FBCLK_SEL | 2194 RADEON_PPLL_RESET | 2195 RADEON_PPLL_ATOMIC_UPDATE_EN | 2196 RADEON_PPLL_VGA_ATOMIC_UPDATE_EN); 2197 2198 /* select clock 0 */ 2199 PATCH32(sc, RADEON_CLOCK_CNTL_INDEX, 0, 2200 ~RADEON_PLL_DIV_SEL); 2201 2202 PUTPLL(sc, RADEON_PPLL_REF_DIV, refdiv); 2203 2204 /* xf86-video-radeon does this, not sure why */ 2205 PUTPLL(sc, RADEON_PPLL_DIV_0, div0); 2206 PUTPLL(sc, RADEON_PPLL_DIV_0, div0); 2207 2208 /* use the atomic update */ 2209 radeonfb_pllwriteupdate(sc, crtc); 2210 2211 /* and wait for it to complete */ 2212 radeonfb_pllwaitatomicread(sc, crtc); 2213 2214 /* program HTOTAL (why?) */ 2215 PUTPLL(sc, RADEON_HTOTAL_CNTL, 0); 2216 2217 /* drop reset */ 2218 CLRPLL(sc, RADEON_PPLL_CNTL, 2219 RADEON_PPLL_RESET | RADEON_PPLL_SLEEP | 2220 RADEON_PPLL_ATOMIC_UPDATE_EN | 2221 RADEON_PPLL_VGA_ATOMIC_UPDATE_EN); 2222 2223 PRINTPLL(RADEON_PPLL_CNTL); 2224 PRINTPLL(RADEON_PPLL_REF_DIV); 2225 PRINTPLL(RADEON_PPLL_DIV_3); 2226 2227 /* give clock time to lock */ 2228 delay(50000); 2229 2230 PATCHPLL(sc, RADEON_VCLK_ECP_CNTL, 2231 RADEON_VCLK_SRC_SEL_PPLLCLK, 2232 ~RADEON_VCLK_SRC_SEL_MASK); 2233 2234 } else { 2235 2236 PATCHPLL(sc, RADEON_PIXCLKS_CNTL, 2237 RADEON_PIX2CLK_SRC_SEL_CPUCLK, 2238 ~RADEON_PIX2CLK_SRC_SEL_MASK); 2239 2240 /* put vclk into reset, use atomic updates */ 2241 SETPLL(sc, RADEON_P2PLL_CNTL, 2242 RADEON_P2PLL_RESET | 2243 RADEON_P2PLL_ATOMIC_UPDATE_EN | 2244 RADEON_P2PLL_VGA_ATOMIC_UPDATE_EN); 2245 2246 /* program reference divider */ 2247 PATCHPLL(sc, RADEON_P2PLL_REF_DIV, sc->sc_refdiv, 2248 ~RADEON_P2PLL_REF_DIV_MASK); 2249 2250 /* program feedback and post dividers */ 2251 data = GETPLL(sc, RADEON_P2PLL_DIV_0); 2252 data &= ~(RADEON_P2PLL_FB0_DIV_MASK | 2253 RADEON_P2PLL_POST0_DIV_MASK); 2254 data |= pbit; 2255 data |= (feed & RADEON_P2PLL_FB0_DIV_MASK); 2256 PUTPLL(sc, RADEON_P2PLL_DIV_0, data); 2257 PUTPLL(sc, RADEON_P2PLL_DIV_0, data); 2258 2259 PRINTPLL(RADEON_P2PLL_REF_DIV); 2260 PRINTPLL(RADEON_P2PLL_DIV_0); 2261 2262 /* use the atomic update */ 2263 radeonfb_pllwriteupdate(sc, crtc); 2264 2265 /* and wait for it to complete */ 2266 radeonfb_pllwaitatomicread(sc, crtc); 2267 2268 /* program HTOTAL (why?) */ 2269 PUTPLL(sc, RADEON_HTOTAL2_CNTL, 0); 2270 2271 /* drop reset */ 2272 CLRPLL(sc, RADEON_P2PLL_CNTL, 2273 RADEON_P2PLL_RESET | RADEON_P2PLL_SLEEP | 2274 RADEON_P2PLL_ATOMIC_UPDATE_EN | 2275 RADEON_P2PLL_VGA_ATOMIC_UPDATE_EN); 2276 2277 /* allow time for clock to lock */ 2278 delay(50000); 2279 2280 PATCHPLL(sc, RADEON_PIXCLKS_CNTL, 2281 RADEON_PIX2CLK_SRC_SEL_P2PLLCLK, 2282 ~RADEON_PIX2CLK_SRC_SEL_MASK); 2283 } 2284 PRINTREG(RADEON_CRTC_MORE_CNTL); 2285 } 2286 2287 void 2288 radeonfb_modeswitch(struct radeonfb_display *dp) 2289 { 2290 struct radeonfb_softc *sc = dp->rd_softc; 2291 int i; 2292 2293 if (IS_AVIVO(sc)) { 2294 /* 2295 * no actual mode setting yet, we just make sure the CRTCs 2296 * point at the right memory ranges and use the same pitch 2297 * for the drawing engine 2298 */ 2299 if (GET32(sc, AVIVO_D1CRTC_CONTROL) & AVIVO_CRTC_EN) { 2300 CLR32(sc, AVIVO_D1GRPH_CONTROL, AVIVO_D1GRPH_MACRO_ADDRESS_MODE); 2301 dp->rd_stride = GET32(sc, AVIVO_D1GRPH_PITCH); 2302 PUT32(sc, AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS, 0); 2303 } 2304 if (GET32(sc, AVIVO_D2CRTC_CONTROL) & AVIVO_CRTC_EN) { 2305 CLR32(sc, AVIVO_D2GRPH_CONTROL, AVIVO_D1GRPH_MACRO_ADDRESS_MODE); 2306 dp->rd_stride = GET32(sc, AVIVO_D2GRPH_PITCH); 2307 PUT32(sc, AVIVO_D2GRPH_PRIMARY_SURFACE_ADDRESS, 0); 2308 } 2309 return; 2310 } 2311 2312 /* blank the display while we switch modes */ 2313 //radeonfb_blank(dp, 1); 2314 2315 #if 0 2316 SET32(sc, RADEON_CRTC_EXT_CNTL, 2317 RADEON_CRTC_VSYNC_DIS | RADEON_CRTC_HSYNC_DIS | 2318 RADEON_CRTC_DISPLAY_DIS /* | RADEON_CRTC_DISP_REQ_EN_B */); 2319 #endif 2320 2321 /* these registers might get in the way... */ 2322 PUT32(sc, RADEON_OVR_CLR, 0); 2323 PUT32(sc, RADEON_OVR_WID_LEFT_RIGHT, 0); 2324 PUT32(sc, RADEON_OVR_WID_TOP_BOTTOM, 0); 2325 PUT32(sc, RADEON_OV0_SCALE_CNTL, 0); 2326 PUT32(sc, RADEON_SUBPIC_CNTL, 0); 2327 PUT32(sc, RADEON_VIPH_CONTROL, 0); 2328 PUT32(sc, RADEON_I2C_CNTL_1, 0); 2329 PUT32(sc, RADEON_GEN_INT_CNTL, 0); 2330 PUT32(sc, RADEON_CAP0_TRIG_CNTL, 0); 2331 PUT32(sc, RADEON_CAP1_TRIG_CNTL, 0); 2332 2333 for (i = 0; i < dp->rd_ncrtcs; i++) 2334 radeonfb_setcrtc(dp, i); 2335 2336 #if 0 2337 /* 2338 * DVO chip voodoo from xf86-video-radeon 2339 * apparently this is needed for some powerbooks with DVI outputs 2340 */ 2341 2342 uint8_t data[5][2] = {{0x8, 0x030}, {0x9, 0}, {0xa, 0x90}, {0xc, 0x89}, {0x8, 0x3b}}; 2343 int n = 0; 2344 iic_acquire_bus(&sc->sc_i2c[0].ric_controller, 0); 2345 for (i = 0; i < 5; i++) 2346 n += iic_exec(&sc->sc_i2c[0].ric_controller, I2C_OP_WRITE, 0x38, data[i], 2, NULL, 0, 0); 2347 iic_release_bus(&sc->sc_i2c[0].ric_controller, 0); 2348 printf("n = %d\n", n); 2349 #endif 2350 2351 /* activate the display */ 2352 radeonfb_blank(dp, 0); 2353 } 2354 2355 void 2356 radeonfb_setcrtc(struct radeonfb_display *dp, int index) 2357 { 2358 int crtc, flags = 0; 2359 struct videomode *mode; 2360 struct radeonfb_softc *sc; 2361 struct radeonfb_crtc *cp; 2362 uint32_t v, hd, vd; 2363 uint32_t gencntl; 2364 uint32_t htotaldisp; 2365 uint32_t hsyncstrt; 2366 uint32_t vtotaldisp; 2367 uint32_t vsyncstrt; 2368 uint32_t fphsyncstrt; 2369 uint32_t fpvsyncstrt; 2370 uint32_t fphtotaldisp; 2371 uint32_t fpvtotaldisp; 2372 uint32_t pitch; 2373 2374 sc = dp->rd_softc; 2375 2376 if ((sc->sc_ports[index].rp_tmds_type == RADEON_TMDS_INT) || 2377 (sc->sc_ports[index].rp_tmds_type == RADEON_TMDS_EXT)) { 2378 flags |= NO_ODD_FBDIV; 2379 } 2380 2381 cp = &dp->rd_crtcs[index]; 2382 crtc = cp->rc_number; 2383 mode = &cp->rc_videomode; 2384 2385 #if 1 2386 pitch = dp->rd_stride / dp->rd_bpp; 2387 #else 2388 pitch = (((sc->sc_maxx * sc->sc_maxbpp) + ((sc->sc_maxbpp * 8) - 1)) / 2389 (sc->sc_maxbpp * 8)); 2390 #endif 2391 switch (crtc) { 2392 case 0: 2393 gencntl = RADEON_CRTC_GEN_CNTL; 2394 htotaldisp = RADEON_CRTC_H_TOTAL_DISP; 2395 hsyncstrt = RADEON_CRTC_H_SYNC_STRT_WID; 2396 vtotaldisp = RADEON_CRTC_V_TOTAL_DISP; 2397 vsyncstrt = RADEON_CRTC_V_SYNC_STRT_WID; 2398 /* should probably leave those alone on non-LVDS */ 2399 fpvsyncstrt = RADEON_FP_V_SYNC_STRT_WID; 2400 fphsyncstrt = RADEON_FP_H_SYNC_STRT_WID; 2401 fpvtotaldisp = RADEON_FP_CRTC_V_TOTAL_DISP; 2402 fphtotaldisp = RADEON_FP_CRTC_H_TOTAL_DISP; 2403 break; 2404 case 1: 2405 gencntl = RADEON_CRTC2_GEN_CNTL; 2406 htotaldisp = RADEON_CRTC2_H_TOTAL_DISP; 2407 hsyncstrt = RADEON_CRTC2_H_SYNC_STRT_WID; 2408 vtotaldisp = RADEON_CRTC2_V_TOTAL_DISP; 2409 vsyncstrt = RADEON_CRTC2_V_SYNC_STRT_WID; 2410 fpvsyncstrt = RADEON_FP_V2_SYNC_STRT_WID; 2411 fphsyncstrt = RADEON_FP_H2_SYNC_STRT_WID; 2412 /* XXX these registers don't seem to exist */ 2413 fpvtotaldisp = 0;//RADEON_FP_CRTC2_V_TOTAL_DISP; 2414 fphtotaldisp = 0;//RADEON_FP_CRTC2_H_TOTAL_DISP; 2415 break; 2416 default: 2417 panic("Bad CRTC!"); 2418 break; 2419 } 2420 2421 /* 2422 * CRTC_GEN_CNTL - depth, accelerator mode, etc. 2423 */ 2424 /* only bother with 32bpp and 8bpp */ 2425 v = dp->rd_format << RADEON_CRTC_PIX_WIDTH_SHIFT; 2426 2427 if (crtc == 1) { 2428 v |= RADEON_CRTC2_CRT2_ON | RADEON_CRTC2_EN; 2429 } else { 2430 v |= RADEON_CRTC_EXT_DISP_EN | RADEON_CRTC_EN; 2431 } 2432 2433 if (mode->flags & VID_DBLSCAN) 2434 v |= RADEON_CRTC2_DBL_SCAN_EN; 2435 2436 if (mode->flags & VID_INTERLACE) 2437 v |= RADEON_CRTC2_INTERLACE_EN; 2438 2439 if (mode->flags & VID_CSYNC) { 2440 v |= RADEON_CRTC2_CSYNC_EN; 2441 if (crtc == 1) 2442 v |= RADEON_CRTC2_VSYNC_TRISTAT; 2443 } 2444 2445 PUT32(sc, gencntl, v); 2446 DPRINTF(("CRTC%s_GEN_CNTL = %08x\n", crtc ? "2" : "", v)); 2447 2448 /* 2449 * CRTC_EXT_CNTL - preserve disable flags, set ATI linear and EXT_CNT 2450 */ 2451 v = GET32(sc, RADEON_CRTC_EXT_CNTL); 2452 if (crtc == 0) { 2453 v &= (RADEON_CRTC_VSYNC_DIS | RADEON_CRTC_HSYNC_DIS | 2454 RADEON_CRTC_DISPLAY_DIS); 2455 v |= RADEON_XCRT_CNT_EN | RADEON_VGA_ATI_LINEAR; 2456 if (mode->flags & VID_CSYNC) 2457 v |= RADEON_CRTC_VSYNC_TRISTAT; 2458 } 2459 /* unconditional turn on CRT, in case first CRTC is DFP */ 2460 v |= RADEON_CRTC_CRT_ON; 2461 PUT32(sc, RADEON_CRTC_EXT_CNTL, v); 2462 PRINTREG(RADEON_CRTC_EXT_CNTL); 2463 2464 hd = ((GET32(sc, htotaldisp) >> 16) + 1) * 8; 2465 vd = (GET32(sc, vtotaldisp) >> 16) + 1; 2466 DPRINTF(("res %d x %d\n", hd, vd)); 2467 2468 if ((hd != mode->hdisplay) || (vd != mode->vdisplay)) { 2469 2470 /* 2471 * H_TOTAL_DISP 2472 */ 2473 v = ((mode->hdisplay / 8) - 1) << 16; 2474 v |= (mode->htotal / 8) - 1; 2475 PRINTREG(RADEON_CRTC_H_TOTAL_DISP); 2476 PUT32(sc, htotaldisp, v); 2477 DPRINTF(("CRTC%s_H_TOTAL_DISP = %08x\n", crtc ? "2" : "", v)); 2478 if (fphtotaldisp) { 2479 PRINTREG(RADEON_FP_CRTC_H_TOTAL_DISP); 2480 PUT32(sc, fphtotaldisp, v); 2481 DPRINTF(("FP_H%s_TOTAL_DISP = %08x\n", crtc ? "2" : "", v)); 2482 } 2483 /* 2484 * H_SYNC_STRT_WID 2485 */ 2486 v = (((mode->hsync_end - mode->hsync_start) / 8) << 16); 2487 v |= (mode->hsync_start - 8); /* match xf86-video-radeon */ 2488 if (mode->flags & VID_NHSYNC) 2489 v |= RADEON_CRTC_H_SYNC_POL; 2490 PUT32(sc, hsyncstrt, v); 2491 DPRINTF(("CRTC%s_H_SYNC_STRT_WID = %08x\n", crtc ? "2" : "", v)); 2492 if (fphsyncstrt) { 2493 PUT32(sc, fphsyncstrt, v); 2494 DPRINTF(("FP_H%s_SYNC_STRT_WID = %08x\n", crtc ? "2" : "", v)); 2495 } 2496 2497 /* 2498 * V_TOTAL_DISP 2499 */ 2500 v = ((mode->vdisplay - 1) << 16); 2501 v |= (mode->vtotal - 1); 2502 PUT32(sc, vtotaldisp, v); 2503 DPRINTF(("CRTC%s_V_TOTAL_DISP = %08x\n", crtc ? "2" : "", v)); 2504 if (fpvtotaldisp) { 2505 PUT32(sc, fpvtotaldisp, v); 2506 DPRINTF(("FP_V%s_TOTAL_DISP = %08x\n", crtc ? "2" : "", v)); 2507 } 2508 2509 /* 2510 * V_SYNC_STRT_WID 2511 */ 2512 v = ((mode->vsync_end - mode->vsync_start) << 16); 2513 v |= (mode->vsync_start - 1); 2514 if (mode->flags & VID_NVSYNC) 2515 v |= RADEON_CRTC_V_SYNC_POL; 2516 PUT32(sc, vsyncstrt, v); 2517 DPRINTF(("CRTC%s_V_SYNC_STRT_WID = %08x\n", crtc ? "2" : "", v)); 2518 if (fpvsyncstrt) { 2519 PUT32(sc, fpvsyncstrt, v); 2520 DPRINTF(("FP_V%s_SYNC_STRT_WID = %08x\n", crtc ? "2" : "", v)); 2521 } 2522 } 2523 radeonfb_program_vclk(sc, mode->dot_clock, crtc, flags); 2524 2525 switch (crtc) { 2526 case 0: 2527 PUT32(sc, RADEON_CRTC_OFFSET, 0); 2528 PUT32(sc, RADEON_CRTC_OFFSET_CNTL, 0); 2529 PUT32(sc, RADEON_CRTC_PITCH, pitch); 2530 CLR32(sc, RADEON_DISP_MERGE_CNTL, RADEON_DISP_RGB_OFFSET_EN); 2531 2532 CLR32(sc, RADEON_CRTC_EXT_CNTL, 2533 RADEON_CRTC_VSYNC_DIS | RADEON_CRTC_HSYNC_DIS | 2534 RADEON_CRTC_DISPLAY_DIS /* | RADEON_CRTC_DISP_REQ_EN_B */); 2535 CLR32(sc, RADEON_CRTC_GEN_CNTL, RADEON_CRTC_DISP_REQ_EN_B); 2536 PRINTREG(RADEON_CRTC_EXT_CNTL); 2537 PRINTREG(RADEON_CRTC_GEN_CNTL); 2538 PRINTREG(RADEON_CLOCK_CNTL_INDEX); 2539 break; 2540 2541 case 1: 2542 PUT32(sc, RADEON_CRTC2_OFFSET, 0); 2543 PUT32(sc, RADEON_CRTC2_OFFSET_CNTL, 0); 2544 PUT32(sc, RADEON_CRTC2_PITCH, pitch); 2545 CLR32(sc, RADEON_DISP2_MERGE_CNTL, RADEON_DISP2_RGB_OFFSET_EN); 2546 CLR32(sc, RADEON_CRTC2_GEN_CNTL, 2547 RADEON_CRTC2_VSYNC_DIS | 2548 RADEON_CRTC2_HSYNC_DIS | 2549 RADEON_CRTC2_DISP_DIS | RADEON_CRTC2_DISP_REQ_EN_B); 2550 PRINTREG(RADEON_CRTC2_GEN_CNTL); 2551 break; 2552 } 2553 } 2554 2555 int 2556 radeonfb_isblank(struct radeonfb_display *dp) 2557 { 2558 struct radeonfb_softc *sc = dp->rd_softc; 2559 uint32_t reg, mask; 2560 2561 if(!dp->rd_softc->sc_mapped) 2562 return 1; 2563 2564 if (IS_AVIVO(sc)) { 2565 reg = GET32(sc, AVIVO_D1CRTC_CONTROL); 2566 return ((reg & AVIVO_CRTC_EN) == 0); 2567 } 2568 2569 if (dp->rd_crtcs[0].rc_number) { 2570 reg = RADEON_CRTC2_GEN_CNTL; 2571 mask = RADEON_CRTC2_DISP_DIS; 2572 } else { 2573 reg = RADEON_CRTC_EXT_CNTL; 2574 mask = RADEON_CRTC_DISPLAY_DIS; 2575 } 2576 return ((GET32(dp->rd_softc, reg) & mask) ? 1 : 0); 2577 } 2578 2579 void 2580 radeonfb_blank(struct radeonfb_display *dp, int blank) 2581 { 2582 struct radeonfb_softc *sc = dp->rd_softc; 2583 uint32_t reg, mask; 2584 uint32_t fpreg, fpval; 2585 int i; 2586 2587 2588 if (!sc->sc_mapped) 2589 return; 2590 2591 if(IS_AVIVO(sc)) { 2592 2593 /* 2594 * XXX 2595 * I don't know how to turn the sunc outputs off for DPMS 2596 * power control, so for now just turn the entire CRTC off 2597 */ 2598 if (blank) { 2599 CLR32(sc, AVIVO_D1CRTC_CONTROL, AVIVO_CRTC_EN); 2600 CLR32(sc, AVIVO_D2CRTC_CONTROL, AVIVO_CRTC_EN); 2601 } else { 2602 SET32(sc, AVIVO_D1CRTC_CONTROL, AVIVO_CRTC_EN); 2603 SET32(sc, AVIVO_D2CRTC_CONTROL, AVIVO_CRTC_EN); 2604 } 2605 return; 2606 } 2607 /* non-AVIVO case */ 2608 for (i = 0; i < dp->rd_ncrtcs; i++) { 2609 2610 if (dp->rd_crtcs[i].rc_number) { 2611 reg = RADEON_CRTC2_GEN_CNTL; 2612 mask = RADEON_CRTC2_DISP_DIS; 2613 fpreg = RADEON_FP2_GEN_CNTL; 2614 fpval = RADEON_FP2_ON; 2615 } else { 2616 reg = RADEON_CRTC_EXT_CNTL; 2617 mask = RADEON_CRTC_DISPLAY_DIS; 2618 fpreg = RADEON_FP_GEN_CNTL; 2619 fpval = RADEON_FP_FPON; 2620 } 2621 2622 if (blank) { 2623 SET32(sc, reg, mask); 2624 CLR32(sc, fpreg, fpval); 2625 } else { 2626 CLR32(sc, reg, mask); 2627 SET32(sc, fpreg, fpval); 2628 } 2629 } 2630 PRINTREG(RADEON_FP_GEN_CNTL); 2631 PRINTREG(RADEON_FP2_GEN_CNTL); 2632 } 2633 2634 void 2635 radeonfb_init_screen(void *cookie, struct vcons_screen *scr, int existing, 2636 long *defattr) 2637 { 2638 struct radeonfb_display *dp = cookie; 2639 struct rasops_info *ri = &scr->scr_ri; 2640 2641 /* initialize font subsystem */ 2642 wsfont_init(); 2643 2644 scr->scr_flags |= VCONS_LOADFONT; 2645 2646 DPRINTF(("init screen called, existing %d\n", existing)); 2647 2648 ri->ri_depth = dp->rd_bpp; 2649 ri->ri_width = dp->rd_virtx; 2650 ri->ri_height = dp->rd_virty; 2651 ri->ri_stride = dp->rd_stride; 2652 ri->ri_flg = RI_CENTER; 2653 switch (ri->ri_depth) { 2654 case 8: 2655 ri->ri_flg |= RI_ENABLE_ALPHA | RI_8BIT_IS_RGB | RI_PREFER_ALPHA; 2656 break; 2657 case 32: 2658 ri->ri_flg |= RI_ENABLE_ALPHA | RI_PREFER_ALPHA; 2659 /* we run radeons in RGB even on SPARC hardware */ 2660 ri->ri_rnum = 8; 2661 ri->ri_gnum = 8; 2662 ri->ri_bnum = 8; 2663 ri->ri_rpos = 16; 2664 ri->ri_gpos = 8; 2665 ri->ri_bpos = 0; 2666 break; 2667 } 2668 2669 ri->ri_bits = (void *)dp->rd_fbptr; 2670 2671 #ifdef VCONS_DRAW_INTR 2672 scr->scr_flags |= VCONS_DONT_READ; 2673 #endif 2674 2675 if (existing) { 2676 ri->ri_flg |= RI_CLEAR; 2677 2678 /* start a modeswitch now */ 2679 //radeonfb_modeswitch(dp); 2680 } 2681 2682 /* 2683 * XXX: font selection should be based on properties, with some 2684 * normal/reasonable default. 2685 */ 2686 2687 /* initialize and look for an initial font */ 2688 rasops_init(ri, 0, 0); 2689 ri->ri_caps = WSSCREEN_UNDERLINE | WSSCREEN_HILIT | 2690 WSSCREEN_WSCOLORS | WSSCREEN_REVERSE | WSSCREEN_RESIZE; 2691 2692 rasops_reconfig(ri, dp->rd_virty / ri->ri_font->fontheight, 2693 dp->rd_virtx / ri->ri_font->fontwidth); 2694 2695 /* enable acceleration */ 2696 dp->rd_putchar = ri->ri_ops.putchar; 2697 ri->ri_ops.copyrows = radeonfb_copyrows; 2698 ri->ri_ops.copycols = radeonfb_copycols; 2699 ri->ri_ops.eraserows = radeonfb_eraserows; 2700 ri->ri_ops.erasecols = radeonfb_erasecols; 2701 /* pick a putchar method based on font and Radeon model */ 2702 if (ri->ri_font->stride < ri->ri_font->fontwidth) { 2703 /* got a bitmap font */ 2704 #if !defined(RADEONFB_ALWAYS_ACCEL_PUTCHAR) 2705 if (IS_R300(dp->rd_softc) && 0) { 2706 /* 2707 * radeonfb_putchar() doesn't work right on some R3xx 2708 * so we use software drawing here, the wrapper just 2709 * makes sure the engine is idle before scribbling 2710 * into vram 2711 */ 2712 ri->ri_ops.putchar = radeonfb_putchar_wrapper; 2713 } else 2714 #endif 2715 ri->ri_ops.putchar = radeonfb_putchar; 2716 } else { 2717 /* got an alpha font */ 2718 switch(ri->ri_depth) { 2719 case 32: 2720 ri->ri_ops.putchar = radeonfb_putchar_aa32; 2721 break; 2722 case 8: 2723 ri->ri_ops.putchar = radeonfb_putchar_aa8; 2724 break; 2725 default: 2726 /* XXX this should never happen */ 2727 panic("%s: depth is not 8 or 32 but we got an" \ 2728 " alpha font?!", __func__); 2729 } 2730 } 2731 ri->ri_ops.cursor = radeonfb_cursor; 2732 } 2733 2734 static uint32_t 2735 radeonfb_avivo_INMC(struct radeonfb_softc *sc, uint32_t addr) 2736 { 2737 uint32_t data; 2738 2739 PUT32(sc, AVIVO_MC_INDEX, (addr & 0xff) | 0x7f0000); 2740 (void)GET32(sc, AVIVO_MC_INDEX); 2741 data = GET32(sc, AVIVO_MC_DATA); 2742 PUT32(sc, AVIVO_MC_INDEX, 0); 2743 (void)GET32(sc, AVIVO_MC_INDEX); 2744 return data; 2745 } 2746 2747 static void 2748 radeonfb_avivo_OUTMC(struct radeonfb_softc *sc, uint32_t addr, uint32_t data) 2749 { 2750 2751 PUT32(sc, AVIVO_MC_INDEX, (addr & 0xff) | 0x7f0000); 2752 (void)GET32(sc, AVIVO_MC_INDEX); 2753 PUT32(sc, AVIVO_MC_DATA, data); 2754 PUT32(sc, AVIVO_MC_INDEX, 0); 2755 (void)GET32(sc, AVIVO_MC_INDEX); 2756 } 2757 2758 void 2759 radeonfb_set_fbloc(struct radeonfb_softc *sc) 2760 { 2761 uint32_t gen = 0, ext = 0, gen2 = 0; 2762 uint32_t agploc, aperbase, apersize, mcfbloc; 2763 2764 2765 if (IS_AVIVO(sc)) { 2766 agploc = radeonfb_avivo_INMC(sc, R520_MC_AGP_LOCATION); 2767 } else { 2768 gen = GET32(sc, RADEON_CRTC_GEN_CNTL); 2769 /* XXX */ 2770 ext = GET32(sc, RADEON_CRTC_EXT_CNTL) & ~RADEON_CRTC_DISPLAY_DIS; 2771 agploc = GET32(sc, RADEON_MC_AGP_LOCATION); 2772 PUT32(sc, RADEON_CRTC_GEN_CNTL, gen | RADEON_CRTC_DISP_REQ_EN_B); 2773 PUT32(sc, RADEON_CRTC_EXT_CNTL, ext | RADEON_CRTC_DISPLAY_DIS); 2774 #if 0 2775 PUT32(sc, RADEON_CRTC_GEN_CNTL, gen | RADEON_CRTC_DISPLAY_DIS); 2776 PUT32(sc, RADEON_CRTC_EXT_CNTL, ext | RADEON_CRTC_DISP_REQ_EN_B); 2777 #endif 2778 2779 if (HAS_CRTC2(sc)) { 2780 gen2 = GET32(sc, RADEON_CRTC2_GEN_CNTL); 2781 PUT32(sc, RADEON_CRTC2_GEN_CNTL, 2782 gen2 | RADEON_CRTC2_DISP_REQ_EN_B); 2783 } 2784 2785 delay(100000); 2786 } 2787 2788 aperbase = GET32(sc, RADEON_CONFIG_APER_0_BASE); 2789 apersize = GET32(sc, RADEON_CONFIG_APER_SIZE); 2790 2791 2792 mcfbloc = (aperbase >> 16) | 2793 ((aperbase + (apersize - 1)) & 0xffff0000); 2794 2795 sc->sc_aperbase = (mcfbloc & 0xffff) << 16; 2796 sc->sc_memsz = apersize; 2797 DPRINTF(("aperbase = %08x\n", aperbase)); 2798 2799 if (((agploc & 0xffff) << 16) != 2800 ((mcfbloc & 0xffff0000U) + 0x10000)) { 2801 agploc = mcfbloc & 0xffff0000U; 2802 agploc |= ((agploc + 0x10000) >> 16); 2803 } 2804 2805 PUT32(sc, RADEON_HOST_PATH_CNTL, 0); 2806 2807 if (IS_AVIVO(sc)) { 2808 radeonfb_avivo_OUTMC(sc, R520_MC_FB_LOCATION, mcfbloc); 2809 radeonfb_avivo_OUTMC(sc, R520_MC_AGP_LOCATION, agploc); 2810 PRINTREG(AVIVO_HDP_FB_LOCATION); 2811 DPRINTF((" FB loc %08x\n", radeonfb_avivo_INMC(sc, R520_MC_FB_LOCATION))); 2812 DPRINTF(("AGP loc %08x\n", radeonfb_avivo_INMC(sc, R520_MC_AGP_LOCATION))); 2813 } else { 2814 PUT32(sc, RADEON_MC_FB_LOCATION, mcfbloc); 2815 PUT32(sc, RADEON_MC_AGP_LOCATION, agploc); 2816 PRINTREG(RADEON_MC_FB_LOCATION); 2817 PRINTREG(RADEON_MC_AGP_LOCATION); 2818 2819 PUT32(sc, RADEON_DISPLAY_BASE_ADDR, sc->sc_aperbase); 2820 2821 if (HAS_CRTC2(sc)) 2822 PUT32(sc, RADEON_DISPLAY2_BASE_ADDR, sc->sc_aperbase); 2823 2824 PUT32(sc, RADEON_OV0_BASE_ADDR, sc->sc_aperbase); 2825 delay(100000); 2826 2827 PUT32(sc, RADEON_CRTC_GEN_CNTL, gen); 2828 PUT32(sc, RADEON_CRTC_EXT_CNTL, ext); 2829 2830 if (HAS_CRTC2(sc)) 2831 PUT32(sc, RADEON_CRTC2_GEN_CNTL, gen2); 2832 } 2833 #if 0 2834 /* XXX: what is this AGP garbage? :-) */ 2835 PUT32(sc, RADEON_AGP_CNTL, 0x00100000); 2836 #endif 2837 } 2838 2839 void 2840 radeonfb_init_misc(struct radeonfb_softc *sc) 2841 { 2842 PUT32(sc, RADEON_BUS_CNTL, 2843 RADEON_BUS_MASTER_DIS | 2844 RADEON_BUS_PREFETCH_MODE_ACT | 2845 RADEON_BUS_PCI_READ_RETRY_EN | 2846 RADEON_BUS_PCI_WRT_RETRY_EN | 2847 (3 << RADEON_BUS_RETRY_WS_SHIFT) | 2848 RADEON_BUS_MSTR_RD_MULT | 2849 RADEON_BUS_MSTR_RD_LINE | 2850 RADEON_BUS_RD_DISCARD_EN | 2851 RADEON_BUS_MSTR_DISCONNECT_EN | 2852 RADEON_BUS_READ_BURST); 2853 2854 PUT32(sc, RADEON_BUS_CNTL1, 0xf0); 2855 /* PUT32(sc, RADEON_SEPROM_CNTL1, 0x09ff0000); */ 2856 PUT32(sc, RADEON_FCP_CNTL, RADEON_FCP0_SRC_GND); 2857 PUT32(sc, RADEON_RBBM_CNTL, 2858 (3 << RADEON_RB_SETTLE_SHIFT) | 2859 (4 << RADEON_ABORTCLKS_HI_SHIFT) | 2860 (4 << RADEON_ABORTCLKS_CP_SHIFT) | 2861 (4 << RADEON_ABORTCLKS_CFIFO_SHIFT)); 2862 2863 /* XXX: figure out what these mean! */ 2864 PUT32(sc, RADEON_AGP_CNTL, 0x00100000); 2865 PUT32(sc, RADEON_HOST_PATH_CNTL, 0); 2866 #if 0 2867 PUT32(sc, RADEON_DISP_MISC_CNTL, 0x5bb00400); 2868 #endif 2869 2870 PUT32(sc, RADEON_GEN_INT_CNTL, 0); 2871 PUT32(sc, RADEON_GEN_INT_STATUS, GET32(sc, RADEON_GEN_INT_STATUS)); 2872 } 2873 2874 static void 2875 radeonfb_putpal(struct radeonfb_display *dp, int idx, int r, int g, int b) 2876 { 2877 struct radeonfb_softc *sc = dp->rd_softc; 2878 int crtc, cc; 2879 uint32_t vclk; 2880 2881 if (IS_AVIVO(sc)) { 2882 for (cc = 0; cc < dp->rd_ncrtcs; cc++) { 2883 crtc = dp->rd_crtcs[cc].rc_number; 2884 2885 if (crtc) 2886 PUT32(sc, AVIVO_DC_LUT_RW_SELECT, 1); 2887 else 2888 PUT32(sc, AVIVO_DC_LUT_RW_SELECT, 0); 2889 2890 PUT32(sc, AVIVO_DC_LUT_RW_INDEX, idx); 2891 PUT32(sc, AVIVO_DC_LUT_30_COLOR, 2892 (r << 22) | (g << 12) | (b << 2)); 2893 } 2894 2895 } else { 2896 vclk = GETPLL(sc, RADEON_VCLK_ECP_CNTL); 2897 PUTPLL(sc, RADEON_VCLK_ECP_CNTL, 2898 vclk & ~RADEON_PIXCLK_DAC_ALWAYS_ONb); 2899 2900 /* init the palette for every CRTC used by this display */ 2901 for (cc = 0; cc < dp->rd_ncrtcs; cc++) { 2902 crtc = dp->rd_crtcs[cc].rc_number; 2903 2904 if (crtc) 2905 SET32(sc, RADEON_DAC_CNTL2, 2906 RADEON_DAC2_PALETTE_ACC_CTL); 2907 else 2908 CLR32(sc, RADEON_DAC_CNTL2, 2909 RADEON_DAC2_PALETTE_ACC_CTL); 2910 2911 PUT32(sc, RADEON_PALETTE_INDEX, idx); 2912 PUT32(sc, RADEON_PALETTE_30_DATA, 2913 (r << 22) | (g << 12) | (b << 2)); 2914 } 2915 2916 PUTPLL(sc, RADEON_VCLK_ECP_CNTL, vclk); 2917 } 2918 } 2919 2920 /* 2921 * This loads a linear color map for true color. 2922 */ 2923 void 2924 radeonfb_init_palette(struct radeonfb_display *dp) 2925 { 2926 int i; 2927 2928 #define DAC_WIDTH ((1 << 10) - 1) 2929 #define CLUT_WIDTH ((1 << 8) - 1) 2930 #define CLUT_COLOR(i) ((i * DAC_WIDTH * 2 / CLUT_WIDTH + 1) / 2) 2931 2932 if (dp->rd_bpp == 8) { 2933 2934 /* R3G3B2 palette */ 2935 uint32_t tmp, r, g, b; 2936 2937 for (i = 0; i <= CLUT_WIDTH; ++i) { 2938 tmp = i & 0xe0; 2939 2940 /* 2941 * replicate bits so 0xe0 maps to a red value of 0xff 2942 * in order to make white look actually white 2943 */ 2944 tmp |= (tmp >> 3) | (tmp >> 6); 2945 r = tmp; 2946 2947 tmp = (i & 0x1c) << 3; 2948 tmp |= (tmp >> 3) | (tmp >> 6); 2949 g = tmp; 2950 2951 tmp = (i & 0x03) << 6; 2952 tmp |= tmp >> 2; 2953 tmp |= tmp >> 4; 2954 b = tmp; 2955 2956 dp->rd_cmap_red[i] = r; 2957 dp->rd_cmap_green[i] = g; 2958 dp->rd_cmap_blue[i] = b; 2959 radeonfb_putpal(dp, i, r, g, b); 2960 } 2961 } else { 2962 /* linear ramp */ 2963 for (i = 0; i <= CLUT_WIDTH; ++i) { 2964 radeonfb_putpal(dp, i, i, i, i); 2965 } 2966 } 2967 } 2968 2969 static int 2970 radeonfb_putcmap(struct radeonfb_display *dp, struct wsdisplay_cmap *cm) 2971 { 2972 u_char *r, *g, *b; 2973 u_int index = cm->index; 2974 u_int count = cm->count; 2975 int i, error; 2976 u_char rbuf[256], gbuf[256], bbuf[256]; 2977 2978 #ifdef GENFB_DEBUG 2979 aprint_debug("putcmap: %d %d\n",index, count); 2980 #endif 2981 if (index >= 256 || count > 256 - index) 2982 return EINVAL; 2983 error = copyin(cm->red, &rbuf[index], count); 2984 if (error) 2985 return error; 2986 error = copyin(cm->green, &gbuf[index], count); 2987 if (error) 2988 return error; 2989 error = copyin(cm->blue, &bbuf[index], count); 2990 if (error) 2991 return error; 2992 2993 memcpy(&dp->rd_cmap_red[index], &rbuf[index], count); 2994 memcpy(&dp->rd_cmap_green[index], &gbuf[index], count); 2995 memcpy(&dp->rd_cmap_blue[index], &bbuf[index], count); 2996 2997 r = &dp->rd_cmap_red[index]; 2998 g = &dp->rd_cmap_green[index]; 2999 b = &dp->rd_cmap_blue[index]; 3000 3001 for (i = 0; i < count; i++) { 3002 radeonfb_putpal(dp, index, *r, *g, *b); 3003 index++; 3004 r++, g++, b++; 3005 } 3006 return 0; 3007 } 3008 3009 static int 3010 radeonfb_getcmap(struct radeonfb_display *dp, struct wsdisplay_cmap *cm) 3011 { 3012 u_int index = cm->index; 3013 u_int count = cm->count; 3014 int error; 3015 3016 if (index >= 256 || count > 256 - index) 3017 return EINVAL; 3018 3019 error = copyout(&dp->rd_cmap_red[index], cm->red, count); 3020 if (error) 3021 return error; 3022 error = copyout(&dp->rd_cmap_green[index], cm->green, count); 3023 if (error) 3024 return error; 3025 error = copyout(&dp->rd_cmap_blue[index], cm->blue, count); 3026 if (error) 3027 return error; 3028 3029 return 0; 3030 } 3031 3032 /* 3033 * Bugs in some R300 hardware requires this when accessing CLOCK_CNTL_INDEX. 3034 */ 3035 void 3036 radeonfb_r300cg_workaround(struct radeonfb_softc *sc) 3037 { 3038 uint32_t tmp, save; 3039 3040 save = GET32(sc, RADEON_CLOCK_CNTL_INDEX); 3041 tmp = save & ~(0x3f | RADEON_PLL_WR_EN); 3042 PUT32(sc, RADEON_CLOCK_CNTL_INDEX, tmp); 3043 tmp = GET32(sc, RADEON_CLOCK_CNTL_DATA); 3044 PUT32(sc, RADEON_CLOCK_CNTL_INDEX, save); 3045 } 3046 3047 /* 3048 * Acceleration entry points. 3049 */ 3050 3051 /* this one draws characters using bitmap fonts */ 3052 static void 3053 radeonfb_putchar(void *cookie, int row, int col, u_int c, long attr) 3054 { 3055 struct rasops_info *ri = cookie; 3056 struct vcons_screen *scr = ri->ri_hw; 3057 struct radeonfb_display *dp = scr->scr_cookie; 3058 struct radeonfb_softc *sc = dp->rd_softc; 3059 struct wsdisplay_font *font = PICK_FONT(ri, c); 3060 uint32_t w, h; 3061 int xd, yd, offset, i; 3062 uint32_t bg, fg, gmc; 3063 uint32_t reg; 3064 uint8_t *data8; 3065 uint16_t *data16; 3066 uint32_t *data32; 3067 void *data; 3068 3069 if (dp->rd_wsmode != WSDISPLAYIO_MODE_EMUL) 3070 return; 3071 3072 if (!CHAR_IN_FONT(c, font)) 3073 return; 3074 3075 w = font->fontwidth; 3076 h = font->fontheight; 3077 3078 bg = ri->ri_devcmap[(attr >> 16) & 0xf]; 3079 fg = ri->ri_devcmap[(attr >> 24) & 0xf]; 3080 3081 xd = ri->ri_xorigin + col * w; 3082 yd = ri->ri_yorigin + row * h; 3083 3084 if (c == 0x20) { 3085 radeonfb_rectfill(dp, xd, yd, w, h, bg); 3086 return; 3087 } 3088 data = WSFONT_GLYPH(c, font); 3089 3090 gmc = dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT; 3091 3092 radeonfb_wait_fifo(sc, 9); 3093 3094 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 3095 RADEON_GMC_BRUSH_NONE | 3096 RADEON_GMC_SRC_DATATYPE_MONO_FG_BG | 3097 RADEON_GMC_DST_CLIPPING | 3098 RADEON_ROP3_S | 3099 RADEON_DP_SRC_SOURCE_HOST_DATA | 3100 RADEON_GMC_CLR_CMP_CNTL_DIS | 3101 RADEON_GMC_WR_MSK_DIS | 3102 gmc); 3103 3104 PUT32(sc, RADEON_SC_LEFT, xd); 3105 PUT32(sc, RADEON_SC_RIGHT, xd + w); 3106 PUT32(sc, RADEON_DP_SRC_FRGD_CLR, fg); 3107 PUT32(sc, RADEON_DP_SRC_BKGD_CLR, bg); 3108 PUT32(sc, RADEON_DP_CNTL, 3109 RADEON_DST_X_LEFT_TO_RIGHT | 3110 RADEON_DST_Y_TOP_TO_BOTTOM); 3111 3112 PUT32(sc, RADEON_SRC_X_Y, 0); 3113 offset = 32 - (font->stride << 3); 3114 PUT32(sc, RADEON_DST_X_Y, ((xd - offset) << 16) | yd); 3115 PUT32(sc, RADEON_DST_WIDTH_HEIGHT, (32 << 16) | h); 3116 3117 radeonfb_wait_fifo(sc, h); 3118 switch (font->stride) { 3119 case 1: { 3120 data8 = data; 3121 for (i = 0; i < h; i++) { 3122 reg = *data8; 3123 #if BYTE_ORDER == LITTLE_ENDIAN 3124 reg = reg << 24; 3125 #endif 3126 bus_space_write_stream_4(sc->sc_regt, 3127 sc->sc_regh, RADEON_HOST_DATA0, reg); 3128 data8++; 3129 } 3130 break; 3131 } 3132 case 2: { 3133 data16 = data; 3134 for (i = 0; i < h; i++) { 3135 reg = *data16; 3136 #if BYTE_ORDER == LITTLE_ENDIAN 3137 reg = reg << 16; 3138 #endif 3139 bus_space_write_stream_4(sc->sc_regt, 3140 sc->sc_regh, RADEON_HOST_DATA0, reg); 3141 data16++; 3142 } 3143 break; 3144 } 3145 case 4: { 3146 data32 = data; 3147 for (i = 0; i < h; i++) { 3148 reg = *data32; 3149 bus_space_write_stream_4(sc->sc_regt, 3150 sc->sc_regh, RADEON_HOST_DATA0, reg); 3151 data32++; 3152 } 3153 break; 3154 } 3155 } 3156 if (attr & 1) 3157 radeonfb_rectfill(dp, xd, yd + h - 2, w, 1, fg); 3158 } 3159 3160 /* ... while this one is for anti-aliased ones */ 3161 static void 3162 radeonfb_putchar_aa32(void *cookie, int row, int col, u_int c, long attr) 3163 { 3164 struct rasops_info *ri = cookie; 3165 struct vcons_screen *scr = ri->ri_hw; 3166 struct radeonfb_display *dp = scr->scr_cookie; 3167 struct radeonfb_softc *sc = dp->rd_softc; 3168 struct wsdisplay_font *font = PICK_FONT(ri, c); 3169 uint32_t bg, fg, gmc; 3170 uint8_t *data; 3171 int w, h, xd, yd; 3172 int i, r, g, b, aval; 3173 int rf, gf, bf, rb, gb, bb; 3174 uint32_t pixel; 3175 int rv; 3176 3177 if (dp->rd_wsmode != WSDISPLAYIO_MODE_EMUL) 3178 return; 3179 3180 if (!CHAR_IN_FONT(c, font)) 3181 return; 3182 3183 w = font->fontwidth; 3184 h = font->fontheight; 3185 3186 bg = ri->ri_devcmap[(attr >> 16) & 0xf]; 3187 fg = ri->ri_devcmap[(attr >> 24) & 0xf]; 3188 3189 xd = ri->ri_xorigin + col * w; 3190 yd = ri->ri_yorigin + row * h; 3191 3192 if (c == 0x20) { 3193 radeonfb_rectfill(dp, xd, yd, w, h, bg); 3194 if (attr & 1) 3195 radeonfb_rectfill(dp, xd, yd + h - 2, w, 1, fg); 3196 return; 3197 } 3198 rv = glyphcache_try(&dp->rd_gc, c, xd, yd, attr); 3199 if (rv == GC_OK) 3200 return; 3201 3202 data = WSFONT_GLYPH(c, font); 3203 3204 gmc = dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT; 3205 3206 radeonfb_wait_fifo(sc, 5); 3207 3208 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 3209 RADEON_GMC_BRUSH_NONE | 3210 RADEON_GMC_SRC_DATATYPE_COLOR | 3211 RADEON_ROP3_S | 3212 RADEON_DP_SRC_SOURCE_HOST_DATA | 3213 RADEON_GMC_CLR_CMP_CNTL_DIS | 3214 RADEON_GMC_WR_MSK_DIS | 3215 gmc); 3216 3217 PUT32(sc, RADEON_DP_CNTL, 3218 RADEON_DST_X_LEFT_TO_RIGHT | 3219 RADEON_DST_Y_TOP_TO_BOTTOM); 3220 3221 PUT32(sc, RADEON_SRC_X_Y, 0); 3222 PUT32(sc, RADEON_DST_X_Y, (xd << 16) | yd); 3223 PUT32(sc, RADEON_DST_WIDTH_HEIGHT, (w << 16) | h); 3224 3225 rf = (fg >> 16) & 0xff; 3226 rb = (bg >> 16) & 0xff; 3227 gf = (fg >> 8) & 0xff; 3228 gb = (bg >> 8) & 0xff; 3229 bf = fg & 0xff; 3230 bb = bg & 0xff; 3231 3232 /* 3233 * I doubt we can upload data faster than even the slowest Radeon 3234 * could process them, especially when doing the alpha blending stuff 3235 * along the way, so just make sure there's some room in the FIFO and 3236 * then hammer away 3237 * As it turns out we can, so make periodic stops to let the FIFO 3238 * drain. 3239 */ 3240 radeonfb_wait_fifo(sc, 20); 3241 for (i = 0; i < ri->ri_fontscale; i++) { 3242 aval = *data; 3243 data++; 3244 if (aval == 0) { 3245 pixel = bg; 3246 } else if (aval == 255) { 3247 pixel = fg; 3248 } else { 3249 r = aval * rf + (255 - aval) * rb; 3250 g = aval * gf + (255 - aval) * gb; 3251 b = aval * bf + (255 - aval) * bb; 3252 pixel = (r & 0xff00) << 8 | 3253 (g & 0xff00) | 3254 (b & 0xff00) >> 8; 3255 } 3256 if (i & 16) 3257 radeonfb_wait_fifo(sc, 20); 3258 PUT32(sc, RADEON_HOST_DATA0, pixel); 3259 } 3260 if (rv == GC_ADD) { 3261 glyphcache_add(&dp->rd_gc, c, xd, yd); 3262 } else if (attr & 1) 3263 radeonfb_rectfill(dp, xd, yd + h - 2, w, 1, fg); 3264 } 3265 3266 static void 3267 radeonfb_putchar_aa8(void *cookie, int row, int col, u_int c, long attr) 3268 { 3269 struct rasops_info *ri = cookie; 3270 struct vcons_screen *scr = ri->ri_hw; 3271 struct radeonfb_display *dp = scr->scr_cookie; 3272 struct radeonfb_softc *sc = dp->rd_softc; 3273 struct wsdisplay_font *font = PICK_FONT(ri, c); 3274 uint32_t bg, fg, latch = 0, bg8, fg8, pixel, gmc; 3275 int i, x, y, wi, he, r, g, b, aval; 3276 int r1, g1, b1, r0, g0, b0, fgo, bgo; 3277 uint8_t *data8; 3278 int rv, cnt; 3279 3280 if (dp->rd_wsmode != WSDISPLAYIO_MODE_EMUL) 3281 return; 3282 3283 if (!CHAR_IN_FONT(c, font)) 3284 return; 3285 3286 wi = font->fontwidth; 3287 he = font->fontheight; 3288 3289 bg = ri->ri_devcmap[(attr >> 16) & 0xf]; 3290 fg = ri->ri_devcmap[(attr >> 24) & 0xf]; 3291 3292 x = ri->ri_xorigin + col * wi; 3293 y = ri->ri_yorigin + row * he; 3294 3295 if (c == 0x20) { 3296 radeonfb_rectfill(dp, x, y, wi, he, bg); 3297 if (attr & 1) 3298 radeonfb_rectfill(dp, x, y + he - 2, wi, 1, fg); 3299 return; 3300 } 3301 rv = glyphcache_try(&dp->rd_gc, c, x, y, attr); 3302 if (rv == GC_OK) 3303 return; 3304 3305 data8 = WSFONT_GLYPH(c, font); 3306 3307 gmc = dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT; 3308 3309 radeonfb_wait_fifo(sc, 5); 3310 3311 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 3312 RADEON_GMC_BRUSH_NONE | 3313 RADEON_GMC_SRC_DATATYPE_COLOR | 3314 RADEON_ROP3_S | 3315 RADEON_DP_SRC_SOURCE_HOST_DATA | 3316 RADEON_GMC_CLR_CMP_CNTL_DIS | 3317 RADEON_GMC_WR_MSK_DIS | 3318 gmc); 3319 3320 PUT32(sc, RADEON_DP_CNTL, 3321 RADEON_DST_X_LEFT_TO_RIGHT | 3322 RADEON_DST_Y_TOP_TO_BOTTOM); 3323 3324 PUT32(sc, RADEON_SRC_X_Y, 0); 3325 PUT32(sc, RADEON_DST_X_Y, (x << 16) | y); 3326 PUT32(sc, RADEON_DST_WIDTH_HEIGHT, (wi << 16) | he); 3327 3328 /* 3329 * we need the RGB colours here, so get offsets into rasops_cmap 3330 */ 3331 fgo = ((attr >> 24) & 0xf) * 3; 3332 bgo = ((attr >> 16) & 0xf) * 3; 3333 3334 r0 = rasops_cmap[bgo]; 3335 r1 = rasops_cmap[fgo]; 3336 g0 = rasops_cmap[bgo + 1]; 3337 g1 = rasops_cmap[fgo + 1]; 3338 b0 = rasops_cmap[bgo + 2]; 3339 b1 = rasops_cmap[fgo + 2]; 3340 #define R3G3B2(r, g, b) ((r & 0xe0) | ((g >> 3) & 0x1c) | (b >> 6)) 3341 bg8 = R3G3B2(r0, g0, b0); 3342 fg8 = R3G3B2(r1, g1, b1); 3343 3344 radeonfb_wait_fifo(sc, 20); 3345 cnt = 0; 3346 for (i = 0; i < ri->ri_fontscale; i++) { 3347 aval = *data8; 3348 if (aval == 0) { 3349 pixel = bg8; 3350 } else if (aval == 255) { 3351 pixel = fg8; 3352 } else { 3353 r = aval * r1 + (255 - aval) * r0; 3354 g = aval * g1 + (255 - aval) * g0; 3355 b = aval * b1 + (255 - aval) * b0; 3356 pixel = ((r & 0xe000) >> 8) | 3357 ((g & 0xe000) >> 11) | 3358 ((b & 0xc000) >> 14); 3359 } 3360 latch |= pixel << (8 * (i & 3)); 3361 /* write in 32bit chunks */ 3362 if ((i & 3) == 3) { 3363 PUT32(sc, RADEON_HOST_DATA0, latch); 3364 /* 3365 * not strictly necessary, old data should be shifted 3366 * out 3367 */ 3368 latch = 0; 3369 cnt++; 3370 if (cnt > 16) { 3371 cnt = 0; 3372 radeonfb_wait_fifo(sc, 20); 3373 } 3374 } 3375 data8++; 3376 } 3377 /* if we have pixels left in latch write them out */ 3378 if ((i & 3) != 0) { 3379 /* 3380 * radeon is weird - apparently leftover pixels are written 3381 * from the middle, not from the left as everything else 3382 */ 3383 PUT32(sc, RADEON_HOST_DATA0, latch); 3384 } 3385 3386 if (rv == GC_ADD) { 3387 glyphcache_add(&dp->rd_gc, c, x, y); 3388 } else 3389 if (attr & 1) 3390 radeonfb_rectfill(dp, x, y + he - 2, wi, 1, fg); 3391 } 3392 3393 /* 3394 * wrapper for software character drawing 3395 * just sync the engine and call rasops*_putchar() 3396 */ 3397 3398 #ifndef RADEONFB_ALWAYS_ACCEL_PUTCHAR 3399 static void 3400 radeonfb_putchar_wrapper(void *cookie, int row, int col, u_int c, long attr) 3401 { 3402 struct rasops_info *ri = cookie; 3403 struct vcons_screen *scr = ri->ri_hw; 3404 struct radeonfb_display *dp = scr->scr_cookie; 3405 3406 radeonfb_engine_idle(dp->rd_softc); 3407 dp->rd_putchar(ri, row, col, c, attr); 3408 } 3409 #endif 3410 3411 static void 3412 radeonfb_eraserows(void *cookie, int row, int nrows, long fillattr) 3413 { 3414 struct rasops_info *ri = cookie; 3415 struct vcons_screen *scr = ri->ri_hw; 3416 struct radeonfb_display *dp = scr->scr_cookie; 3417 uint32_t x, y, w, h, fg, bg, ul; 3418 3419 /* XXX: check for full emulation mode? */ 3420 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 3421 x = ri->ri_xorigin; 3422 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 3423 w = ri->ri_emuwidth; 3424 h = ri->ri_font->fontheight * nrows; 3425 3426 rasops_unpack_attr(fillattr, &fg, &bg, &ul); 3427 radeonfb_rectfill(dp, x, y, w, h, ri->ri_devcmap[bg & 0xf]); 3428 } 3429 } 3430 3431 static void 3432 radeonfb_copyrows(void *cookie, int srcrow, int dstrow, int nrows) 3433 { 3434 struct rasops_info *ri = cookie; 3435 struct vcons_screen *scr = ri->ri_hw; 3436 struct radeonfb_display *dp = scr->scr_cookie; 3437 uint32_t x, ys, yd, w, h; 3438 3439 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 3440 x = ri->ri_xorigin; 3441 ys = ri->ri_yorigin + ri->ri_font->fontheight * srcrow; 3442 yd = ri->ri_yorigin + ri->ri_font->fontheight * dstrow; 3443 w = ri->ri_emuwidth; 3444 h = ri->ri_font->fontheight * nrows; 3445 radeonfb_bitblt(dp, x, ys, x, yd, w, h, 3446 RADEON_ROP3_S); 3447 } 3448 } 3449 3450 static void 3451 radeonfb_copycols(void *cookie, int row, int srccol, int dstcol, int ncols) 3452 { 3453 struct rasops_info *ri = cookie; 3454 struct vcons_screen *scr = ri->ri_hw; 3455 struct radeonfb_display *dp = scr->scr_cookie; 3456 uint32_t xs, xd, y, w, h; 3457 3458 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 3459 xs = ri->ri_xorigin + ri->ri_font->fontwidth * srccol; 3460 xd = ri->ri_xorigin + ri->ri_font->fontwidth * dstcol; 3461 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 3462 w = ri->ri_font->fontwidth * ncols; 3463 h = ri->ri_font->fontheight; 3464 radeonfb_bitblt(dp, xs, y, xd, y, w, h, 3465 RADEON_ROP3_S); 3466 } 3467 } 3468 3469 static void 3470 radeonfb_erasecols(void *cookie, int row, int startcol, int ncols, 3471 long fillattr) 3472 { 3473 struct rasops_info *ri = cookie; 3474 struct vcons_screen *scr = ri->ri_hw; 3475 struct radeonfb_display *dp = scr->scr_cookie; 3476 uint32_t x, y, w, h, fg, bg, ul; 3477 3478 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 3479 x = ri->ri_xorigin + ri->ri_font->fontwidth * startcol; 3480 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 3481 w = ri->ri_font->fontwidth * ncols; 3482 h = ri->ri_font->fontheight; 3483 3484 rasops_unpack_attr(fillattr, &fg, &bg, &ul); 3485 radeonfb_rectfill(dp, x, y, w, h, ri->ri_devcmap[bg & 0xf]); 3486 } 3487 } 3488 3489 static void 3490 radeonfb_cursor(void *cookie, int on, int row, int col) 3491 { 3492 struct rasops_info *ri = cookie; 3493 struct vcons_screen *scr = ri->ri_hw; 3494 struct radeonfb_display *dp = scr->scr_cookie; 3495 int x, y, wi, he; 3496 3497 wi = ri->ri_font->fontwidth; 3498 he = ri->ri_font->fontheight; 3499 3500 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 3501 x = ri->ri_ccol * wi + ri->ri_xorigin; 3502 y = ri->ri_crow * he + ri->ri_yorigin; 3503 /* first turn off the old cursor */ 3504 if (ri->ri_flg & RI_CURSOR) { 3505 radeonfb_bitblt(dp, x, y, x, y, wi, he, 3506 RADEON_ROP3_Dn); 3507 ri->ri_flg &= ~RI_CURSOR; 3508 } 3509 ri->ri_crow = row; 3510 ri->ri_ccol = col; 3511 /* then (possibly) turn on the new one */ 3512 if (on) { 3513 x = ri->ri_ccol * wi + ri->ri_xorigin; 3514 y = ri->ri_crow * he + ri->ri_yorigin; 3515 radeonfb_bitblt(dp, x, y, x, y, wi, he, 3516 RADEON_ROP3_Dn); 3517 ri->ri_flg |= RI_CURSOR; 3518 } 3519 } else { 3520 scr->scr_ri.ri_crow = row; 3521 scr->scr_ri.ri_ccol = col; 3522 scr->scr_ri.ri_flg &= ~RI_CURSOR; 3523 } 3524 } 3525 3526 /* 3527 * Underlying acceleration support. 3528 */ 3529 3530 static void 3531 radeonfb_rectfill(struct radeonfb_display *dp, int dstx, int dsty, 3532 int width, int height, uint32_t color) 3533 { 3534 struct radeonfb_softc *sc = dp->rd_softc; 3535 uint32_t gmc; 3536 3537 gmc = dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT; 3538 3539 radeonfb_wait_fifo(sc, 6); 3540 3541 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 3542 RADEON_GMC_BRUSH_SOLID_COLOR | 3543 RADEON_GMC_SRC_DATATYPE_COLOR | 3544 RADEON_GMC_CLR_CMP_CNTL_DIS | 3545 RADEON_ROP3_P | gmc); 3546 3547 PUT32(sc, RADEON_DP_BRUSH_FRGD_CLR, color); 3548 PUT32(sc, RADEON_DP_WRITE_MASK, 0xffffffff); 3549 PUT32(sc, RADEON_DP_CNTL, 3550 RADEON_DST_X_LEFT_TO_RIGHT | 3551 RADEON_DST_Y_TOP_TO_BOTTOM); 3552 PUT32(sc, RADEON_DST_Y_X, (dsty << 16) | dstx); 3553 PUT32(sc, RADEON_DST_WIDTH_HEIGHT, (width << 16) | (height)); 3554 } 3555 3556 static void 3557 radeonfb_rectfill_a(void *cookie, int dstx, int dsty, 3558 int width, int height, long attr) 3559 { 3560 struct radeonfb_display *dp = cookie; 3561 3562 radeonfb_rectfill(dp, dstx, dsty, width, height, 3563 dp->rd_vscreen.scr_ri.ri_devcmap[(attr >> 24 & 0xf)]); 3564 } 3565 3566 static void 3567 radeonfb_bitblt(void *cookie, int srcx, int srcy, 3568 int dstx, int dsty, int width, int height, int rop) 3569 { 3570 struct radeonfb_display *dp = cookie; 3571 struct radeonfb_softc *sc = dp->rd_softc; 3572 uint32_t gmc; 3573 uint32_t dir; 3574 3575 if (dsty < srcy) { 3576 dir = RADEON_DST_Y_TOP_TO_BOTTOM; 3577 } else { 3578 srcy += height - 1; 3579 dsty += height - 1; 3580 dir = 0; 3581 } 3582 if (dstx < srcx) { 3583 dir |= RADEON_DST_X_LEFT_TO_RIGHT; 3584 } else { 3585 srcx += width - 1; 3586 dstx += width - 1; 3587 } 3588 3589 gmc = dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT; 3590 3591 radeonfb_wait_fifo(sc, 6); 3592 3593 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 3594 RADEON_GMC_BRUSH_NONE | 3595 RADEON_GMC_SRC_DATATYPE_COLOR | 3596 RADEON_GMC_CLR_CMP_CNTL_DIS | 3597 RADEON_DP_SRC_SOURCE_MEMORY | 3598 rop | gmc); 3599 3600 PUT32(sc, RADEON_DP_WRITE_MASK, 0xffffffff); 3601 PUT32(sc, RADEON_DP_CNTL, dir); 3602 PUT32(sc, RADEON_SRC_Y_X, (srcy << 16) | srcx); 3603 PUT32(sc, RADEON_DST_Y_X, (dsty << 16) | dstx); 3604 PUT32(sc, RADEON_DST_WIDTH_HEIGHT, (width << 16) | (height)); 3605 } 3606 3607 static void 3608 radeonfb_engine_idle(struct radeonfb_softc *sc) 3609 { 3610 3611 radeonfb_wait_fifo(sc, 64); 3612 while ((GET32(sc, RADEON_RBBM_STATUS) & 3613 RADEON_RBBM_ACTIVE) != 0); 3614 radeonfb_engine_flush(sc); 3615 } 3616 3617 static inline void 3618 radeonfb_wait_fifo(struct radeonfb_softc *sc, int n) 3619 { 3620 int i; 3621 3622 for (i = RADEON_TIMEOUT; i; i--) { 3623 if ((GET32(sc, RADEON_RBBM_STATUS) & 3624 RADEON_RBBM_FIFOCNT_MASK) >= n) 3625 return; 3626 } 3627 #ifdef RADEONFB_DEBUG 3628 if (!i) 3629 printf("%s: timed out waiting for fifo (%x)\n", 3630 XNAME(sc), GET32(sc, RADEON_RBBM_STATUS)); 3631 #endif 3632 } 3633 3634 static void 3635 radeonfb_engine_flush(struct radeonfb_softc *sc) 3636 { 3637 int i = 0; 3638 3639 if (IS_R300(sc) || IS_AVIVO(sc)) { 3640 SET32(sc, R300_DSTCACHE_CTLSTAT, R300_RB2D_DC_FLUSH_ALL); 3641 while (GET32(sc, R300_DSTCACHE_CTLSTAT) & R300_RB2D_DC_BUSY) { 3642 i++; 3643 } 3644 } else { 3645 SET32(sc, RADEON_RB2D_DSTCACHE_CTLSTAT, 3646 RADEON_RB2D_DC_FLUSH_ALL); 3647 while (GET32(sc, RADEON_RB2D_DSTCACHE_CTLSTAT) & 3648 RADEON_RB2D_DC_BUSY) { 3649 i++; 3650 } 3651 } 3652 #ifdef DIAGNOSTIC 3653 if (i > RADEON_TIMEOUT) 3654 printf("%s: engine flush timed out!\n", XNAME(sc)); 3655 #endif 3656 } 3657 3658 static inline void 3659 radeonfb_unclip(struct radeonfb_softc *sc) 3660 { 3661 3662 radeonfb_wait_fifo(sc, 2); 3663 PUT32(sc, RADEON_SC_TOP_LEFT, 0); 3664 PUT32(sc, RADEON_SC_BOTTOM_RIGHT, 0x1fff1fff); 3665 } 3666 3667 static void 3668 radeonfb_engine_init(struct radeonfb_display *dp) 3669 { 3670 struct radeonfb_softc *sc = dp->rd_softc; 3671 uint32_t pitch; 3672 3673 /* no 3D */ 3674 PUT32(sc, RADEON_RB3D_CNTL, 0); 3675 3676 if (IS_AVIVO(sc)) { 3677 3678 #if 0 3679 /* XXX the xf86-video-radeon does this, causes lockups here */ 3680 psel = GET32(sc, R400_GB_PIPE_SELECT); 3681 PRINTREG(R400_GB_PIPE_SELECT); 3682 DPRINTF(("PLL %08x %08x\n", GETPLL(sc, R500_DYN_SCLK_PWMEM_PIPE), 3683 (1 | ((psel >> 8) & 0xf) << 4))); 3684 PUTPLL(sc, R500_DYN_SCLK_PWMEM_PIPE, (1 | ((psel >> 8) & 0xf) << 4)); 3685 #endif 3686 SET32(sc, RADEON_WAIT_UNTIL, RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN); 3687 SET32(sc, R300_DST_PIPE_CONFIG, R300_PIPE_AUTO_CONFIG); 3688 SET32(sc, R300_RB2D_DSTCACHE_MODE, R300_DC_AUTOFLUSH_ENABLE | 3689 R300_DC_DC_DISABLE_IGNORE_PE); 3690 } 3691 3692 PRINTREG(RADEON_RB3D_CNTL); 3693 PRINTREG(RADEON_DP_GUI_MASTER_CNTL); 3694 PRINTREG(RADEON_RBBM_STATUS); 3695 3696 radeonfb_engine_reset(sc); 3697 PRINTREG(RADEON_RBBM_STATUS); 3698 3699 /* 3700 * Apple OF hands us some radeons with tiling enabled - explicitly 3701 * disable it here 3702 */ 3703 PUT32(sc, RADEON_SURFACE_CNTL, RADEON_SURF_TRANSLATION_DIS); 3704 3705 radeonfb_wait_fifo(sc, 1); 3706 if (!IS_R300(sc) && !IS_AVIVO(sc)) 3707 PUT32(sc, RADEON_RB2D_DSTCACHE_MODE, 0); 3708 3709 radeonfb_wait_fifo(sc, 3); 3710 3711 /* 3712 * XXX 3713 * I strongly suspect this works mostly by accident on !AVIVO 3714 * AVIVO uses all 22 bits for the framebuffer offset, so it can 3715 * address up to 4GB. Older chips probably use bits 20-22 for other 3716 * things and we just so happen to set the right ones by having our 3717 * PCI/AGP space above 0x80000000. 3718 * Either way, r5xx does not work if we set these bits, while older 3719 * chips don't work without. 3720 */ 3721 pitch = (dp->rd_stride + 0x3f) >> 6; 3722 if (IS_AVIVO(sc)) { 3723 pitch = pitch << 22; 3724 } else 3725 pitch = (pitch << 22) | (sc->sc_aperbase >> 10); 3726 3727 PUT32(sc, RADEON_DEFAULT_PITCH_OFFSET, pitch); 3728 PUT32(sc, RADEON_DST_PITCH_OFFSET, pitch); 3729 PUT32(sc, RADEON_SRC_PITCH_OFFSET, pitch); 3730 3731 (void)GET32(sc, RADEON_DP_DATATYPE); 3732 3733 /* default scissors -- no clipping */ 3734 radeonfb_wait_fifo(sc, 1); 3735 PUT32(sc, RADEON_DEFAULT_SC_BOTTOM_RIGHT, 3736 RADEON_DEFAULT_SC_RIGHT_MAX | RADEON_DEFAULT_SC_BOTTOM_MAX); 3737 3738 radeonfb_wait_fifo(sc, 1); 3739 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 3740 (dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT) | 3741 RADEON_GMC_CLR_CMP_CNTL_DIS | 3742 RADEON_GMC_BRUSH_SOLID_COLOR | 3743 RADEON_GMC_SRC_DATATYPE_COLOR); 3744 3745 radeonfb_wait_fifo(sc, 10); 3746 PUT32(sc, RADEON_DST_LINE_START, 0); 3747 PUT32(sc, RADEON_DST_LINE_END, 0); 3748 PUT32(sc, RADEON_DP_BRUSH_FRGD_CLR, 0xffffffff); 3749 PUT32(sc, RADEON_DP_BRUSH_BKGD_CLR, 0); 3750 PUT32(sc, RADEON_DP_SRC_FRGD_CLR, 0xffffffff); 3751 PUT32(sc, RADEON_DP_SRC_BKGD_CLR, 0); 3752 PUT32(sc, RADEON_DP_WRITE_MASK, 0xffffffff); 3753 PUT32(sc, RADEON_SC_TOP_LEFT, 0); 3754 PUT32(sc, RADEON_SC_BOTTOM_RIGHT, 0x1fff1fff); 3755 PUT32(sc, RADEON_AUX_SC_CNTL, 0); 3756 radeonfb_engine_idle(sc); 3757 } 3758 3759 static void 3760 radeonfb_engine_reset(struct radeonfb_softc *sc) 3761 { 3762 uint32_t hpc, rbbm, mclkcntl, clkindex; 3763 3764 radeonfb_engine_flush(sc); 3765 3766 clkindex = GET32(sc, RADEON_CLOCK_CNTL_INDEX); 3767 if (HAS_R300CG(sc)) 3768 radeonfb_r300cg_workaround(sc); 3769 mclkcntl = GETPLL(sc, RADEON_MCLK_CNTL); 3770 3771 /* 3772 * According to comments in XFree code, resetting the HDP via 3773 * the RBBM_SOFT_RESET can cause bad behavior on some systems. 3774 * So we use HOST_PATH_CNTL instead. 3775 */ 3776 3777 hpc = GET32(sc, RADEON_HOST_PATH_CNTL); 3778 rbbm = GET32(sc, RADEON_RBBM_SOFT_RESET); 3779 if (IS_R300(sc) || IS_AVIVO(sc)) { 3780 PUT32(sc, RADEON_RBBM_SOFT_RESET, rbbm | 3781 RADEON_SOFT_RESET_CP | 3782 RADEON_SOFT_RESET_HI | 3783 RADEON_SOFT_RESET_E2); 3784 GET32(sc, RADEON_RBBM_SOFT_RESET); 3785 PUT32(sc, RADEON_RBBM_SOFT_RESET, 0); 3786 /* 3787 * XXX: this bit is not defined in any ATI docs I have, 3788 * nor in the XFree code, but XFree does it. Why? 3789 */ 3790 SET32(sc, RADEON_RB2D_DSTCACHE_MODE, R300_DC_DC_DISABLE_IGNORE_PE); 3791 } else { 3792 PUT32(sc, RADEON_RBBM_SOFT_RESET, rbbm | 3793 RADEON_SOFT_RESET_CP | 3794 RADEON_SOFT_RESET_SE | 3795 RADEON_SOFT_RESET_RE | 3796 RADEON_SOFT_RESET_PP | 3797 RADEON_SOFT_RESET_E2 | 3798 RADEON_SOFT_RESET_RB); 3799 GET32(sc, RADEON_RBBM_SOFT_RESET); 3800 PUT32(sc, RADEON_RBBM_SOFT_RESET, rbbm & 3801 ~(RADEON_SOFT_RESET_CP | 3802 RADEON_SOFT_RESET_SE | 3803 RADEON_SOFT_RESET_RE | 3804 RADEON_SOFT_RESET_PP | 3805 RADEON_SOFT_RESET_E2 | 3806 RADEON_SOFT_RESET_RB)); 3807 GET32(sc, RADEON_RBBM_SOFT_RESET); 3808 } 3809 3810 PUT32(sc, RADEON_HOST_PATH_CNTL, hpc | RADEON_HDP_SOFT_RESET); 3811 GET32(sc, RADEON_HOST_PATH_CNTL); 3812 PUT32(sc, RADEON_HOST_PATH_CNTL, hpc); 3813 3814 if (!IS_R300(sc) && !IS_AVIVO(sc)) 3815 PUT32(sc, RADEON_RBBM_SOFT_RESET, rbbm); 3816 3817 PUT32(sc, RADEON_CLOCK_CNTL_INDEX, clkindex); 3818 PRINTREG(RADEON_CLOCK_CNTL_INDEX); 3819 PUTPLL(sc, RADEON_MCLK_CNTL, mclkcntl); 3820 3821 if (HAS_R300CG(sc)) 3822 radeonfb_r300cg_workaround(sc); 3823 } 3824 3825 static int 3826 radeonfb_set_curpos(struct radeonfb_display *dp, struct wsdisplay_curpos *pos) 3827 { 3828 int x, y; 3829 3830 x = pos->x; 3831 y = pos->y; 3832 3833 /* 3834 * This doesn't let a cursor move off the screen. I'm not 3835 * sure if this will have negative effects for e.g. Xinerama. 3836 * I'd guess Xinerama handles it by changing the cursor shape, 3837 * but that needs verification. 3838 */ 3839 if (x >= dp->rd_virtx) 3840 x = dp->rd_virtx - 1; 3841 if (x < 0) 3842 x = 0; 3843 if (y >= dp->rd_virty) 3844 y = dp->rd_virty - 1; 3845 if (y < 0) 3846 y = 0; 3847 3848 dp->rd_cursor.rc_pos.x = x; 3849 dp->rd_cursor.rc_pos.y = y; 3850 3851 radeonfb_cursor_position(dp); 3852 return 0; 3853 } 3854 3855 static int 3856 radeonfb_set_cursor(struct radeonfb_display *dp, struct wsdisplay_cursor *wc) 3857 { 3858 unsigned flags; 3859 3860 uint8_t r[2], g[2], b[2]; 3861 unsigned index, count; 3862 int i, err; 3863 int pitch, size; 3864 struct radeonfb_cursor *nc = &dp->rd_tempcursor; 3865 3866 flags = wc->which; 3867 3868 /* copy old values */ 3869 memcpy(nc, &dp->rd_cursor, sizeof(struct radeonfb_cursor)); 3870 3871 if (flags & WSDISPLAY_CURSOR_DOCMAP) { 3872 index = wc->cmap.index; 3873 count = wc->cmap.count; 3874 3875 if (index >= 2 || count > 2 - index) 3876 return EINVAL; 3877 3878 err = copyin(wc->cmap.red, &r[index], count); 3879 if (err) 3880 return err; 3881 err = copyin(wc->cmap.green, &g[index], count); 3882 if (err) 3883 return err; 3884 err = copyin(wc->cmap.blue, &b[index], count); 3885 if (err) 3886 return err; 3887 3888 for (i = index; i < index + count; i++) { 3889 nc->rc_cmap[i] = 3890 (r[i] << 16) + (g[i] << 8) + (b[i] << 0); 3891 } 3892 } 3893 3894 if (flags & WSDISPLAY_CURSOR_DOSHAPE) { 3895 if ((wc->size.x > RADEON_CURSORMAXX) || 3896 (wc->size.y > RADEON_CURSORMAXY)) 3897 return EINVAL; 3898 3899 /* figure bytes per line */ 3900 pitch = (wc->size.x + 7) / 8; 3901 size = pitch * wc->size.y; 3902 3903 /* clear the old cursor and mask */ 3904 memset(nc->rc_image, 0, 512); 3905 memset(nc->rc_mask, 0, 512); 3906 3907 nc->rc_size = wc->size; 3908 3909 if ((err = copyin(wc->image, nc->rc_image, size)) != 0) 3910 return err; 3911 3912 if ((err = copyin(wc->mask, nc->rc_mask, size)) != 0) 3913 return err; 3914 } 3915 3916 if (flags & WSDISPLAY_CURSOR_DOHOT) { 3917 nc->rc_hot = wc->hot; 3918 if (nc->rc_hot.x >= nc->rc_size.x) 3919 nc->rc_hot.x = nc->rc_size.x - 1; 3920 if (nc->rc_hot.y >= nc->rc_size.y) 3921 nc->rc_hot.y = nc->rc_size.y - 1; 3922 } 3923 3924 if (flags & WSDISPLAY_CURSOR_DOPOS) { 3925 nc->rc_pos = wc->pos; 3926 if (nc->rc_pos.x >= dp->rd_virtx) 3927 nc->rc_pos.x = dp->rd_virtx - 1; 3928 #if 0 3929 if (nc->rc_pos.x < 0) 3930 nc->rc_pos.x = 0; 3931 #endif 3932 if (nc->rc_pos.y >= dp->rd_virty) 3933 nc->rc_pos.y = dp->rd_virty - 1; 3934 #if 0 3935 if (nc->rc_pos.y < 0) 3936 nc->rc_pos.y = 0; 3937 #endif 3938 } 3939 if (flags & WSDISPLAY_CURSOR_DOCUR) { 3940 nc->rc_visible = wc->enable; 3941 } 3942 3943 memcpy(&dp->rd_cursor, nc, sizeof(struct radeonfb_cursor)); 3944 radeonfb_cursor_update(dp, wc->which); 3945 3946 return 0; 3947 } 3948 3949 static uint8_t 3950 radeonfb_backwards(uint8_t d) 3951 { 3952 uint8_t l; 3953 3954 l = d << 7; 3955 l |= ((d & 0x02) << 5); 3956 l |= ((d & 0x04) << 3); 3957 l |= ((d & 0x08) << 1); 3958 l |= ((d & 0x10) >> 1); 3959 l |= ((d & 0x20) >> 3); 3960 l |= ((d & 0x40) >> 5); 3961 l |= ((d & 0x80) >> 7); 3962 return l; 3963 } 3964 3965 /* 3966 * Change the cursor shape. Call this with the cursor locked to avoid 3967 * flickering/tearing. 3968 */ 3969 static void 3970 radeonfb_cursor_shape(struct radeonfb_display *dp) 3971 { 3972 uint8_t and[512], xor[512]; 3973 int i, j, src, dst /* , pitch */; 3974 const uint8_t *msk = dp->rd_cursor.rc_mask; 3975 const uint8_t *img = dp->rd_cursor.rc_image; 3976 3977 /* 3978 * Radeon cursor data interleaves one line of AND data followed 3979 * by a line of XOR data. (Each line corresponds to a whole hardware 3980 * pitch - i.e. 64 pixels or 8 bytes.) 3981 * 3982 * The cursor is displayed using the following table: 3983 * 3984 * AND XOR Result 3985 * ---------------------- 3986 * 0 0 Cursor color 0 3987 * 0 1 Cursor color 1 3988 * 1 0 Transparent 3989 * 1 1 Complement of background 3990 * 3991 * Our masks are therefore different from what we were passed. 3992 * Passed in, I'm assuming the data represents either color 0 or 1, 3993 * and a mask, so the passed in table looks like: 3994 * 3995 * IMG Mask Result 3996 * ----------------------- 3997 * 0 0 Transparent 3998 * 0 1 Cursor color 0 3999 * 1 0 Transparent 4000 * 1 1 Cursor color 1 4001 * 4002 * IF mask bit == 1, AND = 0, XOR = color. 4003 * IF mask bit == 0, AND = 1, XOR = 0. 4004 * 4005 * hence: AND = ~(mask); XOR = color & ~(mask); 4006 */ 4007 4008 /* pitch = ((dp->rd_cursor.rc_size.x + 7) / 8); */ 4009 4010 /* start by assuming all bits are transparent */ 4011 memset(and, 0xff, 512); 4012 memset(xor, 0x00, 512); 4013 4014 src = 0; 4015 dst = 0; 4016 for (i = 0; i < 64; i++) { 4017 for (j = 0; j < 64; j += 8) { 4018 if ((i < dp->rd_cursor.rc_size.y) && 4019 (j < dp->rd_cursor.rc_size.x)) { 4020 4021 /* take care to leave odd bits alone */ 4022 and[dst] &= ~(msk[src]); 4023 xor[dst] = img[src] & msk[src]; 4024 src++; 4025 } 4026 dst++; 4027 } 4028 } 4029 4030 for (i = 0; i < 512; i++) { 4031 and[i] = radeonfb_backwards(and[i]); 4032 xor[i] = radeonfb_backwards(xor[i]); 4033 } 4034 4035 /* copy the image into place */ 4036 for (i = 0; i < 64; i++) { 4037 memcpy((uint8_t *)dp->rd_curptr + (i * 16), 4038 &and[i * 8], 8); 4039 memcpy((uint8_t *)dp->rd_curptr + (i * 16) + 8, 4040 &xor[i * 8], 8); 4041 } 4042 } 4043 4044 /* 4045 * We use the cursor in 24bit mode on avivo, much simpler than the above. 4046 * Should probably do the same on older radeons 4047 */ 4048 static void 4049 radeonfb_avivo_cursor_shape(struct radeonfb_display *dp) 4050 { 4051 const uint8_t *msk = dp->rd_cursor.rc_mask; 4052 const uint8_t *img = dp->rd_cursor.rc_image; 4053 uint32_t *out = (uint32_t *)dp->rd_curptr; 4054 uint8_t bit; 4055 int i, j, px; 4056 4057 for (i = 0; i < 64 * 8; i++) { 4058 bit = 0x01; 4059 for (j = 0; j < 8; j++) { 4060 px = ((*msk & bit) ? 2 : 0) | ((*img & bit) ? 1 : 0); 4061 switch (px) { 4062 case 0: 4063 case 1: 4064 *out = htole32(0x00000000); 4065 break; 4066 case 2: 4067 *out = htole32(0xff000000 | 4068 dp->rd_cursor.rc_cmap[0]); 4069 break; 4070 case 3: 4071 *out = htole32(0xff000000 | 4072 dp->rd_cursor.rc_cmap[1]); 4073 break; 4074 } 4075 out++; 4076 bit = bit << 1; 4077 } 4078 msk++; 4079 img++; 4080 } 4081 } 4082 4083 static void 4084 radeonfb_cursor_position(struct radeonfb_display *dp) 4085 { 4086 struct radeonfb_softc *sc = dp->rd_softc; 4087 uint32_t offset, hvoff, hvpos; /* registers */ 4088 uint32_t coff; /* cursor offset */ 4089 int i, x, y, xoff, yoff, crtcoff, lock; 4090 4091 /* 4092 * XXX: this also needs to handle pan/scan 4093 */ 4094 for (i = 0; i < dp->rd_ncrtcs; i++) { 4095 4096 struct radeonfb_crtc *rcp = &dp->rd_crtcs[i]; 4097 4098 SET32(sc, AVIVO_D1CUR_UPDATE, AVIVO_D1CURSOR_UPDATE_LOCK); 4099 PUT32(sc, AVIVO_D1CUR_SIZE, 0x003f003f); 4100 if (IS_AVIVO(sc)) { 4101 if (rcp->rc_number) { 4102 offset = AVIVO_D2CUR_SURFACE_ADDRESS; 4103 hvoff = AVIVO_D2CUR_HOT_SPOT; 4104 hvpos = AVIVO_D2CUR_POSITION; 4105 crtcoff = 0/*RADEON_CRTC_OFFSET*/; 4106 } else { 4107 offset = AVIVO_D1CUR_SURFACE_ADDRESS; 4108 hvoff = AVIVO_D1CUR_HOT_SPOT; 4109 hvpos = AVIVO_D1CUR_POSITION; 4110 crtcoff = 0/*RADEON_CRTC_OFFSET*/; 4111 } 4112 lock = 0; 4113 } else { 4114 if (rcp->rc_number) { 4115 offset = RADEON_CUR2_OFFSET; 4116 hvoff = RADEON_CUR2_HORZ_VERT_OFF; 4117 hvpos = RADEON_CUR2_HORZ_VERT_POSN; 4118 crtcoff = RADEON_CRTC2_OFFSET; 4119 } else { 4120 offset = RADEON_CUR_OFFSET; 4121 hvoff = RADEON_CUR_HORZ_VERT_OFF; 4122 hvpos = RADEON_CUR_HORZ_VERT_POSN; 4123 crtcoff = RADEON_CRTC_OFFSET; 4124 } 4125 lock = RADEON_CUR_LOCK; 4126 } 4127 4128 x = dp->rd_cursor.rc_pos.x; 4129 y = dp->rd_cursor.rc_pos.y; 4130 4131 while (y < rcp->rc_yoffset) { 4132 rcp->rc_yoffset -= RADEON_PANINCREMENT; 4133 } 4134 while (y >= (rcp->rc_yoffset + rcp->rc_videomode.vdisplay)) { 4135 rcp->rc_yoffset += RADEON_PANINCREMENT; 4136 } 4137 while (x < rcp->rc_xoffset) { 4138 rcp->rc_xoffset -= RADEON_PANINCREMENT; 4139 } 4140 while (x >= (rcp->rc_xoffset + rcp->rc_videomode.hdisplay)) { 4141 rcp->rc_xoffset += RADEON_PANINCREMENT; 4142 } 4143 4144 /* adjust for the cursor's hotspot */ 4145 x -= dp->rd_cursor.rc_hot.x; 4146 y -= dp->rd_cursor.rc_hot.y; 4147 xoff = yoff = 0; 4148 4149 if (x >= dp->rd_virtx) 4150 x = dp->rd_virtx - 1; 4151 if (y >= dp->rd_virty) 4152 y = dp->rd_virty - 1; 4153 4154 /* now adjust cursor so it is relative to viewport */ 4155 x -= rcp->rc_xoffset; 4156 y -= rcp->rc_yoffset; 4157 4158 /* 4159 * no need to check for fall off, because we should 4160 * never move off the screen entirely! 4161 */ 4162 coff = 0; 4163 if (x < 0) { 4164 xoff = -x; 4165 x = 0; 4166 } 4167 if (y < 0) { 4168 yoff = -y; 4169 y = 0; 4170 coff = (yoff * 2) * 8; 4171 } 4172 4173 /* pan the display */ 4174 if (crtcoff != 0) 4175 PUT32(sc, crtcoff, (rcp->rc_yoffset * dp->rd_stride) + 4176 rcp->rc_xoffset); 4177 4178 PUT32(sc, offset, (dp->rd_curoff + coff) | lock); 4179 PUT32(sc, hvoff, (xoff << 16) | (yoff) | lock); 4180 /* NB: this unlocks the cursor */ 4181 PUT32(sc, hvpos, (x << 16) | y); 4182 if (IS_AVIVO(sc)) 4183 CLR32(sc, AVIVO_D1CUR_UPDATE, AVIVO_D1CURSOR_UPDATE_LOCK); 4184 } 4185 } 4186 4187 static void 4188 radeonfb_cursor_visible(struct radeonfb_display *dp) 4189 { 4190 struct radeonfb_softc *sc = dp->rd_softc; 4191 int i; 4192 uint32_t gencntl, bit; 4193 4194 for (i = 0; i < dp->rd_ncrtcs; i++) { 4195 if (IS_AVIVO(sc)) { 4196 SET32(sc, AVIVO_D1CUR_UPDATE, AVIVO_D1CURSOR_UPDATE_LOCK); 4197 if (dp->rd_crtcs[i].rc_number) { 4198 gencntl = AVIVO_D2CUR_CONTROL; 4199 bit = AVIVO_D1CURSOR_EN | (2 << 8); 4200 } else { 4201 gencntl = AVIVO_D1CUR_CONTROL; 4202 bit = AVIVO_D1CURSOR_EN | (2 << 8); 4203 } 4204 } else { 4205 if (dp->rd_crtcs[i].rc_number) { 4206 gencntl = RADEON_CRTC2_GEN_CNTL; 4207 bit = RADEON_CRTC2_CUR_EN; 4208 } else { 4209 gencntl = RADEON_CRTC_GEN_CNTL; 4210 bit = RADEON_CRTC_CUR_EN; 4211 } 4212 } 4213 if (dp->rd_cursor.rc_visible) 4214 SET32(dp->rd_softc, gencntl, bit); 4215 else 4216 CLR32(dp->rd_softc, gencntl, bit); 4217 if (IS_AVIVO(sc)) 4218 CLR32(sc, AVIVO_D1CUR_UPDATE, AVIVO_D1CURSOR_UPDATE_LOCK); 4219 4220 } 4221 } 4222 4223 static void 4224 radeonfb_cursor_cmap(struct radeonfb_display *dp) 4225 { 4226 int i; 4227 uint32_t c0reg, c1reg; 4228 struct radeonfb_softc *sc = dp->rd_softc; 4229 4230 for (i = 0; i < dp->rd_ncrtcs; i++) { 4231 if (dp->rd_crtcs[i].rc_number) { 4232 c0reg = RADEON_CUR2_CLR0; 4233 c1reg = RADEON_CUR2_CLR1; 4234 } else { 4235 c0reg = RADEON_CUR_CLR0; 4236 c1reg = RADEON_CUR_CLR1; 4237 } 4238 4239 PUT32(sc, c0reg, dp->rd_cursor.rc_cmap[0]); 4240 PUT32(sc, c1reg, dp->rd_cursor.rc_cmap[1]); 4241 } 4242 } 4243 4244 static void 4245 radeonfb_cursor_update(struct radeonfb_display *dp, unsigned which) 4246 { 4247 struct radeonfb_softc *sc; 4248 int i; 4249 4250 sc = dp->rd_softc; 4251 4252 for (i = 0; i < dp->rd_ncrtcs; i++) { 4253 if (dp->rd_crtcs[i].rc_number) { 4254 if (IS_AVIVO(sc)) { 4255 SET32(sc, AVIVO_D2CUR_UPDATE, AVIVO_D1CURSOR_UPDATE_LOCK); 4256 } else 4257 SET32(sc, RADEON_CUR2_OFFSET, RADEON_CUR_LOCK); 4258 } else { 4259 if (IS_AVIVO(sc)) { 4260 SET32(sc, AVIVO_D1CUR_UPDATE, AVIVO_D1CURSOR_UPDATE_LOCK); 4261 } else 4262 SET32(sc, RADEON_CUR_OFFSET,RADEON_CUR_LOCK); 4263 } 4264 } 4265 4266 if (which & WSDISPLAY_CURSOR_DOCMAP) { 4267 if (IS_AVIVO(sc)) { 4268 /* 4269 * we use an ARGB cursor here, so we need to rebuild 4270 * the cursor image every time the palette changes 4271 */ 4272 radeonfb_avivo_cursor_shape(dp); 4273 } else 4274 radeonfb_cursor_cmap(dp); 4275 } 4276 4277 if (which & WSDISPLAY_CURSOR_DOSHAPE) { 4278 if (IS_AVIVO(sc)) { 4279 radeonfb_avivo_cursor_shape(dp); 4280 } else 4281 radeonfb_cursor_shape(dp); 4282 } 4283 4284 if (which & WSDISPLAY_CURSOR_DOCUR) 4285 radeonfb_cursor_visible(dp); 4286 4287 /* this one is unconditional, because it updates other stuff */ 4288 radeonfb_cursor_position(dp); 4289 } 4290 4291 static struct videomode * 4292 radeonfb_best_refresh(struct videomode *m1, struct videomode *m2) 4293 { 4294 int r1, r2; 4295 4296 /* otherwise pick the higher refresh rate */ 4297 r1 = DIVIDE(DIVIDE(m1->dot_clock, m1->htotal), m1->vtotal); 4298 r2 = DIVIDE(DIVIDE(m2->dot_clock, m2->htotal), m2->vtotal); 4299 4300 return (r1 < r2 ? m2 : m1); 4301 } 4302 4303 static const struct videomode * 4304 radeonfb_port_mode(struct radeonfb_softc *sc, struct radeonfb_port *rp, 4305 int x, int y) 4306 { 4307 struct edid_info *ep = &rp->rp_edid; 4308 struct videomode *vmp = NULL; 4309 int i; 4310 4311 if (!rp->rp_edid_valid) { 4312 /* fallback to safe mode */ 4313 return radeonfb_modelookup(sc->sc_defaultmode); 4314 } 4315 4316 /* always choose the preferred mode first! */ 4317 if (ep->edid_preferred_mode) { 4318 4319 /* XXX: add auto-stretching support for native mode */ 4320 4321 /* this may want panning to occur, btw */ 4322 if ((ep->edid_preferred_mode->hdisplay <= x) && 4323 (ep->edid_preferred_mode->vdisplay <= y)) 4324 return ep->edid_preferred_mode; 4325 } 4326 4327 for (i = 0; i < ep->edid_nmodes; i++) { 4328 /* 4329 * We elect to pick a resolution that is too large for 4330 * the monitor than one that is too small. This means 4331 * that we will prefer to pan rather than to try to 4332 * center a smaller display on a larger screen. In 4333 * practice, this shouldn't matter because if a 4334 * monitor can support a larger resolution, it can 4335 * probably also support the smaller. A specific 4336 * exception is fixed format panels, but hopefully 4337 * they are properly dealt with by the "autostretch" 4338 * logic above. 4339 */ 4340 if ((ep->edid_modes[i].hdisplay > x) || 4341 (ep->edid_modes[i].vdisplay > y)) { 4342 continue; 4343 } 4344 4345 /* 4346 * at this point, the display mode is no larger than 4347 * what we've requested. 4348 */ 4349 if (vmp == NULL) 4350 vmp = &ep->edid_modes[i]; 4351 4352 /* eliminate smaller modes */ 4353 if ((vmp->hdisplay >= ep->edid_modes[i].hdisplay) || 4354 (vmp->vdisplay >= ep->edid_modes[i].vdisplay)) 4355 continue; 4356 4357 if ((vmp->hdisplay < ep->edid_modes[i].hdisplay) || 4358 (vmp->vdisplay < ep->edid_modes[i].vdisplay)) { 4359 vmp = &ep->edid_modes[i]; 4360 continue; 4361 } 4362 4363 KASSERT(vmp->hdisplay == ep->edid_modes[i].hdisplay); 4364 KASSERT(vmp->vdisplay == ep->edid_modes[i].vdisplay); 4365 4366 vmp = radeonfb_best_refresh(vmp, &ep->edid_modes[i]); 4367 } 4368 4369 return (vmp ? vmp : radeonfb_modelookup(sc->sc_defaultmode)); 4370 } 4371 4372 static int 4373 radeonfb_hasres(struct videomode *list, int nlist, int x, int y) 4374 { 4375 int i; 4376 4377 for (i = 0; i < nlist; i++) { 4378 if ((x == list[i].hdisplay) && 4379 (y == list[i].vdisplay)) { 4380 return 1; 4381 } 4382 } 4383 return 0; 4384 } 4385 4386 static void 4387 radeonfb_pickres(struct radeonfb_display *dp, uint16_t *x, uint16_t *y, 4388 int pan) 4389 { 4390 struct radeonfb_port *rp; 4391 struct edid_info *ep; 4392 int i, j; 4393 4394 *x = 0; 4395 *y = 0; 4396 4397 if (pan) { 4398 for (i = 0; i < dp->rd_ncrtcs; i++) { 4399 rp = dp->rd_crtcs[i].rc_port; 4400 ep = &rp->rp_edid; 4401 if (!rp->rp_edid_valid) { 4402 /* monitor not present */ 4403 continue; 4404 } 4405 4406 /* 4407 * For now we are ignoring "conflict" that 4408 * could occur when mixing some modes like 4409 * 1280x1024 and 1400x800. It isn't clear 4410 * which is better, so the first one wins. 4411 */ 4412 for (j = 0; j < ep->edid_nmodes; j++) { 4413 /* 4414 * ignore resolutions that are too big for 4415 * the radeon 4416 */ 4417 if (ep->edid_modes[j].hdisplay > 4418 dp->rd_softc->sc_maxx) 4419 continue; 4420 if (ep->edid_modes[j].vdisplay > 4421 dp->rd_softc->sc_maxy) 4422 continue; 4423 4424 /* 4425 * pick largest resolution, the 4426 * smaller monitor will pan 4427 */ 4428 if ((ep->edid_modes[j].hdisplay >= *x) && 4429 (ep->edid_modes[j].vdisplay >= *y)) { 4430 *x = ep->edid_modes[j].hdisplay; 4431 *y = ep->edid_modes[j].vdisplay; 4432 } 4433 } 4434 } 4435 4436 } else { 4437 struct videomode *modes; 4438 size_t smodes; 4439 int nmodes = 0; 4440 int valid = 0; 4441 4442 smodes = sizeof(struct videomode) * 64; 4443 modes = kmem_alloc(smodes, KM_SLEEP); 4444 4445 for (i = 0; i < dp->rd_ncrtcs; i++) { 4446 /* 4447 * pick the largest resolution in common. 4448 */ 4449 rp = dp->rd_crtcs[i].rc_port; 4450 ep = &rp->rp_edid; 4451 4452 if (!rp->rp_edid_valid) 4453 continue; 4454 4455 if (!valid) { 4456 /* 4457 * Pick the preferred mode for this port 4458 * if available. 4459 */ 4460 if (ep->edid_preferred_mode) { 4461 struct videomode *vmp = 4462 ep->edid_preferred_mode; 4463 4464 if ((vmp->hdisplay <= 4465 dp->rd_softc->sc_maxx) && 4466 (vmp->vdisplay <= 4467 dp->rd_softc->sc_maxy)) 4468 modes[nmodes++] = *vmp; 4469 } else { 4470 4471 /* initialize starting list */ 4472 for (j = 0; j < ep->edid_nmodes; j++) { 4473 /* 4474 * ignore resolutions that are 4475 * too big for the radeon 4476 */ 4477 if (ep->edid_modes[j].hdisplay > 4478 dp->rd_softc->sc_maxx) 4479 continue; 4480 if (ep->edid_modes[j].vdisplay > 4481 dp->rd_softc->sc_maxy) 4482 continue; 4483 4484 modes[nmodes] = 4485 ep->edid_modes[j]; 4486 nmodes++; 4487 } 4488 } 4489 valid = 1; 4490 } else { 4491 /* merge into preexisting list */ 4492 for (j = 0; j < nmodes; j++) { 4493 if (!radeonfb_hasres(ep->edid_modes, 4494 ep->edid_nmodes, 4495 modes[j].hdisplay, 4496 modes[j].vdisplay)) { 4497 modes[j] = modes[nmodes]; 4498 j--; 4499 nmodes--; 4500 } 4501 } 4502 } 4503 } 4504 4505 /* now we have to pick from the merged list */ 4506 for (i = 0; i < nmodes; i++) { 4507 if ((modes[i].hdisplay >= *x) && 4508 (modes[i].vdisplay >= *y)) { 4509 *x = modes[i].hdisplay; 4510 *y = modes[i].vdisplay; 4511 } 4512 } 4513 kmem_free(modes, smodes); 4514 4515 } 4516 4517 if ((*x == 0) || (*y == 0)) { 4518 /* fallback to safe mode */ 4519 *x = 640; 4520 *y = 480; 4521 } 4522 } 4523 4524 /* 4525 * backlight levels are linear on: 4526 * - RV200, RV250, RV280, RV350 4527 * - but NOT on PowerBook4,3 6,3 6,5 4528 * according to Linux' radeonfb 4529 */ 4530 4531 /* Get the current backlight level for the display. */ 4532 4533 static int 4534 radeonfb_get_backlight(struct radeonfb_display *dp) 4535 { 4536 int s; 4537 uint32_t level; 4538 4539 s = spltty(); 4540 4541 level = radeonfb_get32(dp->rd_softc, RADEON_LVDS_GEN_CNTL); 4542 level &= RADEON_LVDS_BL_MOD_LEV_MASK; 4543 level >>= RADEON_LVDS_BL_MOD_LEV_SHIFT; 4544 4545 /* 4546 * On some chips, we should negate the backlight level. 4547 * XXX Find out on which chips. 4548 */ 4549 if (dp->rd_softc->sc_flags & RFB_INV_BLIGHT) 4550 level = RADEONFB_BACKLIGHT_MAX - level; 4551 4552 splx(s); 4553 4554 return level; 4555 } 4556 4557 /* Set the backlight to the given level for the display. */ 4558 static void 4559 radeonfb_switch_backlight(struct radeonfb_display *dp, int on) 4560 { 4561 if (dp->rd_bl_on == on) 4562 return; 4563 dp->rd_bl_on = on; 4564 radeonfb_set_backlight(dp, dp->rd_bl_level); 4565 } 4566 4567 static int 4568 radeonfb_set_backlight(struct radeonfb_display *dp, int level) 4569 { 4570 struct radeonfb_softc *sc = dp->rd_softc; 4571 int rlevel, s; 4572 uint32_t lvds; 4573 4574 if(!sc->sc_mapped) 4575 return 0; 4576 4577 s = spltty(); 4578 4579 dp->rd_bl_level = level; 4580 if (dp->rd_bl_on == 0) 4581 level = 0; 4582 4583 if (level < 0) 4584 level = 0; 4585 else if (level >= RADEONFB_BACKLIGHT_MAX) 4586 level = RADEONFB_BACKLIGHT_MAX; 4587 4588 /* On some chips, we should negate the backlight level. */ 4589 if (dp->rd_softc->sc_flags & RFB_INV_BLIGHT) { 4590 rlevel = RADEONFB_BACKLIGHT_MAX - level; 4591 } else 4592 rlevel = level; 4593 4594 callout_stop(&dp->rd_bl_lvds_co); 4595 //radeonfb_engine_idle(sc); 4596 4597 /* 4598 * Turn off the display if the backlight is set to 0, since the 4599 * display is useless without backlight anyway. 4600 */ 4601 if (level == 0) 4602 radeonfb_blank(dp, 1); 4603 else if (radeonfb_get_backlight(dp) == 0) 4604 radeonfb_blank(dp, 0); 4605 4606 lvds = radeonfb_get32(sc, RADEON_LVDS_GEN_CNTL); 4607 lvds &= ~RADEON_LVDS_DISPLAY_DIS; 4608 if (!(lvds & RADEON_LVDS_BLON) || !(lvds & RADEON_LVDS_ON)) { 4609 lvds |= dp->rd_bl_lvds_val & RADEON_LVDS_DIGON; 4610 lvds |= RADEON_LVDS_BLON | RADEON_LVDS_EN; 4611 radeonfb_put32(sc, RADEON_LVDS_GEN_CNTL, lvds); 4612 lvds &= ~RADEON_LVDS_BL_MOD_LEV_MASK; 4613 lvds |= rlevel << RADEON_LVDS_BL_MOD_LEV_SHIFT; 4614 lvds |= RADEON_LVDS_ON; 4615 lvds |= dp->rd_bl_lvds_val & RADEON_LVDS_BL_MOD_EN; 4616 } else { 4617 lvds &= ~RADEON_LVDS_BL_MOD_LEV_MASK; 4618 lvds |= rlevel << RADEON_LVDS_BL_MOD_LEV_SHIFT; 4619 radeonfb_put32(sc, RADEON_LVDS_GEN_CNTL, lvds); 4620 } 4621 4622 dp->rd_bl_lvds_val &= ~RADEON_LVDS_STATE_MASK; 4623 dp->rd_bl_lvds_val |= lvds & RADEON_LVDS_STATE_MASK; 4624 /* XXX What is the correct delay? */ 4625 callout_schedule(&dp->rd_bl_lvds_co, 200 * hz); 4626 4627 splx(s); 4628 4629 return 0; 4630 } 4631 4632 /* 4633 * Callout function for delayed operations on the LVDS_GEN_CNTL register. 4634 * Set the delayed bits in the register, and clear the stored delayed 4635 * value. 4636 */ 4637 4638 static void radeonfb_lvds_callout(void *arg) 4639 { 4640 struct radeonfb_display *dp = arg; 4641 int s; 4642 4643 s = splhigh(); 4644 4645 radeonfb_mask32(dp->rd_softc, RADEON_LVDS_GEN_CNTL, ~0, 4646 dp->rd_bl_lvds_val); 4647 dp->rd_bl_lvds_val = 0; 4648 4649 splx(s); 4650 } 4651 4652 static void 4653 radeonfb_brightness_up(device_t dev) 4654 { 4655 struct radeonfb_softc *sc = device_private(dev); 4656 struct radeonfb_display *dp = &sc->sc_displays[0]; 4657 int level; 4658 4659 /* we assume the main display is the first one - need a better way */ 4660 if (sc->sc_ndisplays < 1) return; 4661 /* make sure pushing the hotkeys always has an effect */ 4662 dp->rd_bl_on = 1; 4663 level = dp->rd_bl_level; 4664 level = uimin(RADEONFB_BACKLIGHT_MAX, level + 5); 4665 radeonfb_set_backlight(dp, level); 4666 } 4667 4668 static void 4669 radeonfb_brightness_down(device_t dev) 4670 { 4671 struct radeonfb_softc *sc = device_private(dev); 4672 struct radeonfb_display *dp = &sc->sc_displays[0]; 4673 int level; 4674 4675 /* we assume the main display is the first one - need a better way */ 4676 if (sc->sc_ndisplays < 1) return; 4677 /* make sure pushing the hotkeys always has an effect */ 4678 dp->rd_bl_on = 1; 4679 level = dp->rd_bl_level; 4680 level = uimax(0, level - 5); 4681 radeonfb_set_backlight(dp, level); 4682 } 4683
Indexes created Mon Oct 20 01:09:56 GMT 2025