radeonfb.c revision 1.116
1 /* $NetBSD: radeonfb.c,v 1.116 2021/08/07 16:19:14 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 2006 Itronix Inc. 5 * All rights reserved. 6 * 7 * Written by Garrett D'Amore for Itronix Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. The name of Itronix Inc. may not be used to endorse 18 * or promote products derived from this software without specific 19 * prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY ITRONIX INC. ``AS IS'' AND ANY EXPRESS 22 * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 23 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL ITRONIX INC. BE LIABLE FOR ANY 25 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE 27 * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 29 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 30 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 31 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * ATI Technologies Inc. ("ATI") has not assisted in the creation of, and 36 * does not endorse, this software. ATI will not be responsible or liable 37 * for any actual or alleged damage or loss caused by or in connection with 38 * the use of or reliance on this software. 39 */ 40 41 /* 42 * Portions of this code were taken from XFree86's Radeon driver, which bears 43 * this notice: 44 * 45 * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and 46 * VA Linux Systems Inc., Fremont, California. 47 * 48 * All Rights Reserved. 49 * 50 * Permission is hereby granted, free of charge, to any person obtaining 51 * a copy of this software and associated documentation files (the 52 * "Software"), to deal in the Software without restriction, including 53 * without limitation on the rights to use, copy, modify, merge, 54 * publish, distribute, sublicense, and/or sell copies of the Software, 55 * and to permit persons to whom the Software is furnished to do so, 56 * subject to the following conditions: 57 * 58 * The above copyright notice and this permission notice (including the 59 * next paragraph) shall be included in all copies or substantial 60 * portions of the Software. 61 * 62 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 63 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 64 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 65 * NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR 66 * THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 67 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 68 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 69 * DEALINGS IN THE SOFTWARE. 70 */ 71 72 #include <sys/cdefs.h> 73 __KERNEL_RCSID(0, "$NetBSD: radeonfb.c,v 1.116 2021/08/07 16:19:14 thorpej Exp $"); 74 75 #include <sys/param.h> 76 #include <sys/systm.h> 77 #include <sys/device.h> 78 #include <sys/malloc.h> 79 #include <sys/bus.h> 80 #include <sys/kernel.h> 81 #include <sys/lwp.h> 82 #include <sys/kauth.h> 83 #include <sys/kmem.h> 84 85 #include <dev/wscons/wsdisplayvar.h> 86 #include <dev/wscons/wsconsio.h> 87 #include <dev/wsfont/wsfont.h> 88 #include <dev/rasops/rasops.h> 89 #include <dev/videomode/videomode.h> 90 #include <dev/videomode/edidvar.h> 91 #include <dev/wscons/wsdisplay_vconsvar.h> 92 #include <dev/pci/wsdisplay_pci.h> 93 #include <dev/wscons/wsdisplay_glyphcachevar.h> 94 95 #include <dev/pci/pcidevs.h> 96 #include <dev/pci/pcireg.h> 97 #include <dev/pci/pcivar.h> 98 #include <dev/pci/pciio.h> 99 #include <dev/pci/radeonfbreg.h> 100 #include <dev/pci/radeonfbvar.h> 101 #include "opt_radeonfb.h" 102 #include "opt_vcons.h" 103 104 #ifdef RADEONFB_DEPTH_32 105 #define RADEONFB_DEFAULT_DEPTH 32 106 #else 107 #define RADEONFB_DEFAULT_DEPTH 8 108 #endif 109 110 static int radeonfb_match(device_t, cfdata_t, void *); 111 static void radeonfb_attach(device_t, device_t, void *); 112 static int radeonfb_ioctl(void *, void *, unsigned long, void *, int, 113 struct lwp *); 114 static paddr_t radeonfb_mmap(void *, void *, off_t, int); 115 static int radeonfb_scratch_test(struct radeonfb_softc *, int, uint32_t); 116 static void radeonfb_loadbios(struct radeonfb_softc *, 117 const struct pci_attach_args *); 118 119 static uintmax_t radeonfb_getprop_num(struct radeonfb_softc *, const char *, 120 uintmax_t); 121 static int radeonfb_getclocks(struct radeonfb_softc *); 122 static int radeonfb_gettmds(struct radeonfb_softc *); 123 static int radeonfb_calc_dividers(struct radeonfb_softc *, uint32_t, 124 uint32_t *, uint32_t *, int); 125 /* flags for radeonfb_calc_dividers */ 126 #define NO_ODD_FBDIV 1 127 128 static int radeonfb_getconnectors(struct radeonfb_softc *); 129 static const struct videomode *radeonfb_modelookup(const char *); 130 static void radeonfb_init_screen(void *, struct vcons_screen *, int, long *); 131 static void radeonfb_pllwriteupdate(struct radeonfb_softc *, int); 132 static void radeonfb_pllwaitatomicread(struct radeonfb_softc *, int); 133 static void radeonfb_program_vclk(struct radeonfb_softc *, int, int, int); 134 static void radeonfb_modeswitch(struct radeonfb_display *); 135 static void radeonfb_setcrtc(struct radeonfb_display *, int); 136 static void radeonfb_init_misc(struct radeonfb_softc *); 137 static void radeonfb_set_fbloc(struct radeonfb_softc *); 138 static void radeonfb_init_palette(struct radeonfb_display *); 139 static void radeonfb_r300cg_workaround(struct radeonfb_softc *); 140 141 static int radeonfb_isblank(struct radeonfb_display *); 142 static void radeonfb_blank(struct radeonfb_display *, int); 143 static int radeonfb_set_cursor(struct radeonfb_display *, 144 struct wsdisplay_cursor *); 145 static int radeonfb_set_curpos(struct radeonfb_display *, 146 struct wsdisplay_curpos *); 147 static void radeonfb_putpal(struct radeonfb_display *, int, int, int, int); 148 static int radeonfb_putcmap(struct radeonfb_display *, struct wsdisplay_cmap *); 149 static int radeonfb_getcmap(struct radeonfb_display *, struct wsdisplay_cmap *); 150 151 /* acceleration support */ 152 static void radeonfb_rectfill(struct radeonfb_display *, int dstx, int dsty, 153 int width, int height, uint32_t color); 154 static void radeonfb_rectfill_a(void *, int, int, int, int, long); 155 static void radeonfb_bitblt(void *, int srcx, int srcy, 156 int dstx, int dsty, int width, int height, int rop); 157 158 /* hw cursor support */ 159 static void radeonfb_cursor_cmap(struct radeonfb_display *); 160 static void radeonfb_cursor_shape(struct radeonfb_display *); 161 static void radeonfb_cursor_position(struct radeonfb_display *); 162 static void radeonfb_cursor_visible(struct radeonfb_display *); 163 static void radeonfb_cursor_update(struct radeonfb_display *, unsigned); 164 165 static inline void radeonfb_wait_fifo(struct radeonfb_softc *, int); 166 static void radeonfb_engine_idle(struct radeonfb_softc *); 167 static void radeonfb_engine_flush(struct radeonfb_softc *); 168 static void radeonfb_engine_reset(struct radeonfb_softc *); 169 static void radeonfb_engine_init(struct radeonfb_display *); 170 static inline void radeonfb_unclip(struct radeonfb_softc *) __unused; 171 172 static void radeonfb_eraserows(void *, int, int, long); 173 static void radeonfb_erasecols(void *, int, int, int, long); 174 static void radeonfb_copyrows(void *, int, int, int); 175 static void radeonfb_copycols(void *, int, int, int, int); 176 static void radeonfb_cursor(void *, int, int, int); 177 static void radeonfb_putchar(void *, int, int, unsigned, long); 178 static void radeonfb_putchar_aa32(void *, int, int, unsigned, long); 179 static void radeonfb_putchar_aa8(void *, int, int, unsigned, long); 180 #ifndef RADEONFB_ALWAYS_ACCEL_PUTCHAR 181 static void radeonfb_putchar_wrapper(void *, int, int, unsigned, long); 182 #endif 183 184 static int radeonfb_set_backlight(struct radeonfb_display *, int); 185 static int radeonfb_get_backlight(struct radeonfb_display *); 186 static void radeonfb_switch_backlight(struct radeonfb_display *, int); 187 static void radeonfb_lvds_callout(void *); 188 189 static void radeonfb_brightness_up(device_t); 190 static void radeonfb_brightness_down(device_t); 191 192 static struct videomode *radeonfb_best_refresh(struct videomode *, 193 struct videomode *); 194 static void radeonfb_pickres(struct radeonfb_display *, uint16_t *, 195 uint16_t *, int); 196 static const struct videomode *radeonfb_port_mode(struct radeonfb_softc *, 197 struct radeonfb_port *, int, int); 198 199 static int radeonfb_drm_print(void *, const char *); 200 201 #ifdef RADEONFB_DEBUG 202 int radeon_debug = 1; 203 #define DPRINTF(x) \ 204 if (radeon_debug) printf x 205 #define PRINTREG(r) DPRINTF((#r " = %08x\n", GET32(sc, r))) 206 #define PRINTPLL(r) DPRINTF((#r " = %08x\n", GETPLL(sc, r))) 207 #else 208 #define DPRINTF(x) 209 #define PRINTREG(r) 210 #define PRINTPLL(r) 211 #endif 212 213 #define ROUNDUP(x,y) (((x) + ((y) - 1)) & ~((y) - 1)) 214 215 #ifndef RADEON_DEFAULT_MODE 216 /* any reasonably modern display should handle this */ 217 #define RADEON_DEFAULT_MODE "1024x768x60" 218 #endif 219 220 extern const u_char rasops_cmap[768]; 221 222 const char *radeonfb_default_mode = RADEON_DEFAULT_MODE; 223 224 static struct { 225 int size; /* minimum memory size (MB) */ 226 int maxx; /* maximum x dimension */ 227 int maxy; /* maximum y dimension */ 228 int maxbpp; /* maximum bpp */ 229 int maxdisp; /* maximum logical display count */ 230 } radeonfb_limits[] = { 231 { 32, 2048, 1536, 32, 2 }, 232 { 16, 1600, 1200, 32, 2 }, 233 { 8, 1600, 1200, 32, 1 }, 234 { 0, 0, 0, 0, 0 }, 235 }; 236 237 static struct wsscreen_descr radeonfb_stdscreen = { 238 "fb", /* name */ 239 0, 0, /* ncols, nrows */ 240 NULL, /* textops */ 241 8, 16, /* fontwidth, fontheight */ 242 WSSCREEN_WSCOLORS | WSSCREEN_UNDERLINE | WSSCREEN_RESIZE, /* capabilities */ 243 0, /* modecookie */ 244 }; 245 246 struct wsdisplay_accessops radeonfb_accessops = { 247 radeonfb_ioctl, 248 radeonfb_mmap, 249 NULL, /* vcons_alloc_screen */ 250 NULL, /* vcons_free_screen */ 251 NULL, /* vcons_show_screen */ 252 NULL, /* load_font */ 253 NULL, /* pollc */ 254 NULL, /* scroll */ 255 }; 256 257 static struct { 258 uint16_t devid; 259 uint16_t family; 260 uint16_t flags; 261 } radeonfb_devices[] = 262 { 263 /* R100 family */ 264 { PCI_PRODUCT_ATI_RADEON_R100_QD, RADEON_R100, 0 }, 265 { PCI_PRODUCT_ATI_RADEON_R100_QE, RADEON_R100, 0 }, 266 { PCI_PRODUCT_ATI_RADEON_R100_QF, RADEON_R100, 0 }, 267 { PCI_PRODUCT_ATI_RADEON_R100_QG, RADEON_R100, 0 }, 268 269 /* RV100 family */ 270 { PCI_PRODUCT_ATI_RADEON_RV100_LY, RADEON_RV100, RFB_MOB }, 271 { PCI_PRODUCT_ATI_RADEON_RV100_LZ, RADEON_RV100, RFB_MOB }, 272 { PCI_PRODUCT_ATI_RADEON_RV100_QY, RADEON_RV100, 0 }, 273 { PCI_PRODUCT_ATI_RADEON_RV100_QZ, RADEON_RV100, 0 }, 274 275 /* RS100 family */ 276 { PCI_PRODUCT_ATI_RADEON_RS100_4136, RADEON_RS100, 0 }, 277 { PCI_PRODUCT_ATI_RADEON_RS100_4336, RADEON_RS100, RFB_MOB }, 278 279 /* RS200/RS250 family */ 280 { PCI_PRODUCT_ATI_RADEON_RS200_4337, RADEON_RS200, RFB_MOB }, 281 { PCI_PRODUCT_ATI_RADEON_RS200_A7, RADEON_RS200, 0 }, 282 { PCI_PRODUCT_ATI_RADEON_RS250_B7, RADEON_RS200, RFB_MOB }, 283 { PCI_PRODUCT_ATI_RADEON_RS250_D7, RADEON_RS200, 0 }, 284 285 /* R200 family */ 286 /* add more R200 products? , 5148 */ 287 { PCI_PRODUCT_ATI_RADEON_R200_BB, RADEON_R200, 0 }, 288 { PCI_PRODUCT_ATI_RADEON_R200_BC, RADEON_R200, 0 }, 289 { PCI_PRODUCT_ATI_RADEON_R200_QH, RADEON_R200, 0 }, 290 { PCI_PRODUCT_ATI_RADEON_R200_QL, RADEON_R200, 0 }, 291 { PCI_PRODUCT_ATI_RADEON_R200_QM, RADEON_R200, 0 }, 292 293 /* RV200 family */ 294 { PCI_PRODUCT_ATI_RADEON_RV200_LW, RADEON_RV200, RFB_MOB }, 295 { PCI_PRODUCT_ATI_RADEON_RV200_LX, RADEON_RV200, RFB_MOB }, 296 { PCI_PRODUCT_ATI_RADEON_RV200_QW, RADEON_RV200, 0 }, 297 { PCI_PRODUCT_ATI_RADEON_RV200_QX, RADEON_RV200, 0 }, 298 299 /* RV250 family */ 300 { PCI_PRODUCT_ATI_RADEON_RV250_4966, RADEON_RV250, 0 }, 301 { PCI_PRODUCT_ATI_RADEON_RV250_4967, RADEON_RV250, 0 }, 302 { PCI_PRODUCT_ATI_RADEON_RV250_4C64, RADEON_RV250, RFB_MOB }, 303 { PCI_PRODUCT_ATI_RADEON_RV250_4C66, RADEON_RV250, RFB_MOB }, 304 { PCI_PRODUCT_ATI_RADEON_RV250_4C67, RADEON_RV250, RFB_MOB }, 305 306 /* RS300 family */ 307 { PCI_PRODUCT_ATI_RADEON_RS300_X5, RADEON_RS300, 0 }, 308 { PCI_PRODUCT_ATI_RADEON_RS300_X4, RADEON_RS300, 0 }, 309 { PCI_PRODUCT_ATI_RADEON_RS300_7834, RADEON_RS300, 0 }, 310 { PCI_PRODUCT_ATI_RADEON_RS300_7835, RADEON_RS300, RFB_MOB }, 311 312 /* RV280 family */ 313 { PCI_PRODUCT_ATI_RADEON_RV280_5960, RADEON_RV280, 0 }, 314 { PCI_PRODUCT_ATI_RADEON_RV280_5961, RADEON_RV280, 0 }, 315 { PCI_PRODUCT_ATI_RADEON_RV280_5962, RADEON_RV280, 0 }, 316 { PCI_PRODUCT_ATI_RADEON_RV280_5963, RADEON_RV280, 0 }, 317 { PCI_PRODUCT_ATI_RADEON_RV280_5964, RADEON_RV280, 0 }, 318 { PCI_PRODUCT_ATI_RADEON_RV280_5C61, RADEON_RV280, RFB_MOB }, 319 { PCI_PRODUCT_ATI_RADEON_RV280_5C63, RADEON_RV280, RFB_MOB }, 320 321 /* R300 family */ 322 { PCI_PRODUCT_ATI_RADEON_R300_AD, RADEON_R300, 0 }, 323 { PCI_PRODUCT_ATI_RADEON_R300_AE, RADEON_R300, 0 }, 324 { PCI_PRODUCT_ATI_RADEON_R300_AF, RADEON_R300, 0 }, 325 { PCI_PRODUCT_ATI_RADEON_R300_AG, RADEON_R300, 0 }, 326 { PCI_PRODUCT_ATI_RADEON_R300_ND, RADEON_R300, 0 }, 327 { PCI_PRODUCT_ATI_RADEON_R300_NE, RADEON_R300, 0 }, 328 { PCI_PRODUCT_ATI_RADEON_R300_NF, RADEON_R300, 0 }, 329 { PCI_PRODUCT_ATI_RADEON_R300_NG, RADEON_R300, 0 }, 330 331 /* RV350/RV360 family */ 332 { PCI_PRODUCT_ATI_RADEON_RV350_AP, RADEON_RV350, 0 }, 333 { PCI_PRODUCT_ATI_RADEON_RV350_AQ, RADEON_RV350, 0 }, 334 { PCI_PRODUCT_ATI_RADEON_RV360_AR, RADEON_RV350, 0 }, 335 { PCI_PRODUCT_ATI_RADEON_RV350_AS, RADEON_RV350, 0 }, 336 { PCI_PRODUCT_ATI_RADEON_RV350_AT, RADEON_RV350, 0 }, 337 { PCI_PRODUCT_ATI_RADEON_RV350_AV, RADEON_RV350, 0 }, 338 { PCI_PRODUCT_ATI_RADEON_RV350_NP, RADEON_RV350, RFB_MOB }, 339 { PCI_PRODUCT_ATI_RADEON_RV350_NQ, RADEON_RV350, RFB_MOB }, 340 { PCI_PRODUCT_ATI_RADEON_RV350_NR, RADEON_RV350, RFB_MOB }, 341 { PCI_PRODUCT_ATI_RADEON_RV350_NS, RADEON_RV350, RFB_MOB }, 342 { PCI_PRODUCT_ATI_RADEON_RV350_NT, RADEON_RV350, RFB_MOB }, 343 { PCI_PRODUCT_ATI_RADEON_RV350_NV, RADEON_RV350, RFB_MOB }, 344 345 /* R350/R360 family */ 346 { PCI_PRODUCT_ATI_RADEON_R350_AH, RADEON_R350, 0 }, 347 { PCI_PRODUCT_ATI_RADEON_R350_AI, RADEON_R350, 0 }, 348 { PCI_PRODUCT_ATI_RADEON_R350_AJ, RADEON_R350, 0 }, 349 { PCI_PRODUCT_ATI_RADEON_R350_AK, RADEON_R350, 0 }, 350 { PCI_PRODUCT_ATI_RADEON_R350_NH, RADEON_R350, 0 }, 351 { PCI_PRODUCT_ATI_RADEON_R350_NI, RADEON_R350, 0 }, 352 { PCI_PRODUCT_ATI_RADEON_R350_NK, RADEON_R350, 0 }, 353 { PCI_PRODUCT_ATI_RADEON_R360_NJ, RADEON_R350, 0 }, 354 355 /* RV380/RV370 family */ 356 { PCI_PRODUCT_ATI_RADEON_RV380_3150, RADEON_RV380, RFB_MOB }, 357 { PCI_PRODUCT_ATI_RADEON_RV380_3154, RADEON_RV380, RFB_MOB }, 358 { PCI_PRODUCT_ATI_RADEON_RV380_3E50, RADEON_RV380, 0 }, 359 { PCI_PRODUCT_ATI_RADEON_RV380_3E54, RADEON_RV380, 0 }, 360 { PCI_PRODUCT_ATI_RADEON_RV370_5460, RADEON_RV380, RFB_MOB }, 361 { PCI_PRODUCT_ATI_RADEON_RV370_5464, RADEON_RV380, RFB_MOB }, 362 { PCI_PRODUCT_ATI_RADEON_RV370_5B60, RADEON_RV380, 0 }, 363 { PCI_PRODUCT_ATI_RADEON_RV370_5B63, RADEON_RV380, 0 }, 364 { PCI_PRODUCT_ATI_RADEON_RV370_5B64, RADEON_RV380, 0 }, 365 { PCI_PRODUCT_ATI_RADEON_RV370_5B65, RADEON_RV380, 0 }, 366 367 #if notyet 368 /* R420/R423 family */ 369 { PCI_PRODUCT_ATI_RADEON_R420_JH, RADEON_R420, 0 }, 370 { PCI_PRODUCT_ATI_RADEON_R420_JI, RADEON_R420, 0 }, 371 { PCI_PRODUCT_ATI_RADEON_R420_JJ, RADEON_R420, 0 }, 372 { PCI_PRODUCT_ATI_RADEON_R420_JK, RADEON_R420, 0 }, 373 { PCI_PRODUCT_ATI_RADEON_R420_JL, RADEON_R420, 0 }, 374 { PCI_PRODUCT_ATI_RADEON_R420_JM, RADEON_R420, 0 }, 375 { PCI_PRODUCT_ATI_RADEON_R420_JN, RADEON_R420, RFB_MOB }, 376 { PCI_PRODUCT_ATI_RADEON_R420_JP, RADEON_R420, 0 }, 377 { PCI_PRODUCT_ATI_RADEON_R423_UH, RADEON_R420, 0 }, 378 { PCI_PRODUCT_ATI_RADEON_R423_UI, RADEON_R420, 0 }, 379 { PCI_PRODUCT_ATI_RADEON_R423_UJ, RADEON_R420, 0 }, 380 { PCI_PRODUCT_ATI_RADEON_R423_UK, RADEON_R420, 0 }, 381 { PCI_PRODUCT_ATI_RADEON_R423_UQ, RADEON_R420, 0 }, 382 { PCI_PRODUCT_ATI_RADEON_R423_UR, RADEON_R420, 0 }, 383 { PCI_PRODUCT_ATI_RADEON_R423_UT, RADEON_R420, 0 }, 384 { PCI_PRODUCT_ATI_RADEON_R423_5D57, RADEON_R420, 0 }, 385 { PCI_PRODUCT_ATI_RADEON_R430_554F, RADEON_R420, 0 }, 386 #endif 387 388 /* R5xx family */ 389 { 0x7240, RADEON_R580, RFB_IS_AVIVO }, 390 { 0, 0, 0 } 391 }; 392 393 static struct { 394 int divider; 395 int mask; 396 } radeonfb_dividers[] = { 397 { 16, 5 }, 398 { 12, 7 }, 399 { 8, 3 }, 400 { 6, 6 }, 401 { 4, 2 }, 402 { 3, 4 }, 403 { 2, 1 }, 404 { 1, 0 }, 405 { 0, 0 } 406 }; 407 408 /* 409 * This table taken from X11. 410 */ 411 static const struct { 412 int family; 413 struct radeon_tmds_pll plls[4]; 414 } radeonfb_tmds_pll[] = { 415 { RADEON_R100, {{12000, 0xa1b}, {-1, 0xa3f}}}, 416 { RADEON_RV100, {{12000, 0xa1b}, {-1, 0xa3f}}}, 417 { RADEON_RS100, {{0, 0}}}, 418 { RADEON_RV200, {{15000, 0xa1b}, {-1, 0xa3f}}}, 419 { RADEON_RS200, {{15000, 0xa1b}, {-1, 0xa3f}}}, 420 { RADEON_R200, {{15000, 0xa1b}, {-1, 0xa3f}}}, 421 { RADEON_RV250, {{15500, 0x81b}, {-1, 0x83f}}}, 422 { RADEON_RS300, {{0, 0}}}, 423 { RADEON_RV280, {{13000, 0x400f4}, {15000, 0x400f7}, {-1, 0x40111}}}, 424 { RADEON_R300, {{-1, 0xb01cb}}}, 425 { RADEON_R350, {{-1, 0xb01cb}}}, 426 { RADEON_RV350, {{15000, 0xb0155}, {-1, 0xb01cb}}}, 427 { RADEON_RV380, {{15000, 0xb0155}, {-1, 0xb01cb}}}, 428 { RADEON_R420, {{-1, 0xb01cb}}}, 429 { RADEON_R580, {{-1, 0xb01cb}}}, /* XXX likely bogus */ 430 }; 431 432 #define RADEONFB_BACKLIGHT_MAX 255 /* Maximum backlight level. */ 433 434 435 CFATTACH_DECL_NEW(radeonfb, sizeof (struct radeonfb_softc), 436 radeonfb_match, radeonfb_attach, NULL, NULL); 437 438 static int 439 radeonfb_match(device_t parent, cfdata_t match, void *aux) 440 { 441 const struct pci_attach_args *pa = aux; 442 int i; 443 444 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_ATI) 445 return 0; 446 447 for (i = 0; radeonfb_devices[i].devid; i++) { 448 if (PCI_PRODUCT(pa->pa_id) == radeonfb_devices[i].devid) 449 return 100; /* high to defeat VGA/VESA */ 450 } 451 452 return 0; 453 } 454 455 static void 456 radeonfb_attach(device_t parent, device_t dev, void *aux) 457 { 458 struct radeonfb_softc *sc = device_private(dev); 459 const struct pci_attach_args *pa = aux; 460 const char *mptr; 461 bus_size_t bsz; 462 pcireg_t screg; 463 int i, j, fg, bg, ul, flags; 464 uint32_t v; 465 466 sc->sc_dev = dev; 467 sc->sc_id = pa->pa_id; 468 for (i = 0; radeonfb_devices[i].devid; i++) { 469 if (PCI_PRODUCT(sc->sc_id) == radeonfb_devices[i].devid) 470 break; 471 } 472 473 pci_aprint_devinfo(pa, NULL); 474 475 DPRINTF(("%s", prop_dictionary_externalize(device_properties(dev)))); 476 477 KASSERT(radeonfb_devices[i].devid != 0); 478 sc->sc_pt = pa->pa_tag; 479 sc->sc_iot = pa->pa_iot; 480 sc->sc_pc = pa->pa_pc; 481 sc->sc_family = radeonfb_devices[i].family; 482 sc->sc_flags = radeonfb_devices[i].flags; 483 sc->sc_bios = NULL; 484 sc->sc_biossz = 0; 485 486 /* enable memory and IO access */ 487 screg = pci_conf_read(sc->sc_pc, sc->sc_pt, PCI_COMMAND_STATUS_REG); 488 screg |= PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE; 489 pci_conf_write(sc->sc_pc, sc->sc_pt, PCI_COMMAND_STATUS_REG, screg); 490 491 /* 492 * Some flags are general to entire chip families, and rather 493 * than clutter up the table with them, we go ahead and set 494 * them here. 495 */ 496 switch (sc->sc_family) { 497 case RADEON_RS100: 498 case RADEON_RS200: 499 sc->sc_flags |= RFB_IGP | RFB_RV100; 500 break; 501 502 case RADEON_RV100: 503 case RADEON_RV200: 504 case RADEON_RV250: 505 case RADEON_RV280: 506 sc->sc_flags |= RFB_RV100; 507 break; 508 509 case RADEON_RS300: 510 sc->sc_flags |= RFB_SDAC | RFB_IGP | RFB_RV100; 511 break; 512 513 case RADEON_R300: 514 case RADEON_RV350: 515 case RADEON_R350: 516 case RADEON_RV380: 517 case RADEON_R420: 518 case RADEON_R580: 519 /* newer chips */ 520 sc->sc_flags |= RFB_R300; 521 break; 522 523 case RADEON_R100: 524 sc->sc_flags |= RFB_NCRTC2; 525 break; 526 } 527 528 if ((sc->sc_family == RADEON_RV200) || 529 (sc->sc_family == RADEON_RV250) || 530 (sc->sc_family == RADEON_RV280) || 531 (sc->sc_family == RADEON_RV350)) { 532 bool inverted = 0; 533 /* backlight level is linear */ 534 DPRINTF(("found RV* chip, backlight is supposedly linear\n")); 535 prop_dictionary_get_bool(device_properties(sc->sc_dev), 536 "backlight_level_reverted", &inverted); 537 if (inverted) { 538 DPRINTF(("nope, it's inverted\n")); 539 sc->sc_flags |= RFB_INV_BLIGHT; 540 } 541 } else 542 sc->sc_flags |= RFB_INV_BLIGHT; 543 544 /* 545 * XXX: to support true multihead, this must change. 546 */ 547 sc->sc_ndisplays = 1; 548 549 /* XXX: */ 550 if (!HAS_CRTC2(sc)) { 551 sc->sc_ndisplays = 1; 552 } 553 554 if (pci_mapreg_map(pa, RADEON_MAPREG_MMIO, PCI_MAPREG_TYPE_MEM, 0, 555 &sc->sc_regt, &sc->sc_regh, &sc->sc_regaddr, 556 &sc->sc_regsz) != 0) { 557 aprint_error("%s: unable to map registers!\n", XNAME(sc)); 558 goto error; 559 } 560 561 if (pci_mapreg_info(sc->sc_pc, sc->sc_pt, PCI_MAPREG_ROM, 562 PCI_MAPREG_TYPE_ROM, &sc->sc_romaddr, &sc->sc_romsz, &flags) != 0) 563 { 564 aprint_error("%s: unable to find ROM!\n", XNAME(sc)); 565 goto error; 566 } 567 sc->sc_romt = sc->sc_memt; 568 569 sc->sc_mapped = TRUE; 570 571 /* scratch register test... */ 572 if (radeonfb_scratch_test(sc, RADEON_BIOS_0_SCRATCH, 0x55555555) || 573 radeonfb_scratch_test(sc, RADEON_BIOS_0_SCRATCH, 0xaaaaaaaa)) { 574 aprint_error("%s: scratch register test failed!\n", XNAME(sc)); 575 goto error; 576 } 577 578 PRINTREG(RADEON_CRTC_EXT_CNTL); 579 PRINTREG(RADEON_CRTC_GEN_CNTL); 580 PRINTREG(RADEON_CRTC2_GEN_CNTL); 581 PRINTREG(RADEON_DISP_OUTPUT_CNTL); 582 PRINTREG(RADEON_DAC_CNTL2); 583 PRINTREG(RADEON_BIOS_4_SCRATCH); 584 PRINTREG(RADEON_FP_GEN_CNTL); 585 sc->sc_fp_gen_cntl = GET32(sc, RADEON_FP_GEN_CNTL); 586 PRINTREG(RADEON_FP2_GEN_CNTL); 587 PRINTREG(RADEON_TMDS_CNTL); 588 PRINTREG(RADEON_TMDS_TRANSMITTER_CNTL); 589 PRINTREG(RADEON_TMDS_PLL_CNTL); 590 PRINTREG(RADEON_LVDS_GEN_CNTL); 591 PRINTREG(RADEON_DISP_HW_DEBUG); 592 if (!IS_AVIVO(sc)) { 593 /* 594 XXX: We can't print this, as it's not correctly aligned 595 PRINTREG(RADEON_PIXCLKS_CNTL); 596 */ 597 PRINTREG(RADEON_CRTC_H_SYNC_STRT_WID); 598 PRINTREG(RADEON_FP_H_SYNC_STRT_WID); 599 PRINTREG(RADEON_CRTC2_H_SYNC_STRT_WID); 600 PRINTREG(RADEON_FP_H2_SYNC_STRT_WID); 601 } 602 /* 603 * XXX 604 * This was if (IS_RV100()), which is set for all pre-R3xx chips. 605 * I suspect this only makes sense on Sun XVR-100 with firmware that doesn't 606 * support DVI, so for now let's restrict it to only actual RV100 607 */ 608 if (sc->sc_family == RADEON_RV100) 609 PUT32(sc, RADEON_TMDS_PLL_CNTL, 0xa27); 610 611 /* XXX 612 * according to xf86-video-radeon R3xx has this bit backwards 613 */ 614 if (IS_R300(sc)) { 615 PATCH32(sc, RADEON_TMDS_TRANSMITTER_CNTL, 616 0, 617 ~(RADEON_TMDS_TRANSMITTER_PLLEN | RADEON_TMDS_TRANSMITTER_PLLRST)); 618 } else { 619 PATCH32(sc, RADEON_TMDS_TRANSMITTER_CNTL, 620 RADEON_TMDS_TRANSMITTER_PLLEN, 621 ~(RADEON_TMDS_TRANSMITTER_PLLEN | RADEON_TMDS_TRANSMITTER_PLLRST)); 622 } 623 624 radeonfb_i2c_init(sc); 625 626 radeonfb_loadbios(sc, pa); 627 628 #ifdef RADEONFB_BIOS_INIT 629 if (radeonfb_bios_init(sc)) { 630 aprint_error("%s: BIOS inititialization failed\n", XNAME(sc)); 631 } 632 #endif 633 634 if (radeonfb_getclocks(sc)) { 635 aprint_error("%s: Unable to get reference clocks from BIOS\n", 636 XNAME(sc)); 637 goto error; 638 } 639 640 if (radeonfb_gettmds(sc)) { 641 aprint_error("%s: Unable to identify TMDS PLL settings\n", 642 XNAME(sc)); 643 goto error; 644 } 645 646 aprint_verbose("%s: refclk = %d.%03d MHz, refdiv = %d " 647 "minpll = %d, maxpll = %d\n", XNAME(sc), 648 (int)sc->sc_refclk / 1000, (int)sc->sc_refclk % 1000, 649 (int)sc->sc_refdiv, (int)sc->sc_minpll, (int)sc->sc_maxpll); 650 651 radeonfb_getconnectors(sc); 652 653 radeonfb_set_fbloc(sc); 654 655 /* 64 MB should be enough -- more just wastes map entries */ 656 if (sc->sc_memsz > (64 << 20)) 657 sc->sc_memsz = (64 << 20); 658 659 for (i = 0; radeonfb_limits[i].size; i++) { 660 if (sc->sc_memsz >= radeonfb_limits[i].size) { 661 sc->sc_maxx = radeonfb_limits[i].maxx; 662 sc->sc_maxy = radeonfb_limits[i].maxy; 663 sc->sc_maxbpp = radeonfb_limits[i].maxbpp; 664 /* framebuffer offset, start at a 4K page */ 665 sc->sc_fboffset = sc->sc_memsz / 666 radeonfb_limits[i].maxdisp; 667 /* 668 * we use the fbsize to figure out where we can store 669 * things like cursor data. 670 */ 671 sc->sc_fbsize = 672 ROUNDUP(ROUNDUP(sc->sc_maxx * sc->sc_maxbpp / 8 , 673 RADEON_STRIDEALIGN) * sc->sc_maxy, 674 4096); 675 break; 676 } 677 } 678 679 680 radeonfb_init_misc(sc); 681 682 /* program the DAC wirings */ 683 for (i = 0; i < (HAS_CRTC2(sc) ? 2 : 1); i++) { 684 switch (sc->sc_ports[i].rp_dac_type) { 685 case RADEON_DAC_PRIMARY: 686 PATCH32(sc, RADEON_DAC_CNTL2, 687 i ? RADEON_DAC2_DAC_CLK_SEL : 0, 688 ~RADEON_DAC2_DAC_CLK_SEL); 689 break; 690 case RADEON_DAC_TVDAC: 691 /* we always use the TVDAC to drive a secondary analog 692 * CRT for now. if we ever support TV-out this will 693 * have to change. 694 */ 695 SET32(sc, RADEON_DAC_CNTL2, 696 RADEON_DAC2_DAC2_CLK_SEL); 697 PATCH32(sc, RADEON_DISP_HW_DEBUG, 698 i ? 0 : RADEON_CRT2_DISP1_SEL, 699 ~RADEON_CRT2_DISP1_SEL); 700 /* we're using CRTC2 for the 2nd port */ 701 if (sc->sc_ports[i].rp_number == 1) { 702 PATCH32(sc, RADEON_DISP_OUTPUT_CNTL, 703 RADEON_DISP_DAC2_SOURCE_CRTC2, 704 ~RADEON_DISP_DAC2_SOURCE_MASK); 705 } 706 707 break; 708 } 709 DPRINTF(("%s: port %d tmds type %d\n", __func__, i, 710 sc->sc_ports[i].rp_tmds_type)); 711 switch (sc->sc_ports[i].rp_tmds_type) { 712 case RADEON_TMDS_INT: 713 /* point FP0 at the CRTC this port uses */ 714 DPRINTF(("%s: plugging internal TMDS into CRTC %d\n", 715 __func__, sc->sc_ports[i].rp_number)); 716 if (IS_R300(sc)) { 717 PATCH32(sc, RADEON_FP_GEN_CNTL, 718 sc->sc_ports[i].rp_number ? 719 R200_FP_SOURCE_SEL_CRTC2 : 720 R200_FP_SOURCE_SEL_CRTC1, 721 ~R200_FP_SOURCE_SEL_MASK); 722 } else { 723 PATCH32(sc, RADEON_FP_GEN_CNTL, 724 sc->sc_ports[i].rp_number ? 725 RADEON_FP_SEL_CRTC2 : 726 RADEON_FP_SEL_CRTC1, 727 ~RADEON_FP_SEL_MASK); 728 } 729 break; 730 case RADEON_TMDS_EXT: 731 /* point FP2 at the CRTC this port uses */ 732 DPRINTF(("%s: plugging external TMDS into CRTC %d\n", 733 __func__, sc->sc_ports[i].rp_number)); 734 if (IS_R300(sc)) { 735 PATCH32(sc, RADEON_FP2_GEN_CNTL, 736 sc->sc_ports[i].rp_number ? 737 R200_FP2_SOURCE_SEL_CRTC2 : 738 R200_FP2_SOURCE_SEL_CRTC1, 739 ~R200_FP2_SOURCE_SEL_CRTC2); 740 } else { 741 PATCH32(sc, RADEON_FP2_GEN_CNTL, 742 sc->sc_ports[i].rp_number ? 743 RADEON_FP2_SRC_SEL_CRTC2 : 744 RADEON_FP2_SRC_SEL_CRTC1, 745 ~RADEON_FP2_SRC_SEL_CRTC2); 746 } 747 break; 748 } 749 } 750 PRINTREG(RADEON_DAC_CNTL2); 751 PRINTREG(RADEON_DISP_HW_DEBUG); 752 753 PRINTREG(RADEON_DAC_CNTL); 754 /* other DAC programming */ 755 v = GET32(sc, RADEON_DAC_CNTL); 756 v &= (RADEON_DAC_RANGE_CNTL_MASK | RADEON_DAC_BLANKING); 757 v |= RADEON_DAC_MASK_ALL | RADEON_DAC_8BIT_EN; 758 PUT32(sc, RADEON_DAC_CNTL, v); 759 PRINTREG(RADEON_DAC_CNTL); 760 761 /* XXX: this may need more investigation */ 762 PUT32(sc, RADEON_TV_DAC_CNTL, 0x00280203); 763 PRINTREG(RADEON_TV_DAC_CNTL); 764 765 /* enable TMDS */ 766 SET32(sc, RADEON_FP_GEN_CNTL, 767 RADEON_FP_TMDS_EN | 768 RADEON_FP_CRTC_DONT_SHADOW_VPAR | 769 RADEON_FP_CRTC_DONT_SHADOW_HEND); 770 /* 771 * XXX 772 * no idea why this is necessary - if I do not clear this bit on my 773 * iBook G4 the screen remains black, even though it's already clear. 774 * It needs to be set on my Sun XVR-100 for the DVI port to work 775 * TODO: 776 * see if this is still necessary now that CRTCs, DACs and outputs are 777 * getting wired up in a halfway sane way 778 */ 779 if (sc->sc_fp_gen_cntl & RADEON_FP_SEL_CRTC2) { 780 SET32(sc, RADEON_FP_GEN_CNTL, RADEON_FP_SEL_CRTC2); 781 } else { 782 CLR32(sc, RADEON_FP_GEN_CNTL, RADEON_FP_SEL_CRTC2); 783 } 784 785 /* 786 * we use bus_space_map instead of pci_mapreg, because we don't 787 * need the full aperature space. no point in wasting virtual 788 * address space we don't intend to use, right? 789 */ 790 if ((sc->sc_memsz < (4096 * 1024)) || 791 (pci_mapreg_info(sc->sc_pc, sc->sc_pt, RADEON_MAPREG_VRAM, 792 PCI_MAPREG_TYPE_MEM, &sc->sc_memaddr, &bsz, NULL) != 0) || 793 (bsz < sc->sc_memsz)) { 794 sc->sc_memsz = 0; 795 aprint_error("%s: Bad frame buffer configuration\n", 796 XNAME(sc)); 797 goto error; 798 } 799 800 sc->sc_memt = pa->pa_memt; 801 if (bus_space_map(sc->sc_memt, sc->sc_memaddr, sc->sc_memsz, 802 BUS_SPACE_MAP_LINEAR, &sc->sc_memh) != 0) { 803 sc->sc_memsz = 0; 804 aprint_error("%s: Unable to map frame buffer\n", XNAME(sc)); 805 goto error; 806 } 807 808 aprint_normal("%s: %d MB aperture at 0x%08x, " 809 "%d KB registers at 0x%08x\n", XNAME(sc), 810 (int)sc->sc_memsz >> 20, (unsigned)sc->sc_memaddr, 811 (int)sc->sc_regsz >> 10, (unsigned)sc->sc_regaddr); 812 813 /* setup default video mode from devprop (allows PROM override) */ 814 sc->sc_defaultmode = radeonfb_default_mode; 815 if (prop_dictionary_get_string(device_properties(sc->sc_dev), 816 "videomode", &mptr)) { 817 818 strncpy(sc->sc_modebuf, mptr, sizeof(sc->sc_modebuf)); 819 sc->sc_defaultmode = sc->sc_modebuf; 820 } 821 822 /* initialize some basic display parameters */ 823 for (i = 0; i < sc->sc_ndisplays; i++) { 824 struct radeonfb_display *dp = &sc->sc_displays[i]; 825 struct rasops_info *ri; 826 long defattr; 827 struct wsemuldisplaydev_attach_args aa; 828 829 /* 830 * Figure out how many "displays" (desktops) we are going to 831 * support. If more than one, then each CRTC gets its own 832 * programming. 833 * 834 * XXX: this code needs to change to support mergedfb. 835 * XXX: would be nice to allow this to be overridden 836 */ 837 if (HAS_CRTC2(sc) && (sc->sc_ndisplays == 1)) { 838 DPRINTF(("dual crtcs!\n")); 839 dp->rd_ncrtcs = 2; 840 dp->rd_crtcs[0].rc_port = 841 &sc->sc_ports[0]; 842 dp->rd_crtcs[0].rc_number = sc->sc_ports[0].rp_number; 843 dp->rd_crtcs[1].rc_port = 844 &sc->sc_ports[1]; 845 dp->rd_crtcs[1].rc_number = sc->sc_ports[1].rp_number; 846 } else { 847 dp->rd_ncrtcs = 1; 848 dp->rd_crtcs[0].rc_port = 849 &sc->sc_ports[i]; 850 dp->rd_crtcs[0].rc_number = sc->sc_ports[i].rp_number; 851 } 852 853 dp->rd_softc = sc; 854 dp->rd_wsmode = WSDISPLAYIO_MODE_EMUL; 855 dp->rd_bpp = RADEONFB_DEFAULT_DEPTH; /* XXX */ 856 857 /* for text mode, we pick a resolution that won't 858 * require panning */ 859 radeonfb_pickres(dp, &dp->rd_virtx, &dp->rd_virty, 0); 860 861 aprint_normal("%s: display %d: " 862 "initial virtual resolution %dx%d at %d bpp\n", 863 XNAME(sc), i, dp->rd_virtx, dp->rd_virty, dp->rd_bpp); 864 aprint_normal_dev(sc->sc_dev, "using %d MB per display\n", 865 sc->sc_fboffset >> 20); 866 /* now select the *video mode* that we will use */ 867 for (j = 0; j < dp->rd_ncrtcs; j++) { 868 const struct videomode *vmp; 869 vmp = radeonfb_port_mode(sc, dp->rd_crtcs[j].rc_port, 870 dp->rd_virtx, dp->rd_virty); 871 872 /* 873 * virtual resolution should be at least as high as 874 * physical 875 */ 876 if (dp->rd_virtx < vmp->hdisplay || 877 dp->rd_virty < vmp->vdisplay) { 878 dp->rd_virtx = vmp->hdisplay; 879 dp->rd_virty = vmp->vdisplay; 880 } 881 882 dp->rd_crtcs[j].rc_videomode = *vmp; 883 printf("%s: port %d: physical %dx%d %dHz\n", 884 XNAME(sc), j, vmp->hdisplay, vmp->vdisplay, 885 DIVIDE(DIVIDE(vmp->dot_clock * 1000, 886 vmp->htotal), vmp->vtotal)); 887 } 888 889 /* N.B.: radeon wants 64-byte aligned stride */ 890 dp->rd_stride = dp->rd_virtx * dp->rd_bpp / 8; 891 dp->rd_stride = ROUNDUP(dp->rd_stride, RADEON_STRIDEALIGN); 892 893 dp->rd_offset = sc->sc_fboffset * i; 894 dp->rd_fbptr = (vaddr_t)bus_space_vaddr(sc->sc_memt, 895 sc->sc_memh) + dp->rd_offset; 896 dp->rd_curoff = sc->sc_fboffset - 16384; /* 16KB cursor space */ 897 dp->rd_curptr = dp->rd_fbptr + dp->rd_curoff; 898 899 DPRINTF(("fpbtr = %p\n", (void *)dp->rd_fbptr)); 900 901 switch (dp->rd_bpp) { 902 case 8: 903 dp->rd_format = 2; 904 break; 905 case 32: 906 dp->rd_format = 6; 907 break; 908 default: 909 aprint_error("%s: bad depth %d\n", XNAME(sc), 910 dp->rd_bpp); 911 goto error; 912 } 913 DPRINTF(("init engine\n")); 914 /* XXX: this seems suspicious - per display engine 915 initialization? */ 916 917 radeonfb_modeswitch(dp); 918 radeonfb_engine_init(dp); 919 920 /* copy the template into place */ 921 dp->rd_wsscreens_storage[0] = radeonfb_stdscreen; 922 dp->rd_wsscreens = dp->rd_wsscreens_storage; 923 924 /* and make up the list */ 925 dp->rd_wsscreenlist.nscreens = 1; 926 dp->rd_wsscreenlist.screens = (void *)&dp->rd_wsscreens; 927 928 vcons_init(&dp->rd_vd, dp, dp->rd_wsscreens, 929 &radeonfb_accessops); 930 931 dp->rd_vd.init_screen = radeonfb_init_screen; 932 933 dp->rd_console = 0; 934 prop_dictionary_get_bool(device_properties(sc->sc_dev), 935 "is_console", &dp->rd_console); 936 937 dp->rd_vscreen.scr_flags |= VCONS_SCREEN_IS_STATIC; 938 939 940 vcons_init_screen(&dp->rd_vd, &dp->rd_vscreen, 941 dp->rd_console, &defattr); 942 943 ri = &dp->rd_vscreen.scr_ri; 944 945 /* clear the screen */ 946 rasops_unpack_attr(defattr, &fg, &bg, &ul); 947 dp->rd_bg = ri->ri_devcmap[bg & 0xf]; 948 radeonfb_rectfill(dp, 0, 0, ri->ri_width, ri->ri_height, 949 dp->rd_bg); 950 951 dp->rd_wsscreens->textops = &ri->ri_ops; 952 dp->rd_wsscreens->capabilities = ri->ri_caps; 953 dp->rd_wsscreens->nrows = ri->ri_rows; 954 dp->rd_wsscreens->ncols = ri->ri_cols; 955 956 #ifdef SPLASHSCREEN 957 dp->rd_splash.si_depth = ri->ri_depth; 958 dp->rd_splash.si_bits = ri->ri_bits; 959 dp->rd_splash.si_hwbits = ri->ri_hwbits; 960 dp->rd_splash.si_width = ri->ri_width; 961 dp->rd_splash.si_height = ri->ri_height; 962 dp->rd_splash.si_stride = ri->ri_stride; 963 dp->rd_splash.si_fillrect = NULL; 964 #endif 965 dp->rd_gc.gc_bitblt = radeonfb_bitblt; 966 dp->rd_gc.gc_rectfill = radeonfb_rectfill_a; 967 dp->rd_gc.gc_rop = RADEON_ROP3_S; 968 dp->rd_gc.gc_blitcookie = dp; 969 /* 970 * use memory between framebuffer and cursor area as glyph 971 * cache, cap at 4096 lines 972 */ 973 glyphcache_init(&dp->rd_gc, dp->rd_virty + 4, 974 uimin(4096, 975 (dp->rd_curoff / dp->rd_stride) - (dp->rd_virty + 4)), 976 dp->rd_virtx, 977 ri->ri_font->fontwidth, 978 ri->ri_font->fontheight, 979 defattr); 980 dp->rd_vd.show_screen_cookie = &dp->rd_gc; 981 dp->rd_vd.show_screen_cb = glyphcache_adapt; 982 983 if (dp->rd_console) { 984 985 wsdisplay_cnattach(dp->rd_wsscreens, ri, 0, 0, 986 defattr); 987 #ifdef SPLASHSCREEN 988 if (splash_render(&dp->rd_splash, 989 SPLASH_F_CENTER|SPLASH_F_FILL) == 0) 990 SCREEN_DISABLE_DRAWING(&dp->rd_vscreen); 991 else 992 #endif 993 vcons_replay_msgbuf(&dp->rd_vscreen); 994 } else { 995 996 /* 997 * since we're not the console we can postpone 998 * the rest until someone actually allocates a 999 * screen for us. but we do clear the screen 1000 * at least. 1001 */ 1002 memset(ri->ri_bits, 0, 1024); 1003 1004 #ifdef SPLASHSCREEN 1005 if (splash_render(&dp->rd_splash, 1006 SPLASH_F_CENTER|SPLASH_F_FILL) == 0) 1007 SCREEN_DISABLE_DRAWING(&dp->rd_vscreen); 1008 #endif 1009 } 1010 1011 aa.console = dp->rd_console; 1012 aa.scrdata = &dp->rd_wsscreenlist; 1013 aa.accessops = &radeonfb_accessops; 1014 aa.accesscookie = &dp->rd_vd; 1015 1016 config_found(sc->sc_dev, &aa, wsemuldisplaydevprint, 1017 CFARGS(.iattr = "wsemuldisplaydev")); 1018 1019 radeonfb_blank(dp, 0); 1020 1021 /* Initialise delayed lvds operations for backlight. */ 1022 callout_init(&dp->rd_bl_lvds_co, 0); 1023 callout_setfunc(&dp->rd_bl_lvds_co, 1024 radeonfb_lvds_callout, dp); 1025 1026 dp->rd_bl_on = 1; 1027 if (sc->sc_flags & RFB_MOB) { 1028 dp->rd_bl_level = radeonfb_get_backlight(dp); 1029 } else 1030 dp->rd_bl_level = 128; 1031 1032 radeonfb_set_backlight(dp, dp->rd_bl_level); 1033 } 1034 for (i = 0; i < RADEON_NDISPLAYS; i++) 1035 radeonfb_init_palette(&sc->sc_displays[i]); 1036 1037 if (HAS_CRTC2(sc) && !IS_AVIVO(sc)) { 1038 CLR32(sc, RADEON_CRTC2_GEN_CNTL, RADEON_CRTC2_DISP_DIS); 1039 } 1040 1041 if (!IS_AVIVO(sc)) { 1042 CLR32(sc, RADEON_CRTC_EXT_CNTL, RADEON_CRTC_DISPLAY_DIS); 1043 SET32(sc, RADEON_FP_GEN_CNTL, RADEON_FP_FPON); 1044 } 1045 1046 pmf_event_register(dev, PMFE_DISPLAY_BRIGHTNESS_UP, 1047 radeonfb_brightness_up, TRUE); 1048 pmf_event_register(dev, PMFE_DISPLAY_BRIGHTNESS_DOWN, 1049 radeonfb_brightness_down, TRUE); 1050 1051 /* 1052 * if we attach a DRM we need to unmap registers in 1053 * WSDISPLAYIO_MODE_MAPPED, since this keeps us from doing things like 1054 * screen blanking we only do it if needed 1055 */ 1056 sc->sc_needs_unmap = 1057 (config_found(dev, aux, radeonfb_drm_print, 1058 CFARGS(.iattr = "drm")) != NULL); 1059 DPRINTF(("needs_unmap: %d\n", sc->sc_needs_unmap)); 1060 1061 if (!IS_AVIVO(sc)) { 1062 PRINTREG(RADEON_CRTC_EXT_CNTL); 1063 PRINTREG(RADEON_CRTC_GEN_CNTL); 1064 PRINTREG(RADEON_CRTC2_GEN_CNTL); 1065 PRINTREG(RADEON_DISP_OUTPUT_CNTL); 1066 PRINTREG(RADEON_DAC_CNTL2); 1067 PRINTREG(RADEON_FP_GEN_CNTL); 1068 PRINTREG(RADEON_FP2_GEN_CNTL); 1069 PRINTREG(RADEON_TMDS_CNTL); 1070 PRINTREG(RADEON_TMDS_TRANSMITTER_CNTL); 1071 PRINTREG(RADEON_TMDS_PLL_CNTL); 1072 /* 1073 XXX: We can't print this, as it's not correctly aligned 1074 PRINTREG(RADEON_PIXCLKS_CNTL); 1075 */ 1076 } 1077 return; 1078 1079 error: 1080 if (sc->sc_biossz) 1081 free(sc->sc_bios, M_DEVBUF); 1082 1083 if (sc->sc_regsz) 1084 bus_space_unmap(sc->sc_regt, sc->sc_regh, sc->sc_regsz); 1085 1086 if (sc->sc_memsz) 1087 bus_space_unmap(sc->sc_memt, sc->sc_memh, sc->sc_memsz); 1088 } 1089 1090 static void 1091 radeonfb_map(struct radeonfb_softc *sc) 1092 { 1093 if (!sc->sc_mapped) { 1094 if (bus_space_map(sc->sc_regt, sc->sc_regaddr, sc->sc_regsz, 0, 1095 &sc->sc_regh) != 0) { 1096 aprint_error_dev(sc->sc_dev, 1097 "unable to map registers!\n"); 1098 return; 1099 } 1100 if (bus_space_map(sc->sc_memt, sc->sc_memaddr, sc->sc_memsz, 1101 BUS_SPACE_MAP_LINEAR, &sc->sc_memh) != 0) { 1102 sc->sc_memsz = 0; 1103 aprint_error_dev(sc->sc_dev, 1104 "Unable to map frame buffer\n"); 1105 return; 1106 } 1107 sc->sc_mapped = TRUE; 1108 } 1109 } 1110 1111 static void 1112 radeonfb_unmap(struct radeonfb_softc *sc) 1113 { 1114 if (!sc->sc_needs_unmap) 1115 return; 1116 1117 if (sc->sc_mapped) { 1118 bus_space_unmap(sc->sc_regt, sc->sc_regh, sc->sc_regsz); 1119 bus_space_unmap(sc->sc_memt, sc->sc_memh, sc->sc_memsz); 1120 sc->sc_mapped = FALSE; 1121 } 1122 } 1123 1124 static int 1125 radeonfb_drm_print(void *aux, const char *pnp) 1126 { 1127 if (pnp) 1128 aprint_normal("drm at %s", pnp); 1129 return (UNCONF); 1130 } 1131 1132 int 1133 radeonfb_ioctl(void *v, void *vs, 1134 unsigned long cmd, void *d, int flag, struct lwp *l) 1135 { 1136 struct vcons_data *vd; 1137 struct radeonfb_display *dp; 1138 struct radeonfb_softc *sc; 1139 struct wsdisplay_param *param; 1140 struct vcons_screen *ms; 1141 1142 vd = (struct vcons_data *)v; 1143 ms = vd->active; 1144 dp = (struct radeonfb_display *)vd->cookie; 1145 sc = dp->rd_softc; 1146 1147 /* can't do these without registers being mapped */ 1148 if (!sc->sc_mapped) { 1149 switch (cmd) { 1150 case WSDISPLAYIO_GVIDEO: 1151 case WSDISPLAYIO_SVIDEO: 1152 case WSDISPLAYIO_GETCMAP: 1153 case WSDISPLAYIO_PUTCMAP: 1154 case WSDISPLAYIO_SCURSOR: 1155 case WSDISPLAYIO_GCURPOS: 1156 case WSDISPLAYIO_SCURPOS: 1157 case WSDISPLAYIO_SETPARAM: 1158 return EINVAL; 1159 } 1160 } 1161 1162 switch (cmd) { 1163 case WSDISPLAYIO_GTYPE: 1164 *(unsigned *)d = WSDISPLAY_TYPE_PCIMISC; 1165 return 0; 1166 1167 case WSDISPLAYIO_GINFO: 1168 if (vd->active != NULL) { 1169 struct wsdisplay_fbinfo *fb; 1170 fb = (struct wsdisplay_fbinfo *)d; 1171 fb->width = dp->rd_virtx; 1172 fb->height = dp->rd_virty; 1173 fb->depth = dp->rd_bpp; 1174 fb->cmsize = 256; 1175 return 0; 1176 } else 1177 return ENODEV; 1178 case WSDISPLAYIO_GVIDEO: 1179 if (radeonfb_isblank(dp)) 1180 *(unsigned *)d = WSDISPLAYIO_VIDEO_OFF; 1181 else 1182 *(unsigned *)d = WSDISPLAYIO_VIDEO_ON; 1183 return 0; 1184 1185 case WSDISPLAYIO_SVIDEO: 1186 if (dp->rd_wsmode != WSDISPLAYIO_MODE_MAPPED) { 1187 radeonfb_blank(dp, 1188 (*(unsigned int *)d == WSDISPLAYIO_VIDEO_OFF)); 1189 radeonfb_switch_backlight(dp, 1190 (*(unsigned int *)d == WSDISPLAYIO_VIDEO_ON)); 1191 } 1192 pmf_event_inject(NULL, 1193 (*(unsigned int *)d == WSDISPLAYIO_VIDEO_ON) ? 1194 PMFE_DISPLAY_ON : PMFE_DISPLAY_OFF); 1195 return 0; 1196 1197 case WSDISPLAYIO_GETCMAP: 1198 if (dp->rd_bpp == 8) 1199 return radeonfb_getcmap(dp, 1200 (struct wsdisplay_cmap *)d); 1201 return EINVAL; 1202 1203 case WSDISPLAYIO_PUTCMAP: 1204 if (dp->rd_bpp == 8) 1205 return radeonfb_putcmap(dp, 1206 (struct wsdisplay_cmap *)d); 1207 return EINVAL; 1208 1209 case WSDISPLAYIO_LINEBYTES: 1210 *(unsigned *)d = dp->rd_stride; 1211 return 0; 1212 1213 case WSDISPLAYIO_SMODE: 1214 if (*(int *)d != dp->rd_wsmode) { 1215 dp->rd_wsmode = *(int *)d; 1216 if ((dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) || 1217 (dp->rd_wsmode == WSDISPLAYIO_MODE_DUMBFB)) 1218 radeonfb_map(sc); 1219 1220 if ((dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) && 1221 (dp->rd_vd.active)) { 1222 radeonfb_engine_init(dp); 1223 glyphcache_wipe(&dp->rd_gc); 1224 radeonfb_init_palette(dp); 1225 radeonfb_modeswitch(dp); 1226 radeonfb_rectfill(dp, 0, 0, dp->rd_virtx, 1227 dp->rd_virty, dp->rd_bg); 1228 vcons_redraw_screen(dp->rd_vd.active); 1229 } 1230 if (dp->rd_wsmode == WSDISPLAYIO_MODE_MAPPED) 1231 radeonfb_unmap(sc); 1232 } 1233 return 0; 1234 1235 case WSDISPLAYIO_GCURMAX: 1236 ((struct wsdisplay_curpos *)d)->x = RADEON_CURSORMAXX; 1237 ((struct wsdisplay_curpos *)d)->y = RADEON_CURSORMAXY; 1238 return 0; 1239 1240 case WSDISPLAYIO_SCURSOR: 1241 return radeonfb_set_cursor(dp, (struct wsdisplay_cursor *)d); 1242 1243 case WSDISPLAYIO_GCURSOR: 1244 return EPASSTHROUGH; 1245 1246 case WSDISPLAYIO_GCURPOS: 1247 ((struct wsdisplay_curpos *)d)->x = dp->rd_cursor.rc_pos.x; 1248 ((struct wsdisplay_curpos *)d)->y = dp->rd_cursor.rc_pos.y; 1249 return 0; 1250 1251 case WSDISPLAYIO_SCURPOS: 1252 return radeonfb_set_curpos(dp, (struct wsdisplay_curpos *)d); 1253 1254 case WSDISPLAYIO_SSPLASH: 1255 #if defined(SPLASHSCREEN) 1256 if (*(int *)d == 1) { 1257 SCREEN_DISABLE_DRAWING(&dp->rd_vscreen); 1258 splash_render(&dp->rd_splash, 1259 SPLASH_F_CENTER|SPLASH_F_FILL); 1260 } else 1261 SCREEN_ENABLE_DRAWING(&dp->rd_vscreen); 1262 return 0; 1263 #else 1264 return ENODEV; 1265 #endif 1266 case WSDISPLAYIO_GETPARAM: 1267 param = (struct wsdisplay_param *)d; 1268 switch (param->param) { 1269 case WSDISPLAYIO_PARAM_BRIGHTNESS: 1270 param->min = 0; 1271 param->max = 255; 1272 param->curval = dp->rd_bl_level; 1273 return 0; 1274 case WSDISPLAYIO_PARAM_BACKLIGHT: 1275 param->min = 0; 1276 param->max = RADEONFB_BACKLIGHT_MAX; 1277 param->curval = dp->rd_bl_on; 1278 return 0; 1279 } 1280 return EPASSTHROUGH; 1281 1282 case WSDISPLAYIO_SETPARAM: 1283 param = (struct wsdisplay_param *)d; 1284 switch (param->param) { 1285 case WSDISPLAYIO_PARAM_BRIGHTNESS: 1286 radeonfb_set_backlight(dp, param->curval); 1287 return 0; 1288 case WSDISPLAYIO_PARAM_BACKLIGHT: 1289 radeonfb_switch_backlight(dp, param->curval); 1290 return 0; 1291 } 1292 return EPASSTHROUGH; 1293 1294 /* PCI config read/write passthrough. */ 1295 case PCI_IOC_CFGREAD: 1296 case PCI_IOC_CFGWRITE: 1297 return pci_devioctl(sc->sc_pc, sc->sc_pt, cmd, d, flag, l); 1298 1299 case WSDISPLAYIO_GET_BUSID: 1300 return wsdisplayio_busid_pci(sc->sc_dev, sc->sc_pc, 1301 sc->sc_pt, d); 1302 1303 case WSDISPLAYIO_GET_EDID: { 1304 struct wsdisplayio_edid_info *ei = d; 1305 return wsdisplayio_get_edid(sc->sc_dev, ei); 1306 } 1307 1308 case WSDISPLAYIO_GET_FBINFO: { 1309 struct wsdisplayio_fbinfo *fbi = d; 1310 return wsdisplayio_get_fbinfo(&ms->scr_ri, fbi); 1311 } 1312 1313 default: 1314 return EPASSTHROUGH; 1315 } 1316 } 1317 1318 paddr_t 1319 radeonfb_mmap(void *v, void *vs, off_t offset, int prot) 1320 { 1321 struct vcons_data *vd; 1322 struct radeonfb_display *dp; 1323 struct radeonfb_softc *sc; 1324 paddr_t pa; 1325 1326 vd = (struct vcons_data *)v; 1327 dp = (struct radeonfb_display *)vd->cookie; 1328 sc = dp->rd_softc; 1329 1330 if ((offset >= 0) && (offset < (dp->rd_virty * dp->rd_stride))) { 1331 pa = bus_space_mmap(sc->sc_memt, 1332 sc->sc_memaddr + dp->rd_offset + offset, 0, 1333 prot, BUS_SPACE_MAP_LINEAR); 1334 return pa; 1335 } 1336 1337 /* 1338 * restrict all other mappings to processes with superuser privileges 1339 * or the kernel itself 1340 */ 1341 if (kauth_authorize_machdep(kauth_cred_get(), KAUTH_MACHDEP_UNMANAGEDMEM, 1342 NULL, NULL, NULL, NULL) != 0) { 1343 aprint_error_dev(sc->sc_dev, "mmap() rejected.\n"); 1344 return -1; 1345 } 1346 1347 if ((offset >= sc->sc_regaddr) && 1348 (offset < sc->sc_regaddr + sc->sc_regsz)) { 1349 return bus_space_mmap(sc->sc_regt, offset, 0, prot, 1350 BUS_SPACE_MAP_LINEAR); 1351 } 1352 1353 if ((offset >= sc->sc_memaddr) && 1354 (offset < sc->sc_memaddr + sc->sc_memsz)) { 1355 return bus_space_mmap(sc->sc_memt, offset, 0, prot, 1356 BUS_SPACE_MAP_LINEAR); 1357 } 1358 1359 if ((offset >= sc->sc_romaddr) && 1360 (offset < sc->sc_romaddr + sc->sc_romsz)) { 1361 return bus_space_mmap(sc->sc_memt, offset, 0, prot, 1362 BUS_SPACE_MAP_LINEAR); 1363 } 1364 1365 #ifdef PCI_MAGIC_IO_RANGE 1366 /* allow mapping of IO space */ 1367 if ((offset >= PCI_MAGIC_IO_RANGE) && 1368 (offset < PCI_MAGIC_IO_RANGE + 0x10000)) { 1369 pa = bus_space_mmap(sc->sc_iot, offset - PCI_MAGIC_IO_RANGE, 1370 0, prot, 0); 1371 return pa; 1372 } 1373 #endif /* PCI_MAGIC_IO_RANGE */ 1374 1375 return -1; 1376 } 1377 1378 static void 1379 radeonfb_loadbios(struct radeonfb_softc *sc, const struct pci_attach_args *pa) 1380 { 1381 bus_space_tag_t romt; 1382 bus_space_handle_t romh, biosh; 1383 bus_size_t romsz; 1384 bus_addr_t ptr; 1385 uint32_t busctl, crtcg, crtc2g = 0, viphctl, seprom, extc; 1386 int bios_voodoo = 0; 1387 1388 if (pci_mapreg_map(pa, PCI_MAPREG_ROM, PCI_MAPREG_TYPE_ROM, 1389 BUS_SPACE_MAP_PREFETCHABLE, &romt, &romh, NULL, &romsz) != 0) { 1390 aprint_verbose("%s: unable to map BIOS!\n", XNAME(sc)); 1391 return; 1392 } 1393 1394 pci_find_rom(pa, romt, romh, romsz, PCI_ROM_CODE_TYPE_X86, &biosh, 1395 &sc->sc_biossz); 1396 if (sc->sc_biossz != 0) goto foundit; 1397 1398 aprint_verbose("trying to read disabled BIOS...\n"); 1399 1400 bios_voodoo = 1; 1401 seprom = radeonfb_get32(sc, RADEON_SEPROM_CNTL1); 1402 radeonfb_put32(sc, RADEON_SEPROM_CNTL1, 1403 (seprom & ~RADEON_SCK_PRESCALE_MASK) | 1404 (0xc << RADEON_SCK_PRESCALE_SHIFT)); 1405 viphctl = radeonfb_get32(sc, RADEON_VIPH_CONTROL); 1406 radeonfb_put32(sc, RADEON_VIPH_CONTROL, viphctl & ~RADEON_VIPH_EN); 1407 busctl = radeonfb_get32(sc, RADEON_BUS_CNTL); 1408 radeonfb_put32(sc, RADEON_BUS_CNTL, busctl & ~RADEON_BUS_BIOS_DIS_ROM); 1409 crtcg = radeonfb_get32(sc, RADEON_CRTC_GEN_CNTL); 1410 radeonfb_put32(sc, RADEON_CRTC_GEN_CNTL, ((crtcg & ~RADEON_CRTC_EN) | 1411 (RADEON_CRTC_DISP_REQ_EN_B | 1412 RADEON_CRTC_EXT_DISP_EN))); 1413 if (HAS_CRTC2(sc)) { 1414 crtc2g = radeonfb_get32(sc, RADEON_CRTC2_GEN_CNTL); 1415 radeonfb_put32(sc, RADEON_CRTC2_GEN_CNTL, 1416 (crtc2g & ~RADEON_CRTC2_EN) | 1417 RADEON_CRTC2_DISP_REQ_EN_B); 1418 } 1419 extc = radeonfb_get32(sc, RADEON_CRTC_EXT_CNTL); 1420 radeonfb_put32(sc, RADEON_CRTC_EXT_CNTL, (extc & ~RADEON_CRTC_CRT_ON) | 1421 (RADEON_CRTC_SYNC_TRISTAT | 1422 RADEON_CRTC_DISPLAY_DIS)); 1423 pci_find_rom(pa, romt, romh, romsz, PCI_ROM_CODE_TYPE_X86, &biosh, 1424 &sc->sc_biossz); 1425 1426 foundit: 1427 if (sc->sc_biossz > 0) { 1428 sc->sc_bios = malloc(sc->sc_biossz, M_DEVBUF, M_WAITOK); 1429 bus_space_read_region_1(romt, biosh, 0, sc->sc_bios, 1430 sc->sc_biossz); 1431 } 1432 1433 if (bios_voodoo != 0) { 1434 radeonfb_put32(sc, RADEON_CRTC_EXT_CNTL, extc); 1435 if (HAS_CRTC2(sc)) { 1436 radeonfb_put32(sc, RADEON_CRTC2_GEN_CNTL, crtc2g); 1437 } 1438 radeonfb_put32(sc, RADEON_CRTC_GEN_CNTL, crtcg); 1439 radeonfb_put32(sc, RADEON_BUS_CNTL, busctl); 1440 radeonfb_put32(sc, RADEON_VIPH_CONTROL, viphctl); 1441 radeonfb_put32(sc, RADEON_SEPROM_CNTL1, seprom); 1442 } 1443 1444 /* unmap the PCI expansion rom */ 1445 bus_space_unmap(romt, romh, romsz); 1446 1447 /* turn off rom decoder now */ 1448 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM, 1449 pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM) & 1450 ~PCI_MAPREG_ROM_ENABLE); 1451 1452 if (sc->sc_biossz > 0) { 1453 ptr = GETBIOS16(sc, 0x48); 1454 if ((GETBIOS32(sc, ptr + 4) == 0x41544f4d /* "ATOM" */) || 1455 (GETBIOS32(sc, ptr + 4) == 0x4d4f5441 /* "MOTA" */)) { 1456 sc->sc_flags |= RFB_ATOM; 1457 } 1458 1459 aprint_verbose("%s: Found %d KB %s BIOS\n", XNAME(sc), 1460 (unsigned)sc->sc_biossz >> 10, 1461 IS_ATOM(sc) ? "ATOM" : "Legacy"); 1462 } 1463 } 1464 1465 1466 uint32_t 1467 radeonfb_get32(struct radeonfb_softc *sc, uint32_t reg) 1468 { 1469 1470 return bus_space_read_4(sc->sc_regt, sc->sc_regh, reg); 1471 } 1472 1473 void 1474 radeonfb_put32(struct radeonfb_softc *sc, uint32_t reg, uint32_t val) 1475 { 1476 1477 bus_space_write_4(sc->sc_regt, sc->sc_regh, reg, val); 1478 } 1479 1480 void 1481 radeonfb_put32s(struct radeonfb_softc *sc, uint32_t reg, uint32_t val) 1482 { 1483 1484 bus_space_write_stream_4(sc->sc_regt, sc->sc_regh, reg, val); 1485 } 1486 1487 void 1488 radeonfb_mask32(struct radeonfb_softc *sc, uint32_t reg, 1489 uint32_t andmask, uint32_t ormask) 1490 { 1491 int s; 1492 uint32_t val; 1493 1494 s = splhigh(); 1495 val = radeonfb_get32(sc, reg); 1496 val = (val & andmask) | ormask; 1497 radeonfb_put32(sc, reg, val); 1498 splx(s); 1499 } 1500 1501 uint32_t 1502 radeonfb_getindex(struct radeonfb_softc *sc, uint32_t idx) 1503 { 1504 int s; 1505 uint32_t val; 1506 1507 s = splhigh(); 1508 radeonfb_put32(sc, RADEON_MM_INDEX, idx); 1509 val = radeonfb_get32(sc, RADEON_MM_DATA); 1510 splx(s); 1511 1512 return (val); 1513 } 1514 1515 void 1516 radeonfb_putindex(struct radeonfb_softc *sc, uint32_t idx, uint32_t val) 1517 { 1518 int s; 1519 1520 s = splhigh(); 1521 radeonfb_put32(sc, RADEON_MM_INDEX, idx); 1522 radeonfb_put32(sc, RADEON_MM_DATA, val); 1523 splx(s); 1524 } 1525 1526 void 1527 radeonfb_maskindex(struct radeonfb_softc *sc, uint32_t idx, 1528 uint32_t andmask, uint32_t ormask) 1529 { 1530 int s; 1531 uint32_t val; 1532 1533 s = splhigh(); 1534 radeonfb_put32(sc, RADEON_MM_INDEX, idx); 1535 val = radeonfb_get32(sc, RADEON_MM_DATA); 1536 val = (val & andmask) | ormask; 1537 radeonfb_put32(sc, RADEON_MM_DATA, val); 1538 splx(s); 1539 } 1540 1541 uint32_t 1542 radeonfb_getpll(struct radeonfb_softc *sc, uint32_t idx) 1543 { 1544 int s; 1545 uint32_t val; 1546 1547 s = splhigh(); 1548 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, (idx & 0x3f)); 1549 val = radeonfb_get32(sc, RADEON_CLOCK_CNTL_DATA); 1550 if (HAS_R300CG(sc)) 1551 radeonfb_r300cg_workaround(sc); 1552 splx(s); 1553 1554 return (val); 1555 } 1556 1557 void 1558 radeonfb_putpll(struct radeonfb_softc *sc, uint32_t idx, uint32_t val) 1559 { 1560 int s; 1561 1562 s = splhigh(); 1563 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, (idx & 0x3f) | 1564 RADEON_PLL_WR_EN); 1565 radeonfb_put32(sc, RADEON_CLOCK_CNTL_DATA, val); 1566 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, 0); 1567 splx(s); 1568 } 1569 1570 void 1571 radeonfb_maskpll(struct radeonfb_softc *sc, uint32_t idx, 1572 uint32_t andmask, uint32_t ormask) 1573 { 1574 int s; 1575 uint32_t val; 1576 1577 s = splhigh(); 1578 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, (idx & 0x3f) | 1579 RADEON_PLL_WR_EN); 1580 val = radeonfb_get32(sc, RADEON_CLOCK_CNTL_DATA); 1581 val = (val & andmask) | ormask; 1582 radeonfb_put32(sc, RADEON_CLOCK_CNTL_DATA, val); 1583 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, 0); 1584 splx(s); 1585 } 1586 1587 int 1588 radeonfb_scratch_test(struct radeonfb_softc *sc, int reg, uint32_t v) 1589 { 1590 uint32_t saved; 1591 1592 saved = GET32(sc, reg); 1593 PUT32(sc, reg, v); 1594 if (GET32(sc, reg) != v) { 1595 return -1; 1596 } 1597 PUT32(sc, reg, saved); 1598 return 0; 1599 } 1600 1601 uintmax_t 1602 radeonfb_getprop_num(struct radeonfb_softc *sc, const char *name, 1603 uintmax_t defval) 1604 { 1605 prop_number_t pn; 1606 pn = prop_dictionary_get(device_properties(sc->sc_dev), name); 1607 if (pn == NULL) { 1608 return defval; 1609 } 1610 KASSERT(prop_object_type(pn) == PROP_TYPE_NUMBER); 1611 return prop_number_unsigned_value(pn); 1612 } 1613 1614 int 1615 radeonfb_getclocks(struct radeonfb_softc *sc) 1616 { 1617 bus_addr_t ptr; 1618 int refclk = 0; 1619 int refdiv = 0; 1620 int minpll = 0; 1621 int maxpll = 0; 1622 1623 /* load initial property values if port/board provides them */ 1624 refclk = radeonfb_getprop_num(sc, "refclk", 0) & 0xffff; 1625 refdiv = radeonfb_getprop_num(sc, "refdiv", 0) & 0xffff; 1626 minpll = radeonfb_getprop_num(sc, "minpll", 0) & 0xffffffffU; 1627 maxpll = radeonfb_getprop_num(sc, "maxpll", 0) & 0xffffffffU; 1628 1629 PRINTPLL(RADEON_PPLL_REF_DIV); 1630 PRINTPLL(RADEON_PPLL_DIV_0); 1631 PRINTPLL(RADEON_PPLL_DIV_1); 1632 PRINTPLL(RADEON_PPLL_DIV_2); 1633 PRINTPLL(RADEON_PPLL_DIV_3); 1634 PRINTREG(RADEON_CLOCK_CNTL_INDEX); 1635 PRINTPLL(RADEON_P2PLL_REF_DIV); 1636 PRINTPLL(RADEON_P2PLL_DIV_0); 1637 1638 if (refclk && refdiv && minpll && maxpll) 1639 goto dontprobe; 1640 1641 if (!sc->sc_biossz) { 1642 /* no BIOS */ 1643 aprint_verbose("%s: No video BIOS, using default clocks\n", 1644 XNAME(sc)); 1645 if (IS_IGP(sc)) 1646 refclk = refclk ? refclk : 1432; 1647 else 1648 refclk = refclk ? refclk : 2700; 1649 refdiv = refdiv ? refdiv : 12; 1650 minpll = minpll ? minpll : 12500; 1651 /* XXX 1652 * Need to check if the firmware or something programmed a 1653 * higher value than this, and if so, bump it. 1654 * The RV280 in my iBook is unhappy if the PLL input is less 1655 * than 360MHz 1656 */ 1657 maxpll = maxpll ? maxpll : 40000/*35000*/; 1658 } else if (IS_ATOM(sc)) { 1659 /* ATOM BIOS */ 1660 ptr = GETBIOS16(sc, 0x48); 1661 ptr = GETBIOS16(sc, ptr + 32); /* aka MasterDataStart */ 1662 ptr = GETBIOS16(sc, ptr + 12); /* pll info block */ 1663 refclk = refclk ? refclk : GETBIOS16(sc, ptr + 82); 1664 minpll = minpll ? minpll : GETBIOS16(sc, ptr + 78); 1665 maxpll = maxpll ? maxpll : GETBIOS16(sc, ptr + 32); 1666 /* 1667 * ATOM BIOS doesn't supply a reference divider, so we 1668 * have to probe for it. 1669 */ 1670 if (refdiv < 2) 1671 refdiv = GETPLL(sc, RADEON_PPLL_REF_DIV) & 1672 RADEON_PPLL_REF_DIV_MASK; 1673 /* 1674 * if probe is zero, just assume one that should work 1675 * for most parts 1676 */ 1677 if (refdiv < 2) 1678 refdiv = 12; 1679 1680 } else { 1681 uint32_t tmp = GETPLL(sc, RADEON_PPLL_REF_DIV); 1682 /* Legacy BIOS */ 1683 ptr = GETBIOS16(sc, 0x48); 1684 ptr = GETBIOS16(sc, ptr + 0x30); 1685 if (IS_R300(sc)) { 1686 refdiv = refdiv ? refdiv : 1687 (tmp & R300_PPLL_REF_DIV_ACC_MASK) >> 1688 R300_PPLL_REF_DIV_ACC_SHIFT; 1689 } else { 1690 refdiv = refdiv ? refdiv : 1691 tmp & RADEON_PPLL_REF_DIV_MASK; 1692 } 1693 refclk = refclk ? refclk : GETBIOS16(sc, ptr + 0x0E); 1694 refdiv = refdiv ? refdiv : GETBIOS16(sc, ptr + 0x10); 1695 minpll = minpll ? minpll : GETBIOS32(sc, ptr + 0x12); 1696 maxpll = maxpll ? maxpll : GETBIOS32(sc, ptr + 0x16); 1697 } 1698 1699 1700 dontprobe: 1701 sc->sc_refclk = refclk * 10; 1702 sc->sc_refdiv = refdiv; 1703 sc->sc_minpll = minpll * 10; 1704 sc->sc_maxpll = maxpll * 10; 1705 return 0; 1706 } 1707 1708 int 1709 radeonfb_calc_dividers(struct radeonfb_softc *sc, uint32_t dotclock, 1710 uint32_t *postdivbit, uint32_t *feedbackdiv, int flags) 1711 { 1712 int i; 1713 uint32_t outfreq; 1714 int div; 1715 1716 DPRINTF(("dot clock: %u\n", dotclock)); 1717 for (i = 0; (div = radeonfb_dividers[i].divider) != 0; i++) { 1718 1719 if ((flags & NO_ODD_FBDIV) && ((div & 1) != 0)) 1720 continue; 1721 1722 /* 1723 * XXX 1724 * the rv350 in my last generation 14" iBook G4 produces 1725 * garbage with dividers > 4. No idea if this is a hardware 1726 * limitation or an error in the divider table. 1727 */ 1728 if ((sc->sc_family == RADEON_RV350) && (div > 4)) 1729 continue; 1730 1731 outfreq = div * dotclock; 1732 if ((outfreq >= sc->sc_minpll) && 1733 (outfreq <= sc->sc_maxpll)) { 1734 DPRINTF(("outfreq: %u\n", outfreq)); 1735 *postdivbit = 1736 ((uint32_t)radeonfb_dividers[i].mask << 16); 1737 DPRINTF(("post divider: %d (mask %x)\n", div, 1738 *postdivbit)); 1739 break; 1740 } 1741 } 1742 1743 if (div == 0) 1744 return 1; 1745 1746 *feedbackdiv = DIVIDE(sc->sc_refdiv * outfreq, sc->sc_refclk); 1747 DPRINTF(("feedback divider: %d\n", *feedbackdiv)); 1748 return 0; 1749 } 1750 1751 #if 0 1752 #ifdef RADEONFB_DEBUG 1753 static void 1754 dump_buffer(const char *pfx, void *buffer, unsigned int size) 1755 { 1756 char asc[17]; 1757 unsigned ptr = (unsigned)buffer; 1758 char *start = (char *)(ptr & ~0xf); 1759 char *end = (char *)(ptr + size); 1760 1761 end = (char *)(((unsigned)end + 0xf) & ~0xf); 1762 1763 if (pfx == NULL) { 1764 pfx = ""; 1765 } 1766 1767 while (start < end) { 1768 unsigned offset = (unsigned)start & 0xf; 1769 if (offset == 0) { 1770 printf("%s%x: ", pfx, (unsigned)start); 1771 } 1772 if (((unsigned)start < ptr) || 1773 ((unsigned)start >= (ptr + size))) { 1774 printf(" "); 1775 asc[offset] = ' '; 1776 } else { 1777 printf("%02x", *(unsigned char *)start); 1778 if ((*start >= ' ') && (*start <= '~')) { 1779 asc[offset] = *start; 1780 } else { 1781 asc[offset] = '.'; 1782 } 1783 } 1784 asc[offset + 1] = 0; 1785 if (offset % 2) { 1786 printf(" "); 1787 } 1788 if (offset == 15) { 1789 printf(" %s\n", asc); 1790 } 1791 start++; 1792 } 1793 } 1794 #endif 1795 #endif 1796 1797 int 1798 radeonfb_getconnectors(struct radeonfb_softc *sc) 1799 { 1800 int i; 1801 int found = 0; 1802 1803 for (i = 0; i < 2; i++) { 1804 sc->sc_ports[i].rp_mon_type = RADEON_MT_UNKNOWN; 1805 sc->sc_ports[i].rp_ddc_type = RADEON_DDC_NONE; 1806 sc->sc_ports[i].rp_dac_type = RADEON_DAC_UNKNOWN; 1807 sc->sc_ports[i].rp_conn_type = RADEON_CONN_NONE; 1808 sc->sc_ports[i].rp_tmds_type = RADEON_TMDS_UNKNOWN; 1809 } 1810 1811 /* 1812 * This logic is borrowed from Xorg's radeon driver. 1813 */ 1814 if (!sc->sc_biossz) 1815 goto nobios; 1816 1817 if (IS_ATOM(sc)) { 1818 /* not done yet */ 1819 } else { 1820 uint16_t ptr; 1821 int port = 0; 1822 1823 ptr = GETBIOS16(sc, 0x48); 1824 ptr = GETBIOS16(sc, ptr + 0x50); 1825 for (i = 1; i < 4; i++) { 1826 uint16_t entry; 1827 uint8_t conn, ddc, dac, tmds; 1828 1829 /* 1830 * Parse the connector table. From reading the code, 1831 * it appears to made up of 16-bit entries for each 1832 * connector. The 16-bits are defined as: 1833 * 1834 * bits 12-15 - connector type (0 == end of table) 1835 * bits 8-11 - DDC type 1836 * bits 5-7 - ??? 1837 * bit 4 - TMDS type (1 = EXT, 0 = INT) 1838 * bits 1-3 - ??? 1839 * bit 0 - DAC, 1 = TVDAC, 0 = primary 1840 */ 1841 if (!GETBIOS8(sc, ptr + i * 2) && i > 1) 1842 break; 1843 entry = GETBIOS16(sc, ptr + i * 2); 1844 1845 conn = (entry >> 12) & 0xf; 1846 ddc = (entry >> 8) & 0xf; 1847 dac = (entry & 0x1) ? RADEON_DAC_TVDAC : 1848 RADEON_DAC_PRIMARY; 1849 tmds = ((entry >> 4) & 0x1) ? RADEON_TMDS_EXT : 1850 RADEON_TMDS_INT; 1851 1852 if (conn == RADEON_CONN_NONE) 1853 continue; /* no connector */ 1854 1855 /* 1856 * XXX 1857 * both Mac Mini variants have both outputs wired to 1858 * the same connector and share the DDC lines 1859 */ 1860 if ((found > 0) && 1861 (sc->sc_ports[port].rp_ddc_type == ddc)) { 1862 /* duplicate entry for same connector */ 1863 continue; 1864 } 1865 1866 /* internal DDC_DVI port gets priority */ 1867 if ((ddc == RADEON_DDC_DVI) || (port == 1)) 1868 port = 0; 1869 else 1870 port = 1; 1871 1872 sc->sc_ports[port].rp_ddc_type = 1873 ddc > RADEON_DDC_CRT2 ? RADEON_DDC_NONE : ddc; 1874 sc->sc_ports[port].rp_dac_type = dac; 1875 sc->sc_ports[port].rp_conn_type = 1876 uimin(conn, RADEON_CONN_UNSUPPORTED) ; 1877 1878 sc->sc_ports[port].rp_tmds_type = tmds; 1879 1880 if ((conn != RADEON_CONN_DVI_I) && 1881 (conn != RADEON_CONN_DVI_D) && 1882 (tmds == RADEON_TMDS_INT)) 1883 sc->sc_ports[port].rp_tmds_type = 1884 RADEON_TMDS_UNKNOWN; 1885 sc->sc_ports[port].rp_number = i - 1; 1886 1887 found += (port + 1); 1888 } 1889 } 1890 1891 nobios: 1892 if (!found) { 1893 bool dvi_ext = FALSE, dvi_int = FALSE; 1894 DPRINTF(("No connector info in BIOS!\n")); 1895 prop_dictionary_get_bool(device_properties(sc->sc_dev), 1896 "dvi-internal", &dvi_int); 1897 prop_dictionary_get_bool(device_properties(sc->sc_dev), 1898 "dvi-external", &dvi_ext); 1899 if (dvi_ext) { 1900 sc->sc_ports[0].rp_mon_type = RADEON_MT_UNKNOWN; 1901 sc->sc_ports[0].rp_ddc_type = RADEON_DDC_CRT2; 1902 sc->sc_ports[0].rp_dac_type = RADEON_DAC_PRIMARY; 1903 sc->sc_ports[0].rp_conn_type = RADEON_CONN_DVI_I; 1904 sc->sc_ports[0].rp_tmds_type = RADEON_TMDS_EXT; /* output to fp2 */ 1905 sc->sc_ports[0].rp_number = 0; 1906 sc->sc_ports[1].rp_mon_type = RADEON_MT_UNKNOWN; 1907 sc->sc_ports[1].rp_ddc_type = RADEON_DDC_NONE; 1908 sc->sc_ports[1].rp_dac_type = RADEON_DAC_UNKNOWN; 1909 sc->sc_ports[1].rp_conn_type = RADEON_CONN_NONE; 1910 sc->sc_ports[1].rp_tmds_type = RADEON_TMDS_UNKNOWN; 1911 sc->sc_ports[1].rp_number = 1; 1912 } else if (dvi_int) { 1913 sc->sc_ports[0].rp_mon_type = RADEON_MT_UNKNOWN; 1914 sc->sc_ports[0].rp_ddc_type = RADEON_DDC_CRT2; 1915 sc->sc_ports[0].rp_dac_type = RADEON_DAC_PRIMARY; 1916 sc->sc_ports[0].rp_conn_type = RADEON_CONN_DVI_I; 1917 sc->sc_ports[0].rp_tmds_type = RADEON_TMDS_INT; 1918 sc->sc_ports[0].rp_number = 0; 1919 sc->sc_ports[1].rp_mon_type = RADEON_MT_UNKNOWN; 1920 sc->sc_ports[1].rp_ddc_type = RADEON_DDC_NONE; 1921 sc->sc_ports[1].rp_dac_type = RADEON_DAC_UNKNOWN; 1922 sc->sc_ports[1].rp_conn_type = RADEON_CONN_NONE; 1923 sc->sc_ports[1].rp_tmds_type = RADEON_TMDS_UNKNOWN; 1924 sc->sc_ports[1].rp_number = 1; 1925 } else if IS_MOBILITY(sc) { 1926 /* default, port 0 = internal TMDS, port 1 = CRT */ 1927 sc->sc_ports[0].rp_mon_type = RADEON_MT_UNKNOWN; 1928 sc->sc_ports[0].rp_ddc_type = RADEON_DDC_DVI; 1929 sc->sc_ports[0].rp_dac_type = RADEON_DAC_TVDAC; 1930 sc->sc_ports[0].rp_conn_type = RADEON_CONN_DVI_D; 1931 sc->sc_ports[0].rp_tmds_type = RADEON_TMDS_INT; 1932 sc->sc_ports[0].rp_number = 0; 1933 1934 sc->sc_ports[1].rp_mon_type = RADEON_MT_UNKNOWN; 1935 sc->sc_ports[1].rp_ddc_type = RADEON_DDC_VGA; 1936 sc->sc_ports[1].rp_dac_type = RADEON_DAC_PRIMARY; 1937 sc->sc_ports[1].rp_conn_type = RADEON_CONN_CRT; 1938 sc->sc_ports[1].rp_tmds_type = RADEON_TMDS_EXT; 1939 sc->sc_ports[1].rp_number = 1; 1940 } else { 1941 /* default, port 0 = DVI, port 1 = CRT */ 1942 sc->sc_ports[0].rp_mon_type = RADEON_MT_UNKNOWN; 1943 sc->sc_ports[0].rp_ddc_type = RADEON_DDC_DVI; 1944 sc->sc_ports[0].rp_dac_type = RADEON_DAC_TVDAC; 1945 sc->sc_ports[0].rp_conn_type = RADEON_CONN_DVI_D; 1946 sc->sc_ports[0].rp_tmds_type = RADEON_TMDS_INT; 1947 sc->sc_ports[0].rp_number = 0; 1948 1949 sc->sc_ports[1].rp_mon_type = RADEON_MT_UNKNOWN; 1950 sc->sc_ports[1].rp_ddc_type = RADEON_DDC_VGA; 1951 sc->sc_ports[1].rp_dac_type = RADEON_DAC_PRIMARY; 1952 sc->sc_ports[1].rp_conn_type = RADEON_CONN_CRT; 1953 sc->sc_ports[1].rp_tmds_type = RADEON_TMDS_UNKNOWN; 1954 sc->sc_ports[1].rp_number = 1; 1955 } 1956 } 1957 1958 /* 1959 * Fixup for RS300/RS350/RS400 chips, that lack a primary DAC. 1960 * these chips should use TVDAC for the VGA port. 1961 */ 1962 if (HAS_SDAC(sc)) { 1963 if (sc->sc_ports[0].rp_conn_type == RADEON_CONN_CRT) { 1964 sc->sc_ports[0].rp_dac_type = RADEON_DAC_TVDAC; 1965 sc->sc_ports[1].rp_dac_type = RADEON_DAC_PRIMARY; 1966 } else { 1967 sc->sc_ports[1].rp_dac_type = RADEON_DAC_TVDAC; 1968 sc->sc_ports[0].rp_dac_type = RADEON_DAC_PRIMARY; 1969 } 1970 } else if (!HAS_CRTC2(sc)) { 1971 sc->sc_ports[0].rp_dac_type = RADEON_DAC_PRIMARY; 1972 } 1973 1974 for (i = 0; i < 2; i++) { 1975 char edid[128], edid_port_str[7] = "EDID:"; 1976 uint8_t ddc; 1977 struct edid_info *eip = &sc->sc_ports[i].rp_edid; 1978 prop_data_t edid_data; 1979 1980 DPRINTF(("Port #%d:\n", i)); 1981 DPRINTF((" conn = %d\n", sc->sc_ports[i].rp_conn_type)); 1982 DPRINTF((" ddc = %d\n", sc->sc_ports[i].rp_ddc_type)); 1983 DPRINTF((" dac = %d\n", sc->sc_ports[i].rp_dac_type)); 1984 DPRINTF((" tmds = %d\n", sc->sc_ports[i].rp_tmds_type)); 1985 DPRINTF((" crtc = %d\n", sc->sc_ports[i].rp_number)); 1986 1987 sc->sc_ports[i].rp_edid_valid = 0; 1988 /* 1989 * First look for static EDID data 1990 * Try "EDID:port" then "EDID" 1991 */ 1992 snprintf(&edid_port_str[5], 2, "%d", i); 1993 edid_data = prop_dictionary_get(device_properties( 1994 sc->sc_dev), edid_port_str); 1995 if (edid_data == NULL) 1996 edid_data = prop_dictionary_get(device_properties( 1997 sc->sc_dev), "EDID"); 1998 if (edid_data != NULL) { 1999 aprint_debug_dev(sc->sc_dev, "using static EDID\n"); 2000 memcpy(edid, prop_data_value(edid_data), 128); 2001 if (edid_parse(edid, eip) == 0) { 2002 2003 sc->sc_ports[i].rp_edid_valid = 1; 2004 #ifdef RADEONFB_DEBUG 2005 edid_print(eip); 2006 #endif 2007 } 2008 } 2009 /* if we didn't find any we'll try to talk to the monitor */ 2010 if (sc->sc_ports[i].rp_edid_valid != 1) { 2011 2012 ddc = sc->sc_ports[i].rp_ddc_type; 2013 if (ddc != RADEON_DDC_NONE) { 2014 if ((radeonfb_i2c_read_edid(sc, ddc, edid) 2015 == 0) && (edid_parse(edid, eip) == 0)) { 2016 2017 sc->sc_ports[i].rp_edid_valid = 1; 2018 #ifdef RADEONFB_DEBUG 2019 edid_print(eip); 2020 #endif 2021 } 2022 } 2023 } 2024 } 2025 2026 return found; 2027 } 2028 2029 int 2030 radeonfb_gettmds(struct radeonfb_softc *sc) 2031 { 2032 int i; 2033 2034 if (!sc->sc_biossz) { 2035 goto nobios; 2036 } 2037 2038 if (IS_ATOM(sc)) { 2039 /* XXX: not done yet */ 2040 } else { 2041 uint16_t ptr; 2042 int n; 2043 2044 ptr = GETBIOS16(sc, 0x48); 2045 ptr = GETBIOS16(sc, ptr + 0x34); 2046 DPRINTF(("DFP table revision %d\n", GETBIOS8(sc, ptr))); 2047 if (GETBIOS8(sc, ptr) == 3) { 2048 /* revision three table */ 2049 n = GETBIOS8(sc, ptr + 5) + 1; 2050 n = uimin(n, 4); 2051 2052 memset(sc->sc_tmds_pll, 0, sizeof (sc->sc_tmds_pll)); 2053 for (i = 0; i < n; i++) { 2054 sc->sc_tmds_pll[i].rtp_pll = GETBIOS32(sc, 2055 ptr + i * 10 + 8); 2056 sc->sc_tmds_pll[i].rtp_freq = GETBIOS16(sc, 2057 ptr + i * 10 + 0x10); 2058 DPRINTF(("TMDS_PLL dot clock %d pll %x\n", 2059 sc->sc_tmds_pll[i].rtp_freq, 2060 sc->sc_tmds_pll[i].rtp_pll)); 2061 } 2062 return 0; 2063 } 2064 } 2065 2066 nobios: 2067 DPRINTF(("no suitable DFP table present\n")); 2068 for (i = 0; 2069 i < sizeof (radeonfb_tmds_pll) / sizeof (radeonfb_tmds_pll[0]); 2070 i++) { 2071 int j; 2072 2073 if (radeonfb_tmds_pll[i].family != sc->sc_family) 2074 continue; 2075 2076 for (j = 0; j < 4; j++) { 2077 sc->sc_tmds_pll[j] = radeonfb_tmds_pll[i].plls[j]; 2078 DPRINTF(("TMDS_PLL dot clock %d pll %x\n", 2079 sc->sc_tmds_pll[j].rtp_freq, 2080 sc->sc_tmds_pll[j].rtp_pll)); 2081 } 2082 return 0; 2083 } 2084 2085 return -1; 2086 } 2087 2088 const struct videomode * 2089 radeonfb_modelookup(const char *name) 2090 { 2091 int i; 2092 /* Use a default mode in case we don't find a matching mode */ 2093 const char *vm = "1024x768x60"; 2094 const struct videomode *vmp = NULL; 2095 2096 for (i = 0; i < videomode_count; i++) { 2097 if (!strcmp(name, videomode_list[i].name)) 2098 return &videomode_list[i]; 2099 if (!strcmp(vm, videomode_list[i].name)) 2100 vmp = &videomode_list[i]; 2101 } 2102 return vmp; 2103 } 2104 2105 void 2106 radeonfb_pllwriteupdate(struct radeonfb_softc *sc, int crtc) 2107 { 2108 if (crtc) { 2109 while (GETPLL(sc, RADEON_P2PLL_REF_DIV) & 2110 RADEON_P2PLL_ATOMIC_UPDATE_R); 2111 SETPLL(sc, RADEON_P2PLL_REF_DIV, RADEON_P2PLL_ATOMIC_UPDATE_W); 2112 } else { 2113 while (GETPLL(sc, RADEON_PPLL_REF_DIV) & 2114 RADEON_PPLL_ATOMIC_UPDATE_R); 2115 SETPLL(sc, RADEON_PPLL_REF_DIV, RADEON_PPLL_ATOMIC_UPDATE_W); 2116 } 2117 } 2118 2119 void 2120 radeonfb_pllwaitatomicread(struct radeonfb_softc *sc, int crtc) 2121 { 2122 int i; 2123 2124 for (i = 10000; i; i--) { 2125 if (crtc) { 2126 if (GETPLL(sc, RADEON_P2PLL_REF_DIV) & 2127 RADEON_P2PLL_ATOMIC_UPDATE_R) 2128 break; 2129 } else { 2130 if (GETPLL(sc, RADEON_PPLL_REF_DIV) & 2131 RADEON_PPLL_ATOMIC_UPDATE_R) 2132 break; 2133 } 2134 } 2135 } 2136 2137 void 2138 radeonfb_program_vclk(struct radeonfb_softc *sc, int dotclock, int crtc, int flags) 2139 { 2140 uint32_t pbit = 0; 2141 uint32_t feed = 0; 2142 uint32_t data, refdiv, div0, r2xxref; 2143 2144 radeonfb_calc_dividers(sc, dotclock, &pbit, &feed, flags); 2145 2146 if (crtc == 0) { 2147 2148 refdiv = GETPLL(sc, RADEON_PPLL_REF_DIV); 2149 2150 /* 2151 * XXX 2152 * the RV350 in my last generation iBook G4 behaves like an 2153 * r2xx here - try to detect that and not screw up the reference 2154 * divider. 2155 * xf86-video-radeon just skips PLL programming altogether 2156 * on iBooks, probably for this reason. 2157 */ 2158 r2xxref = (refdiv & ~RADEON_PPLL_REF_DIV_MASK) | sc->sc_refdiv; 2159 if (IS_R300(sc) && (r2xxref != refdiv)) { 2160 refdiv = (refdiv & ~R300_PPLL_REF_DIV_ACC_MASK) | 2161 (sc->sc_refdiv << R300_PPLL_REF_DIV_ACC_SHIFT); 2162 } else { 2163 refdiv = (refdiv & ~RADEON_PPLL_REF_DIV_MASK) | 2164 sc->sc_refdiv; 2165 } 2166 DPRINTF(("refdiv %08x\n", refdiv)); 2167 div0 = GETPLL(sc, RADEON_PPLL_DIV_0); 2168 DPRINTF(("div0 %08x\n", div0)); 2169 div0 &= ~(RADEON_PPLL_FB3_DIV_MASK | 2170 RADEON_PPLL_POST3_DIV_MASK); 2171 div0 |= pbit; 2172 div0 |= (feed & RADEON_PPLL_FB3_DIV_MASK); 2173 DPRINTF(("div0 %08x\n", div0)); 2174 2175 if ((refdiv == GETPLL(sc, RADEON_PPLL_REF_DIV)) && 2176 (div0 == GETPLL(sc, RADEON_PPLL_DIV_0))) { 2177 /* 2178 * nothing to do here, the PLL is already where we 2179 * want it 2180 */ 2181 PATCH32(sc, RADEON_CLOCK_CNTL_INDEX, 0, 2182 ~RADEON_PLL_DIV_SEL); 2183 aprint_debug_dev(sc->sc_dev, "no need to touch the PLL\n"); 2184 return; 2185 } 2186 2187 /* alright, we do need to reprogram stuff */ 2188 PATCHPLL(sc, RADEON_VCLK_ECP_CNTL, 2189 RADEON_VCLK_SRC_SEL_CPUCLK, 2190 ~RADEON_VCLK_SRC_SEL_MASK); 2191 2192 /* put vclk into reset, use atomic updates */ 2193 SETPLL(sc, RADEON_PPLL_CNTL, 2194 RADEON_PPLL_REFCLK_SEL | 2195 RADEON_PPLL_FBCLK_SEL | 2196 RADEON_PPLL_RESET | 2197 RADEON_PPLL_ATOMIC_UPDATE_EN | 2198 RADEON_PPLL_VGA_ATOMIC_UPDATE_EN); 2199 2200 /* select clock 0 */ 2201 PATCH32(sc, RADEON_CLOCK_CNTL_INDEX, 0, 2202 ~RADEON_PLL_DIV_SEL); 2203 2204 PUTPLL(sc, RADEON_PPLL_REF_DIV, refdiv); 2205 2206 /* xf86-video-radeon does this, not sure why */ 2207 PUTPLL(sc, RADEON_PPLL_DIV_0, div0); 2208 PUTPLL(sc, RADEON_PPLL_DIV_0, div0); 2209 2210 /* use the atomic update */ 2211 radeonfb_pllwriteupdate(sc, crtc); 2212 2213 /* and wait for it to complete */ 2214 radeonfb_pllwaitatomicread(sc, crtc); 2215 2216 /* program HTOTAL (why?) */ 2217 PUTPLL(sc, RADEON_HTOTAL_CNTL, 0); 2218 2219 /* drop reset */ 2220 CLRPLL(sc, RADEON_PPLL_CNTL, 2221 RADEON_PPLL_RESET | RADEON_PPLL_SLEEP | 2222 RADEON_PPLL_ATOMIC_UPDATE_EN | 2223 RADEON_PPLL_VGA_ATOMIC_UPDATE_EN); 2224 2225 PRINTPLL(RADEON_PPLL_CNTL); 2226 PRINTPLL(RADEON_PPLL_REF_DIV); 2227 PRINTPLL(RADEON_PPLL_DIV_3); 2228 2229 /* give clock time to lock */ 2230 delay(50000); 2231 2232 PATCHPLL(sc, RADEON_VCLK_ECP_CNTL, 2233 RADEON_VCLK_SRC_SEL_PPLLCLK, 2234 ~RADEON_VCLK_SRC_SEL_MASK); 2235 2236 } else { 2237 2238 PATCHPLL(sc, RADEON_PIXCLKS_CNTL, 2239 RADEON_PIX2CLK_SRC_SEL_CPUCLK, 2240 ~RADEON_PIX2CLK_SRC_SEL_MASK); 2241 2242 /* put vclk into reset, use atomic updates */ 2243 SETPLL(sc, RADEON_P2PLL_CNTL, 2244 RADEON_P2PLL_RESET | 2245 RADEON_P2PLL_ATOMIC_UPDATE_EN | 2246 RADEON_P2PLL_VGA_ATOMIC_UPDATE_EN); 2247 2248 /* program reference divider */ 2249 PATCHPLL(sc, RADEON_P2PLL_REF_DIV, sc->sc_refdiv, 2250 ~RADEON_P2PLL_REF_DIV_MASK); 2251 2252 /* program feedback and post dividers */ 2253 data = GETPLL(sc, RADEON_P2PLL_DIV_0); 2254 data &= ~(RADEON_P2PLL_FB0_DIV_MASK | 2255 RADEON_P2PLL_POST0_DIV_MASK); 2256 data |= pbit; 2257 data |= (feed & RADEON_P2PLL_FB0_DIV_MASK); 2258 PUTPLL(sc, RADEON_P2PLL_DIV_0, data); 2259 PUTPLL(sc, RADEON_P2PLL_DIV_0, data); 2260 2261 PRINTPLL(RADEON_P2PLL_REF_DIV); 2262 PRINTPLL(RADEON_P2PLL_DIV_0); 2263 2264 /* use the atomic update */ 2265 radeonfb_pllwriteupdate(sc, crtc); 2266 2267 /* and wait for it to complete */ 2268 radeonfb_pllwaitatomicread(sc, crtc); 2269 2270 /* program HTOTAL (why?) */ 2271 PUTPLL(sc, RADEON_HTOTAL2_CNTL, 0); 2272 2273 /* drop reset */ 2274 CLRPLL(sc, RADEON_P2PLL_CNTL, 2275 RADEON_P2PLL_RESET | RADEON_P2PLL_SLEEP | 2276 RADEON_P2PLL_ATOMIC_UPDATE_EN | 2277 RADEON_P2PLL_VGA_ATOMIC_UPDATE_EN); 2278 2279 /* allow time for clock to lock */ 2280 delay(50000); 2281 2282 PATCHPLL(sc, RADEON_PIXCLKS_CNTL, 2283 RADEON_PIX2CLK_SRC_SEL_P2PLLCLK, 2284 ~RADEON_PIX2CLK_SRC_SEL_MASK); 2285 } 2286 PRINTREG(RADEON_CRTC_MORE_CNTL); 2287 } 2288 2289 void 2290 radeonfb_modeswitch(struct radeonfb_display *dp) 2291 { 2292 struct radeonfb_softc *sc = dp->rd_softc; 2293 int i; 2294 2295 if (IS_AVIVO(sc)) { 2296 /* 2297 * no actual mode setting yet, we just make sure the CRTCs 2298 * point at the right memory ranges and use the same pitch 2299 * for the drawing engine 2300 */ 2301 if (GET32(sc, AVIVO_D1CRTC_CONTROL) & AVIVO_CRTC_EN) { 2302 CLR32(sc, AVIVO_D1GRPH_CONTROL, AVIVO_D1GRPH_MACRO_ADDRESS_MODE); 2303 dp->rd_stride = GET32(sc, AVIVO_D1GRPH_PITCH); 2304 PUT32(sc, AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS, 0); 2305 } 2306 if (GET32(sc, AVIVO_D2CRTC_CONTROL) & AVIVO_CRTC_EN) { 2307 CLR32(sc, AVIVO_D2GRPH_CONTROL, AVIVO_D1GRPH_MACRO_ADDRESS_MODE); 2308 dp->rd_stride = GET32(sc, AVIVO_D2GRPH_PITCH); 2309 PUT32(sc, AVIVO_D2GRPH_PRIMARY_SURFACE_ADDRESS, 0); 2310 } 2311 return; 2312 } 2313 2314 /* blank the display while we switch modes */ 2315 //radeonfb_blank(dp, 1); 2316 2317 #if 0 2318 SET32(sc, RADEON_CRTC_EXT_CNTL, 2319 RADEON_CRTC_VSYNC_DIS | RADEON_CRTC_HSYNC_DIS | 2320 RADEON_CRTC_DISPLAY_DIS /* | RADEON_CRTC_DISP_REQ_EN_B */); 2321 #endif 2322 2323 /* these registers might get in the way... */ 2324 PUT32(sc, RADEON_OVR_CLR, 0); 2325 PUT32(sc, RADEON_OVR_WID_LEFT_RIGHT, 0); 2326 PUT32(sc, RADEON_OVR_WID_TOP_BOTTOM, 0); 2327 PUT32(sc, RADEON_OV0_SCALE_CNTL, 0); 2328 PUT32(sc, RADEON_SUBPIC_CNTL, 0); 2329 PUT32(sc, RADEON_VIPH_CONTROL, 0); 2330 PUT32(sc, RADEON_I2C_CNTL_1, 0); 2331 PUT32(sc, RADEON_GEN_INT_CNTL, 0); 2332 PUT32(sc, RADEON_CAP0_TRIG_CNTL, 0); 2333 PUT32(sc, RADEON_CAP1_TRIG_CNTL, 0); 2334 2335 for (i = 0; i < dp->rd_ncrtcs; i++) 2336 radeonfb_setcrtc(dp, i); 2337 2338 #if 0 2339 /* 2340 * DVO chip voodoo from xf86-video-radeon 2341 * apparently this is needed for some powerbooks with DVI outputs 2342 */ 2343 2344 uint8_t data[5][2] = {{0x8, 0x030}, {0x9, 0}, {0xa, 0x90}, {0xc, 0x89}, {0x8, 0x3b}}; 2345 int n = 0; 2346 iic_acquire_bus(&sc->sc_i2c[0].ric_controller, 0); 2347 for (i = 0; i < 5; i++) 2348 n += iic_exec(&sc->sc_i2c[0].ric_controller, I2C_OP_WRITE, 0x38, data[i], 2, NULL, 0, 0); 2349 iic_release_bus(&sc->sc_i2c[0].ric_controller, 0); 2350 printf("n = %d\n", n); 2351 #endif 2352 2353 /* activate the display */ 2354 radeonfb_blank(dp, 0); 2355 } 2356 2357 void 2358 radeonfb_setcrtc(struct radeonfb_display *dp, int index) 2359 { 2360 int crtc, flags = 0; 2361 struct videomode *mode; 2362 struct radeonfb_softc *sc; 2363 struct radeonfb_crtc *cp; 2364 uint32_t v, hd, vd; 2365 uint32_t gencntl; 2366 uint32_t htotaldisp; 2367 uint32_t hsyncstrt; 2368 uint32_t vtotaldisp; 2369 uint32_t vsyncstrt; 2370 uint32_t fphsyncstrt; 2371 uint32_t fpvsyncstrt; 2372 uint32_t fphtotaldisp; 2373 uint32_t fpvtotaldisp; 2374 uint32_t pitch; 2375 2376 sc = dp->rd_softc; 2377 2378 if ((sc->sc_ports[index].rp_tmds_type == RADEON_TMDS_INT) || 2379 (sc->sc_ports[index].rp_tmds_type == RADEON_TMDS_EXT)) { 2380 flags |= NO_ODD_FBDIV; 2381 } 2382 2383 cp = &dp->rd_crtcs[index]; 2384 crtc = cp->rc_number; 2385 mode = &cp->rc_videomode; 2386 2387 #if 1 2388 pitch = dp->rd_stride / dp->rd_bpp; 2389 #else 2390 pitch = (((sc->sc_maxx * sc->sc_maxbpp) + ((sc->sc_maxbpp * 8) - 1)) / 2391 (sc->sc_maxbpp * 8)); 2392 #endif 2393 switch (crtc) { 2394 case 0: 2395 gencntl = RADEON_CRTC_GEN_CNTL; 2396 htotaldisp = RADEON_CRTC_H_TOTAL_DISP; 2397 hsyncstrt = RADEON_CRTC_H_SYNC_STRT_WID; 2398 vtotaldisp = RADEON_CRTC_V_TOTAL_DISP; 2399 vsyncstrt = RADEON_CRTC_V_SYNC_STRT_WID; 2400 /* should probably leave those alone on non-LVDS */ 2401 fpvsyncstrt = RADEON_FP_V_SYNC_STRT_WID; 2402 fphsyncstrt = RADEON_FP_H_SYNC_STRT_WID; 2403 fpvtotaldisp = RADEON_FP_CRTC_V_TOTAL_DISP; 2404 fphtotaldisp = RADEON_FP_CRTC_H_TOTAL_DISP; 2405 break; 2406 case 1: 2407 gencntl = RADEON_CRTC2_GEN_CNTL; 2408 htotaldisp = RADEON_CRTC2_H_TOTAL_DISP; 2409 hsyncstrt = RADEON_CRTC2_H_SYNC_STRT_WID; 2410 vtotaldisp = RADEON_CRTC2_V_TOTAL_DISP; 2411 vsyncstrt = RADEON_CRTC2_V_SYNC_STRT_WID; 2412 fpvsyncstrt = RADEON_FP_V2_SYNC_STRT_WID; 2413 fphsyncstrt = RADEON_FP_H2_SYNC_STRT_WID; 2414 /* XXX these registers don't seem to exist */ 2415 fpvtotaldisp = 0;//RADEON_FP_CRTC2_V_TOTAL_DISP; 2416 fphtotaldisp = 0;//RADEON_FP_CRTC2_H_TOTAL_DISP; 2417 break; 2418 default: 2419 panic("Bad CRTC!"); 2420 break; 2421 } 2422 2423 /* 2424 * CRTC_GEN_CNTL - depth, accelerator mode, etc. 2425 */ 2426 /* only bother with 32bpp and 8bpp */ 2427 v = dp->rd_format << RADEON_CRTC_PIX_WIDTH_SHIFT; 2428 2429 if (crtc == 1) { 2430 v |= RADEON_CRTC2_CRT2_ON | RADEON_CRTC2_EN; 2431 } else { 2432 v |= RADEON_CRTC_EXT_DISP_EN | RADEON_CRTC_EN; 2433 } 2434 2435 if (mode->flags & VID_DBLSCAN) 2436 v |= RADEON_CRTC2_DBL_SCAN_EN; 2437 2438 if (mode->flags & VID_INTERLACE) 2439 v |= RADEON_CRTC2_INTERLACE_EN; 2440 2441 if (mode->flags & VID_CSYNC) { 2442 v |= RADEON_CRTC2_CSYNC_EN; 2443 if (crtc == 1) 2444 v |= RADEON_CRTC2_VSYNC_TRISTAT; 2445 } 2446 2447 PUT32(sc, gencntl, v); 2448 DPRINTF(("CRTC%s_GEN_CNTL = %08x\n", crtc ? "2" : "", v)); 2449 2450 /* 2451 * CRTC_EXT_CNTL - preserve disable flags, set ATI linear and EXT_CNT 2452 */ 2453 v = GET32(sc, RADEON_CRTC_EXT_CNTL); 2454 if (crtc == 0) { 2455 v &= (RADEON_CRTC_VSYNC_DIS | RADEON_CRTC_HSYNC_DIS | 2456 RADEON_CRTC_DISPLAY_DIS); 2457 v |= RADEON_XCRT_CNT_EN | RADEON_VGA_ATI_LINEAR; 2458 if (mode->flags & VID_CSYNC) 2459 v |= RADEON_CRTC_VSYNC_TRISTAT; 2460 } 2461 /* unconditional turn on CRT, in case first CRTC is DFP */ 2462 v |= RADEON_CRTC_CRT_ON; 2463 PUT32(sc, RADEON_CRTC_EXT_CNTL, v); 2464 PRINTREG(RADEON_CRTC_EXT_CNTL); 2465 2466 hd = ((GET32(sc, htotaldisp) >> 16) + 1) * 8; 2467 vd = (GET32(sc, vtotaldisp) >> 16) + 1; 2468 DPRINTF(("res %d x %d\n", hd, vd)); 2469 2470 if ((hd != mode->hdisplay) || (vd != mode->vdisplay)) { 2471 2472 /* 2473 * H_TOTAL_DISP 2474 */ 2475 v = ((mode->hdisplay / 8) - 1) << 16; 2476 v |= (mode->htotal / 8) - 1; 2477 PRINTREG(RADEON_CRTC_H_TOTAL_DISP); 2478 PUT32(sc, htotaldisp, v); 2479 DPRINTF(("CRTC%s_H_TOTAL_DISP = %08x\n", crtc ? "2" : "", v)); 2480 if (fphtotaldisp) { 2481 PRINTREG(RADEON_FP_CRTC_H_TOTAL_DISP); 2482 PUT32(sc, fphtotaldisp, v); 2483 DPRINTF(("FP_H%s_TOTAL_DISP = %08x\n", crtc ? "2" : "", v)); 2484 } 2485 /* 2486 * H_SYNC_STRT_WID 2487 */ 2488 v = (((mode->hsync_end - mode->hsync_start) / 8) << 16); 2489 v |= (mode->hsync_start - 8); /* match xf86-video-radeon */ 2490 if (mode->flags & VID_NHSYNC) 2491 v |= RADEON_CRTC_H_SYNC_POL; 2492 PUT32(sc, hsyncstrt, v); 2493 DPRINTF(("CRTC%s_H_SYNC_STRT_WID = %08x\n", crtc ? "2" : "", v)); 2494 if (fphsyncstrt) { 2495 PUT32(sc, fphsyncstrt, v); 2496 DPRINTF(("FP_H%s_SYNC_STRT_WID = %08x\n", crtc ? "2" : "", v)); 2497 } 2498 2499 /* 2500 * V_TOTAL_DISP 2501 */ 2502 v = ((mode->vdisplay - 1) << 16); 2503 v |= (mode->vtotal - 1); 2504 PUT32(sc, vtotaldisp, v); 2505 DPRINTF(("CRTC%s_V_TOTAL_DISP = %08x\n", crtc ? "2" : "", v)); 2506 if (fpvtotaldisp) { 2507 PUT32(sc, fpvtotaldisp, v); 2508 DPRINTF(("FP_V%s_TOTAL_DISP = %08x\n", crtc ? "2" : "", v)); 2509 } 2510 2511 /* 2512 * V_SYNC_STRT_WID 2513 */ 2514 v = ((mode->vsync_end - mode->vsync_start) << 16); 2515 v |= (mode->vsync_start - 1); 2516 if (mode->flags & VID_NVSYNC) 2517 v |= RADEON_CRTC_V_SYNC_POL; 2518 PUT32(sc, vsyncstrt, v); 2519 DPRINTF(("CRTC%s_V_SYNC_STRT_WID = %08x\n", crtc ? "2" : "", v)); 2520 if (fpvsyncstrt) { 2521 PUT32(sc, fpvsyncstrt, v); 2522 DPRINTF(("FP_V%s_SYNC_STRT_WID = %08x\n", crtc ? "2" : "", v)); 2523 } 2524 } 2525 radeonfb_program_vclk(sc, mode->dot_clock, crtc, flags); 2526 2527 switch (crtc) { 2528 case 0: 2529 PUT32(sc, RADEON_CRTC_OFFSET, 0); 2530 PUT32(sc, RADEON_CRTC_OFFSET_CNTL, 0); 2531 PUT32(sc, RADEON_CRTC_PITCH, pitch); 2532 CLR32(sc, RADEON_DISP_MERGE_CNTL, RADEON_DISP_RGB_OFFSET_EN); 2533 2534 CLR32(sc, RADEON_CRTC_EXT_CNTL, 2535 RADEON_CRTC_VSYNC_DIS | RADEON_CRTC_HSYNC_DIS | 2536 RADEON_CRTC_DISPLAY_DIS /* | RADEON_CRTC_DISP_REQ_EN_B */); 2537 CLR32(sc, RADEON_CRTC_GEN_CNTL, RADEON_CRTC_DISP_REQ_EN_B); 2538 PRINTREG(RADEON_CRTC_EXT_CNTL); 2539 PRINTREG(RADEON_CRTC_GEN_CNTL); 2540 PRINTREG(RADEON_CLOCK_CNTL_INDEX); 2541 break; 2542 2543 case 1: 2544 PUT32(sc, RADEON_CRTC2_OFFSET, 0); 2545 PUT32(sc, RADEON_CRTC2_OFFSET_CNTL, 0); 2546 PUT32(sc, RADEON_CRTC2_PITCH, pitch); 2547 CLR32(sc, RADEON_DISP2_MERGE_CNTL, RADEON_DISP2_RGB_OFFSET_EN); 2548 CLR32(sc, RADEON_CRTC2_GEN_CNTL, 2549 RADEON_CRTC2_VSYNC_DIS | 2550 RADEON_CRTC2_HSYNC_DIS | 2551 RADEON_CRTC2_DISP_DIS | RADEON_CRTC2_DISP_REQ_EN_B); 2552 PRINTREG(RADEON_CRTC2_GEN_CNTL); 2553 break; 2554 } 2555 } 2556 2557 int 2558 radeonfb_isblank(struct radeonfb_display *dp) 2559 { 2560 struct radeonfb_softc *sc = dp->rd_softc; 2561 uint32_t reg, mask; 2562 2563 if(!dp->rd_softc->sc_mapped) 2564 return 1; 2565 2566 if (IS_AVIVO(sc)) { 2567 reg = GET32(sc, AVIVO_D1CRTC_CONTROL); 2568 return ((reg & AVIVO_CRTC_EN) == 0); 2569 } 2570 2571 if (dp->rd_crtcs[0].rc_number) { 2572 reg = RADEON_CRTC2_GEN_CNTL; 2573 mask = RADEON_CRTC2_DISP_DIS; 2574 } else { 2575 reg = RADEON_CRTC_EXT_CNTL; 2576 mask = RADEON_CRTC_DISPLAY_DIS; 2577 } 2578 return ((GET32(dp->rd_softc, reg) & mask) ? 1 : 0); 2579 } 2580 2581 void 2582 radeonfb_blank(struct radeonfb_display *dp, int blank) 2583 { 2584 struct radeonfb_softc *sc = dp->rd_softc; 2585 uint32_t reg, mask; 2586 uint32_t fpreg, fpval; 2587 int i; 2588 2589 2590 if (!sc->sc_mapped) 2591 return; 2592 2593 if(IS_AVIVO(sc)) { 2594 2595 /* 2596 * XXX 2597 * I don't know how to turn the sunc outputs off for DPMS 2598 * power control, so for now just turn the entire CRTC off 2599 */ 2600 if (blank) { 2601 CLR32(sc, AVIVO_D1CRTC_CONTROL, AVIVO_CRTC_EN); 2602 CLR32(sc, AVIVO_D2CRTC_CONTROL, AVIVO_CRTC_EN); 2603 } else { 2604 SET32(sc, AVIVO_D1CRTC_CONTROL, AVIVO_CRTC_EN); 2605 SET32(sc, AVIVO_D2CRTC_CONTROL, AVIVO_CRTC_EN); 2606 } 2607 return; 2608 } 2609 /* non-AVIVO case */ 2610 for (i = 0; i < dp->rd_ncrtcs; i++) { 2611 2612 if (dp->rd_crtcs[i].rc_number) { 2613 reg = RADEON_CRTC2_GEN_CNTL; 2614 mask = RADEON_CRTC2_DISP_DIS; 2615 fpreg = RADEON_FP2_GEN_CNTL; 2616 fpval = RADEON_FP2_ON; 2617 } else { 2618 reg = RADEON_CRTC_EXT_CNTL; 2619 mask = RADEON_CRTC_DISPLAY_DIS; 2620 fpreg = RADEON_FP_GEN_CNTL; 2621 fpval = RADEON_FP_FPON; 2622 } 2623 2624 if (blank) { 2625 SET32(sc, reg, mask); 2626 CLR32(sc, fpreg, fpval); 2627 } else { 2628 CLR32(sc, reg, mask); 2629 SET32(sc, fpreg, fpval); 2630 } 2631 } 2632 PRINTREG(RADEON_FP_GEN_CNTL); 2633 PRINTREG(RADEON_FP2_GEN_CNTL); 2634 } 2635 2636 void 2637 radeonfb_init_screen(void *cookie, struct vcons_screen *scr, int existing, 2638 long *defattr) 2639 { 2640 struct radeonfb_display *dp = cookie; 2641 struct rasops_info *ri = &scr->scr_ri; 2642 2643 /* initialize font subsystem */ 2644 wsfont_init(); 2645 2646 scr->scr_flags |= VCONS_LOADFONT; 2647 2648 DPRINTF(("init screen called, existing %d\n", existing)); 2649 2650 ri->ri_depth = dp->rd_bpp; 2651 ri->ri_width = dp->rd_virtx; 2652 ri->ri_height = dp->rd_virty; 2653 ri->ri_stride = dp->rd_stride; 2654 ri->ri_flg = RI_CENTER; 2655 switch (ri->ri_depth) { 2656 case 8: 2657 ri->ri_flg |= RI_ENABLE_ALPHA | RI_8BIT_IS_RGB | RI_PREFER_ALPHA; 2658 break; 2659 case 32: 2660 ri->ri_flg |= RI_ENABLE_ALPHA | RI_PREFER_ALPHA; 2661 /* we run radeons in RGB even on SPARC hardware */ 2662 ri->ri_rnum = 8; 2663 ri->ri_gnum = 8; 2664 ri->ri_bnum = 8; 2665 ri->ri_rpos = 16; 2666 ri->ri_gpos = 8; 2667 ri->ri_bpos = 0; 2668 break; 2669 } 2670 2671 ri->ri_bits = (void *)dp->rd_fbptr; 2672 2673 #ifdef VCONS_DRAW_INTR 2674 scr->scr_flags |= VCONS_DONT_READ; 2675 #endif 2676 2677 if (existing) { 2678 ri->ri_flg |= RI_CLEAR; 2679 2680 /* start a modeswitch now */ 2681 //radeonfb_modeswitch(dp); 2682 } 2683 2684 /* 2685 * XXX: font selection should be based on properties, with some 2686 * normal/reasonable default. 2687 */ 2688 2689 /* initialize and look for an initial font */ 2690 rasops_init(ri, 0, 0); 2691 ri->ri_caps = WSSCREEN_UNDERLINE | WSSCREEN_HILIT | 2692 WSSCREEN_WSCOLORS | WSSCREEN_REVERSE | WSSCREEN_RESIZE; 2693 2694 rasops_reconfig(ri, dp->rd_virty / ri->ri_font->fontheight, 2695 dp->rd_virtx / ri->ri_font->fontwidth); 2696 2697 /* enable acceleration */ 2698 dp->rd_putchar = ri->ri_ops.putchar; 2699 ri->ri_ops.copyrows = radeonfb_copyrows; 2700 ri->ri_ops.copycols = radeonfb_copycols; 2701 ri->ri_ops.eraserows = radeonfb_eraserows; 2702 ri->ri_ops.erasecols = radeonfb_erasecols; 2703 /* pick a putchar method based on font and Radeon model */ 2704 if (ri->ri_font->stride < ri->ri_font->fontwidth) { 2705 /* got a bitmap font */ 2706 #if !defined(RADEONFB_ALWAYS_ACCEL_PUTCHAR) 2707 if (IS_R300(dp->rd_softc) && 0) { 2708 /* 2709 * radeonfb_putchar() doesn't work right on some R3xx 2710 * so we use software drawing here, the wrapper just 2711 * makes sure the engine is idle before scribbling 2712 * into vram 2713 */ 2714 ri->ri_ops.putchar = radeonfb_putchar_wrapper; 2715 } else 2716 #endif 2717 ri->ri_ops.putchar = radeonfb_putchar; 2718 } else { 2719 /* got an alpha font */ 2720 switch(ri->ri_depth) { 2721 case 32: 2722 ri->ri_ops.putchar = radeonfb_putchar_aa32; 2723 break; 2724 case 8: 2725 ri->ri_ops.putchar = radeonfb_putchar_aa8; 2726 break; 2727 default: 2728 /* XXX this should never happen */ 2729 panic("%s: depth is not 8 or 32 but we got an" \ 2730 " alpha font?!", __func__); 2731 } 2732 } 2733 ri->ri_ops.cursor = radeonfb_cursor; 2734 } 2735 2736 static uint32_t 2737 radeonfb_avivo_INMC(struct radeonfb_softc *sc, uint32_t addr) 2738 { 2739 uint32_t data; 2740 2741 PUT32(sc, AVIVO_MC_INDEX, (addr & 0xff) | 0x7f0000); 2742 (void)GET32(sc, AVIVO_MC_INDEX); 2743 data = GET32(sc, AVIVO_MC_DATA); 2744 PUT32(sc, AVIVO_MC_INDEX, 0); 2745 (void)GET32(sc, AVIVO_MC_INDEX); 2746 return data; 2747 } 2748 2749 static void 2750 radeonfb_avivo_OUTMC(struct radeonfb_softc *sc, uint32_t addr, uint32_t data) 2751 { 2752 2753 PUT32(sc, AVIVO_MC_INDEX, (addr & 0xff) | 0x7f0000); 2754 (void)GET32(sc, AVIVO_MC_INDEX); 2755 PUT32(sc, AVIVO_MC_DATA, data); 2756 PUT32(sc, AVIVO_MC_INDEX, 0); 2757 (void)GET32(sc, AVIVO_MC_INDEX); 2758 } 2759 2760 void 2761 radeonfb_set_fbloc(struct radeonfb_softc *sc) 2762 { 2763 uint32_t gen = 0, ext = 0, gen2 = 0; 2764 uint32_t agploc, aperbase, apersize, mcfbloc; 2765 2766 2767 if (IS_AVIVO(sc)) { 2768 agploc = radeonfb_avivo_INMC(sc, R520_MC_AGP_LOCATION); 2769 } else { 2770 gen = GET32(sc, RADEON_CRTC_GEN_CNTL); 2771 /* XXX */ 2772 ext = GET32(sc, RADEON_CRTC_EXT_CNTL) & ~RADEON_CRTC_DISPLAY_DIS; 2773 agploc = GET32(sc, RADEON_MC_AGP_LOCATION); 2774 PUT32(sc, RADEON_CRTC_GEN_CNTL, gen | RADEON_CRTC_DISP_REQ_EN_B); 2775 PUT32(sc, RADEON_CRTC_EXT_CNTL, ext | RADEON_CRTC_DISPLAY_DIS); 2776 #if 0 2777 PUT32(sc, RADEON_CRTC_GEN_CNTL, gen | RADEON_CRTC_DISPLAY_DIS); 2778 PUT32(sc, RADEON_CRTC_EXT_CNTL, ext | RADEON_CRTC_DISP_REQ_EN_B); 2779 #endif 2780 2781 if (HAS_CRTC2(sc)) { 2782 gen2 = GET32(sc, RADEON_CRTC2_GEN_CNTL); 2783 PUT32(sc, RADEON_CRTC2_GEN_CNTL, 2784 gen2 | RADEON_CRTC2_DISP_REQ_EN_B); 2785 } 2786 2787 delay(100000); 2788 } 2789 2790 aperbase = GET32(sc, RADEON_CONFIG_APER_0_BASE); 2791 apersize = GET32(sc, RADEON_CONFIG_APER_SIZE); 2792 2793 2794 mcfbloc = (aperbase >> 16) | 2795 ((aperbase + (apersize - 1)) & 0xffff0000); 2796 2797 sc->sc_aperbase = (mcfbloc & 0xffff) << 16; 2798 sc->sc_memsz = apersize; 2799 DPRINTF(("aperbase = %08x\n", aperbase)); 2800 2801 if (((agploc & 0xffff) << 16) != 2802 ((mcfbloc & 0xffff0000U) + 0x10000)) { 2803 agploc = mcfbloc & 0xffff0000U; 2804 agploc |= ((agploc + 0x10000) >> 16); 2805 } 2806 2807 PUT32(sc, RADEON_HOST_PATH_CNTL, 0); 2808 2809 if (IS_AVIVO(sc)) { 2810 radeonfb_avivo_OUTMC(sc, R520_MC_FB_LOCATION, mcfbloc); 2811 radeonfb_avivo_OUTMC(sc, R520_MC_AGP_LOCATION, agploc); 2812 PRINTREG(AVIVO_HDP_FB_LOCATION); 2813 DPRINTF((" FB loc %08x\n", radeonfb_avivo_INMC(sc, R520_MC_FB_LOCATION))); 2814 DPRINTF(("AGP loc %08x\n", radeonfb_avivo_INMC(sc, R520_MC_AGP_LOCATION))); 2815 } else { 2816 PUT32(sc, RADEON_MC_FB_LOCATION, mcfbloc); 2817 PUT32(sc, RADEON_MC_AGP_LOCATION, agploc); 2818 PRINTREG(RADEON_MC_FB_LOCATION); 2819 PRINTREG(RADEON_MC_AGP_LOCATION); 2820 2821 PUT32(sc, RADEON_DISPLAY_BASE_ADDR, sc->sc_aperbase); 2822 2823 if (HAS_CRTC2(sc)) 2824 PUT32(sc, RADEON_DISPLAY2_BASE_ADDR, sc->sc_aperbase); 2825 2826 PUT32(sc, RADEON_OV0_BASE_ADDR, sc->sc_aperbase); 2827 delay(100000); 2828 2829 PUT32(sc, RADEON_CRTC_GEN_CNTL, gen); 2830 PUT32(sc, RADEON_CRTC_EXT_CNTL, ext); 2831 2832 if (HAS_CRTC2(sc)) 2833 PUT32(sc, RADEON_CRTC2_GEN_CNTL, gen2); 2834 } 2835 #if 0 2836 /* XXX: what is this AGP garbage? :-) */ 2837 PUT32(sc, RADEON_AGP_CNTL, 0x00100000); 2838 #endif 2839 } 2840 2841 void 2842 radeonfb_init_misc(struct radeonfb_softc *sc) 2843 { 2844 PUT32(sc, RADEON_BUS_CNTL, 2845 RADEON_BUS_MASTER_DIS | 2846 RADEON_BUS_PREFETCH_MODE_ACT | 2847 RADEON_BUS_PCI_READ_RETRY_EN | 2848 RADEON_BUS_PCI_WRT_RETRY_EN | 2849 (3 << RADEON_BUS_RETRY_WS_SHIFT) | 2850 RADEON_BUS_MSTR_RD_MULT | 2851 RADEON_BUS_MSTR_RD_LINE | 2852 RADEON_BUS_RD_DISCARD_EN | 2853 RADEON_BUS_MSTR_DISCONNECT_EN | 2854 RADEON_BUS_READ_BURST); 2855 2856 PUT32(sc, RADEON_BUS_CNTL1, 0xf0); 2857 /* PUT32(sc, RADEON_SEPROM_CNTL1, 0x09ff0000); */ 2858 PUT32(sc, RADEON_FCP_CNTL, RADEON_FCP0_SRC_GND); 2859 PUT32(sc, RADEON_RBBM_CNTL, 2860 (3 << RADEON_RB_SETTLE_SHIFT) | 2861 (4 << RADEON_ABORTCLKS_HI_SHIFT) | 2862 (4 << RADEON_ABORTCLKS_CP_SHIFT) | 2863 (4 << RADEON_ABORTCLKS_CFIFO_SHIFT)); 2864 2865 /* XXX: figure out what these mean! */ 2866 PUT32(sc, RADEON_AGP_CNTL, 0x00100000); 2867 PUT32(sc, RADEON_HOST_PATH_CNTL, 0); 2868 #if 0 2869 PUT32(sc, RADEON_DISP_MISC_CNTL, 0x5bb00400); 2870 #endif 2871 2872 PUT32(sc, RADEON_GEN_INT_CNTL, 0); 2873 PUT32(sc, RADEON_GEN_INT_STATUS, GET32(sc, RADEON_GEN_INT_STATUS)); 2874 } 2875 2876 static void 2877 radeonfb_putpal(struct radeonfb_display *dp, int idx, int r, int g, int b) 2878 { 2879 struct radeonfb_softc *sc = dp->rd_softc; 2880 int crtc, cc; 2881 uint32_t vclk; 2882 2883 if (IS_AVIVO(sc)) { 2884 for (cc = 0; cc < dp->rd_ncrtcs; cc++) { 2885 crtc = dp->rd_crtcs[cc].rc_number; 2886 2887 if (crtc) 2888 PUT32(sc, AVIVO_DC_LUT_RW_SELECT, 1); 2889 else 2890 PUT32(sc, AVIVO_DC_LUT_RW_SELECT, 0); 2891 2892 PUT32(sc, AVIVO_DC_LUT_RW_INDEX, idx); 2893 PUT32(sc, AVIVO_DC_LUT_30_COLOR, 2894 (r << 22) | (g << 12) | (b << 2)); 2895 } 2896 2897 } else { 2898 vclk = GETPLL(sc, RADEON_VCLK_ECP_CNTL); 2899 PUTPLL(sc, RADEON_VCLK_ECP_CNTL, 2900 vclk & ~RADEON_PIXCLK_DAC_ALWAYS_ONb); 2901 2902 /* init the palette for every CRTC used by this display */ 2903 for (cc = 0; cc < dp->rd_ncrtcs; cc++) { 2904 crtc = dp->rd_crtcs[cc].rc_number; 2905 2906 if (crtc) 2907 SET32(sc, RADEON_DAC_CNTL2, 2908 RADEON_DAC2_PALETTE_ACC_CTL); 2909 else 2910 CLR32(sc, RADEON_DAC_CNTL2, 2911 RADEON_DAC2_PALETTE_ACC_CTL); 2912 2913 PUT32(sc, RADEON_PALETTE_INDEX, idx); 2914 PUT32(sc, RADEON_PALETTE_30_DATA, 2915 (r << 22) | (g << 12) | (b << 2)); 2916 } 2917 2918 PUTPLL(sc, RADEON_VCLK_ECP_CNTL, vclk); 2919 } 2920 } 2921 2922 /* 2923 * This loads a linear color map for true color. 2924 */ 2925 void 2926 radeonfb_init_palette(struct radeonfb_display *dp) 2927 { 2928 int i; 2929 2930 #define DAC_WIDTH ((1 << 10) - 1) 2931 #define CLUT_WIDTH ((1 << 8) - 1) 2932 #define CLUT_COLOR(i) ((i * DAC_WIDTH * 2 / CLUT_WIDTH + 1) / 2) 2933 2934 if (dp->rd_bpp == 8) { 2935 2936 /* R3G3B2 palette */ 2937 uint32_t tmp, r, g, b; 2938 2939 for (i = 0; i <= CLUT_WIDTH; ++i) { 2940 tmp = i & 0xe0; 2941 2942 /* 2943 * replicate bits so 0xe0 maps to a red value of 0xff 2944 * in order to make white look actually white 2945 */ 2946 tmp |= (tmp >> 3) | (tmp >> 6); 2947 r = tmp; 2948 2949 tmp = (i & 0x1c) << 3; 2950 tmp |= (tmp >> 3) | (tmp >> 6); 2951 g = tmp; 2952 2953 tmp = (i & 0x03) << 6; 2954 tmp |= tmp >> 2; 2955 tmp |= tmp >> 4; 2956 b = tmp; 2957 2958 dp->rd_cmap_red[i] = r; 2959 dp->rd_cmap_green[i] = g; 2960 dp->rd_cmap_blue[i] = b; 2961 radeonfb_putpal(dp, i, r, g, b); 2962 } 2963 } else { 2964 /* linear ramp */ 2965 for (i = 0; i <= CLUT_WIDTH; ++i) { 2966 radeonfb_putpal(dp, i, i, i, i); 2967 } 2968 } 2969 } 2970 2971 static int 2972 radeonfb_putcmap(struct radeonfb_display *dp, struct wsdisplay_cmap *cm) 2973 { 2974 u_char *r, *g, *b; 2975 u_int index = cm->index; 2976 u_int count = cm->count; 2977 int i, error; 2978 u_char rbuf[256], gbuf[256], bbuf[256]; 2979 2980 #ifdef GENFB_DEBUG 2981 aprint_debug("putcmap: %d %d\n",index, count); 2982 #endif 2983 if (index >= 256 || count > 256 - index) 2984 return EINVAL; 2985 error = copyin(cm->red, &rbuf[index], count); 2986 if (error) 2987 return error; 2988 error = copyin(cm->green, &gbuf[index], count); 2989 if (error) 2990 return error; 2991 error = copyin(cm->blue, &bbuf[index], count); 2992 if (error) 2993 return error; 2994 2995 memcpy(&dp->rd_cmap_red[index], &rbuf[index], count); 2996 memcpy(&dp->rd_cmap_green[index], &gbuf[index], count); 2997 memcpy(&dp->rd_cmap_blue[index], &bbuf[index], count); 2998 2999 r = &dp->rd_cmap_red[index]; 3000 g = &dp->rd_cmap_green[index]; 3001 b = &dp->rd_cmap_blue[index]; 3002 3003 for (i = 0; i < count; i++) { 3004 radeonfb_putpal(dp, index, *r, *g, *b); 3005 index++; 3006 r++, g++, b++; 3007 } 3008 return 0; 3009 } 3010 3011 static int 3012 radeonfb_getcmap(struct radeonfb_display *dp, struct wsdisplay_cmap *cm) 3013 { 3014 u_int index = cm->index; 3015 u_int count = cm->count; 3016 int error; 3017 3018 if (index >= 256 || count > 256 - index) 3019 return EINVAL; 3020 3021 error = copyout(&dp->rd_cmap_red[index], cm->red, count); 3022 if (error) 3023 return error; 3024 error = copyout(&dp->rd_cmap_green[index], cm->green, count); 3025 if (error) 3026 return error; 3027 error = copyout(&dp->rd_cmap_blue[index], cm->blue, count); 3028 if (error) 3029 return error; 3030 3031 return 0; 3032 } 3033 3034 /* 3035 * Bugs in some R300 hardware requires this when accessing CLOCK_CNTL_INDEX. 3036 */ 3037 void 3038 radeonfb_r300cg_workaround(struct radeonfb_softc *sc) 3039 { 3040 uint32_t tmp, save; 3041 3042 save = GET32(sc, RADEON_CLOCK_CNTL_INDEX); 3043 tmp = save & ~(0x3f | RADEON_PLL_WR_EN); 3044 PUT32(sc, RADEON_CLOCK_CNTL_INDEX, tmp); 3045 tmp = GET32(sc, RADEON_CLOCK_CNTL_DATA); 3046 PUT32(sc, RADEON_CLOCK_CNTL_INDEX, save); 3047 } 3048 3049 /* 3050 * Acceleration entry points. 3051 */ 3052 3053 /* this one draws characters using bitmap fonts */ 3054 static void 3055 radeonfb_putchar(void *cookie, int row, int col, u_int c, long attr) 3056 { 3057 struct rasops_info *ri = cookie; 3058 struct vcons_screen *scr = ri->ri_hw; 3059 struct radeonfb_display *dp = scr->scr_cookie; 3060 struct radeonfb_softc *sc = dp->rd_softc; 3061 struct wsdisplay_font *font = PICK_FONT(ri, c); 3062 uint32_t w, h; 3063 int xd, yd, offset, i; 3064 uint32_t bg, fg, gmc; 3065 uint32_t reg; 3066 uint8_t *data8; 3067 uint16_t *data16; 3068 uint32_t *data32; 3069 void *data; 3070 3071 if (dp->rd_wsmode != WSDISPLAYIO_MODE_EMUL) 3072 return; 3073 3074 if (!CHAR_IN_FONT(c, font)) 3075 return; 3076 3077 w = font->fontwidth; 3078 h = font->fontheight; 3079 3080 bg = ri->ri_devcmap[(attr >> 16) & 0xf]; 3081 fg = ri->ri_devcmap[(attr >> 24) & 0xf]; 3082 3083 xd = ri->ri_xorigin + col * w; 3084 yd = ri->ri_yorigin + row * h; 3085 3086 if (c == 0x20) { 3087 radeonfb_rectfill(dp, xd, yd, w, h, bg); 3088 return; 3089 } 3090 data = WSFONT_GLYPH(c, font); 3091 3092 gmc = dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT; 3093 3094 radeonfb_wait_fifo(sc, 9); 3095 3096 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 3097 RADEON_GMC_BRUSH_NONE | 3098 RADEON_GMC_SRC_DATATYPE_MONO_FG_BG | 3099 RADEON_GMC_DST_CLIPPING | 3100 RADEON_ROP3_S | 3101 RADEON_DP_SRC_SOURCE_HOST_DATA | 3102 RADEON_GMC_CLR_CMP_CNTL_DIS | 3103 RADEON_GMC_WR_MSK_DIS | 3104 gmc); 3105 3106 PUT32(sc, RADEON_SC_LEFT, xd); 3107 PUT32(sc, RADEON_SC_RIGHT, xd + w); 3108 PUT32(sc, RADEON_DP_SRC_FRGD_CLR, fg); 3109 PUT32(sc, RADEON_DP_SRC_BKGD_CLR, bg); 3110 PUT32(sc, RADEON_DP_CNTL, 3111 RADEON_DST_X_LEFT_TO_RIGHT | 3112 RADEON_DST_Y_TOP_TO_BOTTOM); 3113 3114 PUT32(sc, RADEON_SRC_X_Y, 0); 3115 offset = 32 - (font->stride << 3); 3116 PUT32(sc, RADEON_DST_X_Y, ((xd - offset) << 16) | yd); 3117 PUT32(sc, RADEON_DST_WIDTH_HEIGHT, (32 << 16) | h); 3118 3119 radeonfb_wait_fifo(sc, h); 3120 switch (font->stride) { 3121 case 1: { 3122 data8 = data; 3123 for (i = 0; i < h; i++) { 3124 reg = *data8; 3125 #if BYTE_ORDER == LITTLE_ENDIAN 3126 reg = reg << 24; 3127 #endif 3128 bus_space_write_stream_4(sc->sc_regt, 3129 sc->sc_regh, RADEON_HOST_DATA0, reg); 3130 data8++; 3131 } 3132 break; 3133 } 3134 case 2: { 3135 data16 = data; 3136 for (i = 0; i < h; i++) { 3137 reg = *data16; 3138 #if BYTE_ORDER == LITTLE_ENDIAN 3139 reg = reg << 16; 3140 #endif 3141 bus_space_write_stream_4(sc->sc_regt, 3142 sc->sc_regh, RADEON_HOST_DATA0, reg); 3143 data16++; 3144 } 3145 break; 3146 } 3147 case 4: { 3148 data32 = data; 3149 for (i = 0; i < h; i++) { 3150 reg = *data32; 3151 bus_space_write_stream_4(sc->sc_regt, 3152 sc->sc_regh, RADEON_HOST_DATA0, reg); 3153 data32++; 3154 } 3155 break; 3156 } 3157 } 3158 if (attr & 1) 3159 radeonfb_rectfill(dp, xd, yd + h - 2, w, 1, fg); 3160 } 3161 3162 /* ... while this one is for anti-aliased ones */ 3163 static void 3164 radeonfb_putchar_aa32(void *cookie, int row, int col, u_int c, long attr) 3165 { 3166 struct rasops_info *ri = cookie; 3167 struct vcons_screen *scr = ri->ri_hw; 3168 struct radeonfb_display *dp = scr->scr_cookie; 3169 struct radeonfb_softc *sc = dp->rd_softc; 3170 struct wsdisplay_font *font = PICK_FONT(ri, c); 3171 uint32_t bg, fg, gmc; 3172 uint8_t *data; 3173 int w, h, xd, yd; 3174 int i, r, g, b, aval; 3175 int rf, gf, bf, rb, gb, bb; 3176 uint32_t pixel; 3177 int rv; 3178 3179 if (dp->rd_wsmode != WSDISPLAYIO_MODE_EMUL) 3180 return; 3181 3182 if (!CHAR_IN_FONT(c, font)) 3183 return; 3184 3185 w = font->fontwidth; 3186 h = font->fontheight; 3187 3188 bg = ri->ri_devcmap[(attr >> 16) & 0xf]; 3189 fg = ri->ri_devcmap[(attr >> 24) & 0xf]; 3190 3191 xd = ri->ri_xorigin + col * w; 3192 yd = ri->ri_yorigin + row * h; 3193 3194 if (c == 0x20) { 3195 radeonfb_rectfill(dp, xd, yd, w, h, bg); 3196 if (attr & 1) 3197 radeonfb_rectfill(dp, xd, yd + h - 2, w, 1, fg); 3198 return; 3199 } 3200 rv = glyphcache_try(&dp->rd_gc, c, xd, yd, attr); 3201 if (rv == GC_OK) 3202 return; 3203 3204 data = WSFONT_GLYPH(c, font); 3205 3206 gmc = dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT; 3207 3208 radeonfb_wait_fifo(sc, 5); 3209 3210 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 3211 RADEON_GMC_BRUSH_NONE | 3212 RADEON_GMC_SRC_DATATYPE_COLOR | 3213 RADEON_ROP3_S | 3214 RADEON_DP_SRC_SOURCE_HOST_DATA | 3215 RADEON_GMC_CLR_CMP_CNTL_DIS | 3216 RADEON_GMC_WR_MSK_DIS | 3217 gmc); 3218 3219 PUT32(sc, RADEON_DP_CNTL, 3220 RADEON_DST_X_LEFT_TO_RIGHT | 3221 RADEON_DST_Y_TOP_TO_BOTTOM); 3222 3223 PUT32(sc, RADEON_SRC_X_Y, 0); 3224 PUT32(sc, RADEON_DST_X_Y, (xd << 16) | yd); 3225 PUT32(sc, RADEON_DST_WIDTH_HEIGHT, (w << 16) | h); 3226 3227 rf = (fg >> 16) & 0xff; 3228 rb = (bg >> 16) & 0xff; 3229 gf = (fg >> 8) & 0xff; 3230 gb = (bg >> 8) & 0xff; 3231 bf = fg & 0xff; 3232 bb = bg & 0xff; 3233 3234 /* 3235 * I doubt we can upload data faster than even the slowest Radeon 3236 * could process them, especially when doing the alpha blending stuff 3237 * along the way, so just make sure there's some room in the FIFO and 3238 * then hammer away 3239 * As it turns out we can, so make periodic stops to let the FIFO 3240 * drain. 3241 */ 3242 radeonfb_wait_fifo(sc, 20); 3243 for (i = 0; i < ri->ri_fontscale; i++) { 3244 aval = *data; 3245 data++; 3246 if (aval == 0) { 3247 pixel = bg; 3248 } else if (aval == 255) { 3249 pixel = fg; 3250 } else { 3251 r = aval * rf + (255 - aval) * rb; 3252 g = aval * gf + (255 - aval) * gb; 3253 b = aval * bf + (255 - aval) * bb; 3254 pixel = (r & 0xff00) << 8 | 3255 (g & 0xff00) | 3256 (b & 0xff00) >> 8; 3257 } 3258 if (i & 16) 3259 radeonfb_wait_fifo(sc, 20); 3260 PUT32(sc, RADEON_HOST_DATA0, pixel); 3261 } 3262 if (rv == GC_ADD) { 3263 glyphcache_add(&dp->rd_gc, c, xd, yd); 3264 } else if (attr & 1) 3265 radeonfb_rectfill(dp, xd, yd + h - 2, w, 1, fg); 3266 } 3267 3268 static void 3269 radeonfb_putchar_aa8(void *cookie, int row, int col, u_int c, long attr) 3270 { 3271 struct rasops_info *ri = cookie; 3272 struct vcons_screen *scr = ri->ri_hw; 3273 struct radeonfb_display *dp = scr->scr_cookie; 3274 struct radeonfb_softc *sc = dp->rd_softc; 3275 struct wsdisplay_font *font = PICK_FONT(ri, c); 3276 uint32_t bg, fg, latch = 0, bg8, fg8, pixel, gmc; 3277 int i, x, y, wi, he, r, g, b, aval; 3278 int r1, g1, b1, r0, g0, b0, fgo, bgo; 3279 uint8_t *data8; 3280 int rv, cnt; 3281 3282 if (dp->rd_wsmode != WSDISPLAYIO_MODE_EMUL) 3283 return; 3284 3285 if (!CHAR_IN_FONT(c, font)) 3286 return; 3287 3288 wi = font->fontwidth; 3289 he = font->fontheight; 3290 3291 bg = ri->ri_devcmap[(attr >> 16) & 0xf]; 3292 fg = ri->ri_devcmap[(attr >> 24) & 0xf]; 3293 3294 x = ri->ri_xorigin + col * wi; 3295 y = ri->ri_yorigin + row * he; 3296 3297 if (c == 0x20) { 3298 radeonfb_rectfill(dp, x, y, wi, he, bg); 3299 if (attr & 1) 3300 radeonfb_rectfill(dp, x, y + he - 2, wi, 1, fg); 3301 return; 3302 } 3303 rv = glyphcache_try(&dp->rd_gc, c, x, y, attr); 3304 if (rv == GC_OK) 3305 return; 3306 3307 data8 = WSFONT_GLYPH(c, font); 3308 3309 gmc = dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT; 3310 3311 radeonfb_wait_fifo(sc, 5); 3312 3313 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 3314 RADEON_GMC_BRUSH_NONE | 3315 RADEON_GMC_SRC_DATATYPE_COLOR | 3316 RADEON_ROP3_S | 3317 RADEON_DP_SRC_SOURCE_HOST_DATA | 3318 RADEON_GMC_CLR_CMP_CNTL_DIS | 3319 RADEON_GMC_WR_MSK_DIS | 3320 gmc); 3321 3322 PUT32(sc, RADEON_DP_CNTL, 3323 RADEON_DST_X_LEFT_TO_RIGHT | 3324 RADEON_DST_Y_TOP_TO_BOTTOM); 3325 3326 PUT32(sc, RADEON_SRC_X_Y, 0); 3327 PUT32(sc, RADEON_DST_X_Y, (x << 16) | y); 3328 PUT32(sc, RADEON_DST_WIDTH_HEIGHT, (wi << 16) | he); 3329 3330 /* 3331 * we need the RGB colours here, so get offsets into rasops_cmap 3332 */ 3333 fgo = ((attr >> 24) & 0xf) * 3; 3334 bgo = ((attr >> 16) & 0xf) * 3; 3335 3336 r0 = rasops_cmap[bgo]; 3337 r1 = rasops_cmap[fgo]; 3338 g0 = rasops_cmap[bgo + 1]; 3339 g1 = rasops_cmap[fgo + 1]; 3340 b0 = rasops_cmap[bgo + 2]; 3341 b1 = rasops_cmap[fgo + 2]; 3342 #define R3G3B2(r, g, b) ((r & 0xe0) | ((g >> 3) & 0x1c) | (b >> 6)) 3343 bg8 = R3G3B2(r0, g0, b0); 3344 fg8 = R3G3B2(r1, g1, b1); 3345 3346 radeonfb_wait_fifo(sc, 20); 3347 cnt = 0; 3348 for (i = 0; i < ri->ri_fontscale; i++) { 3349 aval = *data8; 3350 if (aval == 0) { 3351 pixel = bg8; 3352 } else if (aval == 255) { 3353 pixel = fg8; 3354 } else { 3355 r = aval * r1 + (255 - aval) * r0; 3356 g = aval * g1 + (255 - aval) * g0; 3357 b = aval * b1 + (255 - aval) * b0; 3358 pixel = ((r & 0xe000) >> 8) | 3359 ((g & 0xe000) >> 11) | 3360 ((b & 0xc000) >> 14); 3361 } 3362 latch |= pixel << (8 * (i & 3)); 3363 /* write in 32bit chunks */ 3364 if ((i & 3) == 3) { 3365 PUT32(sc, RADEON_HOST_DATA0, latch); 3366 /* 3367 * not strictly necessary, old data should be shifted 3368 * out 3369 */ 3370 latch = 0; 3371 cnt++; 3372 if (cnt > 16) { 3373 cnt = 0; 3374 radeonfb_wait_fifo(sc, 20); 3375 } 3376 } 3377 data8++; 3378 } 3379 /* if we have pixels left in latch write them out */ 3380 if ((i & 3) != 0) { 3381 /* 3382 * radeon is weird - apparently leftover pixels are written 3383 * from the middle, not from the left as everything else 3384 */ 3385 PUT32(sc, RADEON_HOST_DATA0, latch); 3386 } 3387 3388 if (rv == GC_ADD) { 3389 glyphcache_add(&dp->rd_gc, c, x, y); 3390 } else 3391 if (attr & 1) 3392 radeonfb_rectfill(dp, x, y + he - 2, wi, 1, fg); 3393 } 3394 3395 /* 3396 * wrapper for software character drawing 3397 * just sync the engine and call rasops*_putchar() 3398 */ 3399 3400 #ifndef RADEONFB_ALWAYS_ACCEL_PUTCHAR 3401 static void 3402 radeonfb_putchar_wrapper(void *cookie, int row, int col, u_int c, long attr) 3403 { 3404 struct rasops_info *ri = cookie; 3405 struct vcons_screen *scr = ri->ri_hw; 3406 struct radeonfb_display *dp = scr->scr_cookie; 3407 3408 radeonfb_engine_idle(dp->rd_softc); 3409 dp->rd_putchar(ri, row, col, c, attr); 3410 } 3411 #endif 3412 3413 static void 3414 radeonfb_eraserows(void *cookie, int row, int nrows, long fillattr) 3415 { 3416 struct rasops_info *ri = cookie; 3417 struct vcons_screen *scr = ri->ri_hw; 3418 struct radeonfb_display *dp = scr->scr_cookie; 3419 uint32_t x, y, w, h, fg, bg, ul; 3420 3421 /* XXX: check for full emulation mode? */ 3422 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 3423 x = ri->ri_xorigin; 3424 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 3425 w = ri->ri_emuwidth; 3426 h = ri->ri_font->fontheight * nrows; 3427 3428 rasops_unpack_attr(fillattr, &fg, &bg, &ul); 3429 radeonfb_rectfill(dp, x, y, w, h, ri->ri_devcmap[bg & 0xf]); 3430 } 3431 } 3432 3433 static void 3434 radeonfb_copyrows(void *cookie, int srcrow, int dstrow, int nrows) 3435 { 3436 struct rasops_info *ri = cookie; 3437 struct vcons_screen *scr = ri->ri_hw; 3438 struct radeonfb_display *dp = scr->scr_cookie; 3439 uint32_t x, ys, yd, w, h; 3440 3441 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 3442 x = ri->ri_xorigin; 3443 ys = ri->ri_yorigin + ri->ri_font->fontheight * srcrow; 3444 yd = ri->ri_yorigin + ri->ri_font->fontheight * dstrow; 3445 w = ri->ri_emuwidth; 3446 h = ri->ri_font->fontheight * nrows; 3447 radeonfb_bitblt(dp, x, ys, x, yd, w, h, 3448 RADEON_ROP3_S); 3449 } 3450 } 3451 3452 static void 3453 radeonfb_copycols(void *cookie, int row, int srccol, int dstcol, int ncols) 3454 { 3455 struct rasops_info *ri = cookie; 3456 struct vcons_screen *scr = ri->ri_hw; 3457 struct radeonfb_display *dp = scr->scr_cookie; 3458 uint32_t xs, xd, y, w, h; 3459 3460 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 3461 xs = ri->ri_xorigin + ri->ri_font->fontwidth * srccol; 3462 xd = ri->ri_xorigin + ri->ri_font->fontwidth * dstcol; 3463 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 3464 w = ri->ri_font->fontwidth * ncols; 3465 h = ri->ri_font->fontheight; 3466 radeonfb_bitblt(dp, xs, y, xd, y, w, h, 3467 RADEON_ROP3_S); 3468 } 3469 } 3470 3471 static void 3472 radeonfb_erasecols(void *cookie, int row, int startcol, int ncols, 3473 long fillattr) 3474 { 3475 struct rasops_info *ri = cookie; 3476 struct vcons_screen *scr = ri->ri_hw; 3477 struct radeonfb_display *dp = scr->scr_cookie; 3478 uint32_t x, y, w, h, fg, bg, ul; 3479 3480 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 3481 x = ri->ri_xorigin + ri->ri_font->fontwidth * startcol; 3482 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 3483 w = ri->ri_font->fontwidth * ncols; 3484 h = ri->ri_font->fontheight; 3485 3486 rasops_unpack_attr(fillattr, &fg, &bg, &ul); 3487 radeonfb_rectfill(dp, x, y, w, h, ri->ri_devcmap[bg & 0xf]); 3488 } 3489 } 3490 3491 static void 3492 radeonfb_cursor(void *cookie, int on, int row, int col) 3493 { 3494 struct rasops_info *ri = cookie; 3495 struct vcons_screen *scr = ri->ri_hw; 3496 struct radeonfb_display *dp = scr->scr_cookie; 3497 int x, y, wi, he; 3498 3499 wi = ri->ri_font->fontwidth; 3500 he = ri->ri_font->fontheight; 3501 3502 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 3503 x = ri->ri_ccol * wi + ri->ri_xorigin; 3504 y = ri->ri_crow * he + ri->ri_yorigin; 3505 /* first turn off the old cursor */ 3506 if (ri->ri_flg & RI_CURSOR) { 3507 radeonfb_bitblt(dp, x, y, x, y, wi, he, 3508 RADEON_ROP3_Dn); 3509 ri->ri_flg &= ~RI_CURSOR; 3510 } 3511 ri->ri_crow = row; 3512 ri->ri_ccol = col; 3513 /* then (possibly) turn on the new one */ 3514 if (on) { 3515 x = ri->ri_ccol * wi + ri->ri_xorigin; 3516 y = ri->ri_crow * he + ri->ri_yorigin; 3517 radeonfb_bitblt(dp, x, y, x, y, wi, he, 3518 RADEON_ROP3_Dn); 3519 ri->ri_flg |= RI_CURSOR; 3520 } 3521 } else { 3522 scr->scr_ri.ri_crow = row; 3523 scr->scr_ri.ri_ccol = col; 3524 scr->scr_ri.ri_flg &= ~RI_CURSOR; 3525 } 3526 } 3527 3528 /* 3529 * Underlying acceleration support. 3530 */ 3531 3532 static void 3533 radeonfb_rectfill(struct radeonfb_display *dp, int dstx, int dsty, 3534 int width, int height, uint32_t color) 3535 { 3536 struct radeonfb_softc *sc = dp->rd_softc; 3537 uint32_t gmc; 3538 3539 gmc = dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT; 3540 3541 radeonfb_wait_fifo(sc, 6); 3542 3543 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 3544 RADEON_GMC_BRUSH_SOLID_COLOR | 3545 RADEON_GMC_SRC_DATATYPE_COLOR | 3546 RADEON_GMC_CLR_CMP_CNTL_DIS | 3547 RADEON_ROP3_P | gmc); 3548 3549 PUT32(sc, RADEON_DP_BRUSH_FRGD_CLR, color); 3550 PUT32(sc, RADEON_DP_WRITE_MASK, 0xffffffff); 3551 PUT32(sc, RADEON_DP_CNTL, 3552 RADEON_DST_X_LEFT_TO_RIGHT | 3553 RADEON_DST_Y_TOP_TO_BOTTOM); 3554 PUT32(sc, RADEON_DST_Y_X, (dsty << 16) | dstx); 3555 PUT32(sc, RADEON_DST_WIDTH_HEIGHT, (width << 16) | (height)); 3556 } 3557 3558 static void 3559 radeonfb_rectfill_a(void *cookie, int dstx, int dsty, 3560 int width, int height, long attr) 3561 { 3562 struct radeonfb_display *dp = cookie; 3563 3564 radeonfb_rectfill(dp, dstx, dsty, width, height, 3565 dp->rd_vscreen.scr_ri.ri_devcmap[(attr >> 24 & 0xf)]); 3566 } 3567 3568 static void 3569 radeonfb_bitblt(void *cookie, int srcx, int srcy, 3570 int dstx, int dsty, int width, int height, int rop) 3571 { 3572 struct radeonfb_display *dp = cookie; 3573 struct radeonfb_softc *sc = dp->rd_softc; 3574 uint32_t gmc; 3575 uint32_t dir; 3576 3577 if (dsty < srcy) { 3578 dir = RADEON_DST_Y_TOP_TO_BOTTOM; 3579 } else { 3580 srcy += height - 1; 3581 dsty += height - 1; 3582 dir = 0; 3583 } 3584 if (dstx < srcx) { 3585 dir |= RADEON_DST_X_LEFT_TO_RIGHT; 3586 } else { 3587 srcx += width - 1; 3588 dstx += width - 1; 3589 } 3590 3591 gmc = dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT; 3592 3593 radeonfb_wait_fifo(sc, 6); 3594 3595 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 3596 RADEON_GMC_BRUSH_NONE | 3597 RADEON_GMC_SRC_DATATYPE_COLOR | 3598 RADEON_GMC_CLR_CMP_CNTL_DIS | 3599 RADEON_DP_SRC_SOURCE_MEMORY | 3600 rop | gmc); 3601 3602 PUT32(sc, RADEON_DP_WRITE_MASK, 0xffffffff); 3603 PUT32(sc, RADEON_DP_CNTL, dir); 3604 PUT32(sc, RADEON_SRC_Y_X, (srcy << 16) | srcx); 3605 PUT32(sc, RADEON_DST_Y_X, (dsty << 16) | dstx); 3606 PUT32(sc, RADEON_DST_WIDTH_HEIGHT, (width << 16) | (height)); 3607 } 3608 3609 static void 3610 radeonfb_engine_idle(struct radeonfb_softc *sc) 3611 { 3612 3613 radeonfb_wait_fifo(sc, 64); 3614 while ((GET32(sc, RADEON_RBBM_STATUS) & 3615 RADEON_RBBM_ACTIVE) != 0); 3616 radeonfb_engine_flush(sc); 3617 } 3618 3619 static inline void 3620 radeonfb_wait_fifo(struct radeonfb_softc *sc, int n) 3621 { 3622 int i; 3623 3624 for (i = RADEON_TIMEOUT; i; i--) { 3625 if ((GET32(sc, RADEON_RBBM_STATUS) & 3626 RADEON_RBBM_FIFOCNT_MASK) >= n) 3627 return; 3628 } 3629 #ifdef RADEONFB_DEBUG 3630 if (!i) 3631 printf("%s: timed out waiting for fifo (%x)\n", 3632 XNAME(sc), GET32(sc, RADEON_RBBM_STATUS)); 3633 #endif 3634 } 3635 3636 static void 3637 radeonfb_engine_flush(struct radeonfb_softc *sc) 3638 { 3639 int i = 0; 3640 3641 if (IS_R300(sc) || IS_AVIVO(sc)) { 3642 SET32(sc, R300_DSTCACHE_CTLSTAT, R300_RB2D_DC_FLUSH_ALL); 3643 while (GET32(sc, R300_DSTCACHE_CTLSTAT) & R300_RB2D_DC_BUSY) { 3644 i++; 3645 } 3646 } else { 3647 SET32(sc, RADEON_RB2D_DSTCACHE_CTLSTAT, 3648 RADEON_RB2D_DC_FLUSH_ALL); 3649 while (GET32(sc, RADEON_RB2D_DSTCACHE_CTLSTAT) & 3650 RADEON_RB2D_DC_BUSY) { 3651 i++; 3652 } 3653 } 3654 #ifdef DIAGNOSTIC 3655 if (i > RADEON_TIMEOUT) 3656 printf("%s: engine flush timed out!\n", XNAME(sc)); 3657 #endif 3658 } 3659 3660 static inline void 3661 radeonfb_unclip(struct radeonfb_softc *sc) 3662 { 3663 3664 radeonfb_wait_fifo(sc, 2); 3665 PUT32(sc, RADEON_SC_TOP_LEFT, 0); 3666 PUT32(sc, RADEON_SC_BOTTOM_RIGHT, 0x1fff1fff); 3667 } 3668 3669 static void 3670 radeonfb_engine_init(struct radeonfb_display *dp) 3671 { 3672 struct radeonfb_softc *sc = dp->rd_softc; 3673 uint32_t pitch; 3674 3675 /* no 3D */ 3676 PUT32(sc, RADEON_RB3D_CNTL, 0); 3677 3678 if (IS_AVIVO(sc)) { 3679 3680 #if 0 3681 /* XXX the xf86-video-radeon does this, causes lockups here */ 3682 psel = GET32(sc, R400_GB_PIPE_SELECT); 3683 PRINTREG(R400_GB_PIPE_SELECT); 3684 DPRINTF(("PLL %08x %08x\n", GETPLL(sc, R500_DYN_SCLK_PWMEM_PIPE), 3685 (1 | ((psel >> 8) & 0xf) << 4))); 3686 PUTPLL(sc, R500_DYN_SCLK_PWMEM_PIPE, (1 | ((psel >> 8) & 0xf) << 4)); 3687 #endif 3688 SET32(sc, RADEON_WAIT_UNTIL, RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN); 3689 SET32(sc, R300_DST_PIPE_CONFIG, R300_PIPE_AUTO_CONFIG); 3690 SET32(sc, R300_RB2D_DSTCACHE_MODE, R300_DC_AUTOFLUSH_ENABLE | 3691 R300_DC_DC_DISABLE_IGNORE_PE); 3692 } 3693 3694 PRINTREG(RADEON_RB3D_CNTL); 3695 PRINTREG(RADEON_DP_GUI_MASTER_CNTL); 3696 PRINTREG(RADEON_RBBM_STATUS); 3697 3698 radeonfb_engine_reset(sc); 3699 PRINTREG(RADEON_RBBM_STATUS); 3700 3701 /* 3702 * Apple OF hands us some radeons with tiling enabled - explicitly 3703 * disable it here 3704 */ 3705 PUT32(sc, RADEON_SURFACE_CNTL, RADEON_SURF_TRANSLATION_DIS); 3706 3707 radeonfb_wait_fifo(sc, 1); 3708 if (!IS_R300(sc) && !IS_AVIVO(sc)) 3709 PUT32(sc, RADEON_RB2D_DSTCACHE_MODE, 0); 3710 3711 radeonfb_wait_fifo(sc, 3); 3712 3713 /* 3714 * XXX 3715 * I strongly suspect this works mostly by accident on !AVIVO 3716 * AVIVO uses all 22 bits for the framebuffer offset, so it can 3717 * address up to 4GB. Older chips probably use bits 20-22 for other 3718 * things and we just so happen to set the right ones by having our 3719 * PCI/AGP space above 0x80000000. 3720 * Either way, r5xx does not work if we set these bits, while older 3721 * chips don't work without. 3722 */ 3723 pitch = (dp->rd_stride + 0x3f) >> 6; 3724 if (IS_AVIVO(sc)) { 3725 pitch = pitch << 22; 3726 } else 3727 pitch = (pitch << 22) | (sc->sc_aperbase >> 10); 3728 3729 PUT32(sc, RADEON_DEFAULT_PITCH_OFFSET, pitch); 3730 PUT32(sc, RADEON_DST_PITCH_OFFSET, pitch); 3731 PUT32(sc, RADEON_SRC_PITCH_OFFSET, pitch); 3732 3733 (void)GET32(sc, RADEON_DP_DATATYPE); 3734 3735 /* default scissors -- no clipping */ 3736 radeonfb_wait_fifo(sc, 1); 3737 PUT32(sc, RADEON_DEFAULT_SC_BOTTOM_RIGHT, 3738 RADEON_DEFAULT_SC_RIGHT_MAX | RADEON_DEFAULT_SC_BOTTOM_MAX); 3739 3740 radeonfb_wait_fifo(sc, 1); 3741 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 3742 (dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT) | 3743 RADEON_GMC_CLR_CMP_CNTL_DIS | 3744 RADEON_GMC_BRUSH_SOLID_COLOR | 3745 RADEON_GMC_SRC_DATATYPE_COLOR); 3746 3747 radeonfb_wait_fifo(sc, 10); 3748 PUT32(sc, RADEON_DST_LINE_START, 0); 3749 PUT32(sc, RADEON_DST_LINE_END, 0); 3750 PUT32(sc, RADEON_DP_BRUSH_FRGD_CLR, 0xffffffff); 3751 PUT32(sc, RADEON_DP_BRUSH_BKGD_CLR, 0); 3752 PUT32(sc, RADEON_DP_SRC_FRGD_CLR, 0xffffffff); 3753 PUT32(sc, RADEON_DP_SRC_BKGD_CLR, 0); 3754 PUT32(sc, RADEON_DP_WRITE_MASK, 0xffffffff); 3755 PUT32(sc, RADEON_SC_TOP_LEFT, 0); 3756 PUT32(sc, RADEON_SC_BOTTOM_RIGHT, 0x1fff1fff); 3757 PUT32(sc, RADEON_AUX_SC_CNTL, 0); 3758 radeonfb_engine_idle(sc); 3759 } 3760 3761 static void 3762 radeonfb_engine_reset(struct radeonfb_softc *sc) 3763 { 3764 uint32_t hpc, rbbm, mclkcntl, clkindex; 3765 3766 radeonfb_engine_flush(sc); 3767 3768 clkindex = GET32(sc, RADEON_CLOCK_CNTL_INDEX); 3769 if (HAS_R300CG(sc)) 3770 radeonfb_r300cg_workaround(sc); 3771 mclkcntl = GETPLL(sc, RADEON_MCLK_CNTL); 3772 3773 /* 3774 * According to comments in XFree code, resetting the HDP via 3775 * the RBBM_SOFT_RESET can cause bad behavior on some systems. 3776 * So we use HOST_PATH_CNTL instead. 3777 */ 3778 3779 hpc = GET32(sc, RADEON_HOST_PATH_CNTL); 3780 rbbm = GET32(sc, RADEON_RBBM_SOFT_RESET); 3781 if (IS_R300(sc) || IS_AVIVO(sc)) { 3782 PUT32(sc, RADEON_RBBM_SOFT_RESET, rbbm | 3783 RADEON_SOFT_RESET_CP | 3784 RADEON_SOFT_RESET_HI | 3785 RADEON_SOFT_RESET_E2); 3786 GET32(sc, RADEON_RBBM_SOFT_RESET); 3787 PUT32(sc, RADEON_RBBM_SOFT_RESET, 0); 3788 /* 3789 * XXX: this bit is not defined in any ATI docs I have, 3790 * nor in the XFree code, but XFree does it. Why? 3791 */ 3792 SET32(sc, RADEON_RB2D_DSTCACHE_MODE, R300_DC_DC_DISABLE_IGNORE_PE); 3793 } else { 3794 PUT32(sc, RADEON_RBBM_SOFT_RESET, rbbm | 3795 RADEON_SOFT_RESET_CP | 3796 RADEON_SOFT_RESET_SE | 3797 RADEON_SOFT_RESET_RE | 3798 RADEON_SOFT_RESET_PP | 3799 RADEON_SOFT_RESET_E2 | 3800 RADEON_SOFT_RESET_RB); 3801 GET32(sc, RADEON_RBBM_SOFT_RESET); 3802 PUT32(sc, RADEON_RBBM_SOFT_RESET, rbbm & 3803 ~(RADEON_SOFT_RESET_CP | 3804 RADEON_SOFT_RESET_SE | 3805 RADEON_SOFT_RESET_RE | 3806 RADEON_SOFT_RESET_PP | 3807 RADEON_SOFT_RESET_E2 | 3808 RADEON_SOFT_RESET_RB)); 3809 GET32(sc, RADEON_RBBM_SOFT_RESET); 3810 } 3811 3812 PUT32(sc, RADEON_HOST_PATH_CNTL, hpc | RADEON_HDP_SOFT_RESET); 3813 GET32(sc, RADEON_HOST_PATH_CNTL); 3814 PUT32(sc, RADEON_HOST_PATH_CNTL, hpc); 3815 3816 if (!IS_R300(sc) && !IS_AVIVO(sc)) 3817 PUT32(sc, RADEON_RBBM_SOFT_RESET, rbbm); 3818 3819 PUT32(sc, RADEON_CLOCK_CNTL_INDEX, clkindex); 3820 PRINTREG(RADEON_CLOCK_CNTL_INDEX); 3821 PUTPLL(sc, RADEON_MCLK_CNTL, mclkcntl); 3822 3823 if (HAS_R300CG(sc)) 3824 radeonfb_r300cg_workaround(sc); 3825 } 3826 3827 static int 3828 radeonfb_set_curpos(struct radeonfb_display *dp, struct wsdisplay_curpos *pos) 3829 { 3830 int x, y; 3831 3832 x = pos->x; 3833 y = pos->y; 3834 3835 /* 3836 * This doesn't let a cursor move off the screen. I'm not 3837 * sure if this will have negative effects for e.g. Xinerama. 3838 * I'd guess Xinerama handles it by changing the cursor shape, 3839 * but that needs verification. 3840 */ 3841 if (x >= dp->rd_virtx) 3842 x = dp->rd_virtx - 1; 3843 if (x < 0) 3844 x = 0; 3845 if (y >= dp->rd_virty) 3846 y = dp->rd_virty - 1; 3847 if (y < 0) 3848 y = 0; 3849 3850 dp->rd_cursor.rc_pos.x = x; 3851 dp->rd_cursor.rc_pos.y = y; 3852 3853 radeonfb_cursor_position(dp); 3854 return 0; 3855 } 3856 3857 static int 3858 radeonfb_set_cursor(struct radeonfb_display *dp, struct wsdisplay_cursor *wc) 3859 { 3860 unsigned flags; 3861 3862 uint8_t r[2], g[2], b[2]; 3863 unsigned index, count; 3864 int i, err; 3865 int pitch, size; 3866 struct radeonfb_cursor *nc = &dp->rd_tempcursor; 3867 3868 flags = wc->which; 3869 3870 /* copy old values */ 3871 memcpy(nc, &dp->rd_cursor, sizeof(struct radeonfb_cursor)); 3872 3873 if (flags & WSDISPLAY_CURSOR_DOCMAP) { 3874 index = wc->cmap.index; 3875 count = wc->cmap.count; 3876 3877 if (index >= 2 || count > 2 - index) 3878 return EINVAL; 3879 3880 err = copyin(wc->cmap.red, &r[index], count); 3881 if (err) 3882 return err; 3883 err = copyin(wc->cmap.green, &g[index], count); 3884 if (err) 3885 return err; 3886 err = copyin(wc->cmap.blue, &b[index], count); 3887 if (err) 3888 return err; 3889 3890 for (i = index; i < index + count; i++) { 3891 nc->rc_cmap[i] = 3892 (r[i] << 16) + (g[i] << 8) + (b[i] << 0); 3893 } 3894 } 3895 3896 if (flags & WSDISPLAY_CURSOR_DOSHAPE) { 3897 if ((wc->size.x > RADEON_CURSORMAXX) || 3898 (wc->size.y > RADEON_CURSORMAXY)) 3899 return EINVAL; 3900 3901 /* figure bytes per line */ 3902 pitch = (wc->size.x + 7) / 8; 3903 size = pitch * wc->size.y; 3904 3905 /* clear the old cursor and mask */ 3906 memset(nc->rc_image, 0, 512); 3907 memset(nc->rc_mask, 0, 512); 3908 3909 nc->rc_size = wc->size; 3910 3911 if ((err = copyin(wc->image, nc->rc_image, size)) != 0) 3912 return err; 3913 3914 if ((err = copyin(wc->mask, nc->rc_mask, size)) != 0) 3915 return err; 3916 } 3917 3918 if (flags & WSDISPLAY_CURSOR_DOHOT) { 3919 nc->rc_hot = wc->hot; 3920 if (nc->rc_hot.x >= nc->rc_size.x) 3921 nc->rc_hot.x = nc->rc_size.x - 1; 3922 if (nc->rc_hot.y >= nc->rc_size.y) 3923 nc->rc_hot.y = nc->rc_size.y - 1; 3924 } 3925 3926 if (flags & WSDISPLAY_CURSOR_DOPOS) { 3927 nc->rc_pos = wc->pos; 3928 if (nc->rc_pos.x >= dp->rd_virtx) 3929 nc->rc_pos.x = dp->rd_virtx - 1; 3930 #if 0 3931 if (nc->rc_pos.x < 0) 3932 nc->rc_pos.x = 0; 3933 #endif 3934 if (nc->rc_pos.y >= dp->rd_virty) 3935 nc->rc_pos.y = dp->rd_virty - 1; 3936 #if 0 3937 if (nc->rc_pos.y < 0) 3938 nc->rc_pos.y = 0; 3939 #endif 3940 } 3941 if (flags & WSDISPLAY_CURSOR_DOCUR) { 3942 nc->rc_visible = wc->enable; 3943 } 3944 3945 memcpy(&dp->rd_cursor, nc, sizeof(struct radeonfb_cursor)); 3946 radeonfb_cursor_update(dp, wc->which); 3947 3948 return 0; 3949 } 3950 3951 static uint8_t 3952 radeonfb_backwards(uint8_t d) 3953 { 3954 uint8_t l; 3955 3956 l = d << 7; 3957 l |= ((d & 0x02) << 5); 3958 l |= ((d & 0x04) << 3); 3959 l |= ((d & 0x08) << 1); 3960 l |= ((d & 0x10) >> 1); 3961 l |= ((d & 0x20) >> 3); 3962 l |= ((d & 0x40) >> 5); 3963 l |= ((d & 0x80) >> 7); 3964 return l; 3965 } 3966 3967 /* 3968 * Change the cursor shape. Call this with the cursor locked to avoid 3969 * flickering/tearing. 3970 */ 3971 static void 3972 radeonfb_cursor_shape(struct radeonfb_display *dp) 3973 { 3974 uint8_t and[512], xor[512]; 3975 int i, j, src, dst /* , pitch */; 3976 const uint8_t *msk = dp->rd_cursor.rc_mask; 3977 const uint8_t *img = dp->rd_cursor.rc_image; 3978 3979 /* 3980 * Radeon cursor data interleaves one line of AND data followed 3981 * by a line of XOR data. (Each line corresponds to a whole hardware 3982 * pitch - i.e. 64 pixels or 8 bytes.) 3983 * 3984 * The cursor is displayed using the following table: 3985 * 3986 * AND XOR Result 3987 * ---------------------- 3988 * 0 0 Cursor color 0 3989 * 0 1 Cursor color 1 3990 * 1 0 Transparent 3991 * 1 1 Complement of background 3992 * 3993 * Our masks are therefore different from what we were passed. 3994 * Passed in, I'm assuming the data represents either color 0 or 1, 3995 * and a mask, so the passed in table looks like: 3996 * 3997 * IMG Mask Result 3998 * ----------------------- 3999 * 0 0 Transparent 4000 * 0 1 Cursor color 0 4001 * 1 0 Transparent 4002 * 1 1 Cursor color 1 4003 * 4004 * IF mask bit == 1, AND = 0, XOR = color. 4005 * IF mask bit == 0, AND = 1, XOR = 0. 4006 * 4007 * hence: AND = ~(mask); XOR = color & ~(mask); 4008 */ 4009 4010 /* pitch = ((dp->rd_cursor.rc_size.x + 7) / 8); */ 4011 4012 /* start by assuming all bits are transparent */ 4013 memset(and, 0xff, 512); 4014 memset(xor, 0x00, 512); 4015 4016 src = 0; 4017 dst = 0; 4018 for (i = 0; i < 64; i++) { 4019 for (j = 0; j < 64; j += 8) { 4020 if ((i < dp->rd_cursor.rc_size.y) && 4021 (j < dp->rd_cursor.rc_size.x)) { 4022 4023 /* take care to leave odd bits alone */ 4024 and[dst] &= ~(msk[src]); 4025 xor[dst] = img[src] & msk[src]; 4026 src++; 4027 } 4028 dst++; 4029 } 4030 } 4031 4032 for (i = 0; i < 512; i++) { 4033 and[i] = radeonfb_backwards(and[i]); 4034 xor[i] = radeonfb_backwards(xor[i]); 4035 } 4036 4037 /* copy the image into place */ 4038 for (i = 0; i < 64; i++) { 4039 memcpy((uint8_t *)dp->rd_curptr + (i * 16), 4040 &and[i * 8], 8); 4041 memcpy((uint8_t *)dp->rd_curptr + (i * 16) + 8, 4042 &xor[i * 8], 8); 4043 } 4044 } 4045 4046 /* 4047 * We use the cursor in 24bit mode on avivo, much simpler than the above. 4048 * Should probably do the same on older radeons 4049 */ 4050 static void 4051 radeonfb_avivo_cursor_shape(struct radeonfb_display *dp) 4052 { 4053 const uint8_t *msk = dp->rd_cursor.rc_mask; 4054 const uint8_t *img = dp->rd_cursor.rc_image; 4055 uint32_t *out = (uint32_t *)dp->rd_curptr; 4056 uint8_t bit; 4057 int i, j, px; 4058 4059 for (i = 0; i < 64 * 8; i++) { 4060 bit = 0x01; 4061 for (j = 0; j < 8; j++) { 4062 px = ((*msk & bit) ? 2 : 0) | ((*img & bit) ? 1 : 0); 4063 switch (px) { 4064 case 0: 4065 case 1: 4066 *out = htole32(0x00000000); 4067 break; 4068 case 2: 4069 *out = htole32(0xff000000 | 4070 dp->rd_cursor.rc_cmap[0]); 4071 break; 4072 case 3: 4073 *out = htole32(0xff000000 | 4074 dp->rd_cursor.rc_cmap[1]); 4075 break; 4076 } 4077 out++; 4078 bit = bit << 1; 4079 } 4080 msk++; 4081 img++; 4082 } 4083 } 4084 4085 static void 4086 radeonfb_cursor_position(struct radeonfb_display *dp) 4087 { 4088 struct radeonfb_softc *sc = dp->rd_softc; 4089 uint32_t offset, hvoff, hvpos; /* registers */ 4090 uint32_t coff; /* cursor offset */ 4091 int i, x, y, xoff, yoff, crtcoff, lock; 4092 4093 /* 4094 * XXX: this also needs to handle pan/scan 4095 */ 4096 for (i = 0; i < dp->rd_ncrtcs; i++) { 4097 4098 struct radeonfb_crtc *rcp = &dp->rd_crtcs[i]; 4099 4100 SET32(sc, AVIVO_D1CUR_UPDATE, AVIVO_D1CURSOR_UPDATE_LOCK); 4101 PUT32(sc, AVIVO_D1CUR_SIZE, 0x003f003f); 4102 if (IS_AVIVO(sc)) { 4103 if (rcp->rc_number) { 4104 offset = AVIVO_D2CUR_SURFACE_ADDRESS; 4105 hvoff = AVIVO_D2CUR_HOT_SPOT; 4106 hvpos = AVIVO_D2CUR_POSITION; 4107 crtcoff = 0/*RADEON_CRTC_OFFSET*/; 4108 } else { 4109 offset = AVIVO_D1CUR_SURFACE_ADDRESS; 4110 hvoff = AVIVO_D1CUR_HOT_SPOT; 4111 hvpos = AVIVO_D1CUR_POSITION; 4112 crtcoff = 0/*RADEON_CRTC_OFFSET*/; 4113 } 4114 lock = 0; 4115 } else { 4116 if (rcp->rc_number) { 4117 offset = RADEON_CUR2_OFFSET; 4118 hvoff = RADEON_CUR2_HORZ_VERT_OFF; 4119 hvpos = RADEON_CUR2_HORZ_VERT_POSN; 4120 crtcoff = RADEON_CRTC2_OFFSET; 4121 } else { 4122 offset = RADEON_CUR_OFFSET; 4123 hvoff = RADEON_CUR_HORZ_VERT_OFF; 4124 hvpos = RADEON_CUR_HORZ_VERT_POSN; 4125 crtcoff = RADEON_CRTC_OFFSET; 4126 } 4127 lock = RADEON_CUR_LOCK; 4128 } 4129 4130 x = dp->rd_cursor.rc_pos.x; 4131 y = dp->rd_cursor.rc_pos.y; 4132 4133 while (y < rcp->rc_yoffset) { 4134 rcp->rc_yoffset -= RADEON_PANINCREMENT; 4135 } 4136 while (y >= (rcp->rc_yoffset + rcp->rc_videomode.vdisplay)) { 4137 rcp->rc_yoffset += RADEON_PANINCREMENT; 4138 } 4139 while (x < rcp->rc_xoffset) { 4140 rcp->rc_xoffset -= RADEON_PANINCREMENT; 4141 } 4142 while (x >= (rcp->rc_xoffset + rcp->rc_videomode.hdisplay)) { 4143 rcp->rc_xoffset += RADEON_PANINCREMENT; 4144 } 4145 4146 /* adjust for the cursor's hotspot */ 4147 x -= dp->rd_cursor.rc_hot.x; 4148 y -= dp->rd_cursor.rc_hot.y; 4149 xoff = yoff = 0; 4150 4151 if (x >= dp->rd_virtx) 4152 x = dp->rd_virtx - 1; 4153 if (y >= dp->rd_virty) 4154 y = dp->rd_virty - 1; 4155 4156 /* now adjust cursor so it is relative to viewport */ 4157 x -= rcp->rc_xoffset; 4158 y -= rcp->rc_yoffset; 4159 4160 /* 4161 * no need to check for fall off, because we should 4162 * never move off the screen entirely! 4163 */ 4164 coff = 0; 4165 if (x < 0) { 4166 xoff = -x; 4167 x = 0; 4168 } 4169 if (y < 0) { 4170 yoff = -y; 4171 y = 0; 4172 coff = (yoff * 2) * 8; 4173 } 4174 4175 /* pan the display */ 4176 if (crtcoff != 0) 4177 PUT32(sc, crtcoff, (rcp->rc_yoffset * dp->rd_stride) + 4178 rcp->rc_xoffset); 4179 4180 PUT32(sc, offset, (dp->rd_curoff + coff) | lock); 4181 PUT32(sc, hvoff, (xoff << 16) | (yoff) | lock); 4182 /* NB: this unlocks the cursor */ 4183 PUT32(sc, hvpos, (x << 16) | y); 4184 if (IS_AVIVO(sc)) 4185 CLR32(sc, AVIVO_D1CUR_UPDATE, AVIVO_D1CURSOR_UPDATE_LOCK); 4186 } 4187 } 4188 4189 static void 4190 radeonfb_cursor_visible(struct radeonfb_display *dp) 4191 { 4192 struct radeonfb_softc *sc = dp->rd_softc; 4193 int i; 4194 uint32_t gencntl, bit; 4195 4196 for (i = 0; i < dp->rd_ncrtcs; i++) { 4197 if (IS_AVIVO(sc)) { 4198 SET32(sc, AVIVO_D1CUR_UPDATE, AVIVO_D1CURSOR_UPDATE_LOCK); 4199 if (dp->rd_crtcs[i].rc_number) { 4200 gencntl = AVIVO_D2CUR_CONTROL; 4201 bit = AVIVO_D1CURSOR_EN | (2 << 8); 4202 } else { 4203 gencntl = AVIVO_D1CUR_CONTROL; 4204 bit = AVIVO_D1CURSOR_EN | (2 << 8); 4205 } 4206 } else { 4207 if (dp->rd_crtcs[i].rc_number) { 4208 gencntl = RADEON_CRTC2_GEN_CNTL; 4209 bit = RADEON_CRTC2_CUR_EN; 4210 } else { 4211 gencntl = RADEON_CRTC_GEN_CNTL; 4212 bit = RADEON_CRTC_CUR_EN; 4213 } 4214 } 4215 if (dp->rd_cursor.rc_visible) 4216 SET32(dp->rd_softc, gencntl, bit); 4217 else 4218 CLR32(dp->rd_softc, gencntl, bit); 4219 if (IS_AVIVO(sc)) 4220 CLR32(sc, AVIVO_D1CUR_UPDATE, AVIVO_D1CURSOR_UPDATE_LOCK); 4221 4222 } 4223 } 4224 4225 static void 4226 radeonfb_cursor_cmap(struct radeonfb_display *dp) 4227 { 4228 int i; 4229 uint32_t c0reg, c1reg; 4230 struct radeonfb_softc *sc = dp->rd_softc; 4231 4232 for (i = 0; i < dp->rd_ncrtcs; i++) { 4233 if (dp->rd_crtcs[i].rc_number) { 4234 c0reg = RADEON_CUR2_CLR0; 4235 c1reg = RADEON_CUR2_CLR1; 4236 } else { 4237 c0reg = RADEON_CUR_CLR0; 4238 c1reg = RADEON_CUR_CLR1; 4239 } 4240 4241 PUT32(sc, c0reg, dp->rd_cursor.rc_cmap[0]); 4242 PUT32(sc, c1reg, dp->rd_cursor.rc_cmap[1]); 4243 } 4244 } 4245 4246 static void 4247 radeonfb_cursor_update(struct radeonfb_display *dp, unsigned which) 4248 { 4249 struct radeonfb_softc *sc; 4250 int i; 4251 4252 sc = dp->rd_softc; 4253 4254 for (i = 0; i < dp->rd_ncrtcs; i++) { 4255 if (dp->rd_crtcs[i].rc_number) { 4256 if (IS_AVIVO(sc)) { 4257 SET32(sc, AVIVO_D2CUR_UPDATE, AVIVO_D1CURSOR_UPDATE_LOCK); 4258 } else 4259 SET32(sc, RADEON_CUR2_OFFSET, RADEON_CUR_LOCK); 4260 } else { 4261 if (IS_AVIVO(sc)) { 4262 SET32(sc, AVIVO_D1CUR_UPDATE, AVIVO_D1CURSOR_UPDATE_LOCK); 4263 } else 4264 SET32(sc, RADEON_CUR_OFFSET,RADEON_CUR_LOCK); 4265 } 4266 } 4267 4268 if (which & WSDISPLAY_CURSOR_DOCMAP) { 4269 if (IS_AVIVO(sc)) { 4270 /* 4271 * we use an ARGB cursor here, so we need to rebuild 4272 * the cursor image every time the palette changes 4273 */ 4274 radeonfb_avivo_cursor_shape(dp); 4275 } else 4276 radeonfb_cursor_cmap(dp); 4277 } 4278 4279 if (which & WSDISPLAY_CURSOR_DOSHAPE) { 4280 if (IS_AVIVO(sc)) { 4281 radeonfb_avivo_cursor_shape(dp); 4282 } else 4283 radeonfb_cursor_shape(dp); 4284 } 4285 4286 if (which & WSDISPLAY_CURSOR_DOCUR) 4287 radeonfb_cursor_visible(dp); 4288 4289 /* this one is unconditional, because it updates other stuff */ 4290 radeonfb_cursor_position(dp); 4291 } 4292 4293 static struct videomode * 4294 radeonfb_best_refresh(struct videomode *m1, struct videomode *m2) 4295 { 4296 int r1, r2; 4297 4298 /* otherwise pick the higher refresh rate */ 4299 r1 = DIVIDE(DIVIDE(m1->dot_clock, m1->htotal), m1->vtotal); 4300 r2 = DIVIDE(DIVIDE(m2->dot_clock, m2->htotal), m2->vtotal); 4301 4302 return (r1 < r2 ? m2 : m1); 4303 } 4304 4305 static const struct videomode * 4306 radeonfb_port_mode(struct radeonfb_softc *sc, struct radeonfb_port *rp, 4307 int x, int y) 4308 { 4309 struct edid_info *ep = &rp->rp_edid; 4310 struct videomode *vmp = NULL; 4311 int i; 4312 4313 if (!rp->rp_edid_valid) { 4314 /* fallback to safe mode */ 4315 return radeonfb_modelookup(sc->sc_defaultmode); 4316 } 4317 4318 /* always choose the preferred mode first! */ 4319 if (ep->edid_preferred_mode) { 4320 4321 /* XXX: add auto-stretching support for native mode */ 4322 4323 /* this may want panning to occur, btw */ 4324 if ((ep->edid_preferred_mode->hdisplay <= x) && 4325 (ep->edid_preferred_mode->vdisplay <= y)) 4326 return ep->edid_preferred_mode; 4327 } 4328 4329 for (i = 0; i < ep->edid_nmodes; i++) { 4330 /* 4331 * We elect to pick a resolution that is too large for 4332 * the monitor than one that is too small. This means 4333 * that we will prefer to pan rather than to try to 4334 * center a smaller display on a larger screen. In 4335 * practice, this shouldn't matter because if a 4336 * monitor can support a larger resolution, it can 4337 * probably also support the smaller. A specific 4338 * exception is fixed format panels, but hopefully 4339 * they are properly dealt with by the "autostretch" 4340 * logic above. 4341 */ 4342 if ((ep->edid_modes[i].hdisplay > x) || 4343 (ep->edid_modes[i].vdisplay > y)) { 4344 continue; 4345 } 4346 4347 /* 4348 * at this point, the display mode is no larger than 4349 * what we've requested. 4350 */ 4351 if (vmp == NULL) 4352 vmp = &ep->edid_modes[i]; 4353 4354 /* eliminate smaller modes */ 4355 if ((vmp->hdisplay >= ep->edid_modes[i].hdisplay) || 4356 (vmp->vdisplay >= ep->edid_modes[i].vdisplay)) 4357 continue; 4358 4359 if ((vmp->hdisplay < ep->edid_modes[i].hdisplay) || 4360 (vmp->vdisplay < ep->edid_modes[i].vdisplay)) { 4361 vmp = &ep->edid_modes[i]; 4362 continue; 4363 } 4364 4365 KASSERT(vmp->hdisplay == ep->edid_modes[i].hdisplay); 4366 KASSERT(vmp->vdisplay == ep->edid_modes[i].vdisplay); 4367 4368 vmp = radeonfb_best_refresh(vmp, &ep->edid_modes[i]); 4369 } 4370 4371 return (vmp ? vmp : radeonfb_modelookup(sc->sc_defaultmode)); 4372 } 4373 4374 static int 4375 radeonfb_hasres(struct videomode *list, int nlist, int x, int y) 4376 { 4377 int i; 4378 4379 for (i = 0; i < nlist; i++) { 4380 if ((x == list[i].hdisplay) && 4381 (y == list[i].vdisplay)) { 4382 return 1; 4383 } 4384 } 4385 return 0; 4386 } 4387 4388 static void 4389 radeonfb_pickres(struct radeonfb_display *dp, uint16_t *x, uint16_t *y, 4390 int pan) 4391 { 4392 struct radeonfb_port *rp; 4393 struct edid_info *ep; 4394 int i, j; 4395 4396 *x = 0; 4397 *y = 0; 4398 4399 if (pan) { 4400 for (i = 0; i < dp->rd_ncrtcs; i++) { 4401 rp = dp->rd_crtcs[i].rc_port; 4402 ep = &rp->rp_edid; 4403 if (!rp->rp_edid_valid) { 4404 /* monitor not present */ 4405 continue; 4406 } 4407 4408 /* 4409 * For now we are ignoring "conflict" that 4410 * could occur when mixing some modes like 4411 * 1280x1024 and 1400x800. It isn't clear 4412 * which is better, so the first one wins. 4413 */ 4414 for (j = 0; j < ep->edid_nmodes; j++) { 4415 /* 4416 * ignore resolutions that are too big for 4417 * the radeon 4418 */ 4419 if (ep->edid_modes[j].hdisplay > 4420 dp->rd_softc->sc_maxx) 4421 continue; 4422 if (ep->edid_modes[j].vdisplay > 4423 dp->rd_softc->sc_maxy) 4424 continue; 4425 4426 /* 4427 * pick largest resolution, the 4428 * smaller monitor will pan 4429 */ 4430 if ((ep->edid_modes[j].hdisplay >= *x) && 4431 (ep->edid_modes[j].vdisplay >= *y)) { 4432 *x = ep->edid_modes[j].hdisplay; 4433 *y = ep->edid_modes[j].vdisplay; 4434 } 4435 } 4436 } 4437 4438 } else { 4439 struct videomode *modes; 4440 size_t smodes; 4441 int nmodes = 0; 4442 int valid = 0; 4443 4444 smodes = sizeof(struct videomode) * 64; 4445 modes = kmem_alloc(smodes, KM_SLEEP); 4446 4447 for (i = 0; i < dp->rd_ncrtcs; i++) { 4448 /* 4449 * pick the largest resolution in common. 4450 */ 4451 rp = dp->rd_crtcs[i].rc_port; 4452 ep = &rp->rp_edid; 4453 4454 if (!rp->rp_edid_valid) 4455 continue; 4456 4457 if (!valid) { 4458 /* 4459 * Pick the preferred mode for this port 4460 * if available. 4461 */ 4462 if (ep->edid_preferred_mode) { 4463 struct videomode *vmp = 4464 ep->edid_preferred_mode; 4465 4466 if ((vmp->hdisplay <= 4467 dp->rd_softc->sc_maxx) && 4468 (vmp->vdisplay <= 4469 dp->rd_softc->sc_maxy)) 4470 modes[nmodes++] = *vmp; 4471 } else { 4472 4473 /* initialize starting list */ 4474 for (j = 0; j < ep->edid_nmodes; j++) { 4475 /* 4476 * ignore resolutions that are 4477 * too big for the radeon 4478 */ 4479 if (ep->edid_modes[j].hdisplay > 4480 dp->rd_softc->sc_maxx) 4481 continue; 4482 if (ep->edid_modes[j].vdisplay > 4483 dp->rd_softc->sc_maxy) 4484 continue; 4485 4486 modes[nmodes] = 4487 ep->edid_modes[j]; 4488 nmodes++; 4489 } 4490 } 4491 valid = 1; 4492 } else { 4493 /* merge into preexisting list */ 4494 for (j = 0; j < nmodes; j++) { 4495 if (!radeonfb_hasres(ep->edid_modes, 4496 ep->edid_nmodes, 4497 modes[j].hdisplay, 4498 modes[j].vdisplay)) { 4499 modes[j] = modes[nmodes]; 4500 j--; 4501 nmodes--; 4502 } 4503 } 4504 } 4505 } 4506 4507 /* now we have to pick from the merged list */ 4508 for (i = 0; i < nmodes; i++) { 4509 if ((modes[i].hdisplay >= *x) && 4510 (modes[i].vdisplay >= *y)) { 4511 *x = modes[i].hdisplay; 4512 *y = modes[i].vdisplay; 4513 } 4514 } 4515 kmem_free(modes, smodes); 4516 4517 } 4518 4519 if ((*x == 0) || (*y == 0)) { 4520 /* fallback to safe mode */ 4521 *x = 640; 4522 *y = 480; 4523 } 4524 } 4525 4526 /* 4527 * backlight levels are linear on: 4528 * - RV200, RV250, RV280, RV350 4529 * - but NOT on PowerBook4,3 6,3 6,5 4530 * according to Linux' radeonfb 4531 */ 4532 4533 /* Get the current backlight level for the display. */ 4534 4535 static int 4536 radeonfb_get_backlight(struct radeonfb_display *dp) 4537 { 4538 int s; 4539 uint32_t level; 4540 4541 s = spltty(); 4542 4543 level = radeonfb_get32(dp->rd_softc, RADEON_LVDS_GEN_CNTL); 4544 level &= RADEON_LVDS_BL_MOD_LEV_MASK; 4545 level >>= RADEON_LVDS_BL_MOD_LEV_SHIFT; 4546 4547 /* 4548 * On some chips, we should negate the backlight level. 4549 * XXX Find out on which chips. 4550 */ 4551 if (dp->rd_softc->sc_flags & RFB_INV_BLIGHT) 4552 level = RADEONFB_BACKLIGHT_MAX - level; 4553 4554 splx(s); 4555 4556 return level; 4557 } 4558 4559 /* Set the backlight to the given level for the display. */ 4560 static void 4561 radeonfb_switch_backlight(struct radeonfb_display *dp, int on) 4562 { 4563 if (dp->rd_bl_on == on) 4564 return; 4565 dp->rd_bl_on = on; 4566 radeonfb_set_backlight(dp, dp->rd_bl_level); 4567 } 4568 4569 static int 4570 radeonfb_set_backlight(struct radeonfb_display *dp, int level) 4571 { 4572 struct radeonfb_softc *sc = dp->rd_softc; 4573 int rlevel, s; 4574 uint32_t lvds; 4575 4576 if(!sc->sc_mapped) 4577 return 0; 4578 4579 s = spltty(); 4580 4581 dp->rd_bl_level = level; 4582 if (dp->rd_bl_on == 0) 4583 level = 0; 4584 4585 if (level < 0) 4586 level = 0; 4587 else if (level >= RADEONFB_BACKLIGHT_MAX) 4588 level = RADEONFB_BACKLIGHT_MAX; 4589 4590 /* On some chips, we should negate the backlight level. */ 4591 if (dp->rd_softc->sc_flags & RFB_INV_BLIGHT) { 4592 rlevel = RADEONFB_BACKLIGHT_MAX - level; 4593 } else 4594 rlevel = level; 4595 4596 callout_stop(&dp->rd_bl_lvds_co); 4597 //radeonfb_engine_idle(sc); 4598 4599 /* 4600 * Turn off the display if the backlight is set to 0, since the 4601 * display is useless without backlight anyway. 4602 */ 4603 if (level == 0) 4604 radeonfb_blank(dp, 1); 4605 else if (radeonfb_get_backlight(dp) == 0) 4606 radeonfb_blank(dp, 0); 4607 4608 lvds = radeonfb_get32(sc, RADEON_LVDS_GEN_CNTL); 4609 lvds &= ~RADEON_LVDS_DISPLAY_DIS; 4610 if (!(lvds & RADEON_LVDS_BLON) || !(lvds & RADEON_LVDS_ON)) { 4611 lvds |= dp->rd_bl_lvds_val & RADEON_LVDS_DIGON; 4612 lvds |= RADEON_LVDS_BLON | RADEON_LVDS_EN; 4613 radeonfb_put32(sc, RADEON_LVDS_GEN_CNTL, lvds); 4614 lvds &= ~RADEON_LVDS_BL_MOD_LEV_MASK; 4615 lvds |= rlevel << RADEON_LVDS_BL_MOD_LEV_SHIFT; 4616 lvds |= RADEON_LVDS_ON; 4617 lvds |= dp->rd_bl_lvds_val & RADEON_LVDS_BL_MOD_EN; 4618 } else { 4619 lvds &= ~RADEON_LVDS_BL_MOD_LEV_MASK; 4620 lvds |= rlevel << RADEON_LVDS_BL_MOD_LEV_SHIFT; 4621 radeonfb_put32(sc, RADEON_LVDS_GEN_CNTL, lvds); 4622 } 4623 4624 dp->rd_bl_lvds_val &= ~RADEON_LVDS_STATE_MASK; 4625 dp->rd_bl_lvds_val |= lvds & RADEON_LVDS_STATE_MASK; 4626 /* XXX What is the correct delay? */ 4627 callout_schedule(&dp->rd_bl_lvds_co, 200 * hz); 4628 4629 splx(s); 4630 4631 return 0; 4632 } 4633 4634 /* 4635 * Callout function for delayed operations on the LVDS_GEN_CNTL register. 4636 * Set the delayed bits in the register, and clear the stored delayed 4637 * value. 4638 */ 4639 4640 static void radeonfb_lvds_callout(void *arg) 4641 { 4642 struct radeonfb_display *dp = arg; 4643 int s; 4644 4645 s = splhigh(); 4646 4647 radeonfb_mask32(dp->rd_softc, RADEON_LVDS_GEN_CNTL, ~0, 4648 dp->rd_bl_lvds_val); 4649 dp->rd_bl_lvds_val = 0; 4650 4651 splx(s); 4652 } 4653 4654 static void 4655 radeonfb_brightness_up(device_t dev) 4656 { 4657 struct radeonfb_softc *sc = device_private(dev); 4658 struct radeonfb_display *dp = &sc->sc_displays[0]; 4659 int level; 4660 4661 /* we assume the main display is the first one - need a better way */ 4662 if (sc->sc_ndisplays < 1) return; 4663 /* make sure pushing the hotkeys always has an effect */ 4664 dp->rd_bl_on = 1; 4665 level = dp->rd_bl_level; 4666 level = uimin(RADEONFB_BACKLIGHT_MAX, level + 5); 4667 radeonfb_set_backlight(dp, level); 4668 } 4669 4670 static void 4671 radeonfb_brightness_down(device_t dev) 4672 { 4673 struct radeonfb_softc *sc = device_private(dev); 4674 struct radeonfb_display *dp = &sc->sc_displays[0]; 4675 int level; 4676 4677 /* we assume the main display is the first one - need a better way */ 4678 if (sc->sc_ndisplays < 1) return; 4679 /* make sure pushing the hotkeys always has an effect */ 4680 dp->rd_bl_on = 1; 4681 level = dp->rd_bl_level; 4682 level = uimax(0, level - 5); 4683 radeonfb_set_backlight(dp, level); 4684 } 4685
Indexes created Thu Sep 25 16:09:42 GMT 2025