radeonfb.c revision 1.15
1 /* $NetBSD: radeonfb.c,v 1.15 2007/07/09 21:00:57 ad Exp $ */ 2 3 /*- 4 * Copyright (c) 2006 Itronix Inc. 5 * All rights reserved. 6 * 7 * Written by Garrett D'Amore for Itronix Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. The name of Itronix Inc. may not be used to endorse 18 * or promote products derived from this software without specific 19 * prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY ITRONIX INC. ``AS IS'' AND ANY EXPRESS 22 * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 23 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL ITRONIX INC. BE LIABLE FOR ANY 25 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE 27 * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 29 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 30 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 31 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * ATI Technologies Inc. ("ATI") has not assisted in the creation of, and 36 * does not endorse, this software. ATI will not be responsible or liable 37 * for any actual or alleged damage or loss caused by or in connection with 38 * the use of or reliance on this software. 39 */ 40 41 /* 42 * Portions of this code were taken from XFree86's Radeon driver, which bears 43 * this notice: 44 * 45 * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and 46 * VA Linux Systems Inc., Fremont, California. 47 * 48 * All Rights Reserved. 49 * 50 * Permission is hereby granted, free of charge, to any person obtaining 51 * a copy of this software and associated documentation files (the 52 * "Software"), to deal in the Software without restriction, including 53 * without limitation on the rights to use, copy, modify, merge, 54 * publish, distribute, sublicense, and/or sell copies of the Software, 55 * and to permit persons to whom the Software is furnished to do so, 56 * subject to the following conditions: 57 * 58 * The above copyright notice and this permission notice (including the 59 * next paragraph) shall be included in all copies or substantial 60 * portions of the Software. 61 * 62 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 63 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 64 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 65 * NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR 66 * THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 67 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 68 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 69 * DEALINGS IN THE SOFTWARE. 70 */ 71 72 #include <sys/cdefs.h> 73 __KERNEL_RCSID(0, "$NetBSD: radeonfb.c,v 1.15 2007/07/09 21:00:57 ad Exp $"); 74 75 #define RADEONFB_DEFAULT_DEPTH 32 76 77 #include <sys/param.h> 78 #include <sys/systm.h> 79 #include <sys/device.h> 80 #include <sys/malloc.h> 81 #include <machine/bus.h> 82 #include <sys/kernel.h> 83 #include <sys/lwp.h> 84 #include <sys/kauth.h> 85 86 #include <dev/wscons/wsdisplayvar.h> 87 #include <dev/wscons/wsconsio.h> 88 #include <dev/wsfont/wsfont.h> 89 #include <dev/rasops/rasops.h> 90 #include <dev/videomode/videomode.h> 91 #include <dev/videomode/edidvar.h> 92 #include <dev/wscons/wsdisplay_vconsvar.h> 93 94 #include <dev/pci/pcidevs.h> 95 #include <dev/pci/pcireg.h> 96 #include <dev/pci/pcivar.h> 97 #include <dev/pci/radeonfbreg.h> 98 #include <dev/pci/radeonfbvar.h> 99 #include "opt_radeonfb.h" 100 101 static int radeonfb_match(struct device *, struct cfdata *, void *); 102 static void radeonfb_attach(struct device *, struct device *, void *); 103 static int radeonfb_ioctl(void *, void *, unsigned long, void *, int, 104 struct lwp *); 105 static paddr_t radeonfb_mmap(void *, void *, off_t, int); 106 static int radeonfb_scratch_test(struct radeonfb_softc *, int, uint32_t); 107 static void radeonfb_loadbios(struct radeonfb_softc *, 108 struct pci_attach_args *); 109 110 static uintmax_t radeonfb_getprop_num(struct radeonfb_softc *, const char *, 111 uintmax_t); 112 static int radeonfb_getclocks(struct radeonfb_softc *); 113 static int radeonfb_gettmds(struct radeonfb_softc *); 114 static int radeonfb_calc_dividers(struct radeonfb_softc *, uint32_t, 115 uint32_t *, uint32_t *); 116 static int radeonfb_getconnectors(struct radeonfb_softc *); 117 static const struct videomode *radeonfb_modelookup(const char *); 118 static void radeonfb_init_screen(void *, struct vcons_screen *, int, long *); 119 static void radeonfb_pllwriteupdate(struct radeonfb_softc *, int); 120 static void radeonfb_pllwaitatomicread(struct radeonfb_softc *, int); 121 static void radeonfb_program_vclk(struct radeonfb_softc *, int, int); 122 static void radeonfb_modeswitch(struct radeonfb_display *); 123 static void radeonfb_setcrtc(struct radeonfb_display *, int); 124 static void radeonfb_init_misc(struct radeonfb_softc *); 125 static void radeonfb_set_fbloc(struct radeonfb_softc *); 126 static void radeonfb_init_palette(struct radeonfb_softc *, int); 127 static void radeonfb_r300cg_workaround(struct radeonfb_softc *); 128 129 static int radeonfb_isblank(struct radeonfb_display *); 130 static void radeonfb_blank(struct radeonfb_display *, int); 131 static int radeonfb_set_cursor(struct radeonfb_display *, 132 struct wsdisplay_cursor *); 133 static int radeonfb_set_curpos(struct radeonfb_display *, 134 struct wsdisplay_curpos *); 135 136 /* acceleration support */ 137 static void radeonfb_rectfill(struct radeonfb_display *, int dstx, int dsty, 138 int width, int height, uint32_t color); 139 static void radeonfb_bitblt(struct radeonfb_display *, int srcx, int srcy, 140 int dstx, int dsty, int width, int height, int rop, uint32_t mask); 141 static void radeonfb_feed_bytes(struct radeonfb_display *, int, uint8_t *); 142 static void radeonfb_setup_mono(struct radeonfb_display *, int, int, int, 143 int, uint32_t, uint32_t); 144 145 /* hw cursor support */ 146 static void radeonfb_cursor_cmap(struct radeonfb_display *); 147 static void radeonfb_cursor_shape(struct radeonfb_display *); 148 static void radeonfb_cursor_position(struct radeonfb_display *); 149 static void radeonfb_cursor_visible(struct radeonfb_display *); 150 static void radeonfb_cursor_update(struct radeonfb_display *, unsigned); 151 152 static void radeonfb_wait_fifo(struct radeonfb_softc *, int); 153 static void radeonfb_engine_idle(struct radeonfb_softc *); 154 static void radeonfb_engine_flush(struct radeonfb_softc *); 155 static void radeonfb_engine_reset(struct radeonfb_softc *); 156 static void radeonfb_engine_init(struct radeonfb_display *); 157 static inline void radeonfb_unclip(struct radeonfb_softc *); 158 159 static void radeonfb_eraserows(void *, int, int, long); 160 static void radeonfb_erasecols(void *, int, int, int, long); 161 static void radeonfb_copyrows(void *, int, int, int); 162 static void radeonfb_copycols(void *, int, int, int, int); 163 static void radeonfb_cursor(void *, int, int, int); 164 static void radeonfb_putchar(void *, int, int, unsigned, long); 165 static int radeonfb_allocattr(void *, int, int, int, long *); 166 167 static int radeonfb_get_backlight(struct radeonfb_display *); 168 static int radeonfb_set_backlight(struct radeonfb_display *, int); 169 static void radeonfb_lvds_callout(void *); 170 171 static struct videomode *radeonfb_best_refresh(struct videomode *, 172 struct videomode *); 173 static void radeonfb_pickres(struct radeonfb_display *, uint16_t *, 174 uint16_t *, int); 175 static const struct videomode *radeonfb_port_mode(struct radeonfb_softc *, 176 struct radeonfb_port *, int, int); 177 178 static int radeonfb_drm_print(void *, const char *); 179 180 #ifdef RADEON_DEBUG 181 int radeon_debug = 1; 182 #define DPRINTF(x) \ 183 if (radeon_debug) printf x 184 #define PRINTREG(r) DPRINTF((#r " = %08x\n", GET32(sc, r))) 185 #define PRINTPLL(r) DPRINTF((#r " = %08x\n", GETPLL(sc, r))) 186 #else 187 #define DPRINTF(x) 188 #define PRINTREG(r) 189 #define PRINTPLL(r) 190 #endif 191 192 #define ROUNDUP(x,y) (((x) + ((y) - 1)) & ~((y) - 1)) 193 194 #ifndef RADEON_DEFAULT_MODE 195 /* any reasonably modern display should handle this */ 196 #define RADEON_DEFAULT_MODE "1024x768x60" 197 //#define RADEON_DEFAULT_MODE "1280x1024x60" 198 #endif 199 200 const char *radeonfb_default_mode = RADEON_DEFAULT_MODE; 201 202 static struct { 203 int size; /* minimum memory size (MB) */ 204 int maxx; /* maximum x dimension */ 205 int maxy; /* maximum y dimension */ 206 int maxbpp; /* maximum bpp */ 207 int maxdisp; /* maximum logical display count */ 208 } radeonfb_limits[] = { 209 { 32, 2048, 1536, 32, 2 }, 210 { 16, 1600, 1200, 32, 2 }, 211 { 8, 1600, 1200, 32, 1 }, 212 { 0, 0, 0, 0, 0 }, 213 }; 214 215 static struct wsscreen_descr radeonfb_stdscreen = { 216 "fb", /* name */ 217 0, 0, /* ncols, nrows */ 218 NULL, /* textops */ 219 8, 16, /* fontwidth, fontheight */ 220 WSSCREEN_WSCOLORS, /* capabilities */ 221 0, /* modecookie */ 222 }; 223 224 struct wsdisplay_accessops radeonfb_accessops = { 225 radeonfb_ioctl, 226 radeonfb_mmap, 227 NULL, /* vcons_alloc_screen */ 228 NULL, /* vcons_free_screen */ 229 NULL, /* vcons_show_screen */ 230 NULL, /* load_font */ 231 NULL, /* pollc */ 232 NULL, /* scroll */ 233 }; 234 235 static struct { 236 uint16_t devid; 237 uint16_t family; 238 uint16_t flags; 239 } radeonfb_devices[] = 240 { 241 /* R100 family */ 242 { PCI_PRODUCT_ATI_RADEON_R100_QD, RADEON_R100, 0 }, 243 { PCI_PRODUCT_ATI_RADEON_R100_QE, RADEON_R100, 0 }, 244 { PCI_PRODUCT_ATI_RADEON_R100_QF, RADEON_R100, 0 }, 245 { PCI_PRODUCT_ATI_RADEON_R100_QG, RADEON_R100, 0 }, 246 247 /* RV100 family */ 248 { PCI_PRODUCT_ATI_RADEON_RV100_LY, RADEON_RV100, RFB_MOB }, 249 { PCI_PRODUCT_ATI_RADEON_RV100_LZ, RADEON_RV100, RFB_MOB }, 250 { PCI_PRODUCT_ATI_RADEON_RV100_QY, RADEON_RV100, 0 }, 251 { PCI_PRODUCT_ATI_RADEON_RV100_QZ, RADEON_RV100, 0 }, 252 253 /* RS100 family */ 254 { PCI_PRODUCT_ATI_RADEON_RS100_4136, RADEON_RS100, 0 }, 255 { PCI_PRODUCT_ATI_RADEON_RS100_4336, RADEON_RS100, RFB_MOB }, 256 257 /* RS200/RS250 family */ 258 { PCI_PRODUCT_ATI_RADEON_RS200_4337, RADEON_RS200, RFB_MOB }, 259 { PCI_PRODUCT_ATI_RADEON_RS200_A7, RADEON_RS200, 0 }, 260 { PCI_PRODUCT_ATI_RADEON_RS250_B7, RADEON_RS200, RFB_MOB }, 261 { PCI_PRODUCT_ATI_RADEON_RS250_D7, RADEON_RS200, 0 }, 262 263 /* R200 family */ 264 /* add more R200 products? , 5148 */ 265 { PCI_PRODUCT_ATI_RADEON_R200_BB, RADEON_R200, 0 }, 266 { PCI_PRODUCT_ATI_RADEON_R200_BC, RADEON_R200, 0 }, 267 { PCI_PRODUCT_ATI_RADEON_R200_QH, RADEON_R200, 0 }, 268 { PCI_PRODUCT_ATI_RADEON_R200_QL, RADEON_R200, 0 }, 269 { PCI_PRODUCT_ATI_RADEON_R200_QM, RADEON_R200, 0 }, 270 271 /* RV200 family */ 272 { PCI_PRODUCT_ATI_RADEON_RV200_LW, RADEON_RV200, RFB_MOB }, 273 { PCI_PRODUCT_ATI_RADEON_RV200_LX, RADEON_RV200, RFB_MOB }, 274 { PCI_PRODUCT_ATI_RADEON_RV200_QW, RADEON_RV200, 0 }, 275 { PCI_PRODUCT_ATI_RADEON_RV200_QX, RADEON_RV200, 0 }, 276 277 /* RV250 family */ 278 { PCI_PRODUCT_ATI_RADEON_RV250_4966, RADEON_RV250, 0 }, 279 { PCI_PRODUCT_ATI_RADEON_RV250_4967, RADEON_RV250, 0 }, 280 { PCI_PRODUCT_ATI_RADEON_RV250_4C64, RADEON_RV250, RFB_MOB }, 281 { PCI_PRODUCT_ATI_RADEON_RV250_4C66, RADEON_RV250, RFB_MOB }, 282 { PCI_PRODUCT_ATI_RADEON_RV250_4C67, RADEON_RV250, RFB_MOB }, 283 284 /* RS300 family */ 285 { PCI_PRODUCT_ATI_RADEON_RS300_X5, RADEON_RS300, 0 }, 286 { PCI_PRODUCT_ATI_RADEON_RS300_X4, RADEON_RS300, 0 }, 287 { PCI_PRODUCT_ATI_RADEON_RS300_7834, RADEON_RS300, 0 }, 288 { PCI_PRODUCT_ATI_RADEON_RS300_7835, RADEON_RS300, RFB_MOB }, 289 290 /* RV280 family */ 291 { PCI_PRODUCT_ATI_RADEON_RV280_5960, RADEON_RV280, 0 }, 292 { PCI_PRODUCT_ATI_RADEON_RV280_5961, RADEON_RV280, 0 }, 293 { PCI_PRODUCT_ATI_RADEON_RV280_5962, RADEON_RV280, 0 }, 294 { PCI_PRODUCT_ATI_RADEON_RV280_5963, RADEON_RV280, 0 }, 295 { PCI_PRODUCT_ATI_RADEON_RV280_5964, RADEON_RV280, 0 }, 296 { PCI_PRODUCT_ATI_RADEON_RV280_5C61, RADEON_RV280, RFB_MOB }, 297 { PCI_PRODUCT_ATI_RADEON_RV280_5C63, RADEON_RV280, RFB_MOB }, 298 299 /* R300 family */ 300 { PCI_PRODUCT_ATI_RADEON_R300_AD, RADEON_R300, 0 }, 301 { PCI_PRODUCT_ATI_RADEON_R300_AE, RADEON_R300, 0 }, 302 { PCI_PRODUCT_ATI_RADEON_R300_AF, RADEON_R300, 0 }, 303 { PCI_PRODUCT_ATI_RADEON_R300_AG, RADEON_R300, 0 }, 304 { PCI_PRODUCT_ATI_RADEON_R300_ND, RADEON_R300, 0 }, 305 { PCI_PRODUCT_ATI_RADEON_R300_NE, RADEON_R300, 0 }, 306 { PCI_PRODUCT_ATI_RADEON_R300_NF, RADEON_R300, 0 }, 307 { PCI_PRODUCT_ATI_RADEON_R300_NG, RADEON_R300, 0 }, 308 309 /* RV350/RV360 family */ 310 { PCI_PRODUCT_ATI_RADEON_RV350_AP, RADEON_RV350, 0 }, 311 { PCI_PRODUCT_ATI_RADEON_RV350_AQ, RADEON_RV350, 0 }, 312 { PCI_PRODUCT_ATI_RADEON_RV360_AR, RADEON_RV350, 0 }, 313 { PCI_PRODUCT_ATI_RADEON_RV350_AS, RADEON_RV350, 0 }, 314 { PCI_PRODUCT_ATI_RADEON_RV350_AT, RADEON_RV350, 0 }, 315 { PCI_PRODUCT_ATI_RADEON_RV350_AV, RADEON_RV350, 0 }, 316 { PCI_PRODUCT_ATI_RADEON_RV350_NP, RADEON_RV350, RFB_MOB }, 317 { PCI_PRODUCT_ATI_RADEON_RV350_NQ, RADEON_RV350, RFB_MOB }, 318 { PCI_PRODUCT_ATI_RADEON_RV350_NR, RADEON_RV350, RFB_MOB }, 319 { PCI_PRODUCT_ATI_RADEON_RV350_NS, RADEON_RV350, RFB_MOB }, 320 { PCI_PRODUCT_ATI_RADEON_RV350_NT, RADEON_RV350, RFB_MOB }, 321 { PCI_PRODUCT_ATI_RADEON_RV350_NV, RADEON_RV350, RFB_MOB }, 322 323 /* R350/R360 family */ 324 { PCI_PRODUCT_ATI_RADEON_R350_AH, RADEON_R350, 0 }, 325 { PCI_PRODUCT_ATI_RADEON_R350_AI, RADEON_R350, 0 }, 326 { PCI_PRODUCT_ATI_RADEON_R350_AJ, RADEON_R350, 0 }, 327 { PCI_PRODUCT_ATI_RADEON_R350_AK, RADEON_R350, 0 }, 328 { PCI_PRODUCT_ATI_RADEON_R350_NH, RADEON_R350, 0 }, 329 { PCI_PRODUCT_ATI_RADEON_R350_NI, RADEON_R350, 0 }, 330 { PCI_PRODUCT_ATI_RADEON_R350_NK, RADEON_R350, 0 }, 331 { PCI_PRODUCT_ATI_RADEON_R360_NJ, RADEON_R350, 0 }, 332 333 /* RV380/RV370 family */ 334 { PCI_PRODUCT_ATI_RADEON_RV380_3150, RADEON_RV380, RFB_MOB }, 335 { PCI_PRODUCT_ATI_RADEON_RV380_3154, RADEON_RV380, RFB_MOB }, 336 { PCI_PRODUCT_ATI_RADEON_RV380_3E50, RADEON_RV380, 0 }, 337 { PCI_PRODUCT_ATI_RADEON_RV380_3E54, RADEON_RV380, 0 }, 338 { PCI_PRODUCT_ATI_RADEON_RV370_5460, RADEON_RV380, RFB_MOB }, 339 { PCI_PRODUCT_ATI_RADEON_RV370_5464, RADEON_RV380, RFB_MOB }, 340 { PCI_PRODUCT_ATI_RADEON_RV370_5B60, RADEON_RV380, 0 }, 341 { PCI_PRODUCT_ATI_RADEON_RV370_5B64, RADEON_RV380, 0 }, 342 { PCI_PRODUCT_ATI_RADEON_RV370_5B65, RADEON_RV380, 0 }, 343 344 /* R420/R423 family */ 345 { PCI_PRODUCT_ATI_RADEON_R420_JH, RADEON_R420, 0 }, 346 { PCI_PRODUCT_ATI_RADEON_R420_JI, RADEON_R420, 0 }, 347 { PCI_PRODUCT_ATI_RADEON_R420_JJ, RADEON_R420, 0 }, 348 { PCI_PRODUCT_ATI_RADEON_R420_JK, RADEON_R420, 0 }, 349 { PCI_PRODUCT_ATI_RADEON_R420_JL, RADEON_R420, 0 }, 350 { PCI_PRODUCT_ATI_RADEON_R420_JM, RADEON_R420, 0 }, 351 { PCI_PRODUCT_ATI_RADEON_R420_JN, RADEON_R420, RFB_MOB }, 352 { PCI_PRODUCT_ATI_RADEON_R420_JP, RADEON_R420, 0 }, 353 { PCI_PRODUCT_ATI_RADEON_R423_UH, RADEON_R420, 0 }, 354 { PCI_PRODUCT_ATI_RADEON_R423_UI, RADEON_R420, 0 }, 355 { PCI_PRODUCT_ATI_RADEON_R423_UJ, RADEON_R420, 0 }, 356 { PCI_PRODUCT_ATI_RADEON_R423_UK, RADEON_R420, 0 }, 357 { PCI_PRODUCT_ATI_RADEON_R423_UQ, RADEON_R420, 0 }, 358 { PCI_PRODUCT_ATI_RADEON_R423_UR, RADEON_R420, 0 }, 359 { PCI_PRODUCT_ATI_RADEON_R423_UT, RADEON_R420, 0 }, 360 { PCI_PRODUCT_ATI_RADEON_R423_5D57, RADEON_R420, 0 }, 361 362 { 0, 0, 0 } 363 }; 364 365 static struct { 366 int divider; 367 int mask; 368 } radeonfb_dividers[] = { 369 { 1, 0 }, 370 { 2, 1 }, 371 { 3, 4 }, 372 { 4, 2 }, 373 { 6, 6 }, 374 { 8, 3 }, 375 { 12, 7 }, 376 { 0, 0 } 377 }; 378 379 /* 380 * This table taken from X11. 381 */ 382 static const struct { 383 int family; 384 struct radeon_tmds_pll plls[4]; 385 } radeonfb_tmds_pll[] = { 386 { RADEON_R100, {{12000, 0xa1b}, {-1, 0xa3f}}}, 387 { RADEON_RV100, {{12000, 0xa1b}, {-1, 0xa3f}}}, 388 { RADEON_RS100, {{0, 0}}}, 389 { RADEON_RV200, {{15000, 0xa1b}, {-1, 0xa3f}}}, 390 { RADEON_RS200, {{15000, 0xa1b}, {-1, 0xa3f}}}, 391 { RADEON_R200, {{15000, 0xa1b}, {-1, 0xa3f}}}, 392 { RADEON_RV250, {{15500, 0x81b}, {-1, 0x83f}}}, 393 { RADEON_RS300, {{0, 0}}}, 394 { RADEON_RV280, {{13000, 0x400f4}, {15000, 0x400f7}}}, 395 { RADEON_R300, {{-1, 0xb01cb}}}, 396 { RADEON_R350, {{-1, 0xb01cb}}}, 397 { RADEON_RV350, {{15000, 0xb0155}, {-1, 0xb01cb}}}, 398 { RADEON_RV380, {{15000, 0xb0155}, {-1, 0xb01cb}}}, 399 { RADEON_R420, {{-1, 0xb01cb}}}, 400 }; 401 402 #define RADEONFB_BACKLIGHT_MAX 255 /* Maximum backlight level. */ 403 404 405 CFATTACH_DECL(radeonfb, sizeof (struct radeonfb_softc), 406 radeonfb_match, radeonfb_attach, NULL, NULL); 407 408 static int 409 radeonfb_match(struct device *parent, struct cfdata *match, void *aux) 410 { 411 struct pci_attach_args *pa = aux; 412 int i; 413 414 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_ATI) 415 return 0; 416 417 for (i = 0; radeonfb_devices[i].devid; i++) { 418 if (PCI_PRODUCT(pa->pa_id) == radeonfb_devices[i].devid) 419 return 100; /* high to defeat VGA/VESA */ 420 } 421 422 return 0; 423 } 424 425 static void 426 radeonfb_attach(struct device *parent, struct device *dev, void *aux) 427 { 428 struct radeonfb_softc *sc = (struct radeonfb_softc *)dev; 429 struct pci_attach_args *pa = aux; 430 const char *mptr; 431 bus_size_t bsz; 432 pcireg_t screg; 433 int i, j, fg, bg, ul; 434 uint32_t v; 435 436 sc->sc_id = pa->pa_id; 437 for (i = 0; radeonfb_devices[i].devid; i++) { 438 if (PCI_PRODUCT(sc->sc_id) == radeonfb_devices[i].devid) 439 break; 440 } 441 442 pci_devinfo(sc->sc_id, pa->pa_class, 0, sc->sc_devinfo, 443 sizeof(sc->sc_devinfo)); 444 445 aprint_naive("\n"); 446 aprint_normal(": %s\n", sc->sc_devinfo); 447 448 KASSERT(radeonfb_devices[i].devid != 0); 449 sc->sc_pt = pa->pa_tag; 450 sc->sc_pc = pa->pa_pc; 451 sc->sc_family = radeonfb_devices[i].family; 452 sc->sc_flags = radeonfb_devices[i].flags; 453 454 /* enable memory and IO access */ 455 screg = pci_conf_read(sc->sc_pc, sc->sc_pt, PCI_COMMAND_STATUS_REG); 456 screg |= PCI_FLAGS_IO_ENABLED | PCI_FLAGS_MEM_ENABLED; 457 pci_conf_write(sc->sc_pc, sc->sc_pt, PCI_COMMAND_STATUS_REG, screg); 458 459 /* 460 * Some flags are general to entire chip families, and rather 461 * than clutter up the table with them, we go ahead and set 462 * them here. 463 */ 464 switch (sc->sc_family) { 465 case RADEON_RS100: 466 case RADEON_RS200: 467 sc->sc_flags |= RFB_IGP | RFB_RV100; 468 break; 469 470 case RADEON_RV100: 471 case RADEON_RV200: 472 case RADEON_RV250: 473 case RADEON_RV280: 474 sc->sc_flags |= RFB_RV100; 475 break; 476 477 case RADEON_RS300: 478 sc->sc_flags |= RFB_SDAC | RFB_IGP | RFB_RV100; 479 break; 480 481 case RADEON_R300: 482 case RADEON_RV350: 483 case RADEON_R350: 484 case RADEON_RV380: 485 case RADEON_R420: 486 /* newer chips */ 487 sc->sc_flags |= RFB_R300; 488 break; 489 490 case RADEON_R100: 491 sc->sc_flags |= RFB_NCRTC2; 492 break; 493 } 494 495 /* 496 * XXX: to support true multihead, this must change. 497 */ 498 sc->sc_ndisplays = 1; 499 500 /* XXX: */ 501 if (!HAS_CRTC2(sc)) { 502 sc->sc_ndisplays = 1; 503 } 504 505 if (pci_mapreg_map(pa, RADEON_MAPREG_MMIO, PCI_MAPREG_TYPE_MEM, 0, 506 &sc->sc_regt, &sc->sc_regh, &sc->sc_regaddr, 507 &sc->sc_regsz) != 0) { 508 aprint_error("%s: unable to map registers!\n", XNAME(sc)); 509 goto error; 510 } 511 512 if (pci_mapreg_map(pa, RADEON_MAPREG_IO, PCI_MAPREG_TYPE_IO, 0, 513 &sc->sc_iot, &sc->sc_ioh, &sc->sc_ioaddr, 514 &sc->sc_iosz) != 0) { 515 aprint_error("%s: unable to map IO registers!\n", XNAME(sc)); 516 } 517 518 /* scratch register test... */ 519 if (radeonfb_scratch_test(sc, RADEON_BIOS_0_SCRATCH, 0x55555555) || 520 radeonfb_scratch_test(sc, RADEON_BIOS_0_SCRATCH, 0xaaaaaaaa)) { 521 aprint_error("%s: scratch register test failed!\n", XNAME(sc)); 522 goto error; 523 } 524 525 PRINTREG(RADEON_BIOS_4_SCRATCH); 526 PRINTREG(RADEON_FP_GEN_CNTL); 527 PRINTREG(RADEON_FP2_GEN_CNTL); 528 PRINTREG(RADEON_TMDS_CNTL); 529 PRINTREG(RADEON_TMDS_TRANSMITTER_CNTL); 530 PRINTREG(RADEON_TMDS_PLL_CNTL); 531 PRINTREG(RADEON_LVDS_GEN_CNTL); 532 PRINTREG(RADEON_FP_HORZ_STRETCH); 533 PRINTREG(RADEON_FP_VERT_STRETCH); 534 535 /* XXX: RV100 specific */ 536 PUT32(sc, RADEON_TMDS_PLL_CNTL, 0xa27); 537 538 PATCH32(sc, RADEON_TMDS_TRANSMITTER_CNTL, 539 RADEON_TMDS_TRANSMITTER_PLLEN, 540 RADEON_TMDS_TRANSMITTER_PLLEN | RADEON_TMDS_TRANSMITTER_PLLRST); 541 542 radeonfb_i2c_init(sc); 543 544 radeonfb_loadbios(sc, pa); 545 546 #ifdef RADEON_BIOS_INIT 547 if (radeonfb_bios_init(sc)) { 548 aprint_error("%s: BIOS inititialization failed\n", XNAME(sc)); 549 goto error; 550 } 551 #endif 552 553 if (radeonfb_getclocks(sc)) { 554 aprint_error("%s: Unable to get reference clocks from BIOS\n", 555 XNAME(sc)); 556 goto error; 557 } 558 559 if (radeonfb_gettmds(sc)) { 560 aprint_error("%s: Unable to identify TMDS PLL settings\n", 561 XNAME(sc)); 562 goto error; 563 } 564 565 aprint_verbose("%s: refclk = %d.%03d MHz, refdiv = %d " 566 "minpll = %d, maxpll = %d\n", XNAME(sc), 567 (int)sc->sc_refclk / 1000, (int)sc->sc_refclk % 1000, 568 (int)sc->sc_refdiv, (int)sc->sc_minpll, (int)sc->sc_maxpll); 569 570 radeonfb_getconnectors(sc); 571 572 radeonfb_set_fbloc(sc); 573 574 for (i = 0; radeonfb_limits[i].size; i++) { 575 if (sc->sc_memsz >= radeonfb_limits[i].size) { 576 sc->sc_maxx = radeonfb_limits[i].maxx; 577 sc->sc_maxy = radeonfb_limits[i].maxy; 578 sc->sc_maxbpp = radeonfb_limits[i].maxbpp; 579 /* framebuffer offset, start at a 4K page */ 580 sc->sc_fboffset = sc->sc_memsz / 581 radeonfb_limits[i].maxdisp; 582 /* 583 * we use the fbsize to figure out where we can store 584 * things like cursor data. 585 */ 586 sc->sc_fbsize = 587 ROUNDUP(ROUNDUP(sc->sc_maxx * sc->sc_maxbpp / 8 , 588 RADEON_STRIDEALIGN) * sc->sc_maxy, 589 4096); 590 break; 591 } 592 } 593 594 595 radeonfb_init_misc(sc); 596 radeonfb_init_palette(sc, 0); 597 if (HAS_CRTC2(sc)) 598 radeonfb_init_palette(sc, 1); 599 600 /* program the DAC wirings */ 601 for (i = 0; i < (HAS_CRTC2(sc) ? 2 : 1); i++) { 602 switch (sc->sc_ports[i].rp_dac_type) { 603 case RADEON_DAC_PRIMARY: 604 PATCH32(sc, RADEON_DAC_CNTL2, 605 i ? RADEON_DAC2_DAC_CLK_SEL : 0, 606 ~RADEON_DAC2_DAC_CLK_SEL); 607 break; 608 case RADEON_DAC_TVDAC: 609 /* we always use the TVDAC to drive a secondary analog 610 * CRT for now. if we ever support TV-out this will 611 * have to change. 612 */ 613 SET32(sc, RADEON_DAC_CNTL2, 614 RADEON_DAC2_DAC2_CLK_SEL); 615 PATCH32(sc, RADEON_DISP_HW_DEBUG, 616 i ? 0 : RADEON_CRT2_DISP1_SEL, 617 ~RADEON_CRT2_DISP1_SEL); 618 break; 619 } 620 } 621 PRINTREG(RADEON_DAC_CNTL2); 622 PRINTREG(RADEON_DISP_HW_DEBUG); 623 624 /* other DAC programming */ 625 v = GET32(sc, RADEON_DAC_CNTL); 626 v &= (RADEON_DAC_RANGE_CNTL_MASK | RADEON_DAC_BLANKING); 627 v |= RADEON_DAC_MASK_ALL | RADEON_DAC_8BIT_EN; 628 PUT32(sc, RADEON_DAC_CNTL, v); 629 PRINTREG(RADEON_DAC_CNTL); 630 631 /* XXX: this may need more investigation */ 632 PUT32(sc, RADEON_TV_DAC_CNTL, 0x00280203); 633 PRINTREG(RADEON_TV_DAC_CNTL); 634 635 /* enable TMDS */ 636 SET32(sc, RADEON_FP_GEN_CNTL, 637 RADEON_FP_TMDS_EN | 638 RADEON_FP_CRTC_DONT_SHADOW_VPAR | 639 RADEON_FP_CRTC_DONT_SHADOW_HEND); 640 CLR32(sc, RADEON_FP_GEN_CNTL, RADEON_FP_SEL_CRTC2); 641 if (HAS_CRTC2(sc)) 642 SET32(sc, RADEON_FP2_GEN_CNTL, RADEON_FP2_SRC_SEL_CRTC2); 643 644 /* 645 * we use bus_space_map instead of pci_mapreg, because we don't 646 * need the full aperature space. no point in wasting virtual 647 * address space we don't intend to use, right? 648 */ 649 if ((sc->sc_memsz < (4096 * 1024)) || 650 (pci_mapreg_info(sc->sc_pc, sc->sc_pt, RADEON_MAPREG_VRAM, 651 PCI_MAPREG_TYPE_MEM, &sc->sc_memaddr, &bsz, NULL) != 0) || 652 (bsz < sc->sc_memsz)) { 653 sc->sc_memsz = 0; 654 aprint_error("%s: Bad frame buffer configuration\n", 655 XNAME(sc)); 656 goto error; 657 } 658 659 /* 64 MB should be enough -- more just wastes map entries */ 660 if (sc->sc_memsz > (64 << 20)) 661 sc->sc_memsz = (64 << 20); 662 663 sc->sc_memt = pa->pa_memt; 664 if (bus_space_map(sc->sc_memt, sc->sc_memaddr, sc->sc_memsz, 665 BUS_SPACE_MAP_LINEAR, &sc->sc_memh) != 0) { 666 sc->sc_memsz = 0; 667 aprint_error("%s: Unable to map frame buffer\n", XNAME(sc)); 668 goto error; 669 } 670 671 aprint_normal("%s: %d MB aperture at 0x%08x, " 672 "%d KB registers at 0x%08x\n", XNAME(sc), 673 (int)sc->sc_memsz >> 20, (unsigned)sc->sc_memaddr, 674 (int)sc->sc_regsz >> 10, (unsigned)sc->sc_regaddr); 675 676 /* setup default video mode from devprop (allows PROM override) */ 677 sc->sc_defaultmode = radeonfb_default_mode; 678 if (prop_dictionary_get_cstring_nocopy(device_properties(&sc->sc_dev), 679 "videomode", &mptr)) { 680 681 strncpy(sc->sc_modebuf, mptr, sizeof(sc->sc_modebuf)); 682 sc->sc_defaultmode = sc->sc_modebuf; 683 } 684 685 /* initialize some basic display parameters */ 686 for (i = 0; i < sc->sc_ndisplays; i++) { 687 struct radeonfb_display *dp = &sc->sc_displays[i]; 688 struct rasops_info *ri; 689 long defattr; 690 struct wsemuldisplaydev_attach_args aa; 691 692 /* 693 * Figure out how many "displays" (desktops) we are going to 694 * support. If more than one, then each CRTC gets its own 695 * programming. 696 * 697 * XXX: this code needs to change to support mergedfb. 698 * XXX: would be nice to allow this to be overridden 699 */ 700 if (HAS_CRTC2(sc) && (sc->sc_ndisplays == 1)) { 701 DPRINTF(("dual crtcs!\n")); 702 dp->rd_ncrtcs = 2; 703 dp->rd_crtcs[0].rc_number = 0; 704 dp->rd_crtcs[1].rc_number = 1; 705 } else { 706 dp->rd_ncrtcs = 1; 707 dp->rd_crtcs[0].rc_number = i; 708 } 709 710 /* set up port pointer */ 711 for (j = 0; j < dp->rd_ncrtcs; j++) { 712 dp->rd_crtcs[j].rc_port = 713 &sc->sc_ports[dp->rd_crtcs[j].rc_number]; 714 } 715 716 dp->rd_softc = sc; 717 dp->rd_wsmode = WSDISPLAYIO_MODE_EMUL; 718 dp->rd_bg = WS_DEFAULT_BG; 719 #if 0 720 dp->rd_bpp = sc->sc_maxbpp; /* XXX: for now */ 721 #else 722 dp->rd_bpp = RADEONFB_DEFAULT_DEPTH; /* XXX */ 723 #endif 724 /* for text mode, we pick a resolution that won't 725 * require panning */ 726 radeonfb_pickres(dp, &dp->rd_virtx, &dp->rd_virty, 0); 727 728 aprint_normal("%s: display %d: " 729 "initial virtual resolution %dx%d at %d bpp\n", 730 XNAME(sc), i, dp->rd_virtx, dp->rd_virty, dp->rd_bpp); 731 732 /* now select the *video mode* that we will use */ 733 for (j = 0; j < dp->rd_ncrtcs; j++) { 734 const struct videomode *vmp; 735 vmp = radeonfb_port_mode(sc, dp->rd_crtcs[j].rc_port, 736 dp->rd_virtx, dp->rd_virty); 737 738 /* 739 * virtual resolution should be at least as high as 740 * physical 741 */ 742 if (dp->rd_virtx < vmp->hdisplay || 743 dp->rd_virty < vmp->vdisplay) { 744 dp->rd_virtx = vmp->hdisplay; 745 dp->rd_virty = vmp->vdisplay; 746 } 747 748 dp->rd_crtcs[j].rc_videomode = *vmp; 749 printf("%s: port %d: physical %dx%d %dHz\n", 750 XNAME(sc), j, vmp->hdisplay, vmp->vdisplay, 751 DIVIDE(DIVIDE(vmp->dot_clock * 1000, 752 vmp->htotal), vmp->vtotal)); 753 } 754 755 /* N.B.: radeon wants 64-byte aligned stride */ 756 dp->rd_stride = dp->rd_virtx * dp->rd_bpp / 8; 757 dp->rd_stride = ROUNDUP(dp->rd_stride, RADEON_STRIDEALIGN); 758 759 dp->rd_offset = sc->sc_fboffset * i; 760 dp->rd_fbptr = (vaddr_t)bus_space_vaddr(sc->sc_memt, 761 sc->sc_memh) + dp->rd_offset; 762 dp->rd_curoff = sc->sc_fbsize; 763 dp->rd_curptr = dp->rd_fbptr + dp->rd_curoff; 764 765 DPRINTF(("fpbtr = %p\n", (void *)dp->rd_fbptr)); 766 767 switch (dp->rd_bpp) { 768 case 8: 769 dp->rd_format = 2; 770 break; 771 case 32: 772 dp->rd_format = 6; 773 break; 774 default: 775 aprint_error("%s: bad depth %d\n", XNAME(sc), 776 dp->rd_bpp); 777 goto error; 778 } 779 780 printf("init engine\n"); 781 /* XXX: this seems suspicious - per display engine 782 initialization? */ 783 radeonfb_engine_init(dp); 784 785 /* copy the template into place */ 786 dp->rd_wsscreens_storage[0] = radeonfb_stdscreen; 787 dp->rd_wsscreens = dp->rd_wsscreens_storage; 788 789 /* and make up the list */ 790 dp->rd_wsscreenlist.nscreens = 1; 791 dp->rd_wsscreenlist.screens = 792 (const struct wsscreen_descr **)&dp->rd_wsscreens; 793 794 vcons_init(&dp->rd_vd, dp, dp->rd_wsscreens, 795 &radeonfb_accessops); 796 797 dp->rd_vd.init_screen = radeonfb_init_screen; 798 799 dp->rd_console = 1; 800 801 dp->rd_vscreen.scr_flags |= VCONS_SCREEN_IS_STATIC; 802 803 804 vcons_init_screen(&dp->rd_vd, &dp->rd_vscreen, 805 dp->rd_console, &defattr); 806 807 ri = &dp->rd_vscreen.scr_ri; 808 809 /* clear the screen */ 810 rasops_unpack_attr(defattr, &fg, &bg, &ul); 811 radeonfb_rectfill(dp, 0, 0, ri->ri_width, ri->ri_height, 812 ri->ri_devcmap[bg & 0xf]); 813 814 dp->rd_wsscreens->textops = &ri->ri_ops; 815 dp->rd_wsscreens->capabilities = ri->ri_caps; 816 dp->rd_wsscreens->nrows = ri->ri_rows; 817 dp->rd_wsscreens->ncols = ri->ri_cols; 818 819 #ifdef SPLASHSCREEN 820 dp->rd_splash.si_depth = ri->ri_depth; 821 dp->rd_splash.si_bits = ri->ri_bits; 822 dp->rd_splash.si_hwbits = ri->ri_hwbits; 823 dp->rd_splash.si_width = ri->ri_width; 824 dp->rd_splash.si_height = ri->ri_height; 825 dp->rd_splash.si_stride = ri->ri_stride; 826 dp->rd_splash.si_fillrect = NULL; 827 #endif 828 if (dp->rd_console) { 829 830 wsdisplay_cnattach(dp->rd_wsscreens, ri, 0, 0, 831 defattr); 832 #ifdef SPLASHSCREEN 833 splash_render(&dp->rd_splash, 834 SPLASH_F_CENTER|SPLASH_F_FILL); 835 #endif 836 837 #ifdef SPLASHSCREEN_PROGRESS 838 dp->rd_progress.sp_top = (dp->rd_virty / 8) * 7; 839 dp->rd_progress.sp_width = (dp->rd_virtx / 4) * 3; 840 dp->rd_progress.sp_left = (dp->rd_virtx - 841 dp->rd_progress.sp_width) / 2; 842 dp->rd_progress.sp_height = 20; 843 dp->rd_progress.sp_state = -1; 844 dp->rd_progress.sp_si = &dp->rd_splash; 845 splash_progress_init(&dp->rd_progress); 846 SCREEN_DISABLE_DRAWING(&dp->rd_vscreen); 847 #endif 848 849 } else { 850 851 /* 852 * since we're not the console we can postpone 853 * the rest until someone actually allocates a 854 * screen for us. but we do clear the screen 855 * at least. 856 */ 857 memset(ri->ri_bits, 0, 1024); 858 859 radeonfb_modeswitch(dp); 860 #ifdef SPLASHSCREEN 861 splash_render(&dp->rd_splash, 862 SPLASH_F_CENTER|SPLASH_F_FILL); 863 SCREEN_DISABLE_DRAWING(&dp->rd_vscreen); 864 #endif 865 } 866 867 aa.console = dp->rd_console; 868 aa.scrdata = &dp->rd_wsscreenlist; 869 aa.accessops = &radeonfb_accessops; 870 aa.accesscookie = &dp->rd_vd; 871 872 config_found(&sc->sc_dev, &aa, wsemuldisplaydevprint); 873 radeonfb_blank(dp, 0); 874 875 /* Initialise delayed lvds operations for backlight. */ 876 callout_init(&dp->rd_bl_lvds_co, 0); 877 callout_setfunc(&dp->rd_bl_lvds_co, 878 radeonfb_lvds_callout, dp); 879 } 880 881 config_found_ia(dev, "drm", aux, radeonfb_drm_print); 882 883 return; 884 885 error: 886 if (sc->sc_biossz) 887 free(sc->sc_bios, M_DEVBUF); 888 889 if (sc->sc_regsz) 890 bus_space_unmap(sc->sc_regt, sc->sc_regh, sc->sc_regsz); 891 892 if (sc->sc_memsz) 893 bus_space_unmap(sc->sc_memt, sc->sc_memh, sc->sc_memsz); 894 } 895 896 static int 897 radeonfb_drm_print(void *aux, const char *pnp) 898 { 899 if (pnp) 900 aprint_normal("direct rendering for %s", pnp); 901 return (UNSUPP); 902 } 903 904 int 905 radeonfb_ioctl(void *v, void *vs, 906 unsigned long cmd, void *d, int flag, struct lwp *l) 907 { 908 struct vcons_data *vd; 909 struct radeonfb_display *dp; 910 struct radeonfb_softc *sc; 911 struct wsdisplay_param *param; 912 913 vd = (struct vcons_data *)v; 914 dp = (struct radeonfb_display *)vd->cookie; 915 sc = dp->rd_softc; 916 917 switch (cmd) { 918 case WSDISPLAYIO_GTYPE: 919 *(unsigned *)d = WSDISPLAY_TYPE_PCIMISC; 920 return 0; 921 922 case WSDISPLAYIO_GINFO: 923 if (vd->active != NULL) { 924 struct wsdisplay_fbinfo *fb; 925 fb = (struct wsdisplay_fbinfo *)d; 926 fb->width = dp->rd_virtx; 927 fb->height = dp->rd_virty; 928 fb->depth = dp->rd_bpp; 929 fb->cmsize = 256; 930 return 0; 931 } else 932 return ENODEV; 933 case WSDISPLAYIO_GVIDEO: 934 if (radeonfb_isblank(dp)) 935 *(unsigned *)d = WSDISPLAYIO_VIDEO_OFF; 936 else 937 *(unsigned *)d = WSDISPLAYIO_VIDEO_ON; 938 return 0; 939 940 case WSDISPLAYIO_SVIDEO: 941 radeonfb_blank(dp, 942 (*(unsigned int *)d == WSDISPLAYIO_VIDEO_OFF)); 943 return 0; 944 945 case WSDISPLAYIO_GETCMAP: 946 #if 0 947 if (dp->rd_bpp == 8) 948 return radeonfb_getcmap(sc, 949 (struct wsdisplay_cmap *)d); 950 #endif 951 return EINVAL; 952 953 case WSDISPLAYIO_PUTCMAP: 954 #if 0 955 if (dp->rd_bpp == 8) 956 return radeonfb_putcmap(sc, 957 (struct wsdisplay_cmap *)d); 958 #endif 959 return EINVAL; 960 961 case WSDISPLAYIO_LINEBYTES: 962 *(unsigned *)d = dp->rd_stride; 963 return 0; 964 965 case WSDISPLAYIO_SMODE: 966 if (*(int *)d != dp->rd_wsmode) { 967 dp->rd_wsmode = *(int *)d; 968 if ((dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) && 969 (dp->rd_vd.active)) { 970 vcons_redraw_screen(dp->rd_vd.active); 971 } 972 } 973 return 0; 974 975 case WSDISPLAYIO_GCURMAX: 976 ((struct wsdisplay_curpos *)d)->x = RADEON_CURSORMAXX; 977 ((struct wsdisplay_curpos *)d)->y = RADEON_CURSORMAXY; 978 return 0; 979 980 case WSDISPLAYIO_SCURSOR: 981 return radeonfb_set_cursor(dp, (struct wsdisplay_cursor *)d); 982 983 case WSDISPLAYIO_GCURSOR: 984 return EPASSTHROUGH; 985 986 case WSDISPLAYIO_GCURPOS: 987 ((struct wsdisplay_curpos *)d)->x = dp->rd_cursor.rc_pos.x; 988 ((struct wsdisplay_curpos *)d)->y = dp->rd_cursor.rc_pos.y; 989 return 0; 990 991 case WSDISPLAYIO_SCURPOS: 992 return radeonfb_set_curpos(dp, (struct wsdisplay_curpos *)d); 993 994 case WSDISPLAYIO_SSPLASH: 995 #if defined(SPLASHSCREEN) 996 if (*(int *)d == 1) { 997 SCREEN_DISABLE_DRAWING(&dp->rd_vscreen); 998 splash_render(&dp->rd_splash, 999 SPLASH_F_CENTER|SPLASH_F_FILL); 1000 } else 1001 SCREEN_ENABLE_DRAWING(&dp->rd_vscreen); 1002 return 0; 1003 #else 1004 return ENODEV; 1005 #endif 1006 case WSDISPLAYIO_SPROGRESS: 1007 #if defined(SPLASHSCREEN) && defined(SPLASHSCREEN_PROGRESS) 1008 dp->rd_progress.sp_force = 1; 1009 splash_progress_update(&dp->rd_progress); 1010 dp->rd_progress.sp_force = 0; 1011 return 0; 1012 #else 1013 return ENODEV; 1014 #endif 1015 case WSDISPLAYIO_GETPARAM: 1016 param = (struct wsdisplay_param *)d; 1017 if (param->param == WSDISPLAYIO_PARAM_BACKLIGHT) { 1018 param->min = 0; 1019 param->max = RADEONFB_BACKLIGHT_MAX; 1020 param->curval = radeonfb_get_backlight(dp); 1021 return 0; 1022 } 1023 return EPASSTHROUGH; 1024 1025 case WSDISPLAYIO_SETPARAM: 1026 param = (struct wsdisplay_param *)d; 1027 if (param->param == WSDISPLAYIO_PARAM_BACKLIGHT) { 1028 return radeonfb_set_backlight(dp, param->curval); 1029 } 1030 return EPASSTHROUGH; 1031 1032 default: 1033 return EPASSTHROUGH; 1034 } 1035 } 1036 1037 paddr_t 1038 radeonfb_mmap(void *v, void *vs, off_t offset, int prot) 1039 { 1040 struct vcons_data *vd; 1041 struct radeonfb_display *dp; 1042 struct radeonfb_softc *sc; 1043 #ifdef RADEONFB_MMAP_BARS 1044 struct lwp *me; 1045 #endif 1046 paddr_t pa; 1047 1048 vd = (struct vcons_data *)v; 1049 dp = (struct radeonfb_display *)vd->cookie; 1050 sc = dp->rd_softc; 1051 1052 /* XXX: note that we don't allow mapping of registers right now */ 1053 /* XXX: this means that the XFree86 radeon driver won't work */ 1054 1055 if ((offset >= 0) && (offset < (dp->rd_virty * dp->rd_stride))) { 1056 pa = bus_space_mmap(sc->sc_memt, 1057 sc->sc_memaddr + dp->rd_offset + offset, 0, 1058 prot, BUS_SPACE_MAP_LINEAR); 1059 return pa; 1060 } 1061 1062 #ifdef RADEONFB_MMAP_BARS 1063 /* 1064 * restrict all other mappings to processes with superuser privileges 1065 * or the kernel itself 1066 */ 1067 me = curlwp; 1068 if (me != NULL) { 1069 if (kauth_authorize_generic(me->l_cred, KAUTH_GENERIC_ISSUSER, 1070 NULL) != 0) { 1071 printf("%s: mmap() rejected.\n", sc->sc_dev.dv_xname); 1072 return -1; 1073 } 1074 } 1075 1076 if ((offset >= sc->sc_regaddr) && 1077 (offset < sc->sc_regaddr + sc->sc_regsz)) { 1078 return bus_space_mmap(sc->sc_regt, offset, 0, prot, 1079 BUS_SPACE_MAP_LINEAR); 1080 } 1081 1082 if ((offset >= sc->sc_memaddr) && 1083 (offset < sc->sc_memaddr + sc->sc_memsz)) { 1084 return bus_space_mmap(sc->sc_memt, offset, 0, prot, 1085 BUS_SPACE_MAP_LINEAR); 1086 } 1087 1088 #ifdef macppc 1089 /* allow mapping of IO space */ 1090 if ((offset >= 0xf2000000) && (offset < 0xf2800000)) { 1091 pa = bus_space_mmap(sc->sc_iot, offset-0xf2000000, 0, prot, 1092 BUS_SPACE_MAP_LINEAR); 1093 return pa; 1094 } 1095 #endif /* macppc */ 1096 1097 #endif /* RADEONFB_MMAP_BARS */ 1098 1099 return -1; 1100 } 1101 1102 static void 1103 radeonfb_loadbios(struct radeonfb_softc *sc, struct pci_attach_args *pa) 1104 { 1105 bus_space_tag_t romt; 1106 bus_space_handle_t romh, biosh; 1107 bus_size_t romsz; 1108 bus_addr_t ptr; 1109 1110 if (pci_mapreg_map(pa, PCI_MAPREG_ROM, PCI_MAPREG_TYPE_ROM, 1111 BUS_SPACE_MAP_PREFETCHABLE, &romt, &romh, NULL, &romsz) != 0) { 1112 aprint_verbose("%s: unable to map BIOS!\n", XNAME(sc)); 1113 return; 1114 } 1115 1116 pci_find_rom(pa, romt, romh, PCI_ROM_CODE_TYPE_X86, &biosh, 1117 &sc->sc_biossz); 1118 if (sc->sc_biossz == 0) { 1119 aprint_verbose("%s: Video BIOS not present\n", XNAME(sc)); 1120 return; 1121 } 1122 1123 sc->sc_bios = malloc(sc->sc_biossz, M_DEVBUF, M_WAITOK); 1124 bus_space_read_region_1(romt, biosh, 0, sc->sc_bios, sc->sc_biossz); 1125 1126 /* unmap the PCI expansion rom */ 1127 bus_space_unmap(romt, romh, romsz); 1128 1129 /* turn off rom decoder now */ 1130 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM, 1131 pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM) & 1132 ~PCI_MAPREG_ROM_ENABLE); 1133 1134 ptr = GETBIOS16(sc, 0x48); 1135 if ((GETBIOS32(sc, ptr + 4) == 0x41544f4d /* "ATOM" */) || 1136 (GETBIOS32(sc, ptr + 4) == 0x4d4f5441 /* "MOTA" */)) { 1137 sc->sc_flags |= RFB_ATOM; 1138 } 1139 1140 aprint_verbose("%s: Found %d KB %s BIOS\n", XNAME(sc), 1141 (unsigned)sc->sc_biossz >> 10, IS_ATOM(sc) ? "ATOM" : "Legacy"); 1142 } 1143 1144 1145 uint32_t 1146 radeonfb_get32(struct radeonfb_softc *sc, uint32_t reg) 1147 { 1148 1149 return bus_space_read_4(sc->sc_regt, sc->sc_regh, reg); 1150 } 1151 1152 void 1153 radeonfb_put32(struct radeonfb_softc *sc, uint32_t reg, uint32_t val) 1154 { 1155 1156 bus_space_write_4(sc->sc_regt, sc->sc_regh, reg, val); 1157 } 1158 1159 void 1160 radeonfb_mask32(struct radeonfb_softc *sc, uint32_t reg, 1161 uint32_t andmask, uint32_t ormask) 1162 { 1163 int s; 1164 uint32_t val; 1165 1166 s = splhigh(); 1167 val = radeonfb_get32(sc, reg); 1168 val = (val & andmask) | ormask; 1169 radeonfb_put32(sc, reg, val); 1170 splx(s); 1171 } 1172 1173 uint32_t 1174 radeonfb_getindex(struct radeonfb_softc *sc, uint32_t idx) 1175 { 1176 int s; 1177 uint32_t val; 1178 1179 s = splhigh(); 1180 radeonfb_put32(sc, RADEON_MM_INDEX, idx); 1181 val = radeonfb_get32(sc, RADEON_MM_DATA); 1182 splx(s); 1183 1184 return (val); 1185 } 1186 1187 void 1188 radeonfb_putindex(struct radeonfb_softc *sc, uint32_t idx, uint32_t val) 1189 { 1190 int s; 1191 1192 s = splhigh(); 1193 radeonfb_put32(sc, RADEON_MM_INDEX, idx); 1194 radeonfb_put32(sc, RADEON_MM_DATA, val); 1195 splx(s); 1196 } 1197 1198 void 1199 radeonfb_maskindex(struct radeonfb_softc *sc, uint32_t idx, 1200 uint32_t andmask, uint32_t ormask) 1201 { 1202 int s; 1203 uint32_t val; 1204 1205 s = splhigh(); 1206 radeonfb_put32(sc, RADEON_MM_INDEX, idx); 1207 val = radeonfb_get32(sc, RADEON_MM_DATA); 1208 val = (val & andmask) | ormask; 1209 radeonfb_put32(sc, RADEON_MM_DATA, val); 1210 splx(s); 1211 } 1212 1213 uint32_t 1214 radeonfb_getpll(struct radeonfb_softc *sc, uint32_t idx) 1215 { 1216 int s; 1217 uint32_t val; 1218 1219 s = splhigh(); 1220 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, idx & 0x3f); 1221 val = radeonfb_get32(sc, RADEON_CLOCK_CNTL_DATA); 1222 if (HAS_R300CG(sc)) 1223 radeonfb_r300cg_workaround(sc); 1224 splx(s); 1225 1226 return (val); 1227 } 1228 1229 void 1230 radeonfb_putpll(struct radeonfb_softc *sc, uint32_t idx, uint32_t val) 1231 { 1232 int s; 1233 1234 s = splhigh(); 1235 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, (idx & 0x3f) | 1236 RADEON_PLL_WR_EN); 1237 radeonfb_put32(sc, RADEON_CLOCK_CNTL_DATA, val); 1238 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, 0); 1239 splx(s); 1240 } 1241 1242 void 1243 radeonfb_maskpll(struct radeonfb_softc *sc, uint32_t idx, 1244 uint32_t andmask, uint32_t ormask) 1245 { 1246 int s; 1247 uint32_t val; 1248 1249 s = splhigh(); 1250 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, (idx & 0x3f) | 1251 RADEON_PLL_WR_EN); 1252 val = radeonfb_get32(sc, RADEON_CLOCK_CNTL_DATA); 1253 val = (val & andmask) | ormask; 1254 radeonfb_put32(sc, RADEON_CLOCK_CNTL_DATA, val); 1255 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, 0); 1256 splx(s); 1257 } 1258 1259 int 1260 radeonfb_scratch_test(struct radeonfb_softc *sc, int reg, uint32_t v) 1261 { 1262 uint32_t saved; 1263 1264 saved = GET32(sc, reg); 1265 PUT32(sc, reg, v); 1266 if (GET32(sc, reg) != v) { 1267 return -1; 1268 } 1269 PUT32(sc, reg, saved); 1270 return 0; 1271 } 1272 1273 uintmax_t 1274 radeonfb_getprop_num(struct radeonfb_softc *sc, const char *name, 1275 uintmax_t defval) 1276 { 1277 prop_number_t pn; 1278 pn = prop_dictionary_get(device_properties(&sc->sc_dev), name); 1279 if (pn == NULL) { 1280 return defval; 1281 } 1282 KASSERT(prop_object_type(pn) == PROP_TYPE_NUMBER); 1283 return (prop_number_integer_value(pn)); 1284 } 1285 1286 int 1287 radeonfb_getclocks(struct radeonfb_softc *sc) 1288 { 1289 bus_addr_t ptr; 1290 int refclk = 0; 1291 int refdiv = 0; 1292 int minpll = 0; 1293 int maxpll = 0; 1294 1295 /* load initial property values if port/board provides them */ 1296 refclk = radeonfb_getprop_num(sc, "refclk", 0) & 0xffff; 1297 refdiv = radeonfb_getprop_num(sc, "refdiv", 0) & 0xffff; 1298 minpll = radeonfb_getprop_num(sc, "minpll", 0) & 0xffffffffU; 1299 maxpll = radeonfb_getprop_num(sc, "maxpll", 0) & 0xffffffffU; 1300 1301 if (refclk && refdiv && minpll && maxpll) 1302 goto dontprobe; 1303 1304 if (!sc->sc_biossz) { 1305 /* no BIOS */ 1306 aprint_verbose("%s: No video BIOS, using default clocks\n", 1307 XNAME(sc)); 1308 if (IS_IGP(sc)) 1309 refclk = refclk ? refclk : 1432; 1310 else 1311 refclk = refclk ? refclk : 2700; 1312 refdiv = refdiv ? refdiv : 12; 1313 minpll = minpll ? minpll : 12500; 1314 maxpll = maxpll ? maxpll : 35000; 1315 } else if (IS_ATOM(sc)) { 1316 /* ATOM BIOS */ 1317 ptr = GETBIOS16(sc, 0x48); 1318 ptr = GETBIOS16(sc, ptr + 32); /* aka MasterDataStart */ 1319 ptr = GETBIOS16(sc, ptr + 12); /* pll info block */ 1320 refclk = refclk ? refclk : GETBIOS16(sc, ptr + 82); 1321 minpll = minpll ? minpll : GETBIOS16(sc, ptr + 78); 1322 maxpll = maxpll ? maxpll : GETBIOS16(sc, ptr + 32); 1323 /* 1324 * ATOM BIOS doesn't supply a reference divider, so we 1325 * have to probe for it. 1326 */ 1327 if (refdiv < 2) 1328 refdiv = GETPLL(sc, RADEON_PPLL_REF_DIV) & 1329 RADEON_PPLL_REF_DIV_MASK; 1330 /* 1331 * if probe is zero, just assume one that should work 1332 * for most parts 1333 */ 1334 if (refdiv < 2) 1335 refdiv = 12; 1336 1337 } else { 1338 /* Legacy BIOS */ 1339 ptr = GETBIOS16(sc, 0x48); 1340 ptr = GETBIOS16(sc, ptr + 0x30); 1341 refclk = refclk ? refclk : GETBIOS16(sc, ptr + 0x0E); 1342 refdiv = refdiv ? refdiv : GETBIOS16(sc, ptr + 0x10); 1343 minpll = minpll ? minpll : GETBIOS32(sc, ptr + 0x12); 1344 maxpll = maxpll ? maxpll : GETBIOS32(sc, ptr + 0x16); 1345 } 1346 1347 1348 dontprobe: 1349 sc->sc_refclk = refclk * 10; 1350 sc->sc_refdiv = refdiv; 1351 sc->sc_minpll = minpll * 10; 1352 sc->sc_maxpll = maxpll * 10; 1353 return 0; 1354 } 1355 1356 int 1357 radeonfb_calc_dividers(struct radeonfb_softc *sc, uint32_t dotclock, 1358 uint32_t *postdivbit, uint32_t *feedbackdiv) 1359 { 1360 int i; 1361 uint32_t outfreq; 1362 int div; 1363 1364 DPRINTF(("dot clock: %u\n", dotclock)); 1365 for (i = 0; (div = radeonfb_dividers[i].divider) != 0; i++) { 1366 outfreq = div * dotclock; 1367 if ((outfreq >= sc->sc_minpll) && 1368 (outfreq <= sc->sc_maxpll)) { 1369 DPRINTF(("outfreq: %u\n", outfreq)); 1370 *postdivbit = 1371 ((uint32_t)radeonfb_dividers[i].mask << 16); 1372 DPRINTF(("post divider: %d (mask %x)\n", div, 1373 *postdivbit)); 1374 break; 1375 } 1376 } 1377 1378 if (div == 0) 1379 return 1; 1380 1381 *feedbackdiv = DIVIDE(sc->sc_refdiv * outfreq, sc->sc_refclk); 1382 DPRINTF(("feedback divider: %d\n", *feedbackdiv)); 1383 return 0; 1384 } 1385 1386 #if 0 1387 #ifdef RADEON_DEBUG 1388 static void 1389 dump_buffer(const char *pfx, void *buffer, unsigned int size) 1390 { 1391 char asc[17]; 1392 unsigned ptr = (unsigned)buffer; 1393 char *start = (char *)(ptr & ~0xf); 1394 char *end = (char *)(ptr + size); 1395 1396 end = (char *)(((unsigned)end + 0xf) & ~0xf); 1397 1398 if (pfx == NULL) { 1399 pfx = ""; 1400 } 1401 1402 while (start < end) { 1403 unsigned offset = (unsigned)start & 0xf; 1404 if (offset == 0) { 1405 printf("%s%x: ", pfx, (unsigned)start); 1406 } 1407 if (((unsigned)start < ptr) || 1408 ((unsigned)start >= (ptr + size))) { 1409 printf(" "); 1410 asc[offset] = ' '; 1411 } else { 1412 printf("%02x", *(unsigned char *)start); 1413 if ((*start >= ' ') && (*start <= '~')) { 1414 asc[offset] = *start; 1415 } else { 1416 asc[offset] = '.'; 1417 } 1418 } 1419 asc[offset + 1] = 0; 1420 if (offset % 2) { 1421 printf(" "); 1422 } 1423 if (offset == 15) { 1424 printf(" %s\n", asc); 1425 } 1426 start++; 1427 } 1428 } 1429 #endif 1430 #endif 1431 1432 int 1433 radeonfb_getconnectors(struct radeonfb_softc *sc) 1434 { 1435 int i; 1436 int found = 0; 1437 1438 for (i = 0; i < 2; i++) { 1439 sc->sc_ports[i].rp_mon_type = RADEON_MT_UNKNOWN; 1440 sc->sc_ports[i].rp_ddc_type = RADEON_DDC_NONE; 1441 sc->sc_ports[i].rp_dac_type = RADEON_DAC_UNKNOWN; 1442 sc->sc_ports[i].rp_conn_type = RADEON_CONN_NONE; 1443 sc->sc_ports[i].rp_tmds_type = RADEON_TMDS_UNKNOWN; 1444 } 1445 1446 /* 1447 * This logic is borrowed from Xorg's radeon driver. 1448 */ 1449 if (!sc->sc_biossz) 1450 goto nobios; 1451 1452 if (IS_ATOM(sc)) { 1453 /* not done yet */ 1454 } else { 1455 uint16_t ptr; 1456 int port = 0; 1457 1458 ptr = GETBIOS16(sc, 0x48); 1459 ptr = GETBIOS16(sc, ptr + 0x50); 1460 for (i = 1; i < 4; i++) { 1461 uint16_t entry; 1462 uint8_t conn, ddc, dac, tmds; 1463 1464 /* 1465 * Parse the connector table. From reading the code, 1466 * it appears to made up of 16-bit entries for each 1467 * connector. The 16-bits are defined as: 1468 * 1469 * bits 12-15 - connector type (0 == end of table) 1470 * bits 8-11 - DDC type 1471 * bits 5-7 - ??? 1472 * bit 4 - TMDS type (1 = EXT, 0 = INT) 1473 * bits 1-3 - ??? 1474 * bit 0 - DAC, 1 = TVDAC, 0 = primary 1475 */ 1476 if (!GETBIOS8(sc, ptr + i * 2) && i > 1) 1477 break; 1478 entry = GETBIOS16(sc, ptr + i * 2); 1479 1480 conn = (entry >> 12) & 0xf; 1481 ddc = (entry >> 8) & 0xf; 1482 dac = (entry & 0x1) ? RADEON_DAC_TVDAC : 1483 RADEON_DAC_PRIMARY; 1484 tmds = ((entry >> 4) & 0x1) ? RADEON_TMDS_EXT : 1485 RADEON_TMDS_INT; 1486 1487 if (conn == RADEON_CONN_NONE) 1488 continue; /* no connector */ 1489 1490 if ((found > 0) && 1491 (sc->sc_ports[port].rp_ddc_type == ddc)) { 1492 /* duplicate entry for same connector */ 1493 continue; 1494 } 1495 1496 /* internal DDC_DVI port gets priority */ 1497 if ((ddc == RADEON_DDC_DVI) || (port == 1)) 1498 port = 0; 1499 else 1500 port = 1; 1501 1502 sc->sc_ports[port].rp_ddc_type = 1503 ddc > RADEON_DDC_CRT2 ? RADEON_DDC_NONE : ddc; 1504 sc->sc_ports[port].rp_dac_type = dac; 1505 sc->sc_ports[port].rp_conn_type = 1506 min(conn, RADEON_CONN_UNSUPPORTED) ; 1507 1508 sc->sc_ports[port].rp_tmds_type = tmds; 1509 1510 if ((conn != RADEON_CONN_DVI_I) && 1511 (conn != RADEON_CONN_DVI_D) && 1512 (tmds == RADEON_TMDS_INT)) 1513 sc->sc_ports[port].rp_tmds_type = 1514 RADEON_TMDS_UNKNOWN; 1515 1516 found += (port + 1); 1517 } 1518 } 1519 1520 nobios: 1521 if (!found) { 1522 DPRINTF(("No connector info in BIOS!\n")); 1523 /* default, port 0 = internal TMDS, port 1 = CRT */ 1524 sc->sc_ports[0].rp_mon_type = RADEON_MT_UNKNOWN; 1525 sc->sc_ports[0].rp_ddc_type = RADEON_DDC_DVI; 1526 sc->sc_ports[0].rp_dac_type = RADEON_DAC_TVDAC; 1527 sc->sc_ports[0].rp_conn_type = RADEON_CONN_DVI_D; 1528 sc->sc_ports[0].rp_tmds_type = RADEON_TMDS_INT; 1529 1530 sc->sc_ports[1].rp_mon_type = RADEON_MT_UNKNOWN; 1531 sc->sc_ports[1].rp_ddc_type = RADEON_DDC_VGA; 1532 sc->sc_ports[1].rp_dac_type = RADEON_DAC_PRIMARY; 1533 sc->sc_ports[1].rp_conn_type = RADEON_CONN_CRT; 1534 sc->sc_ports[1].rp_tmds_type = RADEON_TMDS_EXT; 1535 } 1536 1537 /* 1538 * Fixup for RS300/RS350/RS400 chips, that lack a primary DAC. 1539 * these chips should use TVDAC for the VGA port. 1540 */ 1541 if (HAS_SDAC(sc)) { 1542 if (sc->sc_ports[0].rp_conn_type == RADEON_CONN_CRT) { 1543 sc->sc_ports[0].rp_dac_type = RADEON_DAC_TVDAC; 1544 sc->sc_ports[1].rp_dac_type = RADEON_DAC_PRIMARY; 1545 } else { 1546 sc->sc_ports[1].rp_dac_type = RADEON_DAC_TVDAC; 1547 sc->sc_ports[0].rp_dac_type = RADEON_DAC_PRIMARY; 1548 } 1549 } else if (!HAS_CRTC2(sc)) { 1550 sc->sc_ports[0].rp_dac_type = RADEON_DAC_PRIMARY; 1551 } 1552 1553 for (i = 0; i < 2; i++) { 1554 char edid[128]; 1555 uint8_t ddc; 1556 struct edid_info *eip = &sc->sc_ports[i].rp_edid; 1557 prop_data_t edid_data; 1558 1559 DPRINTF(("Port #%d:\n", i)); 1560 DPRINTF((" conn = %d\n", sc->sc_ports[i].rp_conn_type)); 1561 DPRINTF((" ddc = %d\n", sc->sc_ports[i].rp_ddc_type)); 1562 DPRINTF((" dac = %d\n", sc->sc_ports[i].rp_dac_type)); 1563 DPRINTF((" tmds = %d\n", sc->sc_ports[i].rp_tmds_type)); 1564 1565 sc->sc_ports[i].rp_edid_valid = 0; 1566 /* first look for static EDID data */ 1567 if ((edid_data = prop_dictionary_get(device_properties( 1568 &sc->sc_dev), "EDID")) != NULL) { 1569 1570 aprint_normal("%s: using static EDID\n", 1571 sc->sc_dev.dv_xname); 1572 memcpy(edid, prop_data_data_nocopy(edid_data), 128); 1573 if (edid_parse(edid, eip) == 0) { 1574 1575 sc->sc_ports[i].rp_edid_valid = 1; 1576 edid_print(eip); 1577 } 1578 } 1579 /* if we didn't find any we'll try to talk to the monitor */ 1580 if (sc->sc_ports[i].rp_edid_valid != 1) { 1581 1582 ddc = sc->sc_ports[i].rp_ddc_type; 1583 if (ddc != RADEON_DDC_NONE) { 1584 if ((radeonfb_i2c_read_edid(sc, ddc, edid) 1585 == 0) && (edid_parse(edid, eip) == 0)) { 1586 1587 sc->sc_ports[i].rp_edid_valid = 1; 1588 edid_print(eip); 1589 } 1590 } 1591 } 1592 } 1593 1594 return found; 1595 } 1596 1597 int 1598 radeonfb_gettmds(struct radeonfb_softc *sc) 1599 { 1600 int i; 1601 1602 if (!sc->sc_biossz) { 1603 goto nobios; 1604 } 1605 1606 if (IS_ATOM(sc)) { 1607 /* XXX: not done yet */ 1608 } else { 1609 uint16_t ptr; 1610 int n; 1611 1612 ptr = GETBIOS16(sc, 0x48); 1613 ptr = GETBIOS16(sc, ptr + 0x34); 1614 DPRINTF(("DFP table revision %d\n", GETBIOS8(sc, ptr))); 1615 if (GETBIOS8(sc, ptr) == 3) { 1616 /* revision three table */ 1617 n = GETBIOS8(sc, ptr + 5) + 1; 1618 n = min(n, 4); 1619 1620 memset(sc->sc_tmds_pll, 0, sizeof (sc->sc_tmds_pll)); 1621 for (i = 0; i < n; i++) { 1622 sc->sc_tmds_pll[i].rtp_pll = GETBIOS32(sc, 1623 ptr + i * 10 + 8); 1624 sc->sc_tmds_pll[i].rtp_freq = GETBIOS16(sc, 1625 ptr + i * 10 + 0x10); 1626 DPRINTF(("TMDS_PLL dot clock %d pll %x\n", 1627 sc->sc_tmds_pll[i].rtp_freq, 1628 sc->sc_tmds_pll[i].rtp_pll)); 1629 } 1630 return 0; 1631 } 1632 } 1633 1634 nobios: 1635 DPRINTF(("no suitable DFP table present\n")); 1636 for (i = 0; 1637 i < sizeof (radeonfb_tmds_pll) / sizeof (radeonfb_tmds_pll[0]); 1638 i++) { 1639 int j; 1640 1641 if (radeonfb_tmds_pll[i].family != sc->sc_family) 1642 continue; 1643 1644 for (j = 0; j < 4; j++) { 1645 sc->sc_tmds_pll[j] = radeonfb_tmds_pll[i].plls[j]; 1646 DPRINTF(("TMDS_PLL dot clock %d pll %x\n", 1647 sc->sc_tmds_pll[j].rtp_freq, 1648 sc->sc_tmds_pll[j].rtp_pll)); 1649 } 1650 return 0; 1651 } 1652 1653 return -1; 1654 } 1655 1656 const struct videomode * 1657 radeonfb_modelookup(const char *name) 1658 { 1659 int i; 1660 1661 for (i = 0; i < videomode_count; i++) 1662 if (!strcmp(name, videomode_list[i].name)) 1663 return &videomode_list[i]; 1664 1665 return NULL; 1666 } 1667 1668 void 1669 radeonfb_pllwriteupdate(struct radeonfb_softc *sc, int crtc) 1670 { 1671 if (crtc) { 1672 while (GETPLL(sc, RADEON_P2PLL_REF_DIV) & 1673 RADEON_P2PLL_ATOMIC_UPDATE_R); 1674 SETPLL(sc, RADEON_P2PLL_REF_DIV, RADEON_P2PLL_ATOMIC_UPDATE_W); 1675 } else { 1676 while (GETPLL(sc, RADEON_PPLL_REF_DIV) & 1677 RADEON_PPLL_ATOMIC_UPDATE_R); 1678 SETPLL(sc, RADEON_PPLL_REF_DIV, RADEON_PPLL_ATOMIC_UPDATE_W); 1679 } 1680 } 1681 1682 void 1683 radeonfb_pllwaitatomicread(struct radeonfb_softc *sc, int crtc) 1684 { 1685 int i; 1686 1687 for (i = 10000; i; i--) { 1688 if (crtc) { 1689 if (GETPLL(sc, RADEON_P2PLL_REF_DIV) & 1690 RADEON_P2PLL_ATOMIC_UPDATE_R) 1691 break; 1692 } else { 1693 if (GETPLL(sc, RADEON_PPLL_REF_DIV) & 1694 RADEON_PPLL_ATOMIC_UPDATE_R) 1695 break; 1696 } 1697 } 1698 } 1699 1700 void 1701 radeonfb_program_vclk(struct radeonfb_softc *sc, int dotclock, int crtc) 1702 { 1703 uint32_t pbit = 0; 1704 uint32_t feed = 0; 1705 uint32_t data; 1706 #if 1 1707 int i; 1708 #endif 1709 1710 radeonfb_calc_dividers(sc, dotclock, &pbit, &feed); 1711 1712 if (crtc == 0) { 1713 1714 /* XXXX: mobility workaround missing */ 1715 /* XXXX: R300 stuff missing */ 1716 1717 PATCHPLL(sc, RADEON_VCLK_ECP_CNTL, 1718 RADEON_VCLK_SRC_SEL_CPUCLK, 1719 ~RADEON_VCLK_SRC_SEL_MASK); 1720 1721 /* put vclk into reset, use atomic updates */ 1722 SETPLL(sc, RADEON_PPLL_CNTL, 1723 RADEON_PPLL_REFCLK_SEL | 1724 RADEON_PPLL_FBCLK_SEL | 1725 RADEON_PPLL_RESET | 1726 RADEON_PPLL_ATOMIC_UPDATE_EN | 1727 RADEON_PPLL_VGA_ATOMIC_UPDATE_EN); 1728 1729 /* select clock 3 */ 1730 #if 0 1731 PATCH32(sc, RADEON_CLOCK_CNTL_INDEX, RADEON_PLL_DIV_SEL, 1732 ~RADEON_PLL_DIV_SEL); 1733 #else 1734 PATCH32(sc, RADEON_CLOCK_CNTL_INDEX, 0, 1735 ~RADEON_PLL_DIV_SEL); 1736 #endif 1737 1738 /* XXX: R300 family -- program divider differently? */ 1739 1740 /* program reference divider */ 1741 PATCHPLL(sc, RADEON_PPLL_REF_DIV, sc->sc_refdiv, 1742 ~RADEON_PPLL_REF_DIV_MASK); 1743 PRINTPLL(RADEON_PPLL_REF_DIV); 1744 1745 #if 0 1746 data = GETPLL(sc, RADEON_PPLL_DIV_3); 1747 data &= ~(RADEON_PPLL_FB3_DIV_MASK | 1748 RADEON_PPLL_POST3_DIV_MASK); 1749 data |= pbit; 1750 data |= (feed & RADEON_PPLL_FB3_DIV_MASK); 1751 PUTPLL(sc, RADEON_PPLL_DIV_3, data); 1752 #else 1753 for (i = 0; i < 4; i++) { 1754 } 1755 #endif 1756 1757 /* use the atomic update */ 1758 radeonfb_pllwriteupdate(sc, crtc); 1759 1760 /* and wait for it to complete */ 1761 radeonfb_pllwaitatomicread(sc, crtc); 1762 1763 /* program HTOTAL (why?) */ 1764 PUTPLL(sc, RADEON_HTOTAL_CNTL, 0); 1765 1766 /* drop reset */ 1767 CLRPLL(sc, RADEON_PPLL_CNTL, 1768 RADEON_PPLL_RESET | RADEON_PPLL_SLEEP | 1769 RADEON_PPLL_ATOMIC_UPDATE_EN | 1770 RADEON_PPLL_VGA_ATOMIC_UPDATE_EN); 1771 1772 PRINTPLL(RADEON_PPLL_CNTL); 1773 1774 /* give clock time to lock */ 1775 delay(50000); 1776 1777 PATCHPLL(sc, RADEON_VCLK_ECP_CNTL, 1778 RADEON_VCLK_SRC_SEL_PPLLCLK, 1779 ~RADEON_VCLK_SRC_SEL_MASK); 1780 1781 } else { 1782 1783 PATCHPLL(sc, RADEON_PIXCLKS_CNTL, 1784 RADEON_PIX2CLK_SRC_SEL_CPUCLK, 1785 ~RADEON_PIX2CLK_SRC_SEL_MASK); 1786 1787 /* put vclk into reset, use atomic updates */ 1788 SETPLL(sc, RADEON_P2PLL_CNTL, 1789 RADEON_P2PLL_RESET | 1790 RADEON_P2PLL_ATOMIC_UPDATE_EN | 1791 RADEON_P2PLL_VGA_ATOMIC_UPDATE_EN); 1792 1793 /* XXX: R300 family -- program divider differently? */ 1794 1795 /* program reference divider */ 1796 PATCHPLL(sc, RADEON_P2PLL_REF_DIV, sc->sc_refdiv, 1797 ~RADEON_P2PLL_REF_DIV_MASK); 1798 1799 /* program feedback and post dividers */ 1800 data = GETPLL(sc, RADEON_P2PLL_DIV_0); 1801 data &= ~(RADEON_P2PLL_FB0_DIV_MASK | 1802 RADEON_P2PLL_POST0_DIV_MASK); 1803 data |= pbit; 1804 data |= (feed & RADEON_P2PLL_FB0_DIV_MASK); 1805 PUTPLL(sc, RADEON_P2PLL_DIV_0, data); 1806 1807 /* use the atomic update */ 1808 radeonfb_pllwriteupdate(sc, crtc); 1809 1810 /* and wait for it to complete */ 1811 radeonfb_pllwaitatomicread(sc, crtc); 1812 1813 /* program HTOTAL (why?) */ 1814 PUTPLL(sc, RADEON_HTOTAL2_CNTL, 0); 1815 1816 /* drop reset */ 1817 CLRPLL(sc, RADEON_P2PLL_CNTL, 1818 RADEON_P2PLL_RESET | RADEON_P2PLL_SLEEP | 1819 RADEON_P2PLL_ATOMIC_UPDATE_EN | 1820 RADEON_P2PLL_VGA_ATOMIC_UPDATE_EN); 1821 1822 /* allow time for clock to lock */ 1823 delay(50000); 1824 1825 PATCHPLL(sc, RADEON_PIXCLKS_CNTL, 1826 RADEON_PIX2CLK_SRC_SEL_P2PLLCLK, 1827 ~RADEON_PIX2CLK_SRC_SEL_MASK); 1828 } 1829 PRINTREG(RADEON_CRTC_MORE_CNTL); 1830 } 1831 1832 void 1833 radeonfb_modeswitch(struct radeonfb_display *dp) 1834 { 1835 struct radeonfb_softc *sc = dp->rd_softc; 1836 int i; 1837 1838 /* blank the display while we switch modes */ 1839 //radeonfb_blank(dp, 1); 1840 1841 #if 0 1842 SET32(sc, RADEON_CRTC_EXT_CNTL, 1843 RADEON_CRTC_VSYNC_DIS | RADEON_CRTC_HSYNC_DIS | 1844 RADEON_CRTC_DISPLAY_DIS /* | RADEON_CRTC_DISP_REQ_EN_B */); 1845 #endif 1846 1847 /* these registers might get in the way... */ 1848 PUT32(sc, RADEON_OVR_CLR, 0); 1849 PUT32(sc, RADEON_OVR_WID_LEFT_RIGHT, 0); 1850 PUT32(sc, RADEON_OVR_WID_TOP_BOTTOM, 0); 1851 PUT32(sc, RADEON_OV0_SCALE_CNTL, 0); 1852 PUT32(sc, RADEON_SUBPIC_CNTL, 0); 1853 PUT32(sc, RADEON_VIPH_CONTROL, 0); 1854 PUT32(sc, RADEON_I2C_CNTL_1, 0); 1855 PUT32(sc, RADEON_GEN_INT_CNTL, 0); 1856 PUT32(sc, RADEON_CAP0_TRIG_CNTL, 0); 1857 PUT32(sc, RADEON_CAP1_TRIG_CNTL, 0); 1858 PUT32(sc, RADEON_SURFACE_CNTL, 0); 1859 1860 for (i = 0; i < dp->rd_ncrtcs; i++) 1861 radeonfb_setcrtc(dp, i); 1862 1863 /* activate the display */ 1864 //radeonfb_blank(dp, 0); 1865 } 1866 1867 void 1868 radeonfb_setcrtc(struct radeonfb_display *dp, int index) 1869 { 1870 int crtc; 1871 struct videomode *mode; 1872 struct radeonfb_softc *sc; 1873 struct radeonfb_crtc *cp; 1874 uint32_t v; 1875 uint32_t gencntl; 1876 uint32_t htotaldisp; 1877 uint32_t hsyncstrt; 1878 uint32_t vtotaldisp; 1879 uint32_t vsyncstrt; 1880 uint32_t fphsyncstrt; 1881 uint32_t fpvsyncstrt; 1882 uint32_t fphtotaldisp; 1883 uint32_t fpvtotaldisp; 1884 uint32_t pitch; 1885 1886 sc = dp->rd_softc; 1887 cp = &dp->rd_crtcs[index]; 1888 crtc = cp->rc_number; 1889 mode = &cp->rc_videomode; 1890 1891 #if 1 1892 pitch = (((dp->rd_virtx * dp->rd_bpp) + ((dp->rd_bpp * 8) - 1)) / 1893 (dp->rd_bpp * 8)); 1894 #else 1895 pitch = (((sc->sc_maxx * sc->sc_maxbpp) + ((sc->sc_maxbpp * 8) - 1)) / 1896 (sc->sc_maxbpp * 8)); 1897 #endif 1898 //pitch = pitch | (pitch << 16); 1899 1900 switch (crtc) { 1901 case 0: 1902 gencntl = RADEON_CRTC_GEN_CNTL; 1903 htotaldisp = RADEON_CRTC_H_TOTAL_DISP; 1904 hsyncstrt = RADEON_CRTC_H_SYNC_STRT_WID; 1905 vtotaldisp = RADEON_CRTC_V_TOTAL_DISP; 1906 vsyncstrt = RADEON_CRTC_V_SYNC_STRT_WID; 1907 fpvsyncstrt = RADEON_FP_V_SYNC_STRT_WID; 1908 fphsyncstrt = RADEON_FP_H_SYNC_STRT_WID; 1909 fpvtotaldisp = RADEON_FP_CRTC_V_TOTAL_DISP; 1910 fphtotaldisp = RADEON_FP_CRTC_H_TOTAL_DISP; 1911 break; 1912 case 1: 1913 gencntl = RADEON_CRTC2_GEN_CNTL; 1914 htotaldisp = RADEON_CRTC2_H_TOTAL_DISP; 1915 hsyncstrt = RADEON_CRTC2_H_SYNC_STRT_WID; 1916 vtotaldisp = RADEON_CRTC2_V_TOTAL_DISP; 1917 vsyncstrt = RADEON_CRTC2_V_SYNC_STRT_WID; 1918 fpvsyncstrt = RADEON_FP_V2_SYNC_STRT_WID; 1919 fphsyncstrt = RADEON_FP_H2_SYNC_STRT_WID; 1920 fpvtotaldisp = RADEON_FP_CRTC2_V_TOTAL_DISP; 1921 fphtotaldisp = RADEON_FP_CRTC2_H_TOTAL_DISP; 1922 break; 1923 default: 1924 panic("Bad CRTC!"); 1925 break; 1926 } 1927 1928 /* 1929 * CRTC_GEN_CNTL - depth, accelerator mode, etc. 1930 */ 1931 /* only bother with 32bpp and 8bpp */ 1932 v = dp->rd_format << RADEON_CRTC_PIX_WIDTH_SHIFT; 1933 1934 if (crtc == 1) { 1935 v |= RADEON_CRTC2_CRT2_ON | RADEON_CRTC2_EN; 1936 } else { 1937 v |= RADEON_CRTC_EXT_DISP_EN | RADEON_CRTC_EN; 1938 } 1939 1940 if (mode->flags & VID_DBLSCAN) 1941 v |= RADEON_CRTC2_DBL_SCAN_EN; 1942 1943 if (mode->flags & VID_INTERLACE) 1944 v |= RADEON_CRTC2_INTERLACE_EN; 1945 1946 if (mode->flags & VID_CSYNC) { 1947 v |= RADEON_CRTC2_CSYNC_EN; 1948 if (crtc == 1) 1949 v |= RADEON_CRTC2_VSYNC_TRISTAT; 1950 } 1951 1952 PUT32(sc, gencntl, v); 1953 DPRINTF(("CRTC%s_GEN_CNTL = %08x\n", crtc ? "2" : "", v)); 1954 1955 /* 1956 * CRTC_EXT_CNTL - preserve disable flags, set ATI linear and EXT_CNT 1957 */ 1958 v = GET32(sc, RADEON_CRTC_EXT_CNTL); 1959 if (crtc == 0) { 1960 v &= (RADEON_CRTC_VSYNC_DIS | RADEON_CRTC_HSYNC_DIS | 1961 RADEON_CRTC_DISPLAY_DIS); 1962 v |= RADEON_XCRT_CNT_EN | RADEON_VGA_ATI_LINEAR; 1963 if (mode->flags & VID_CSYNC) 1964 v |= RADEON_CRTC_VSYNC_TRISTAT; 1965 } 1966 /* unconditional turn on CRT, in case first CRTC is DFP */ 1967 v |= RADEON_CRTC_CRT_ON; 1968 PUT32(sc, RADEON_CRTC_EXT_CNTL, v); 1969 PRINTREG(RADEON_CRTC_EXT_CNTL); 1970 1971 /* 1972 * H_TOTAL_DISP 1973 */ 1974 v = ((mode->hdisplay / 8) - 1) << 16; 1975 v |= (mode->htotal / 8) - 1; 1976 PUT32(sc, htotaldisp, v); 1977 DPRINTF(("CRTC%s_H_TOTAL_DISP = %08x\n", crtc ? "2" : "", v)); 1978 PUT32(sc, fphtotaldisp, v); 1979 DPRINTF(("FP_H%s_TOTAL_DISP = %08x\n", crtc ? "2" : "", v)); 1980 1981 /* 1982 * H_SYNC_STRT_WID 1983 */ 1984 v = (((mode->hsync_end - mode->hsync_start) / 8) << 16); 1985 v |= mode->hsync_start; 1986 if (mode->flags & VID_NHSYNC) 1987 v |= RADEON_CRTC_H_SYNC_POL; 1988 PUT32(sc, hsyncstrt, v); 1989 DPRINTF(("CRTC%s_H_SYNC_STRT_WID = %08x\n", crtc ? "2" : "", v)); 1990 PUT32(sc, fphsyncstrt, v); 1991 DPRINTF(("FP_H%s_SYNC_STRT_WID = %08x\n", crtc ? "2" : "", v)); 1992 1993 /* 1994 * V_TOTAL_DISP 1995 */ 1996 v = ((mode->vdisplay - 1) << 16); 1997 v |= (mode->vtotal - 1); 1998 PUT32(sc, vtotaldisp, v); 1999 DPRINTF(("CRTC%s_V_TOTAL_DISP = %08x\n", crtc ? "2" : "", v)); 2000 PUT32(sc, fpvtotaldisp, v); 2001 DPRINTF(("FP_V%s_TOTAL_DISP = %08x\n", crtc ? "2" : "", v)); 2002 2003 /* 2004 * V_SYNC_STRT_WID 2005 */ 2006 v = ((mode->vsync_end - mode->vsync_start) << 16); 2007 v |= (mode->vsync_start - 1); 2008 if (mode->flags & VID_NVSYNC) 2009 v |= RADEON_CRTC_V_SYNC_POL; 2010 PUT32(sc, vsyncstrt, v); 2011 DPRINTF(("CRTC%s_V_SYNC_STRT_WID = %08x\n", crtc ? "2" : "", v)); 2012 PUT32(sc, fpvsyncstrt, v); 2013 DPRINTF(("FP_V%s_SYNC_STRT_WID = %08x\n", crtc ? "2" : "", v)); 2014 2015 radeonfb_program_vclk(sc, mode->dot_clock, crtc); 2016 2017 switch (crtc) { 2018 case 0: 2019 PUT32(sc, RADEON_CRTC_OFFSET, 0); 2020 PUT32(sc, RADEON_CRTC_OFFSET_CNTL, 0); 2021 PUT32(sc, RADEON_CRTC_PITCH, pitch); 2022 CLR32(sc, RADEON_DISP_MERGE_CNTL, RADEON_DISP_RGB_OFFSET_EN); 2023 2024 CLR32(sc, RADEON_CRTC_EXT_CNTL, 2025 RADEON_CRTC_VSYNC_DIS | RADEON_CRTC_HSYNC_DIS | 2026 RADEON_CRTC_DISPLAY_DIS /* | RADEON_CRTC_DISP_REQ_EN_B */); 2027 CLR32(sc, RADEON_CRTC_GEN_CNTL, RADEON_CRTC_DISP_REQ_EN_B); 2028 PRINTREG(RADEON_CRTC_EXT_CNTL); 2029 PRINTREG(RADEON_CRTC_GEN_CNTL); 2030 PRINTREG(RADEON_CLOCK_CNTL_INDEX); 2031 break; 2032 2033 case 1: 2034 PUT32(sc, RADEON_CRTC2_OFFSET, 0); 2035 PUT32(sc, RADEON_CRTC2_OFFSET_CNTL, 0); 2036 PUT32(sc, RADEON_CRTC2_PITCH, pitch); 2037 CLR32(sc, RADEON_DISP2_MERGE_CNTL, RADEON_DISP2_RGB_OFFSET_EN); 2038 CLR32(sc, RADEON_CRTC2_GEN_CNTL, 2039 RADEON_CRTC2_VSYNC_DIS | 2040 RADEON_CRTC2_HSYNC_DIS | 2041 RADEON_CRTC2_DISP_DIS | RADEON_CRTC2_DISP_REQ_EN_B); 2042 PRINTREG(RADEON_CRTC2_GEN_CNTL); 2043 break; 2044 } 2045 } 2046 2047 int 2048 radeonfb_isblank(struct radeonfb_display *dp) 2049 { 2050 uint32_t reg, mask; 2051 2052 if (dp->rd_crtcs[0].rc_number) { 2053 reg = RADEON_CRTC2_GEN_CNTL; 2054 mask = RADEON_CRTC2_DISP_DIS; 2055 } else { 2056 reg = RADEON_CRTC_EXT_CNTL; 2057 mask = RADEON_CRTC_DISPLAY_DIS; 2058 } 2059 return ((GET32(dp->rd_softc, reg) & mask) ? 1 : 0); 2060 } 2061 2062 void 2063 radeonfb_blank(struct radeonfb_display *dp, int blank) 2064 { 2065 struct radeonfb_softc *sc = dp->rd_softc; 2066 uint32_t reg, mask; 2067 uint32_t fpreg, fpval; 2068 int i; 2069 2070 for (i = 0; i < dp->rd_ncrtcs; i++) { 2071 2072 if (dp->rd_crtcs[i].rc_number) { 2073 reg = RADEON_CRTC2_GEN_CNTL; 2074 mask = RADEON_CRTC2_DISP_DIS; 2075 fpreg = RADEON_FP2_GEN_CNTL; 2076 fpval = RADEON_FP2_ON; 2077 } else { 2078 reg = RADEON_CRTC_EXT_CNTL; 2079 mask = RADEON_CRTC_DISPLAY_DIS; 2080 fpreg = RADEON_FP_GEN_CNTL; 2081 fpval = RADEON_FP_FPON; 2082 } 2083 2084 if (blank) { 2085 SET32(sc, reg, mask); 2086 CLR32(sc, fpreg, fpval); 2087 } else { 2088 CLR32(sc, reg, mask); 2089 SET32(sc, fpreg, fpval); 2090 } 2091 } 2092 PRINTREG(RADEON_FP_GEN_CNTL); 2093 PRINTREG(RADEON_FP2_GEN_CNTL); 2094 } 2095 2096 void 2097 radeonfb_init_screen(void *cookie, struct vcons_screen *scr, int existing, 2098 long *defattr) 2099 { 2100 struct radeonfb_display *dp = cookie; 2101 struct rasops_info *ri = &scr->scr_ri; 2102 2103 /* initialize font subsystem */ 2104 wsfont_init(); 2105 2106 DPRINTF(("init screen called, existing %d\n", existing)); 2107 2108 ri->ri_depth = dp->rd_bpp; 2109 ri->ri_width = dp->rd_virtx; 2110 ri->ri_height = dp->rd_virty; 2111 ri->ri_stride = dp->rd_stride; 2112 ri->ri_flg = RI_CENTER; 2113 ri->ri_bits = (void *)dp->rd_fbptr; 2114 2115 /* XXX: 32 bpp only */ 2116 /* this is rgb in "big-endian order..." */ 2117 ri->ri_rnum = 8; 2118 ri->ri_gnum = 8; 2119 ri->ri_bnum = 8; 2120 ri->ri_rpos = 16; 2121 ri->ri_gpos = 8; 2122 ri->ri_bpos = 0; 2123 2124 if (existing) { 2125 ri->ri_flg |= RI_CLEAR; 2126 2127 /* start a modeswitch now */ 2128 radeonfb_modeswitch(dp); 2129 } 2130 2131 /* 2132 * XXX: font selection should be based on properties, with some 2133 * normal/reasonable default. 2134 */ 2135 ri->ri_caps = WSSCREEN_WSCOLORS; 2136 2137 /* initialize and look for an initial font */ 2138 rasops_init(ri, dp->rd_virty/8, dp->rd_virtx/8); 2139 2140 rasops_reconfig(ri, dp->rd_virty / ri->ri_font->fontheight, 2141 dp->rd_virtx / ri->ri_font->fontwidth); 2142 2143 /* enable acceleration */ 2144 ri->ri_ops.copyrows = radeonfb_copyrows; 2145 ri->ri_ops.copycols = radeonfb_copycols; 2146 ri->ri_ops.eraserows = radeonfb_eraserows; 2147 ri->ri_ops.erasecols = radeonfb_erasecols; 2148 ri->ri_ops.allocattr = radeonfb_allocattr; 2149 if (!IS_R300(dp->rd_softc)) { 2150 ri->ri_ops.putchar = radeonfb_putchar; 2151 } 2152 ri->ri_ops.cursor = radeonfb_cursor; 2153 } 2154 2155 void 2156 radeonfb_set_fbloc(struct radeonfb_softc *sc) 2157 { 2158 uint32_t gen, ext, gen2 = 0; 2159 uint32_t agploc, aperbase, apersize, mcfbloc; 2160 2161 gen = GET32(sc, RADEON_CRTC_GEN_CNTL); 2162 ext = GET32(sc, RADEON_CRTC_EXT_CNTL); 2163 agploc = GET32(sc, RADEON_MC_AGP_LOCATION); 2164 aperbase = GET32(sc, RADEON_CONFIG_APER_0_BASE); 2165 apersize = GET32(sc, RADEON_CONFIG_APER_SIZE); 2166 2167 PUT32(sc, RADEON_CRTC_GEN_CNTL, gen | RADEON_CRTC_DISP_REQ_EN_B); 2168 PUT32(sc, RADEON_CRTC_EXT_CNTL, ext | RADEON_CRTC_DISPLAY_DIS); 2169 //PUT32(sc, RADEON_CRTC_GEN_CNTL, gen | RADEON_CRTC_DISPLAY_DIS); 2170 //PUT32(sc, RADEON_CRTC_EXT_CNTL, ext | RADEON_CRTC_DISP_REQ_EN_B); 2171 2172 if (HAS_CRTC2(sc)) { 2173 gen2 = GET32(sc, RADEON_CRTC2_GEN_CNTL); 2174 PUT32(sc, RADEON_CRTC2_GEN_CNTL, 2175 gen2 | RADEON_CRTC2_DISP_REQ_EN_B); 2176 } 2177 2178 delay(100000); 2179 2180 mcfbloc = (aperbase >> 16) | 2181 ((aperbase + (apersize - 1)) & 0xffff0000); 2182 2183 sc->sc_aperbase = (mcfbloc & 0xffff) << 16; 2184 sc->sc_memsz = apersize; 2185 2186 if (((agploc & 0xffff) << 16) != 2187 ((mcfbloc & 0xffff0000U) + 0x10000)) { 2188 agploc = mcfbloc & 0xffff0000U; 2189 agploc |= ((agploc + 0x10000) >> 16); 2190 } 2191 2192 PUT32(sc, RADEON_HOST_PATH_CNTL, 0); 2193 2194 PUT32(sc, RADEON_MC_FB_LOCATION, mcfbloc); 2195 PUT32(sc, RADEON_MC_AGP_LOCATION, agploc); 2196 2197 DPRINTF(("aperbase = %u\n", aperbase)); 2198 PRINTREG(RADEON_MC_FB_LOCATION); 2199 PRINTREG(RADEON_MC_AGP_LOCATION); 2200 2201 PUT32(sc, RADEON_DISPLAY_BASE_ADDR, sc->sc_aperbase); 2202 2203 if (HAS_CRTC2(sc)) 2204 PUT32(sc, RADEON_DISPLAY2_BASE_ADDR, sc->sc_aperbase); 2205 2206 PUT32(sc, RADEON_OV0_BASE_ADDR, sc->sc_aperbase); 2207 2208 #if 0 2209 /* XXX: what is this AGP garbage? :-) */ 2210 PUT32(sc, RADEON_AGP_CNTL, 0x00100000); 2211 #endif 2212 2213 delay(100000); 2214 2215 PUT32(sc, RADEON_CRTC_GEN_CNTL, gen); 2216 PUT32(sc, RADEON_CRTC_EXT_CNTL, ext); 2217 2218 if (HAS_CRTC2(sc)) 2219 PUT32(sc, RADEON_CRTC2_GEN_CNTL, gen2); 2220 } 2221 2222 void 2223 radeonfb_init_misc(struct radeonfb_softc *sc) 2224 { 2225 PUT32(sc, RADEON_BUS_CNTL, 2226 RADEON_BUS_MASTER_DIS | 2227 RADEON_BUS_PREFETCH_MODE_ACT | 2228 RADEON_BUS_PCI_READ_RETRY_EN | 2229 RADEON_BUS_PCI_WRT_RETRY_EN | 2230 (3 << RADEON_BUS_RETRY_WS_SHIFT) | 2231 RADEON_BUS_MSTR_RD_MULT | 2232 RADEON_BUS_MSTR_RD_LINE | 2233 RADEON_BUS_RD_DISCARD_EN | 2234 RADEON_BUS_MSTR_DISCONNECT_EN | 2235 RADEON_BUS_READ_BURST); 2236 2237 PUT32(sc, RADEON_BUS_CNTL1, 0xf0); 2238 /* PUT32(sc, RADEON_SEPROM_CNTL1, 0x09ff0000); */ 2239 PUT32(sc, RADEON_FCP_CNTL, RADEON_FCP0_SRC_GND); 2240 PUT32(sc, RADEON_RBBM_CNTL, 2241 (3 << RADEON_RB_SETTLE_SHIFT) | 2242 (4 << RADEON_ABORTCLKS_HI_SHIFT) | 2243 (4 << RADEON_ABORTCLKS_CP_SHIFT) | 2244 (4 << RADEON_ABORTCLKS_CFIFO_SHIFT)); 2245 2246 /* XXX: figure out what these mean! */ 2247 PUT32(sc, RADEON_AGP_CNTL, 0x00100000); 2248 PUT32(sc, RADEON_HOST_PATH_CNTL, 0); 2249 //PUT32(sc, RADEON_DISP_MISC_CNTL, 0x5bb00400); 2250 2251 PUT32(sc, RADEON_GEN_INT_CNTL, 0); 2252 PUT32(sc, RADEON_GEN_INT_STATUS, GET32(sc, RADEON_GEN_INT_STATUS)); 2253 } 2254 2255 /* 2256 * This loads a linear color map for true color. 2257 */ 2258 void 2259 radeonfb_init_palette(struct radeonfb_softc *sc, int crtc) 2260 { 2261 int i; 2262 uint32_t vclk; 2263 2264 #define DAC_WIDTH ((1 << 10) - 1) 2265 #define CLUT_WIDTH ((1 << 8) - 1) 2266 #define CLUT_COLOR(i) ((i * DAC_WIDTH * 2 / CLUT_WIDTH + 1) / 2) 2267 2268 vclk = GETPLL(sc, RADEON_VCLK_ECP_CNTL); 2269 PUTPLL(sc, RADEON_VCLK_ECP_CNTL, vclk & ~RADEON_PIXCLK_DAC_ALWAYS_ONb); 2270 2271 if (crtc) 2272 SET32(sc, RADEON_DAC_CNTL2, RADEON_DAC2_PALETTE_ACC_CTL); 2273 else 2274 CLR32(sc, RADEON_DAC_CNTL2, RADEON_DAC2_PALETTE_ACC_CTL); 2275 2276 PUT32(sc, RADEON_PALETTE_INDEX, 0); 2277 for (i = 0; i <= CLUT_WIDTH; ++i) { 2278 PUT32(sc, RADEON_PALETTE_30_DATA, 2279 (CLUT_COLOR(i) << 10) | 2280 (CLUT_COLOR(i) << 20) | 2281 (CLUT_COLOR(i))); 2282 } 2283 2284 CLR32(sc, RADEON_DAC_CNTL2, RADEON_DAC2_PALETTE_ACC_CTL); 2285 PRINTREG(RADEON_DAC_CNTL2); 2286 2287 PUTPLL(sc, RADEON_VCLK_ECP_CNTL, vclk); 2288 } 2289 2290 /* 2291 * Bugs in some R300 hardware requires this when accessing CLOCK_CNTL_INDEX. 2292 */ 2293 void 2294 radeonfb_r300cg_workaround(struct radeonfb_softc *sc) 2295 { 2296 uint32_t tmp, save; 2297 2298 save = GET32(sc, RADEON_CLOCK_CNTL_INDEX); 2299 tmp = save & ~(0x3f | RADEON_PLL_WR_EN); 2300 PUT32(sc, RADEON_CLOCK_CNTL_INDEX, tmp); 2301 tmp = GET32(sc, RADEON_CLOCK_CNTL_DATA); 2302 PUT32(sc, RADEON_CLOCK_CNTL_INDEX, save); 2303 } 2304 2305 /* 2306 * Acceleration entry points. 2307 */ 2308 static void 2309 radeonfb_putchar(void *cookie, int row, int col, u_int c, long attr) 2310 { 2311 struct rasops_info *ri = cookie; 2312 struct vcons_screen *scr = ri->ri_hw; 2313 struct radeonfb_display *dp = scr->scr_cookie; 2314 uint32_t x, y, w, h; 2315 uint32_t bg, fg; 2316 uint8_t *data; 2317 2318 if (dp->rd_wsmode != WSDISPLAYIO_MODE_EMUL) 2319 return; 2320 2321 if (!CHAR_IN_FONT(c, ri->ri_font)) 2322 return; 2323 2324 w = ri->ri_font->fontwidth; 2325 h = ri->ri_font->fontheight; 2326 2327 bg = ri->ri_devcmap[(attr >> 16) & 0xf]; 2328 fg = ri->ri_devcmap[(attr >> 24) & 0xf]; 2329 2330 x = ri->ri_xorigin + col * w; 2331 y = ri->ri_yorigin + row * h; 2332 2333 if (c == 0x20) { 2334 radeonfb_rectfill(dp, x, y, w, h, bg); 2335 } else { 2336 data = (uint8_t *)ri->ri_font->data + 2337 (c - ri->ri_font->firstchar) * ri->ri_fontscale; 2338 2339 radeonfb_setup_mono(dp, x, y, w, h, fg, bg); 2340 radeonfb_feed_bytes(dp, ri->ri_fontscale, data); 2341 } 2342 } 2343 2344 static void 2345 radeonfb_eraserows(void *cookie, int row, int nrows, long fillattr) 2346 { 2347 struct rasops_info *ri = cookie; 2348 struct vcons_screen *scr = ri->ri_hw; 2349 struct radeonfb_display *dp = scr->scr_cookie; 2350 uint32_t x, y, w, h, fg, bg, ul; 2351 2352 /* XXX: check for full emulation mode? */ 2353 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 2354 x = ri->ri_xorigin; 2355 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 2356 w = ri->ri_emuwidth; 2357 h = ri->ri_font->fontheight * nrows; 2358 2359 rasops_unpack_attr(fillattr, &fg, &bg, &ul); 2360 radeonfb_rectfill(dp, x, y, w, h, ri->ri_devcmap[bg & 0xf]); 2361 } 2362 } 2363 2364 static void 2365 radeonfb_copyrows(void *cookie, int srcrow, int dstrow, int nrows) 2366 { 2367 struct rasops_info *ri = cookie; 2368 struct vcons_screen *scr = ri->ri_hw; 2369 struct radeonfb_display *dp = scr->scr_cookie; 2370 uint32_t x, ys, yd, w, h; 2371 2372 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 2373 x = ri->ri_xorigin; 2374 ys = ri->ri_yorigin + ri->ri_font->fontheight * srcrow; 2375 yd = ri->ri_yorigin + ri->ri_font->fontheight * dstrow; 2376 w = ri->ri_emuwidth; 2377 h = ri->ri_font->fontheight * nrows; 2378 radeonfb_bitblt(dp, x, ys, x, yd, w, h, 2379 RADEON_ROP3_S, 0xffffffff); 2380 } 2381 } 2382 2383 static void 2384 radeonfb_copycols(void *cookie, int row, int srccol, int dstcol, int ncols) 2385 { 2386 struct rasops_info *ri = cookie; 2387 struct vcons_screen *scr = ri->ri_hw; 2388 struct radeonfb_display *dp = scr->scr_cookie; 2389 uint32_t xs, xd, y, w, h; 2390 2391 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 2392 xs = ri->ri_xorigin + ri->ri_font->fontwidth * srccol; 2393 xd = ri->ri_xorigin + ri->ri_font->fontwidth * dstcol; 2394 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 2395 w = ri->ri_font->fontwidth * ncols; 2396 h = ri->ri_font->fontheight; 2397 radeonfb_bitblt(dp, xs, y, xd, y, w, h, 2398 RADEON_ROP3_S, 0xffffffff); 2399 } 2400 } 2401 2402 static void 2403 radeonfb_erasecols(void *cookie, int row, int startcol, int ncols, 2404 long fillattr) 2405 { 2406 struct rasops_info *ri = cookie; 2407 struct vcons_screen *scr = ri->ri_hw; 2408 struct radeonfb_display *dp = scr->scr_cookie; 2409 uint32_t x, y, w, h, fg, bg, ul; 2410 2411 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 2412 x = ri->ri_xorigin + ri->ri_font->fontwidth * startcol; 2413 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 2414 w = ri->ri_font->fontwidth * ncols; 2415 h = ri->ri_font->fontheight; 2416 2417 rasops_unpack_attr(fillattr, &fg, &bg, &ul); 2418 radeonfb_rectfill(dp, x, y, w, h, ri->ri_devcmap[bg & 0xf]); 2419 } 2420 } 2421 2422 static void 2423 radeonfb_cursor(void *cookie, int on, int row, int col) 2424 { 2425 struct rasops_info *ri = cookie; 2426 struct vcons_screen *scr = ri->ri_hw; 2427 struct radeonfb_display *dp = scr->scr_cookie; 2428 int x, y, wi, he; 2429 2430 wi = ri->ri_font->fontwidth; 2431 he = ri->ri_font->fontheight; 2432 2433 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 2434 x = ri->ri_ccol * wi + ri->ri_xorigin; 2435 y = ri->ri_crow * he + ri->ri_yorigin; 2436 /* first turn off the old cursor */ 2437 if (ri->ri_flg & RI_CURSOR) { 2438 radeonfb_bitblt(dp, x, y, x, y, wi, he, 2439 RADEON_ROP3_Dn, 0xffffffff); 2440 ri->ri_flg &= ~RI_CURSOR; 2441 } 2442 ri->ri_crow = row; 2443 ri->ri_ccol = col; 2444 /* then (possibly) turn on the new one */ 2445 if (on) { 2446 x = ri->ri_ccol * wi + ri->ri_xorigin; 2447 y = ri->ri_crow * he + ri->ri_yorigin; 2448 radeonfb_bitblt(dp, x, y, x, y, wi, he, 2449 RADEON_ROP3_Dn, 0xffffffff); 2450 ri->ri_flg |= RI_CURSOR; 2451 } 2452 } else { 2453 scr->scr_ri.ri_crow = row; 2454 scr->scr_ri.ri_ccol = col; 2455 scr->scr_ri.ri_flg &= ~RI_CURSOR; 2456 } 2457 } 2458 2459 static int 2460 radeonfb_allocattr(void *cookie, int fg, int bg, int flags, long *attrp) 2461 { 2462 if ((fg == 0) && (bg == 0)) { 2463 fg = WS_DEFAULT_FG; 2464 bg = WS_DEFAULT_BG; 2465 } 2466 *attrp = ((fg & 0xf) << 24) | ((bg & 0xf) << 16) | (flags & 0xff) << 8; 2467 return 0; 2468 } 2469 2470 /* 2471 * Underlying acceleration support. 2472 */ 2473 static void 2474 radeonfb_setup_mono(struct radeonfb_display *dp, int xd, int yd, int width, 2475 int height, uint32_t fg, uint32_t bg) 2476 { 2477 struct radeonfb_softc *sc = dp->rd_softc; 2478 uint32_t gmc; 2479 uint32_t padded_width = (width+7) & 0xfff8; 2480 uint32_t topleft, bottomright; 2481 2482 gmc = dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT; 2483 2484 if (width != padded_width) { 2485 2486 radeonfb_wait_fifo(sc, 2); 2487 topleft = ((yd << 16) & 0x1fff0000) | (xd & 0x1fff); 2488 bottomright = (((yd + height) << 16) & 0x1fff0000) | 2489 ((xd + width) & 0x1fff); 2490 PUT32(sc, RADEON_SC_TOP_LEFT, topleft); 2491 PUT32(sc, RADEON_SC_BOTTOM_RIGHT, bottomright); 2492 } 2493 2494 radeonfb_wait_fifo(sc, 5); 2495 2496 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 2497 RADEON_GMC_BRUSH_NONE | 2498 RADEON_GMC_SRC_DATATYPE_MONO_FG_BG | 2499 //RADEON_GMC_BYTE_LSB_TO_MSB | 2500 RADEON_GMC_DST_CLIPPING | 2501 RADEON_ROP3_S | 2502 RADEON_DP_SRC_SOURCE_HOST_DATA | 2503 RADEON_GMC_CLR_CMP_CNTL_DIS | 2504 RADEON_GMC_WR_MSK_DIS | 2505 gmc); 2506 2507 PUT32(sc, RADEON_DP_SRC_FRGD_CLR, fg); 2508 PUT32(sc, RADEON_DP_SRC_BKGD_CLR, bg); 2509 2510 PUT32(sc, RADEON_DST_X_Y, (xd << 16) | yd); 2511 PUT32(sc, RADEON_DST_WIDTH_HEIGHT, (padded_width << 16) | height); 2512 2513 } 2514 2515 static void 2516 radeonfb_feed_bytes(struct radeonfb_display *dp, int count, uint8_t *data) 2517 { 2518 struct radeonfb_softc *sc = dp->rd_softc; 2519 int i; 2520 uint32_t latch = 0; 2521 int shift = 0; 2522 2523 for (i = 0; i < count; i++) { 2524 latch |= (data[i] << shift); 2525 if (shift == 24) { 2526 radeonfb_wait_fifo(sc, 1); 2527 PUT32(sc, RADEON_HOST_DATA0, latch); 2528 latch = 0; 2529 shift = 0; 2530 } else 2531 shift += 8; 2532 } 2533 if (shift != 0) { 2534 radeonfb_wait_fifo(sc, 1); 2535 PUT32(sc, RADEON_HOST_DATA0, latch); 2536 } 2537 radeonfb_unclip(sc); 2538 } 2539 2540 static void 2541 radeonfb_rectfill(struct radeonfb_display *dp, int dstx, int dsty, 2542 int width, int height, uint32_t color) 2543 { 2544 struct radeonfb_softc *sc = dp->rd_softc; 2545 uint32_t gmc; 2546 2547 gmc = dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT; 2548 2549 radeonfb_wait_fifo(sc, 6); 2550 2551 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 2552 RADEON_GMC_BRUSH_SOLID_COLOR | 2553 RADEON_GMC_SRC_DATATYPE_COLOR | 2554 RADEON_GMC_CLR_CMP_CNTL_DIS | 2555 RADEON_ROP3_P | gmc); 2556 2557 PUT32(sc, RADEON_DP_BRUSH_FRGD_CLR, color); 2558 PUT32(sc, RADEON_DP_WRITE_MASK, 0xffffffff); 2559 PUT32(sc, RADEON_DP_CNTL, 2560 RADEON_DST_X_LEFT_TO_RIGHT | 2561 RADEON_DST_Y_TOP_TO_BOTTOM); 2562 PUT32(sc, RADEON_DST_Y_X, (dsty << 16) | dstx); 2563 PUT32(sc, RADEON_DST_WIDTH_HEIGHT, (width << 16) | (height)); 2564 2565 /* 2566 * XXX: we don't wait for the fifo to empty -- that would slow 2567 * things down! The linux radeonfb driver waits, but xfree doesn't 2568 */ 2569 /* XXX: for now we do, to make it safe for direct drawing */ 2570 radeonfb_engine_idle(sc); 2571 } 2572 2573 static void 2574 radeonfb_bitblt(struct radeonfb_display *dp, int srcx, int srcy, 2575 int dstx, int dsty, int width, int height, int rop, uint32_t mask) 2576 { 2577 struct radeonfb_softc *sc = dp->rd_softc; 2578 uint32_t gmc; 2579 uint32_t dir; 2580 2581 if (dsty < srcy) { 2582 dir = RADEON_DST_Y_TOP_TO_BOTTOM; 2583 } else { 2584 srcy += height - 1; 2585 dsty += height - 1; 2586 dir = 0; 2587 } 2588 if (dstx < srcx) { 2589 dir |= RADEON_DST_X_LEFT_TO_RIGHT; 2590 } else { 2591 srcx += width - 1; 2592 dstx += width - 1; 2593 } 2594 2595 gmc = dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT; 2596 2597 radeonfb_wait_fifo(sc, 6); 2598 2599 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 2600 //RADEON_GMC_SRC_CLIPPING | 2601 RADEON_GMC_BRUSH_SOLID_COLOR | 2602 RADEON_GMC_SRC_DATATYPE_COLOR | 2603 RADEON_GMC_CLR_CMP_CNTL_DIS | 2604 RADEON_DP_SRC_SOURCE_MEMORY | 2605 rop | gmc); 2606 2607 PUT32(sc, RADEON_DP_WRITE_MASK, mask); 2608 PUT32(sc, RADEON_DP_CNTL, dir); 2609 PUT32(sc, RADEON_SRC_Y_X, (srcy << 16) | srcx); 2610 PUT32(sc, RADEON_DST_Y_X, (dsty << 16) | dstx); 2611 PUT32(sc, RADEON_DST_WIDTH_HEIGHT, (width << 16) | (height)); 2612 2613 /* 2614 * XXX: we don't wait for the fifo to empty -- that would slow 2615 * things down! The linux radeonfb driver waits, but xfree doesn't 2616 */ 2617 /* XXX: for now we do, to make it safe for direct drawing */ 2618 radeonfb_engine_idle(sc); 2619 } 2620 2621 static void 2622 radeonfb_engine_idle(struct radeonfb_softc *sc) 2623 { 2624 int i; 2625 2626 radeonfb_wait_fifo(sc, 64); 2627 for (i = RADEON_TIMEOUT; i; i--) { 2628 if ((GET32(sc, RADEON_RBBM_STATUS) & 2629 RADEON_RBBM_ACTIVE) == 0) { 2630 radeonfb_engine_flush(sc); 2631 break; 2632 } 2633 } 2634 } 2635 2636 static void 2637 radeonfb_wait_fifo(struct radeonfb_softc *sc, int n) 2638 { 2639 int i; 2640 2641 for (i = RADEON_TIMEOUT; i; i--) { 2642 if ((GET32(sc, RADEON_RBBM_STATUS) & 2643 RADEON_RBBM_FIFOCNT_MASK) >= n) 2644 return; 2645 } 2646 #ifdef DIAGNOSTIC 2647 if (!i) 2648 printf("%s: timed out waiting for fifo (%x)\n", 2649 XNAME(sc), GET32(sc, RADEON_RBBM_STATUS)); 2650 #endif 2651 } 2652 2653 static void 2654 radeonfb_engine_flush(struct radeonfb_softc *sc) 2655 { 2656 int i; 2657 SET32(sc, RADEON_RB2D_DSTCACHE_CTLSTAT, RADEON_RB2D_DC_FLUSH_ALL); 2658 for (i = RADEON_TIMEOUT; i; i--) { 2659 if ((GET32(sc, RADEON_RB2D_DSTCACHE_CTLSTAT) & 2660 RADEON_RB2D_DC_BUSY) == 0) 2661 break; 2662 } 2663 #ifdef DIAGNOSTIC 2664 if (!i) 2665 printf("%s: engine flush timed out!\n", XNAME(sc)); 2666 #endif 2667 } 2668 2669 static inline void 2670 radeonfb_unclip(struct radeonfb_softc *sc) 2671 { 2672 2673 radeonfb_wait_fifo(sc, 2); 2674 PUT32(sc, RADEON_SC_TOP_LEFT, 0); 2675 PUT32(sc, RADEON_SC_BOTTOM_RIGHT, 0x1fff1fff); 2676 } 2677 2678 static void 2679 radeonfb_engine_init(struct radeonfb_display *dp) 2680 { 2681 struct radeonfb_softc *sc = dp->rd_softc; 2682 uint32_t pitch; 2683 2684 /* no 3D */ 2685 PUT32(sc, RADEON_RB3D_CNTL, 0); 2686 2687 radeonfb_engine_reset(sc); 2688 pitch = ((dp->rd_virtx * (dp->rd_bpp / 8) + 0x3f)) >> 6; 2689 //pitch = ((sc->sc_maxx * (sc->sc_maxbpp / 8) + 0x3f)) >> 6; 2690 2691 radeonfb_wait_fifo(sc, 1); 2692 if (!IS_R300(sc)) 2693 PUT32(sc, RADEON_RB2D_DSTCACHE_MODE, 0); 2694 2695 radeonfb_wait_fifo(sc, 3); 2696 PUT32(sc, RADEON_DEFAULT_PITCH_OFFSET, 2697 (pitch << 22) | (sc->sc_aperbase >> 10)); 2698 2699 2700 PUT32(sc, RADEON_DST_PITCH_OFFSET, 2701 (pitch << 22) | (sc->sc_aperbase >> 10)); 2702 PUT32(sc, RADEON_SRC_PITCH_OFFSET, 2703 (pitch << 22) | (sc->sc_aperbase >> 10)); 2704 2705 radeonfb_wait_fifo(sc, 1); 2706 #if _BYTE_ORDER == _BIG_ENDIAN 2707 SET32(sc, RADEON_DP_DATATYPE, RADEON_HOST_BIG_ENDIAN_EN); 2708 #else 2709 CLR32(sc, RADEON_DP_DATATYPE, RADEON_HOST_BIG_ENDIAN_EN); 2710 #endif 2711 2712 /* default scissors -- no clipping */ 2713 radeonfb_wait_fifo(sc, 1); 2714 PUT32(sc, RADEON_DEFAULT_SC_BOTTOM_RIGHT, 2715 RADEON_DEFAULT_SC_RIGHT_MAX | RADEON_DEFAULT_SC_BOTTOM_MAX); 2716 2717 radeonfb_wait_fifo(sc, 1); 2718 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 2719 (dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT) | 2720 RADEON_GMC_CLR_CMP_CNTL_DIS | 2721 RADEON_GMC_BRUSH_SOLID_COLOR | 2722 RADEON_GMC_SRC_DATATYPE_COLOR); 2723 2724 radeonfb_wait_fifo(sc, 7); 2725 PUT32(sc, RADEON_DST_LINE_START, 0); 2726 PUT32(sc, RADEON_DST_LINE_END, 0); 2727 PUT32(sc, RADEON_DP_BRUSH_FRGD_CLR, 0xffffffff); 2728 PUT32(sc, RADEON_DP_BRUSH_BKGD_CLR, 0); 2729 PUT32(sc, RADEON_DP_SRC_FRGD_CLR, 0xffffffff); 2730 PUT32(sc, RADEON_DP_SRC_BKGD_CLR, 0); 2731 PUT32(sc, RADEON_DP_WRITE_MASK, 0xffffffff); 2732 2733 radeonfb_engine_idle(sc); 2734 } 2735 2736 static void 2737 radeonfb_engine_reset(struct radeonfb_softc *sc) 2738 { 2739 uint32_t hpc, rbbm, mclkcntl, clkindex; 2740 2741 radeonfb_engine_flush(sc); 2742 2743 clkindex = GET32(sc, RADEON_CLOCK_CNTL_INDEX); 2744 if (HAS_R300CG(sc)) 2745 radeonfb_r300cg_workaround(sc); 2746 mclkcntl = GETPLL(sc, RADEON_MCLK_CNTL); 2747 2748 /* 2749 * According to comments in XFree code, resetting the HDP via 2750 * the RBBM_SOFT_RESET can cause bad behavior on some systems. 2751 * So we use HOST_PATH_CNTL instead. 2752 */ 2753 2754 hpc = GET32(sc, RADEON_HOST_PATH_CNTL); 2755 rbbm = GET32(sc, RADEON_RBBM_SOFT_RESET); 2756 if (IS_R300(sc)) { 2757 PUT32(sc, RADEON_RBBM_SOFT_RESET, rbbm | 2758 RADEON_SOFT_RESET_CP | 2759 RADEON_SOFT_RESET_HI | 2760 RADEON_SOFT_RESET_E2); 2761 GET32(sc, RADEON_RBBM_SOFT_RESET); 2762 PUT32(sc, RADEON_RBBM_SOFT_RESET, 0); 2763 /* 2764 * XXX: this bit is not defined in any ATI docs I have, 2765 * nor in the XFree code, but XFree does it. Why? 2766 */ 2767 SET32(sc, RADEON_RB2D_DSTCACHE_MODE, (1<<17)); 2768 } else { 2769 PUT32(sc, RADEON_RBBM_SOFT_RESET, rbbm | 2770 RADEON_SOFT_RESET_CP | 2771 RADEON_SOFT_RESET_SE | 2772 RADEON_SOFT_RESET_RE | 2773 RADEON_SOFT_RESET_PP | 2774 RADEON_SOFT_RESET_E2 | 2775 RADEON_SOFT_RESET_RB); 2776 GET32(sc, RADEON_RBBM_SOFT_RESET); 2777 PUT32(sc, RADEON_RBBM_SOFT_RESET, rbbm & 2778 ~(RADEON_SOFT_RESET_CP | 2779 RADEON_SOFT_RESET_SE | 2780 RADEON_SOFT_RESET_RE | 2781 RADEON_SOFT_RESET_PP | 2782 RADEON_SOFT_RESET_E2 | 2783 RADEON_SOFT_RESET_RB)); 2784 GET32(sc, RADEON_RBBM_SOFT_RESET); 2785 } 2786 2787 PUT32(sc, RADEON_HOST_PATH_CNTL, hpc | RADEON_HDP_SOFT_RESET); 2788 GET32(sc, RADEON_HOST_PATH_CNTL); 2789 PUT32(sc, RADEON_HOST_PATH_CNTL, hpc); 2790 2791 if (IS_R300(sc)) 2792 PUT32(sc, RADEON_RBBM_SOFT_RESET, rbbm); 2793 2794 PUT32(sc, RADEON_CLOCK_CNTL_INDEX, clkindex); 2795 PUTPLL(sc, RADEON_MCLK_CNTL, mclkcntl); 2796 2797 if (HAS_R300CG(sc)) 2798 radeonfb_r300cg_workaround(sc); 2799 } 2800 2801 static int 2802 radeonfb_set_curpos(struct radeonfb_display *dp, struct wsdisplay_curpos *pos) 2803 { 2804 int x, y; 2805 2806 x = pos->x; 2807 y = pos->y; 2808 2809 /* 2810 * This doesn't let a cursor move off the screen. I'm not 2811 * sure if this will have negative effects for e.g. Xinerama. 2812 * I'd guess Xinerama handles it by changing the cursor shape, 2813 * but that needs verification. 2814 */ 2815 if (x >= dp->rd_virtx) 2816 x = dp->rd_virtx - 1; 2817 if (x < 0) 2818 x = 0; 2819 if (y >= dp->rd_virty) 2820 y = dp->rd_virty - 1; 2821 if (y < 0) 2822 y = 0; 2823 2824 dp->rd_cursor.rc_pos.x = x; 2825 dp->rd_cursor.rc_pos.y = y; 2826 2827 radeonfb_cursor_position(dp); 2828 return 0; 2829 } 2830 2831 static int 2832 radeonfb_set_cursor(struct radeonfb_display *dp, struct wsdisplay_cursor *wc) 2833 { 2834 unsigned flags; 2835 2836 uint8_t r[2], g[2], b[2]; 2837 unsigned index, count; 2838 int i, err; 2839 int pitch, size; 2840 struct radeonfb_cursor nc; 2841 2842 flags = wc->which; 2843 2844 /* copy old values */ 2845 nc = dp->rd_cursor; 2846 2847 if (flags & WSDISPLAY_CURSOR_DOCMAP) { 2848 index = wc->cmap.index; 2849 count = wc->cmap.count; 2850 2851 if (index >= 2 || (index + count) > 2) 2852 return EINVAL; 2853 2854 err = copyin(wc->cmap.red, &r[index], count); 2855 if (err) 2856 return err; 2857 err = copyin(wc->cmap.green, &g[index], count); 2858 if (err) 2859 return err; 2860 err = copyin(wc->cmap.blue, &b[index], count); 2861 if (err) 2862 return err; 2863 2864 for (i = index; i < index + count; i++) { 2865 nc.rc_cmap[i] = 2866 (r[i] << 16) + (g[i] << 8) + (b[i] << 0); 2867 } 2868 } 2869 2870 if (flags & WSDISPLAY_CURSOR_DOSHAPE) { 2871 if ((wc->size.x > RADEON_CURSORMAXX) || 2872 (wc->size.y > RADEON_CURSORMAXY)) 2873 return EINVAL; 2874 2875 /* figure bytes per line */ 2876 pitch = (wc->size.x + 7) / 8; 2877 size = pitch * wc->size.y; 2878 2879 /* clear the old cursor and mask */ 2880 memset(nc.rc_image, 0, 512); 2881 memset(nc.rc_mask, 0, 512); 2882 2883 nc.rc_size = wc->size; 2884 2885 if ((err = copyin(wc->image, nc.rc_image, size)) != 0) 2886 return err; 2887 2888 if ((err = copyin(wc->mask, nc.rc_mask, size)) != 0) 2889 return err; 2890 } 2891 2892 if (flags & WSDISPLAY_CURSOR_DOHOT) { 2893 nc.rc_hot = wc->hot; 2894 if (nc.rc_hot.x >= nc.rc_size.x) 2895 nc.rc_hot.x = nc.rc_size.x - 1; 2896 if (nc.rc_hot.y >= nc.rc_size.y) 2897 nc.rc_hot.y = nc.rc_size.y - 1; 2898 } 2899 2900 if (flags & WSDISPLAY_CURSOR_DOPOS) { 2901 nc.rc_pos = wc->pos; 2902 if (nc.rc_pos.x >= dp->rd_virtx) 2903 nc.rc_pos.x = dp->rd_virtx - 1; 2904 #if 0 2905 if (nc.rc_pos.x < 0) 2906 nc.rc_pos.x = 0; 2907 #endif 2908 if (nc.rc_pos.y >= dp->rd_virty) 2909 nc.rc_pos.y = dp->rd_virty - 1; 2910 #if 0 2911 if (nc.rc_pos.y < 0) 2912 nc.rc_pos.y = 0; 2913 #endif 2914 } 2915 if (flags & WSDISPLAY_CURSOR_DOCUR) { 2916 nc.rc_visible = wc->enable; 2917 } 2918 2919 dp->rd_cursor = nc; 2920 radeonfb_cursor_update(dp, wc->which); 2921 2922 return 0; 2923 } 2924 2925 /* 2926 * Change the cursor shape. Call this with the cursor locked to avoid 2927 * flickering/tearing. 2928 */ 2929 static void 2930 radeonfb_cursor_shape(struct radeonfb_display *dp) 2931 { 2932 uint8_t and[512], xor[512]; 2933 int i, j, src, dst, pitch; 2934 const uint8_t *msk = dp->rd_cursor.rc_mask; 2935 const uint8_t *img = dp->rd_cursor.rc_image; 2936 2937 /* 2938 * Radeon cursor data interleaves one line of AND data followed 2939 * by a line of XOR data. (Each line corresponds to a whole hardware 2940 * pitch - i.e. 64 pixels or 8 bytes.) 2941 * 2942 * The cursor is displayed using the following table: 2943 * 2944 * AND XOR Result 2945 * ---------------------- 2946 * 0 0 Cursor color 0 2947 * 0 1 Cursor color 1 2948 * 1 0 Transparent 2949 * 1 1 Complement of background 2950 * 2951 * Our masks are therefore different from what we were passed. 2952 * Passed in, I'm assuming the data represents either color 0 or 1, 2953 * and a mask, so the passed in table looks like: 2954 * 2955 * IMG Mask Result 2956 * ----------------------- 2957 * 0 0 Transparent 2958 * 0 1 Cursor color 0 2959 * 1 0 Transparent 2960 * 1 1 Cursor color 1 2961 * 2962 * IF mask bit == 1, AND = 0, XOR = color. 2963 * IF mask bit == 0, AND = 1, XOR = 0. 2964 * 2965 * hence: AND = ~(mask); XOR = color & ~(mask); 2966 */ 2967 2968 pitch = ((dp->rd_cursor.rc_size.x + 7) / 8); 2969 2970 /* start by assuming all bits are transparent */ 2971 memset(and, 0xff, 512); 2972 memset(xor, 0x00, 512); 2973 2974 src = 0; 2975 dst = 0; 2976 for (i = 0; i < 64; i++) { 2977 for (j = 0; j < 64; j += 8) { 2978 if ((i < dp->rd_cursor.rc_size.y) && 2979 (j < dp->rd_cursor.rc_size.x)) { 2980 2981 /* take care to leave odd bits alone */ 2982 and[dst] &= ~(msk[src]); 2983 xor[dst] = img[src] & msk[src]; 2984 src++; 2985 } 2986 dst++; 2987 } 2988 } 2989 2990 /* copy the image into place */ 2991 for (i = 0; i < 64; i++) { 2992 memcpy((uint8_t *)dp->rd_curptr + (i * 16), 2993 &and[i * 8], 8); 2994 memcpy((uint8_t *)dp->rd_curptr + (i * 16) + 8, 2995 &xor[i * 8], 8); 2996 } 2997 } 2998 2999 static void 3000 radeonfb_cursor_position(struct radeonfb_display *dp) 3001 { 3002 struct radeonfb_softc *sc = dp->rd_softc; 3003 uint32_t offset, hvoff, hvpos; /* registers */ 3004 uint32_t coff; /* cursor offset */ 3005 int i, x, y, xoff, yoff, crtcoff; 3006 3007 /* 3008 * XXX: this also needs to handle pan/scan 3009 */ 3010 for (i = 0; i < dp->rd_ncrtcs; i++) { 3011 3012 struct radeonfb_crtc *rcp = &dp->rd_crtcs[i]; 3013 3014 if (rcp->rc_number) { 3015 offset = RADEON_CUR2_OFFSET; 3016 hvoff = RADEON_CUR2_HORZ_VERT_OFF; 3017 hvpos = RADEON_CUR2_HORZ_VERT_POSN; 3018 crtcoff = RADEON_CRTC2_OFFSET; 3019 } else { 3020 offset = RADEON_CUR_OFFSET; 3021 hvoff = RADEON_CUR_HORZ_VERT_OFF; 3022 hvpos = RADEON_CUR_HORZ_VERT_POSN; 3023 crtcoff = RADEON_CRTC_OFFSET; 3024 } 3025 3026 x = dp->rd_cursor.rc_pos.x; 3027 y = dp->rd_cursor.rc_pos.y; 3028 3029 while (y < rcp->rc_yoffset) { 3030 rcp->rc_yoffset -= RADEON_PANINCREMENT; 3031 } 3032 while (y >= (rcp->rc_yoffset + rcp->rc_videomode.vdisplay)) { 3033 rcp->rc_yoffset += RADEON_PANINCREMENT; 3034 } 3035 while (x < rcp->rc_xoffset) { 3036 rcp->rc_xoffset -= RADEON_PANINCREMENT; 3037 } 3038 while (x >= (rcp->rc_xoffset + rcp->rc_videomode.hdisplay)) { 3039 rcp->rc_xoffset += RADEON_PANINCREMENT; 3040 } 3041 3042 /* adjust for the cursor's hotspot */ 3043 x -= dp->rd_cursor.rc_hot.x; 3044 y -= dp->rd_cursor.rc_hot.y; 3045 xoff = yoff = 0; 3046 3047 if (x >= dp->rd_virtx) 3048 x = dp->rd_virtx - 1; 3049 if (y >= dp->rd_virty) 3050 y = dp->rd_virty - 1; 3051 3052 /* now adjust cursor so it is relative to viewport */ 3053 x -= rcp->rc_xoffset; 3054 y -= rcp->rc_yoffset; 3055 3056 /* 3057 * no need to check for fall off, because we should 3058 * never move off the screen entirely! 3059 */ 3060 coff = 0; 3061 if (x < 0) { 3062 xoff = -x; 3063 x = 0; 3064 } 3065 if (y < 0) { 3066 yoff = -y; 3067 y = 0; 3068 coff = (yoff * 2) * 8; 3069 } 3070 3071 /* pan the display */ 3072 PUT32(sc, crtcoff, (rcp->rc_yoffset * dp->rd_stride) + 3073 rcp->rc_xoffset); 3074 3075 PUT32(sc, offset, (dp->rd_curoff + coff) | RADEON_CUR_LOCK); 3076 PUT32(sc, hvoff, (xoff << 16) | (yoff) | RADEON_CUR_LOCK); 3077 /* NB: this unlocks the cursor */ 3078 PUT32(sc, hvpos, (x << 16) | y); 3079 } 3080 } 3081 3082 static void 3083 radeonfb_cursor_visible(struct radeonfb_display *dp) 3084 { 3085 int i; 3086 uint32_t gencntl, bit; 3087 3088 for (i = 0; i < dp->rd_ncrtcs; i++) { 3089 if (dp->rd_crtcs[i].rc_number) { 3090 gencntl = RADEON_CRTC2_GEN_CNTL; 3091 bit = RADEON_CRTC2_CUR_EN; 3092 } else { 3093 gencntl = RADEON_CRTC_GEN_CNTL; 3094 bit = RADEON_CRTC_CUR_EN; 3095 } 3096 3097 if (dp->rd_cursor.rc_visible) 3098 SET32(dp->rd_softc, gencntl, bit); 3099 else 3100 CLR32(dp->rd_softc, gencntl, bit); 3101 } 3102 } 3103 3104 static void 3105 radeonfb_cursor_cmap(struct radeonfb_display *dp) 3106 { 3107 int i; 3108 uint32_t c0reg, c1reg; 3109 struct radeonfb_softc *sc = dp->rd_softc; 3110 3111 for (i = 0; i < dp->rd_ncrtcs; i++) { 3112 if (dp->rd_crtcs[i].rc_number) { 3113 c0reg = RADEON_CUR2_CLR0; 3114 c1reg = RADEON_CUR2_CLR1; 3115 } else { 3116 c0reg = RADEON_CUR_CLR0; 3117 c1reg = RADEON_CUR_CLR1; 3118 } 3119 3120 PUT32(sc, c0reg, dp->rd_cursor.rc_cmap[0]); 3121 PUT32(sc, c1reg, dp->rd_cursor.rc_cmap[1]); 3122 } 3123 } 3124 3125 static void 3126 radeonfb_cursor_update(struct radeonfb_display *dp, unsigned which) 3127 { 3128 struct radeonfb_softc *sc; 3129 int i; 3130 3131 sc = dp->rd_softc; 3132 for (i = 0; i < dp->rd_ncrtcs; i++) { 3133 if (dp->rd_crtcs[i].rc_number) { 3134 SET32(sc, RADEON_CUR2_OFFSET, RADEON_CUR_LOCK); 3135 } else { 3136 SET32(sc, RADEON_CUR_OFFSET,RADEON_CUR_LOCK); 3137 } 3138 } 3139 3140 if (which & WSDISPLAY_CURSOR_DOCMAP) 3141 radeonfb_cursor_cmap(dp); 3142 3143 if (which & WSDISPLAY_CURSOR_DOSHAPE) 3144 radeonfb_cursor_shape(dp); 3145 3146 if (which & WSDISPLAY_CURSOR_DOCUR) 3147 radeonfb_cursor_visible(dp); 3148 3149 /* this one is unconditional, because it updates other stuff */ 3150 radeonfb_cursor_position(dp); 3151 } 3152 3153 static struct videomode * 3154 radeonfb_best_refresh(struct videomode *m1, struct videomode *m2) 3155 { 3156 int r1, r2; 3157 3158 /* otherwise pick the higher refresh rate */ 3159 r1 = DIVIDE(DIVIDE(m1->dot_clock, m1->htotal), m1->vtotal); 3160 r2 = DIVIDE(DIVIDE(m2->dot_clock, m2->htotal), m2->vtotal); 3161 3162 return (r1 < r2 ? m2 : m1); 3163 } 3164 3165 static const struct videomode * 3166 radeonfb_port_mode(struct radeonfb_softc *sc, struct radeonfb_port *rp, 3167 int x, int y) 3168 { 3169 struct edid_info *ep = &rp->rp_edid; 3170 struct videomode *vmp = NULL; 3171 int i; 3172 3173 if (!rp->rp_edid_valid) { 3174 /* fallback to safe mode */ 3175 return radeonfb_modelookup(sc->sc_defaultmode); 3176 } 3177 3178 /* always choose the preferred mode first! */ 3179 if (ep->edid_preferred_mode) { 3180 3181 /* XXX: add auto-stretching support for native mode */ 3182 3183 /* this may want panning to occur, btw */ 3184 if ((ep->edid_preferred_mode->hdisplay <= x) && 3185 (ep->edid_preferred_mode->vdisplay <= y)) 3186 return ep->edid_preferred_mode; 3187 } 3188 3189 for (i = 0; i < ep->edid_nmodes; i++) { 3190 /* 3191 * We elect to pick a resolution that is too large for 3192 * the monitor than one that is too small. This means 3193 * that we will prefer to pan rather than to try to 3194 * center a smaller display on a larger screen. In 3195 * practice, this shouldn't matter because if a 3196 * monitor can support a larger resolution, it can 3197 * probably also support the smaller. A specific 3198 * exception is fixed format panels, but hopefully 3199 * they are properly dealt with by the "autostretch" 3200 * logic above. 3201 */ 3202 if ((ep->edid_modes[i].hdisplay > x) || 3203 (ep->edid_modes[i].vdisplay > y)) { 3204 continue; 3205 } 3206 3207 /* 3208 * at this point, the display mode is no larger than 3209 * what we've requested. 3210 */ 3211 if (vmp == NULL) 3212 vmp = &ep->edid_modes[i]; 3213 3214 /* eliminate smaller modes */ 3215 if ((vmp->hdisplay >= ep->edid_modes[i].hdisplay) || 3216 (vmp->vdisplay >= ep->edid_modes[i].vdisplay)) 3217 continue; 3218 3219 if ((vmp->hdisplay < ep->edid_modes[i].hdisplay) || 3220 (vmp->vdisplay < ep->edid_modes[i].vdisplay)) { 3221 vmp = &ep->edid_modes[i]; 3222 continue; 3223 } 3224 3225 KASSERT(vmp->hdisplay == ep->edid_modes[i].hdisplay); 3226 KASSERT(vmp->vdisplay == ep->edid_modes[i].vdisplay); 3227 3228 vmp = radeonfb_best_refresh(vmp, &ep->edid_modes[i]); 3229 } 3230 3231 return (vmp ? vmp : radeonfb_modelookup(sc->sc_defaultmode)); 3232 } 3233 3234 static int 3235 radeonfb_hasres(struct videomode *list, int nlist, int x, int y) 3236 { 3237 int i; 3238 3239 for (i = 0; i < nlist; i++) { 3240 if ((x == list[i].hdisplay) && 3241 (y == list[i].vdisplay)) { 3242 return 1; 3243 } 3244 } 3245 return 0; 3246 } 3247 3248 static void 3249 radeonfb_pickres(struct radeonfb_display *dp, uint16_t *x, uint16_t *y, 3250 int pan) 3251 { 3252 struct radeonfb_port *rp; 3253 struct edid_info *ep; 3254 int i, j; 3255 3256 *x = 0; 3257 *y = 0; 3258 3259 if (pan) { 3260 for (i = 0; i < dp->rd_ncrtcs; i++) { 3261 rp = dp->rd_crtcs[i].rc_port; 3262 ep = &rp->rp_edid; 3263 if (!rp->rp_edid_valid) { 3264 /* monitor not present */ 3265 continue; 3266 } 3267 3268 /* 3269 * For now we are ignoring "conflict" that 3270 * could occur when mixing some modes like 3271 * 1280x1024 and 1400x800. It isn't clear 3272 * which is better, so the first one wins. 3273 */ 3274 for (j = 0; j < ep->edid_nmodes; j++) { 3275 /* 3276 * ignore resolutions that are too big for 3277 * the radeon 3278 */ 3279 if (ep->edid_modes[j].hdisplay > 3280 dp->rd_softc->sc_maxx) 3281 continue; 3282 if (ep->edid_modes[j].vdisplay > 3283 dp->rd_softc->sc_maxy) 3284 continue; 3285 3286 /* 3287 * pick largest resolution, the 3288 * smaller monitor will pan 3289 */ 3290 if ((ep->edid_modes[j].hdisplay >= *x) && 3291 (ep->edid_modes[j].vdisplay >= *y)) { 3292 *x = ep->edid_modes[j].hdisplay; 3293 *y = ep->edid_modes[j].vdisplay; 3294 } 3295 } 3296 } 3297 3298 } else { 3299 struct videomode modes[64]; 3300 int nmodes = 0; 3301 int valid = 0; 3302 3303 for (i = 0; i < dp->rd_ncrtcs; i++) { 3304 /* 3305 * pick the largest resolution in common. 3306 */ 3307 rp = dp->rd_crtcs[i].rc_port; 3308 ep = &rp->rp_edid; 3309 3310 if (!rp->rp_edid_valid) 3311 continue; 3312 3313 if (!valid) { 3314 /* initialize starting list */ 3315 for (j = 0; j < ep->edid_nmodes; j++) { 3316 /* 3317 * ignore resolutions that are 3318 * too big for the radeon 3319 */ 3320 if (ep->edid_modes[j].hdisplay > 3321 dp->rd_softc->sc_maxx) 3322 continue; 3323 if (ep->edid_modes[j].vdisplay > 3324 dp->rd_softc->sc_maxy) 3325 continue; 3326 3327 modes[nmodes] = ep->edid_modes[j]; 3328 nmodes++; 3329 } 3330 valid = 1; 3331 } else { 3332 /* merge into preexisting list */ 3333 for (j = 0; j < nmodes; j++) { 3334 if (!radeonfb_hasres(ep->edid_modes, 3335 ep->edid_nmodes, 3336 modes[j].hdisplay, 3337 modes[j].vdisplay)) { 3338 modes[j] = modes[nmodes]; 3339 j--; 3340 nmodes--; 3341 } 3342 } 3343 } 3344 } 3345 3346 /* now we have to pick from the merged list */ 3347 for (i = 0; i < nmodes; i++) { 3348 if ((modes[i].hdisplay >= *x) && 3349 (modes[i].vdisplay >= *y)) { 3350 *x = modes[i].hdisplay; 3351 *y = modes[i].vdisplay; 3352 } 3353 } 3354 } 3355 3356 if ((*x == 0) || (*y == 0)) { 3357 /* fallback to safe mode */ 3358 *x = 640; 3359 *y = 480; 3360 } 3361 } 3362 3363 3364 /* Get the current backlight level for the display. */ 3365 3366 static int 3367 radeonfb_get_backlight(struct radeonfb_display *dp) 3368 { 3369 int s; 3370 uint32_t level; 3371 3372 s = spltty(); 3373 3374 level = radeonfb_get32(dp->rd_softc, RADEON_LVDS_GEN_CNTL); 3375 level &= RADEON_LVDS_BL_MOD_LEV_MASK; 3376 level >>= RADEON_LVDS_BL_MOD_LEV_SHIFT; 3377 3378 /* 3379 * On some chips, we should negate the backlight level. 3380 * XXX Find out on which chips. 3381 */ 3382 #ifdef RADEONFB_BACKLIGHT_NEGATED 3383 level = RADEONFB_BACKLIGHT_MAX - level; 3384 #endif /* RADEONFB_BACKLIGHT_NEGATED */ 3385 3386 splx(s); 3387 3388 return level; 3389 } 3390 3391 /* Set the backlight to the given level for the display. */ 3392 3393 static int 3394 radeonfb_set_backlight(struct radeonfb_display *dp, int level) 3395 { 3396 struct radeonfb_softc *sc; 3397 int rlevel, s; 3398 uint32_t lvds; 3399 3400 s = spltty(); 3401 3402 if (level < 0) 3403 level = 0; 3404 else if (level >= RADEONFB_BACKLIGHT_MAX) 3405 level = RADEONFB_BACKLIGHT_MAX; 3406 3407 sc = dp->rd_softc; 3408 3409 /* On some chips, we should negate the backlight level. */ 3410 #ifdef RADEONFB_BACKLIGHT_NEGATED 3411 rlevel = RADEONFB_BACKLIGHT_MAX - level; 3412 #else 3413 rlevel = level; 3414 #endif /* RADEONFB_BACKLIGHT_NEGATED */ 3415 3416 callout_stop(&dp->rd_bl_lvds_co); 3417 radeonfb_engine_idle(sc); 3418 3419 /* 3420 * Turn off the display if the backlight is set to 0, since the 3421 * display is useless without backlight anyway. 3422 */ 3423 if (level == 0) 3424 radeonfb_blank(dp, 1); 3425 else if (radeonfb_get_backlight(dp) == 0) 3426 radeonfb_blank(dp, 0); 3427 3428 lvds = radeonfb_get32(sc, RADEON_LVDS_GEN_CNTL); 3429 lvds &= ~RADEON_LVDS_DISPLAY_DIS; 3430 if (!(lvds & RADEON_LVDS_BLON) || !(lvds & RADEON_LVDS_ON)) { 3431 lvds |= dp->rd_bl_lvds_val & RADEON_LVDS_DIGON; 3432 lvds |= RADEON_LVDS_BLON | RADEON_LVDS_EN; 3433 radeonfb_put32(sc, RADEON_LVDS_GEN_CNTL, lvds); 3434 lvds &= ~RADEON_LVDS_BL_MOD_LEV_MASK; 3435 lvds |= rlevel << RADEON_LVDS_BL_MOD_LEV_SHIFT; 3436 lvds |= RADEON_LVDS_ON; 3437 lvds |= dp->rd_bl_lvds_val & RADEON_LVDS_BL_MOD_EN; 3438 } else { 3439 lvds &= ~RADEON_LVDS_BL_MOD_LEV_MASK; 3440 lvds |= rlevel << RADEON_LVDS_BL_MOD_LEV_SHIFT; 3441 radeonfb_put32(sc, RADEON_LVDS_GEN_CNTL, lvds); 3442 } 3443 3444 dp->rd_bl_lvds_val &= ~RADEON_LVDS_STATE_MASK; 3445 dp->rd_bl_lvds_val |= lvds & RADEON_LVDS_STATE_MASK; 3446 /* XXX What is the correct delay? */ 3447 callout_schedule(&dp->rd_bl_lvds_co, 200 * hz); 3448 3449 splx(s); 3450 3451 return 0; 3452 } 3453 3454 /* 3455 * Callout function for delayed operations on the LVDS_GEN_CNTL register. 3456 * Set the delayed bits in the register, and clear the stored delayed 3457 * value. 3458 */ 3459 3460 static void radeonfb_lvds_callout(void *arg) 3461 { 3462 struct radeonfb_display *dp = arg; 3463 int s; 3464 3465 s = splhigh(); 3466 3467 radeonfb_mask32(dp->rd_softc, RADEON_LVDS_GEN_CNTL, ~0, 3468 dp->rd_bl_lvds_val); 3469 dp->rd_bl_lvds_val = 0; 3470 3471 splx(s); 3472 } 3473
Indexes created Thu Sep 25 16:09:42 GMT 2025