radeonfb.c revision 1.16
1 /* $NetBSD: radeonfb.c,v 1.16 2007/08/03 05:02:23 macallan Exp $ */ 2 3 /*- 4 * Copyright (c) 2006 Itronix Inc. 5 * All rights reserved. 6 * 7 * Written by Garrett D'Amore for Itronix Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. The name of Itronix Inc. may not be used to endorse 18 * or promote products derived from this software without specific 19 * prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY ITRONIX INC. ``AS IS'' AND ANY EXPRESS 22 * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 23 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL ITRONIX INC. BE LIABLE FOR ANY 25 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE 27 * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 29 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 30 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 31 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * ATI Technologies Inc. ("ATI") has not assisted in the creation of, and 36 * does not endorse, this software. ATI will not be responsible or liable 37 * for any actual or alleged damage or loss caused by or in connection with 38 * the use of or reliance on this software. 39 */ 40 41 /* 42 * Portions of this code were taken from XFree86's Radeon driver, which bears 43 * this notice: 44 * 45 * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and 46 * VA Linux Systems Inc., Fremont, California. 47 * 48 * All Rights Reserved. 49 * 50 * Permission is hereby granted, free of charge, to any person obtaining 51 * a copy of this software and associated documentation files (the 52 * "Software"), to deal in the Software without restriction, including 53 * without limitation on the rights to use, copy, modify, merge, 54 * publish, distribute, sublicense, and/or sell copies of the Software, 55 * and to permit persons to whom the Software is furnished to do so, 56 * subject to the following conditions: 57 * 58 * The above copyright notice and this permission notice (including the 59 * next paragraph) shall be included in all copies or substantial 60 * portions of the Software. 61 * 62 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 63 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 64 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 65 * NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR 66 * THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 67 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 68 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 69 * DEALINGS IN THE SOFTWARE. 70 */ 71 72 #include <sys/cdefs.h> 73 __KERNEL_RCSID(0, "$NetBSD: radeonfb.c,v 1.16 2007/08/03 05:02:23 macallan Exp $"); 74 75 #define RADEONFB_DEFAULT_DEPTH 32 76 77 #include <sys/param.h> 78 #include <sys/systm.h> 79 #include <sys/device.h> 80 #include <sys/malloc.h> 81 #include <machine/bus.h> 82 #include <sys/kernel.h> 83 #include <sys/lwp.h> 84 #include <sys/kauth.h> 85 86 #include <dev/wscons/wsdisplayvar.h> 87 #include <dev/wscons/wsconsio.h> 88 #include <dev/wsfont/wsfont.h> 89 #include <dev/rasops/rasops.h> 90 #include <dev/videomode/videomode.h> 91 #include <dev/videomode/edidvar.h> 92 #include <dev/wscons/wsdisplay_vconsvar.h> 93 94 #include <dev/pci/pcidevs.h> 95 #include <dev/pci/pcireg.h> 96 #include <dev/pci/pcivar.h> 97 #include <dev/pci/radeonfbreg.h> 98 #include <dev/pci/radeonfbvar.h> 99 #include "opt_radeonfb.h" 100 101 static int radeonfb_match(struct device *, struct cfdata *, void *); 102 static void radeonfb_attach(struct device *, struct device *, void *); 103 static int radeonfb_ioctl(void *, void *, unsigned long, void *, int, 104 struct lwp *); 105 static paddr_t radeonfb_mmap(void *, void *, off_t, int); 106 static int radeonfb_scratch_test(struct radeonfb_softc *, int, uint32_t); 107 static void radeonfb_loadbios(struct radeonfb_softc *, 108 struct pci_attach_args *); 109 110 static uintmax_t radeonfb_getprop_num(struct radeonfb_softc *, const char *, 111 uintmax_t); 112 static int radeonfb_getclocks(struct radeonfb_softc *); 113 static int radeonfb_gettmds(struct radeonfb_softc *); 114 static int radeonfb_calc_dividers(struct radeonfb_softc *, uint32_t, 115 uint32_t *, uint32_t *); 116 static int radeonfb_getconnectors(struct radeonfb_softc *); 117 static const struct videomode *radeonfb_modelookup(const char *); 118 static void radeonfb_init_screen(void *, struct vcons_screen *, int, long *); 119 static void radeonfb_pllwriteupdate(struct radeonfb_softc *, int); 120 static void radeonfb_pllwaitatomicread(struct radeonfb_softc *, int); 121 static void radeonfb_program_vclk(struct radeonfb_softc *, int, int); 122 static void radeonfb_modeswitch(struct radeonfb_display *); 123 static void radeonfb_setcrtc(struct radeonfb_display *, int); 124 static void radeonfb_init_misc(struct radeonfb_softc *); 125 static void radeonfb_set_fbloc(struct radeonfb_softc *); 126 static void radeonfb_init_palette(struct radeonfb_softc *, int); 127 static void radeonfb_r300cg_workaround(struct radeonfb_softc *); 128 129 static int radeonfb_isblank(struct radeonfb_display *); 130 static void radeonfb_blank(struct radeonfb_display *, int); 131 static int radeonfb_set_cursor(struct radeonfb_display *, 132 struct wsdisplay_cursor *); 133 static int radeonfb_set_curpos(struct radeonfb_display *, 134 struct wsdisplay_curpos *); 135 136 /* acceleration support */ 137 static void radeonfb_rectfill(struct radeonfb_display *, int dstx, int dsty, 138 int width, int height, uint32_t color); 139 static void radeonfb_bitblt(struct radeonfb_display *, int srcx, int srcy, 140 int dstx, int dsty, int width, int height, int rop, uint32_t mask); 141 static void radeonfb_feed_bytes(struct radeonfb_display *, int, uint8_t *); 142 static void radeonfb_setup_mono(struct radeonfb_display *, int, int, int, 143 int, uint32_t, uint32_t); 144 145 /* hw cursor support */ 146 static void radeonfb_cursor_cmap(struct radeonfb_display *); 147 static void radeonfb_cursor_shape(struct radeonfb_display *); 148 static void radeonfb_cursor_position(struct radeonfb_display *); 149 static void radeonfb_cursor_visible(struct radeonfb_display *); 150 static void radeonfb_cursor_update(struct radeonfb_display *, unsigned); 151 152 static void radeonfb_wait_fifo(struct radeonfb_softc *, int); 153 static void radeonfb_engine_idle(struct radeonfb_softc *); 154 static void radeonfb_engine_flush(struct radeonfb_softc *); 155 static void radeonfb_engine_reset(struct radeonfb_softc *); 156 static void radeonfb_engine_init(struct radeonfb_display *); 157 static inline void radeonfb_unclip(struct radeonfb_softc *); 158 159 static void radeonfb_eraserows(void *, int, int, long); 160 static void radeonfb_erasecols(void *, int, int, int, long); 161 static void radeonfb_copyrows(void *, int, int, int); 162 static void radeonfb_copycols(void *, int, int, int, int); 163 static void radeonfb_cursor(void *, int, int, int); 164 static void radeonfb_putchar(void *, int, int, unsigned, long); 165 static int radeonfb_allocattr(void *, int, int, int, long *); 166 167 static int radeonfb_get_backlight(struct radeonfb_display *); 168 static int radeonfb_set_backlight(struct radeonfb_display *, int); 169 static void radeonfb_lvds_callout(void *); 170 171 static struct videomode *radeonfb_best_refresh(struct videomode *, 172 struct videomode *); 173 static void radeonfb_pickres(struct radeonfb_display *, uint16_t *, 174 uint16_t *, int); 175 static const struct videomode *radeonfb_port_mode(struct radeonfb_softc *, 176 struct radeonfb_port *, int, int); 177 178 static int radeonfb_drm_print(void *, const char *); 179 180 #ifdef RADEON_DEBUG 181 int radeon_debug = 1; 182 #define DPRINTF(x) \ 183 if (radeon_debug) printf x 184 #define PRINTREG(r) DPRINTF((#r " = %08x\n", GET32(sc, r))) 185 #define PRINTPLL(r) DPRINTF((#r " = %08x\n", GETPLL(sc, r))) 186 #else 187 #define DPRINTF(x) 188 #define PRINTREG(r) 189 #define PRINTPLL(r) 190 #endif 191 192 #define ROUNDUP(x,y) (((x) + ((y) - 1)) & ~((y) - 1)) 193 194 #ifndef RADEON_DEFAULT_MODE 195 /* any reasonably modern display should handle this */ 196 #define RADEON_DEFAULT_MODE "1024x768x60" 197 //#define RADEON_DEFAULT_MODE "1280x1024x60" 198 #endif 199 200 const char *radeonfb_default_mode = RADEON_DEFAULT_MODE; 201 202 static struct { 203 int size; /* minimum memory size (MB) */ 204 int maxx; /* maximum x dimension */ 205 int maxy; /* maximum y dimension */ 206 int maxbpp; /* maximum bpp */ 207 int maxdisp; /* maximum logical display count */ 208 } radeonfb_limits[] = { 209 { 32, 2048, 1536, 32, 2 }, 210 { 16, 1600, 1200, 32, 2 }, 211 { 8, 1600, 1200, 32, 1 }, 212 { 0, 0, 0, 0, 0 }, 213 }; 214 215 static struct wsscreen_descr radeonfb_stdscreen = { 216 "fb", /* name */ 217 0, 0, /* ncols, nrows */ 218 NULL, /* textops */ 219 8, 16, /* fontwidth, fontheight */ 220 WSSCREEN_WSCOLORS, /* capabilities */ 221 0, /* modecookie */ 222 }; 223 224 struct wsdisplay_accessops radeonfb_accessops = { 225 radeonfb_ioctl, 226 radeonfb_mmap, 227 NULL, /* vcons_alloc_screen */ 228 NULL, /* vcons_free_screen */ 229 NULL, /* vcons_show_screen */ 230 NULL, /* load_font */ 231 NULL, /* pollc */ 232 NULL, /* scroll */ 233 }; 234 235 static struct { 236 uint16_t devid; 237 uint16_t family; 238 uint16_t flags; 239 } radeonfb_devices[] = 240 { 241 /* R100 family */ 242 { PCI_PRODUCT_ATI_RADEON_R100_QD, RADEON_R100, 0 }, 243 { PCI_PRODUCT_ATI_RADEON_R100_QE, RADEON_R100, 0 }, 244 { PCI_PRODUCT_ATI_RADEON_R100_QF, RADEON_R100, 0 }, 245 { PCI_PRODUCT_ATI_RADEON_R100_QG, RADEON_R100, 0 }, 246 247 /* RV100 family */ 248 { PCI_PRODUCT_ATI_RADEON_RV100_LY, RADEON_RV100, RFB_MOB }, 249 { PCI_PRODUCT_ATI_RADEON_RV100_LZ, RADEON_RV100, RFB_MOB }, 250 { PCI_PRODUCT_ATI_RADEON_RV100_QY, RADEON_RV100, 0 }, 251 { PCI_PRODUCT_ATI_RADEON_RV100_QZ, RADEON_RV100, 0 }, 252 253 /* RS100 family */ 254 { PCI_PRODUCT_ATI_RADEON_RS100_4136, RADEON_RS100, 0 }, 255 { PCI_PRODUCT_ATI_RADEON_RS100_4336, RADEON_RS100, RFB_MOB }, 256 257 /* RS200/RS250 family */ 258 { PCI_PRODUCT_ATI_RADEON_RS200_4337, RADEON_RS200, RFB_MOB }, 259 { PCI_PRODUCT_ATI_RADEON_RS200_A7, RADEON_RS200, 0 }, 260 { PCI_PRODUCT_ATI_RADEON_RS250_B7, RADEON_RS200, RFB_MOB }, 261 { PCI_PRODUCT_ATI_RADEON_RS250_D7, RADEON_RS200, 0 }, 262 263 /* R200 family */ 264 /* add more R200 products? , 5148 */ 265 { PCI_PRODUCT_ATI_RADEON_R200_BB, RADEON_R200, 0 }, 266 { PCI_PRODUCT_ATI_RADEON_R200_BC, RADEON_R200, 0 }, 267 { PCI_PRODUCT_ATI_RADEON_R200_QH, RADEON_R200, 0 }, 268 { PCI_PRODUCT_ATI_RADEON_R200_QL, RADEON_R200, 0 }, 269 { PCI_PRODUCT_ATI_RADEON_R200_QM, RADEON_R200, 0 }, 270 271 /* RV200 family */ 272 { PCI_PRODUCT_ATI_RADEON_RV200_LW, RADEON_RV200, RFB_MOB }, 273 { PCI_PRODUCT_ATI_RADEON_RV200_LX, RADEON_RV200, RFB_MOB }, 274 { PCI_PRODUCT_ATI_RADEON_RV200_QW, RADEON_RV200, 0 }, 275 { PCI_PRODUCT_ATI_RADEON_RV200_QX, RADEON_RV200, 0 }, 276 277 /* RV250 family */ 278 { PCI_PRODUCT_ATI_RADEON_RV250_4966, RADEON_RV250, 0 }, 279 { PCI_PRODUCT_ATI_RADEON_RV250_4967, RADEON_RV250, 0 }, 280 { PCI_PRODUCT_ATI_RADEON_RV250_4C64, RADEON_RV250, RFB_MOB }, 281 { PCI_PRODUCT_ATI_RADEON_RV250_4C66, RADEON_RV250, RFB_MOB }, 282 { PCI_PRODUCT_ATI_RADEON_RV250_4C67, RADEON_RV250, RFB_MOB }, 283 284 /* RS300 family */ 285 { PCI_PRODUCT_ATI_RADEON_RS300_X5, RADEON_RS300, 0 }, 286 { PCI_PRODUCT_ATI_RADEON_RS300_X4, RADEON_RS300, 0 }, 287 { PCI_PRODUCT_ATI_RADEON_RS300_7834, RADEON_RS300, 0 }, 288 { PCI_PRODUCT_ATI_RADEON_RS300_7835, RADEON_RS300, RFB_MOB }, 289 290 /* RV280 family */ 291 { PCI_PRODUCT_ATI_RADEON_RV280_5960, RADEON_RV280, 0 }, 292 { PCI_PRODUCT_ATI_RADEON_RV280_5961, RADEON_RV280, 0 }, 293 { PCI_PRODUCT_ATI_RADEON_RV280_5962, RADEON_RV280, 0 }, 294 { PCI_PRODUCT_ATI_RADEON_RV280_5963, RADEON_RV280, 0 }, 295 { PCI_PRODUCT_ATI_RADEON_RV280_5964, RADEON_RV280, 0 }, 296 { PCI_PRODUCT_ATI_RADEON_RV280_5C61, RADEON_RV280, RFB_MOB }, 297 { PCI_PRODUCT_ATI_RADEON_RV280_5C63, RADEON_RV280, RFB_MOB }, 298 299 /* R300 family */ 300 { PCI_PRODUCT_ATI_RADEON_R300_AD, RADEON_R300, 0 }, 301 { PCI_PRODUCT_ATI_RADEON_R300_AE, RADEON_R300, 0 }, 302 { PCI_PRODUCT_ATI_RADEON_R300_AF, RADEON_R300, 0 }, 303 { PCI_PRODUCT_ATI_RADEON_R300_AG, RADEON_R300, 0 }, 304 { PCI_PRODUCT_ATI_RADEON_R300_ND, RADEON_R300, 0 }, 305 { PCI_PRODUCT_ATI_RADEON_R300_NE, RADEON_R300, 0 }, 306 { PCI_PRODUCT_ATI_RADEON_R300_NF, RADEON_R300, 0 }, 307 { PCI_PRODUCT_ATI_RADEON_R300_NG, RADEON_R300, 0 }, 308 309 /* RV350/RV360 family */ 310 { PCI_PRODUCT_ATI_RADEON_RV350_AP, RADEON_RV350, 0 }, 311 { PCI_PRODUCT_ATI_RADEON_RV350_AQ, RADEON_RV350, 0 }, 312 { PCI_PRODUCT_ATI_RADEON_RV360_AR, RADEON_RV350, 0 }, 313 { PCI_PRODUCT_ATI_RADEON_RV350_AS, RADEON_RV350, 0 }, 314 { PCI_PRODUCT_ATI_RADEON_RV350_AT, RADEON_RV350, 0 }, 315 { PCI_PRODUCT_ATI_RADEON_RV350_AV, RADEON_RV350, 0 }, 316 { PCI_PRODUCT_ATI_RADEON_RV350_NP, RADEON_RV350, RFB_MOB }, 317 { PCI_PRODUCT_ATI_RADEON_RV350_NQ, RADEON_RV350, RFB_MOB }, 318 { PCI_PRODUCT_ATI_RADEON_RV350_NR, RADEON_RV350, RFB_MOB }, 319 { PCI_PRODUCT_ATI_RADEON_RV350_NS, RADEON_RV350, RFB_MOB }, 320 { PCI_PRODUCT_ATI_RADEON_RV350_NT, RADEON_RV350, RFB_MOB }, 321 { PCI_PRODUCT_ATI_RADEON_RV350_NV, RADEON_RV350, RFB_MOB }, 322 323 /* R350/R360 family */ 324 { PCI_PRODUCT_ATI_RADEON_R350_AH, RADEON_R350, 0 }, 325 { PCI_PRODUCT_ATI_RADEON_R350_AI, RADEON_R350, 0 }, 326 { PCI_PRODUCT_ATI_RADEON_R350_AJ, RADEON_R350, 0 }, 327 { PCI_PRODUCT_ATI_RADEON_R350_AK, RADEON_R350, 0 }, 328 { PCI_PRODUCT_ATI_RADEON_R350_NH, RADEON_R350, 0 }, 329 { PCI_PRODUCT_ATI_RADEON_R350_NI, RADEON_R350, 0 }, 330 { PCI_PRODUCT_ATI_RADEON_R350_NK, RADEON_R350, 0 }, 331 { PCI_PRODUCT_ATI_RADEON_R360_NJ, RADEON_R350, 0 }, 332 333 /* RV380/RV370 family */ 334 { PCI_PRODUCT_ATI_RADEON_RV380_3150, RADEON_RV380, RFB_MOB }, 335 { PCI_PRODUCT_ATI_RADEON_RV380_3154, RADEON_RV380, RFB_MOB }, 336 { PCI_PRODUCT_ATI_RADEON_RV380_3E50, RADEON_RV380, 0 }, 337 { PCI_PRODUCT_ATI_RADEON_RV380_3E54, RADEON_RV380, 0 }, 338 { PCI_PRODUCT_ATI_RADEON_RV370_5460, RADEON_RV380, RFB_MOB }, 339 { PCI_PRODUCT_ATI_RADEON_RV370_5464, RADEON_RV380, RFB_MOB }, 340 { PCI_PRODUCT_ATI_RADEON_RV370_5B60, RADEON_RV380, 0 }, 341 { PCI_PRODUCT_ATI_RADEON_RV370_5B64, RADEON_RV380, 0 }, 342 { PCI_PRODUCT_ATI_RADEON_RV370_5B65, RADEON_RV380, 0 }, 343 344 /* R420/R423 family */ 345 { PCI_PRODUCT_ATI_RADEON_R420_JH, RADEON_R420, 0 }, 346 { PCI_PRODUCT_ATI_RADEON_R420_JI, RADEON_R420, 0 }, 347 { PCI_PRODUCT_ATI_RADEON_R420_JJ, RADEON_R420, 0 }, 348 { PCI_PRODUCT_ATI_RADEON_R420_JK, RADEON_R420, 0 }, 349 { PCI_PRODUCT_ATI_RADEON_R420_JL, RADEON_R420, 0 }, 350 { PCI_PRODUCT_ATI_RADEON_R420_JM, RADEON_R420, 0 }, 351 { PCI_PRODUCT_ATI_RADEON_R420_JN, RADEON_R420, RFB_MOB }, 352 { PCI_PRODUCT_ATI_RADEON_R420_JP, RADEON_R420, 0 }, 353 { PCI_PRODUCT_ATI_RADEON_R423_UH, RADEON_R420, 0 }, 354 { PCI_PRODUCT_ATI_RADEON_R423_UI, RADEON_R420, 0 }, 355 { PCI_PRODUCT_ATI_RADEON_R423_UJ, RADEON_R420, 0 }, 356 { PCI_PRODUCT_ATI_RADEON_R423_UK, RADEON_R420, 0 }, 357 { PCI_PRODUCT_ATI_RADEON_R423_UQ, RADEON_R420, 0 }, 358 { PCI_PRODUCT_ATI_RADEON_R423_UR, RADEON_R420, 0 }, 359 { PCI_PRODUCT_ATI_RADEON_R423_UT, RADEON_R420, 0 }, 360 { PCI_PRODUCT_ATI_RADEON_R423_5D57, RADEON_R420, 0 }, 361 362 { 0, 0, 0 } 363 }; 364 365 static struct { 366 int divider; 367 int mask; 368 } radeonfb_dividers[] = { 369 { 1, 0 }, 370 { 2, 1 }, 371 { 3, 4 }, 372 { 4, 2 }, 373 { 6, 6 }, 374 { 8, 3 }, 375 { 12, 7 }, 376 { 0, 0 } 377 }; 378 379 /* 380 * This table taken from X11. 381 */ 382 static const struct { 383 int family; 384 struct radeon_tmds_pll plls[4]; 385 } radeonfb_tmds_pll[] = { 386 { RADEON_R100, {{12000, 0xa1b}, {-1, 0xa3f}}}, 387 { RADEON_RV100, {{12000, 0xa1b}, {-1, 0xa3f}}}, 388 { RADEON_RS100, {{0, 0}}}, 389 { RADEON_RV200, {{15000, 0xa1b}, {-1, 0xa3f}}}, 390 { RADEON_RS200, {{15000, 0xa1b}, {-1, 0xa3f}}}, 391 { RADEON_R200, {{15000, 0xa1b}, {-1, 0xa3f}}}, 392 { RADEON_RV250, {{15500, 0x81b}, {-1, 0x83f}}}, 393 { RADEON_RS300, {{0, 0}}}, 394 { RADEON_RV280, {{13000, 0x400f4}, {15000, 0x400f7}}}, 395 { RADEON_R300, {{-1, 0xb01cb}}}, 396 { RADEON_R350, {{-1, 0xb01cb}}}, 397 { RADEON_RV350, {{15000, 0xb0155}, {-1, 0xb01cb}}}, 398 { RADEON_RV380, {{15000, 0xb0155}, {-1, 0xb01cb}}}, 399 { RADEON_R420, {{-1, 0xb01cb}}}, 400 }; 401 402 #define RADEONFB_BACKLIGHT_MAX 255 /* Maximum backlight level. */ 403 404 405 CFATTACH_DECL(radeonfb, sizeof (struct radeonfb_softc), 406 radeonfb_match, radeonfb_attach, NULL, NULL); 407 408 static int 409 radeonfb_match(struct device *parent, struct cfdata *match, void *aux) 410 { 411 struct pci_attach_args *pa = aux; 412 int i; 413 414 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_ATI) 415 return 0; 416 417 for (i = 0; radeonfb_devices[i].devid; i++) { 418 if (PCI_PRODUCT(pa->pa_id) == radeonfb_devices[i].devid) 419 return 100; /* high to defeat VGA/VESA */ 420 } 421 422 return 0; 423 } 424 425 static void 426 radeonfb_attach(struct device *parent, struct device *dev, void *aux) 427 { 428 struct radeonfb_softc *sc = (struct radeonfb_softc *)dev; 429 struct pci_attach_args *pa = aux; 430 const char *mptr; 431 bus_size_t bsz; 432 pcireg_t screg; 433 int i, j, fg, bg, ul; 434 uint32_t v; 435 436 sc->sc_id = pa->pa_id; 437 for (i = 0; radeonfb_devices[i].devid; i++) { 438 if (PCI_PRODUCT(sc->sc_id) == radeonfb_devices[i].devid) 439 break; 440 } 441 442 pci_devinfo(sc->sc_id, pa->pa_class, 0, sc->sc_devinfo, 443 sizeof(sc->sc_devinfo)); 444 445 aprint_naive("\n"); 446 aprint_normal(": %s\n", sc->sc_devinfo); 447 448 KASSERT(radeonfb_devices[i].devid != 0); 449 sc->sc_pt = pa->pa_tag; 450 sc->sc_iot = pa->pa_iot; 451 sc->sc_pc = pa->pa_pc; 452 sc->sc_family = radeonfb_devices[i].family; 453 sc->sc_flags = radeonfb_devices[i].flags; 454 455 /* enable memory and IO access */ 456 screg = pci_conf_read(sc->sc_pc, sc->sc_pt, PCI_COMMAND_STATUS_REG); 457 screg |= PCI_FLAGS_IO_ENABLED | PCI_FLAGS_MEM_ENABLED; 458 pci_conf_write(sc->sc_pc, sc->sc_pt, PCI_COMMAND_STATUS_REG, screg); 459 460 /* 461 * Some flags are general to entire chip families, and rather 462 * than clutter up the table with them, we go ahead and set 463 * them here. 464 */ 465 switch (sc->sc_family) { 466 case RADEON_RS100: 467 case RADEON_RS200: 468 sc->sc_flags |= RFB_IGP | RFB_RV100; 469 break; 470 471 case RADEON_RV100: 472 case RADEON_RV200: 473 case RADEON_RV250: 474 case RADEON_RV280: 475 sc->sc_flags |= RFB_RV100; 476 break; 477 478 case RADEON_RS300: 479 sc->sc_flags |= RFB_SDAC | RFB_IGP | RFB_RV100; 480 break; 481 482 case RADEON_R300: 483 case RADEON_RV350: 484 case RADEON_R350: 485 case RADEON_RV380: 486 case RADEON_R420: 487 /* newer chips */ 488 sc->sc_flags |= RFB_R300; 489 break; 490 491 case RADEON_R100: 492 sc->sc_flags |= RFB_NCRTC2; 493 break; 494 } 495 496 /* 497 * XXX: to support true multihead, this must change. 498 */ 499 sc->sc_ndisplays = 1; 500 501 /* XXX: */ 502 if (!HAS_CRTC2(sc)) { 503 sc->sc_ndisplays = 1; 504 } 505 506 if (pci_mapreg_map(pa, RADEON_MAPREG_MMIO, PCI_MAPREG_TYPE_MEM, 0, 507 &sc->sc_regt, &sc->sc_regh, &sc->sc_regaddr, 508 &sc->sc_regsz) != 0) { 509 aprint_error("%s: unable to map registers!\n", XNAME(sc)); 510 goto error; 511 } 512 513 /* scratch register test... */ 514 if (radeonfb_scratch_test(sc, RADEON_BIOS_0_SCRATCH, 0x55555555) || 515 radeonfb_scratch_test(sc, RADEON_BIOS_0_SCRATCH, 0xaaaaaaaa)) { 516 aprint_error("%s: scratch register test failed!\n", XNAME(sc)); 517 goto error; 518 } 519 520 PRINTREG(RADEON_BIOS_4_SCRATCH); 521 PRINTREG(RADEON_FP_GEN_CNTL); 522 PRINTREG(RADEON_FP2_GEN_CNTL); 523 PRINTREG(RADEON_TMDS_CNTL); 524 PRINTREG(RADEON_TMDS_TRANSMITTER_CNTL); 525 PRINTREG(RADEON_TMDS_PLL_CNTL); 526 PRINTREG(RADEON_LVDS_GEN_CNTL); 527 PRINTREG(RADEON_FP_HORZ_STRETCH); 528 PRINTREG(RADEON_FP_VERT_STRETCH); 529 530 /* XXX: RV100 specific */ 531 PUT32(sc, RADEON_TMDS_PLL_CNTL, 0xa27); 532 533 PATCH32(sc, RADEON_TMDS_TRANSMITTER_CNTL, 534 RADEON_TMDS_TRANSMITTER_PLLEN, 535 RADEON_TMDS_TRANSMITTER_PLLEN | RADEON_TMDS_TRANSMITTER_PLLRST); 536 537 radeonfb_i2c_init(sc); 538 539 radeonfb_loadbios(sc, pa); 540 541 #ifdef RADEON_BIOS_INIT 542 if (radeonfb_bios_init(sc)) { 543 aprint_error("%s: BIOS inititialization failed\n", XNAME(sc)); 544 goto error; 545 } 546 #endif 547 548 if (radeonfb_getclocks(sc)) { 549 aprint_error("%s: Unable to get reference clocks from BIOS\n", 550 XNAME(sc)); 551 goto error; 552 } 553 554 if (radeonfb_gettmds(sc)) { 555 aprint_error("%s: Unable to identify TMDS PLL settings\n", 556 XNAME(sc)); 557 goto error; 558 } 559 560 aprint_verbose("%s: refclk = %d.%03d MHz, refdiv = %d " 561 "minpll = %d, maxpll = %d\n", XNAME(sc), 562 (int)sc->sc_refclk / 1000, (int)sc->sc_refclk % 1000, 563 (int)sc->sc_refdiv, (int)sc->sc_minpll, (int)sc->sc_maxpll); 564 565 radeonfb_getconnectors(sc); 566 567 radeonfb_set_fbloc(sc); 568 569 for (i = 0; radeonfb_limits[i].size; i++) { 570 if (sc->sc_memsz >= radeonfb_limits[i].size) { 571 sc->sc_maxx = radeonfb_limits[i].maxx; 572 sc->sc_maxy = radeonfb_limits[i].maxy; 573 sc->sc_maxbpp = radeonfb_limits[i].maxbpp; 574 /* framebuffer offset, start at a 4K page */ 575 sc->sc_fboffset = sc->sc_memsz / 576 radeonfb_limits[i].maxdisp; 577 /* 578 * we use the fbsize to figure out where we can store 579 * things like cursor data. 580 */ 581 sc->sc_fbsize = 582 ROUNDUP(ROUNDUP(sc->sc_maxx * sc->sc_maxbpp / 8 , 583 RADEON_STRIDEALIGN) * sc->sc_maxy, 584 4096); 585 break; 586 } 587 } 588 589 590 radeonfb_init_misc(sc); 591 radeonfb_init_palette(sc, 0); 592 if (HAS_CRTC2(sc)) 593 radeonfb_init_palette(sc, 1); 594 595 /* program the DAC wirings */ 596 for (i = 0; i < (HAS_CRTC2(sc) ? 2 : 1); i++) { 597 switch (sc->sc_ports[i].rp_dac_type) { 598 case RADEON_DAC_PRIMARY: 599 PATCH32(sc, RADEON_DAC_CNTL2, 600 i ? RADEON_DAC2_DAC_CLK_SEL : 0, 601 ~RADEON_DAC2_DAC_CLK_SEL); 602 break; 603 case RADEON_DAC_TVDAC: 604 /* we always use the TVDAC to drive a secondary analog 605 * CRT for now. if we ever support TV-out this will 606 * have to change. 607 */ 608 SET32(sc, RADEON_DAC_CNTL2, 609 RADEON_DAC2_DAC2_CLK_SEL); 610 PATCH32(sc, RADEON_DISP_HW_DEBUG, 611 i ? 0 : RADEON_CRT2_DISP1_SEL, 612 ~RADEON_CRT2_DISP1_SEL); 613 break; 614 } 615 } 616 PRINTREG(RADEON_DAC_CNTL2); 617 PRINTREG(RADEON_DISP_HW_DEBUG); 618 619 /* other DAC programming */ 620 v = GET32(sc, RADEON_DAC_CNTL); 621 v &= (RADEON_DAC_RANGE_CNTL_MASK | RADEON_DAC_BLANKING); 622 v |= RADEON_DAC_MASK_ALL | RADEON_DAC_8BIT_EN; 623 PUT32(sc, RADEON_DAC_CNTL, v); 624 PRINTREG(RADEON_DAC_CNTL); 625 626 /* XXX: this may need more investigation */ 627 PUT32(sc, RADEON_TV_DAC_CNTL, 0x00280203); 628 PRINTREG(RADEON_TV_DAC_CNTL); 629 630 /* enable TMDS */ 631 SET32(sc, RADEON_FP_GEN_CNTL, 632 RADEON_FP_TMDS_EN | 633 RADEON_FP_CRTC_DONT_SHADOW_VPAR | 634 RADEON_FP_CRTC_DONT_SHADOW_HEND); 635 CLR32(sc, RADEON_FP_GEN_CNTL, RADEON_FP_SEL_CRTC2); 636 if (HAS_CRTC2(sc)) 637 SET32(sc, RADEON_FP2_GEN_CNTL, RADEON_FP2_SRC_SEL_CRTC2); 638 639 /* 640 * we use bus_space_map instead of pci_mapreg, because we don't 641 * need the full aperature space. no point in wasting virtual 642 * address space we don't intend to use, right? 643 */ 644 if ((sc->sc_memsz < (4096 * 1024)) || 645 (pci_mapreg_info(sc->sc_pc, sc->sc_pt, RADEON_MAPREG_VRAM, 646 PCI_MAPREG_TYPE_MEM, &sc->sc_memaddr, &bsz, NULL) != 0) || 647 (bsz < sc->sc_memsz)) { 648 sc->sc_memsz = 0; 649 aprint_error("%s: Bad frame buffer configuration\n", 650 XNAME(sc)); 651 goto error; 652 } 653 654 /* 64 MB should be enough -- more just wastes map entries */ 655 if (sc->sc_memsz > (64 << 20)) 656 sc->sc_memsz = (64 << 20); 657 658 sc->sc_memt = pa->pa_memt; 659 if (bus_space_map(sc->sc_memt, sc->sc_memaddr, sc->sc_memsz, 660 BUS_SPACE_MAP_LINEAR, &sc->sc_memh) != 0) { 661 sc->sc_memsz = 0; 662 aprint_error("%s: Unable to map frame buffer\n", XNAME(sc)); 663 goto error; 664 } 665 666 aprint_normal("%s: %d MB aperture at 0x%08x, " 667 "%d KB registers at 0x%08x\n", XNAME(sc), 668 (int)sc->sc_memsz >> 20, (unsigned)sc->sc_memaddr, 669 (int)sc->sc_regsz >> 10, (unsigned)sc->sc_regaddr); 670 671 /* setup default video mode from devprop (allows PROM override) */ 672 sc->sc_defaultmode = radeonfb_default_mode; 673 if (prop_dictionary_get_cstring_nocopy(device_properties(&sc->sc_dev), 674 "videomode", &mptr)) { 675 676 strncpy(sc->sc_modebuf, mptr, sizeof(sc->sc_modebuf)); 677 sc->sc_defaultmode = sc->sc_modebuf; 678 } 679 680 /* initialize some basic display parameters */ 681 for (i = 0; i < sc->sc_ndisplays; i++) { 682 struct radeonfb_display *dp = &sc->sc_displays[i]; 683 struct rasops_info *ri; 684 long defattr; 685 struct wsemuldisplaydev_attach_args aa; 686 687 /* 688 * Figure out how many "displays" (desktops) we are going to 689 * support. If more than one, then each CRTC gets its own 690 * programming. 691 * 692 * XXX: this code needs to change to support mergedfb. 693 * XXX: would be nice to allow this to be overridden 694 */ 695 if (HAS_CRTC2(sc) && (sc->sc_ndisplays == 1)) { 696 DPRINTF(("dual crtcs!\n")); 697 dp->rd_ncrtcs = 2; 698 dp->rd_crtcs[0].rc_number = 0; 699 dp->rd_crtcs[1].rc_number = 1; 700 } else { 701 dp->rd_ncrtcs = 1; 702 dp->rd_crtcs[0].rc_number = i; 703 } 704 705 /* set up port pointer */ 706 for (j = 0; j < dp->rd_ncrtcs; j++) { 707 dp->rd_crtcs[j].rc_port = 708 &sc->sc_ports[dp->rd_crtcs[j].rc_number]; 709 } 710 711 dp->rd_softc = sc; 712 dp->rd_wsmode = WSDISPLAYIO_MODE_EMUL; 713 dp->rd_bg = WS_DEFAULT_BG; 714 #if 0 715 dp->rd_bpp = sc->sc_maxbpp; /* XXX: for now */ 716 #else 717 dp->rd_bpp = RADEONFB_DEFAULT_DEPTH; /* XXX */ 718 #endif 719 /* for text mode, we pick a resolution that won't 720 * require panning */ 721 radeonfb_pickres(dp, &dp->rd_virtx, &dp->rd_virty, 0); 722 723 aprint_normal("%s: display %d: " 724 "initial virtual resolution %dx%d at %d bpp\n", 725 XNAME(sc), i, dp->rd_virtx, dp->rd_virty, dp->rd_bpp); 726 727 /* now select the *video mode* that we will use */ 728 for (j = 0; j < dp->rd_ncrtcs; j++) { 729 const struct videomode *vmp; 730 vmp = radeonfb_port_mode(sc, dp->rd_crtcs[j].rc_port, 731 dp->rd_virtx, dp->rd_virty); 732 733 /* 734 * virtual resolution should be at least as high as 735 * physical 736 */ 737 if (dp->rd_virtx < vmp->hdisplay || 738 dp->rd_virty < vmp->vdisplay) { 739 dp->rd_virtx = vmp->hdisplay; 740 dp->rd_virty = vmp->vdisplay; 741 } 742 743 dp->rd_crtcs[j].rc_videomode = *vmp; 744 printf("%s: port %d: physical %dx%d %dHz\n", 745 XNAME(sc), j, vmp->hdisplay, vmp->vdisplay, 746 DIVIDE(DIVIDE(vmp->dot_clock * 1000, 747 vmp->htotal), vmp->vtotal)); 748 } 749 750 /* N.B.: radeon wants 64-byte aligned stride */ 751 dp->rd_stride = dp->rd_virtx * dp->rd_bpp / 8; 752 dp->rd_stride = ROUNDUP(dp->rd_stride, RADEON_STRIDEALIGN); 753 754 dp->rd_offset = sc->sc_fboffset * i; 755 dp->rd_fbptr = (vaddr_t)bus_space_vaddr(sc->sc_memt, 756 sc->sc_memh) + dp->rd_offset; 757 dp->rd_curoff = sc->sc_fbsize; 758 dp->rd_curptr = dp->rd_fbptr + dp->rd_curoff; 759 760 DPRINTF(("fpbtr = %p\n", (void *)dp->rd_fbptr)); 761 762 switch (dp->rd_bpp) { 763 case 8: 764 dp->rd_format = 2; 765 break; 766 case 32: 767 dp->rd_format = 6; 768 break; 769 default: 770 aprint_error("%s: bad depth %d\n", XNAME(sc), 771 dp->rd_bpp); 772 goto error; 773 } 774 775 printf("init engine\n"); 776 /* XXX: this seems suspicious - per display engine 777 initialization? */ 778 radeonfb_engine_init(dp); 779 780 /* copy the template into place */ 781 dp->rd_wsscreens_storage[0] = radeonfb_stdscreen; 782 dp->rd_wsscreens = dp->rd_wsscreens_storage; 783 784 /* and make up the list */ 785 dp->rd_wsscreenlist.nscreens = 1; 786 dp->rd_wsscreenlist.screens = 787 (const struct wsscreen_descr **)&dp->rd_wsscreens; 788 789 vcons_init(&dp->rd_vd, dp, dp->rd_wsscreens, 790 &radeonfb_accessops); 791 792 dp->rd_vd.init_screen = radeonfb_init_screen; 793 794 dp->rd_console = 1; 795 796 dp->rd_vscreen.scr_flags |= VCONS_SCREEN_IS_STATIC; 797 798 799 vcons_init_screen(&dp->rd_vd, &dp->rd_vscreen, 800 dp->rd_console, &defattr); 801 802 ri = &dp->rd_vscreen.scr_ri; 803 804 /* clear the screen */ 805 rasops_unpack_attr(defattr, &fg, &bg, &ul); 806 radeonfb_rectfill(dp, 0, 0, ri->ri_width, ri->ri_height, 807 ri->ri_devcmap[bg & 0xf]); 808 809 dp->rd_wsscreens->textops = &ri->ri_ops; 810 dp->rd_wsscreens->capabilities = ri->ri_caps; 811 dp->rd_wsscreens->nrows = ri->ri_rows; 812 dp->rd_wsscreens->ncols = ri->ri_cols; 813 814 #ifdef SPLASHSCREEN 815 dp->rd_splash.si_depth = ri->ri_depth; 816 dp->rd_splash.si_bits = ri->ri_bits; 817 dp->rd_splash.si_hwbits = ri->ri_hwbits; 818 dp->rd_splash.si_width = ri->ri_width; 819 dp->rd_splash.si_height = ri->ri_height; 820 dp->rd_splash.si_stride = ri->ri_stride; 821 dp->rd_splash.si_fillrect = NULL; 822 #endif 823 if (dp->rd_console) { 824 825 wsdisplay_cnattach(dp->rd_wsscreens, ri, 0, 0, 826 defattr); 827 #ifdef SPLASHSCREEN 828 splash_render(&dp->rd_splash, 829 SPLASH_F_CENTER|SPLASH_F_FILL); 830 #endif 831 832 #ifdef SPLASHSCREEN_PROGRESS 833 dp->rd_progress.sp_top = (dp->rd_virty / 8) * 7; 834 dp->rd_progress.sp_width = (dp->rd_virtx / 4) * 3; 835 dp->rd_progress.sp_left = (dp->rd_virtx - 836 dp->rd_progress.sp_width) / 2; 837 dp->rd_progress.sp_height = 20; 838 dp->rd_progress.sp_state = -1; 839 dp->rd_progress.sp_si = &dp->rd_splash; 840 splash_progress_init(&dp->rd_progress); 841 SCREEN_DISABLE_DRAWING(&dp->rd_vscreen); 842 #endif 843 844 } else { 845 846 /* 847 * since we're not the console we can postpone 848 * the rest until someone actually allocates a 849 * screen for us. but we do clear the screen 850 * at least. 851 */ 852 memset(ri->ri_bits, 0, 1024); 853 854 radeonfb_modeswitch(dp); 855 #ifdef SPLASHSCREEN 856 splash_render(&dp->rd_splash, 857 SPLASH_F_CENTER|SPLASH_F_FILL); 858 SCREEN_DISABLE_DRAWING(&dp->rd_vscreen); 859 #endif 860 } 861 862 aa.console = dp->rd_console; 863 aa.scrdata = &dp->rd_wsscreenlist; 864 aa.accessops = &radeonfb_accessops; 865 aa.accesscookie = &dp->rd_vd; 866 867 config_found(&sc->sc_dev, &aa, wsemuldisplaydevprint); 868 radeonfb_blank(dp, 0); 869 870 /* Initialise delayed lvds operations for backlight. */ 871 callout_init(&dp->rd_bl_lvds_co, 0); 872 callout_setfunc(&dp->rd_bl_lvds_co, 873 radeonfb_lvds_callout, dp); 874 } 875 876 config_found_ia(dev, "drm", aux, radeonfb_drm_print); 877 878 return; 879 880 error: 881 if (sc->sc_biossz) 882 free(sc->sc_bios, M_DEVBUF); 883 884 if (sc->sc_regsz) 885 bus_space_unmap(sc->sc_regt, sc->sc_regh, sc->sc_regsz); 886 887 if (sc->sc_memsz) 888 bus_space_unmap(sc->sc_memt, sc->sc_memh, sc->sc_memsz); 889 } 890 891 static int 892 radeonfb_drm_print(void *aux, const char *pnp) 893 { 894 if (pnp) 895 aprint_normal("direct rendering for %s", pnp); 896 return (UNSUPP); 897 } 898 899 int 900 radeonfb_ioctl(void *v, void *vs, 901 unsigned long cmd, void *d, int flag, struct lwp *l) 902 { 903 struct vcons_data *vd; 904 struct radeonfb_display *dp; 905 struct radeonfb_softc *sc; 906 struct wsdisplay_param *param; 907 908 vd = (struct vcons_data *)v; 909 dp = (struct radeonfb_display *)vd->cookie; 910 sc = dp->rd_softc; 911 912 switch (cmd) { 913 case WSDISPLAYIO_GTYPE: 914 *(unsigned *)d = WSDISPLAY_TYPE_PCIMISC; 915 return 0; 916 917 case WSDISPLAYIO_GINFO: 918 if (vd->active != NULL) { 919 struct wsdisplay_fbinfo *fb; 920 fb = (struct wsdisplay_fbinfo *)d; 921 fb->width = dp->rd_virtx; 922 fb->height = dp->rd_virty; 923 fb->depth = dp->rd_bpp; 924 fb->cmsize = 256; 925 return 0; 926 } else 927 return ENODEV; 928 case WSDISPLAYIO_GVIDEO: 929 if (radeonfb_isblank(dp)) 930 *(unsigned *)d = WSDISPLAYIO_VIDEO_OFF; 931 else 932 *(unsigned *)d = WSDISPLAYIO_VIDEO_ON; 933 return 0; 934 935 case WSDISPLAYIO_SVIDEO: 936 radeonfb_blank(dp, 937 (*(unsigned int *)d == WSDISPLAYIO_VIDEO_OFF)); 938 return 0; 939 940 case WSDISPLAYIO_GETCMAP: 941 #if 0 942 if (dp->rd_bpp == 8) 943 return radeonfb_getcmap(sc, 944 (struct wsdisplay_cmap *)d); 945 #endif 946 return EINVAL; 947 948 case WSDISPLAYIO_PUTCMAP: 949 #if 0 950 if (dp->rd_bpp == 8) 951 return radeonfb_putcmap(sc, 952 (struct wsdisplay_cmap *)d); 953 #endif 954 return EINVAL; 955 956 case WSDISPLAYIO_LINEBYTES: 957 *(unsigned *)d = dp->rd_stride; 958 return 0; 959 960 case WSDISPLAYIO_SMODE: 961 if (*(int *)d != dp->rd_wsmode) { 962 dp->rd_wsmode = *(int *)d; 963 if ((dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) && 964 (dp->rd_vd.active)) { 965 vcons_redraw_screen(dp->rd_vd.active); 966 } 967 } 968 return 0; 969 970 case WSDISPLAYIO_GCURMAX: 971 ((struct wsdisplay_curpos *)d)->x = RADEON_CURSORMAXX; 972 ((struct wsdisplay_curpos *)d)->y = RADEON_CURSORMAXY; 973 return 0; 974 975 case WSDISPLAYIO_SCURSOR: 976 return radeonfb_set_cursor(dp, (struct wsdisplay_cursor *)d); 977 978 case WSDISPLAYIO_GCURSOR: 979 return EPASSTHROUGH; 980 981 case WSDISPLAYIO_GCURPOS: 982 ((struct wsdisplay_curpos *)d)->x = dp->rd_cursor.rc_pos.x; 983 ((struct wsdisplay_curpos *)d)->y = dp->rd_cursor.rc_pos.y; 984 return 0; 985 986 case WSDISPLAYIO_SCURPOS: 987 return radeonfb_set_curpos(dp, (struct wsdisplay_curpos *)d); 988 989 case WSDISPLAYIO_SSPLASH: 990 #if defined(SPLASHSCREEN) 991 if (*(int *)d == 1) { 992 SCREEN_DISABLE_DRAWING(&dp->rd_vscreen); 993 splash_render(&dp->rd_splash, 994 SPLASH_F_CENTER|SPLASH_F_FILL); 995 } else 996 SCREEN_ENABLE_DRAWING(&dp->rd_vscreen); 997 return 0; 998 #else 999 return ENODEV; 1000 #endif 1001 case WSDISPLAYIO_SPROGRESS: 1002 #if defined(SPLASHSCREEN) && defined(SPLASHSCREEN_PROGRESS) 1003 dp->rd_progress.sp_force = 1; 1004 splash_progress_update(&dp->rd_progress); 1005 dp->rd_progress.sp_force = 0; 1006 return 0; 1007 #else 1008 return ENODEV; 1009 #endif 1010 case WSDISPLAYIO_GETPARAM: 1011 param = (struct wsdisplay_param *)d; 1012 if (param->param == WSDISPLAYIO_PARAM_BACKLIGHT) { 1013 param->min = 0; 1014 param->max = RADEONFB_BACKLIGHT_MAX; 1015 param->curval = radeonfb_get_backlight(dp); 1016 return 0; 1017 } 1018 return EPASSTHROUGH; 1019 1020 case WSDISPLAYIO_SETPARAM: 1021 param = (struct wsdisplay_param *)d; 1022 if (param->param == WSDISPLAYIO_PARAM_BACKLIGHT) { 1023 return radeonfb_set_backlight(dp, param->curval); 1024 } 1025 return EPASSTHROUGH; 1026 1027 default: 1028 return EPASSTHROUGH; 1029 } 1030 } 1031 1032 paddr_t 1033 radeonfb_mmap(void *v, void *vs, off_t offset, int prot) 1034 { 1035 struct vcons_data *vd; 1036 struct radeonfb_display *dp; 1037 struct radeonfb_softc *sc; 1038 #ifdef RADEONFB_MMAP_BARS 1039 struct lwp *me; 1040 #endif 1041 paddr_t pa; 1042 1043 vd = (struct vcons_data *)v; 1044 dp = (struct radeonfb_display *)vd->cookie; 1045 sc = dp->rd_softc; 1046 1047 /* XXX: note that we don't allow mapping of registers right now */ 1048 /* XXX: this means that the XFree86 radeon driver won't work */ 1049 1050 if ((offset >= 0) && (offset < (dp->rd_virty * dp->rd_stride))) { 1051 pa = bus_space_mmap(sc->sc_memt, 1052 sc->sc_memaddr + dp->rd_offset + offset, 0, 1053 prot, BUS_SPACE_MAP_LINEAR); 1054 return pa; 1055 } 1056 1057 #ifdef RADEONFB_MMAP_BARS 1058 /* 1059 * restrict all other mappings to processes with superuser privileges 1060 * or the kernel itself 1061 */ 1062 me = curlwp; 1063 if (me != NULL) { 1064 if (kauth_authorize_generic(me->l_cred, KAUTH_GENERIC_ISSUSER, 1065 NULL) != 0) { 1066 printf("%s: mmap() rejected.\n", sc->sc_dev.dv_xname); 1067 return -1; 1068 } 1069 } 1070 1071 if ((offset >= sc->sc_regaddr) && 1072 (offset < sc->sc_regaddr + sc->sc_regsz)) { 1073 return bus_space_mmap(sc->sc_regt, offset, 0, prot, 1074 BUS_SPACE_MAP_LINEAR); 1075 } 1076 1077 if ((offset >= sc->sc_memaddr) && 1078 (offset < sc->sc_memaddr + sc->sc_memsz)) { 1079 return bus_space_mmap(sc->sc_memt, offset, 0, prot, 1080 BUS_SPACE_MAP_LINEAR); 1081 } 1082 1083 #ifdef macppc 1084 /* allow mapping of IO space */ 1085 if ((offset >= 0xf2000000) && (offset < 0xf2800000)) { 1086 pa = bus_space_mmap(sc->sc_iot, offset - 0xf2000000, 0, prot, 1087 0); 1088 return pa; 1089 } 1090 #endif /* macppc */ 1091 1092 #endif /* RADEONFB_MMAP_BARS */ 1093 1094 return -1; 1095 } 1096 1097 static void 1098 radeonfb_loadbios(struct radeonfb_softc *sc, struct pci_attach_args *pa) 1099 { 1100 bus_space_tag_t romt; 1101 bus_space_handle_t romh, biosh; 1102 bus_size_t romsz; 1103 bus_addr_t ptr; 1104 1105 if (pci_mapreg_map(pa, PCI_MAPREG_ROM, PCI_MAPREG_TYPE_ROM, 1106 BUS_SPACE_MAP_PREFETCHABLE, &romt, &romh, NULL, &romsz) != 0) { 1107 aprint_verbose("%s: unable to map BIOS!\n", XNAME(sc)); 1108 return; 1109 } 1110 1111 pci_find_rom(pa, romt, romh, PCI_ROM_CODE_TYPE_X86, &biosh, 1112 &sc->sc_biossz); 1113 if (sc->sc_biossz == 0) { 1114 aprint_verbose("%s: Video BIOS not present\n", XNAME(sc)); 1115 return; 1116 } 1117 1118 sc->sc_bios = malloc(sc->sc_biossz, M_DEVBUF, M_WAITOK); 1119 bus_space_read_region_1(romt, biosh, 0, sc->sc_bios, sc->sc_biossz); 1120 1121 /* unmap the PCI expansion rom */ 1122 bus_space_unmap(romt, romh, romsz); 1123 1124 /* turn off rom decoder now */ 1125 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM, 1126 pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM) & 1127 ~PCI_MAPREG_ROM_ENABLE); 1128 1129 ptr = GETBIOS16(sc, 0x48); 1130 if ((GETBIOS32(sc, ptr + 4) == 0x41544f4d /* "ATOM" */) || 1131 (GETBIOS32(sc, ptr + 4) == 0x4d4f5441 /* "MOTA" */)) { 1132 sc->sc_flags |= RFB_ATOM; 1133 } 1134 1135 aprint_verbose("%s: Found %d KB %s BIOS\n", XNAME(sc), 1136 (unsigned)sc->sc_biossz >> 10, IS_ATOM(sc) ? "ATOM" : "Legacy"); 1137 } 1138 1139 1140 uint32_t 1141 radeonfb_get32(struct radeonfb_softc *sc, uint32_t reg) 1142 { 1143 1144 return bus_space_read_4(sc->sc_regt, sc->sc_regh, reg); 1145 } 1146 1147 void 1148 radeonfb_put32(struct radeonfb_softc *sc, uint32_t reg, uint32_t val) 1149 { 1150 1151 bus_space_write_4(sc->sc_regt, sc->sc_regh, reg, val); 1152 } 1153 1154 void 1155 radeonfb_mask32(struct radeonfb_softc *sc, uint32_t reg, 1156 uint32_t andmask, uint32_t ormask) 1157 { 1158 int s; 1159 uint32_t val; 1160 1161 s = splhigh(); 1162 val = radeonfb_get32(sc, reg); 1163 val = (val & andmask) | ormask; 1164 radeonfb_put32(sc, reg, val); 1165 splx(s); 1166 } 1167 1168 uint32_t 1169 radeonfb_getindex(struct radeonfb_softc *sc, uint32_t idx) 1170 { 1171 int s; 1172 uint32_t val; 1173 1174 s = splhigh(); 1175 radeonfb_put32(sc, RADEON_MM_INDEX, idx); 1176 val = radeonfb_get32(sc, RADEON_MM_DATA); 1177 splx(s); 1178 1179 return (val); 1180 } 1181 1182 void 1183 radeonfb_putindex(struct radeonfb_softc *sc, uint32_t idx, uint32_t val) 1184 { 1185 int s; 1186 1187 s = splhigh(); 1188 radeonfb_put32(sc, RADEON_MM_INDEX, idx); 1189 radeonfb_put32(sc, RADEON_MM_DATA, val); 1190 splx(s); 1191 } 1192 1193 void 1194 radeonfb_maskindex(struct radeonfb_softc *sc, uint32_t idx, 1195 uint32_t andmask, uint32_t ormask) 1196 { 1197 int s; 1198 uint32_t val; 1199 1200 s = splhigh(); 1201 radeonfb_put32(sc, RADEON_MM_INDEX, idx); 1202 val = radeonfb_get32(sc, RADEON_MM_DATA); 1203 val = (val & andmask) | ormask; 1204 radeonfb_put32(sc, RADEON_MM_DATA, val); 1205 splx(s); 1206 } 1207 1208 uint32_t 1209 radeonfb_getpll(struct radeonfb_softc *sc, uint32_t idx) 1210 { 1211 int s; 1212 uint32_t val; 1213 1214 s = splhigh(); 1215 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, idx & 0x3f); 1216 val = radeonfb_get32(sc, RADEON_CLOCK_CNTL_DATA); 1217 if (HAS_R300CG(sc)) 1218 radeonfb_r300cg_workaround(sc); 1219 splx(s); 1220 1221 return (val); 1222 } 1223 1224 void 1225 radeonfb_putpll(struct radeonfb_softc *sc, uint32_t idx, uint32_t val) 1226 { 1227 int s; 1228 1229 s = splhigh(); 1230 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, (idx & 0x3f) | 1231 RADEON_PLL_WR_EN); 1232 radeonfb_put32(sc, RADEON_CLOCK_CNTL_DATA, val); 1233 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, 0); 1234 splx(s); 1235 } 1236 1237 void 1238 radeonfb_maskpll(struct radeonfb_softc *sc, uint32_t idx, 1239 uint32_t andmask, uint32_t ormask) 1240 { 1241 int s; 1242 uint32_t val; 1243 1244 s = splhigh(); 1245 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, (idx & 0x3f) | 1246 RADEON_PLL_WR_EN); 1247 val = radeonfb_get32(sc, RADEON_CLOCK_CNTL_DATA); 1248 val = (val & andmask) | ormask; 1249 radeonfb_put32(sc, RADEON_CLOCK_CNTL_DATA, val); 1250 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, 0); 1251 splx(s); 1252 } 1253 1254 int 1255 radeonfb_scratch_test(struct radeonfb_softc *sc, int reg, uint32_t v) 1256 { 1257 uint32_t saved; 1258 1259 saved = GET32(sc, reg); 1260 PUT32(sc, reg, v); 1261 if (GET32(sc, reg) != v) { 1262 return -1; 1263 } 1264 PUT32(sc, reg, saved); 1265 return 0; 1266 } 1267 1268 uintmax_t 1269 radeonfb_getprop_num(struct radeonfb_softc *sc, const char *name, 1270 uintmax_t defval) 1271 { 1272 prop_number_t pn; 1273 pn = prop_dictionary_get(device_properties(&sc->sc_dev), name); 1274 if (pn == NULL) { 1275 return defval; 1276 } 1277 KASSERT(prop_object_type(pn) == PROP_TYPE_NUMBER); 1278 return (prop_number_integer_value(pn)); 1279 } 1280 1281 int 1282 radeonfb_getclocks(struct radeonfb_softc *sc) 1283 { 1284 bus_addr_t ptr; 1285 int refclk = 0; 1286 int refdiv = 0; 1287 int minpll = 0; 1288 int maxpll = 0; 1289 1290 /* load initial property values if port/board provides them */ 1291 refclk = radeonfb_getprop_num(sc, "refclk", 0) & 0xffff; 1292 refdiv = radeonfb_getprop_num(sc, "refdiv", 0) & 0xffff; 1293 minpll = radeonfb_getprop_num(sc, "minpll", 0) & 0xffffffffU; 1294 maxpll = radeonfb_getprop_num(sc, "maxpll", 0) & 0xffffffffU; 1295 1296 if (refclk && refdiv && minpll && maxpll) 1297 goto dontprobe; 1298 1299 if (!sc->sc_biossz) { 1300 /* no BIOS */ 1301 aprint_verbose("%s: No video BIOS, using default clocks\n", 1302 XNAME(sc)); 1303 if (IS_IGP(sc)) 1304 refclk = refclk ? refclk : 1432; 1305 else 1306 refclk = refclk ? refclk : 2700; 1307 refdiv = refdiv ? refdiv : 12; 1308 minpll = minpll ? minpll : 12500; 1309 maxpll = maxpll ? maxpll : 35000; 1310 } else if (IS_ATOM(sc)) { 1311 /* ATOM BIOS */ 1312 ptr = GETBIOS16(sc, 0x48); 1313 ptr = GETBIOS16(sc, ptr + 32); /* aka MasterDataStart */ 1314 ptr = GETBIOS16(sc, ptr + 12); /* pll info block */ 1315 refclk = refclk ? refclk : GETBIOS16(sc, ptr + 82); 1316 minpll = minpll ? minpll : GETBIOS16(sc, ptr + 78); 1317 maxpll = maxpll ? maxpll : GETBIOS16(sc, ptr + 32); 1318 /* 1319 * ATOM BIOS doesn't supply a reference divider, so we 1320 * have to probe for it. 1321 */ 1322 if (refdiv < 2) 1323 refdiv = GETPLL(sc, RADEON_PPLL_REF_DIV) & 1324 RADEON_PPLL_REF_DIV_MASK; 1325 /* 1326 * if probe is zero, just assume one that should work 1327 * for most parts 1328 */ 1329 if (refdiv < 2) 1330 refdiv = 12; 1331 1332 } else { 1333 /* Legacy BIOS */ 1334 ptr = GETBIOS16(sc, 0x48); 1335 ptr = GETBIOS16(sc, ptr + 0x30); 1336 refclk = refclk ? refclk : GETBIOS16(sc, ptr + 0x0E); 1337 refdiv = refdiv ? refdiv : GETBIOS16(sc, ptr + 0x10); 1338 minpll = minpll ? minpll : GETBIOS32(sc, ptr + 0x12); 1339 maxpll = maxpll ? maxpll : GETBIOS32(sc, ptr + 0x16); 1340 } 1341 1342 1343 dontprobe: 1344 sc->sc_refclk = refclk * 10; 1345 sc->sc_refdiv = refdiv; 1346 sc->sc_minpll = minpll * 10; 1347 sc->sc_maxpll = maxpll * 10; 1348 return 0; 1349 } 1350 1351 int 1352 radeonfb_calc_dividers(struct radeonfb_softc *sc, uint32_t dotclock, 1353 uint32_t *postdivbit, uint32_t *feedbackdiv) 1354 { 1355 int i; 1356 uint32_t outfreq; 1357 int div; 1358 1359 DPRINTF(("dot clock: %u\n", dotclock)); 1360 for (i = 0; (div = radeonfb_dividers[i].divider) != 0; i++) { 1361 outfreq = div * dotclock; 1362 if ((outfreq >= sc->sc_minpll) && 1363 (outfreq <= sc->sc_maxpll)) { 1364 DPRINTF(("outfreq: %u\n", outfreq)); 1365 *postdivbit = 1366 ((uint32_t)radeonfb_dividers[i].mask << 16); 1367 DPRINTF(("post divider: %d (mask %x)\n", div, 1368 *postdivbit)); 1369 break; 1370 } 1371 } 1372 1373 if (div == 0) 1374 return 1; 1375 1376 *feedbackdiv = DIVIDE(sc->sc_refdiv * outfreq, sc->sc_refclk); 1377 DPRINTF(("feedback divider: %d\n", *feedbackdiv)); 1378 return 0; 1379 } 1380 1381 #if 0 1382 #ifdef RADEON_DEBUG 1383 static void 1384 dump_buffer(const char *pfx, void *buffer, unsigned int size) 1385 { 1386 char asc[17]; 1387 unsigned ptr = (unsigned)buffer; 1388 char *start = (char *)(ptr & ~0xf); 1389 char *end = (char *)(ptr + size); 1390 1391 end = (char *)(((unsigned)end + 0xf) & ~0xf); 1392 1393 if (pfx == NULL) { 1394 pfx = ""; 1395 } 1396 1397 while (start < end) { 1398 unsigned offset = (unsigned)start & 0xf; 1399 if (offset == 0) { 1400 printf("%s%x: ", pfx, (unsigned)start); 1401 } 1402 if (((unsigned)start < ptr) || 1403 ((unsigned)start >= (ptr + size))) { 1404 printf(" "); 1405 asc[offset] = ' '; 1406 } else { 1407 printf("%02x", *(unsigned char *)start); 1408 if ((*start >= ' ') && (*start <= '~')) { 1409 asc[offset] = *start; 1410 } else { 1411 asc[offset] = '.'; 1412 } 1413 } 1414 asc[offset + 1] = 0; 1415 if (offset % 2) { 1416 printf(" "); 1417 } 1418 if (offset == 15) { 1419 printf(" %s\n", asc); 1420 } 1421 start++; 1422 } 1423 } 1424 #endif 1425 #endif 1426 1427 int 1428 radeonfb_getconnectors(struct radeonfb_softc *sc) 1429 { 1430 int i; 1431 int found = 0; 1432 1433 for (i = 0; i < 2; i++) { 1434 sc->sc_ports[i].rp_mon_type = RADEON_MT_UNKNOWN; 1435 sc->sc_ports[i].rp_ddc_type = RADEON_DDC_NONE; 1436 sc->sc_ports[i].rp_dac_type = RADEON_DAC_UNKNOWN; 1437 sc->sc_ports[i].rp_conn_type = RADEON_CONN_NONE; 1438 sc->sc_ports[i].rp_tmds_type = RADEON_TMDS_UNKNOWN; 1439 } 1440 1441 /* 1442 * This logic is borrowed from Xorg's radeon driver. 1443 */ 1444 if (!sc->sc_biossz) 1445 goto nobios; 1446 1447 if (IS_ATOM(sc)) { 1448 /* not done yet */ 1449 } else { 1450 uint16_t ptr; 1451 int port = 0; 1452 1453 ptr = GETBIOS16(sc, 0x48); 1454 ptr = GETBIOS16(sc, ptr + 0x50); 1455 for (i = 1; i < 4; i++) { 1456 uint16_t entry; 1457 uint8_t conn, ddc, dac, tmds; 1458 1459 /* 1460 * Parse the connector table. From reading the code, 1461 * it appears to made up of 16-bit entries for each 1462 * connector. The 16-bits are defined as: 1463 * 1464 * bits 12-15 - connector type (0 == end of table) 1465 * bits 8-11 - DDC type 1466 * bits 5-7 - ??? 1467 * bit 4 - TMDS type (1 = EXT, 0 = INT) 1468 * bits 1-3 - ??? 1469 * bit 0 - DAC, 1 = TVDAC, 0 = primary 1470 */ 1471 if (!GETBIOS8(sc, ptr + i * 2) && i > 1) 1472 break; 1473 entry = GETBIOS16(sc, ptr + i * 2); 1474 1475 conn = (entry >> 12) & 0xf; 1476 ddc = (entry >> 8) & 0xf; 1477 dac = (entry & 0x1) ? RADEON_DAC_TVDAC : 1478 RADEON_DAC_PRIMARY; 1479 tmds = ((entry >> 4) & 0x1) ? RADEON_TMDS_EXT : 1480 RADEON_TMDS_INT; 1481 1482 if (conn == RADEON_CONN_NONE) 1483 continue; /* no connector */ 1484 1485 if ((found > 0) && 1486 (sc->sc_ports[port].rp_ddc_type == ddc)) { 1487 /* duplicate entry for same connector */ 1488 continue; 1489 } 1490 1491 /* internal DDC_DVI port gets priority */ 1492 if ((ddc == RADEON_DDC_DVI) || (port == 1)) 1493 port = 0; 1494 else 1495 port = 1; 1496 1497 sc->sc_ports[port].rp_ddc_type = 1498 ddc > RADEON_DDC_CRT2 ? RADEON_DDC_NONE : ddc; 1499 sc->sc_ports[port].rp_dac_type = dac; 1500 sc->sc_ports[port].rp_conn_type = 1501 min(conn, RADEON_CONN_UNSUPPORTED) ; 1502 1503 sc->sc_ports[port].rp_tmds_type = tmds; 1504 1505 if ((conn != RADEON_CONN_DVI_I) && 1506 (conn != RADEON_CONN_DVI_D) && 1507 (tmds == RADEON_TMDS_INT)) 1508 sc->sc_ports[port].rp_tmds_type = 1509 RADEON_TMDS_UNKNOWN; 1510 1511 found += (port + 1); 1512 } 1513 } 1514 1515 nobios: 1516 if (!found) { 1517 DPRINTF(("No connector info in BIOS!\n")); 1518 /* default, port 0 = internal TMDS, port 1 = CRT */ 1519 sc->sc_ports[0].rp_mon_type = RADEON_MT_UNKNOWN; 1520 sc->sc_ports[0].rp_ddc_type = RADEON_DDC_DVI; 1521 sc->sc_ports[0].rp_dac_type = RADEON_DAC_TVDAC; 1522 sc->sc_ports[0].rp_conn_type = RADEON_CONN_DVI_D; 1523 sc->sc_ports[0].rp_tmds_type = RADEON_TMDS_INT; 1524 1525 sc->sc_ports[1].rp_mon_type = RADEON_MT_UNKNOWN; 1526 sc->sc_ports[1].rp_ddc_type = RADEON_DDC_VGA; 1527 sc->sc_ports[1].rp_dac_type = RADEON_DAC_PRIMARY; 1528 sc->sc_ports[1].rp_conn_type = RADEON_CONN_CRT; 1529 sc->sc_ports[1].rp_tmds_type = RADEON_TMDS_EXT; 1530 } 1531 1532 /* 1533 * Fixup for RS300/RS350/RS400 chips, that lack a primary DAC. 1534 * these chips should use TVDAC for the VGA port. 1535 */ 1536 if (HAS_SDAC(sc)) { 1537 if (sc->sc_ports[0].rp_conn_type == RADEON_CONN_CRT) { 1538 sc->sc_ports[0].rp_dac_type = RADEON_DAC_TVDAC; 1539 sc->sc_ports[1].rp_dac_type = RADEON_DAC_PRIMARY; 1540 } else { 1541 sc->sc_ports[1].rp_dac_type = RADEON_DAC_TVDAC; 1542 sc->sc_ports[0].rp_dac_type = RADEON_DAC_PRIMARY; 1543 } 1544 } else if (!HAS_CRTC2(sc)) { 1545 sc->sc_ports[0].rp_dac_type = RADEON_DAC_PRIMARY; 1546 } 1547 1548 for (i = 0; i < 2; i++) { 1549 char edid[128]; 1550 uint8_t ddc; 1551 struct edid_info *eip = &sc->sc_ports[i].rp_edid; 1552 prop_data_t edid_data; 1553 1554 DPRINTF(("Port #%d:\n", i)); 1555 DPRINTF((" conn = %d\n", sc->sc_ports[i].rp_conn_type)); 1556 DPRINTF((" ddc = %d\n", sc->sc_ports[i].rp_ddc_type)); 1557 DPRINTF((" dac = %d\n", sc->sc_ports[i].rp_dac_type)); 1558 DPRINTF((" tmds = %d\n", sc->sc_ports[i].rp_tmds_type)); 1559 1560 sc->sc_ports[i].rp_edid_valid = 0; 1561 /* first look for static EDID data */ 1562 if ((edid_data = prop_dictionary_get(device_properties( 1563 &sc->sc_dev), "EDID")) != NULL) { 1564 1565 aprint_normal("%s: using static EDID\n", 1566 sc->sc_dev.dv_xname); 1567 memcpy(edid, prop_data_data_nocopy(edid_data), 128); 1568 if (edid_parse(edid, eip) == 0) { 1569 1570 sc->sc_ports[i].rp_edid_valid = 1; 1571 edid_print(eip); 1572 } 1573 } 1574 /* if we didn't find any we'll try to talk to the monitor */ 1575 if (sc->sc_ports[i].rp_edid_valid != 1) { 1576 1577 ddc = sc->sc_ports[i].rp_ddc_type; 1578 if (ddc != RADEON_DDC_NONE) { 1579 if ((radeonfb_i2c_read_edid(sc, ddc, edid) 1580 == 0) && (edid_parse(edid, eip) == 0)) { 1581 1582 sc->sc_ports[i].rp_edid_valid = 1; 1583 edid_print(eip); 1584 } 1585 } 1586 } 1587 } 1588 1589 return found; 1590 } 1591 1592 int 1593 radeonfb_gettmds(struct radeonfb_softc *sc) 1594 { 1595 int i; 1596 1597 if (!sc->sc_biossz) { 1598 goto nobios; 1599 } 1600 1601 if (IS_ATOM(sc)) { 1602 /* XXX: not done yet */ 1603 } else { 1604 uint16_t ptr; 1605 int n; 1606 1607 ptr = GETBIOS16(sc, 0x48); 1608 ptr = GETBIOS16(sc, ptr + 0x34); 1609 DPRINTF(("DFP table revision %d\n", GETBIOS8(sc, ptr))); 1610 if (GETBIOS8(sc, ptr) == 3) { 1611 /* revision three table */ 1612 n = GETBIOS8(sc, ptr + 5) + 1; 1613 n = min(n, 4); 1614 1615 memset(sc->sc_tmds_pll, 0, sizeof (sc->sc_tmds_pll)); 1616 for (i = 0; i < n; i++) { 1617 sc->sc_tmds_pll[i].rtp_pll = GETBIOS32(sc, 1618 ptr + i * 10 + 8); 1619 sc->sc_tmds_pll[i].rtp_freq = GETBIOS16(sc, 1620 ptr + i * 10 + 0x10); 1621 DPRINTF(("TMDS_PLL dot clock %d pll %x\n", 1622 sc->sc_tmds_pll[i].rtp_freq, 1623 sc->sc_tmds_pll[i].rtp_pll)); 1624 } 1625 return 0; 1626 } 1627 } 1628 1629 nobios: 1630 DPRINTF(("no suitable DFP table present\n")); 1631 for (i = 0; 1632 i < sizeof (radeonfb_tmds_pll) / sizeof (radeonfb_tmds_pll[0]); 1633 i++) { 1634 int j; 1635 1636 if (radeonfb_tmds_pll[i].family != sc->sc_family) 1637 continue; 1638 1639 for (j = 0; j < 4; j++) { 1640 sc->sc_tmds_pll[j] = radeonfb_tmds_pll[i].plls[j]; 1641 DPRINTF(("TMDS_PLL dot clock %d pll %x\n", 1642 sc->sc_tmds_pll[j].rtp_freq, 1643 sc->sc_tmds_pll[j].rtp_pll)); 1644 } 1645 return 0; 1646 } 1647 1648 return -1; 1649 } 1650 1651 const struct videomode * 1652 radeonfb_modelookup(const char *name) 1653 { 1654 int i; 1655 1656 for (i = 0; i < videomode_count; i++) 1657 if (!strcmp(name, videomode_list[i].name)) 1658 return &videomode_list[i]; 1659 1660 return NULL; 1661 } 1662 1663 void 1664 radeonfb_pllwriteupdate(struct radeonfb_softc *sc, int crtc) 1665 { 1666 if (crtc) { 1667 while (GETPLL(sc, RADEON_P2PLL_REF_DIV) & 1668 RADEON_P2PLL_ATOMIC_UPDATE_R); 1669 SETPLL(sc, RADEON_P2PLL_REF_DIV, RADEON_P2PLL_ATOMIC_UPDATE_W); 1670 } else { 1671 while (GETPLL(sc, RADEON_PPLL_REF_DIV) & 1672 RADEON_PPLL_ATOMIC_UPDATE_R); 1673 SETPLL(sc, RADEON_PPLL_REF_DIV, RADEON_PPLL_ATOMIC_UPDATE_W); 1674 } 1675 } 1676 1677 void 1678 radeonfb_pllwaitatomicread(struct radeonfb_softc *sc, int crtc) 1679 { 1680 int i; 1681 1682 for (i = 10000; i; i--) { 1683 if (crtc) { 1684 if (GETPLL(sc, RADEON_P2PLL_REF_DIV) & 1685 RADEON_P2PLL_ATOMIC_UPDATE_R) 1686 break; 1687 } else { 1688 if (GETPLL(sc, RADEON_PPLL_REF_DIV) & 1689 RADEON_PPLL_ATOMIC_UPDATE_R) 1690 break; 1691 } 1692 } 1693 } 1694 1695 void 1696 radeonfb_program_vclk(struct radeonfb_softc *sc, int dotclock, int crtc) 1697 { 1698 uint32_t pbit = 0; 1699 uint32_t feed = 0; 1700 uint32_t data; 1701 #if 1 1702 int i; 1703 #endif 1704 1705 radeonfb_calc_dividers(sc, dotclock, &pbit, &feed); 1706 1707 if (crtc == 0) { 1708 1709 /* XXXX: mobility workaround missing */ 1710 /* XXXX: R300 stuff missing */ 1711 1712 PATCHPLL(sc, RADEON_VCLK_ECP_CNTL, 1713 RADEON_VCLK_SRC_SEL_CPUCLK, 1714 ~RADEON_VCLK_SRC_SEL_MASK); 1715 1716 /* put vclk into reset, use atomic updates */ 1717 SETPLL(sc, RADEON_PPLL_CNTL, 1718 RADEON_PPLL_REFCLK_SEL | 1719 RADEON_PPLL_FBCLK_SEL | 1720 RADEON_PPLL_RESET | 1721 RADEON_PPLL_ATOMIC_UPDATE_EN | 1722 RADEON_PPLL_VGA_ATOMIC_UPDATE_EN); 1723 1724 /* select clock 3 */ 1725 #if 0 1726 PATCH32(sc, RADEON_CLOCK_CNTL_INDEX, RADEON_PLL_DIV_SEL, 1727 ~RADEON_PLL_DIV_SEL); 1728 #else 1729 PATCH32(sc, RADEON_CLOCK_CNTL_INDEX, 0, 1730 ~RADEON_PLL_DIV_SEL); 1731 #endif 1732 1733 /* XXX: R300 family -- program divider differently? */ 1734 1735 /* program reference divider */ 1736 PATCHPLL(sc, RADEON_PPLL_REF_DIV, sc->sc_refdiv, 1737 ~RADEON_PPLL_REF_DIV_MASK); 1738 PRINTPLL(RADEON_PPLL_REF_DIV); 1739 1740 #if 0 1741 data = GETPLL(sc, RADEON_PPLL_DIV_3); 1742 data &= ~(RADEON_PPLL_FB3_DIV_MASK | 1743 RADEON_PPLL_POST3_DIV_MASK); 1744 data |= pbit; 1745 data |= (feed & RADEON_PPLL_FB3_DIV_MASK); 1746 PUTPLL(sc, RADEON_PPLL_DIV_3, data); 1747 #else 1748 for (i = 0; i < 4; i++) { 1749 } 1750 #endif 1751 1752 /* use the atomic update */ 1753 radeonfb_pllwriteupdate(sc, crtc); 1754 1755 /* and wait for it to complete */ 1756 radeonfb_pllwaitatomicread(sc, crtc); 1757 1758 /* program HTOTAL (why?) */ 1759 PUTPLL(sc, RADEON_HTOTAL_CNTL, 0); 1760 1761 /* drop reset */ 1762 CLRPLL(sc, RADEON_PPLL_CNTL, 1763 RADEON_PPLL_RESET | RADEON_PPLL_SLEEP | 1764 RADEON_PPLL_ATOMIC_UPDATE_EN | 1765 RADEON_PPLL_VGA_ATOMIC_UPDATE_EN); 1766 1767 PRINTPLL(RADEON_PPLL_CNTL); 1768 1769 /* give clock time to lock */ 1770 delay(50000); 1771 1772 PATCHPLL(sc, RADEON_VCLK_ECP_CNTL, 1773 RADEON_VCLK_SRC_SEL_PPLLCLK, 1774 ~RADEON_VCLK_SRC_SEL_MASK); 1775 1776 } else { 1777 1778 PATCHPLL(sc, RADEON_PIXCLKS_CNTL, 1779 RADEON_PIX2CLK_SRC_SEL_CPUCLK, 1780 ~RADEON_PIX2CLK_SRC_SEL_MASK); 1781 1782 /* put vclk into reset, use atomic updates */ 1783 SETPLL(sc, RADEON_P2PLL_CNTL, 1784 RADEON_P2PLL_RESET | 1785 RADEON_P2PLL_ATOMIC_UPDATE_EN | 1786 RADEON_P2PLL_VGA_ATOMIC_UPDATE_EN); 1787 1788 /* XXX: R300 family -- program divider differently? */ 1789 1790 /* program reference divider */ 1791 PATCHPLL(sc, RADEON_P2PLL_REF_DIV, sc->sc_refdiv, 1792 ~RADEON_P2PLL_REF_DIV_MASK); 1793 1794 /* program feedback and post dividers */ 1795 data = GETPLL(sc, RADEON_P2PLL_DIV_0); 1796 data &= ~(RADEON_P2PLL_FB0_DIV_MASK | 1797 RADEON_P2PLL_POST0_DIV_MASK); 1798 data |= pbit; 1799 data |= (feed & RADEON_P2PLL_FB0_DIV_MASK); 1800 PUTPLL(sc, RADEON_P2PLL_DIV_0, data); 1801 1802 /* use the atomic update */ 1803 radeonfb_pllwriteupdate(sc, crtc); 1804 1805 /* and wait for it to complete */ 1806 radeonfb_pllwaitatomicread(sc, crtc); 1807 1808 /* program HTOTAL (why?) */ 1809 PUTPLL(sc, RADEON_HTOTAL2_CNTL, 0); 1810 1811 /* drop reset */ 1812 CLRPLL(sc, RADEON_P2PLL_CNTL, 1813 RADEON_P2PLL_RESET | RADEON_P2PLL_SLEEP | 1814 RADEON_P2PLL_ATOMIC_UPDATE_EN | 1815 RADEON_P2PLL_VGA_ATOMIC_UPDATE_EN); 1816 1817 /* allow time for clock to lock */ 1818 delay(50000); 1819 1820 PATCHPLL(sc, RADEON_PIXCLKS_CNTL, 1821 RADEON_PIX2CLK_SRC_SEL_P2PLLCLK, 1822 ~RADEON_PIX2CLK_SRC_SEL_MASK); 1823 } 1824 PRINTREG(RADEON_CRTC_MORE_CNTL); 1825 } 1826 1827 void 1828 radeonfb_modeswitch(struct radeonfb_display *dp) 1829 { 1830 struct radeonfb_softc *sc = dp->rd_softc; 1831 int i; 1832 1833 /* blank the display while we switch modes */ 1834 //radeonfb_blank(dp, 1); 1835 1836 #if 0 1837 SET32(sc, RADEON_CRTC_EXT_CNTL, 1838 RADEON_CRTC_VSYNC_DIS | RADEON_CRTC_HSYNC_DIS | 1839 RADEON_CRTC_DISPLAY_DIS /* | RADEON_CRTC_DISP_REQ_EN_B */); 1840 #endif 1841 1842 /* these registers might get in the way... */ 1843 PUT32(sc, RADEON_OVR_CLR, 0); 1844 PUT32(sc, RADEON_OVR_WID_LEFT_RIGHT, 0); 1845 PUT32(sc, RADEON_OVR_WID_TOP_BOTTOM, 0); 1846 PUT32(sc, RADEON_OV0_SCALE_CNTL, 0); 1847 PUT32(sc, RADEON_SUBPIC_CNTL, 0); 1848 PUT32(sc, RADEON_VIPH_CONTROL, 0); 1849 PUT32(sc, RADEON_I2C_CNTL_1, 0); 1850 PUT32(sc, RADEON_GEN_INT_CNTL, 0); 1851 PUT32(sc, RADEON_CAP0_TRIG_CNTL, 0); 1852 PUT32(sc, RADEON_CAP1_TRIG_CNTL, 0); 1853 PUT32(sc, RADEON_SURFACE_CNTL, 0); 1854 1855 for (i = 0; i < dp->rd_ncrtcs; i++) 1856 radeonfb_setcrtc(dp, i); 1857 1858 /* activate the display */ 1859 //radeonfb_blank(dp, 0); 1860 } 1861 1862 void 1863 radeonfb_setcrtc(struct radeonfb_display *dp, int index) 1864 { 1865 int crtc; 1866 struct videomode *mode; 1867 struct radeonfb_softc *sc; 1868 struct radeonfb_crtc *cp; 1869 uint32_t v; 1870 uint32_t gencntl; 1871 uint32_t htotaldisp; 1872 uint32_t hsyncstrt; 1873 uint32_t vtotaldisp; 1874 uint32_t vsyncstrt; 1875 uint32_t fphsyncstrt; 1876 uint32_t fpvsyncstrt; 1877 uint32_t fphtotaldisp; 1878 uint32_t fpvtotaldisp; 1879 uint32_t pitch; 1880 1881 sc = dp->rd_softc; 1882 cp = &dp->rd_crtcs[index]; 1883 crtc = cp->rc_number; 1884 mode = &cp->rc_videomode; 1885 1886 #if 1 1887 pitch = (((dp->rd_virtx * dp->rd_bpp) + ((dp->rd_bpp * 8) - 1)) / 1888 (dp->rd_bpp * 8)); 1889 #else 1890 pitch = (((sc->sc_maxx * sc->sc_maxbpp) + ((sc->sc_maxbpp * 8) - 1)) / 1891 (sc->sc_maxbpp * 8)); 1892 #endif 1893 //pitch = pitch | (pitch << 16); 1894 1895 switch (crtc) { 1896 case 0: 1897 gencntl = RADEON_CRTC_GEN_CNTL; 1898 htotaldisp = RADEON_CRTC_H_TOTAL_DISP; 1899 hsyncstrt = RADEON_CRTC_H_SYNC_STRT_WID; 1900 vtotaldisp = RADEON_CRTC_V_TOTAL_DISP; 1901 vsyncstrt = RADEON_CRTC_V_SYNC_STRT_WID; 1902 fpvsyncstrt = RADEON_FP_V_SYNC_STRT_WID; 1903 fphsyncstrt = RADEON_FP_H_SYNC_STRT_WID; 1904 fpvtotaldisp = RADEON_FP_CRTC_V_TOTAL_DISP; 1905 fphtotaldisp = RADEON_FP_CRTC_H_TOTAL_DISP; 1906 break; 1907 case 1: 1908 gencntl = RADEON_CRTC2_GEN_CNTL; 1909 htotaldisp = RADEON_CRTC2_H_TOTAL_DISP; 1910 hsyncstrt = RADEON_CRTC2_H_SYNC_STRT_WID; 1911 vtotaldisp = RADEON_CRTC2_V_TOTAL_DISP; 1912 vsyncstrt = RADEON_CRTC2_V_SYNC_STRT_WID; 1913 fpvsyncstrt = RADEON_FP_V2_SYNC_STRT_WID; 1914 fphsyncstrt = RADEON_FP_H2_SYNC_STRT_WID; 1915 fpvtotaldisp = RADEON_FP_CRTC2_V_TOTAL_DISP; 1916 fphtotaldisp = RADEON_FP_CRTC2_H_TOTAL_DISP; 1917 break; 1918 default: 1919 panic("Bad CRTC!"); 1920 break; 1921 } 1922 1923 /* 1924 * CRTC_GEN_CNTL - depth, accelerator mode, etc. 1925 */ 1926 /* only bother with 32bpp and 8bpp */ 1927 v = dp->rd_format << RADEON_CRTC_PIX_WIDTH_SHIFT; 1928 1929 if (crtc == 1) { 1930 v |= RADEON_CRTC2_CRT2_ON | RADEON_CRTC2_EN; 1931 } else { 1932 v |= RADEON_CRTC_EXT_DISP_EN | RADEON_CRTC_EN; 1933 } 1934 1935 if (mode->flags & VID_DBLSCAN) 1936 v |= RADEON_CRTC2_DBL_SCAN_EN; 1937 1938 if (mode->flags & VID_INTERLACE) 1939 v |= RADEON_CRTC2_INTERLACE_EN; 1940 1941 if (mode->flags & VID_CSYNC) { 1942 v |= RADEON_CRTC2_CSYNC_EN; 1943 if (crtc == 1) 1944 v |= RADEON_CRTC2_VSYNC_TRISTAT; 1945 } 1946 1947 PUT32(sc, gencntl, v); 1948 DPRINTF(("CRTC%s_GEN_CNTL = %08x\n", crtc ? "2" : "", v)); 1949 1950 /* 1951 * CRTC_EXT_CNTL - preserve disable flags, set ATI linear and EXT_CNT 1952 */ 1953 v = GET32(sc, RADEON_CRTC_EXT_CNTL); 1954 if (crtc == 0) { 1955 v &= (RADEON_CRTC_VSYNC_DIS | RADEON_CRTC_HSYNC_DIS | 1956 RADEON_CRTC_DISPLAY_DIS); 1957 v |= RADEON_XCRT_CNT_EN | RADEON_VGA_ATI_LINEAR; 1958 if (mode->flags & VID_CSYNC) 1959 v |= RADEON_CRTC_VSYNC_TRISTAT; 1960 } 1961 /* unconditional turn on CRT, in case first CRTC is DFP */ 1962 v |= RADEON_CRTC_CRT_ON; 1963 PUT32(sc, RADEON_CRTC_EXT_CNTL, v); 1964 PRINTREG(RADEON_CRTC_EXT_CNTL); 1965 1966 /* 1967 * H_TOTAL_DISP 1968 */ 1969 v = ((mode->hdisplay / 8) - 1) << 16; 1970 v |= (mode->htotal / 8) - 1; 1971 PUT32(sc, htotaldisp, v); 1972 DPRINTF(("CRTC%s_H_TOTAL_DISP = %08x\n", crtc ? "2" : "", v)); 1973 PUT32(sc, fphtotaldisp, v); 1974 DPRINTF(("FP_H%s_TOTAL_DISP = %08x\n", crtc ? "2" : "", v)); 1975 1976 /* 1977 * H_SYNC_STRT_WID 1978 */ 1979 v = (((mode->hsync_end - mode->hsync_start) / 8) << 16); 1980 v |= mode->hsync_start; 1981 if (mode->flags & VID_NHSYNC) 1982 v |= RADEON_CRTC_H_SYNC_POL; 1983 PUT32(sc, hsyncstrt, v); 1984 DPRINTF(("CRTC%s_H_SYNC_STRT_WID = %08x\n", crtc ? "2" : "", v)); 1985 PUT32(sc, fphsyncstrt, v); 1986 DPRINTF(("FP_H%s_SYNC_STRT_WID = %08x\n", crtc ? "2" : "", v)); 1987 1988 /* 1989 * V_TOTAL_DISP 1990 */ 1991 v = ((mode->vdisplay - 1) << 16); 1992 v |= (mode->vtotal - 1); 1993 PUT32(sc, vtotaldisp, v); 1994 DPRINTF(("CRTC%s_V_TOTAL_DISP = %08x\n", crtc ? "2" : "", v)); 1995 PUT32(sc, fpvtotaldisp, v); 1996 DPRINTF(("FP_V%s_TOTAL_DISP = %08x\n", crtc ? "2" : "", v)); 1997 1998 /* 1999 * V_SYNC_STRT_WID 2000 */ 2001 v = ((mode->vsync_end - mode->vsync_start) << 16); 2002 v |= (mode->vsync_start - 1); 2003 if (mode->flags & VID_NVSYNC) 2004 v |= RADEON_CRTC_V_SYNC_POL; 2005 PUT32(sc, vsyncstrt, v); 2006 DPRINTF(("CRTC%s_V_SYNC_STRT_WID = %08x\n", crtc ? "2" : "", v)); 2007 PUT32(sc, fpvsyncstrt, v); 2008 DPRINTF(("FP_V%s_SYNC_STRT_WID = %08x\n", crtc ? "2" : "", v)); 2009 2010 radeonfb_program_vclk(sc, mode->dot_clock, crtc); 2011 2012 switch (crtc) { 2013 case 0: 2014 PUT32(sc, RADEON_CRTC_OFFSET, 0); 2015 PUT32(sc, RADEON_CRTC_OFFSET_CNTL, 0); 2016 PUT32(sc, RADEON_CRTC_PITCH, pitch); 2017 CLR32(sc, RADEON_DISP_MERGE_CNTL, RADEON_DISP_RGB_OFFSET_EN); 2018 2019 CLR32(sc, RADEON_CRTC_EXT_CNTL, 2020 RADEON_CRTC_VSYNC_DIS | RADEON_CRTC_HSYNC_DIS | 2021 RADEON_CRTC_DISPLAY_DIS /* | RADEON_CRTC_DISP_REQ_EN_B */); 2022 CLR32(sc, RADEON_CRTC_GEN_CNTL, RADEON_CRTC_DISP_REQ_EN_B); 2023 PRINTREG(RADEON_CRTC_EXT_CNTL); 2024 PRINTREG(RADEON_CRTC_GEN_CNTL); 2025 PRINTREG(RADEON_CLOCK_CNTL_INDEX); 2026 break; 2027 2028 case 1: 2029 PUT32(sc, RADEON_CRTC2_OFFSET, 0); 2030 PUT32(sc, RADEON_CRTC2_OFFSET_CNTL, 0); 2031 PUT32(sc, RADEON_CRTC2_PITCH, pitch); 2032 CLR32(sc, RADEON_DISP2_MERGE_CNTL, RADEON_DISP2_RGB_OFFSET_EN); 2033 CLR32(sc, RADEON_CRTC2_GEN_CNTL, 2034 RADEON_CRTC2_VSYNC_DIS | 2035 RADEON_CRTC2_HSYNC_DIS | 2036 RADEON_CRTC2_DISP_DIS | RADEON_CRTC2_DISP_REQ_EN_B); 2037 PRINTREG(RADEON_CRTC2_GEN_CNTL); 2038 break; 2039 } 2040 } 2041 2042 int 2043 radeonfb_isblank(struct radeonfb_display *dp) 2044 { 2045 uint32_t reg, mask; 2046 2047 if (dp->rd_crtcs[0].rc_number) { 2048 reg = RADEON_CRTC2_GEN_CNTL; 2049 mask = RADEON_CRTC2_DISP_DIS; 2050 } else { 2051 reg = RADEON_CRTC_EXT_CNTL; 2052 mask = RADEON_CRTC_DISPLAY_DIS; 2053 } 2054 return ((GET32(dp->rd_softc, reg) & mask) ? 1 : 0); 2055 } 2056 2057 void 2058 radeonfb_blank(struct radeonfb_display *dp, int blank) 2059 { 2060 struct radeonfb_softc *sc = dp->rd_softc; 2061 uint32_t reg, mask; 2062 uint32_t fpreg, fpval; 2063 int i; 2064 2065 for (i = 0; i < dp->rd_ncrtcs; i++) { 2066 2067 if (dp->rd_crtcs[i].rc_number) { 2068 reg = RADEON_CRTC2_GEN_CNTL; 2069 mask = RADEON_CRTC2_DISP_DIS; 2070 fpreg = RADEON_FP2_GEN_CNTL; 2071 fpval = RADEON_FP2_ON; 2072 } else { 2073 reg = RADEON_CRTC_EXT_CNTL; 2074 mask = RADEON_CRTC_DISPLAY_DIS; 2075 fpreg = RADEON_FP_GEN_CNTL; 2076 fpval = RADEON_FP_FPON; 2077 } 2078 2079 if (blank) { 2080 SET32(sc, reg, mask); 2081 CLR32(sc, fpreg, fpval); 2082 } else { 2083 CLR32(sc, reg, mask); 2084 SET32(sc, fpreg, fpval); 2085 } 2086 } 2087 PRINTREG(RADEON_FP_GEN_CNTL); 2088 PRINTREG(RADEON_FP2_GEN_CNTL); 2089 } 2090 2091 void 2092 radeonfb_init_screen(void *cookie, struct vcons_screen *scr, int existing, 2093 long *defattr) 2094 { 2095 struct radeonfb_display *dp = cookie; 2096 struct rasops_info *ri = &scr->scr_ri; 2097 2098 /* initialize font subsystem */ 2099 wsfont_init(); 2100 2101 DPRINTF(("init screen called, existing %d\n", existing)); 2102 2103 ri->ri_depth = dp->rd_bpp; 2104 ri->ri_width = dp->rd_virtx; 2105 ri->ri_height = dp->rd_virty; 2106 ri->ri_stride = dp->rd_stride; 2107 ri->ri_flg = RI_CENTER; 2108 ri->ri_bits = (void *)dp->rd_fbptr; 2109 2110 /* XXX: 32 bpp only */ 2111 /* this is rgb in "big-endian order..." */ 2112 ri->ri_rnum = 8; 2113 ri->ri_gnum = 8; 2114 ri->ri_bnum = 8; 2115 ri->ri_rpos = 16; 2116 ri->ri_gpos = 8; 2117 ri->ri_bpos = 0; 2118 2119 if (existing) { 2120 ri->ri_flg |= RI_CLEAR; 2121 2122 /* start a modeswitch now */ 2123 radeonfb_modeswitch(dp); 2124 } 2125 2126 /* 2127 * XXX: font selection should be based on properties, with some 2128 * normal/reasonable default. 2129 */ 2130 ri->ri_caps = WSSCREEN_WSCOLORS; 2131 2132 /* initialize and look for an initial font */ 2133 rasops_init(ri, dp->rd_virty/8, dp->rd_virtx/8); 2134 2135 rasops_reconfig(ri, dp->rd_virty / ri->ri_font->fontheight, 2136 dp->rd_virtx / ri->ri_font->fontwidth); 2137 2138 /* enable acceleration */ 2139 ri->ri_ops.copyrows = radeonfb_copyrows; 2140 ri->ri_ops.copycols = radeonfb_copycols; 2141 ri->ri_ops.eraserows = radeonfb_eraserows; 2142 ri->ri_ops.erasecols = radeonfb_erasecols; 2143 ri->ri_ops.allocattr = radeonfb_allocattr; 2144 if (!IS_R300(dp->rd_softc)) { 2145 ri->ri_ops.putchar = radeonfb_putchar; 2146 } 2147 ri->ri_ops.cursor = radeonfb_cursor; 2148 } 2149 2150 void 2151 radeonfb_set_fbloc(struct radeonfb_softc *sc) 2152 { 2153 uint32_t gen, ext, gen2 = 0; 2154 uint32_t agploc, aperbase, apersize, mcfbloc; 2155 2156 gen = GET32(sc, RADEON_CRTC_GEN_CNTL); 2157 ext = GET32(sc, RADEON_CRTC_EXT_CNTL); 2158 agploc = GET32(sc, RADEON_MC_AGP_LOCATION); 2159 aperbase = GET32(sc, RADEON_CONFIG_APER_0_BASE); 2160 apersize = GET32(sc, RADEON_CONFIG_APER_SIZE); 2161 2162 PUT32(sc, RADEON_CRTC_GEN_CNTL, gen | RADEON_CRTC_DISP_REQ_EN_B); 2163 PUT32(sc, RADEON_CRTC_EXT_CNTL, ext | RADEON_CRTC_DISPLAY_DIS); 2164 //PUT32(sc, RADEON_CRTC_GEN_CNTL, gen | RADEON_CRTC_DISPLAY_DIS); 2165 //PUT32(sc, RADEON_CRTC_EXT_CNTL, ext | RADEON_CRTC_DISP_REQ_EN_B); 2166 2167 if (HAS_CRTC2(sc)) { 2168 gen2 = GET32(sc, RADEON_CRTC2_GEN_CNTL); 2169 PUT32(sc, RADEON_CRTC2_GEN_CNTL, 2170 gen2 | RADEON_CRTC2_DISP_REQ_EN_B); 2171 } 2172 2173 delay(100000); 2174 2175 mcfbloc = (aperbase >> 16) | 2176 ((aperbase + (apersize - 1)) & 0xffff0000); 2177 2178 sc->sc_aperbase = (mcfbloc & 0xffff) << 16; 2179 sc->sc_memsz = apersize; 2180 2181 if (((agploc & 0xffff) << 16) != 2182 ((mcfbloc & 0xffff0000U) + 0x10000)) { 2183 agploc = mcfbloc & 0xffff0000U; 2184 agploc |= ((agploc + 0x10000) >> 16); 2185 } 2186 2187 PUT32(sc, RADEON_HOST_PATH_CNTL, 0); 2188 2189 PUT32(sc, RADEON_MC_FB_LOCATION, mcfbloc); 2190 PUT32(sc, RADEON_MC_AGP_LOCATION, agploc); 2191 2192 DPRINTF(("aperbase = %u\n", aperbase)); 2193 PRINTREG(RADEON_MC_FB_LOCATION); 2194 PRINTREG(RADEON_MC_AGP_LOCATION); 2195 2196 PUT32(sc, RADEON_DISPLAY_BASE_ADDR, sc->sc_aperbase); 2197 2198 if (HAS_CRTC2(sc)) 2199 PUT32(sc, RADEON_DISPLAY2_BASE_ADDR, sc->sc_aperbase); 2200 2201 PUT32(sc, RADEON_OV0_BASE_ADDR, sc->sc_aperbase); 2202 2203 #if 0 2204 /* XXX: what is this AGP garbage? :-) */ 2205 PUT32(sc, RADEON_AGP_CNTL, 0x00100000); 2206 #endif 2207 2208 delay(100000); 2209 2210 PUT32(sc, RADEON_CRTC_GEN_CNTL, gen); 2211 PUT32(sc, RADEON_CRTC_EXT_CNTL, ext); 2212 2213 if (HAS_CRTC2(sc)) 2214 PUT32(sc, RADEON_CRTC2_GEN_CNTL, gen2); 2215 } 2216 2217 void 2218 radeonfb_init_misc(struct radeonfb_softc *sc) 2219 { 2220 PUT32(sc, RADEON_BUS_CNTL, 2221 RADEON_BUS_MASTER_DIS | 2222 RADEON_BUS_PREFETCH_MODE_ACT | 2223 RADEON_BUS_PCI_READ_RETRY_EN | 2224 RADEON_BUS_PCI_WRT_RETRY_EN | 2225 (3 << RADEON_BUS_RETRY_WS_SHIFT) | 2226 RADEON_BUS_MSTR_RD_MULT | 2227 RADEON_BUS_MSTR_RD_LINE | 2228 RADEON_BUS_RD_DISCARD_EN | 2229 RADEON_BUS_MSTR_DISCONNECT_EN | 2230 RADEON_BUS_READ_BURST); 2231 2232 PUT32(sc, RADEON_BUS_CNTL1, 0xf0); 2233 /* PUT32(sc, RADEON_SEPROM_CNTL1, 0x09ff0000); */ 2234 PUT32(sc, RADEON_FCP_CNTL, RADEON_FCP0_SRC_GND); 2235 PUT32(sc, RADEON_RBBM_CNTL, 2236 (3 << RADEON_RB_SETTLE_SHIFT) | 2237 (4 << RADEON_ABORTCLKS_HI_SHIFT) | 2238 (4 << RADEON_ABORTCLKS_CP_SHIFT) | 2239 (4 << RADEON_ABORTCLKS_CFIFO_SHIFT)); 2240 2241 /* XXX: figure out what these mean! */ 2242 PUT32(sc, RADEON_AGP_CNTL, 0x00100000); 2243 PUT32(sc, RADEON_HOST_PATH_CNTL, 0); 2244 //PUT32(sc, RADEON_DISP_MISC_CNTL, 0x5bb00400); 2245 2246 PUT32(sc, RADEON_GEN_INT_CNTL, 0); 2247 PUT32(sc, RADEON_GEN_INT_STATUS, GET32(sc, RADEON_GEN_INT_STATUS)); 2248 } 2249 2250 /* 2251 * This loads a linear color map for true color. 2252 */ 2253 void 2254 radeonfb_init_palette(struct radeonfb_softc *sc, int crtc) 2255 { 2256 int i; 2257 uint32_t vclk; 2258 2259 #define DAC_WIDTH ((1 << 10) - 1) 2260 #define CLUT_WIDTH ((1 << 8) - 1) 2261 #define CLUT_COLOR(i) ((i * DAC_WIDTH * 2 / CLUT_WIDTH + 1) / 2) 2262 2263 vclk = GETPLL(sc, RADEON_VCLK_ECP_CNTL); 2264 PUTPLL(sc, RADEON_VCLK_ECP_CNTL, vclk & ~RADEON_PIXCLK_DAC_ALWAYS_ONb); 2265 2266 if (crtc) 2267 SET32(sc, RADEON_DAC_CNTL2, RADEON_DAC2_PALETTE_ACC_CTL); 2268 else 2269 CLR32(sc, RADEON_DAC_CNTL2, RADEON_DAC2_PALETTE_ACC_CTL); 2270 2271 PUT32(sc, RADEON_PALETTE_INDEX, 0); 2272 for (i = 0; i <= CLUT_WIDTH; ++i) { 2273 PUT32(sc, RADEON_PALETTE_30_DATA, 2274 (CLUT_COLOR(i) << 10) | 2275 (CLUT_COLOR(i) << 20) | 2276 (CLUT_COLOR(i))); 2277 } 2278 2279 CLR32(sc, RADEON_DAC_CNTL2, RADEON_DAC2_PALETTE_ACC_CTL); 2280 PRINTREG(RADEON_DAC_CNTL2); 2281 2282 PUTPLL(sc, RADEON_VCLK_ECP_CNTL, vclk); 2283 } 2284 2285 /* 2286 * Bugs in some R300 hardware requires this when accessing CLOCK_CNTL_INDEX. 2287 */ 2288 void 2289 radeonfb_r300cg_workaround(struct radeonfb_softc *sc) 2290 { 2291 uint32_t tmp, save; 2292 2293 save = GET32(sc, RADEON_CLOCK_CNTL_INDEX); 2294 tmp = save & ~(0x3f | RADEON_PLL_WR_EN); 2295 PUT32(sc, RADEON_CLOCK_CNTL_INDEX, tmp); 2296 tmp = GET32(sc, RADEON_CLOCK_CNTL_DATA); 2297 PUT32(sc, RADEON_CLOCK_CNTL_INDEX, save); 2298 } 2299 2300 /* 2301 * Acceleration entry points. 2302 */ 2303 static void 2304 radeonfb_putchar(void *cookie, int row, int col, u_int c, long attr) 2305 { 2306 struct rasops_info *ri = cookie; 2307 struct vcons_screen *scr = ri->ri_hw; 2308 struct radeonfb_display *dp = scr->scr_cookie; 2309 uint32_t x, y, w, h; 2310 uint32_t bg, fg; 2311 uint8_t *data; 2312 2313 if (dp->rd_wsmode != WSDISPLAYIO_MODE_EMUL) 2314 return; 2315 2316 if (!CHAR_IN_FONT(c, ri->ri_font)) 2317 return; 2318 2319 w = ri->ri_font->fontwidth; 2320 h = ri->ri_font->fontheight; 2321 2322 bg = ri->ri_devcmap[(attr >> 16) & 0xf]; 2323 fg = ri->ri_devcmap[(attr >> 24) & 0xf]; 2324 2325 x = ri->ri_xorigin + col * w; 2326 y = ri->ri_yorigin + row * h; 2327 2328 if (c == 0x20) { 2329 radeonfb_rectfill(dp, x, y, w, h, bg); 2330 } else { 2331 data = (uint8_t *)ri->ri_font->data + 2332 (c - ri->ri_font->firstchar) * ri->ri_fontscale; 2333 2334 radeonfb_setup_mono(dp, x, y, w, h, fg, bg); 2335 radeonfb_feed_bytes(dp, ri->ri_fontscale, data); 2336 } 2337 } 2338 2339 static void 2340 radeonfb_eraserows(void *cookie, int row, int nrows, long fillattr) 2341 { 2342 struct rasops_info *ri = cookie; 2343 struct vcons_screen *scr = ri->ri_hw; 2344 struct radeonfb_display *dp = scr->scr_cookie; 2345 uint32_t x, y, w, h, fg, bg, ul; 2346 2347 /* XXX: check for full emulation mode? */ 2348 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 2349 x = ri->ri_xorigin; 2350 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 2351 w = ri->ri_emuwidth; 2352 h = ri->ri_font->fontheight * nrows; 2353 2354 rasops_unpack_attr(fillattr, &fg, &bg, &ul); 2355 radeonfb_rectfill(dp, x, y, w, h, ri->ri_devcmap[bg & 0xf]); 2356 } 2357 } 2358 2359 static void 2360 radeonfb_copyrows(void *cookie, int srcrow, int dstrow, int nrows) 2361 { 2362 struct rasops_info *ri = cookie; 2363 struct vcons_screen *scr = ri->ri_hw; 2364 struct radeonfb_display *dp = scr->scr_cookie; 2365 uint32_t x, ys, yd, w, h; 2366 2367 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 2368 x = ri->ri_xorigin; 2369 ys = ri->ri_yorigin + ri->ri_font->fontheight * srcrow; 2370 yd = ri->ri_yorigin + ri->ri_font->fontheight * dstrow; 2371 w = ri->ri_emuwidth; 2372 h = ri->ri_font->fontheight * nrows; 2373 radeonfb_bitblt(dp, x, ys, x, yd, w, h, 2374 RADEON_ROP3_S, 0xffffffff); 2375 } 2376 } 2377 2378 static void 2379 radeonfb_copycols(void *cookie, int row, int srccol, int dstcol, int ncols) 2380 { 2381 struct rasops_info *ri = cookie; 2382 struct vcons_screen *scr = ri->ri_hw; 2383 struct radeonfb_display *dp = scr->scr_cookie; 2384 uint32_t xs, xd, y, w, h; 2385 2386 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 2387 xs = ri->ri_xorigin + ri->ri_font->fontwidth * srccol; 2388 xd = ri->ri_xorigin + ri->ri_font->fontwidth * dstcol; 2389 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 2390 w = ri->ri_font->fontwidth * ncols; 2391 h = ri->ri_font->fontheight; 2392 radeonfb_bitblt(dp, xs, y, xd, y, w, h, 2393 RADEON_ROP3_S, 0xffffffff); 2394 } 2395 } 2396 2397 static void 2398 radeonfb_erasecols(void *cookie, int row, int startcol, int ncols, 2399 long fillattr) 2400 { 2401 struct rasops_info *ri = cookie; 2402 struct vcons_screen *scr = ri->ri_hw; 2403 struct radeonfb_display *dp = scr->scr_cookie; 2404 uint32_t x, y, w, h, fg, bg, ul; 2405 2406 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 2407 x = ri->ri_xorigin + ri->ri_font->fontwidth * startcol; 2408 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 2409 w = ri->ri_font->fontwidth * ncols; 2410 h = ri->ri_font->fontheight; 2411 2412 rasops_unpack_attr(fillattr, &fg, &bg, &ul); 2413 radeonfb_rectfill(dp, x, y, w, h, ri->ri_devcmap[bg & 0xf]); 2414 } 2415 } 2416 2417 static void 2418 radeonfb_cursor(void *cookie, int on, int row, int col) 2419 { 2420 struct rasops_info *ri = cookie; 2421 struct vcons_screen *scr = ri->ri_hw; 2422 struct radeonfb_display *dp = scr->scr_cookie; 2423 int x, y, wi, he; 2424 2425 wi = ri->ri_font->fontwidth; 2426 he = ri->ri_font->fontheight; 2427 2428 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 2429 x = ri->ri_ccol * wi + ri->ri_xorigin; 2430 y = ri->ri_crow * he + ri->ri_yorigin; 2431 /* first turn off the old cursor */ 2432 if (ri->ri_flg & RI_CURSOR) { 2433 radeonfb_bitblt(dp, x, y, x, y, wi, he, 2434 RADEON_ROP3_Dn, 0xffffffff); 2435 ri->ri_flg &= ~RI_CURSOR; 2436 } 2437 ri->ri_crow = row; 2438 ri->ri_ccol = col; 2439 /* then (possibly) turn on the new one */ 2440 if (on) { 2441 x = ri->ri_ccol * wi + ri->ri_xorigin; 2442 y = ri->ri_crow * he + ri->ri_yorigin; 2443 radeonfb_bitblt(dp, x, y, x, y, wi, he, 2444 RADEON_ROP3_Dn, 0xffffffff); 2445 ri->ri_flg |= RI_CURSOR; 2446 } 2447 } else { 2448 scr->scr_ri.ri_crow = row; 2449 scr->scr_ri.ri_ccol = col; 2450 scr->scr_ri.ri_flg &= ~RI_CURSOR; 2451 } 2452 } 2453 2454 static int 2455 radeonfb_allocattr(void *cookie, int fg, int bg, int flags, long *attrp) 2456 { 2457 if ((fg == 0) && (bg == 0)) { 2458 fg = WS_DEFAULT_FG; 2459 bg = WS_DEFAULT_BG; 2460 } 2461 *attrp = ((fg & 0xf) << 24) | ((bg & 0xf) << 16) | (flags & 0xff) << 8; 2462 return 0; 2463 } 2464 2465 /* 2466 * Underlying acceleration support. 2467 */ 2468 static void 2469 radeonfb_setup_mono(struct radeonfb_display *dp, int xd, int yd, int width, 2470 int height, uint32_t fg, uint32_t bg) 2471 { 2472 struct radeonfb_softc *sc = dp->rd_softc; 2473 uint32_t gmc; 2474 uint32_t padded_width = (width+7) & 0xfff8; 2475 uint32_t topleft, bottomright; 2476 2477 gmc = dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT; 2478 2479 if (width != padded_width) { 2480 2481 radeonfb_wait_fifo(sc, 2); 2482 topleft = ((yd << 16) & 0x1fff0000) | (xd & 0x1fff); 2483 bottomright = (((yd + height) << 16) & 0x1fff0000) | 2484 ((xd + width) & 0x1fff); 2485 PUT32(sc, RADEON_SC_TOP_LEFT, topleft); 2486 PUT32(sc, RADEON_SC_BOTTOM_RIGHT, bottomright); 2487 } 2488 2489 radeonfb_wait_fifo(sc, 5); 2490 2491 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 2492 RADEON_GMC_BRUSH_NONE | 2493 RADEON_GMC_SRC_DATATYPE_MONO_FG_BG | 2494 //RADEON_GMC_BYTE_LSB_TO_MSB | 2495 RADEON_GMC_DST_CLIPPING | 2496 RADEON_ROP3_S | 2497 RADEON_DP_SRC_SOURCE_HOST_DATA | 2498 RADEON_GMC_CLR_CMP_CNTL_DIS | 2499 RADEON_GMC_WR_MSK_DIS | 2500 gmc); 2501 2502 PUT32(sc, RADEON_DP_SRC_FRGD_CLR, fg); 2503 PUT32(sc, RADEON_DP_SRC_BKGD_CLR, bg); 2504 2505 PUT32(sc, RADEON_DST_X_Y, (xd << 16) | yd); 2506 PUT32(sc, RADEON_DST_WIDTH_HEIGHT, (padded_width << 16) | height); 2507 2508 } 2509 2510 static void 2511 radeonfb_feed_bytes(struct radeonfb_display *dp, int count, uint8_t *data) 2512 { 2513 struct radeonfb_softc *sc = dp->rd_softc; 2514 int i; 2515 uint32_t latch = 0; 2516 int shift = 0; 2517 2518 for (i = 0; i < count; i++) { 2519 latch |= (data[i] << shift); 2520 if (shift == 24) { 2521 radeonfb_wait_fifo(sc, 1); 2522 PUT32(sc, RADEON_HOST_DATA0, latch); 2523 latch = 0; 2524 shift = 0; 2525 } else 2526 shift += 8; 2527 } 2528 if (shift != 0) { 2529 radeonfb_wait_fifo(sc, 1); 2530 PUT32(sc, RADEON_HOST_DATA0, latch); 2531 } 2532 radeonfb_unclip(sc); 2533 } 2534 2535 static void 2536 radeonfb_rectfill(struct radeonfb_display *dp, int dstx, int dsty, 2537 int width, int height, uint32_t color) 2538 { 2539 struct radeonfb_softc *sc = dp->rd_softc; 2540 uint32_t gmc; 2541 2542 gmc = dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT; 2543 2544 radeonfb_wait_fifo(sc, 6); 2545 2546 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 2547 RADEON_GMC_BRUSH_SOLID_COLOR | 2548 RADEON_GMC_SRC_DATATYPE_COLOR | 2549 RADEON_GMC_CLR_CMP_CNTL_DIS | 2550 RADEON_ROP3_P | gmc); 2551 2552 PUT32(sc, RADEON_DP_BRUSH_FRGD_CLR, color); 2553 PUT32(sc, RADEON_DP_WRITE_MASK, 0xffffffff); 2554 PUT32(sc, RADEON_DP_CNTL, 2555 RADEON_DST_X_LEFT_TO_RIGHT | 2556 RADEON_DST_Y_TOP_TO_BOTTOM); 2557 PUT32(sc, RADEON_DST_Y_X, (dsty << 16) | dstx); 2558 PUT32(sc, RADEON_DST_WIDTH_HEIGHT, (width << 16) | (height)); 2559 2560 /* 2561 * XXX: we don't wait for the fifo to empty -- that would slow 2562 * things down! The linux radeonfb driver waits, but xfree doesn't 2563 */ 2564 /* XXX: for now we do, to make it safe for direct drawing */ 2565 radeonfb_engine_idle(sc); 2566 } 2567 2568 static void 2569 radeonfb_bitblt(struct radeonfb_display *dp, int srcx, int srcy, 2570 int dstx, int dsty, int width, int height, int rop, uint32_t mask) 2571 { 2572 struct radeonfb_softc *sc = dp->rd_softc; 2573 uint32_t gmc; 2574 uint32_t dir; 2575 2576 if (dsty < srcy) { 2577 dir = RADEON_DST_Y_TOP_TO_BOTTOM; 2578 } else { 2579 srcy += height - 1; 2580 dsty += height - 1; 2581 dir = 0; 2582 } 2583 if (dstx < srcx) { 2584 dir |= RADEON_DST_X_LEFT_TO_RIGHT; 2585 } else { 2586 srcx += width - 1; 2587 dstx += width - 1; 2588 } 2589 2590 gmc = dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT; 2591 2592 radeonfb_wait_fifo(sc, 6); 2593 2594 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 2595 //RADEON_GMC_SRC_CLIPPING | 2596 RADEON_GMC_BRUSH_SOLID_COLOR | 2597 RADEON_GMC_SRC_DATATYPE_COLOR | 2598 RADEON_GMC_CLR_CMP_CNTL_DIS | 2599 RADEON_DP_SRC_SOURCE_MEMORY | 2600 rop | gmc); 2601 2602 PUT32(sc, RADEON_DP_WRITE_MASK, mask); 2603 PUT32(sc, RADEON_DP_CNTL, dir); 2604 PUT32(sc, RADEON_SRC_Y_X, (srcy << 16) | srcx); 2605 PUT32(sc, RADEON_DST_Y_X, (dsty << 16) | dstx); 2606 PUT32(sc, RADEON_DST_WIDTH_HEIGHT, (width << 16) | (height)); 2607 2608 /* 2609 * XXX: we don't wait for the fifo to empty -- that would slow 2610 * things down! The linux radeonfb driver waits, but xfree doesn't 2611 */ 2612 /* XXX: for now we do, to make it safe for direct drawing */ 2613 radeonfb_engine_idle(sc); 2614 } 2615 2616 static void 2617 radeonfb_engine_idle(struct radeonfb_softc *sc) 2618 { 2619 int i; 2620 2621 radeonfb_wait_fifo(sc, 64); 2622 for (i = RADEON_TIMEOUT; i; i--) { 2623 if ((GET32(sc, RADEON_RBBM_STATUS) & 2624 RADEON_RBBM_ACTIVE) == 0) { 2625 radeonfb_engine_flush(sc); 2626 break; 2627 } 2628 } 2629 } 2630 2631 static void 2632 radeonfb_wait_fifo(struct radeonfb_softc *sc, int n) 2633 { 2634 int i; 2635 2636 for (i = RADEON_TIMEOUT; i; i--) { 2637 if ((GET32(sc, RADEON_RBBM_STATUS) & 2638 RADEON_RBBM_FIFOCNT_MASK) >= n) 2639 return; 2640 } 2641 #ifdef DIAGNOSTIC 2642 if (!i) 2643 printf("%s: timed out waiting for fifo (%x)\n", 2644 XNAME(sc), GET32(sc, RADEON_RBBM_STATUS)); 2645 #endif 2646 } 2647 2648 static void 2649 radeonfb_engine_flush(struct radeonfb_softc *sc) 2650 { 2651 int i; 2652 SET32(sc, RADEON_RB2D_DSTCACHE_CTLSTAT, RADEON_RB2D_DC_FLUSH_ALL); 2653 for (i = RADEON_TIMEOUT; i; i--) { 2654 if ((GET32(sc, RADEON_RB2D_DSTCACHE_CTLSTAT) & 2655 RADEON_RB2D_DC_BUSY) == 0) 2656 break; 2657 } 2658 #ifdef DIAGNOSTIC 2659 if (!i) 2660 printf("%s: engine flush timed out!\n", XNAME(sc)); 2661 #endif 2662 } 2663 2664 static inline void 2665 radeonfb_unclip(struct radeonfb_softc *sc) 2666 { 2667 2668 radeonfb_wait_fifo(sc, 2); 2669 PUT32(sc, RADEON_SC_TOP_LEFT, 0); 2670 PUT32(sc, RADEON_SC_BOTTOM_RIGHT, 0x1fff1fff); 2671 } 2672 2673 static void 2674 radeonfb_engine_init(struct radeonfb_display *dp) 2675 { 2676 struct radeonfb_softc *sc = dp->rd_softc; 2677 uint32_t pitch; 2678 2679 /* no 3D */ 2680 PUT32(sc, RADEON_RB3D_CNTL, 0); 2681 2682 radeonfb_engine_reset(sc); 2683 pitch = ((dp->rd_virtx * (dp->rd_bpp / 8) + 0x3f)) >> 6; 2684 //pitch = ((sc->sc_maxx * (sc->sc_maxbpp / 8) + 0x3f)) >> 6; 2685 2686 radeonfb_wait_fifo(sc, 1); 2687 if (!IS_R300(sc)) 2688 PUT32(sc, RADEON_RB2D_DSTCACHE_MODE, 0); 2689 2690 radeonfb_wait_fifo(sc, 3); 2691 PUT32(sc, RADEON_DEFAULT_PITCH_OFFSET, 2692 (pitch << 22) | (sc->sc_aperbase >> 10)); 2693 2694 2695 PUT32(sc, RADEON_DST_PITCH_OFFSET, 2696 (pitch << 22) | (sc->sc_aperbase >> 10)); 2697 PUT32(sc, RADEON_SRC_PITCH_OFFSET, 2698 (pitch << 22) | (sc->sc_aperbase >> 10)); 2699 2700 radeonfb_wait_fifo(sc, 1); 2701 #if _BYTE_ORDER == _BIG_ENDIAN 2702 SET32(sc, RADEON_DP_DATATYPE, RADEON_HOST_BIG_ENDIAN_EN); 2703 #else 2704 CLR32(sc, RADEON_DP_DATATYPE, RADEON_HOST_BIG_ENDIAN_EN); 2705 #endif 2706 2707 /* default scissors -- no clipping */ 2708 radeonfb_wait_fifo(sc, 1); 2709 PUT32(sc, RADEON_DEFAULT_SC_BOTTOM_RIGHT, 2710 RADEON_DEFAULT_SC_RIGHT_MAX | RADEON_DEFAULT_SC_BOTTOM_MAX); 2711 2712 radeonfb_wait_fifo(sc, 1); 2713 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 2714 (dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT) | 2715 RADEON_GMC_CLR_CMP_CNTL_DIS | 2716 RADEON_GMC_BRUSH_SOLID_COLOR | 2717 RADEON_GMC_SRC_DATATYPE_COLOR); 2718 2719 radeonfb_wait_fifo(sc, 7); 2720 PUT32(sc, RADEON_DST_LINE_START, 0); 2721 PUT32(sc, RADEON_DST_LINE_END, 0); 2722 PUT32(sc, RADEON_DP_BRUSH_FRGD_CLR, 0xffffffff); 2723 PUT32(sc, RADEON_DP_BRUSH_BKGD_CLR, 0); 2724 PUT32(sc, RADEON_DP_SRC_FRGD_CLR, 0xffffffff); 2725 PUT32(sc, RADEON_DP_SRC_BKGD_CLR, 0); 2726 PUT32(sc, RADEON_DP_WRITE_MASK, 0xffffffff); 2727 2728 radeonfb_engine_idle(sc); 2729 } 2730 2731 static void 2732 radeonfb_engine_reset(struct radeonfb_softc *sc) 2733 { 2734 uint32_t hpc, rbbm, mclkcntl, clkindex; 2735 2736 radeonfb_engine_flush(sc); 2737 2738 clkindex = GET32(sc, RADEON_CLOCK_CNTL_INDEX); 2739 if (HAS_R300CG(sc)) 2740 radeonfb_r300cg_workaround(sc); 2741 mclkcntl = GETPLL(sc, RADEON_MCLK_CNTL); 2742 2743 /* 2744 * According to comments in XFree code, resetting the HDP via 2745 * the RBBM_SOFT_RESET can cause bad behavior on some systems. 2746 * So we use HOST_PATH_CNTL instead. 2747 */ 2748 2749 hpc = GET32(sc, RADEON_HOST_PATH_CNTL); 2750 rbbm = GET32(sc, RADEON_RBBM_SOFT_RESET); 2751 if (IS_R300(sc)) { 2752 PUT32(sc, RADEON_RBBM_SOFT_RESET, rbbm | 2753 RADEON_SOFT_RESET_CP | 2754 RADEON_SOFT_RESET_HI | 2755 RADEON_SOFT_RESET_E2); 2756 GET32(sc, RADEON_RBBM_SOFT_RESET); 2757 PUT32(sc, RADEON_RBBM_SOFT_RESET, 0); 2758 /* 2759 * XXX: this bit is not defined in any ATI docs I have, 2760 * nor in the XFree code, but XFree does it. Why? 2761 */ 2762 SET32(sc, RADEON_RB2D_DSTCACHE_MODE, (1<<17)); 2763 } else { 2764 PUT32(sc, RADEON_RBBM_SOFT_RESET, rbbm | 2765 RADEON_SOFT_RESET_CP | 2766 RADEON_SOFT_RESET_SE | 2767 RADEON_SOFT_RESET_RE | 2768 RADEON_SOFT_RESET_PP | 2769 RADEON_SOFT_RESET_E2 | 2770 RADEON_SOFT_RESET_RB); 2771 GET32(sc, RADEON_RBBM_SOFT_RESET); 2772 PUT32(sc, RADEON_RBBM_SOFT_RESET, rbbm & 2773 ~(RADEON_SOFT_RESET_CP | 2774 RADEON_SOFT_RESET_SE | 2775 RADEON_SOFT_RESET_RE | 2776 RADEON_SOFT_RESET_PP | 2777 RADEON_SOFT_RESET_E2 | 2778 RADEON_SOFT_RESET_RB)); 2779 GET32(sc, RADEON_RBBM_SOFT_RESET); 2780 } 2781 2782 PUT32(sc, RADEON_HOST_PATH_CNTL, hpc | RADEON_HDP_SOFT_RESET); 2783 GET32(sc, RADEON_HOST_PATH_CNTL); 2784 PUT32(sc, RADEON_HOST_PATH_CNTL, hpc); 2785 2786 if (IS_R300(sc)) 2787 PUT32(sc, RADEON_RBBM_SOFT_RESET, rbbm); 2788 2789 PUT32(sc, RADEON_CLOCK_CNTL_INDEX, clkindex); 2790 PUTPLL(sc, RADEON_MCLK_CNTL, mclkcntl); 2791 2792 if (HAS_R300CG(sc)) 2793 radeonfb_r300cg_workaround(sc); 2794 } 2795 2796 static int 2797 radeonfb_set_curpos(struct radeonfb_display *dp, struct wsdisplay_curpos *pos) 2798 { 2799 int x, y; 2800 2801 x = pos->x; 2802 y = pos->y; 2803 2804 /* 2805 * This doesn't let a cursor move off the screen. I'm not 2806 * sure if this will have negative effects for e.g. Xinerama. 2807 * I'd guess Xinerama handles it by changing the cursor shape, 2808 * but that needs verification. 2809 */ 2810 if (x >= dp->rd_virtx) 2811 x = dp->rd_virtx - 1; 2812 if (x < 0) 2813 x = 0; 2814 if (y >= dp->rd_virty) 2815 y = dp->rd_virty - 1; 2816 if (y < 0) 2817 y = 0; 2818 2819 dp->rd_cursor.rc_pos.x = x; 2820 dp->rd_cursor.rc_pos.y = y; 2821 2822 radeonfb_cursor_position(dp); 2823 return 0; 2824 } 2825 2826 static int 2827 radeonfb_set_cursor(struct radeonfb_display *dp, struct wsdisplay_cursor *wc) 2828 { 2829 unsigned flags; 2830 2831 uint8_t r[2], g[2], b[2]; 2832 unsigned index, count; 2833 int i, err; 2834 int pitch, size; 2835 struct radeonfb_cursor nc; 2836 2837 flags = wc->which; 2838 2839 /* copy old values */ 2840 nc = dp->rd_cursor; 2841 2842 if (flags & WSDISPLAY_CURSOR_DOCMAP) { 2843 index = wc->cmap.index; 2844 count = wc->cmap.count; 2845 2846 if (index >= 2 || (index + count) > 2) 2847 return EINVAL; 2848 2849 err = copyin(wc->cmap.red, &r[index], count); 2850 if (err) 2851 return err; 2852 err = copyin(wc->cmap.green, &g[index], count); 2853 if (err) 2854 return err; 2855 err = copyin(wc->cmap.blue, &b[index], count); 2856 if (err) 2857 return err; 2858 2859 for (i = index; i < index + count; i++) { 2860 nc.rc_cmap[i] = 2861 (r[i] << 16) + (g[i] << 8) + (b[i] << 0); 2862 } 2863 } 2864 2865 if (flags & WSDISPLAY_CURSOR_DOSHAPE) { 2866 if ((wc->size.x > RADEON_CURSORMAXX) || 2867 (wc->size.y > RADEON_CURSORMAXY)) 2868 return EINVAL; 2869 2870 /* figure bytes per line */ 2871 pitch = (wc->size.x + 7) / 8; 2872 size = pitch * wc->size.y; 2873 2874 /* clear the old cursor and mask */ 2875 memset(nc.rc_image, 0, 512); 2876 memset(nc.rc_mask, 0, 512); 2877 2878 nc.rc_size = wc->size; 2879 2880 if ((err = copyin(wc->image, nc.rc_image, size)) != 0) 2881 return err; 2882 2883 if ((err = copyin(wc->mask, nc.rc_mask, size)) != 0) 2884 return err; 2885 } 2886 2887 if (flags & WSDISPLAY_CURSOR_DOHOT) { 2888 nc.rc_hot = wc->hot; 2889 if (nc.rc_hot.x >= nc.rc_size.x) 2890 nc.rc_hot.x = nc.rc_size.x - 1; 2891 if (nc.rc_hot.y >= nc.rc_size.y) 2892 nc.rc_hot.y = nc.rc_size.y - 1; 2893 } 2894 2895 if (flags & WSDISPLAY_CURSOR_DOPOS) { 2896 nc.rc_pos = wc->pos; 2897 if (nc.rc_pos.x >= dp->rd_virtx) 2898 nc.rc_pos.x = dp->rd_virtx - 1; 2899 #if 0 2900 if (nc.rc_pos.x < 0) 2901 nc.rc_pos.x = 0; 2902 #endif 2903 if (nc.rc_pos.y >= dp->rd_virty) 2904 nc.rc_pos.y = dp->rd_virty - 1; 2905 #if 0 2906 if (nc.rc_pos.y < 0) 2907 nc.rc_pos.y = 0; 2908 #endif 2909 } 2910 if (flags & WSDISPLAY_CURSOR_DOCUR) { 2911 nc.rc_visible = wc->enable; 2912 } 2913 2914 dp->rd_cursor = nc; 2915 radeonfb_cursor_update(dp, wc->which); 2916 2917 return 0; 2918 } 2919 2920 /* 2921 * Change the cursor shape. Call this with the cursor locked to avoid 2922 * flickering/tearing. 2923 */ 2924 static void 2925 radeonfb_cursor_shape(struct radeonfb_display *dp) 2926 { 2927 uint8_t and[512], xor[512]; 2928 int i, j, src, dst, pitch; 2929 const uint8_t *msk = dp->rd_cursor.rc_mask; 2930 const uint8_t *img = dp->rd_cursor.rc_image; 2931 2932 /* 2933 * Radeon cursor data interleaves one line of AND data followed 2934 * by a line of XOR data. (Each line corresponds to a whole hardware 2935 * pitch - i.e. 64 pixels or 8 bytes.) 2936 * 2937 * The cursor is displayed using the following table: 2938 * 2939 * AND XOR Result 2940 * ---------------------- 2941 * 0 0 Cursor color 0 2942 * 0 1 Cursor color 1 2943 * 1 0 Transparent 2944 * 1 1 Complement of background 2945 * 2946 * Our masks are therefore different from what we were passed. 2947 * Passed in, I'm assuming the data represents either color 0 or 1, 2948 * and a mask, so the passed in table looks like: 2949 * 2950 * IMG Mask Result 2951 * ----------------------- 2952 * 0 0 Transparent 2953 * 0 1 Cursor color 0 2954 * 1 0 Transparent 2955 * 1 1 Cursor color 1 2956 * 2957 * IF mask bit == 1, AND = 0, XOR = color. 2958 * IF mask bit == 0, AND = 1, XOR = 0. 2959 * 2960 * hence: AND = ~(mask); XOR = color & ~(mask); 2961 */ 2962 2963 pitch = ((dp->rd_cursor.rc_size.x + 7) / 8); 2964 2965 /* start by assuming all bits are transparent */ 2966 memset(and, 0xff, 512); 2967 memset(xor, 0x00, 512); 2968 2969 src = 0; 2970 dst = 0; 2971 for (i = 0; i < 64; i++) { 2972 for (j = 0; j < 64; j += 8) { 2973 if ((i < dp->rd_cursor.rc_size.y) && 2974 (j < dp->rd_cursor.rc_size.x)) { 2975 2976 /* take care to leave odd bits alone */ 2977 and[dst] &= ~(msk[src]); 2978 xor[dst] = img[src] & msk[src]; 2979 src++; 2980 } 2981 dst++; 2982 } 2983 } 2984 2985 /* copy the image into place */ 2986 for (i = 0; i < 64; i++) { 2987 memcpy((uint8_t *)dp->rd_curptr + (i * 16), 2988 &and[i * 8], 8); 2989 memcpy((uint8_t *)dp->rd_curptr + (i * 16) + 8, 2990 &xor[i * 8], 8); 2991 } 2992 } 2993 2994 static void 2995 radeonfb_cursor_position(struct radeonfb_display *dp) 2996 { 2997 struct radeonfb_softc *sc = dp->rd_softc; 2998 uint32_t offset, hvoff, hvpos; /* registers */ 2999 uint32_t coff; /* cursor offset */ 3000 int i, x, y, xoff, yoff, crtcoff; 3001 3002 /* 3003 * XXX: this also needs to handle pan/scan 3004 */ 3005 for (i = 0; i < dp->rd_ncrtcs; i++) { 3006 3007 struct radeonfb_crtc *rcp = &dp->rd_crtcs[i]; 3008 3009 if (rcp->rc_number) { 3010 offset = RADEON_CUR2_OFFSET; 3011 hvoff = RADEON_CUR2_HORZ_VERT_OFF; 3012 hvpos = RADEON_CUR2_HORZ_VERT_POSN; 3013 crtcoff = RADEON_CRTC2_OFFSET; 3014 } else { 3015 offset = RADEON_CUR_OFFSET; 3016 hvoff = RADEON_CUR_HORZ_VERT_OFF; 3017 hvpos = RADEON_CUR_HORZ_VERT_POSN; 3018 crtcoff = RADEON_CRTC_OFFSET; 3019 } 3020 3021 x = dp->rd_cursor.rc_pos.x; 3022 y = dp->rd_cursor.rc_pos.y; 3023 3024 while (y < rcp->rc_yoffset) { 3025 rcp->rc_yoffset -= RADEON_PANINCREMENT; 3026 } 3027 while (y >= (rcp->rc_yoffset + rcp->rc_videomode.vdisplay)) { 3028 rcp->rc_yoffset += RADEON_PANINCREMENT; 3029 } 3030 while (x < rcp->rc_xoffset) { 3031 rcp->rc_xoffset -= RADEON_PANINCREMENT; 3032 } 3033 while (x >= (rcp->rc_xoffset + rcp->rc_videomode.hdisplay)) { 3034 rcp->rc_xoffset += RADEON_PANINCREMENT; 3035 } 3036 3037 /* adjust for the cursor's hotspot */ 3038 x -= dp->rd_cursor.rc_hot.x; 3039 y -= dp->rd_cursor.rc_hot.y; 3040 xoff = yoff = 0; 3041 3042 if (x >= dp->rd_virtx) 3043 x = dp->rd_virtx - 1; 3044 if (y >= dp->rd_virty) 3045 y = dp->rd_virty - 1; 3046 3047 /* now adjust cursor so it is relative to viewport */ 3048 x -= rcp->rc_xoffset; 3049 y -= rcp->rc_yoffset; 3050 3051 /* 3052 * no need to check for fall off, because we should 3053 * never move off the screen entirely! 3054 */ 3055 coff = 0; 3056 if (x < 0) { 3057 xoff = -x; 3058 x = 0; 3059 } 3060 if (y < 0) { 3061 yoff = -y; 3062 y = 0; 3063 coff = (yoff * 2) * 8; 3064 } 3065 3066 /* pan the display */ 3067 PUT32(sc, crtcoff, (rcp->rc_yoffset * dp->rd_stride) + 3068 rcp->rc_xoffset); 3069 3070 PUT32(sc, offset, (dp->rd_curoff + coff) | RADEON_CUR_LOCK); 3071 PUT32(sc, hvoff, (xoff << 16) | (yoff) | RADEON_CUR_LOCK); 3072 /* NB: this unlocks the cursor */ 3073 PUT32(sc, hvpos, (x << 16) | y); 3074 } 3075 } 3076 3077 static void 3078 radeonfb_cursor_visible(struct radeonfb_display *dp) 3079 { 3080 int i; 3081 uint32_t gencntl, bit; 3082 3083 for (i = 0; i < dp->rd_ncrtcs; i++) { 3084 if (dp->rd_crtcs[i].rc_number) { 3085 gencntl = RADEON_CRTC2_GEN_CNTL; 3086 bit = RADEON_CRTC2_CUR_EN; 3087 } else { 3088 gencntl = RADEON_CRTC_GEN_CNTL; 3089 bit = RADEON_CRTC_CUR_EN; 3090 } 3091 3092 if (dp->rd_cursor.rc_visible) 3093 SET32(dp->rd_softc, gencntl, bit); 3094 else 3095 CLR32(dp->rd_softc, gencntl, bit); 3096 } 3097 } 3098 3099 static void 3100 radeonfb_cursor_cmap(struct radeonfb_display *dp) 3101 { 3102 int i; 3103 uint32_t c0reg, c1reg; 3104 struct radeonfb_softc *sc = dp->rd_softc; 3105 3106 for (i = 0; i < dp->rd_ncrtcs; i++) { 3107 if (dp->rd_crtcs[i].rc_number) { 3108 c0reg = RADEON_CUR2_CLR0; 3109 c1reg = RADEON_CUR2_CLR1; 3110 } else { 3111 c0reg = RADEON_CUR_CLR0; 3112 c1reg = RADEON_CUR_CLR1; 3113 } 3114 3115 PUT32(sc, c0reg, dp->rd_cursor.rc_cmap[0]); 3116 PUT32(sc, c1reg, dp->rd_cursor.rc_cmap[1]); 3117 } 3118 } 3119 3120 static void 3121 radeonfb_cursor_update(struct radeonfb_display *dp, unsigned which) 3122 { 3123 struct radeonfb_softc *sc; 3124 int i; 3125 3126 sc = dp->rd_softc; 3127 for (i = 0; i < dp->rd_ncrtcs; i++) { 3128 if (dp->rd_crtcs[i].rc_number) { 3129 SET32(sc, RADEON_CUR2_OFFSET, RADEON_CUR_LOCK); 3130 } else { 3131 SET32(sc, RADEON_CUR_OFFSET,RADEON_CUR_LOCK); 3132 } 3133 } 3134 3135 if (which & WSDISPLAY_CURSOR_DOCMAP) 3136 radeonfb_cursor_cmap(dp); 3137 3138 if (which & WSDISPLAY_CURSOR_DOSHAPE) 3139 radeonfb_cursor_shape(dp); 3140 3141 if (which & WSDISPLAY_CURSOR_DOCUR) 3142 radeonfb_cursor_visible(dp); 3143 3144 /* this one is unconditional, because it updates other stuff */ 3145 radeonfb_cursor_position(dp); 3146 } 3147 3148 static struct videomode * 3149 radeonfb_best_refresh(struct videomode *m1, struct videomode *m2) 3150 { 3151 int r1, r2; 3152 3153 /* otherwise pick the higher refresh rate */ 3154 r1 = DIVIDE(DIVIDE(m1->dot_clock, m1->htotal), m1->vtotal); 3155 r2 = DIVIDE(DIVIDE(m2->dot_clock, m2->htotal), m2->vtotal); 3156 3157 return (r1 < r2 ? m2 : m1); 3158 } 3159 3160 static const struct videomode * 3161 radeonfb_port_mode(struct radeonfb_softc *sc, struct radeonfb_port *rp, 3162 int x, int y) 3163 { 3164 struct edid_info *ep = &rp->rp_edid; 3165 struct videomode *vmp = NULL; 3166 int i; 3167 3168 if (!rp->rp_edid_valid) { 3169 /* fallback to safe mode */ 3170 return radeonfb_modelookup(sc->sc_defaultmode); 3171 } 3172 3173 /* always choose the preferred mode first! */ 3174 if (ep->edid_preferred_mode) { 3175 3176 /* XXX: add auto-stretching support for native mode */ 3177 3178 /* this may want panning to occur, btw */ 3179 if ((ep->edid_preferred_mode->hdisplay <= x) && 3180 (ep->edid_preferred_mode->vdisplay <= y)) 3181 return ep->edid_preferred_mode; 3182 } 3183 3184 for (i = 0; i < ep->edid_nmodes; i++) { 3185 /* 3186 * We elect to pick a resolution that is too large for 3187 * the monitor than one that is too small. This means 3188 * that we will prefer to pan rather than to try to 3189 * center a smaller display on a larger screen. In 3190 * practice, this shouldn't matter because if a 3191 * monitor can support a larger resolution, it can 3192 * probably also support the smaller. A specific 3193 * exception is fixed format panels, but hopefully 3194 * they are properly dealt with by the "autostretch" 3195 * logic above. 3196 */ 3197 if ((ep->edid_modes[i].hdisplay > x) || 3198 (ep->edid_modes[i].vdisplay > y)) { 3199 continue; 3200 } 3201 3202 /* 3203 * at this point, the display mode is no larger than 3204 * what we've requested. 3205 */ 3206 if (vmp == NULL) 3207 vmp = &ep->edid_modes[i]; 3208 3209 /* eliminate smaller modes */ 3210 if ((vmp->hdisplay >= ep->edid_modes[i].hdisplay) || 3211 (vmp->vdisplay >= ep->edid_modes[i].vdisplay)) 3212 continue; 3213 3214 if ((vmp->hdisplay < ep->edid_modes[i].hdisplay) || 3215 (vmp->vdisplay < ep->edid_modes[i].vdisplay)) { 3216 vmp = &ep->edid_modes[i]; 3217 continue; 3218 } 3219 3220 KASSERT(vmp->hdisplay == ep->edid_modes[i].hdisplay); 3221 KASSERT(vmp->vdisplay == ep->edid_modes[i].vdisplay); 3222 3223 vmp = radeonfb_best_refresh(vmp, &ep->edid_modes[i]); 3224 } 3225 3226 return (vmp ? vmp : radeonfb_modelookup(sc->sc_defaultmode)); 3227 } 3228 3229 static int 3230 radeonfb_hasres(struct videomode *list, int nlist, int x, int y) 3231 { 3232 int i; 3233 3234 for (i = 0; i < nlist; i++) { 3235 if ((x == list[i].hdisplay) && 3236 (y == list[i].vdisplay)) { 3237 return 1; 3238 } 3239 } 3240 return 0; 3241 } 3242 3243 static void 3244 radeonfb_pickres(struct radeonfb_display *dp, uint16_t *x, uint16_t *y, 3245 int pan) 3246 { 3247 struct radeonfb_port *rp; 3248 struct edid_info *ep; 3249 int i, j; 3250 3251 *x = 0; 3252 *y = 0; 3253 3254 if (pan) { 3255 for (i = 0; i < dp->rd_ncrtcs; i++) { 3256 rp = dp->rd_crtcs[i].rc_port; 3257 ep = &rp->rp_edid; 3258 if (!rp->rp_edid_valid) { 3259 /* monitor not present */ 3260 continue; 3261 } 3262 3263 /* 3264 * For now we are ignoring "conflict" that 3265 * could occur when mixing some modes like 3266 * 1280x1024 and 1400x800. It isn't clear 3267 * which is better, so the first one wins. 3268 */ 3269 for (j = 0; j < ep->edid_nmodes; j++) { 3270 /* 3271 * ignore resolutions that are too big for 3272 * the radeon 3273 */ 3274 if (ep->edid_modes[j].hdisplay > 3275 dp->rd_softc->sc_maxx) 3276 continue; 3277 if (ep->edid_modes[j].vdisplay > 3278 dp->rd_softc->sc_maxy) 3279 continue; 3280 3281 /* 3282 * pick largest resolution, the 3283 * smaller monitor will pan 3284 */ 3285 if ((ep->edid_modes[j].hdisplay >= *x) && 3286 (ep->edid_modes[j].vdisplay >= *y)) { 3287 *x = ep->edid_modes[j].hdisplay; 3288 *y = ep->edid_modes[j].vdisplay; 3289 } 3290 } 3291 } 3292 3293 } else { 3294 struct videomode modes[64]; 3295 int nmodes = 0; 3296 int valid = 0; 3297 3298 for (i = 0; i < dp->rd_ncrtcs; i++) { 3299 /* 3300 * pick the largest resolution in common. 3301 */ 3302 rp = dp->rd_crtcs[i].rc_port; 3303 ep = &rp->rp_edid; 3304 3305 if (!rp->rp_edid_valid) 3306 continue; 3307 3308 if (!valid) { 3309 /* initialize starting list */ 3310 for (j = 0; j < ep->edid_nmodes; j++) { 3311 /* 3312 * ignore resolutions that are 3313 * too big for the radeon 3314 */ 3315 if (ep->edid_modes[j].hdisplay > 3316 dp->rd_softc->sc_maxx) 3317 continue; 3318 if (ep->edid_modes[j].vdisplay > 3319 dp->rd_softc->sc_maxy) 3320 continue; 3321 3322 modes[nmodes] = ep->edid_modes[j]; 3323 nmodes++; 3324 } 3325 valid = 1; 3326 } else { 3327 /* merge into preexisting list */ 3328 for (j = 0; j < nmodes; j++) { 3329 if (!radeonfb_hasres(ep->edid_modes, 3330 ep->edid_nmodes, 3331 modes[j].hdisplay, 3332 modes[j].vdisplay)) { 3333 modes[j] = modes[nmodes]; 3334 j--; 3335 nmodes--; 3336 } 3337 } 3338 } 3339 } 3340 3341 /* now we have to pick from the merged list */ 3342 for (i = 0; i < nmodes; i++) { 3343 if ((modes[i].hdisplay >= *x) && 3344 (modes[i].vdisplay >= *y)) { 3345 *x = modes[i].hdisplay; 3346 *y = modes[i].vdisplay; 3347 } 3348 } 3349 } 3350 3351 if ((*x == 0) || (*y == 0)) { 3352 /* fallback to safe mode */ 3353 *x = 640; 3354 *y = 480; 3355 } 3356 } 3357 3358 3359 /* Get the current backlight level for the display. */ 3360 3361 static int 3362 radeonfb_get_backlight(struct radeonfb_display *dp) 3363 { 3364 int s; 3365 uint32_t level; 3366 3367 s = spltty(); 3368 3369 level = radeonfb_get32(dp->rd_softc, RADEON_LVDS_GEN_CNTL); 3370 level &= RADEON_LVDS_BL_MOD_LEV_MASK; 3371 level >>= RADEON_LVDS_BL_MOD_LEV_SHIFT; 3372 3373 /* 3374 * On some chips, we should negate the backlight level. 3375 * XXX Find out on which chips. 3376 */ 3377 #ifdef RADEONFB_BACKLIGHT_NEGATED 3378 level = RADEONFB_BACKLIGHT_MAX - level; 3379 #endif /* RADEONFB_BACKLIGHT_NEGATED */ 3380 3381 splx(s); 3382 3383 return level; 3384 } 3385 3386 /* Set the backlight to the given level for the display. */ 3387 3388 static int 3389 radeonfb_set_backlight(struct radeonfb_display *dp, int level) 3390 { 3391 struct radeonfb_softc *sc; 3392 int rlevel, s; 3393 uint32_t lvds; 3394 3395 s = spltty(); 3396 3397 if (level < 0) 3398 level = 0; 3399 else if (level >= RADEONFB_BACKLIGHT_MAX) 3400 level = RADEONFB_BACKLIGHT_MAX; 3401 3402 sc = dp->rd_softc; 3403 3404 /* On some chips, we should negate the backlight level. */ 3405 #ifdef RADEONFB_BACKLIGHT_NEGATED 3406 rlevel = RADEONFB_BACKLIGHT_MAX - level; 3407 #else 3408 rlevel = level; 3409 #endif /* RADEONFB_BACKLIGHT_NEGATED */ 3410 3411 callout_stop(&dp->rd_bl_lvds_co); 3412 radeonfb_engine_idle(sc); 3413 3414 /* 3415 * Turn off the display if the backlight is set to 0, since the 3416 * display is useless without backlight anyway. 3417 */ 3418 if (level == 0) 3419 radeonfb_blank(dp, 1); 3420 else if (radeonfb_get_backlight(dp) == 0) 3421 radeonfb_blank(dp, 0); 3422 3423 lvds = radeonfb_get32(sc, RADEON_LVDS_GEN_CNTL); 3424 lvds &= ~RADEON_LVDS_DISPLAY_DIS; 3425 if (!(lvds & RADEON_LVDS_BLON) || !(lvds & RADEON_LVDS_ON)) { 3426 lvds |= dp->rd_bl_lvds_val & RADEON_LVDS_DIGON; 3427 lvds |= RADEON_LVDS_BLON | RADEON_LVDS_EN; 3428 radeonfb_put32(sc, RADEON_LVDS_GEN_CNTL, lvds); 3429 lvds &= ~RADEON_LVDS_BL_MOD_LEV_MASK; 3430 lvds |= rlevel << RADEON_LVDS_BL_MOD_LEV_SHIFT; 3431 lvds |= RADEON_LVDS_ON; 3432 lvds |= dp->rd_bl_lvds_val & RADEON_LVDS_BL_MOD_EN; 3433 } else { 3434 lvds &= ~RADEON_LVDS_BL_MOD_LEV_MASK; 3435 lvds |= rlevel << RADEON_LVDS_BL_MOD_LEV_SHIFT; 3436 radeonfb_put32(sc, RADEON_LVDS_GEN_CNTL, lvds); 3437 } 3438 3439 dp->rd_bl_lvds_val &= ~RADEON_LVDS_STATE_MASK; 3440 dp->rd_bl_lvds_val |= lvds & RADEON_LVDS_STATE_MASK; 3441 /* XXX What is the correct delay? */ 3442 callout_schedule(&dp->rd_bl_lvds_co, 200 * hz); 3443 3444 splx(s); 3445 3446 return 0; 3447 } 3448 3449 /* 3450 * Callout function for delayed operations on the LVDS_GEN_CNTL register. 3451 * Set the delayed bits in the register, and clear the stored delayed 3452 * value. 3453 */ 3454 3455 static void radeonfb_lvds_callout(void *arg) 3456 { 3457 struct radeonfb_display *dp = arg; 3458 int s; 3459 3460 s = splhigh(); 3461 3462 radeonfb_mask32(dp->rd_softc, RADEON_LVDS_GEN_CNTL, ~0, 3463 dp->rd_bl_lvds_val); 3464 dp->rd_bl_lvds_val = 0; 3465 3466 splx(s); 3467 } 3468
Indexes created Tue Sep 23 07:09:52 GMT 2025