radeonfb.c revision 1.19
1 /* $NetBSD: radeonfb.c,v 1.19 2007/09/02 18:47:27 macallan Exp $ */ 2 3 /*- 4 * Copyright (c) 2006 Itronix Inc. 5 * All rights reserved. 6 * 7 * Written by Garrett D'Amore for Itronix Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. The name of Itronix Inc. may not be used to endorse 18 * or promote products derived from this software without specific 19 * prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY ITRONIX INC. ``AS IS'' AND ANY EXPRESS 22 * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 23 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL ITRONIX INC. BE LIABLE FOR ANY 25 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE 27 * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 29 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 30 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 31 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * ATI Technologies Inc. ("ATI") has not assisted in the creation of, and 36 * does not endorse, this software. ATI will not be responsible or liable 37 * for any actual or alleged damage or loss caused by or in connection with 38 * the use of or reliance on this software. 39 */ 40 41 /* 42 * Portions of this code were taken from XFree86's Radeon driver, which bears 43 * this notice: 44 * 45 * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and 46 * VA Linux Systems Inc., Fremont, California. 47 * 48 * All Rights Reserved. 49 * 50 * Permission is hereby granted, free of charge, to any person obtaining 51 * a copy of this software and associated documentation files (the 52 * "Software"), to deal in the Software without restriction, including 53 * without limitation on the rights to use, copy, modify, merge, 54 * publish, distribute, sublicense, and/or sell copies of the Software, 55 * and to permit persons to whom the Software is furnished to do so, 56 * subject to the following conditions: 57 * 58 * The above copyright notice and this permission notice (including the 59 * next paragraph) shall be included in all copies or substantial 60 * portions of the Software. 61 * 62 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 63 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 64 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 65 * NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR 66 * THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 67 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 68 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 69 * DEALINGS IN THE SOFTWARE. 70 */ 71 72 #include <sys/cdefs.h> 73 __KERNEL_RCSID(0, "$NetBSD: radeonfb.c,v 1.19 2007/09/02 18:47:27 macallan Exp $"); 74 75 #define RADEONFB_DEFAULT_DEPTH 32 76 77 #include <sys/param.h> 78 #include <sys/systm.h> 79 #include <sys/device.h> 80 #include <sys/malloc.h> 81 #include <machine/bus.h> 82 #include <sys/kernel.h> 83 #include <sys/lwp.h> 84 #include <sys/kauth.h> 85 86 #include <dev/wscons/wsdisplayvar.h> 87 #include <dev/wscons/wsconsio.h> 88 #include <dev/wsfont/wsfont.h> 89 #include <dev/rasops/rasops.h> 90 #include <dev/videomode/videomode.h> 91 #include <dev/videomode/edidvar.h> 92 #include <dev/wscons/wsdisplay_vconsvar.h> 93 94 #include <dev/pci/pcidevs.h> 95 #include <dev/pci/pcireg.h> 96 #include <dev/pci/pcivar.h> 97 #include <dev/pci/radeonfbreg.h> 98 #include <dev/pci/radeonfbvar.h> 99 #include "opt_radeonfb.h" 100 101 static int radeonfb_match(struct device *, struct cfdata *, void *); 102 static void radeonfb_attach(struct device *, struct device *, void *); 103 static int radeonfb_ioctl(void *, void *, unsigned long, void *, int, 104 struct lwp *); 105 static paddr_t radeonfb_mmap(void *, void *, off_t, int); 106 static int radeonfb_scratch_test(struct radeonfb_softc *, int, uint32_t); 107 static void radeonfb_loadbios(struct radeonfb_softc *, 108 struct pci_attach_args *); 109 110 static uintmax_t radeonfb_getprop_num(struct radeonfb_softc *, const char *, 111 uintmax_t); 112 static int radeonfb_getclocks(struct radeonfb_softc *); 113 static int radeonfb_gettmds(struct radeonfb_softc *); 114 static int radeonfb_calc_dividers(struct radeonfb_softc *, uint32_t, 115 uint32_t *, uint32_t *); 116 static int radeonfb_getconnectors(struct radeonfb_softc *); 117 static const struct videomode *radeonfb_modelookup(const char *); 118 static void radeonfb_init_screen(void *, struct vcons_screen *, int, long *); 119 static void radeonfb_pllwriteupdate(struct radeonfb_softc *, int); 120 static void radeonfb_pllwaitatomicread(struct radeonfb_softc *, int); 121 static void radeonfb_program_vclk(struct radeonfb_softc *, int, int); 122 static void radeonfb_modeswitch(struct radeonfb_display *); 123 static void radeonfb_setcrtc(struct radeonfb_display *, int); 124 static void radeonfb_init_misc(struct radeonfb_softc *); 125 static void radeonfb_set_fbloc(struct radeonfb_softc *); 126 static void radeonfb_init_palette(struct radeonfb_softc *, int); 127 static void radeonfb_r300cg_workaround(struct radeonfb_softc *); 128 129 static int radeonfb_isblank(struct radeonfb_display *); 130 static void radeonfb_blank(struct radeonfb_display *, int); 131 static int radeonfb_set_cursor(struct radeonfb_display *, 132 struct wsdisplay_cursor *); 133 static int radeonfb_set_curpos(struct radeonfb_display *, 134 struct wsdisplay_curpos *); 135 136 /* acceleration support */ 137 static void radeonfb_rectfill(struct radeonfb_display *, int dstx, int dsty, 138 int width, int height, uint32_t color); 139 static void radeonfb_bitblt(struct radeonfb_display *, int srcx, int srcy, 140 int dstx, int dsty, int width, int height, int rop, uint32_t mask); 141 static void radeonfb_feed_bytes(struct radeonfb_display *, int, uint8_t *); 142 static void radeonfb_setup_mono(struct radeonfb_display *, int, int, int, 143 int, uint32_t, uint32_t); 144 145 /* hw cursor support */ 146 static void radeonfb_cursor_cmap(struct radeonfb_display *); 147 static void radeonfb_cursor_shape(struct radeonfb_display *); 148 static void radeonfb_cursor_position(struct radeonfb_display *); 149 static void radeonfb_cursor_visible(struct radeonfb_display *); 150 static void radeonfb_cursor_update(struct radeonfb_display *, unsigned); 151 152 static void radeonfb_wait_fifo(struct radeonfb_softc *, int); 153 static void radeonfb_engine_idle(struct radeonfb_softc *); 154 static void radeonfb_engine_flush(struct radeonfb_softc *); 155 static void radeonfb_engine_reset(struct radeonfb_softc *); 156 static void radeonfb_engine_init(struct radeonfb_display *); 157 static inline void radeonfb_unclip(struct radeonfb_softc *); 158 159 static void radeonfb_eraserows(void *, int, int, long); 160 static void radeonfb_erasecols(void *, int, int, int, long); 161 static void radeonfb_copyrows(void *, int, int, int); 162 static void radeonfb_copycols(void *, int, int, int, int); 163 static void radeonfb_cursor(void *, int, int, int); 164 static void radeonfb_putchar(void *, int, int, unsigned, long); 165 static int radeonfb_allocattr(void *, int, int, int, long *); 166 167 static int radeonfb_get_backlight(struct radeonfb_display *); 168 static int radeonfb_set_backlight(struct radeonfb_display *, int); 169 static void radeonfb_lvds_callout(void *); 170 171 static struct videomode *radeonfb_best_refresh(struct videomode *, 172 struct videomode *); 173 static void radeonfb_pickres(struct radeonfb_display *, uint16_t *, 174 uint16_t *, int); 175 static const struct videomode *radeonfb_port_mode(struct radeonfb_softc *, 176 struct radeonfb_port *, int, int); 177 178 static int radeonfb_drm_print(void *, const char *); 179 180 #ifdef RADEON_DEBUG 181 int radeon_debug = 1; 182 #define DPRINTF(x) \ 183 if (radeon_debug) printf x 184 #define PRINTREG(r) DPRINTF((#r " = %08x\n", GET32(sc, r))) 185 #define PRINTPLL(r) DPRINTF((#r " = %08x\n", GETPLL(sc, r))) 186 #else 187 #define DPRINTF(x) 188 #define PRINTREG(r) 189 #define PRINTPLL(r) 190 #endif 191 192 #define ROUNDUP(x,y) (((x) + ((y) - 1)) & ~((y) - 1)) 193 194 #ifndef RADEON_DEFAULT_MODE 195 /* any reasonably modern display should handle this */ 196 #define RADEON_DEFAULT_MODE "1024x768x60" 197 #endif 198 199 const char *radeonfb_default_mode = RADEON_DEFAULT_MODE; 200 201 static struct { 202 int size; /* minimum memory size (MB) */ 203 int maxx; /* maximum x dimension */ 204 int maxy; /* maximum y dimension */ 205 int maxbpp; /* maximum bpp */ 206 int maxdisp; /* maximum logical display count */ 207 } radeonfb_limits[] = { 208 { 32, 2048, 1536, 32, 2 }, 209 { 16, 1600, 1200, 32, 2 }, 210 { 8, 1600, 1200, 32, 1 }, 211 { 0, 0, 0, 0, 0 }, 212 }; 213 214 static struct wsscreen_descr radeonfb_stdscreen = { 215 "fb", /* name */ 216 0, 0, /* ncols, nrows */ 217 NULL, /* textops */ 218 8, 16, /* fontwidth, fontheight */ 219 WSSCREEN_WSCOLORS, /* capabilities */ 220 0, /* modecookie */ 221 }; 222 223 struct wsdisplay_accessops radeonfb_accessops = { 224 radeonfb_ioctl, 225 radeonfb_mmap, 226 NULL, /* vcons_alloc_screen */ 227 NULL, /* vcons_free_screen */ 228 NULL, /* vcons_show_screen */ 229 NULL, /* load_font */ 230 NULL, /* pollc */ 231 NULL, /* scroll */ 232 }; 233 234 static struct { 235 uint16_t devid; 236 uint16_t family; 237 uint16_t flags; 238 } radeonfb_devices[] = 239 { 240 /* R100 family */ 241 { PCI_PRODUCT_ATI_RADEON_R100_QD, RADEON_R100, 0 }, 242 { PCI_PRODUCT_ATI_RADEON_R100_QE, RADEON_R100, 0 }, 243 { PCI_PRODUCT_ATI_RADEON_R100_QF, RADEON_R100, 0 }, 244 { PCI_PRODUCT_ATI_RADEON_R100_QG, RADEON_R100, 0 }, 245 246 /* RV100 family */ 247 { PCI_PRODUCT_ATI_RADEON_RV100_LY, RADEON_RV100, RFB_MOB }, 248 { PCI_PRODUCT_ATI_RADEON_RV100_LZ, RADEON_RV100, RFB_MOB }, 249 { PCI_PRODUCT_ATI_RADEON_RV100_QY, RADEON_RV100, 0 }, 250 { PCI_PRODUCT_ATI_RADEON_RV100_QZ, RADEON_RV100, 0 }, 251 252 /* RS100 family */ 253 { PCI_PRODUCT_ATI_RADEON_RS100_4136, RADEON_RS100, 0 }, 254 { PCI_PRODUCT_ATI_RADEON_RS100_4336, RADEON_RS100, RFB_MOB }, 255 256 /* RS200/RS250 family */ 257 { PCI_PRODUCT_ATI_RADEON_RS200_4337, RADEON_RS200, RFB_MOB }, 258 { PCI_PRODUCT_ATI_RADEON_RS200_A7, RADEON_RS200, 0 }, 259 { PCI_PRODUCT_ATI_RADEON_RS250_B7, RADEON_RS200, RFB_MOB }, 260 { PCI_PRODUCT_ATI_RADEON_RS250_D7, RADEON_RS200, 0 }, 261 262 /* R200 family */ 263 /* add more R200 products? , 5148 */ 264 { PCI_PRODUCT_ATI_RADEON_R200_BB, RADEON_R200, 0 }, 265 { PCI_PRODUCT_ATI_RADEON_R200_BC, RADEON_R200, 0 }, 266 { PCI_PRODUCT_ATI_RADEON_R200_QH, RADEON_R200, 0 }, 267 { PCI_PRODUCT_ATI_RADEON_R200_QL, RADEON_R200, 0 }, 268 { PCI_PRODUCT_ATI_RADEON_R200_QM, RADEON_R200, 0 }, 269 270 /* RV200 family */ 271 { PCI_PRODUCT_ATI_RADEON_RV200_LW, RADEON_RV200, RFB_MOB }, 272 { PCI_PRODUCT_ATI_RADEON_RV200_LX, RADEON_RV200, RFB_MOB }, 273 { PCI_PRODUCT_ATI_RADEON_RV200_QW, RADEON_RV200, 0 }, 274 { PCI_PRODUCT_ATI_RADEON_RV200_QX, RADEON_RV200, 0 }, 275 276 /* RV250 family */ 277 { PCI_PRODUCT_ATI_RADEON_RV250_4966, RADEON_RV250, 0 }, 278 { PCI_PRODUCT_ATI_RADEON_RV250_4967, RADEON_RV250, 0 }, 279 { PCI_PRODUCT_ATI_RADEON_RV250_4C64, RADEON_RV250, RFB_MOB }, 280 { PCI_PRODUCT_ATI_RADEON_RV250_4C66, RADEON_RV250, RFB_MOB }, 281 { PCI_PRODUCT_ATI_RADEON_RV250_4C67, RADEON_RV250, RFB_MOB }, 282 283 /* RS300 family */ 284 { PCI_PRODUCT_ATI_RADEON_RS300_X5, RADEON_RS300, 0 }, 285 { PCI_PRODUCT_ATI_RADEON_RS300_X4, RADEON_RS300, 0 }, 286 { PCI_PRODUCT_ATI_RADEON_RS300_7834, RADEON_RS300, 0 }, 287 { PCI_PRODUCT_ATI_RADEON_RS300_7835, RADEON_RS300, RFB_MOB }, 288 289 /* RV280 family */ 290 { PCI_PRODUCT_ATI_RADEON_RV280_5960, RADEON_RV280, 0 }, 291 { PCI_PRODUCT_ATI_RADEON_RV280_5961, RADEON_RV280, 0 }, 292 { PCI_PRODUCT_ATI_RADEON_RV280_5962, RADEON_RV280, 0 }, 293 { PCI_PRODUCT_ATI_RADEON_RV280_5963, RADEON_RV280, 0 }, 294 { PCI_PRODUCT_ATI_RADEON_RV280_5964, RADEON_RV280, 0 }, 295 { PCI_PRODUCT_ATI_RADEON_RV280_5C61, RADEON_RV280, RFB_MOB }, 296 { PCI_PRODUCT_ATI_RADEON_RV280_5C63, RADEON_RV280, RFB_MOB }, 297 298 /* R300 family */ 299 { PCI_PRODUCT_ATI_RADEON_R300_AD, RADEON_R300, 0 }, 300 { PCI_PRODUCT_ATI_RADEON_R300_AE, RADEON_R300, 0 }, 301 { PCI_PRODUCT_ATI_RADEON_R300_AF, RADEON_R300, 0 }, 302 { PCI_PRODUCT_ATI_RADEON_R300_AG, RADEON_R300, 0 }, 303 { PCI_PRODUCT_ATI_RADEON_R300_ND, RADEON_R300, 0 }, 304 { PCI_PRODUCT_ATI_RADEON_R300_NE, RADEON_R300, 0 }, 305 { PCI_PRODUCT_ATI_RADEON_R300_NF, RADEON_R300, 0 }, 306 { PCI_PRODUCT_ATI_RADEON_R300_NG, RADEON_R300, 0 }, 307 308 /* RV350/RV360 family */ 309 { PCI_PRODUCT_ATI_RADEON_RV350_AP, RADEON_RV350, 0 }, 310 { PCI_PRODUCT_ATI_RADEON_RV350_AQ, RADEON_RV350, 0 }, 311 { PCI_PRODUCT_ATI_RADEON_RV360_AR, RADEON_RV350, 0 }, 312 { PCI_PRODUCT_ATI_RADEON_RV350_AS, RADEON_RV350, 0 }, 313 { PCI_PRODUCT_ATI_RADEON_RV350_AT, RADEON_RV350, 0 }, 314 { PCI_PRODUCT_ATI_RADEON_RV350_AV, RADEON_RV350, 0 }, 315 { PCI_PRODUCT_ATI_RADEON_RV350_NP, RADEON_RV350, RFB_MOB }, 316 { PCI_PRODUCT_ATI_RADEON_RV350_NQ, RADEON_RV350, RFB_MOB }, 317 { PCI_PRODUCT_ATI_RADEON_RV350_NR, RADEON_RV350, RFB_MOB }, 318 { PCI_PRODUCT_ATI_RADEON_RV350_NS, RADEON_RV350, RFB_MOB }, 319 { PCI_PRODUCT_ATI_RADEON_RV350_NT, RADEON_RV350, RFB_MOB }, 320 { PCI_PRODUCT_ATI_RADEON_RV350_NV, RADEON_RV350, RFB_MOB }, 321 322 /* R350/R360 family */ 323 { PCI_PRODUCT_ATI_RADEON_R350_AH, RADEON_R350, 0 }, 324 { PCI_PRODUCT_ATI_RADEON_R350_AI, RADEON_R350, 0 }, 325 { PCI_PRODUCT_ATI_RADEON_R350_AJ, RADEON_R350, 0 }, 326 { PCI_PRODUCT_ATI_RADEON_R350_AK, RADEON_R350, 0 }, 327 { PCI_PRODUCT_ATI_RADEON_R350_NH, RADEON_R350, 0 }, 328 { PCI_PRODUCT_ATI_RADEON_R350_NI, RADEON_R350, 0 }, 329 { PCI_PRODUCT_ATI_RADEON_R350_NK, RADEON_R350, 0 }, 330 { PCI_PRODUCT_ATI_RADEON_R360_NJ, RADEON_R350, 0 }, 331 332 /* RV380/RV370 family */ 333 { PCI_PRODUCT_ATI_RADEON_RV380_3150, RADEON_RV380, RFB_MOB }, 334 { PCI_PRODUCT_ATI_RADEON_RV380_3154, RADEON_RV380, RFB_MOB }, 335 { PCI_PRODUCT_ATI_RADEON_RV380_3E50, RADEON_RV380, 0 }, 336 { PCI_PRODUCT_ATI_RADEON_RV380_3E54, RADEON_RV380, 0 }, 337 { PCI_PRODUCT_ATI_RADEON_RV370_5460, RADEON_RV380, RFB_MOB }, 338 { PCI_PRODUCT_ATI_RADEON_RV370_5464, RADEON_RV380, RFB_MOB }, 339 { PCI_PRODUCT_ATI_RADEON_RV370_5B60, RADEON_RV380, 0 }, 340 { PCI_PRODUCT_ATI_RADEON_RV370_5B64, RADEON_RV380, 0 }, 341 { PCI_PRODUCT_ATI_RADEON_RV370_5B65, RADEON_RV380, 0 }, 342 343 /* R420/R423 family */ 344 { PCI_PRODUCT_ATI_RADEON_R420_JH, RADEON_R420, 0 }, 345 { PCI_PRODUCT_ATI_RADEON_R420_JI, RADEON_R420, 0 }, 346 { PCI_PRODUCT_ATI_RADEON_R420_JJ, RADEON_R420, 0 }, 347 { PCI_PRODUCT_ATI_RADEON_R420_JK, RADEON_R420, 0 }, 348 { PCI_PRODUCT_ATI_RADEON_R420_JL, RADEON_R420, 0 }, 349 { PCI_PRODUCT_ATI_RADEON_R420_JM, RADEON_R420, 0 }, 350 { PCI_PRODUCT_ATI_RADEON_R420_JN, RADEON_R420, RFB_MOB }, 351 { PCI_PRODUCT_ATI_RADEON_R420_JP, RADEON_R420, 0 }, 352 { PCI_PRODUCT_ATI_RADEON_R423_UH, RADEON_R420, 0 }, 353 { PCI_PRODUCT_ATI_RADEON_R423_UI, RADEON_R420, 0 }, 354 { PCI_PRODUCT_ATI_RADEON_R423_UJ, RADEON_R420, 0 }, 355 { PCI_PRODUCT_ATI_RADEON_R423_UK, RADEON_R420, 0 }, 356 { PCI_PRODUCT_ATI_RADEON_R423_UQ, RADEON_R420, 0 }, 357 { PCI_PRODUCT_ATI_RADEON_R423_UR, RADEON_R420, 0 }, 358 { PCI_PRODUCT_ATI_RADEON_R423_UT, RADEON_R420, 0 }, 359 { PCI_PRODUCT_ATI_RADEON_R423_5D57, RADEON_R420, 0 }, 360 361 { 0, 0, 0 } 362 }; 363 364 static struct { 365 int divider; 366 int mask; 367 } radeonfb_dividers[] = { 368 { 1, 0 }, 369 { 2, 1 }, 370 { 3, 4 }, 371 { 4, 2 }, 372 { 6, 6 }, 373 { 8, 3 }, 374 { 12, 7 }, 375 { 0, 0 } 376 }; 377 378 /* 379 * This table taken from X11. 380 */ 381 static const struct { 382 int family; 383 struct radeon_tmds_pll plls[4]; 384 } radeonfb_tmds_pll[] = { 385 { RADEON_R100, {{12000, 0xa1b}, {-1, 0xa3f}}}, 386 { RADEON_RV100, {{12000, 0xa1b}, {-1, 0xa3f}}}, 387 { RADEON_RS100, {{0, 0}}}, 388 { RADEON_RV200, {{15000, 0xa1b}, {-1, 0xa3f}}}, 389 { RADEON_RS200, {{15000, 0xa1b}, {-1, 0xa3f}}}, 390 { RADEON_R200, {{15000, 0xa1b}, {-1, 0xa3f}}}, 391 { RADEON_RV250, {{15500, 0x81b}, {-1, 0x83f}}}, 392 { RADEON_RS300, {{0, 0}}}, 393 { RADEON_RV280, {{13000, 0x400f4}, {15000, 0x400f7}}}, 394 { RADEON_R300, {{-1, 0xb01cb}}}, 395 { RADEON_R350, {{-1, 0xb01cb}}}, 396 { RADEON_RV350, {{15000, 0xb0155}, {-1, 0xb01cb}}}, 397 { RADEON_RV380, {{15000, 0xb0155}, {-1, 0xb01cb}}}, 398 { RADEON_R420, {{-1, 0xb01cb}}}, 399 }; 400 401 #define RADEONFB_BACKLIGHT_MAX 255 /* Maximum backlight level. */ 402 403 404 CFATTACH_DECL(radeonfb, sizeof (struct radeonfb_softc), 405 radeonfb_match, radeonfb_attach, NULL, NULL); 406 407 static int 408 radeonfb_match(struct device *parent, struct cfdata *match, void *aux) 409 { 410 struct pci_attach_args *pa = aux; 411 int i; 412 413 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_ATI) 414 return 0; 415 416 for (i = 0; radeonfb_devices[i].devid; i++) { 417 if (PCI_PRODUCT(pa->pa_id) == radeonfb_devices[i].devid) 418 return 100; /* high to defeat VGA/VESA */ 419 } 420 421 return 0; 422 } 423 424 static void 425 radeonfb_attach(struct device *parent, struct device *dev, void *aux) 426 { 427 struct radeonfb_softc *sc = (struct radeonfb_softc *)dev; 428 struct pci_attach_args *pa = aux; 429 const char *mptr; 430 bus_size_t bsz; 431 pcireg_t screg; 432 int i, j, fg, bg, ul; 433 uint32_t v; 434 435 sc->sc_id = pa->pa_id; 436 for (i = 0; radeonfb_devices[i].devid; i++) { 437 if (PCI_PRODUCT(sc->sc_id) == radeonfb_devices[i].devid) 438 break; 439 } 440 441 pci_devinfo(sc->sc_id, pa->pa_class, 0, sc->sc_devinfo, 442 sizeof(sc->sc_devinfo)); 443 444 aprint_naive("\n"); 445 aprint_normal(": %s\n", sc->sc_devinfo); 446 447 DPRINTF((prop_dictionary_externalize(device_properties(dev)))); 448 449 KASSERT(radeonfb_devices[i].devid != 0); 450 sc->sc_pt = pa->pa_tag; 451 sc->sc_iot = pa->pa_iot; 452 sc->sc_pc = pa->pa_pc; 453 sc->sc_family = radeonfb_devices[i].family; 454 sc->sc_flags = radeonfb_devices[i].flags; 455 456 /* enable memory and IO access */ 457 screg = pci_conf_read(sc->sc_pc, sc->sc_pt, PCI_COMMAND_STATUS_REG); 458 screg |= PCI_FLAGS_IO_ENABLED | PCI_FLAGS_MEM_ENABLED; 459 pci_conf_write(sc->sc_pc, sc->sc_pt, PCI_COMMAND_STATUS_REG, screg); 460 461 /* 462 * Some flags are general to entire chip families, and rather 463 * than clutter up the table with them, we go ahead and set 464 * them here. 465 */ 466 switch (sc->sc_family) { 467 case RADEON_RS100: 468 case RADEON_RS200: 469 sc->sc_flags |= RFB_IGP | RFB_RV100; 470 break; 471 472 case RADEON_RV100: 473 case RADEON_RV200: 474 case RADEON_RV250: 475 case RADEON_RV280: 476 sc->sc_flags |= RFB_RV100; 477 break; 478 479 case RADEON_RS300: 480 sc->sc_flags |= RFB_SDAC | RFB_IGP | RFB_RV100; 481 break; 482 483 case RADEON_R300: 484 case RADEON_RV350: 485 case RADEON_R350: 486 case RADEON_RV380: 487 case RADEON_R420: 488 /* newer chips */ 489 sc->sc_flags |= RFB_R300; 490 break; 491 492 case RADEON_R100: 493 sc->sc_flags |= RFB_NCRTC2; 494 break; 495 } 496 497 if ((sc->sc_family == RADEON_RV200) || 498 (sc->sc_family == RADEON_RV250) || 499 (sc->sc_family == RADEON_RV280) || 500 (sc->sc_family == RADEON_RV350)) { 501 bool inverted = 0; 502 /* backlight level is linear */ 503 DPRINTF(("found RV* chip, backlight is supposedly linear\n")); 504 prop_dictionary_get_bool(device_properties(&sc->sc_dev), 505 "backlight_level_reverted", &inverted); 506 if (inverted) { 507 DPRINTF(("nope, it's inverted\n")); 508 sc->sc_flags |= RFB_INV_BLIGHT; 509 } 510 } else 511 sc->sc_flags |= RFB_INV_BLIGHT; 512 513 /* 514 * XXX: to support true multihead, this must change. 515 */ 516 sc->sc_ndisplays = 1; 517 518 /* XXX: */ 519 if (!HAS_CRTC2(sc)) { 520 sc->sc_ndisplays = 1; 521 } 522 523 if (pci_mapreg_map(pa, RADEON_MAPREG_MMIO, PCI_MAPREG_TYPE_MEM, 0, 524 &sc->sc_regt, &sc->sc_regh, &sc->sc_regaddr, 525 &sc->sc_regsz) != 0) { 526 aprint_error("%s: unable to map registers!\n", XNAME(sc)); 527 goto error; 528 } 529 530 /* scratch register test... */ 531 if (radeonfb_scratch_test(sc, RADEON_BIOS_0_SCRATCH, 0x55555555) || 532 radeonfb_scratch_test(sc, RADEON_BIOS_0_SCRATCH, 0xaaaaaaaa)) { 533 aprint_error("%s: scratch register test failed!\n", XNAME(sc)); 534 goto error; 535 } 536 537 PRINTREG(RADEON_BIOS_4_SCRATCH); 538 PRINTREG(RADEON_FP_GEN_CNTL); 539 PRINTREG(RADEON_FP2_GEN_CNTL); 540 PRINTREG(RADEON_TMDS_CNTL); 541 PRINTREG(RADEON_TMDS_TRANSMITTER_CNTL); 542 PRINTREG(RADEON_TMDS_PLL_CNTL); 543 PRINTREG(RADEON_LVDS_GEN_CNTL); 544 PRINTREG(RADEON_FP_HORZ_STRETCH); 545 PRINTREG(RADEON_FP_VERT_STRETCH); 546 547 /* XXX: RV100 specific */ 548 PUT32(sc, RADEON_TMDS_PLL_CNTL, 0xa27); 549 550 PATCH32(sc, RADEON_TMDS_TRANSMITTER_CNTL, 551 RADEON_TMDS_TRANSMITTER_PLLEN, 552 RADEON_TMDS_TRANSMITTER_PLLEN | RADEON_TMDS_TRANSMITTER_PLLRST); 553 554 radeonfb_i2c_init(sc); 555 556 radeonfb_loadbios(sc, pa); 557 558 #ifdef RADEON_BIOS_INIT 559 if (radeonfb_bios_init(sc)) { 560 aprint_error("%s: BIOS inititialization failed\n", XNAME(sc)); 561 goto error; 562 } 563 #endif 564 565 if (radeonfb_getclocks(sc)) { 566 aprint_error("%s: Unable to get reference clocks from BIOS\n", 567 XNAME(sc)); 568 goto error; 569 } 570 571 if (radeonfb_gettmds(sc)) { 572 aprint_error("%s: Unable to identify TMDS PLL settings\n", 573 XNAME(sc)); 574 goto error; 575 } 576 577 aprint_verbose("%s: refclk = %d.%03d MHz, refdiv = %d " 578 "minpll = %d, maxpll = %d\n", XNAME(sc), 579 (int)sc->sc_refclk / 1000, (int)sc->sc_refclk % 1000, 580 (int)sc->sc_refdiv, (int)sc->sc_minpll, (int)sc->sc_maxpll); 581 582 radeonfb_getconnectors(sc); 583 584 radeonfb_set_fbloc(sc); 585 586 for (i = 0; radeonfb_limits[i].size; i++) { 587 if (sc->sc_memsz >= radeonfb_limits[i].size) { 588 sc->sc_maxx = radeonfb_limits[i].maxx; 589 sc->sc_maxy = radeonfb_limits[i].maxy; 590 sc->sc_maxbpp = radeonfb_limits[i].maxbpp; 591 /* framebuffer offset, start at a 4K page */ 592 sc->sc_fboffset = sc->sc_memsz / 593 radeonfb_limits[i].maxdisp; 594 /* 595 * we use the fbsize to figure out where we can store 596 * things like cursor data. 597 */ 598 sc->sc_fbsize = 599 ROUNDUP(ROUNDUP(sc->sc_maxx * sc->sc_maxbpp / 8 , 600 RADEON_STRIDEALIGN) * sc->sc_maxy, 601 4096); 602 break; 603 } 604 } 605 606 607 radeonfb_init_misc(sc); 608 radeonfb_init_palette(sc, 0); 609 if (HAS_CRTC2(sc)) 610 radeonfb_init_palette(sc, 1); 611 612 /* program the DAC wirings */ 613 for (i = 0; i < (HAS_CRTC2(sc) ? 2 : 1); i++) { 614 switch (sc->sc_ports[i].rp_dac_type) { 615 case RADEON_DAC_PRIMARY: 616 PATCH32(sc, RADEON_DAC_CNTL2, 617 i ? RADEON_DAC2_DAC_CLK_SEL : 0, 618 ~RADEON_DAC2_DAC_CLK_SEL); 619 break; 620 case RADEON_DAC_TVDAC: 621 /* we always use the TVDAC to drive a secondary analog 622 * CRT for now. if we ever support TV-out this will 623 * have to change. 624 */ 625 SET32(sc, RADEON_DAC_CNTL2, 626 RADEON_DAC2_DAC2_CLK_SEL); 627 PATCH32(sc, RADEON_DISP_HW_DEBUG, 628 i ? 0 : RADEON_CRT2_DISP1_SEL, 629 ~RADEON_CRT2_DISP1_SEL); 630 break; 631 } 632 } 633 PRINTREG(RADEON_DAC_CNTL2); 634 PRINTREG(RADEON_DISP_HW_DEBUG); 635 636 /* other DAC programming */ 637 v = GET32(sc, RADEON_DAC_CNTL); 638 v &= (RADEON_DAC_RANGE_CNTL_MASK | RADEON_DAC_BLANKING); 639 v |= RADEON_DAC_MASK_ALL | RADEON_DAC_8BIT_EN; 640 PUT32(sc, RADEON_DAC_CNTL, v); 641 PRINTREG(RADEON_DAC_CNTL); 642 643 /* XXX: this may need more investigation */ 644 PUT32(sc, RADEON_TV_DAC_CNTL, 0x00280203); 645 PRINTREG(RADEON_TV_DAC_CNTL); 646 647 /* enable TMDS */ 648 SET32(sc, RADEON_FP_GEN_CNTL, 649 RADEON_FP_TMDS_EN | 650 RADEON_FP_CRTC_DONT_SHADOW_VPAR | 651 RADEON_FP_CRTC_DONT_SHADOW_HEND); 652 CLR32(sc, RADEON_FP_GEN_CNTL, RADEON_FP_SEL_CRTC2); 653 if (HAS_CRTC2(sc)) 654 SET32(sc, RADEON_FP2_GEN_CNTL, RADEON_FP2_SRC_SEL_CRTC2); 655 656 /* 657 * we use bus_space_map instead of pci_mapreg, because we don't 658 * need the full aperature space. no point in wasting virtual 659 * address space we don't intend to use, right? 660 */ 661 if ((sc->sc_memsz < (4096 * 1024)) || 662 (pci_mapreg_info(sc->sc_pc, sc->sc_pt, RADEON_MAPREG_VRAM, 663 PCI_MAPREG_TYPE_MEM, &sc->sc_memaddr, &bsz, NULL) != 0) || 664 (bsz < sc->sc_memsz)) { 665 sc->sc_memsz = 0; 666 aprint_error("%s: Bad frame buffer configuration\n", 667 XNAME(sc)); 668 goto error; 669 } 670 671 /* 64 MB should be enough -- more just wastes map entries */ 672 if (sc->sc_memsz > (64 << 20)) 673 sc->sc_memsz = (64 << 20); 674 675 sc->sc_memt = pa->pa_memt; 676 if (bus_space_map(sc->sc_memt, sc->sc_memaddr, sc->sc_memsz, 677 BUS_SPACE_MAP_LINEAR, &sc->sc_memh) != 0) { 678 sc->sc_memsz = 0; 679 aprint_error("%s: Unable to map frame buffer\n", XNAME(sc)); 680 goto error; 681 } 682 683 aprint_normal("%s: %d MB aperture at 0x%08x, " 684 "%d KB registers at 0x%08x\n", XNAME(sc), 685 (int)sc->sc_memsz >> 20, (unsigned)sc->sc_memaddr, 686 (int)sc->sc_regsz >> 10, (unsigned)sc->sc_regaddr); 687 688 /* setup default video mode from devprop (allows PROM override) */ 689 sc->sc_defaultmode = radeonfb_default_mode; 690 if (prop_dictionary_get_cstring_nocopy(device_properties(&sc->sc_dev), 691 "videomode", &mptr)) { 692 693 strncpy(sc->sc_modebuf, mptr, sizeof(sc->sc_modebuf)); 694 sc->sc_defaultmode = sc->sc_modebuf; 695 } 696 697 /* initialize some basic display parameters */ 698 for (i = 0; i < sc->sc_ndisplays; i++) { 699 struct radeonfb_display *dp = &sc->sc_displays[i]; 700 struct rasops_info *ri; 701 long defattr; 702 struct wsemuldisplaydev_attach_args aa; 703 704 /* 705 * Figure out how many "displays" (desktops) we are going to 706 * support. If more than one, then each CRTC gets its own 707 * programming. 708 * 709 * XXX: this code needs to change to support mergedfb. 710 * XXX: would be nice to allow this to be overridden 711 */ 712 if (HAS_CRTC2(sc) && (sc->sc_ndisplays == 1)) { 713 DPRINTF(("dual crtcs!\n")); 714 dp->rd_ncrtcs = 2; 715 dp->rd_crtcs[0].rc_number = 0; 716 dp->rd_crtcs[1].rc_number = 1; 717 } else { 718 dp->rd_ncrtcs = 1; 719 dp->rd_crtcs[0].rc_number = i; 720 } 721 722 /* set up port pointer */ 723 for (j = 0; j < dp->rd_ncrtcs; j++) { 724 dp->rd_crtcs[j].rc_port = 725 &sc->sc_ports[dp->rd_crtcs[j].rc_number]; 726 } 727 728 dp->rd_softc = sc; 729 dp->rd_wsmode = WSDISPLAYIO_MODE_EMUL; 730 dp->rd_bg = WS_DEFAULT_BG; 731 #if 0 732 dp->rd_bpp = sc->sc_maxbpp; /* XXX: for now */ 733 #else 734 dp->rd_bpp = RADEONFB_DEFAULT_DEPTH; /* XXX */ 735 #endif 736 /* for text mode, we pick a resolution that won't 737 * require panning */ 738 radeonfb_pickres(dp, &dp->rd_virtx, &dp->rd_virty, 0); 739 740 aprint_normal("%s: display %d: " 741 "initial virtual resolution %dx%d at %d bpp\n", 742 XNAME(sc), i, dp->rd_virtx, dp->rd_virty, dp->rd_bpp); 743 744 /* now select the *video mode* that we will use */ 745 for (j = 0; j < dp->rd_ncrtcs; j++) { 746 const struct videomode *vmp; 747 vmp = radeonfb_port_mode(sc, dp->rd_crtcs[j].rc_port, 748 dp->rd_virtx, dp->rd_virty); 749 750 /* 751 * virtual resolution should be at least as high as 752 * physical 753 */ 754 if (dp->rd_virtx < vmp->hdisplay || 755 dp->rd_virty < vmp->vdisplay) { 756 dp->rd_virtx = vmp->hdisplay; 757 dp->rd_virty = vmp->vdisplay; 758 } 759 760 dp->rd_crtcs[j].rc_videomode = *vmp; 761 printf("%s: port %d: physical %dx%d %dHz\n", 762 XNAME(sc), j, vmp->hdisplay, vmp->vdisplay, 763 DIVIDE(DIVIDE(vmp->dot_clock * 1000, 764 vmp->htotal), vmp->vtotal)); 765 } 766 767 /* N.B.: radeon wants 64-byte aligned stride */ 768 dp->rd_stride = dp->rd_virtx * dp->rd_bpp / 8; 769 dp->rd_stride = ROUNDUP(dp->rd_stride, RADEON_STRIDEALIGN); 770 771 dp->rd_offset = sc->sc_fboffset * i; 772 dp->rd_fbptr = (vaddr_t)bus_space_vaddr(sc->sc_memt, 773 sc->sc_memh) + dp->rd_offset; 774 dp->rd_curoff = sc->sc_fbsize; 775 dp->rd_curptr = dp->rd_fbptr + dp->rd_curoff; 776 777 DPRINTF(("fpbtr = %p\n", (void *)dp->rd_fbptr)); 778 779 switch (dp->rd_bpp) { 780 case 8: 781 dp->rd_format = 2; 782 break; 783 case 32: 784 dp->rd_format = 6; 785 break; 786 default: 787 aprint_error("%s: bad depth %d\n", XNAME(sc), 788 dp->rd_bpp); 789 goto error; 790 } 791 792 printf("init engine\n"); 793 /* XXX: this seems suspicious - per display engine 794 initialization? */ 795 radeonfb_engine_init(dp); 796 797 /* copy the template into place */ 798 dp->rd_wsscreens_storage[0] = radeonfb_stdscreen; 799 dp->rd_wsscreens = dp->rd_wsscreens_storage; 800 801 /* and make up the list */ 802 dp->rd_wsscreenlist.nscreens = 1; 803 dp->rd_wsscreenlist.screens = 804 (const struct wsscreen_descr **)&dp->rd_wsscreens; 805 806 vcons_init(&dp->rd_vd, dp, dp->rd_wsscreens, 807 &radeonfb_accessops); 808 809 dp->rd_vd.init_screen = radeonfb_init_screen; 810 811 dp->rd_console = 1; 812 813 dp->rd_vscreen.scr_flags |= VCONS_SCREEN_IS_STATIC; 814 815 816 vcons_init_screen(&dp->rd_vd, &dp->rd_vscreen, 817 dp->rd_console, &defattr); 818 819 ri = &dp->rd_vscreen.scr_ri; 820 821 /* clear the screen */ 822 rasops_unpack_attr(defattr, &fg, &bg, &ul); 823 radeonfb_rectfill(dp, 0, 0, ri->ri_width, ri->ri_height, 824 ri->ri_devcmap[bg & 0xf]); 825 826 dp->rd_wsscreens->textops = &ri->ri_ops; 827 dp->rd_wsscreens->capabilities = ri->ri_caps; 828 dp->rd_wsscreens->nrows = ri->ri_rows; 829 dp->rd_wsscreens->ncols = ri->ri_cols; 830 831 #ifdef SPLASHSCREEN 832 dp->rd_splash.si_depth = ri->ri_depth; 833 dp->rd_splash.si_bits = ri->ri_bits; 834 dp->rd_splash.si_hwbits = ri->ri_hwbits; 835 dp->rd_splash.si_width = ri->ri_width; 836 dp->rd_splash.si_height = ri->ri_height; 837 dp->rd_splash.si_stride = ri->ri_stride; 838 dp->rd_splash.si_fillrect = NULL; 839 #endif 840 if (dp->rd_console) { 841 842 wsdisplay_cnattach(dp->rd_wsscreens, ri, 0, 0, 843 defattr); 844 #ifdef SPLASHSCREEN 845 splash_render(&dp->rd_splash, 846 SPLASH_F_CENTER|SPLASH_F_FILL); 847 #endif 848 849 #ifdef SPLASHSCREEN_PROGRESS 850 dp->rd_progress.sp_top = (dp->rd_virty / 8) * 7; 851 dp->rd_progress.sp_width = (dp->rd_virtx / 4) * 3; 852 dp->rd_progress.sp_left = (dp->rd_virtx - 853 dp->rd_progress.sp_width) / 2; 854 dp->rd_progress.sp_height = 20; 855 dp->rd_progress.sp_state = -1; 856 dp->rd_progress.sp_si = &dp->rd_splash; 857 splash_progress_init(&dp->rd_progress); 858 SCREEN_DISABLE_DRAWING(&dp->rd_vscreen); 859 #endif 860 861 } else { 862 863 /* 864 * since we're not the console we can postpone 865 * the rest until someone actually allocates a 866 * screen for us. but we do clear the screen 867 * at least. 868 */ 869 memset(ri->ri_bits, 0, 1024); 870 871 radeonfb_modeswitch(dp); 872 #ifdef SPLASHSCREEN 873 splash_render(&dp->rd_splash, 874 SPLASH_F_CENTER|SPLASH_F_FILL); 875 SCREEN_DISABLE_DRAWING(&dp->rd_vscreen); 876 #endif 877 } 878 879 aa.console = dp->rd_console; 880 aa.scrdata = &dp->rd_wsscreenlist; 881 aa.accessops = &radeonfb_accessops; 882 aa.accesscookie = &dp->rd_vd; 883 884 config_found(&sc->sc_dev, &aa, wsemuldisplaydevprint); 885 radeonfb_blank(dp, 0); 886 887 /* Initialise delayed lvds operations for backlight. */ 888 callout_init(&dp->rd_bl_lvds_co, 0); 889 callout_setfunc(&dp->rd_bl_lvds_co, 890 radeonfb_lvds_callout, dp); 891 } 892 893 config_found_ia(dev, "drm", aux, radeonfb_drm_print); 894 895 return; 896 897 error: 898 if (sc->sc_biossz) 899 free(sc->sc_bios, M_DEVBUF); 900 901 if (sc->sc_regsz) 902 bus_space_unmap(sc->sc_regt, sc->sc_regh, sc->sc_regsz); 903 904 if (sc->sc_memsz) 905 bus_space_unmap(sc->sc_memt, sc->sc_memh, sc->sc_memsz); 906 } 907 908 static int 909 radeonfb_drm_print(void *aux, const char *pnp) 910 { 911 if (pnp) 912 aprint_normal("direct rendering for %s", pnp); 913 return (UNSUPP); 914 } 915 916 int 917 radeonfb_ioctl(void *v, void *vs, 918 unsigned long cmd, void *d, int flag, struct lwp *l) 919 { 920 struct vcons_data *vd; 921 struct radeonfb_display *dp; 922 struct radeonfb_softc *sc; 923 struct wsdisplay_param *param; 924 925 vd = (struct vcons_data *)v; 926 dp = (struct radeonfb_display *)vd->cookie; 927 sc = dp->rd_softc; 928 929 switch (cmd) { 930 case WSDISPLAYIO_GTYPE: 931 *(unsigned *)d = WSDISPLAY_TYPE_PCIMISC; 932 return 0; 933 934 case WSDISPLAYIO_GINFO: 935 if (vd->active != NULL) { 936 struct wsdisplay_fbinfo *fb; 937 fb = (struct wsdisplay_fbinfo *)d; 938 fb->width = dp->rd_virtx; 939 fb->height = dp->rd_virty; 940 fb->depth = dp->rd_bpp; 941 fb->cmsize = 256; 942 return 0; 943 } else 944 return ENODEV; 945 case WSDISPLAYIO_GVIDEO: 946 if (radeonfb_isblank(dp)) 947 *(unsigned *)d = WSDISPLAYIO_VIDEO_OFF; 948 else 949 *(unsigned *)d = WSDISPLAYIO_VIDEO_ON; 950 return 0; 951 952 case WSDISPLAYIO_SVIDEO: 953 radeonfb_blank(dp, 954 (*(unsigned int *)d == WSDISPLAYIO_VIDEO_OFF)); 955 return 0; 956 957 case WSDISPLAYIO_GETCMAP: 958 #if 0 959 if (dp->rd_bpp == 8) 960 return radeonfb_getcmap(sc, 961 (struct wsdisplay_cmap *)d); 962 #endif 963 return EINVAL; 964 965 case WSDISPLAYIO_PUTCMAP: 966 #if 0 967 if (dp->rd_bpp == 8) 968 return radeonfb_putcmap(sc, 969 (struct wsdisplay_cmap *)d); 970 #endif 971 return EINVAL; 972 973 case WSDISPLAYIO_LINEBYTES: 974 *(unsigned *)d = dp->rd_stride; 975 return 0; 976 977 case WSDISPLAYIO_SMODE: 978 if (*(int *)d != dp->rd_wsmode) { 979 dp->rd_wsmode = *(int *)d; 980 if ((dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) && 981 (dp->rd_vd.active)) { 982 radeonfb_engine_init(dp); 983 radeonfb_modeswitch(dp); 984 vcons_redraw_screen(dp->rd_vd.active); 985 } 986 } 987 return 0; 988 989 case WSDISPLAYIO_GCURMAX: 990 ((struct wsdisplay_curpos *)d)->x = RADEON_CURSORMAXX; 991 ((struct wsdisplay_curpos *)d)->y = RADEON_CURSORMAXY; 992 return 0; 993 994 case WSDISPLAYIO_SCURSOR: 995 return radeonfb_set_cursor(dp, (struct wsdisplay_cursor *)d); 996 997 case WSDISPLAYIO_GCURSOR: 998 return EPASSTHROUGH; 999 1000 case WSDISPLAYIO_GCURPOS: 1001 ((struct wsdisplay_curpos *)d)->x = dp->rd_cursor.rc_pos.x; 1002 ((struct wsdisplay_curpos *)d)->y = dp->rd_cursor.rc_pos.y; 1003 return 0; 1004 1005 case WSDISPLAYIO_SCURPOS: 1006 return radeonfb_set_curpos(dp, (struct wsdisplay_curpos *)d); 1007 1008 case WSDISPLAYIO_SSPLASH: 1009 #if defined(SPLASHSCREEN) 1010 if (*(int *)d == 1) { 1011 SCREEN_DISABLE_DRAWING(&dp->rd_vscreen); 1012 splash_render(&dp->rd_splash, 1013 SPLASH_F_CENTER|SPLASH_F_FILL); 1014 } else 1015 SCREEN_ENABLE_DRAWING(&dp->rd_vscreen); 1016 return 0; 1017 #else 1018 return ENODEV; 1019 #endif 1020 case WSDISPLAYIO_SPROGRESS: 1021 #if defined(SPLASHSCREEN) && defined(SPLASHSCREEN_PROGRESS) 1022 dp->rd_progress.sp_force = 1; 1023 splash_progress_update(&dp->rd_progress); 1024 dp->rd_progress.sp_force = 0; 1025 return 0; 1026 #else 1027 return ENODEV; 1028 #endif 1029 case WSDISPLAYIO_GETPARAM: 1030 param = (struct wsdisplay_param *)d; 1031 if (param->param == WSDISPLAYIO_PARAM_BACKLIGHT) { 1032 param->min = 0; 1033 param->max = RADEONFB_BACKLIGHT_MAX; 1034 param->curval = radeonfb_get_backlight(dp); 1035 return 0; 1036 } 1037 return EPASSTHROUGH; 1038 1039 case WSDISPLAYIO_SETPARAM: 1040 param = (struct wsdisplay_param *)d; 1041 if (param->param == WSDISPLAYIO_PARAM_BACKLIGHT) { 1042 return radeonfb_set_backlight(dp, param->curval); 1043 } 1044 return EPASSTHROUGH; 1045 1046 default: 1047 return EPASSTHROUGH; 1048 } 1049 } 1050 1051 paddr_t 1052 radeonfb_mmap(void *v, void *vs, off_t offset, int prot) 1053 { 1054 struct vcons_data *vd; 1055 struct radeonfb_display *dp; 1056 struct radeonfb_softc *sc; 1057 #ifdef RADEONFB_MMAP_BARS 1058 struct lwp *me; 1059 #endif 1060 paddr_t pa; 1061 1062 vd = (struct vcons_data *)v; 1063 dp = (struct radeonfb_display *)vd->cookie; 1064 sc = dp->rd_softc; 1065 1066 /* XXX: note that we don't allow mapping of registers right now */ 1067 /* XXX: this means that the XFree86 radeon driver won't work */ 1068 1069 if ((offset >= 0) && (offset < (dp->rd_virty * dp->rd_stride))) { 1070 pa = bus_space_mmap(sc->sc_memt, 1071 sc->sc_memaddr + dp->rd_offset + offset, 0, 1072 prot, BUS_SPACE_MAP_LINEAR); 1073 return pa; 1074 } 1075 1076 #ifdef RADEONFB_MMAP_BARS 1077 /* 1078 * restrict all other mappings to processes with superuser privileges 1079 * or the kernel itself 1080 */ 1081 me = curlwp; 1082 if (me != NULL) { 1083 if (kauth_authorize_generic(me->l_cred, KAUTH_GENERIC_ISSUSER, 1084 NULL) != 0) { 1085 printf("%s: mmap() rejected.\n", sc->sc_dev.dv_xname); 1086 return -1; 1087 } 1088 } 1089 1090 if ((offset >= sc->sc_regaddr) && 1091 (offset < sc->sc_regaddr + sc->sc_regsz)) { 1092 return bus_space_mmap(sc->sc_regt, offset, 0, prot, 1093 BUS_SPACE_MAP_LINEAR); 1094 } 1095 1096 if ((offset >= sc->sc_memaddr) && 1097 (offset < sc->sc_memaddr + sc->sc_memsz)) { 1098 return bus_space_mmap(sc->sc_memt, offset, 0, prot, 1099 BUS_SPACE_MAP_LINEAR); 1100 } 1101 1102 #ifdef macppc 1103 /* allow mapping of IO space */ 1104 if ((offset >= 0xf2000000) && (offset < 0xf2800000)) { 1105 pa = bus_space_mmap(sc->sc_iot, offset - 0xf2000000, 0, prot, 1106 0); 1107 return pa; 1108 } 1109 #endif /* macppc */ 1110 1111 #endif /* RADEONFB_MMAP_BARS */ 1112 1113 return -1; 1114 } 1115 1116 static void 1117 radeonfb_loadbios(struct radeonfb_softc *sc, struct pci_attach_args *pa) 1118 { 1119 bus_space_tag_t romt; 1120 bus_space_handle_t romh, biosh; 1121 bus_size_t romsz; 1122 bus_addr_t ptr; 1123 1124 if (pci_mapreg_map(pa, PCI_MAPREG_ROM, PCI_MAPREG_TYPE_ROM, 1125 BUS_SPACE_MAP_PREFETCHABLE, &romt, &romh, NULL, &romsz) != 0) { 1126 aprint_verbose("%s: unable to map BIOS!\n", XNAME(sc)); 1127 return; 1128 } 1129 1130 pci_find_rom(pa, romt, romh, PCI_ROM_CODE_TYPE_X86, &biosh, 1131 &sc->sc_biossz); 1132 if (sc->sc_biossz == 0) { 1133 aprint_verbose("%s: Video BIOS not present\n", XNAME(sc)); 1134 return; 1135 } 1136 1137 sc->sc_bios = malloc(sc->sc_biossz, M_DEVBUF, M_WAITOK); 1138 bus_space_read_region_1(romt, biosh, 0, sc->sc_bios, sc->sc_biossz); 1139 1140 /* unmap the PCI expansion rom */ 1141 bus_space_unmap(romt, romh, romsz); 1142 1143 /* turn off rom decoder now */ 1144 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM, 1145 pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM) & 1146 ~PCI_MAPREG_ROM_ENABLE); 1147 1148 ptr = GETBIOS16(sc, 0x48); 1149 if ((GETBIOS32(sc, ptr + 4) == 0x41544f4d /* "ATOM" */) || 1150 (GETBIOS32(sc, ptr + 4) == 0x4d4f5441 /* "MOTA" */)) { 1151 sc->sc_flags |= RFB_ATOM; 1152 } 1153 1154 aprint_verbose("%s: Found %d KB %s BIOS\n", XNAME(sc), 1155 (unsigned)sc->sc_biossz >> 10, IS_ATOM(sc) ? "ATOM" : "Legacy"); 1156 } 1157 1158 1159 uint32_t 1160 radeonfb_get32(struct radeonfb_softc *sc, uint32_t reg) 1161 { 1162 1163 return bus_space_read_4(sc->sc_regt, sc->sc_regh, reg); 1164 } 1165 1166 void 1167 radeonfb_put32(struct radeonfb_softc *sc, uint32_t reg, uint32_t val) 1168 { 1169 1170 bus_space_write_4(sc->sc_regt, sc->sc_regh, reg, val); 1171 } 1172 1173 void 1174 radeonfb_mask32(struct radeonfb_softc *sc, uint32_t reg, 1175 uint32_t andmask, uint32_t ormask) 1176 { 1177 int s; 1178 uint32_t val; 1179 1180 s = splhigh(); 1181 val = radeonfb_get32(sc, reg); 1182 val = (val & andmask) | ormask; 1183 radeonfb_put32(sc, reg, val); 1184 splx(s); 1185 } 1186 1187 uint32_t 1188 radeonfb_getindex(struct radeonfb_softc *sc, uint32_t idx) 1189 { 1190 int s; 1191 uint32_t val; 1192 1193 s = splhigh(); 1194 radeonfb_put32(sc, RADEON_MM_INDEX, idx); 1195 val = radeonfb_get32(sc, RADEON_MM_DATA); 1196 splx(s); 1197 1198 return (val); 1199 } 1200 1201 void 1202 radeonfb_putindex(struct radeonfb_softc *sc, uint32_t idx, uint32_t val) 1203 { 1204 int s; 1205 1206 s = splhigh(); 1207 radeonfb_put32(sc, RADEON_MM_INDEX, idx); 1208 radeonfb_put32(sc, RADEON_MM_DATA, val); 1209 splx(s); 1210 } 1211 1212 void 1213 radeonfb_maskindex(struct radeonfb_softc *sc, uint32_t idx, 1214 uint32_t andmask, uint32_t ormask) 1215 { 1216 int s; 1217 uint32_t val; 1218 1219 s = splhigh(); 1220 radeonfb_put32(sc, RADEON_MM_INDEX, idx); 1221 val = radeonfb_get32(sc, RADEON_MM_DATA); 1222 val = (val & andmask) | ormask; 1223 radeonfb_put32(sc, RADEON_MM_DATA, val); 1224 splx(s); 1225 } 1226 1227 uint32_t 1228 radeonfb_getpll(struct radeonfb_softc *sc, uint32_t idx) 1229 { 1230 int s; 1231 uint32_t val; 1232 1233 s = splhigh(); 1234 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, idx & 0x3f); 1235 val = radeonfb_get32(sc, RADEON_CLOCK_CNTL_DATA); 1236 if (HAS_R300CG(sc)) 1237 radeonfb_r300cg_workaround(sc); 1238 splx(s); 1239 1240 return (val); 1241 } 1242 1243 void 1244 radeonfb_putpll(struct radeonfb_softc *sc, uint32_t idx, uint32_t val) 1245 { 1246 int s; 1247 1248 s = splhigh(); 1249 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, (idx & 0x3f) | 1250 RADEON_PLL_WR_EN); 1251 radeonfb_put32(sc, RADEON_CLOCK_CNTL_DATA, val); 1252 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, 0); 1253 splx(s); 1254 } 1255 1256 void 1257 radeonfb_maskpll(struct radeonfb_softc *sc, uint32_t idx, 1258 uint32_t andmask, uint32_t ormask) 1259 { 1260 int s; 1261 uint32_t val; 1262 1263 s = splhigh(); 1264 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, (idx & 0x3f) | 1265 RADEON_PLL_WR_EN); 1266 val = radeonfb_get32(sc, RADEON_CLOCK_CNTL_DATA); 1267 val = (val & andmask) | ormask; 1268 radeonfb_put32(sc, RADEON_CLOCK_CNTL_DATA, val); 1269 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, 0); 1270 splx(s); 1271 } 1272 1273 int 1274 radeonfb_scratch_test(struct radeonfb_softc *sc, int reg, uint32_t v) 1275 { 1276 uint32_t saved; 1277 1278 saved = GET32(sc, reg); 1279 PUT32(sc, reg, v); 1280 if (GET32(sc, reg) != v) { 1281 return -1; 1282 } 1283 PUT32(sc, reg, saved); 1284 return 0; 1285 } 1286 1287 uintmax_t 1288 radeonfb_getprop_num(struct radeonfb_softc *sc, const char *name, 1289 uintmax_t defval) 1290 { 1291 prop_number_t pn; 1292 pn = prop_dictionary_get(device_properties(&sc->sc_dev), name); 1293 if (pn == NULL) { 1294 return defval; 1295 } 1296 KASSERT(prop_object_type(pn) == PROP_TYPE_NUMBER); 1297 return (prop_number_integer_value(pn)); 1298 } 1299 1300 int 1301 radeonfb_getclocks(struct radeonfb_softc *sc) 1302 { 1303 bus_addr_t ptr; 1304 int refclk = 0; 1305 int refdiv = 0; 1306 int minpll = 0; 1307 int maxpll = 0; 1308 1309 /* load initial property values if port/board provides them */ 1310 refclk = radeonfb_getprop_num(sc, "refclk", 0) & 0xffff; 1311 refdiv = radeonfb_getprop_num(sc, "refdiv", 0) & 0xffff; 1312 minpll = radeonfb_getprop_num(sc, "minpll", 0) & 0xffffffffU; 1313 maxpll = radeonfb_getprop_num(sc, "maxpll", 0) & 0xffffffffU; 1314 1315 if (refclk && refdiv && minpll && maxpll) 1316 goto dontprobe; 1317 1318 if (!sc->sc_biossz) { 1319 /* no BIOS */ 1320 aprint_verbose("%s: No video BIOS, using default clocks\n", 1321 XNAME(sc)); 1322 if (IS_IGP(sc)) 1323 refclk = refclk ? refclk : 1432; 1324 else 1325 refclk = refclk ? refclk : 2700; 1326 if (refdiv < 2) 1327 refdiv = GETPLL(sc, RADEON_PPLL_REF_DIV) & 1328 RADEON_PPLL_REF_DIV_MASK; 1329 if (refdiv < 2) 1330 refdiv = 12; 1331 minpll = minpll ? minpll : 12500; 1332 maxpll = maxpll ? maxpll : 35000; 1333 } else if (IS_ATOM(sc)) { 1334 /* ATOM BIOS */ 1335 ptr = GETBIOS16(sc, 0x48); 1336 ptr = GETBIOS16(sc, ptr + 32); /* aka MasterDataStart */ 1337 ptr = GETBIOS16(sc, ptr + 12); /* pll info block */ 1338 refclk = refclk ? refclk : GETBIOS16(sc, ptr + 82); 1339 minpll = minpll ? minpll : GETBIOS16(sc, ptr + 78); 1340 maxpll = maxpll ? maxpll : GETBIOS16(sc, ptr + 32); 1341 /* 1342 * ATOM BIOS doesn't supply a reference divider, so we 1343 * have to probe for it. 1344 */ 1345 if (refdiv < 2) 1346 refdiv = GETPLL(sc, RADEON_PPLL_REF_DIV) & 1347 RADEON_PPLL_REF_DIV_MASK; 1348 /* 1349 * if probe is zero, just assume one that should work 1350 * for most parts 1351 */ 1352 if (refdiv < 2) 1353 refdiv = 12; 1354 1355 } else { 1356 /* Legacy BIOS */ 1357 ptr = GETBIOS16(sc, 0x48); 1358 ptr = GETBIOS16(sc, ptr + 0x30); 1359 refclk = refclk ? refclk : GETBIOS16(sc, ptr + 0x0E); 1360 refdiv = refdiv ? refdiv : GETBIOS16(sc, ptr + 0x10); 1361 minpll = minpll ? minpll : GETBIOS32(sc, ptr + 0x12); 1362 maxpll = maxpll ? maxpll : GETBIOS32(sc, ptr + 0x16); 1363 } 1364 1365 1366 dontprobe: 1367 sc->sc_refclk = refclk * 10; 1368 sc->sc_refdiv = refdiv; 1369 sc->sc_minpll = minpll * 10; 1370 sc->sc_maxpll = maxpll * 10; 1371 return 0; 1372 } 1373 1374 int 1375 radeonfb_calc_dividers(struct radeonfb_softc *sc, uint32_t dotclock, 1376 uint32_t *postdivbit, uint32_t *feedbackdiv) 1377 { 1378 int i; 1379 uint32_t outfreq; 1380 int div; 1381 1382 DPRINTF(("dot clock: %u\n", dotclock)); 1383 for (i = 0; (div = radeonfb_dividers[i].divider) != 0; i++) { 1384 outfreq = div * dotclock; 1385 if ((outfreq >= sc->sc_minpll) && 1386 (outfreq <= sc->sc_maxpll)) { 1387 DPRINTF(("outfreq: %u\n", outfreq)); 1388 *postdivbit = 1389 ((uint32_t)radeonfb_dividers[i].mask << 16); 1390 DPRINTF(("post divider: %d (mask %x)\n", div, 1391 *postdivbit)); 1392 break; 1393 } 1394 } 1395 1396 if (div == 0) 1397 return 1; 1398 1399 *feedbackdiv = DIVIDE(sc->sc_refdiv * outfreq, sc->sc_refclk); 1400 DPRINTF(("feedback divider: %d\n", *feedbackdiv)); 1401 return 0; 1402 } 1403 1404 #if 0 1405 #ifdef RADEON_DEBUG 1406 static void 1407 dump_buffer(const char *pfx, void *buffer, unsigned int size) 1408 { 1409 char asc[17]; 1410 unsigned ptr = (unsigned)buffer; 1411 char *start = (char *)(ptr & ~0xf); 1412 char *end = (char *)(ptr + size); 1413 1414 end = (char *)(((unsigned)end + 0xf) & ~0xf); 1415 1416 if (pfx == NULL) { 1417 pfx = ""; 1418 } 1419 1420 while (start < end) { 1421 unsigned offset = (unsigned)start & 0xf; 1422 if (offset == 0) { 1423 printf("%s%x: ", pfx, (unsigned)start); 1424 } 1425 if (((unsigned)start < ptr) || 1426 ((unsigned)start >= (ptr + size))) { 1427 printf(" "); 1428 asc[offset] = ' '; 1429 } else { 1430 printf("%02x", *(unsigned char *)start); 1431 if ((*start >= ' ') && (*start <= '~')) { 1432 asc[offset] = *start; 1433 } else { 1434 asc[offset] = '.'; 1435 } 1436 } 1437 asc[offset + 1] = 0; 1438 if (offset % 2) { 1439 printf(" "); 1440 } 1441 if (offset == 15) { 1442 printf(" %s\n", asc); 1443 } 1444 start++; 1445 } 1446 } 1447 #endif 1448 #endif 1449 1450 int 1451 radeonfb_getconnectors(struct radeonfb_softc *sc) 1452 { 1453 int i; 1454 int found = 0; 1455 1456 for (i = 0; i < 2; i++) { 1457 sc->sc_ports[i].rp_mon_type = RADEON_MT_UNKNOWN; 1458 sc->sc_ports[i].rp_ddc_type = RADEON_DDC_NONE; 1459 sc->sc_ports[i].rp_dac_type = RADEON_DAC_UNKNOWN; 1460 sc->sc_ports[i].rp_conn_type = RADEON_CONN_NONE; 1461 sc->sc_ports[i].rp_tmds_type = RADEON_TMDS_UNKNOWN; 1462 } 1463 1464 /* 1465 * This logic is borrowed from Xorg's radeon driver. 1466 */ 1467 if (!sc->sc_biossz) 1468 goto nobios; 1469 1470 if (IS_ATOM(sc)) { 1471 /* not done yet */ 1472 } else { 1473 uint16_t ptr; 1474 int port = 0; 1475 1476 ptr = GETBIOS16(sc, 0x48); 1477 ptr = GETBIOS16(sc, ptr + 0x50); 1478 for (i = 1; i < 4; i++) { 1479 uint16_t entry; 1480 uint8_t conn, ddc, dac, tmds; 1481 1482 /* 1483 * Parse the connector table. From reading the code, 1484 * it appears to made up of 16-bit entries for each 1485 * connector. The 16-bits are defined as: 1486 * 1487 * bits 12-15 - connector type (0 == end of table) 1488 * bits 8-11 - DDC type 1489 * bits 5-7 - ??? 1490 * bit 4 - TMDS type (1 = EXT, 0 = INT) 1491 * bits 1-3 - ??? 1492 * bit 0 - DAC, 1 = TVDAC, 0 = primary 1493 */ 1494 if (!GETBIOS8(sc, ptr + i * 2) && i > 1) 1495 break; 1496 entry = GETBIOS16(sc, ptr + i * 2); 1497 1498 conn = (entry >> 12) & 0xf; 1499 ddc = (entry >> 8) & 0xf; 1500 dac = (entry & 0x1) ? RADEON_DAC_TVDAC : 1501 RADEON_DAC_PRIMARY; 1502 tmds = ((entry >> 4) & 0x1) ? RADEON_TMDS_EXT : 1503 RADEON_TMDS_INT; 1504 1505 if (conn == RADEON_CONN_NONE) 1506 continue; /* no connector */ 1507 1508 if ((found > 0) && 1509 (sc->sc_ports[port].rp_ddc_type == ddc)) { 1510 /* duplicate entry for same connector */ 1511 continue; 1512 } 1513 1514 /* internal DDC_DVI port gets priority */ 1515 if ((ddc == RADEON_DDC_DVI) || (port == 1)) 1516 port = 0; 1517 else 1518 port = 1; 1519 1520 sc->sc_ports[port].rp_ddc_type = 1521 ddc > RADEON_DDC_CRT2 ? RADEON_DDC_NONE : ddc; 1522 sc->sc_ports[port].rp_dac_type = dac; 1523 sc->sc_ports[port].rp_conn_type = 1524 min(conn, RADEON_CONN_UNSUPPORTED) ; 1525 1526 sc->sc_ports[port].rp_tmds_type = tmds; 1527 1528 if ((conn != RADEON_CONN_DVI_I) && 1529 (conn != RADEON_CONN_DVI_D) && 1530 (tmds == RADEON_TMDS_INT)) 1531 sc->sc_ports[port].rp_tmds_type = 1532 RADEON_TMDS_UNKNOWN; 1533 1534 found += (port + 1); 1535 } 1536 } 1537 1538 nobios: 1539 if (!found) { 1540 DPRINTF(("No connector info in BIOS!\n")); 1541 /* default, port 0 = internal TMDS, port 1 = CRT */ 1542 sc->sc_ports[0].rp_mon_type = RADEON_MT_UNKNOWN; 1543 sc->sc_ports[0].rp_ddc_type = RADEON_DDC_DVI; 1544 sc->sc_ports[0].rp_dac_type = RADEON_DAC_TVDAC; 1545 sc->sc_ports[0].rp_conn_type = RADEON_CONN_DVI_D; 1546 sc->sc_ports[0].rp_tmds_type = RADEON_TMDS_INT; 1547 1548 sc->sc_ports[1].rp_mon_type = RADEON_MT_UNKNOWN; 1549 sc->sc_ports[1].rp_ddc_type = RADEON_DDC_VGA; 1550 sc->sc_ports[1].rp_dac_type = RADEON_DAC_PRIMARY; 1551 sc->sc_ports[1].rp_conn_type = RADEON_CONN_CRT; 1552 sc->sc_ports[1].rp_tmds_type = RADEON_TMDS_EXT; 1553 } 1554 1555 /* 1556 * Fixup for RS300/RS350/RS400 chips, that lack a primary DAC. 1557 * these chips should use TVDAC for the VGA port. 1558 */ 1559 if (HAS_SDAC(sc)) { 1560 if (sc->sc_ports[0].rp_conn_type == RADEON_CONN_CRT) { 1561 sc->sc_ports[0].rp_dac_type = RADEON_DAC_TVDAC; 1562 sc->sc_ports[1].rp_dac_type = RADEON_DAC_PRIMARY; 1563 } else { 1564 sc->sc_ports[1].rp_dac_type = RADEON_DAC_TVDAC; 1565 sc->sc_ports[0].rp_dac_type = RADEON_DAC_PRIMARY; 1566 } 1567 } else if (!HAS_CRTC2(sc)) { 1568 sc->sc_ports[0].rp_dac_type = RADEON_DAC_PRIMARY; 1569 } 1570 1571 for (i = 0; i < 2; i++) { 1572 char edid[128]; 1573 uint8_t ddc; 1574 struct edid_info *eip = &sc->sc_ports[i].rp_edid; 1575 prop_data_t edid_data; 1576 1577 DPRINTF(("Port #%d:\n", i)); 1578 DPRINTF((" conn = %d\n", sc->sc_ports[i].rp_conn_type)); 1579 DPRINTF((" ddc = %d\n", sc->sc_ports[i].rp_ddc_type)); 1580 DPRINTF((" dac = %d\n", sc->sc_ports[i].rp_dac_type)); 1581 DPRINTF((" tmds = %d\n", sc->sc_ports[i].rp_tmds_type)); 1582 1583 sc->sc_ports[i].rp_edid_valid = 0; 1584 /* first look for static EDID data */ 1585 if ((edid_data = prop_dictionary_get(device_properties( 1586 &sc->sc_dev), "EDID")) != NULL) { 1587 1588 aprint_normal("%s: using static EDID\n", 1589 sc->sc_dev.dv_xname); 1590 memcpy(edid, prop_data_data_nocopy(edid_data), 128); 1591 if (edid_parse(edid, eip) == 0) { 1592 1593 sc->sc_ports[i].rp_edid_valid = 1; 1594 edid_print(eip); 1595 } 1596 } 1597 /* if we didn't find any we'll try to talk to the monitor */ 1598 if (sc->sc_ports[i].rp_edid_valid != 1) { 1599 1600 ddc = sc->sc_ports[i].rp_ddc_type; 1601 if (ddc != RADEON_DDC_NONE) { 1602 if ((radeonfb_i2c_read_edid(sc, ddc, edid) 1603 == 0) && (edid_parse(edid, eip) == 0)) { 1604 1605 sc->sc_ports[i].rp_edid_valid = 1; 1606 edid_print(eip); 1607 } 1608 } 1609 } 1610 } 1611 1612 return found; 1613 } 1614 1615 int 1616 radeonfb_gettmds(struct radeonfb_softc *sc) 1617 { 1618 int i; 1619 1620 if (!sc->sc_biossz) { 1621 goto nobios; 1622 } 1623 1624 if (IS_ATOM(sc)) { 1625 /* XXX: not done yet */ 1626 } else { 1627 uint16_t ptr; 1628 int n; 1629 1630 ptr = GETBIOS16(sc, 0x48); 1631 ptr = GETBIOS16(sc, ptr + 0x34); 1632 DPRINTF(("DFP table revision %d\n", GETBIOS8(sc, ptr))); 1633 if (GETBIOS8(sc, ptr) == 3) { 1634 /* revision three table */ 1635 n = GETBIOS8(sc, ptr + 5) + 1; 1636 n = min(n, 4); 1637 1638 memset(sc->sc_tmds_pll, 0, sizeof (sc->sc_tmds_pll)); 1639 for (i = 0; i < n; i++) { 1640 sc->sc_tmds_pll[i].rtp_pll = GETBIOS32(sc, 1641 ptr + i * 10 + 8); 1642 sc->sc_tmds_pll[i].rtp_freq = GETBIOS16(sc, 1643 ptr + i * 10 + 0x10); 1644 DPRINTF(("TMDS_PLL dot clock %d pll %x\n", 1645 sc->sc_tmds_pll[i].rtp_freq, 1646 sc->sc_tmds_pll[i].rtp_pll)); 1647 } 1648 return 0; 1649 } 1650 } 1651 1652 nobios: 1653 DPRINTF(("no suitable DFP table present\n")); 1654 for (i = 0; 1655 i < sizeof (radeonfb_tmds_pll) / sizeof (radeonfb_tmds_pll[0]); 1656 i++) { 1657 int j; 1658 1659 if (radeonfb_tmds_pll[i].family != sc->sc_family) 1660 continue; 1661 1662 for (j = 0; j < 4; j++) { 1663 sc->sc_tmds_pll[j] = radeonfb_tmds_pll[i].plls[j]; 1664 DPRINTF(("TMDS_PLL dot clock %d pll %x\n", 1665 sc->sc_tmds_pll[j].rtp_freq, 1666 sc->sc_tmds_pll[j].rtp_pll)); 1667 } 1668 return 0; 1669 } 1670 1671 return -1; 1672 } 1673 1674 const struct videomode * 1675 radeonfb_modelookup(const char *name) 1676 { 1677 int i; 1678 1679 for (i = 0; i < videomode_count; i++) 1680 if (!strcmp(name, videomode_list[i].name)) 1681 return &videomode_list[i]; 1682 1683 return NULL; 1684 } 1685 1686 void 1687 radeonfb_pllwriteupdate(struct radeonfb_softc *sc, int crtc) 1688 { 1689 if (crtc) { 1690 while (GETPLL(sc, RADEON_P2PLL_REF_DIV) & 1691 RADEON_P2PLL_ATOMIC_UPDATE_R); 1692 SETPLL(sc, RADEON_P2PLL_REF_DIV, RADEON_P2PLL_ATOMIC_UPDATE_W); 1693 } else { 1694 while (GETPLL(sc, RADEON_PPLL_REF_DIV) & 1695 RADEON_PPLL_ATOMIC_UPDATE_R); 1696 SETPLL(sc, RADEON_PPLL_REF_DIV, RADEON_PPLL_ATOMIC_UPDATE_W); 1697 } 1698 } 1699 1700 void 1701 radeonfb_pllwaitatomicread(struct radeonfb_softc *sc, int crtc) 1702 { 1703 int i; 1704 1705 for (i = 10000; i; i--) { 1706 if (crtc) { 1707 if (GETPLL(sc, RADEON_P2PLL_REF_DIV) & 1708 RADEON_P2PLL_ATOMIC_UPDATE_R) 1709 break; 1710 } else { 1711 if (GETPLL(sc, RADEON_PPLL_REF_DIV) & 1712 RADEON_PPLL_ATOMIC_UPDATE_R) 1713 break; 1714 } 1715 } 1716 } 1717 1718 void 1719 radeonfb_program_vclk(struct radeonfb_softc *sc, int dotclock, int crtc) 1720 { 1721 uint32_t pbit = 0; 1722 uint32_t feed = 0; 1723 uint32_t data; 1724 #if 1 1725 int i; 1726 #endif 1727 1728 radeonfb_calc_dividers(sc, dotclock, &pbit, &feed); 1729 1730 if (crtc == 0) { 1731 1732 /* XXXX: mobility workaround missing */ 1733 /* XXXX: R300 stuff missing */ 1734 1735 PATCHPLL(sc, RADEON_VCLK_ECP_CNTL, 1736 RADEON_VCLK_SRC_SEL_CPUCLK, 1737 ~RADEON_VCLK_SRC_SEL_MASK); 1738 1739 /* put vclk into reset, use atomic updates */ 1740 SETPLL(sc, RADEON_PPLL_CNTL, 1741 RADEON_PPLL_REFCLK_SEL | 1742 RADEON_PPLL_FBCLK_SEL | 1743 RADEON_PPLL_RESET | 1744 RADEON_PPLL_ATOMIC_UPDATE_EN | 1745 RADEON_PPLL_VGA_ATOMIC_UPDATE_EN); 1746 1747 /* select clock 3 */ 1748 #if 0 1749 PATCH32(sc, RADEON_CLOCK_CNTL_INDEX, RADEON_PLL_DIV_SEL, 1750 ~RADEON_PLL_DIV_SEL); 1751 #else 1752 PATCH32(sc, RADEON_CLOCK_CNTL_INDEX, 0, 1753 ~RADEON_PLL_DIV_SEL); 1754 #endif 1755 1756 /* XXX: R300 family -- program divider differently? */ 1757 1758 /* program reference divider */ 1759 PATCHPLL(sc, RADEON_PPLL_REF_DIV, sc->sc_refdiv, 1760 ~RADEON_PPLL_REF_DIV_MASK); 1761 PRINTPLL(RADEON_PPLL_REF_DIV); 1762 1763 #if 0 1764 data = GETPLL(sc, RADEON_PPLL_DIV_3); 1765 data &= ~(RADEON_PPLL_FB3_DIV_MASK | 1766 RADEON_PPLL_POST3_DIV_MASK); 1767 data |= pbit; 1768 data |= (feed & RADEON_PPLL_FB3_DIV_MASK); 1769 PUTPLL(sc, RADEON_PPLL_DIV_3, data); 1770 #else 1771 for (i = 0; i < 4; i++) { 1772 } 1773 #endif 1774 1775 /* use the atomic update */ 1776 radeonfb_pllwriteupdate(sc, crtc); 1777 1778 /* and wait for it to complete */ 1779 radeonfb_pllwaitatomicread(sc, crtc); 1780 1781 /* program HTOTAL (why?) */ 1782 PUTPLL(sc, RADEON_HTOTAL_CNTL, 0); 1783 1784 /* drop reset */ 1785 CLRPLL(sc, RADEON_PPLL_CNTL, 1786 RADEON_PPLL_RESET | RADEON_PPLL_SLEEP | 1787 RADEON_PPLL_ATOMIC_UPDATE_EN | 1788 RADEON_PPLL_VGA_ATOMIC_UPDATE_EN); 1789 1790 PRINTPLL(RADEON_PPLL_CNTL); 1791 1792 /* give clock time to lock */ 1793 delay(50000); 1794 1795 PATCHPLL(sc, RADEON_VCLK_ECP_CNTL, 1796 RADEON_VCLK_SRC_SEL_PPLLCLK, 1797 ~RADEON_VCLK_SRC_SEL_MASK); 1798 1799 } else { 1800 1801 PATCHPLL(sc, RADEON_PIXCLKS_CNTL, 1802 RADEON_PIX2CLK_SRC_SEL_CPUCLK, 1803 ~RADEON_PIX2CLK_SRC_SEL_MASK); 1804 1805 /* put vclk into reset, use atomic updates */ 1806 SETPLL(sc, RADEON_P2PLL_CNTL, 1807 RADEON_P2PLL_RESET | 1808 RADEON_P2PLL_ATOMIC_UPDATE_EN | 1809 RADEON_P2PLL_VGA_ATOMIC_UPDATE_EN); 1810 1811 /* XXX: R300 family -- program divider differently? */ 1812 1813 /* program reference divider */ 1814 PATCHPLL(sc, RADEON_P2PLL_REF_DIV, sc->sc_refdiv, 1815 ~RADEON_P2PLL_REF_DIV_MASK); 1816 1817 /* program feedback and post dividers */ 1818 data = GETPLL(sc, RADEON_P2PLL_DIV_0); 1819 data &= ~(RADEON_P2PLL_FB0_DIV_MASK | 1820 RADEON_P2PLL_POST0_DIV_MASK); 1821 data |= pbit; 1822 data |= (feed & RADEON_P2PLL_FB0_DIV_MASK); 1823 PUTPLL(sc, RADEON_P2PLL_DIV_0, data); 1824 1825 /* use the atomic update */ 1826 radeonfb_pllwriteupdate(sc, crtc); 1827 1828 /* and wait for it to complete */ 1829 radeonfb_pllwaitatomicread(sc, crtc); 1830 1831 /* program HTOTAL (why?) */ 1832 PUTPLL(sc, RADEON_HTOTAL2_CNTL, 0); 1833 1834 /* drop reset */ 1835 CLRPLL(sc, RADEON_P2PLL_CNTL, 1836 RADEON_P2PLL_RESET | RADEON_P2PLL_SLEEP | 1837 RADEON_P2PLL_ATOMIC_UPDATE_EN | 1838 RADEON_P2PLL_VGA_ATOMIC_UPDATE_EN); 1839 1840 /* allow time for clock to lock */ 1841 delay(50000); 1842 1843 PATCHPLL(sc, RADEON_PIXCLKS_CNTL, 1844 RADEON_PIX2CLK_SRC_SEL_P2PLLCLK, 1845 ~RADEON_PIX2CLK_SRC_SEL_MASK); 1846 } 1847 PRINTREG(RADEON_CRTC_MORE_CNTL); 1848 } 1849 1850 void 1851 radeonfb_modeswitch(struct radeonfb_display *dp) 1852 { 1853 struct radeonfb_softc *sc = dp->rd_softc; 1854 int i; 1855 1856 /* blank the display while we switch modes */ 1857 //radeonfb_blank(dp, 1); 1858 1859 #if 0 1860 SET32(sc, RADEON_CRTC_EXT_CNTL, 1861 RADEON_CRTC_VSYNC_DIS | RADEON_CRTC_HSYNC_DIS | 1862 RADEON_CRTC_DISPLAY_DIS /* | RADEON_CRTC_DISP_REQ_EN_B */); 1863 #endif 1864 1865 /* these registers might get in the way... */ 1866 PUT32(sc, RADEON_OVR_CLR, 0); 1867 PUT32(sc, RADEON_OVR_WID_LEFT_RIGHT, 0); 1868 PUT32(sc, RADEON_OVR_WID_TOP_BOTTOM, 0); 1869 PUT32(sc, RADEON_OV0_SCALE_CNTL, 0); 1870 PUT32(sc, RADEON_SUBPIC_CNTL, 0); 1871 PUT32(sc, RADEON_VIPH_CONTROL, 0); 1872 PUT32(sc, RADEON_I2C_CNTL_1, 0); 1873 PUT32(sc, RADEON_GEN_INT_CNTL, 0); 1874 PUT32(sc, RADEON_CAP0_TRIG_CNTL, 0); 1875 PUT32(sc, RADEON_CAP1_TRIG_CNTL, 0); 1876 PUT32(sc, RADEON_SURFACE_CNTL, 0); 1877 1878 for (i = 0; i < dp->rd_ncrtcs; i++) 1879 radeonfb_setcrtc(dp, i); 1880 1881 /* activate the display */ 1882 //radeonfb_blank(dp, 0); 1883 } 1884 1885 void 1886 radeonfb_setcrtc(struct radeonfb_display *dp, int index) 1887 { 1888 int crtc; 1889 struct videomode *mode; 1890 struct radeonfb_softc *sc; 1891 struct radeonfb_crtc *cp; 1892 uint32_t v; 1893 uint32_t gencntl; 1894 uint32_t htotaldisp; 1895 uint32_t hsyncstrt; 1896 uint32_t vtotaldisp; 1897 uint32_t vsyncstrt; 1898 uint32_t fphsyncstrt; 1899 uint32_t fpvsyncstrt; 1900 uint32_t fphtotaldisp; 1901 uint32_t fpvtotaldisp; 1902 uint32_t pitch; 1903 1904 sc = dp->rd_softc; 1905 cp = &dp->rd_crtcs[index]; 1906 crtc = cp->rc_number; 1907 mode = &cp->rc_videomode; 1908 1909 #if 1 1910 pitch = (((dp->rd_virtx * dp->rd_bpp) + ((dp->rd_bpp * 8) - 1)) / 1911 (dp->rd_bpp * 8)); 1912 #else 1913 pitch = (((sc->sc_maxx * sc->sc_maxbpp) + ((sc->sc_maxbpp * 8) - 1)) / 1914 (sc->sc_maxbpp * 8)); 1915 #endif 1916 //pitch = pitch | (pitch << 16); 1917 1918 switch (crtc) { 1919 case 0: 1920 gencntl = RADEON_CRTC_GEN_CNTL; 1921 htotaldisp = RADEON_CRTC_H_TOTAL_DISP; 1922 hsyncstrt = RADEON_CRTC_H_SYNC_STRT_WID; 1923 vtotaldisp = RADEON_CRTC_V_TOTAL_DISP; 1924 vsyncstrt = RADEON_CRTC_V_SYNC_STRT_WID; 1925 fpvsyncstrt = RADEON_FP_V_SYNC_STRT_WID; 1926 fphsyncstrt = RADEON_FP_H_SYNC_STRT_WID; 1927 fpvtotaldisp = RADEON_FP_CRTC_V_TOTAL_DISP; 1928 fphtotaldisp = RADEON_FP_CRTC_H_TOTAL_DISP; 1929 break; 1930 case 1: 1931 gencntl = RADEON_CRTC2_GEN_CNTL; 1932 htotaldisp = RADEON_CRTC2_H_TOTAL_DISP; 1933 hsyncstrt = RADEON_CRTC2_H_SYNC_STRT_WID; 1934 vtotaldisp = RADEON_CRTC2_V_TOTAL_DISP; 1935 vsyncstrt = RADEON_CRTC2_V_SYNC_STRT_WID; 1936 fpvsyncstrt = RADEON_FP_V2_SYNC_STRT_WID; 1937 fphsyncstrt = RADEON_FP_H2_SYNC_STRT_WID; 1938 fpvtotaldisp = RADEON_FP_CRTC2_V_TOTAL_DISP; 1939 fphtotaldisp = RADEON_FP_CRTC2_H_TOTAL_DISP; 1940 break; 1941 default: 1942 panic("Bad CRTC!"); 1943 break; 1944 } 1945 1946 /* 1947 * CRTC_GEN_CNTL - depth, accelerator mode, etc. 1948 */ 1949 /* only bother with 32bpp and 8bpp */ 1950 v = dp->rd_format << RADEON_CRTC_PIX_WIDTH_SHIFT; 1951 1952 if (crtc == 1) { 1953 v |= RADEON_CRTC2_CRT2_ON | RADEON_CRTC2_EN; 1954 } else { 1955 v |= RADEON_CRTC_EXT_DISP_EN | RADEON_CRTC_EN; 1956 } 1957 1958 if (mode->flags & VID_DBLSCAN) 1959 v |= RADEON_CRTC2_DBL_SCAN_EN; 1960 1961 if (mode->flags & VID_INTERLACE) 1962 v |= RADEON_CRTC2_INTERLACE_EN; 1963 1964 if (mode->flags & VID_CSYNC) { 1965 v |= RADEON_CRTC2_CSYNC_EN; 1966 if (crtc == 1) 1967 v |= RADEON_CRTC2_VSYNC_TRISTAT; 1968 } 1969 1970 PUT32(sc, gencntl, v); 1971 DPRINTF(("CRTC%s_GEN_CNTL = %08x\n", crtc ? "2" : "", v)); 1972 1973 /* 1974 * CRTC_EXT_CNTL - preserve disable flags, set ATI linear and EXT_CNT 1975 */ 1976 v = GET32(sc, RADEON_CRTC_EXT_CNTL); 1977 if (crtc == 0) { 1978 v &= (RADEON_CRTC_VSYNC_DIS | RADEON_CRTC_HSYNC_DIS | 1979 RADEON_CRTC_DISPLAY_DIS); 1980 v |= RADEON_XCRT_CNT_EN | RADEON_VGA_ATI_LINEAR; 1981 if (mode->flags & VID_CSYNC) 1982 v |= RADEON_CRTC_VSYNC_TRISTAT; 1983 } 1984 /* unconditional turn on CRT, in case first CRTC is DFP */ 1985 v |= RADEON_CRTC_CRT_ON; 1986 PUT32(sc, RADEON_CRTC_EXT_CNTL, v); 1987 PRINTREG(RADEON_CRTC_EXT_CNTL); 1988 1989 /* 1990 * H_TOTAL_DISP 1991 */ 1992 v = ((mode->hdisplay / 8) - 1) << 16; 1993 v |= (mode->htotal / 8) - 1; 1994 PUT32(sc, htotaldisp, v); 1995 DPRINTF(("CRTC%s_H_TOTAL_DISP = %08x\n", crtc ? "2" : "", v)); 1996 PUT32(sc, fphtotaldisp, v); 1997 DPRINTF(("FP_H%s_TOTAL_DISP = %08x\n", crtc ? "2" : "", v)); 1998 1999 /* 2000 * H_SYNC_STRT_WID 2001 */ 2002 v = (((mode->hsync_end - mode->hsync_start) / 8) << 16); 2003 v |= mode->hsync_start; 2004 if (mode->flags & VID_NHSYNC) 2005 v |= RADEON_CRTC_H_SYNC_POL; 2006 PUT32(sc, hsyncstrt, v); 2007 DPRINTF(("CRTC%s_H_SYNC_STRT_WID = %08x\n", crtc ? "2" : "", v)); 2008 PUT32(sc, fphsyncstrt, v); 2009 DPRINTF(("FP_H%s_SYNC_STRT_WID = %08x\n", crtc ? "2" : "", v)); 2010 2011 /* 2012 * V_TOTAL_DISP 2013 */ 2014 v = ((mode->vdisplay - 1) << 16); 2015 v |= (mode->vtotal - 1); 2016 PUT32(sc, vtotaldisp, v); 2017 DPRINTF(("CRTC%s_V_TOTAL_DISP = %08x\n", crtc ? "2" : "", v)); 2018 PUT32(sc, fpvtotaldisp, v); 2019 DPRINTF(("FP_V%s_TOTAL_DISP = %08x\n", crtc ? "2" : "", v)); 2020 2021 /* 2022 * V_SYNC_STRT_WID 2023 */ 2024 v = ((mode->vsync_end - mode->vsync_start) << 16); 2025 v |= (mode->vsync_start - 1); 2026 if (mode->flags & VID_NVSYNC) 2027 v |= RADEON_CRTC_V_SYNC_POL; 2028 PUT32(sc, vsyncstrt, v); 2029 DPRINTF(("CRTC%s_V_SYNC_STRT_WID = %08x\n", crtc ? "2" : "", v)); 2030 PUT32(sc, fpvsyncstrt, v); 2031 DPRINTF(("FP_V%s_SYNC_STRT_WID = %08x\n", crtc ? "2" : "", v)); 2032 2033 radeonfb_program_vclk(sc, mode->dot_clock, crtc); 2034 2035 switch (crtc) { 2036 case 0: 2037 PUT32(sc, RADEON_CRTC_OFFSET, 0); 2038 PUT32(sc, RADEON_CRTC_OFFSET_CNTL, 0); 2039 PUT32(sc, RADEON_CRTC_PITCH, pitch); 2040 CLR32(sc, RADEON_DISP_MERGE_CNTL, RADEON_DISP_RGB_OFFSET_EN); 2041 2042 CLR32(sc, RADEON_CRTC_EXT_CNTL, 2043 RADEON_CRTC_VSYNC_DIS | RADEON_CRTC_HSYNC_DIS | 2044 RADEON_CRTC_DISPLAY_DIS /* | RADEON_CRTC_DISP_REQ_EN_B */); 2045 CLR32(sc, RADEON_CRTC_GEN_CNTL, RADEON_CRTC_DISP_REQ_EN_B); 2046 PRINTREG(RADEON_CRTC_EXT_CNTL); 2047 PRINTREG(RADEON_CRTC_GEN_CNTL); 2048 PRINTREG(RADEON_CLOCK_CNTL_INDEX); 2049 break; 2050 2051 case 1: 2052 PUT32(sc, RADEON_CRTC2_OFFSET, 0); 2053 PUT32(sc, RADEON_CRTC2_OFFSET_CNTL, 0); 2054 PUT32(sc, RADEON_CRTC2_PITCH, pitch); 2055 CLR32(sc, RADEON_DISP2_MERGE_CNTL, RADEON_DISP2_RGB_OFFSET_EN); 2056 CLR32(sc, RADEON_CRTC2_GEN_CNTL, 2057 RADEON_CRTC2_VSYNC_DIS | 2058 RADEON_CRTC2_HSYNC_DIS | 2059 RADEON_CRTC2_DISP_DIS | RADEON_CRTC2_DISP_REQ_EN_B); 2060 PRINTREG(RADEON_CRTC2_GEN_CNTL); 2061 break; 2062 } 2063 } 2064 2065 int 2066 radeonfb_isblank(struct radeonfb_display *dp) 2067 { 2068 uint32_t reg, mask; 2069 2070 if (dp->rd_crtcs[0].rc_number) { 2071 reg = RADEON_CRTC2_GEN_CNTL; 2072 mask = RADEON_CRTC2_DISP_DIS; 2073 } else { 2074 reg = RADEON_CRTC_EXT_CNTL; 2075 mask = RADEON_CRTC_DISPLAY_DIS; 2076 } 2077 return ((GET32(dp->rd_softc, reg) & mask) ? 1 : 0); 2078 } 2079 2080 void 2081 radeonfb_blank(struct radeonfb_display *dp, int blank) 2082 { 2083 struct radeonfb_softc *sc = dp->rd_softc; 2084 uint32_t reg, mask; 2085 uint32_t fpreg, fpval; 2086 int i; 2087 2088 for (i = 0; i < dp->rd_ncrtcs; i++) { 2089 2090 if (dp->rd_crtcs[i].rc_number) { 2091 reg = RADEON_CRTC2_GEN_CNTL; 2092 mask = RADEON_CRTC2_DISP_DIS; 2093 fpreg = RADEON_FP2_GEN_CNTL; 2094 fpval = RADEON_FP2_ON; 2095 } else { 2096 reg = RADEON_CRTC_EXT_CNTL; 2097 mask = RADEON_CRTC_DISPLAY_DIS; 2098 fpreg = RADEON_FP_GEN_CNTL; 2099 fpval = RADEON_FP_FPON; 2100 } 2101 2102 if (blank) { 2103 SET32(sc, reg, mask); 2104 CLR32(sc, fpreg, fpval); 2105 } else { 2106 CLR32(sc, reg, mask); 2107 SET32(sc, fpreg, fpval); 2108 } 2109 } 2110 PRINTREG(RADEON_FP_GEN_CNTL); 2111 PRINTREG(RADEON_FP2_GEN_CNTL); 2112 } 2113 2114 void 2115 radeonfb_init_screen(void *cookie, struct vcons_screen *scr, int existing, 2116 long *defattr) 2117 { 2118 struct radeonfb_display *dp = cookie; 2119 struct rasops_info *ri = &scr->scr_ri; 2120 2121 /* initialize font subsystem */ 2122 wsfont_init(); 2123 2124 DPRINTF(("init screen called, existing %d\n", existing)); 2125 2126 ri->ri_depth = dp->rd_bpp; 2127 ri->ri_width = dp->rd_virtx; 2128 ri->ri_height = dp->rd_virty; 2129 ri->ri_stride = dp->rd_stride; 2130 ri->ri_flg = RI_CENTER; 2131 ri->ri_bits = (void *)dp->rd_fbptr; 2132 2133 /* XXX: 32 bpp only */ 2134 /* this is rgb in "big-endian order..." */ 2135 ri->ri_rnum = 8; 2136 ri->ri_gnum = 8; 2137 ri->ri_bnum = 8; 2138 ri->ri_rpos = 16; 2139 ri->ri_gpos = 8; 2140 ri->ri_bpos = 0; 2141 2142 if (existing) { 2143 ri->ri_flg |= RI_CLEAR; 2144 2145 /* start a modeswitch now */ 2146 radeonfb_modeswitch(dp); 2147 } 2148 2149 /* 2150 * XXX: font selection should be based on properties, with some 2151 * normal/reasonable default. 2152 */ 2153 ri->ri_caps = WSSCREEN_WSCOLORS; 2154 2155 /* initialize and look for an initial font */ 2156 rasops_init(ri, dp->rd_virty/8, dp->rd_virtx/8); 2157 2158 rasops_reconfig(ri, dp->rd_virty / ri->ri_font->fontheight, 2159 dp->rd_virtx / ri->ri_font->fontwidth); 2160 2161 /* enable acceleration */ 2162 ri->ri_ops.copyrows = radeonfb_copyrows; 2163 ri->ri_ops.copycols = radeonfb_copycols; 2164 ri->ri_ops.eraserows = radeonfb_eraserows; 2165 ri->ri_ops.erasecols = radeonfb_erasecols; 2166 ri->ri_ops.allocattr = radeonfb_allocattr; 2167 if (!IS_R300(dp->rd_softc)) { 2168 ri->ri_ops.putchar = radeonfb_putchar; 2169 } 2170 ri->ri_ops.cursor = radeonfb_cursor; 2171 } 2172 2173 void 2174 radeonfb_set_fbloc(struct radeonfb_softc *sc) 2175 { 2176 uint32_t gen, ext, gen2 = 0; 2177 uint32_t agploc, aperbase, apersize, mcfbloc; 2178 2179 gen = GET32(sc, RADEON_CRTC_GEN_CNTL); 2180 ext = GET32(sc, RADEON_CRTC_EXT_CNTL); 2181 agploc = GET32(sc, RADEON_MC_AGP_LOCATION); 2182 aperbase = GET32(sc, RADEON_CONFIG_APER_0_BASE); 2183 apersize = GET32(sc, RADEON_CONFIG_APER_SIZE); 2184 2185 PUT32(sc, RADEON_CRTC_GEN_CNTL, gen | RADEON_CRTC_DISP_REQ_EN_B); 2186 PUT32(sc, RADEON_CRTC_EXT_CNTL, ext | RADEON_CRTC_DISPLAY_DIS); 2187 //PUT32(sc, RADEON_CRTC_GEN_CNTL, gen | RADEON_CRTC_DISPLAY_DIS); 2188 //PUT32(sc, RADEON_CRTC_EXT_CNTL, ext | RADEON_CRTC_DISP_REQ_EN_B); 2189 2190 if (HAS_CRTC2(sc)) { 2191 gen2 = GET32(sc, RADEON_CRTC2_GEN_CNTL); 2192 PUT32(sc, RADEON_CRTC2_GEN_CNTL, 2193 gen2 | RADEON_CRTC2_DISP_REQ_EN_B); 2194 } 2195 2196 delay(100000); 2197 2198 mcfbloc = (aperbase >> 16) | 2199 ((aperbase + (apersize - 1)) & 0xffff0000); 2200 2201 sc->sc_aperbase = (mcfbloc & 0xffff) << 16; 2202 sc->sc_memsz = apersize; 2203 2204 if (((agploc & 0xffff) << 16) != 2205 ((mcfbloc & 0xffff0000U) + 0x10000)) { 2206 agploc = mcfbloc & 0xffff0000U; 2207 agploc |= ((agploc + 0x10000) >> 16); 2208 } 2209 2210 PUT32(sc, RADEON_HOST_PATH_CNTL, 0); 2211 2212 PUT32(sc, RADEON_MC_FB_LOCATION, mcfbloc); 2213 PUT32(sc, RADEON_MC_AGP_LOCATION, agploc); 2214 2215 DPRINTF(("aperbase = %u\n", aperbase)); 2216 PRINTREG(RADEON_MC_FB_LOCATION); 2217 PRINTREG(RADEON_MC_AGP_LOCATION); 2218 2219 PUT32(sc, RADEON_DISPLAY_BASE_ADDR, sc->sc_aperbase); 2220 2221 if (HAS_CRTC2(sc)) 2222 PUT32(sc, RADEON_DISPLAY2_BASE_ADDR, sc->sc_aperbase); 2223 2224 PUT32(sc, RADEON_OV0_BASE_ADDR, sc->sc_aperbase); 2225 2226 #if 0 2227 /* XXX: what is this AGP garbage? :-) */ 2228 PUT32(sc, RADEON_AGP_CNTL, 0x00100000); 2229 #endif 2230 2231 delay(100000); 2232 2233 PUT32(sc, RADEON_CRTC_GEN_CNTL, gen); 2234 PUT32(sc, RADEON_CRTC_EXT_CNTL, ext); 2235 2236 if (HAS_CRTC2(sc)) 2237 PUT32(sc, RADEON_CRTC2_GEN_CNTL, gen2); 2238 } 2239 2240 void 2241 radeonfb_init_misc(struct radeonfb_softc *sc) 2242 { 2243 PUT32(sc, RADEON_BUS_CNTL, 2244 RADEON_BUS_MASTER_DIS | 2245 RADEON_BUS_PREFETCH_MODE_ACT | 2246 RADEON_BUS_PCI_READ_RETRY_EN | 2247 RADEON_BUS_PCI_WRT_RETRY_EN | 2248 (3 << RADEON_BUS_RETRY_WS_SHIFT) | 2249 RADEON_BUS_MSTR_RD_MULT | 2250 RADEON_BUS_MSTR_RD_LINE | 2251 RADEON_BUS_RD_DISCARD_EN | 2252 RADEON_BUS_MSTR_DISCONNECT_EN | 2253 RADEON_BUS_READ_BURST); 2254 2255 PUT32(sc, RADEON_BUS_CNTL1, 0xf0); 2256 /* PUT32(sc, RADEON_SEPROM_CNTL1, 0x09ff0000); */ 2257 PUT32(sc, RADEON_FCP_CNTL, RADEON_FCP0_SRC_GND); 2258 PUT32(sc, RADEON_RBBM_CNTL, 2259 (3 << RADEON_RB_SETTLE_SHIFT) | 2260 (4 << RADEON_ABORTCLKS_HI_SHIFT) | 2261 (4 << RADEON_ABORTCLKS_CP_SHIFT) | 2262 (4 << RADEON_ABORTCLKS_CFIFO_SHIFT)); 2263 2264 /* XXX: figure out what these mean! */ 2265 PUT32(sc, RADEON_AGP_CNTL, 0x00100000); 2266 PUT32(sc, RADEON_HOST_PATH_CNTL, 0); 2267 //PUT32(sc, RADEON_DISP_MISC_CNTL, 0x5bb00400); 2268 2269 PUT32(sc, RADEON_GEN_INT_CNTL, 0); 2270 PUT32(sc, RADEON_GEN_INT_STATUS, GET32(sc, RADEON_GEN_INT_STATUS)); 2271 } 2272 2273 /* 2274 * This loads a linear color map for true color. 2275 */ 2276 void 2277 radeonfb_init_palette(struct radeonfb_softc *sc, int crtc) 2278 { 2279 int i; 2280 uint32_t vclk; 2281 2282 #define DAC_WIDTH ((1 << 10) - 1) 2283 #define CLUT_WIDTH ((1 << 8) - 1) 2284 #define CLUT_COLOR(i) ((i * DAC_WIDTH * 2 / CLUT_WIDTH + 1) / 2) 2285 2286 vclk = GETPLL(sc, RADEON_VCLK_ECP_CNTL); 2287 PUTPLL(sc, RADEON_VCLK_ECP_CNTL, vclk & ~RADEON_PIXCLK_DAC_ALWAYS_ONb); 2288 2289 if (crtc) 2290 SET32(sc, RADEON_DAC_CNTL2, RADEON_DAC2_PALETTE_ACC_CTL); 2291 else 2292 CLR32(sc, RADEON_DAC_CNTL2, RADEON_DAC2_PALETTE_ACC_CTL); 2293 2294 PUT32(sc, RADEON_PALETTE_INDEX, 0); 2295 for (i = 0; i <= CLUT_WIDTH; ++i) { 2296 PUT32(sc, RADEON_PALETTE_30_DATA, 2297 (CLUT_COLOR(i) << 10) | 2298 (CLUT_COLOR(i) << 20) | 2299 (CLUT_COLOR(i))); 2300 } 2301 2302 CLR32(sc, RADEON_DAC_CNTL2, RADEON_DAC2_PALETTE_ACC_CTL); 2303 PRINTREG(RADEON_DAC_CNTL2); 2304 2305 PUTPLL(sc, RADEON_VCLK_ECP_CNTL, vclk); 2306 } 2307 2308 /* 2309 * Bugs in some R300 hardware requires this when accessing CLOCK_CNTL_INDEX. 2310 */ 2311 void 2312 radeonfb_r300cg_workaround(struct radeonfb_softc *sc) 2313 { 2314 uint32_t tmp, save; 2315 2316 save = GET32(sc, RADEON_CLOCK_CNTL_INDEX); 2317 tmp = save & ~(0x3f | RADEON_PLL_WR_EN); 2318 PUT32(sc, RADEON_CLOCK_CNTL_INDEX, tmp); 2319 tmp = GET32(sc, RADEON_CLOCK_CNTL_DATA); 2320 PUT32(sc, RADEON_CLOCK_CNTL_INDEX, save); 2321 } 2322 2323 /* 2324 * Acceleration entry points. 2325 */ 2326 static void 2327 radeonfb_putchar(void *cookie, int row, int col, u_int c, long attr) 2328 { 2329 struct rasops_info *ri = cookie; 2330 struct vcons_screen *scr = ri->ri_hw; 2331 struct radeonfb_display *dp = scr->scr_cookie; 2332 uint32_t x, y, w, h; 2333 uint32_t bg, fg; 2334 uint8_t *data; 2335 2336 if (dp->rd_wsmode != WSDISPLAYIO_MODE_EMUL) 2337 return; 2338 2339 if (!CHAR_IN_FONT(c, ri->ri_font)) 2340 return; 2341 2342 w = ri->ri_font->fontwidth; 2343 h = ri->ri_font->fontheight; 2344 2345 bg = ri->ri_devcmap[(attr >> 16) & 0xf]; 2346 fg = ri->ri_devcmap[(attr >> 24) & 0xf]; 2347 2348 x = ri->ri_xorigin + col * w; 2349 y = ri->ri_yorigin + row * h; 2350 2351 if (c == 0x20) { 2352 radeonfb_rectfill(dp, x, y, w, h, bg); 2353 } else { 2354 data = (uint8_t *)ri->ri_font->data + 2355 (c - ri->ri_font->firstchar) * ri->ri_fontscale; 2356 2357 radeonfb_setup_mono(dp, x, y, w, h, fg, bg); 2358 radeonfb_feed_bytes(dp, ri->ri_fontscale, data); 2359 } 2360 } 2361 2362 static void 2363 radeonfb_eraserows(void *cookie, int row, int nrows, long fillattr) 2364 { 2365 struct rasops_info *ri = cookie; 2366 struct vcons_screen *scr = ri->ri_hw; 2367 struct radeonfb_display *dp = scr->scr_cookie; 2368 uint32_t x, y, w, h, fg, bg, ul; 2369 2370 /* XXX: check for full emulation mode? */ 2371 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 2372 x = ri->ri_xorigin; 2373 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 2374 w = ri->ri_emuwidth; 2375 h = ri->ri_font->fontheight * nrows; 2376 2377 rasops_unpack_attr(fillattr, &fg, &bg, &ul); 2378 radeonfb_rectfill(dp, x, y, w, h, ri->ri_devcmap[bg & 0xf]); 2379 } 2380 } 2381 2382 static void 2383 radeonfb_copyrows(void *cookie, int srcrow, int dstrow, int nrows) 2384 { 2385 struct rasops_info *ri = cookie; 2386 struct vcons_screen *scr = ri->ri_hw; 2387 struct radeonfb_display *dp = scr->scr_cookie; 2388 uint32_t x, ys, yd, w, h; 2389 2390 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 2391 x = ri->ri_xorigin; 2392 ys = ri->ri_yorigin + ri->ri_font->fontheight * srcrow; 2393 yd = ri->ri_yorigin + ri->ri_font->fontheight * dstrow; 2394 w = ri->ri_emuwidth; 2395 h = ri->ri_font->fontheight * nrows; 2396 radeonfb_bitblt(dp, x, ys, x, yd, w, h, 2397 RADEON_ROP3_S, 0xffffffff); 2398 } 2399 } 2400 2401 static void 2402 radeonfb_copycols(void *cookie, int row, int srccol, int dstcol, int ncols) 2403 { 2404 struct rasops_info *ri = cookie; 2405 struct vcons_screen *scr = ri->ri_hw; 2406 struct radeonfb_display *dp = scr->scr_cookie; 2407 uint32_t xs, xd, y, w, h; 2408 2409 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 2410 xs = ri->ri_xorigin + ri->ri_font->fontwidth * srccol; 2411 xd = ri->ri_xorigin + ri->ri_font->fontwidth * dstcol; 2412 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 2413 w = ri->ri_font->fontwidth * ncols; 2414 h = ri->ri_font->fontheight; 2415 radeonfb_bitblt(dp, xs, y, xd, y, w, h, 2416 RADEON_ROP3_S, 0xffffffff); 2417 } 2418 } 2419 2420 static void 2421 radeonfb_erasecols(void *cookie, int row, int startcol, int ncols, 2422 long fillattr) 2423 { 2424 struct rasops_info *ri = cookie; 2425 struct vcons_screen *scr = ri->ri_hw; 2426 struct radeonfb_display *dp = scr->scr_cookie; 2427 uint32_t x, y, w, h, fg, bg, ul; 2428 2429 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 2430 x = ri->ri_xorigin + ri->ri_font->fontwidth * startcol; 2431 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 2432 w = ri->ri_font->fontwidth * ncols; 2433 h = ri->ri_font->fontheight; 2434 2435 rasops_unpack_attr(fillattr, &fg, &bg, &ul); 2436 radeonfb_rectfill(dp, x, y, w, h, ri->ri_devcmap[bg & 0xf]); 2437 } 2438 } 2439 2440 static void 2441 radeonfb_cursor(void *cookie, int on, int row, int col) 2442 { 2443 struct rasops_info *ri = cookie; 2444 struct vcons_screen *scr = ri->ri_hw; 2445 struct radeonfb_display *dp = scr->scr_cookie; 2446 int x, y, wi, he; 2447 2448 wi = ri->ri_font->fontwidth; 2449 he = ri->ri_font->fontheight; 2450 2451 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 2452 x = ri->ri_ccol * wi + ri->ri_xorigin; 2453 y = ri->ri_crow * he + ri->ri_yorigin; 2454 /* first turn off the old cursor */ 2455 if (ri->ri_flg & RI_CURSOR) { 2456 radeonfb_bitblt(dp, x, y, x, y, wi, he, 2457 RADEON_ROP3_Dn, 0xffffffff); 2458 ri->ri_flg &= ~RI_CURSOR; 2459 } 2460 ri->ri_crow = row; 2461 ri->ri_ccol = col; 2462 /* then (possibly) turn on the new one */ 2463 if (on) { 2464 x = ri->ri_ccol * wi + ri->ri_xorigin; 2465 y = ri->ri_crow * he + ri->ri_yorigin; 2466 radeonfb_bitblt(dp, x, y, x, y, wi, he, 2467 RADEON_ROP3_Dn, 0xffffffff); 2468 ri->ri_flg |= RI_CURSOR; 2469 } 2470 } else { 2471 scr->scr_ri.ri_crow = row; 2472 scr->scr_ri.ri_ccol = col; 2473 scr->scr_ri.ri_flg &= ~RI_CURSOR; 2474 } 2475 } 2476 2477 static int 2478 radeonfb_allocattr(void *cookie, int fg, int bg, int flags, long *attrp) 2479 { 2480 if ((fg == 0) && (bg == 0)) { 2481 fg = WS_DEFAULT_FG; 2482 bg = WS_DEFAULT_BG; 2483 } 2484 *attrp = ((fg & 0xf) << 24) | ((bg & 0xf) << 16) | (flags & 0xff) << 8; 2485 return 0; 2486 } 2487 2488 /* 2489 * Underlying acceleration support. 2490 */ 2491 static void 2492 radeonfb_setup_mono(struct radeonfb_display *dp, int xd, int yd, int width, 2493 int height, uint32_t fg, uint32_t bg) 2494 { 2495 struct radeonfb_softc *sc = dp->rd_softc; 2496 uint32_t gmc; 2497 uint32_t padded_width = (width+7) & 0xfff8; 2498 uint32_t topleft, bottomright; 2499 2500 gmc = dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT; 2501 2502 if (width != padded_width) { 2503 2504 radeonfb_wait_fifo(sc, 2); 2505 topleft = ((yd << 16) & 0x1fff0000) | (xd & 0x1fff); 2506 bottomright = (((yd + height) << 16) & 0x1fff0000) | 2507 ((xd + width) & 0x1fff); 2508 PUT32(sc, RADEON_SC_TOP_LEFT, topleft); 2509 PUT32(sc, RADEON_SC_BOTTOM_RIGHT, bottomright); 2510 } 2511 2512 radeonfb_wait_fifo(sc, 5); 2513 2514 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 2515 RADEON_GMC_BRUSH_NONE | 2516 RADEON_GMC_SRC_DATATYPE_MONO_FG_BG | 2517 //RADEON_GMC_BYTE_LSB_TO_MSB | 2518 RADEON_GMC_DST_CLIPPING | 2519 RADEON_ROP3_S | 2520 RADEON_DP_SRC_SOURCE_HOST_DATA | 2521 RADEON_GMC_CLR_CMP_CNTL_DIS | 2522 RADEON_GMC_WR_MSK_DIS | 2523 gmc); 2524 2525 PUT32(sc, RADEON_DP_SRC_FRGD_CLR, fg); 2526 PUT32(sc, RADEON_DP_SRC_BKGD_CLR, bg); 2527 2528 PUT32(sc, RADEON_DST_X_Y, (xd << 16) | yd); 2529 PUT32(sc, RADEON_DST_WIDTH_HEIGHT, (padded_width << 16) | height); 2530 2531 } 2532 2533 static void 2534 radeonfb_feed_bytes(struct radeonfb_display *dp, int count, uint8_t *data) 2535 { 2536 struct radeonfb_softc *sc = dp->rd_softc; 2537 int i; 2538 uint32_t latch = 0; 2539 int shift = 0; 2540 2541 for (i = 0; i < count; i++) { 2542 latch |= (data[i] << shift); 2543 if (shift == 24) { 2544 radeonfb_wait_fifo(sc, 1); 2545 PUT32(sc, RADEON_HOST_DATA0, latch); 2546 latch = 0; 2547 shift = 0; 2548 } else 2549 shift += 8; 2550 } 2551 if (shift != 0) { 2552 radeonfb_wait_fifo(sc, 1); 2553 PUT32(sc, RADEON_HOST_DATA0, latch); 2554 } 2555 radeonfb_unclip(sc); 2556 } 2557 2558 static void 2559 radeonfb_rectfill(struct radeonfb_display *dp, int dstx, int dsty, 2560 int width, int height, uint32_t color) 2561 { 2562 struct radeonfb_softc *sc = dp->rd_softc; 2563 uint32_t gmc; 2564 2565 gmc = dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT; 2566 2567 radeonfb_wait_fifo(sc, 6); 2568 2569 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 2570 RADEON_GMC_BRUSH_SOLID_COLOR | 2571 RADEON_GMC_SRC_DATATYPE_COLOR | 2572 RADEON_GMC_CLR_CMP_CNTL_DIS | 2573 RADEON_ROP3_P | gmc); 2574 2575 PUT32(sc, RADEON_DP_BRUSH_FRGD_CLR, color); 2576 PUT32(sc, RADEON_DP_WRITE_MASK, 0xffffffff); 2577 PUT32(sc, RADEON_DP_CNTL, 2578 RADEON_DST_X_LEFT_TO_RIGHT | 2579 RADEON_DST_Y_TOP_TO_BOTTOM); 2580 PUT32(sc, RADEON_DST_Y_X, (dsty << 16) | dstx); 2581 PUT32(sc, RADEON_DST_WIDTH_HEIGHT, (width << 16) | (height)); 2582 2583 /* 2584 * XXX: we don't wait for the fifo to empty -- that would slow 2585 * things down! The linux radeonfb driver waits, but xfree doesn't 2586 */ 2587 /* XXX: for now we do, to make it safe for direct drawing */ 2588 radeonfb_engine_idle(sc); 2589 } 2590 2591 static void 2592 radeonfb_bitblt(struct radeonfb_display *dp, int srcx, int srcy, 2593 int dstx, int dsty, int width, int height, int rop, uint32_t mask) 2594 { 2595 struct radeonfb_softc *sc = dp->rd_softc; 2596 uint32_t gmc; 2597 uint32_t dir; 2598 2599 if (dsty < srcy) { 2600 dir = RADEON_DST_Y_TOP_TO_BOTTOM; 2601 } else { 2602 srcy += height - 1; 2603 dsty += height - 1; 2604 dir = 0; 2605 } 2606 if (dstx < srcx) { 2607 dir |= RADEON_DST_X_LEFT_TO_RIGHT; 2608 } else { 2609 srcx += width - 1; 2610 dstx += width - 1; 2611 } 2612 2613 gmc = dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT; 2614 2615 radeonfb_wait_fifo(sc, 6); 2616 2617 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 2618 //RADEON_GMC_SRC_CLIPPING | 2619 RADEON_GMC_BRUSH_SOLID_COLOR | 2620 RADEON_GMC_SRC_DATATYPE_COLOR | 2621 RADEON_GMC_CLR_CMP_CNTL_DIS | 2622 RADEON_DP_SRC_SOURCE_MEMORY | 2623 rop | gmc); 2624 2625 PUT32(sc, RADEON_DP_WRITE_MASK, mask); 2626 PUT32(sc, RADEON_DP_CNTL, dir); 2627 PUT32(sc, RADEON_SRC_Y_X, (srcy << 16) | srcx); 2628 PUT32(sc, RADEON_DST_Y_X, (dsty << 16) | dstx); 2629 PUT32(sc, RADEON_DST_WIDTH_HEIGHT, (width << 16) | (height)); 2630 2631 /* 2632 * XXX: we don't wait for the fifo to empty -- that would slow 2633 * things down! The linux radeonfb driver waits, but xfree doesn't 2634 */ 2635 /* XXX: for now we do, to make it safe for direct drawing */ 2636 radeonfb_engine_idle(sc); 2637 } 2638 2639 static void 2640 radeonfb_engine_idle(struct radeonfb_softc *sc) 2641 { 2642 int i; 2643 2644 radeonfb_wait_fifo(sc, 64); 2645 for (i = RADEON_TIMEOUT; i; i--) { 2646 if ((GET32(sc, RADEON_RBBM_STATUS) & 2647 RADEON_RBBM_ACTIVE) == 0) { 2648 radeonfb_engine_flush(sc); 2649 break; 2650 } 2651 } 2652 } 2653 2654 static void 2655 radeonfb_wait_fifo(struct radeonfb_softc *sc, int n) 2656 { 2657 int i; 2658 2659 for (i = RADEON_TIMEOUT; i; i--) { 2660 if ((GET32(sc, RADEON_RBBM_STATUS) & 2661 RADEON_RBBM_FIFOCNT_MASK) >= n) 2662 return; 2663 } 2664 #ifdef DIAGNOSTIC 2665 if (!i) 2666 printf("%s: timed out waiting for fifo (%x)\n", 2667 XNAME(sc), GET32(sc, RADEON_RBBM_STATUS)); 2668 #endif 2669 } 2670 2671 static void 2672 radeonfb_engine_flush(struct radeonfb_softc *sc) 2673 { 2674 int i; 2675 SET32(sc, RADEON_RB2D_DSTCACHE_CTLSTAT, RADEON_RB2D_DC_FLUSH_ALL); 2676 for (i = RADEON_TIMEOUT; i; i--) { 2677 if ((GET32(sc, RADEON_RB2D_DSTCACHE_CTLSTAT) & 2678 RADEON_RB2D_DC_BUSY) == 0) 2679 break; 2680 } 2681 #ifdef DIAGNOSTIC 2682 if (!i) 2683 printf("%s: engine flush timed out!\n", XNAME(sc)); 2684 #endif 2685 } 2686 2687 static inline void 2688 radeonfb_unclip(struct radeonfb_softc *sc) 2689 { 2690 2691 radeonfb_wait_fifo(sc, 2); 2692 PUT32(sc, RADEON_SC_TOP_LEFT, 0); 2693 PUT32(sc, RADEON_SC_BOTTOM_RIGHT, 0x1fff1fff); 2694 } 2695 2696 static void 2697 radeonfb_engine_init(struct radeonfb_display *dp) 2698 { 2699 struct radeonfb_softc *sc = dp->rd_softc; 2700 uint32_t pitch; 2701 2702 /* no 3D */ 2703 PUT32(sc, RADEON_RB3D_CNTL, 0); 2704 2705 radeonfb_engine_reset(sc); 2706 pitch = ((dp->rd_virtx * (dp->rd_bpp / 8) + 0x3f)) >> 6; 2707 //pitch = ((sc->sc_maxx * (sc->sc_maxbpp / 8) + 0x3f)) >> 6; 2708 2709 radeonfb_wait_fifo(sc, 1); 2710 if (!IS_R300(sc)) 2711 PUT32(sc, RADEON_RB2D_DSTCACHE_MODE, 0); 2712 2713 radeonfb_wait_fifo(sc, 3); 2714 PUT32(sc, RADEON_DEFAULT_PITCH_OFFSET, 2715 (pitch << 22) | (sc->sc_aperbase >> 10)); 2716 2717 2718 PUT32(sc, RADEON_DST_PITCH_OFFSET, 2719 (pitch << 22) | (sc->sc_aperbase >> 10)); 2720 PUT32(sc, RADEON_SRC_PITCH_OFFSET, 2721 (pitch << 22) | (sc->sc_aperbase >> 10)); 2722 2723 radeonfb_wait_fifo(sc, 1); 2724 #if _BYTE_ORDER == _BIG_ENDIAN 2725 SET32(sc, RADEON_DP_DATATYPE, RADEON_HOST_BIG_ENDIAN_EN); 2726 #else 2727 CLR32(sc, RADEON_DP_DATATYPE, RADEON_HOST_BIG_ENDIAN_EN); 2728 #endif 2729 2730 /* default scissors -- no clipping */ 2731 radeonfb_wait_fifo(sc, 1); 2732 PUT32(sc, RADEON_DEFAULT_SC_BOTTOM_RIGHT, 2733 RADEON_DEFAULT_SC_RIGHT_MAX | RADEON_DEFAULT_SC_BOTTOM_MAX); 2734 2735 radeonfb_wait_fifo(sc, 1); 2736 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 2737 (dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT) | 2738 RADEON_GMC_CLR_CMP_CNTL_DIS | 2739 RADEON_GMC_BRUSH_SOLID_COLOR | 2740 RADEON_GMC_SRC_DATATYPE_COLOR); 2741 2742 radeonfb_wait_fifo(sc, 7); 2743 PUT32(sc, RADEON_DST_LINE_START, 0); 2744 PUT32(sc, RADEON_DST_LINE_END, 0); 2745 PUT32(sc, RADEON_DP_BRUSH_FRGD_CLR, 0xffffffff); 2746 PUT32(sc, RADEON_DP_BRUSH_BKGD_CLR, 0); 2747 PUT32(sc, RADEON_DP_SRC_FRGD_CLR, 0xffffffff); 2748 PUT32(sc, RADEON_DP_SRC_BKGD_CLR, 0); 2749 PUT32(sc, RADEON_DP_WRITE_MASK, 0xffffffff); 2750 2751 radeonfb_engine_idle(sc); 2752 } 2753 2754 static void 2755 radeonfb_engine_reset(struct radeonfb_softc *sc) 2756 { 2757 uint32_t hpc, rbbm, mclkcntl, clkindex; 2758 2759 radeonfb_engine_flush(sc); 2760 2761 clkindex = GET32(sc, RADEON_CLOCK_CNTL_INDEX); 2762 if (HAS_R300CG(sc)) 2763 radeonfb_r300cg_workaround(sc); 2764 mclkcntl = GETPLL(sc, RADEON_MCLK_CNTL); 2765 2766 /* 2767 * According to comments in XFree code, resetting the HDP via 2768 * the RBBM_SOFT_RESET can cause bad behavior on some systems. 2769 * So we use HOST_PATH_CNTL instead. 2770 */ 2771 2772 hpc = GET32(sc, RADEON_HOST_PATH_CNTL); 2773 rbbm = GET32(sc, RADEON_RBBM_SOFT_RESET); 2774 if (IS_R300(sc)) { 2775 PUT32(sc, RADEON_RBBM_SOFT_RESET, rbbm | 2776 RADEON_SOFT_RESET_CP | 2777 RADEON_SOFT_RESET_HI | 2778 RADEON_SOFT_RESET_E2); 2779 GET32(sc, RADEON_RBBM_SOFT_RESET); 2780 PUT32(sc, RADEON_RBBM_SOFT_RESET, 0); 2781 /* 2782 * XXX: this bit is not defined in any ATI docs I have, 2783 * nor in the XFree code, but XFree does it. Why? 2784 */ 2785 SET32(sc, RADEON_RB2D_DSTCACHE_MODE, (1<<17)); 2786 } else { 2787 PUT32(sc, RADEON_RBBM_SOFT_RESET, rbbm | 2788 RADEON_SOFT_RESET_CP | 2789 RADEON_SOFT_RESET_SE | 2790 RADEON_SOFT_RESET_RE | 2791 RADEON_SOFT_RESET_PP | 2792 RADEON_SOFT_RESET_E2 | 2793 RADEON_SOFT_RESET_RB); 2794 GET32(sc, RADEON_RBBM_SOFT_RESET); 2795 PUT32(sc, RADEON_RBBM_SOFT_RESET, rbbm & 2796 ~(RADEON_SOFT_RESET_CP | 2797 RADEON_SOFT_RESET_SE | 2798 RADEON_SOFT_RESET_RE | 2799 RADEON_SOFT_RESET_PP | 2800 RADEON_SOFT_RESET_E2 | 2801 RADEON_SOFT_RESET_RB)); 2802 GET32(sc, RADEON_RBBM_SOFT_RESET); 2803 } 2804 2805 PUT32(sc, RADEON_HOST_PATH_CNTL, hpc | RADEON_HDP_SOFT_RESET); 2806 GET32(sc, RADEON_HOST_PATH_CNTL); 2807 PUT32(sc, RADEON_HOST_PATH_CNTL, hpc); 2808 2809 if (IS_R300(sc)) 2810 PUT32(sc, RADEON_RBBM_SOFT_RESET, rbbm); 2811 2812 PUT32(sc, RADEON_CLOCK_CNTL_INDEX, clkindex); 2813 PUTPLL(sc, RADEON_MCLK_CNTL, mclkcntl); 2814 2815 if (HAS_R300CG(sc)) 2816 radeonfb_r300cg_workaround(sc); 2817 } 2818 2819 static int 2820 radeonfb_set_curpos(struct radeonfb_display *dp, struct wsdisplay_curpos *pos) 2821 { 2822 int x, y; 2823 2824 x = pos->x; 2825 y = pos->y; 2826 2827 /* 2828 * This doesn't let a cursor move off the screen. I'm not 2829 * sure if this will have negative effects for e.g. Xinerama. 2830 * I'd guess Xinerama handles it by changing the cursor shape, 2831 * but that needs verification. 2832 */ 2833 if (x >= dp->rd_virtx) 2834 x = dp->rd_virtx - 1; 2835 if (x < 0) 2836 x = 0; 2837 if (y >= dp->rd_virty) 2838 y = dp->rd_virty - 1; 2839 if (y < 0) 2840 y = 0; 2841 2842 dp->rd_cursor.rc_pos.x = x; 2843 dp->rd_cursor.rc_pos.y = y; 2844 2845 radeonfb_cursor_position(dp); 2846 return 0; 2847 } 2848 2849 static int 2850 radeonfb_set_cursor(struct radeonfb_display *dp, struct wsdisplay_cursor *wc) 2851 { 2852 unsigned flags; 2853 2854 uint8_t r[2], g[2], b[2]; 2855 unsigned index, count; 2856 int i, err; 2857 int pitch, size; 2858 struct radeonfb_cursor nc; 2859 2860 flags = wc->which; 2861 2862 /* copy old values */ 2863 nc = dp->rd_cursor; 2864 2865 if (flags & WSDISPLAY_CURSOR_DOCMAP) { 2866 index = wc->cmap.index; 2867 count = wc->cmap.count; 2868 2869 if (index >= 2 || (index + count) > 2) 2870 return EINVAL; 2871 2872 err = copyin(wc->cmap.red, &r[index], count); 2873 if (err) 2874 return err; 2875 err = copyin(wc->cmap.green, &g[index], count); 2876 if (err) 2877 return err; 2878 err = copyin(wc->cmap.blue, &b[index], count); 2879 if (err) 2880 return err; 2881 2882 for (i = index; i < index + count; i++) { 2883 nc.rc_cmap[i] = 2884 (r[i] << 16) + (g[i] << 8) + (b[i] << 0); 2885 } 2886 } 2887 2888 if (flags & WSDISPLAY_CURSOR_DOSHAPE) { 2889 if ((wc->size.x > RADEON_CURSORMAXX) || 2890 (wc->size.y > RADEON_CURSORMAXY)) 2891 return EINVAL; 2892 2893 /* figure bytes per line */ 2894 pitch = (wc->size.x + 7) / 8; 2895 size = pitch * wc->size.y; 2896 2897 /* clear the old cursor and mask */ 2898 memset(nc.rc_image, 0, 512); 2899 memset(nc.rc_mask, 0, 512); 2900 2901 nc.rc_size = wc->size; 2902 2903 if ((err = copyin(wc->image, nc.rc_image, size)) != 0) 2904 return err; 2905 2906 if ((err = copyin(wc->mask, nc.rc_mask, size)) != 0) 2907 return err; 2908 } 2909 2910 if (flags & WSDISPLAY_CURSOR_DOHOT) { 2911 nc.rc_hot = wc->hot; 2912 if (nc.rc_hot.x >= nc.rc_size.x) 2913 nc.rc_hot.x = nc.rc_size.x - 1; 2914 if (nc.rc_hot.y >= nc.rc_size.y) 2915 nc.rc_hot.y = nc.rc_size.y - 1; 2916 } 2917 2918 if (flags & WSDISPLAY_CURSOR_DOPOS) { 2919 nc.rc_pos = wc->pos; 2920 if (nc.rc_pos.x >= dp->rd_virtx) 2921 nc.rc_pos.x = dp->rd_virtx - 1; 2922 #if 0 2923 if (nc.rc_pos.x < 0) 2924 nc.rc_pos.x = 0; 2925 #endif 2926 if (nc.rc_pos.y >= dp->rd_virty) 2927 nc.rc_pos.y = dp->rd_virty - 1; 2928 #if 0 2929 if (nc.rc_pos.y < 0) 2930 nc.rc_pos.y = 0; 2931 #endif 2932 } 2933 if (flags & WSDISPLAY_CURSOR_DOCUR) { 2934 nc.rc_visible = wc->enable; 2935 } 2936 2937 dp->rd_cursor = nc; 2938 radeonfb_cursor_update(dp, wc->which); 2939 2940 return 0; 2941 } 2942 2943 /* 2944 * Change the cursor shape. Call this with the cursor locked to avoid 2945 * flickering/tearing. 2946 */ 2947 static void 2948 radeonfb_cursor_shape(struct radeonfb_display *dp) 2949 { 2950 uint8_t and[512], xor[512]; 2951 int i, j, src, dst, pitch; 2952 const uint8_t *msk = dp->rd_cursor.rc_mask; 2953 const uint8_t *img = dp->rd_cursor.rc_image; 2954 2955 /* 2956 * Radeon cursor data interleaves one line of AND data followed 2957 * by a line of XOR data. (Each line corresponds to a whole hardware 2958 * pitch - i.e. 64 pixels or 8 bytes.) 2959 * 2960 * The cursor is displayed using the following table: 2961 * 2962 * AND XOR Result 2963 * ---------------------- 2964 * 0 0 Cursor color 0 2965 * 0 1 Cursor color 1 2966 * 1 0 Transparent 2967 * 1 1 Complement of background 2968 * 2969 * Our masks are therefore different from what we were passed. 2970 * Passed in, I'm assuming the data represents either color 0 or 1, 2971 * and a mask, so the passed in table looks like: 2972 * 2973 * IMG Mask Result 2974 * ----------------------- 2975 * 0 0 Transparent 2976 * 0 1 Cursor color 0 2977 * 1 0 Transparent 2978 * 1 1 Cursor color 1 2979 * 2980 * IF mask bit == 1, AND = 0, XOR = color. 2981 * IF mask bit == 0, AND = 1, XOR = 0. 2982 * 2983 * hence: AND = ~(mask); XOR = color & ~(mask); 2984 */ 2985 2986 pitch = ((dp->rd_cursor.rc_size.x + 7) / 8); 2987 2988 /* start by assuming all bits are transparent */ 2989 memset(and, 0xff, 512); 2990 memset(xor, 0x00, 512); 2991 2992 src = 0; 2993 dst = 0; 2994 for (i = 0; i < 64; i++) { 2995 for (j = 0; j < 64; j += 8) { 2996 if ((i < dp->rd_cursor.rc_size.y) && 2997 (j < dp->rd_cursor.rc_size.x)) { 2998 2999 /* take care to leave odd bits alone */ 3000 and[dst] &= ~(msk[src]); 3001 xor[dst] = img[src] & msk[src]; 3002 src++; 3003 } 3004 dst++; 3005 } 3006 } 3007 3008 /* copy the image into place */ 3009 for (i = 0; i < 64; i++) { 3010 memcpy((uint8_t *)dp->rd_curptr + (i * 16), 3011 &and[i * 8], 8); 3012 memcpy((uint8_t *)dp->rd_curptr + (i * 16) + 8, 3013 &xor[i * 8], 8); 3014 } 3015 } 3016 3017 static void 3018 radeonfb_cursor_position(struct radeonfb_display *dp) 3019 { 3020 struct radeonfb_softc *sc = dp->rd_softc; 3021 uint32_t offset, hvoff, hvpos; /* registers */ 3022 uint32_t coff; /* cursor offset */ 3023 int i, x, y, xoff, yoff, crtcoff; 3024 3025 /* 3026 * XXX: this also needs to handle pan/scan 3027 */ 3028 for (i = 0; i < dp->rd_ncrtcs; i++) { 3029 3030 struct radeonfb_crtc *rcp = &dp->rd_crtcs[i]; 3031 3032 if (rcp->rc_number) { 3033 offset = RADEON_CUR2_OFFSET; 3034 hvoff = RADEON_CUR2_HORZ_VERT_OFF; 3035 hvpos = RADEON_CUR2_HORZ_VERT_POSN; 3036 crtcoff = RADEON_CRTC2_OFFSET; 3037 } else { 3038 offset = RADEON_CUR_OFFSET; 3039 hvoff = RADEON_CUR_HORZ_VERT_OFF; 3040 hvpos = RADEON_CUR_HORZ_VERT_POSN; 3041 crtcoff = RADEON_CRTC_OFFSET; 3042 } 3043 3044 x = dp->rd_cursor.rc_pos.x; 3045 y = dp->rd_cursor.rc_pos.y; 3046 3047 while (y < rcp->rc_yoffset) { 3048 rcp->rc_yoffset -= RADEON_PANINCREMENT; 3049 } 3050 while (y >= (rcp->rc_yoffset + rcp->rc_videomode.vdisplay)) { 3051 rcp->rc_yoffset += RADEON_PANINCREMENT; 3052 } 3053 while (x < rcp->rc_xoffset) { 3054 rcp->rc_xoffset -= RADEON_PANINCREMENT; 3055 } 3056 while (x >= (rcp->rc_xoffset + rcp->rc_videomode.hdisplay)) { 3057 rcp->rc_xoffset += RADEON_PANINCREMENT; 3058 } 3059 3060 /* adjust for the cursor's hotspot */ 3061 x -= dp->rd_cursor.rc_hot.x; 3062 y -= dp->rd_cursor.rc_hot.y; 3063 xoff = yoff = 0; 3064 3065 if (x >= dp->rd_virtx) 3066 x = dp->rd_virtx - 1; 3067 if (y >= dp->rd_virty) 3068 y = dp->rd_virty - 1; 3069 3070 /* now adjust cursor so it is relative to viewport */ 3071 x -= rcp->rc_xoffset; 3072 y -= rcp->rc_yoffset; 3073 3074 /* 3075 * no need to check for fall off, because we should 3076 * never move off the screen entirely! 3077 */ 3078 coff = 0; 3079 if (x < 0) { 3080 xoff = -x; 3081 x = 0; 3082 } 3083 if (y < 0) { 3084 yoff = -y; 3085 y = 0; 3086 coff = (yoff * 2) * 8; 3087 } 3088 3089 /* pan the display */ 3090 PUT32(sc, crtcoff, (rcp->rc_yoffset * dp->rd_stride) + 3091 rcp->rc_xoffset); 3092 3093 PUT32(sc, offset, (dp->rd_curoff + coff) | RADEON_CUR_LOCK); 3094 PUT32(sc, hvoff, (xoff << 16) | (yoff) | RADEON_CUR_LOCK); 3095 /* NB: this unlocks the cursor */ 3096 PUT32(sc, hvpos, (x << 16) | y); 3097 } 3098 } 3099 3100 static void 3101 radeonfb_cursor_visible(struct radeonfb_display *dp) 3102 { 3103 int i; 3104 uint32_t gencntl, bit; 3105 3106 for (i = 0; i < dp->rd_ncrtcs; i++) { 3107 if (dp->rd_crtcs[i].rc_number) { 3108 gencntl = RADEON_CRTC2_GEN_CNTL; 3109 bit = RADEON_CRTC2_CUR_EN; 3110 } else { 3111 gencntl = RADEON_CRTC_GEN_CNTL; 3112 bit = RADEON_CRTC_CUR_EN; 3113 } 3114 3115 if (dp->rd_cursor.rc_visible) 3116 SET32(dp->rd_softc, gencntl, bit); 3117 else 3118 CLR32(dp->rd_softc, gencntl, bit); 3119 } 3120 } 3121 3122 static void 3123 radeonfb_cursor_cmap(struct radeonfb_display *dp) 3124 { 3125 int i; 3126 uint32_t c0reg, c1reg; 3127 struct radeonfb_softc *sc = dp->rd_softc; 3128 3129 for (i = 0; i < dp->rd_ncrtcs; i++) { 3130 if (dp->rd_crtcs[i].rc_number) { 3131 c0reg = RADEON_CUR2_CLR0; 3132 c1reg = RADEON_CUR2_CLR1; 3133 } else { 3134 c0reg = RADEON_CUR_CLR0; 3135 c1reg = RADEON_CUR_CLR1; 3136 } 3137 3138 PUT32(sc, c0reg, dp->rd_cursor.rc_cmap[0]); 3139 PUT32(sc, c1reg, dp->rd_cursor.rc_cmap[1]); 3140 } 3141 } 3142 3143 static void 3144 radeonfb_cursor_update(struct radeonfb_display *dp, unsigned which) 3145 { 3146 struct radeonfb_softc *sc; 3147 int i; 3148 3149 sc = dp->rd_softc; 3150 for (i = 0; i < dp->rd_ncrtcs; i++) { 3151 if (dp->rd_crtcs[i].rc_number) { 3152 SET32(sc, RADEON_CUR2_OFFSET, RADEON_CUR_LOCK); 3153 } else { 3154 SET32(sc, RADEON_CUR_OFFSET,RADEON_CUR_LOCK); 3155 } 3156 } 3157 3158 if (which & WSDISPLAY_CURSOR_DOCMAP) 3159 radeonfb_cursor_cmap(dp); 3160 3161 if (which & WSDISPLAY_CURSOR_DOSHAPE) 3162 radeonfb_cursor_shape(dp); 3163 3164 if (which & WSDISPLAY_CURSOR_DOCUR) 3165 radeonfb_cursor_visible(dp); 3166 3167 /* this one is unconditional, because it updates other stuff */ 3168 radeonfb_cursor_position(dp); 3169 } 3170 3171 static struct videomode * 3172 radeonfb_best_refresh(struct videomode *m1, struct videomode *m2) 3173 { 3174 int r1, r2; 3175 3176 /* otherwise pick the higher refresh rate */ 3177 r1 = DIVIDE(DIVIDE(m1->dot_clock, m1->htotal), m1->vtotal); 3178 r2 = DIVIDE(DIVIDE(m2->dot_clock, m2->htotal), m2->vtotal); 3179 3180 return (r1 < r2 ? m2 : m1); 3181 } 3182 3183 static const struct videomode * 3184 radeonfb_port_mode(struct radeonfb_softc *sc, struct radeonfb_port *rp, 3185 int x, int y) 3186 { 3187 struct edid_info *ep = &rp->rp_edid; 3188 struct videomode *vmp = NULL; 3189 int i; 3190 3191 if (!rp->rp_edid_valid) { 3192 /* fallback to safe mode */ 3193 return radeonfb_modelookup(sc->sc_defaultmode); 3194 } 3195 3196 /* always choose the preferred mode first! */ 3197 if (ep->edid_preferred_mode) { 3198 3199 /* XXX: add auto-stretching support for native mode */ 3200 3201 /* this may want panning to occur, btw */ 3202 if ((ep->edid_preferred_mode->hdisplay <= x) && 3203 (ep->edid_preferred_mode->vdisplay <= y)) 3204 return ep->edid_preferred_mode; 3205 } 3206 3207 for (i = 0; i < ep->edid_nmodes; i++) { 3208 /* 3209 * We elect to pick a resolution that is too large for 3210 * the monitor than one that is too small. This means 3211 * that we will prefer to pan rather than to try to 3212 * center a smaller display on a larger screen. In 3213 * practice, this shouldn't matter because if a 3214 * monitor can support a larger resolution, it can 3215 * probably also support the smaller. A specific 3216 * exception is fixed format panels, but hopefully 3217 * they are properly dealt with by the "autostretch" 3218 * logic above. 3219 */ 3220 if ((ep->edid_modes[i].hdisplay > x) || 3221 (ep->edid_modes[i].vdisplay > y)) { 3222 continue; 3223 } 3224 3225 /* 3226 * at this point, the display mode is no larger than 3227 * what we've requested. 3228 */ 3229 if (vmp == NULL) 3230 vmp = &ep->edid_modes[i]; 3231 3232 /* eliminate smaller modes */ 3233 if ((vmp->hdisplay >= ep->edid_modes[i].hdisplay) || 3234 (vmp->vdisplay >= ep->edid_modes[i].vdisplay)) 3235 continue; 3236 3237 if ((vmp->hdisplay < ep->edid_modes[i].hdisplay) || 3238 (vmp->vdisplay < ep->edid_modes[i].vdisplay)) { 3239 vmp = &ep->edid_modes[i]; 3240 continue; 3241 } 3242 3243 KASSERT(vmp->hdisplay == ep->edid_modes[i].hdisplay); 3244 KASSERT(vmp->vdisplay == ep->edid_modes[i].vdisplay); 3245 3246 vmp = radeonfb_best_refresh(vmp, &ep->edid_modes[i]); 3247 } 3248 3249 return (vmp ? vmp : radeonfb_modelookup(sc->sc_defaultmode)); 3250 } 3251 3252 static int 3253 radeonfb_hasres(struct videomode *list, int nlist, int x, int y) 3254 { 3255 int i; 3256 3257 for (i = 0; i < nlist; i++) { 3258 if ((x == list[i].hdisplay) && 3259 (y == list[i].vdisplay)) { 3260 return 1; 3261 } 3262 } 3263 return 0; 3264 } 3265 3266 static void 3267 radeonfb_pickres(struct radeonfb_display *dp, uint16_t *x, uint16_t *y, 3268 int pan) 3269 { 3270 struct radeonfb_port *rp; 3271 struct edid_info *ep; 3272 int i, j; 3273 3274 *x = 0; 3275 *y = 0; 3276 3277 if (pan) { 3278 for (i = 0; i < dp->rd_ncrtcs; i++) { 3279 rp = dp->rd_crtcs[i].rc_port; 3280 ep = &rp->rp_edid; 3281 if (!rp->rp_edid_valid) { 3282 /* monitor not present */ 3283 continue; 3284 } 3285 3286 /* 3287 * For now we are ignoring "conflict" that 3288 * could occur when mixing some modes like 3289 * 1280x1024 and 1400x800. It isn't clear 3290 * which is better, so the first one wins. 3291 */ 3292 for (j = 0; j < ep->edid_nmodes; j++) { 3293 /* 3294 * ignore resolutions that are too big for 3295 * the radeon 3296 */ 3297 if (ep->edid_modes[j].hdisplay > 3298 dp->rd_softc->sc_maxx) 3299 continue; 3300 if (ep->edid_modes[j].vdisplay > 3301 dp->rd_softc->sc_maxy) 3302 continue; 3303 3304 /* 3305 * pick largest resolution, the 3306 * smaller monitor will pan 3307 */ 3308 if ((ep->edid_modes[j].hdisplay >= *x) && 3309 (ep->edid_modes[j].vdisplay >= *y)) { 3310 *x = ep->edid_modes[j].hdisplay; 3311 *y = ep->edid_modes[j].vdisplay; 3312 } 3313 } 3314 } 3315 3316 } else { 3317 struct videomode modes[64]; 3318 int nmodes = 0; 3319 int valid = 0; 3320 3321 for (i = 0; i < dp->rd_ncrtcs; i++) { 3322 /* 3323 * pick the largest resolution in common. 3324 */ 3325 rp = dp->rd_crtcs[i].rc_port; 3326 ep = &rp->rp_edid; 3327 3328 if (!rp->rp_edid_valid) 3329 continue; 3330 3331 if (!valid) { 3332 /* initialize starting list */ 3333 for (j = 0; j < ep->edid_nmodes; j++) { 3334 /* 3335 * ignore resolutions that are 3336 * too big for the radeon 3337 */ 3338 if (ep->edid_modes[j].hdisplay > 3339 dp->rd_softc->sc_maxx) 3340 continue; 3341 if (ep->edid_modes[j].vdisplay > 3342 dp->rd_softc->sc_maxy) 3343 continue; 3344 3345 modes[nmodes] = ep->edid_modes[j]; 3346 nmodes++; 3347 } 3348 valid = 1; 3349 } else { 3350 /* merge into preexisting list */ 3351 for (j = 0; j < nmodes; j++) { 3352 if (!radeonfb_hasres(ep->edid_modes, 3353 ep->edid_nmodes, 3354 modes[j].hdisplay, 3355 modes[j].vdisplay)) { 3356 modes[j] = modes[nmodes]; 3357 j--; 3358 nmodes--; 3359 } 3360 } 3361 } 3362 } 3363 3364 /* now we have to pick from the merged list */ 3365 for (i = 0; i < nmodes; i++) { 3366 if ((modes[i].hdisplay >= *x) && 3367 (modes[i].vdisplay >= *y)) { 3368 *x = modes[i].hdisplay; 3369 *y = modes[i].vdisplay; 3370 } 3371 } 3372 } 3373 3374 if ((*x == 0) || (*y == 0)) { 3375 /* fallback to safe mode */ 3376 *x = 640; 3377 *y = 480; 3378 } 3379 } 3380 3381 /* 3382 * backlight levels are linear on: 3383 * - RV200, RV250, RV280, RV350 3384 * - but NOT on PowerBook4,3 6,3 6,5 3385 * according to Linux' radeonfb 3386 */ 3387 3388 /* Get the current backlight level for the display. */ 3389 3390 static int 3391 radeonfb_get_backlight(struct radeonfb_display *dp) 3392 { 3393 int s; 3394 uint32_t level; 3395 3396 s = spltty(); 3397 3398 level = radeonfb_get32(dp->rd_softc, RADEON_LVDS_GEN_CNTL); 3399 level &= RADEON_LVDS_BL_MOD_LEV_MASK; 3400 level >>= RADEON_LVDS_BL_MOD_LEV_SHIFT; 3401 3402 /* 3403 * On some chips, we should negate the backlight level. 3404 * XXX Find out on which chips. 3405 */ 3406 if (dp->rd_softc->sc_flags & RFB_INV_BLIGHT) 3407 level = RADEONFB_BACKLIGHT_MAX - level; 3408 3409 splx(s); 3410 3411 return level; 3412 } 3413 3414 /* Set the backlight to the given level for the display. */ 3415 3416 static int 3417 radeonfb_set_backlight(struct radeonfb_display *dp, int level) 3418 { 3419 struct radeonfb_softc *sc; 3420 int rlevel, s; 3421 uint32_t lvds; 3422 3423 s = spltty(); 3424 3425 if (level < 0) 3426 level = 0; 3427 else if (level >= RADEONFB_BACKLIGHT_MAX) 3428 level = RADEONFB_BACKLIGHT_MAX; 3429 3430 sc = dp->rd_softc; 3431 3432 /* On some chips, we should negate the backlight level. */ 3433 if (dp->rd_softc->sc_flags & RFB_INV_BLIGHT) { 3434 rlevel = RADEONFB_BACKLIGHT_MAX - level; 3435 } else 3436 rlevel = level; 3437 3438 callout_stop(&dp->rd_bl_lvds_co); 3439 radeonfb_engine_idle(sc); 3440 3441 /* 3442 * Turn off the display if the backlight is set to 0, since the 3443 * display is useless without backlight anyway. 3444 */ 3445 if (level == 0) 3446 radeonfb_blank(dp, 1); 3447 else if (radeonfb_get_backlight(dp) == 0) 3448 radeonfb_blank(dp, 0); 3449 3450 lvds = radeonfb_get32(sc, RADEON_LVDS_GEN_CNTL); 3451 lvds &= ~RADEON_LVDS_DISPLAY_DIS; 3452 if (!(lvds & RADEON_LVDS_BLON) || !(lvds & RADEON_LVDS_ON)) { 3453 lvds |= dp->rd_bl_lvds_val & RADEON_LVDS_DIGON; 3454 lvds |= RADEON_LVDS_BLON | RADEON_LVDS_EN; 3455 radeonfb_put32(sc, RADEON_LVDS_GEN_CNTL, lvds); 3456 lvds &= ~RADEON_LVDS_BL_MOD_LEV_MASK; 3457 lvds |= rlevel << RADEON_LVDS_BL_MOD_LEV_SHIFT; 3458 lvds |= RADEON_LVDS_ON; 3459 lvds |= dp->rd_bl_lvds_val & RADEON_LVDS_BL_MOD_EN; 3460 } else { 3461 lvds &= ~RADEON_LVDS_BL_MOD_LEV_MASK; 3462 lvds |= rlevel << RADEON_LVDS_BL_MOD_LEV_SHIFT; 3463 radeonfb_put32(sc, RADEON_LVDS_GEN_CNTL, lvds); 3464 } 3465 3466 dp->rd_bl_lvds_val &= ~RADEON_LVDS_STATE_MASK; 3467 dp->rd_bl_lvds_val |= lvds & RADEON_LVDS_STATE_MASK; 3468 /* XXX What is the correct delay? */ 3469 callout_schedule(&dp->rd_bl_lvds_co, 200 * hz); 3470 3471 splx(s); 3472 3473 return 0; 3474 } 3475 3476 /* 3477 * Callout function for delayed operations on the LVDS_GEN_CNTL register. 3478 * Set the delayed bits in the register, and clear the stored delayed 3479 * value. 3480 */ 3481 3482 static void radeonfb_lvds_callout(void *arg) 3483 { 3484 struct radeonfb_display *dp = arg; 3485 int s; 3486 3487 s = splhigh(); 3488 3489 radeonfb_mask32(dp->rd_softc, RADEON_LVDS_GEN_CNTL, ~0, 3490 dp->rd_bl_lvds_val); 3491 dp->rd_bl_lvds_val = 0; 3492 3493 splx(s); 3494 } 3495
Indexes created Fri Oct 17 00:09:41 GMT 2025