radeonfb.c revision 1.20
1 /* $NetBSD: radeonfb.c,v 1.20 2007/09/03 02:45:06 macallan Exp $ */ 2 3 /*- 4 * Copyright (c) 2006 Itronix Inc. 5 * All rights reserved. 6 * 7 * Written by Garrett D'Amore for Itronix Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. The name of Itronix Inc. may not be used to endorse 18 * or promote products derived from this software without specific 19 * prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY ITRONIX INC. ``AS IS'' AND ANY EXPRESS 22 * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 23 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL ITRONIX INC. BE LIABLE FOR ANY 25 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE 27 * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 29 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 30 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 31 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * ATI Technologies Inc. ("ATI") has not assisted in the creation of, and 36 * does not endorse, this software. ATI will not be responsible or liable 37 * for any actual or alleged damage or loss caused by or in connection with 38 * the use of or reliance on this software. 39 */ 40 41 /* 42 * Portions of this code were taken from XFree86's Radeon driver, which bears 43 * this notice: 44 * 45 * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and 46 * VA Linux Systems Inc., Fremont, California. 47 * 48 * All Rights Reserved. 49 * 50 * Permission is hereby granted, free of charge, to any person obtaining 51 * a copy of this software and associated documentation files (the 52 * "Software"), to deal in the Software without restriction, including 53 * without limitation on the rights to use, copy, modify, merge, 54 * publish, distribute, sublicense, and/or sell copies of the Software, 55 * and to permit persons to whom the Software is furnished to do so, 56 * subject to the following conditions: 57 * 58 * The above copyright notice and this permission notice (including the 59 * next paragraph) shall be included in all copies or substantial 60 * portions of the Software. 61 * 62 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 63 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 64 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 65 * NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR 66 * THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 67 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 68 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 69 * DEALINGS IN THE SOFTWARE. 70 */ 71 72 #include <sys/cdefs.h> 73 __KERNEL_RCSID(0, "$NetBSD: radeonfb.c,v 1.20 2007/09/03 02:45:06 macallan Exp $"); 74 75 #define RADEONFB_DEFAULT_DEPTH 32 76 77 #include <sys/param.h> 78 #include <sys/systm.h> 79 #include <sys/device.h> 80 #include <sys/malloc.h> 81 #include <machine/bus.h> 82 #include <sys/kernel.h> 83 #include <sys/lwp.h> 84 #include <sys/kauth.h> 85 86 #include <dev/wscons/wsdisplayvar.h> 87 #include <dev/wscons/wsconsio.h> 88 #include <dev/wsfont/wsfont.h> 89 #include <dev/rasops/rasops.h> 90 #include <dev/videomode/videomode.h> 91 #include <dev/videomode/edidvar.h> 92 #include <dev/wscons/wsdisplay_vconsvar.h> 93 94 #include <dev/pci/pcidevs.h> 95 #include <dev/pci/pcireg.h> 96 #include <dev/pci/pcivar.h> 97 #include <dev/pci/radeonfbreg.h> 98 #include <dev/pci/radeonfbvar.h> 99 #include "opt_radeonfb.h" 100 101 static int radeonfb_match(struct device *, struct cfdata *, void *); 102 static void radeonfb_attach(struct device *, struct device *, void *); 103 static int radeonfb_ioctl(void *, void *, unsigned long, void *, int, 104 struct lwp *); 105 static paddr_t radeonfb_mmap(void *, void *, off_t, int); 106 static int radeonfb_scratch_test(struct radeonfb_softc *, int, uint32_t); 107 static void radeonfb_loadbios(struct radeonfb_softc *, 108 struct pci_attach_args *); 109 110 static uintmax_t radeonfb_getprop_num(struct radeonfb_softc *, const char *, 111 uintmax_t); 112 static int radeonfb_getclocks(struct radeonfb_softc *); 113 static int radeonfb_gettmds(struct radeonfb_softc *); 114 static int radeonfb_calc_dividers(struct radeonfb_softc *, uint32_t, 115 uint32_t *, uint32_t *); 116 static int radeonfb_getconnectors(struct radeonfb_softc *); 117 static const struct videomode *radeonfb_modelookup(const char *); 118 static void radeonfb_init_screen(void *, struct vcons_screen *, int, long *); 119 static void radeonfb_pllwriteupdate(struct radeonfb_softc *, int); 120 static void radeonfb_pllwaitatomicread(struct radeonfb_softc *, int); 121 static void radeonfb_program_vclk(struct radeonfb_softc *, int, int); 122 static void radeonfb_modeswitch(struct radeonfb_display *); 123 static void radeonfb_setcrtc(struct radeonfb_display *, int); 124 static void radeonfb_init_misc(struct radeonfb_softc *); 125 static void radeonfb_set_fbloc(struct radeonfb_softc *); 126 static void radeonfb_init_palette(struct radeonfb_softc *, int); 127 static void radeonfb_r300cg_workaround(struct radeonfb_softc *); 128 129 static int radeonfb_isblank(struct radeonfb_display *); 130 static void radeonfb_blank(struct radeonfb_display *, int); 131 static int radeonfb_set_cursor(struct radeonfb_display *, 132 struct wsdisplay_cursor *); 133 static int radeonfb_set_curpos(struct radeonfb_display *, 134 struct wsdisplay_curpos *); 135 136 /* acceleration support */ 137 static void radeonfb_rectfill(struct radeonfb_display *, int dstx, int dsty, 138 int width, int height, uint32_t color); 139 static void radeonfb_bitblt(struct radeonfb_display *, int srcx, int srcy, 140 int dstx, int dsty, int width, int height, int rop, uint32_t mask); 141 static void radeonfb_feed_bytes(struct radeonfb_display *, int, uint8_t *); 142 static void radeonfb_setup_mono(struct radeonfb_display *, int, int, int, 143 int, uint32_t, uint32_t); 144 145 /* hw cursor support */ 146 static void radeonfb_cursor_cmap(struct radeonfb_display *); 147 static void radeonfb_cursor_shape(struct radeonfb_display *); 148 static void radeonfb_cursor_position(struct radeonfb_display *); 149 static void radeonfb_cursor_visible(struct radeonfb_display *); 150 static void radeonfb_cursor_update(struct radeonfb_display *, unsigned); 151 152 static void radeonfb_wait_fifo(struct radeonfb_softc *, int); 153 static void radeonfb_engine_idle(struct radeonfb_softc *); 154 static void radeonfb_engine_flush(struct radeonfb_softc *); 155 static void radeonfb_engine_reset(struct radeonfb_softc *); 156 static void radeonfb_engine_init(struct radeonfb_display *); 157 static inline void radeonfb_unclip(struct radeonfb_softc *); 158 159 static void radeonfb_eraserows(void *, int, int, long); 160 static void radeonfb_erasecols(void *, int, int, int, long); 161 static void radeonfb_copyrows(void *, int, int, int); 162 static void radeonfb_copycols(void *, int, int, int, int); 163 static void radeonfb_cursor(void *, int, int, int); 164 static void radeonfb_putchar(void *, int, int, unsigned, long); 165 static int radeonfb_allocattr(void *, int, int, int, long *); 166 167 static int radeonfb_get_backlight(struct radeonfb_display *); 168 static int radeonfb_set_backlight(struct radeonfb_display *, int); 169 static void radeonfb_lvds_callout(void *); 170 171 static struct videomode *radeonfb_best_refresh(struct videomode *, 172 struct videomode *); 173 static void radeonfb_pickres(struct radeonfb_display *, uint16_t *, 174 uint16_t *, int); 175 static const struct videomode *radeonfb_port_mode(struct radeonfb_softc *, 176 struct radeonfb_port *, int, int); 177 178 static int radeonfb_drm_print(void *, const char *); 179 180 #ifdef RADEON_DEBUG 181 int radeon_debug = 1; 182 #define DPRINTF(x) \ 183 if (radeon_debug) printf x 184 #define PRINTREG(r) DPRINTF((#r " = %08x\n", GET32(sc, r))) 185 #define PRINTPLL(r) DPRINTF((#r " = %08x\n", GETPLL(sc, r))) 186 #else 187 #define DPRINTF(x) 188 #define PRINTREG(r) 189 #define PRINTPLL(r) 190 #endif 191 192 #define ROUNDUP(x,y) (((x) + ((y) - 1)) & ~((y) - 1)) 193 194 #ifndef RADEON_DEFAULT_MODE 195 /* any reasonably modern display should handle this */ 196 #define RADEON_DEFAULT_MODE "1024x768x60" 197 #endif 198 199 const char *radeonfb_default_mode = RADEON_DEFAULT_MODE; 200 201 static struct { 202 int size; /* minimum memory size (MB) */ 203 int maxx; /* maximum x dimension */ 204 int maxy; /* maximum y dimension */ 205 int maxbpp; /* maximum bpp */ 206 int maxdisp; /* maximum logical display count */ 207 } radeonfb_limits[] = { 208 { 32, 2048, 1536, 32, 2 }, 209 { 16, 1600, 1200, 32, 2 }, 210 { 8, 1600, 1200, 32, 1 }, 211 { 0, 0, 0, 0, 0 }, 212 }; 213 214 static struct wsscreen_descr radeonfb_stdscreen = { 215 "fb", /* name */ 216 0, 0, /* ncols, nrows */ 217 NULL, /* textops */ 218 8, 16, /* fontwidth, fontheight */ 219 WSSCREEN_WSCOLORS, /* capabilities */ 220 0, /* modecookie */ 221 }; 222 223 struct wsdisplay_accessops radeonfb_accessops = { 224 radeonfb_ioctl, 225 radeonfb_mmap, 226 NULL, /* vcons_alloc_screen */ 227 NULL, /* vcons_free_screen */ 228 NULL, /* vcons_show_screen */ 229 NULL, /* load_font */ 230 NULL, /* pollc */ 231 NULL, /* scroll */ 232 }; 233 234 static struct { 235 uint16_t devid; 236 uint16_t family; 237 uint16_t flags; 238 } radeonfb_devices[] = 239 { 240 /* R100 family */ 241 { PCI_PRODUCT_ATI_RADEON_R100_QD, RADEON_R100, 0 }, 242 { PCI_PRODUCT_ATI_RADEON_R100_QE, RADEON_R100, 0 }, 243 { PCI_PRODUCT_ATI_RADEON_R100_QF, RADEON_R100, 0 }, 244 { PCI_PRODUCT_ATI_RADEON_R100_QG, RADEON_R100, 0 }, 245 246 /* RV100 family */ 247 { PCI_PRODUCT_ATI_RADEON_RV100_LY, RADEON_RV100, RFB_MOB }, 248 { PCI_PRODUCT_ATI_RADEON_RV100_LZ, RADEON_RV100, RFB_MOB }, 249 { PCI_PRODUCT_ATI_RADEON_RV100_QY, RADEON_RV100, 0 }, 250 { PCI_PRODUCT_ATI_RADEON_RV100_QZ, RADEON_RV100, 0 }, 251 252 /* RS100 family */ 253 { PCI_PRODUCT_ATI_RADEON_RS100_4136, RADEON_RS100, 0 }, 254 { PCI_PRODUCT_ATI_RADEON_RS100_4336, RADEON_RS100, RFB_MOB }, 255 256 /* RS200/RS250 family */ 257 { PCI_PRODUCT_ATI_RADEON_RS200_4337, RADEON_RS200, RFB_MOB }, 258 { PCI_PRODUCT_ATI_RADEON_RS200_A7, RADEON_RS200, 0 }, 259 { PCI_PRODUCT_ATI_RADEON_RS250_B7, RADEON_RS200, RFB_MOB }, 260 { PCI_PRODUCT_ATI_RADEON_RS250_D7, RADEON_RS200, 0 }, 261 262 /* R200 family */ 263 /* add more R200 products? , 5148 */ 264 { PCI_PRODUCT_ATI_RADEON_R200_BB, RADEON_R200, 0 }, 265 { PCI_PRODUCT_ATI_RADEON_R200_BC, RADEON_R200, 0 }, 266 { PCI_PRODUCT_ATI_RADEON_R200_QH, RADEON_R200, 0 }, 267 { PCI_PRODUCT_ATI_RADEON_R200_QL, RADEON_R200, 0 }, 268 { PCI_PRODUCT_ATI_RADEON_R200_QM, RADEON_R200, 0 }, 269 270 /* RV200 family */ 271 { PCI_PRODUCT_ATI_RADEON_RV200_LW, RADEON_RV200, RFB_MOB }, 272 { PCI_PRODUCT_ATI_RADEON_RV200_LX, RADEON_RV200, RFB_MOB }, 273 { PCI_PRODUCT_ATI_RADEON_RV200_QW, RADEON_RV200, 0 }, 274 { PCI_PRODUCT_ATI_RADEON_RV200_QX, RADEON_RV200, 0 }, 275 276 /* RV250 family */ 277 { PCI_PRODUCT_ATI_RADEON_RV250_4966, RADEON_RV250, 0 }, 278 { PCI_PRODUCT_ATI_RADEON_RV250_4967, RADEON_RV250, 0 }, 279 { PCI_PRODUCT_ATI_RADEON_RV250_4C64, RADEON_RV250, RFB_MOB }, 280 { PCI_PRODUCT_ATI_RADEON_RV250_4C66, RADEON_RV250, RFB_MOB }, 281 { PCI_PRODUCT_ATI_RADEON_RV250_4C67, RADEON_RV250, RFB_MOB }, 282 283 /* RS300 family */ 284 { PCI_PRODUCT_ATI_RADEON_RS300_X5, RADEON_RS300, 0 }, 285 { PCI_PRODUCT_ATI_RADEON_RS300_X4, RADEON_RS300, 0 }, 286 { PCI_PRODUCT_ATI_RADEON_RS300_7834, RADEON_RS300, 0 }, 287 { PCI_PRODUCT_ATI_RADEON_RS300_7835, RADEON_RS300, RFB_MOB }, 288 289 /* RV280 family */ 290 { PCI_PRODUCT_ATI_RADEON_RV280_5960, RADEON_RV280, 0 }, 291 { PCI_PRODUCT_ATI_RADEON_RV280_5961, RADEON_RV280, 0 }, 292 { PCI_PRODUCT_ATI_RADEON_RV280_5962, RADEON_RV280, 0 }, 293 { PCI_PRODUCT_ATI_RADEON_RV280_5963, RADEON_RV280, 0 }, 294 { PCI_PRODUCT_ATI_RADEON_RV280_5964, RADEON_RV280, 0 }, 295 { PCI_PRODUCT_ATI_RADEON_RV280_5C61, RADEON_RV280, RFB_MOB }, 296 { PCI_PRODUCT_ATI_RADEON_RV280_5C63, RADEON_RV280, RFB_MOB }, 297 298 /* R300 family */ 299 { PCI_PRODUCT_ATI_RADEON_R300_AD, RADEON_R300, 0 }, 300 { PCI_PRODUCT_ATI_RADEON_R300_AE, RADEON_R300, 0 }, 301 { PCI_PRODUCT_ATI_RADEON_R300_AF, RADEON_R300, 0 }, 302 { PCI_PRODUCT_ATI_RADEON_R300_AG, RADEON_R300, 0 }, 303 { PCI_PRODUCT_ATI_RADEON_R300_ND, RADEON_R300, 0 }, 304 { PCI_PRODUCT_ATI_RADEON_R300_NE, RADEON_R300, 0 }, 305 { PCI_PRODUCT_ATI_RADEON_R300_NF, RADEON_R300, 0 }, 306 { PCI_PRODUCT_ATI_RADEON_R300_NG, RADEON_R300, 0 }, 307 308 /* RV350/RV360 family */ 309 { PCI_PRODUCT_ATI_RADEON_RV350_AP, RADEON_RV350, 0 }, 310 { PCI_PRODUCT_ATI_RADEON_RV350_AQ, RADEON_RV350, 0 }, 311 { PCI_PRODUCT_ATI_RADEON_RV360_AR, RADEON_RV350, 0 }, 312 { PCI_PRODUCT_ATI_RADEON_RV350_AS, RADEON_RV350, 0 }, 313 { PCI_PRODUCT_ATI_RADEON_RV350_AT, RADEON_RV350, 0 }, 314 { PCI_PRODUCT_ATI_RADEON_RV350_AV, RADEON_RV350, 0 }, 315 { PCI_PRODUCT_ATI_RADEON_RV350_NP, RADEON_RV350, RFB_MOB }, 316 { PCI_PRODUCT_ATI_RADEON_RV350_NQ, RADEON_RV350, RFB_MOB }, 317 { PCI_PRODUCT_ATI_RADEON_RV350_NR, RADEON_RV350, RFB_MOB }, 318 { PCI_PRODUCT_ATI_RADEON_RV350_NS, RADEON_RV350, RFB_MOB }, 319 { PCI_PRODUCT_ATI_RADEON_RV350_NT, RADEON_RV350, RFB_MOB }, 320 { PCI_PRODUCT_ATI_RADEON_RV350_NV, RADEON_RV350, RFB_MOB }, 321 322 /* R350/R360 family */ 323 { PCI_PRODUCT_ATI_RADEON_R350_AH, RADEON_R350, 0 }, 324 { PCI_PRODUCT_ATI_RADEON_R350_AI, RADEON_R350, 0 }, 325 { PCI_PRODUCT_ATI_RADEON_R350_AJ, RADEON_R350, 0 }, 326 { PCI_PRODUCT_ATI_RADEON_R350_AK, RADEON_R350, 0 }, 327 { PCI_PRODUCT_ATI_RADEON_R350_NH, RADEON_R350, 0 }, 328 { PCI_PRODUCT_ATI_RADEON_R350_NI, RADEON_R350, 0 }, 329 { PCI_PRODUCT_ATI_RADEON_R350_NK, RADEON_R350, 0 }, 330 { PCI_PRODUCT_ATI_RADEON_R360_NJ, RADEON_R350, 0 }, 331 332 /* RV380/RV370 family */ 333 { PCI_PRODUCT_ATI_RADEON_RV380_3150, RADEON_RV380, RFB_MOB }, 334 { PCI_PRODUCT_ATI_RADEON_RV380_3154, RADEON_RV380, RFB_MOB }, 335 { PCI_PRODUCT_ATI_RADEON_RV380_3E50, RADEON_RV380, 0 }, 336 { PCI_PRODUCT_ATI_RADEON_RV380_3E54, RADEON_RV380, 0 }, 337 { PCI_PRODUCT_ATI_RADEON_RV370_5460, RADEON_RV380, RFB_MOB }, 338 { PCI_PRODUCT_ATI_RADEON_RV370_5464, RADEON_RV380, RFB_MOB }, 339 { PCI_PRODUCT_ATI_RADEON_RV370_5B60, RADEON_RV380, 0 }, 340 { PCI_PRODUCT_ATI_RADEON_RV370_5B64, RADEON_RV380, 0 }, 341 { PCI_PRODUCT_ATI_RADEON_RV370_5B65, RADEON_RV380, 0 }, 342 343 /* R420/R423 family */ 344 { PCI_PRODUCT_ATI_RADEON_R420_JH, RADEON_R420, 0 }, 345 { PCI_PRODUCT_ATI_RADEON_R420_JI, RADEON_R420, 0 }, 346 { PCI_PRODUCT_ATI_RADEON_R420_JJ, RADEON_R420, 0 }, 347 { PCI_PRODUCT_ATI_RADEON_R420_JK, RADEON_R420, 0 }, 348 { PCI_PRODUCT_ATI_RADEON_R420_JL, RADEON_R420, 0 }, 349 { PCI_PRODUCT_ATI_RADEON_R420_JM, RADEON_R420, 0 }, 350 { PCI_PRODUCT_ATI_RADEON_R420_JN, RADEON_R420, RFB_MOB }, 351 { PCI_PRODUCT_ATI_RADEON_R420_JP, RADEON_R420, 0 }, 352 { PCI_PRODUCT_ATI_RADEON_R423_UH, RADEON_R420, 0 }, 353 { PCI_PRODUCT_ATI_RADEON_R423_UI, RADEON_R420, 0 }, 354 { PCI_PRODUCT_ATI_RADEON_R423_UJ, RADEON_R420, 0 }, 355 { PCI_PRODUCT_ATI_RADEON_R423_UK, RADEON_R420, 0 }, 356 { PCI_PRODUCT_ATI_RADEON_R423_UQ, RADEON_R420, 0 }, 357 { PCI_PRODUCT_ATI_RADEON_R423_UR, RADEON_R420, 0 }, 358 { PCI_PRODUCT_ATI_RADEON_R423_UT, RADEON_R420, 0 }, 359 { PCI_PRODUCT_ATI_RADEON_R423_5D57, RADEON_R420, 0 }, 360 361 { 0, 0, 0 } 362 }; 363 364 static struct { 365 int divider; 366 int mask; 367 } radeonfb_dividers[] = { 368 { 1, 0 }, 369 { 2, 1 }, 370 { 3, 4 }, 371 { 4, 2 }, 372 { 6, 6 }, 373 { 8, 3 }, 374 { 12, 7 }, 375 { 0, 0 } 376 }; 377 378 /* 379 * This table taken from X11. 380 */ 381 static const struct { 382 int family; 383 struct radeon_tmds_pll plls[4]; 384 } radeonfb_tmds_pll[] = { 385 { RADEON_R100, {{12000, 0xa1b}, {-1, 0xa3f}}}, 386 { RADEON_RV100, {{12000, 0xa1b}, {-1, 0xa3f}}}, 387 { RADEON_RS100, {{0, 0}}}, 388 { RADEON_RV200, {{15000, 0xa1b}, {-1, 0xa3f}}}, 389 { RADEON_RS200, {{15000, 0xa1b}, {-1, 0xa3f}}}, 390 { RADEON_R200, {{15000, 0xa1b}, {-1, 0xa3f}}}, 391 { RADEON_RV250, {{15500, 0x81b}, {-1, 0x83f}}}, 392 { RADEON_RS300, {{0, 0}}}, 393 { RADEON_RV280, {{13000, 0x400f4}, {15000, 0x400f7}}}, 394 { RADEON_R300, {{-1, 0xb01cb}}}, 395 { RADEON_R350, {{-1, 0xb01cb}}}, 396 { RADEON_RV350, {{15000, 0xb0155}, {-1, 0xb01cb}}}, 397 { RADEON_RV380, {{15000, 0xb0155}, {-1, 0xb01cb}}}, 398 { RADEON_R420, {{-1, 0xb01cb}}}, 399 }; 400 401 #define RADEONFB_BACKLIGHT_MAX 255 /* Maximum backlight level. */ 402 403 404 CFATTACH_DECL(radeonfb, sizeof (struct radeonfb_softc), 405 radeonfb_match, radeonfb_attach, NULL, NULL); 406 407 static int 408 radeonfb_match(struct device *parent, struct cfdata *match, void *aux) 409 { 410 struct pci_attach_args *pa = aux; 411 int i; 412 413 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_ATI) 414 return 0; 415 416 for (i = 0; radeonfb_devices[i].devid; i++) { 417 if (PCI_PRODUCT(pa->pa_id) == radeonfb_devices[i].devid) 418 return 100; /* high to defeat VGA/VESA */ 419 } 420 421 return 0; 422 } 423 424 static void 425 radeonfb_attach(struct device *parent, struct device *dev, void *aux) 426 { 427 struct radeonfb_softc *sc = (struct radeonfb_softc *)dev; 428 struct pci_attach_args *pa = aux; 429 const char *mptr; 430 bus_size_t bsz; 431 pcireg_t screg; 432 int i, j, fg, bg, ul; 433 uint32_t v; 434 435 sc->sc_id = pa->pa_id; 436 for (i = 0; radeonfb_devices[i].devid; i++) { 437 if (PCI_PRODUCT(sc->sc_id) == radeonfb_devices[i].devid) 438 break; 439 } 440 441 pci_devinfo(sc->sc_id, pa->pa_class, 0, sc->sc_devinfo, 442 sizeof(sc->sc_devinfo)); 443 444 aprint_naive("\n"); 445 aprint_normal(": %s\n", sc->sc_devinfo); 446 447 DPRINTF((prop_dictionary_externalize(device_properties(dev)))); 448 449 KASSERT(radeonfb_devices[i].devid != 0); 450 sc->sc_pt = pa->pa_tag; 451 sc->sc_iot = pa->pa_iot; 452 sc->sc_pc = pa->pa_pc; 453 sc->sc_family = radeonfb_devices[i].family; 454 sc->sc_flags = radeonfb_devices[i].flags; 455 456 /* enable memory and IO access */ 457 screg = pci_conf_read(sc->sc_pc, sc->sc_pt, PCI_COMMAND_STATUS_REG); 458 screg |= PCI_FLAGS_IO_ENABLED | PCI_FLAGS_MEM_ENABLED; 459 pci_conf_write(sc->sc_pc, sc->sc_pt, PCI_COMMAND_STATUS_REG, screg); 460 461 /* 462 * Some flags are general to entire chip families, and rather 463 * than clutter up the table with them, we go ahead and set 464 * them here. 465 */ 466 switch (sc->sc_family) { 467 case RADEON_RS100: 468 case RADEON_RS200: 469 sc->sc_flags |= RFB_IGP | RFB_RV100; 470 break; 471 472 case RADEON_RV100: 473 case RADEON_RV200: 474 case RADEON_RV250: 475 case RADEON_RV280: 476 sc->sc_flags |= RFB_RV100; 477 break; 478 479 case RADEON_RS300: 480 sc->sc_flags |= RFB_SDAC | RFB_IGP | RFB_RV100; 481 break; 482 483 case RADEON_R300: 484 case RADEON_RV350: 485 case RADEON_R350: 486 case RADEON_RV380: 487 case RADEON_R420: 488 /* newer chips */ 489 sc->sc_flags |= RFB_R300; 490 break; 491 492 case RADEON_R100: 493 sc->sc_flags |= RFB_NCRTC2; 494 break; 495 } 496 497 if ((sc->sc_family == RADEON_RV200) || 498 (sc->sc_family == RADEON_RV250) || 499 (sc->sc_family == RADEON_RV280) || 500 (sc->sc_family == RADEON_RV350)) { 501 bool inverted = 0; 502 /* backlight level is linear */ 503 DPRINTF(("found RV* chip, backlight is supposedly linear\n")); 504 prop_dictionary_get_bool(device_properties(&sc->sc_dev), 505 "backlight_level_reverted", &inverted); 506 if (inverted) { 507 DPRINTF(("nope, it's inverted\n")); 508 sc->sc_flags |= RFB_INV_BLIGHT; 509 } 510 } else 511 sc->sc_flags |= RFB_INV_BLIGHT; 512 513 /* 514 * XXX: to support true multihead, this must change. 515 */ 516 sc->sc_ndisplays = 1; 517 518 /* XXX: */ 519 if (!HAS_CRTC2(sc)) { 520 sc->sc_ndisplays = 1; 521 } 522 523 if (pci_mapreg_map(pa, RADEON_MAPREG_MMIO, PCI_MAPREG_TYPE_MEM, 0, 524 &sc->sc_regt, &sc->sc_regh, &sc->sc_regaddr, 525 &sc->sc_regsz) != 0) { 526 aprint_error("%s: unable to map registers!\n", XNAME(sc)); 527 goto error; 528 } 529 530 /* scratch register test... */ 531 if (radeonfb_scratch_test(sc, RADEON_BIOS_0_SCRATCH, 0x55555555) || 532 radeonfb_scratch_test(sc, RADEON_BIOS_0_SCRATCH, 0xaaaaaaaa)) { 533 aprint_error("%s: scratch register test failed!\n", XNAME(sc)); 534 goto error; 535 } 536 537 PRINTREG(RADEON_BIOS_4_SCRATCH); 538 PRINTREG(RADEON_FP_GEN_CNTL); 539 PRINTREG(RADEON_FP2_GEN_CNTL); 540 PRINTREG(RADEON_TMDS_CNTL); 541 PRINTREG(RADEON_TMDS_TRANSMITTER_CNTL); 542 PRINTREG(RADEON_TMDS_PLL_CNTL); 543 PRINTREG(RADEON_LVDS_GEN_CNTL); 544 PRINTREG(RADEON_FP_HORZ_STRETCH); 545 PRINTREG(RADEON_FP_VERT_STRETCH); 546 547 /* XXX: RV100 specific */ 548 PUT32(sc, RADEON_TMDS_PLL_CNTL, 0xa27); 549 550 PATCH32(sc, RADEON_TMDS_TRANSMITTER_CNTL, 551 RADEON_TMDS_TRANSMITTER_PLLEN, 552 RADEON_TMDS_TRANSMITTER_PLLEN | RADEON_TMDS_TRANSMITTER_PLLRST); 553 554 radeonfb_i2c_init(sc); 555 556 radeonfb_loadbios(sc, pa); 557 558 #ifdef RADEON_BIOS_INIT 559 if (radeonfb_bios_init(sc)) { 560 aprint_error("%s: BIOS inititialization failed\n", XNAME(sc)); 561 goto error; 562 } 563 #endif 564 565 if (radeonfb_getclocks(sc)) { 566 aprint_error("%s: Unable to get reference clocks from BIOS\n", 567 XNAME(sc)); 568 goto error; 569 } 570 571 if (radeonfb_gettmds(sc)) { 572 aprint_error("%s: Unable to identify TMDS PLL settings\n", 573 XNAME(sc)); 574 goto error; 575 } 576 577 aprint_verbose("%s: refclk = %d.%03d MHz, refdiv = %d " 578 "minpll = %d, maxpll = %d\n", XNAME(sc), 579 (int)sc->sc_refclk / 1000, (int)sc->sc_refclk % 1000, 580 (int)sc->sc_refdiv, (int)sc->sc_minpll, (int)sc->sc_maxpll); 581 582 radeonfb_getconnectors(sc); 583 584 radeonfb_set_fbloc(sc); 585 586 for (i = 0; radeonfb_limits[i].size; i++) { 587 if (sc->sc_memsz >= radeonfb_limits[i].size) { 588 sc->sc_maxx = radeonfb_limits[i].maxx; 589 sc->sc_maxy = radeonfb_limits[i].maxy; 590 sc->sc_maxbpp = radeonfb_limits[i].maxbpp; 591 /* framebuffer offset, start at a 4K page */ 592 sc->sc_fboffset = sc->sc_memsz / 593 radeonfb_limits[i].maxdisp; 594 /* 595 * we use the fbsize to figure out where we can store 596 * things like cursor data. 597 */ 598 sc->sc_fbsize = 599 ROUNDUP(ROUNDUP(sc->sc_maxx * sc->sc_maxbpp / 8 , 600 RADEON_STRIDEALIGN) * sc->sc_maxy, 601 4096); 602 break; 603 } 604 } 605 606 607 radeonfb_init_misc(sc); 608 radeonfb_init_palette(sc, 0); 609 if (HAS_CRTC2(sc)) 610 radeonfb_init_palette(sc, 1); 611 612 /* program the DAC wirings */ 613 for (i = 0; i < (HAS_CRTC2(sc) ? 2 : 1); i++) { 614 switch (sc->sc_ports[i].rp_dac_type) { 615 case RADEON_DAC_PRIMARY: 616 PATCH32(sc, RADEON_DAC_CNTL2, 617 i ? RADEON_DAC2_DAC_CLK_SEL : 0, 618 ~RADEON_DAC2_DAC_CLK_SEL); 619 break; 620 case RADEON_DAC_TVDAC: 621 /* we always use the TVDAC to drive a secondary analog 622 * CRT for now. if we ever support TV-out this will 623 * have to change. 624 */ 625 SET32(sc, RADEON_DAC_CNTL2, 626 RADEON_DAC2_DAC2_CLK_SEL); 627 PATCH32(sc, RADEON_DISP_HW_DEBUG, 628 i ? 0 : RADEON_CRT2_DISP1_SEL, 629 ~RADEON_CRT2_DISP1_SEL); 630 break; 631 } 632 } 633 PRINTREG(RADEON_DAC_CNTL2); 634 PRINTREG(RADEON_DISP_HW_DEBUG); 635 636 /* other DAC programming */ 637 v = GET32(sc, RADEON_DAC_CNTL); 638 v &= (RADEON_DAC_RANGE_CNTL_MASK | RADEON_DAC_BLANKING); 639 v |= RADEON_DAC_MASK_ALL | RADEON_DAC_8BIT_EN; 640 PUT32(sc, RADEON_DAC_CNTL, v); 641 PRINTREG(RADEON_DAC_CNTL); 642 643 /* XXX: this may need more investigation */ 644 PUT32(sc, RADEON_TV_DAC_CNTL, 0x00280203); 645 PRINTREG(RADEON_TV_DAC_CNTL); 646 647 /* enable TMDS */ 648 SET32(sc, RADEON_FP_GEN_CNTL, 649 RADEON_FP_TMDS_EN | 650 RADEON_FP_CRTC_DONT_SHADOW_VPAR | 651 RADEON_FP_CRTC_DONT_SHADOW_HEND); 652 CLR32(sc, RADEON_FP_GEN_CNTL, RADEON_FP_SEL_CRTC2); 653 if (HAS_CRTC2(sc)) 654 SET32(sc, RADEON_FP2_GEN_CNTL, RADEON_FP2_SRC_SEL_CRTC2); 655 656 /* 657 * we use bus_space_map instead of pci_mapreg, because we don't 658 * need the full aperature space. no point in wasting virtual 659 * address space we don't intend to use, right? 660 */ 661 if ((sc->sc_memsz < (4096 * 1024)) || 662 (pci_mapreg_info(sc->sc_pc, sc->sc_pt, RADEON_MAPREG_VRAM, 663 PCI_MAPREG_TYPE_MEM, &sc->sc_memaddr, &bsz, NULL) != 0) || 664 (bsz < sc->sc_memsz)) { 665 sc->sc_memsz = 0; 666 aprint_error("%s: Bad frame buffer configuration\n", 667 XNAME(sc)); 668 goto error; 669 } 670 671 /* 64 MB should be enough -- more just wastes map entries */ 672 if (sc->sc_memsz > (64 << 20)) 673 sc->sc_memsz = (64 << 20); 674 675 sc->sc_memt = pa->pa_memt; 676 if (bus_space_map(sc->sc_memt, sc->sc_memaddr, sc->sc_memsz, 677 BUS_SPACE_MAP_LINEAR, &sc->sc_memh) != 0) { 678 sc->sc_memsz = 0; 679 aprint_error("%s: Unable to map frame buffer\n", XNAME(sc)); 680 goto error; 681 } 682 683 aprint_normal("%s: %d MB aperture at 0x%08x, " 684 "%d KB registers at 0x%08x\n", XNAME(sc), 685 (int)sc->sc_memsz >> 20, (unsigned)sc->sc_memaddr, 686 (int)sc->sc_regsz >> 10, (unsigned)sc->sc_regaddr); 687 688 /* setup default video mode from devprop (allows PROM override) */ 689 sc->sc_defaultmode = radeonfb_default_mode; 690 if (prop_dictionary_get_cstring_nocopy(device_properties(&sc->sc_dev), 691 "videomode", &mptr)) { 692 693 strncpy(sc->sc_modebuf, mptr, sizeof(sc->sc_modebuf)); 694 sc->sc_defaultmode = sc->sc_modebuf; 695 } 696 697 /* initialize some basic display parameters */ 698 for (i = 0; i < sc->sc_ndisplays; i++) { 699 struct radeonfb_display *dp = &sc->sc_displays[i]; 700 struct rasops_info *ri; 701 long defattr; 702 struct wsemuldisplaydev_attach_args aa; 703 704 /* 705 * Figure out how many "displays" (desktops) we are going to 706 * support. If more than one, then each CRTC gets its own 707 * programming. 708 * 709 * XXX: this code needs to change to support mergedfb. 710 * XXX: would be nice to allow this to be overridden 711 */ 712 if (HAS_CRTC2(sc) && (sc->sc_ndisplays == 1)) { 713 DPRINTF(("dual crtcs!\n")); 714 dp->rd_ncrtcs = 2; 715 dp->rd_crtcs[0].rc_number = 0; 716 dp->rd_crtcs[1].rc_number = 1; 717 } else { 718 dp->rd_ncrtcs = 1; 719 dp->rd_crtcs[0].rc_number = i; 720 } 721 722 /* set up port pointer */ 723 for (j = 0; j < dp->rd_ncrtcs; j++) { 724 dp->rd_crtcs[j].rc_port = 725 &sc->sc_ports[dp->rd_crtcs[j].rc_number]; 726 } 727 728 dp->rd_softc = sc; 729 dp->rd_wsmode = WSDISPLAYIO_MODE_EMUL; 730 dp->rd_bg = WS_DEFAULT_BG; 731 #if 0 732 dp->rd_bpp = sc->sc_maxbpp; /* XXX: for now */ 733 #else 734 dp->rd_bpp = RADEONFB_DEFAULT_DEPTH; /* XXX */ 735 #endif 736 /* for text mode, we pick a resolution that won't 737 * require panning */ 738 radeonfb_pickres(dp, &dp->rd_virtx, &dp->rd_virty, 0); 739 740 aprint_normal("%s: display %d: " 741 "initial virtual resolution %dx%d at %d bpp\n", 742 XNAME(sc), i, dp->rd_virtx, dp->rd_virty, dp->rd_bpp); 743 744 /* now select the *video mode* that we will use */ 745 for (j = 0; j < dp->rd_ncrtcs; j++) { 746 const struct videomode *vmp; 747 vmp = radeonfb_port_mode(sc, dp->rd_crtcs[j].rc_port, 748 dp->rd_virtx, dp->rd_virty); 749 750 /* 751 * virtual resolution should be at least as high as 752 * physical 753 */ 754 if (dp->rd_virtx < vmp->hdisplay || 755 dp->rd_virty < vmp->vdisplay) { 756 dp->rd_virtx = vmp->hdisplay; 757 dp->rd_virty = vmp->vdisplay; 758 } 759 760 dp->rd_crtcs[j].rc_videomode = *vmp; 761 printf("%s: port %d: physical %dx%d %dHz\n", 762 XNAME(sc), j, vmp->hdisplay, vmp->vdisplay, 763 DIVIDE(DIVIDE(vmp->dot_clock * 1000, 764 vmp->htotal), vmp->vtotal)); 765 } 766 767 /* N.B.: radeon wants 64-byte aligned stride */ 768 dp->rd_stride = dp->rd_virtx * dp->rd_bpp / 8; 769 dp->rd_stride = ROUNDUP(dp->rd_stride, RADEON_STRIDEALIGN); 770 771 dp->rd_offset = sc->sc_fboffset * i; 772 dp->rd_fbptr = (vaddr_t)bus_space_vaddr(sc->sc_memt, 773 sc->sc_memh) + dp->rd_offset; 774 dp->rd_curoff = sc->sc_fbsize; 775 dp->rd_curptr = dp->rd_fbptr + dp->rd_curoff; 776 777 DPRINTF(("fpbtr = %p\n", (void *)dp->rd_fbptr)); 778 779 switch (dp->rd_bpp) { 780 case 8: 781 dp->rd_format = 2; 782 break; 783 case 32: 784 dp->rd_format = 6; 785 break; 786 default: 787 aprint_error("%s: bad depth %d\n", XNAME(sc), 788 dp->rd_bpp); 789 goto error; 790 } 791 792 printf("init engine\n"); 793 /* XXX: this seems suspicious - per display engine 794 initialization? */ 795 radeonfb_engine_init(dp); 796 797 /* copy the template into place */ 798 dp->rd_wsscreens_storage[0] = radeonfb_stdscreen; 799 dp->rd_wsscreens = dp->rd_wsscreens_storage; 800 801 /* and make up the list */ 802 dp->rd_wsscreenlist.nscreens = 1; 803 dp->rd_wsscreenlist.screens = 804 (const struct wsscreen_descr **)&dp->rd_wsscreens; 805 806 vcons_init(&dp->rd_vd, dp, dp->rd_wsscreens, 807 &radeonfb_accessops); 808 809 dp->rd_vd.init_screen = radeonfb_init_screen; 810 811 dp->rd_console = 1; 812 813 dp->rd_vscreen.scr_flags |= VCONS_SCREEN_IS_STATIC; 814 815 816 vcons_init_screen(&dp->rd_vd, &dp->rd_vscreen, 817 dp->rd_console, &defattr); 818 819 ri = &dp->rd_vscreen.scr_ri; 820 821 /* clear the screen */ 822 rasops_unpack_attr(defattr, &fg, &bg, &ul); 823 radeonfb_rectfill(dp, 0, 0, ri->ri_width, ri->ri_height, 824 ri->ri_devcmap[bg & 0xf]); 825 826 dp->rd_wsscreens->textops = &ri->ri_ops; 827 dp->rd_wsscreens->capabilities = ri->ri_caps; 828 dp->rd_wsscreens->nrows = ri->ri_rows; 829 dp->rd_wsscreens->ncols = ri->ri_cols; 830 831 #ifdef SPLASHSCREEN 832 dp->rd_splash.si_depth = ri->ri_depth; 833 dp->rd_splash.si_bits = ri->ri_bits; 834 dp->rd_splash.si_hwbits = ri->ri_hwbits; 835 dp->rd_splash.si_width = ri->ri_width; 836 dp->rd_splash.si_height = ri->ri_height; 837 dp->rd_splash.si_stride = ri->ri_stride; 838 dp->rd_splash.si_fillrect = NULL; 839 #endif 840 if (dp->rd_console) { 841 842 wsdisplay_cnattach(dp->rd_wsscreens, ri, 0, 0, 843 defattr); 844 #ifdef SPLASHSCREEN 845 splash_render(&dp->rd_splash, 846 SPLASH_F_CENTER|SPLASH_F_FILL); 847 #endif 848 849 #ifdef SPLASHSCREEN_PROGRESS 850 dp->rd_progress.sp_top = (dp->rd_virty / 8) * 7; 851 dp->rd_progress.sp_width = (dp->rd_virtx / 4) * 3; 852 dp->rd_progress.sp_left = (dp->rd_virtx - 853 dp->rd_progress.sp_width) / 2; 854 dp->rd_progress.sp_height = 20; 855 dp->rd_progress.sp_state = -1; 856 dp->rd_progress.sp_si = &dp->rd_splash; 857 splash_progress_init(&dp->rd_progress); 858 SCREEN_DISABLE_DRAWING(&dp->rd_vscreen); 859 #endif 860 861 } else { 862 863 /* 864 * since we're not the console we can postpone 865 * the rest until someone actually allocates a 866 * screen for us. but we do clear the screen 867 * at least. 868 */ 869 memset(ri->ri_bits, 0, 1024); 870 871 radeonfb_modeswitch(dp); 872 #ifdef SPLASHSCREEN 873 splash_render(&dp->rd_splash, 874 SPLASH_F_CENTER|SPLASH_F_FILL); 875 SCREEN_DISABLE_DRAWING(&dp->rd_vscreen); 876 #endif 877 } 878 879 aa.console = dp->rd_console; 880 aa.scrdata = &dp->rd_wsscreenlist; 881 aa.accessops = &radeonfb_accessops; 882 aa.accesscookie = &dp->rd_vd; 883 884 config_found(&sc->sc_dev, &aa, wsemuldisplaydevprint); 885 radeonfb_blank(dp, 0); 886 887 /* Initialise delayed lvds operations for backlight. */ 888 callout_init(&dp->rd_bl_lvds_co, 0); 889 callout_setfunc(&dp->rd_bl_lvds_co, 890 radeonfb_lvds_callout, dp); 891 } 892 893 config_found_ia(dev, "drm", aux, radeonfb_drm_print); 894 895 return; 896 897 error: 898 if (sc->sc_biossz) 899 free(sc->sc_bios, M_DEVBUF); 900 901 if (sc->sc_regsz) 902 bus_space_unmap(sc->sc_regt, sc->sc_regh, sc->sc_regsz); 903 904 if (sc->sc_memsz) 905 bus_space_unmap(sc->sc_memt, sc->sc_memh, sc->sc_memsz); 906 } 907 908 static int 909 radeonfb_drm_print(void *aux, const char *pnp) 910 { 911 if (pnp) 912 aprint_normal("direct rendering for %s", pnp); 913 return (UNSUPP); 914 } 915 916 int 917 radeonfb_ioctl(void *v, void *vs, 918 unsigned long cmd, void *d, int flag, struct lwp *l) 919 { 920 struct vcons_data *vd; 921 struct radeonfb_display *dp; 922 struct radeonfb_softc *sc; 923 struct wsdisplay_param *param; 924 925 vd = (struct vcons_data *)v; 926 dp = (struct radeonfb_display *)vd->cookie; 927 sc = dp->rd_softc; 928 929 switch (cmd) { 930 case WSDISPLAYIO_GTYPE: 931 *(unsigned *)d = WSDISPLAY_TYPE_PCIMISC; 932 return 0; 933 934 case WSDISPLAYIO_GINFO: 935 if (vd->active != NULL) { 936 struct wsdisplay_fbinfo *fb; 937 fb = (struct wsdisplay_fbinfo *)d; 938 fb->width = dp->rd_virtx; 939 fb->height = dp->rd_virty; 940 fb->depth = dp->rd_bpp; 941 fb->cmsize = 256; 942 return 0; 943 } else 944 return ENODEV; 945 case WSDISPLAYIO_GVIDEO: 946 if (radeonfb_isblank(dp)) 947 *(unsigned *)d = WSDISPLAYIO_VIDEO_OFF; 948 else 949 *(unsigned *)d = WSDISPLAYIO_VIDEO_ON; 950 return 0; 951 952 case WSDISPLAYIO_SVIDEO: 953 radeonfb_blank(dp, 954 (*(unsigned int *)d == WSDISPLAYIO_VIDEO_OFF)); 955 return 0; 956 957 case WSDISPLAYIO_GETCMAP: 958 #if 0 959 if (dp->rd_bpp == 8) 960 return radeonfb_getcmap(sc, 961 (struct wsdisplay_cmap *)d); 962 #endif 963 return EINVAL; 964 965 case WSDISPLAYIO_PUTCMAP: 966 #if 0 967 if (dp->rd_bpp == 8) 968 return radeonfb_putcmap(sc, 969 (struct wsdisplay_cmap *)d); 970 #endif 971 return EINVAL; 972 973 case WSDISPLAYIO_LINEBYTES: 974 *(unsigned *)d = dp->rd_stride; 975 return 0; 976 977 case WSDISPLAYIO_SMODE: 978 if (*(int *)d != dp->rd_wsmode) { 979 dp->rd_wsmode = *(int *)d; 980 if ((dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) && 981 (dp->rd_vd.active)) { 982 radeonfb_engine_init(dp); 983 radeonfb_modeswitch(dp); 984 vcons_redraw_screen(dp->rd_vd.active); 985 } 986 } 987 return 0; 988 989 case WSDISPLAYIO_GCURMAX: 990 ((struct wsdisplay_curpos *)d)->x = RADEON_CURSORMAXX; 991 ((struct wsdisplay_curpos *)d)->y = RADEON_CURSORMAXY; 992 return 0; 993 994 case WSDISPLAYIO_SCURSOR: 995 return radeonfb_set_cursor(dp, (struct wsdisplay_cursor *)d); 996 997 case WSDISPLAYIO_GCURSOR: 998 return EPASSTHROUGH; 999 1000 case WSDISPLAYIO_GCURPOS: 1001 ((struct wsdisplay_curpos *)d)->x = dp->rd_cursor.rc_pos.x; 1002 ((struct wsdisplay_curpos *)d)->y = dp->rd_cursor.rc_pos.y; 1003 return 0; 1004 1005 case WSDISPLAYIO_SCURPOS: 1006 return radeonfb_set_curpos(dp, (struct wsdisplay_curpos *)d); 1007 1008 case WSDISPLAYIO_SSPLASH: 1009 #if defined(SPLASHSCREEN) 1010 if (*(int *)d == 1) { 1011 SCREEN_DISABLE_DRAWING(&dp->rd_vscreen); 1012 splash_render(&dp->rd_splash, 1013 SPLASH_F_CENTER|SPLASH_F_FILL); 1014 } else 1015 SCREEN_ENABLE_DRAWING(&dp->rd_vscreen); 1016 return 0; 1017 #else 1018 return ENODEV; 1019 #endif 1020 case WSDISPLAYIO_SPROGRESS: 1021 #if defined(SPLASHSCREEN) && defined(SPLASHSCREEN_PROGRESS) 1022 dp->rd_progress.sp_force = 1; 1023 splash_progress_update(&dp->rd_progress); 1024 dp->rd_progress.sp_force = 0; 1025 return 0; 1026 #else 1027 return ENODEV; 1028 #endif 1029 case WSDISPLAYIO_GETPARAM: 1030 param = (struct wsdisplay_param *)d; 1031 if (param->param == WSDISPLAYIO_PARAM_BACKLIGHT) { 1032 param->min = 0; 1033 param->max = RADEONFB_BACKLIGHT_MAX; 1034 param->curval = radeonfb_get_backlight(dp); 1035 return 0; 1036 } 1037 return EPASSTHROUGH; 1038 1039 case WSDISPLAYIO_SETPARAM: 1040 param = (struct wsdisplay_param *)d; 1041 if (param->param == WSDISPLAYIO_PARAM_BACKLIGHT) { 1042 return radeonfb_set_backlight(dp, param->curval); 1043 } 1044 return EPASSTHROUGH; 1045 1046 default: 1047 return EPASSTHROUGH; 1048 } 1049 } 1050 1051 paddr_t 1052 radeonfb_mmap(void *v, void *vs, off_t offset, int prot) 1053 { 1054 struct vcons_data *vd; 1055 struct radeonfb_display *dp; 1056 struct radeonfb_softc *sc; 1057 #ifdef RADEONFB_MMAP_BARS 1058 struct lwp *me; 1059 #endif 1060 paddr_t pa; 1061 1062 vd = (struct vcons_data *)v; 1063 dp = (struct radeonfb_display *)vd->cookie; 1064 sc = dp->rd_softc; 1065 1066 /* XXX: note that we don't allow mapping of registers right now */ 1067 /* XXX: this means that the XFree86 radeon driver won't work */ 1068 1069 if ((offset >= 0) && (offset < (dp->rd_virty * dp->rd_stride))) { 1070 pa = bus_space_mmap(sc->sc_memt, 1071 sc->sc_memaddr + dp->rd_offset + offset, 0, 1072 prot, BUS_SPACE_MAP_LINEAR); 1073 return pa; 1074 } 1075 1076 #ifdef RADEONFB_MMAP_BARS 1077 /* 1078 * restrict all other mappings to processes with superuser privileges 1079 * or the kernel itself 1080 */ 1081 me = curlwp; 1082 if (me != NULL) { 1083 if (kauth_authorize_generic(me->l_cred, KAUTH_GENERIC_ISSUSER, 1084 NULL) != 0) { 1085 printf("%s: mmap() rejected.\n", sc->sc_dev.dv_xname); 1086 return -1; 1087 } 1088 } 1089 1090 if ((offset >= sc->sc_regaddr) && 1091 (offset < sc->sc_regaddr + sc->sc_regsz)) { 1092 return bus_space_mmap(sc->sc_regt, offset, 0, prot, 1093 BUS_SPACE_MAP_LINEAR); 1094 } 1095 1096 if ((offset >= sc->sc_memaddr) && 1097 (offset < sc->sc_memaddr + sc->sc_memsz)) { 1098 return bus_space_mmap(sc->sc_memt, offset, 0, prot, 1099 BUS_SPACE_MAP_LINEAR); 1100 } 1101 1102 #ifdef macppc 1103 /* allow mapping of IO space */ 1104 if ((offset >= 0xf2000000) && (offset < 0xf2800000)) { 1105 pa = bus_space_mmap(sc->sc_iot, offset - 0xf2000000, 0, prot, 1106 0); 1107 return pa; 1108 } 1109 #endif /* macppc */ 1110 1111 #endif /* RADEONFB_MMAP_BARS */ 1112 1113 return -1; 1114 } 1115 1116 static void 1117 radeonfb_loadbios(struct radeonfb_softc *sc, struct pci_attach_args *pa) 1118 { 1119 bus_space_tag_t romt; 1120 bus_space_handle_t romh, biosh; 1121 bus_size_t romsz; 1122 bus_addr_t ptr; 1123 1124 if (pci_mapreg_map(pa, PCI_MAPREG_ROM, PCI_MAPREG_TYPE_ROM, 1125 BUS_SPACE_MAP_PREFETCHABLE, &romt, &romh, NULL, &romsz) != 0) { 1126 aprint_verbose("%s: unable to map BIOS!\n", XNAME(sc)); 1127 return; 1128 } 1129 1130 pci_find_rom(pa, romt, romh, PCI_ROM_CODE_TYPE_X86, &biosh, 1131 &sc->sc_biossz); 1132 if (sc->sc_biossz == 0) { 1133 aprint_verbose("%s: Video BIOS not present\n", XNAME(sc)); 1134 return; 1135 } 1136 1137 sc->sc_bios = malloc(sc->sc_biossz, M_DEVBUF, M_WAITOK); 1138 bus_space_read_region_1(romt, biosh, 0, sc->sc_bios, sc->sc_biossz); 1139 1140 /* unmap the PCI expansion rom */ 1141 bus_space_unmap(romt, romh, romsz); 1142 1143 /* turn off rom decoder now */ 1144 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM, 1145 pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM) & 1146 ~PCI_MAPREG_ROM_ENABLE); 1147 1148 ptr = GETBIOS16(sc, 0x48); 1149 if ((GETBIOS32(sc, ptr + 4) == 0x41544f4d /* "ATOM" */) || 1150 (GETBIOS32(sc, ptr + 4) == 0x4d4f5441 /* "MOTA" */)) { 1151 sc->sc_flags |= RFB_ATOM; 1152 } 1153 1154 aprint_verbose("%s: Found %d KB %s BIOS\n", XNAME(sc), 1155 (unsigned)sc->sc_biossz >> 10, IS_ATOM(sc) ? "ATOM" : "Legacy"); 1156 } 1157 1158 1159 uint32_t 1160 radeonfb_get32(struct radeonfb_softc *sc, uint32_t reg) 1161 { 1162 1163 return bus_space_read_4(sc->sc_regt, sc->sc_regh, reg); 1164 } 1165 1166 void 1167 radeonfb_put32(struct radeonfb_softc *sc, uint32_t reg, uint32_t val) 1168 { 1169 1170 bus_space_write_4(sc->sc_regt, sc->sc_regh, reg, val); 1171 } 1172 1173 void 1174 radeonfb_mask32(struct radeonfb_softc *sc, uint32_t reg, 1175 uint32_t andmask, uint32_t ormask) 1176 { 1177 int s; 1178 uint32_t val; 1179 1180 s = splhigh(); 1181 val = radeonfb_get32(sc, reg); 1182 val = (val & andmask) | ormask; 1183 radeonfb_put32(sc, reg, val); 1184 splx(s); 1185 } 1186 1187 uint32_t 1188 radeonfb_getindex(struct radeonfb_softc *sc, uint32_t idx) 1189 { 1190 int s; 1191 uint32_t val; 1192 1193 s = splhigh(); 1194 radeonfb_put32(sc, RADEON_MM_INDEX, idx); 1195 val = radeonfb_get32(sc, RADEON_MM_DATA); 1196 splx(s); 1197 1198 return (val); 1199 } 1200 1201 void 1202 radeonfb_putindex(struct radeonfb_softc *sc, uint32_t idx, uint32_t val) 1203 { 1204 int s; 1205 1206 s = splhigh(); 1207 radeonfb_put32(sc, RADEON_MM_INDEX, idx); 1208 radeonfb_put32(sc, RADEON_MM_DATA, val); 1209 splx(s); 1210 } 1211 1212 void 1213 radeonfb_maskindex(struct radeonfb_softc *sc, uint32_t idx, 1214 uint32_t andmask, uint32_t ormask) 1215 { 1216 int s; 1217 uint32_t val; 1218 1219 s = splhigh(); 1220 radeonfb_put32(sc, RADEON_MM_INDEX, idx); 1221 val = radeonfb_get32(sc, RADEON_MM_DATA); 1222 val = (val & andmask) | ormask; 1223 radeonfb_put32(sc, RADEON_MM_DATA, val); 1224 splx(s); 1225 } 1226 1227 uint32_t 1228 radeonfb_getpll(struct radeonfb_softc *sc, uint32_t idx) 1229 { 1230 int s; 1231 uint32_t val; 1232 1233 s = splhigh(); 1234 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, idx & 0x3f); 1235 val = radeonfb_get32(sc, RADEON_CLOCK_CNTL_DATA); 1236 if (HAS_R300CG(sc)) 1237 radeonfb_r300cg_workaround(sc); 1238 splx(s); 1239 1240 return (val); 1241 } 1242 1243 void 1244 radeonfb_putpll(struct radeonfb_softc *sc, uint32_t idx, uint32_t val) 1245 { 1246 int s; 1247 1248 s = splhigh(); 1249 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, (idx & 0x3f) | 1250 RADEON_PLL_WR_EN); 1251 radeonfb_put32(sc, RADEON_CLOCK_CNTL_DATA, val); 1252 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, 0); 1253 splx(s); 1254 } 1255 1256 void 1257 radeonfb_maskpll(struct radeonfb_softc *sc, uint32_t idx, 1258 uint32_t andmask, uint32_t ormask) 1259 { 1260 int s; 1261 uint32_t val; 1262 1263 s = splhigh(); 1264 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, (idx & 0x3f) | 1265 RADEON_PLL_WR_EN); 1266 val = radeonfb_get32(sc, RADEON_CLOCK_CNTL_DATA); 1267 val = (val & andmask) | ormask; 1268 radeonfb_put32(sc, RADEON_CLOCK_CNTL_DATA, val); 1269 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, 0); 1270 splx(s); 1271 } 1272 1273 int 1274 radeonfb_scratch_test(struct radeonfb_softc *sc, int reg, uint32_t v) 1275 { 1276 uint32_t saved; 1277 1278 saved = GET32(sc, reg); 1279 PUT32(sc, reg, v); 1280 if (GET32(sc, reg) != v) { 1281 return -1; 1282 } 1283 PUT32(sc, reg, saved); 1284 return 0; 1285 } 1286 1287 uintmax_t 1288 radeonfb_getprop_num(struct radeonfb_softc *sc, const char *name, 1289 uintmax_t defval) 1290 { 1291 prop_number_t pn; 1292 pn = prop_dictionary_get(device_properties(&sc->sc_dev), name); 1293 if (pn == NULL) { 1294 return defval; 1295 } 1296 KASSERT(prop_object_type(pn) == PROP_TYPE_NUMBER); 1297 return (prop_number_integer_value(pn)); 1298 } 1299 1300 int 1301 radeonfb_getclocks(struct radeonfb_softc *sc) 1302 { 1303 bus_addr_t ptr; 1304 int refclk = 0; 1305 int refdiv = 0; 1306 int minpll = 0; 1307 int maxpll = 0; 1308 1309 /* load initial property values if port/board provides them */ 1310 refclk = radeonfb_getprop_num(sc, "refclk", 0) & 0xffff; 1311 refdiv = radeonfb_getprop_num(sc, "refdiv", 0) & 0xffff; 1312 minpll = radeonfb_getprop_num(sc, "minpll", 0) & 0xffffffffU; 1313 maxpll = radeonfb_getprop_num(sc, "maxpll", 0) & 0xffffffffU; 1314 1315 if (refclk && refdiv && minpll && maxpll) 1316 goto dontprobe; 1317 1318 if (!sc->sc_biossz) { 1319 /* no BIOS */ 1320 aprint_verbose("%s: No video BIOS, using default clocks\n", 1321 XNAME(sc)); 1322 if (IS_IGP(sc)) 1323 refclk = refclk ? refclk : 1432; 1324 else 1325 refclk = refclk ? refclk : 2700; 1326 refdiv = refdiv ? refdiv : 12; 1327 minpll = minpll ? minpll : 12500; 1328 maxpll = maxpll ? maxpll : 35000; 1329 } else if (IS_ATOM(sc)) { 1330 /* ATOM BIOS */ 1331 ptr = GETBIOS16(sc, 0x48); 1332 ptr = GETBIOS16(sc, ptr + 32); /* aka MasterDataStart */ 1333 ptr = GETBIOS16(sc, ptr + 12); /* pll info block */ 1334 refclk = refclk ? refclk : GETBIOS16(sc, ptr + 82); 1335 minpll = minpll ? minpll : GETBIOS16(sc, ptr + 78); 1336 maxpll = maxpll ? maxpll : GETBIOS16(sc, ptr + 32); 1337 /* 1338 * ATOM BIOS doesn't supply a reference divider, so we 1339 * have to probe for it. 1340 */ 1341 if (refdiv < 2) 1342 refdiv = GETPLL(sc, RADEON_PPLL_REF_DIV) & 1343 RADEON_PPLL_REF_DIV_MASK; 1344 /* 1345 * if probe is zero, just assume one that should work 1346 * for most parts 1347 */ 1348 if (refdiv < 2) 1349 refdiv = 12; 1350 1351 } else { 1352 /* Legacy BIOS */ 1353 ptr = GETBIOS16(sc, 0x48); 1354 ptr = GETBIOS16(sc, ptr + 0x30); 1355 refclk = refclk ? refclk : GETBIOS16(sc, ptr + 0x0E); 1356 refdiv = refdiv ? refdiv : GETBIOS16(sc, ptr + 0x10); 1357 minpll = minpll ? minpll : GETBIOS32(sc, ptr + 0x12); 1358 maxpll = maxpll ? maxpll : GETBIOS32(sc, ptr + 0x16); 1359 } 1360 1361 1362 dontprobe: 1363 sc->sc_refclk = refclk * 10; 1364 sc->sc_refdiv = refdiv; 1365 sc->sc_minpll = minpll * 10; 1366 sc->sc_maxpll = maxpll * 10; 1367 return 0; 1368 } 1369 1370 int 1371 radeonfb_calc_dividers(struct radeonfb_softc *sc, uint32_t dotclock, 1372 uint32_t *postdivbit, uint32_t *feedbackdiv) 1373 { 1374 int i; 1375 uint32_t outfreq; 1376 int div; 1377 1378 DPRINTF(("dot clock: %u\n", dotclock)); 1379 for (i = 0; (div = radeonfb_dividers[i].divider) != 0; i++) { 1380 outfreq = div * dotclock; 1381 if ((outfreq >= sc->sc_minpll) && 1382 (outfreq <= sc->sc_maxpll)) { 1383 DPRINTF(("outfreq: %u\n", outfreq)); 1384 *postdivbit = 1385 ((uint32_t)radeonfb_dividers[i].mask << 16); 1386 DPRINTF(("post divider: %d (mask %x)\n", div, 1387 *postdivbit)); 1388 break; 1389 } 1390 } 1391 1392 if (div == 0) 1393 return 1; 1394 1395 *feedbackdiv = DIVIDE(sc->sc_refdiv * outfreq, sc->sc_refclk); 1396 DPRINTF(("feedback divider: %d\n", *feedbackdiv)); 1397 return 0; 1398 } 1399 1400 #if 0 1401 #ifdef RADEON_DEBUG 1402 static void 1403 dump_buffer(const char *pfx, void *buffer, unsigned int size) 1404 { 1405 char asc[17]; 1406 unsigned ptr = (unsigned)buffer; 1407 char *start = (char *)(ptr & ~0xf); 1408 char *end = (char *)(ptr + size); 1409 1410 end = (char *)(((unsigned)end + 0xf) & ~0xf); 1411 1412 if (pfx == NULL) { 1413 pfx = ""; 1414 } 1415 1416 while (start < end) { 1417 unsigned offset = (unsigned)start & 0xf; 1418 if (offset == 0) { 1419 printf("%s%x: ", pfx, (unsigned)start); 1420 } 1421 if (((unsigned)start < ptr) || 1422 ((unsigned)start >= (ptr + size))) { 1423 printf(" "); 1424 asc[offset] = ' '; 1425 } else { 1426 printf("%02x", *(unsigned char *)start); 1427 if ((*start >= ' ') && (*start <= '~')) { 1428 asc[offset] = *start; 1429 } else { 1430 asc[offset] = '.'; 1431 } 1432 } 1433 asc[offset + 1] = 0; 1434 if (offset % 2) { 1435 printf(" "); 1436 } 1437 if (offset == 15) { 1438 printf(" %s\n", asc); 1439 } 1440 start++; 1441 } 1442 } 1443 #endif 1444 #endif 1445 1446 int 1447 radeonfb_getconnectors(struct radeonfb_softc *sc) 1448 { 1449 int i; 1450 int found = 0; 1451 1452 for (i = 0; i < 2; i++) { 1453 sc->sc_ports[i].rp_mon_type = RADEON_MT_UNKNOWN; 1454 sc->sc_ports[i].rp_ddc_type = RADEON_DDC_NONE; 1455 sc->sc_ports[i].rp_dac_type = RADEON_DAC_UNKNOWN; 1456 sc->sc_ports[i].rp_conn_type = RADEON_CONN_NONE; 1457 sc->sc_ports[i].rp_tmds_type = RADEON_TMDS_UNKNOWN; 1458 } 1459 1460 /* 1461 * This logic is borrowed from Xorg's radeon driver. 1462 */ 1463 if (!sc->sc_biossz) 1464 goto nobios; 1465 1466 if (IS_ATOM(sc)) { 1467 /* not done yet */ 1468 } else { 1469 uint16_t ptr; 1470 int port = 0; 1471 1472 ptr = GETBIOS16(sc, 0x48); 1473 ptr = GETBIOS16(sc, ptr + 0x50); 1474 for (i = 1; i < 4; i++) { 1475 uint16_t entry; 1476 uint8_t conn, ddc, dac, tmds; 1477 1478 /* 1479 * Parse the connector table. From reading the code, 1480 * it appears to made up of 16-bit entries for each 1481 * connector. The 16-bits are defined as: 1482 * 1483 * bits 12-15 - connector type (0 == end of table) 1484 * bits 8-11 - DDC type 1485 * bits 5-7 - ??? 1486 * bit 4 - TMDS type (1 = EXT, 0 = INT) 1487 * bits 1-3 - ??? 1488 * bit 0 - DAC, 1 = TVDAC, 0 = primary 1489 */ 1490 if (!GETBIOS8(sc, ptr + i * 2) && i > 1) 1491 break; 1492 entry = GETBIOS16(sc, ptr + i * 2); 1493 1494 conn = (entry >> 12) & 0xf; 1495 ddc = (entry >> 8) & 0xf; 1496 dac = (entry & 0x1) ? RADEON_DAC_TVDAC : 1497 RADEON_DAC_PRIMARY; 1498 tmds = ((entry >> 4) & 0x1) ? RADEON_TMDS_EXT : 1499 RADEON_TMDS_INT; 1500 1501 if (conn == RADEON_CONN_NONE) 1502 continue; /* no connector */ 1503 1504 if ((found > 0) && 1505 (sc->sc_ports[port].rp_ddc_type == ddc)) { 1506 /* duplicate entry for same connector */ 1507 continue; 1508 } 1509 1510 /* internal DDC_DVI port gets priority */ 1511 if ((ddc == RADEON_DDC_DVI) || (port == 1)) 1512 port = 0; 1513 else 1514 port = 1; 1515 1516 sc->sc_ports[port].rp_ddc_type = 1517 ddc > RADEON_DDC_CRT2 ? RADEON_DDC_NONE : ddc; 1518 sc->sc_ports[port].rp_dac_type = dac; 1519 sc->sc_ports[port].rp_conn_type = 1520 min(conn, RADEON_CONN_UNSUPPORTED) ; 1521 1522 sc->sc_ports[port].rp_tmds_type = tmds; 1523 1524 if ((conn != RADEON_CONN_DVI_I) && 1525 (conn != RADEON_CONN_DVI_D) && 1526 (tmds == RADEON_TMDS_INT)) 1527 sc->sc_ports[port].rp_tmds_type = 1528 RADEON_TMDS_UNKNOWN; 1529 1530 found += (port + 1); 1531 } 1532 } 1533 1534 nobios: 1535 if (!found) { 1536 DPRINTF(("No connector info in BIOS!\n")); 1537 /* default, port 0 = internal TMDS, port 1 = CRT */ 1538 sc->sc_ports[0].rp_mon_type = RADEON_MT_UNKNOWN; 1539 sc->sc_ports[0].rp_ddc_type = RADEON_DDC_DVI; 1540 sc->sc_ports[0].rp_dac_type = RADEON_DAC_TVDAC; 1541 sc->sc_ports[0].rp_conn_type = RADEON_CONN_DVI_D; 1542 sc->sc_ports[0].rp_tmds_type = RADEON_TMDS_INT; 1543 1544 sc->sc_ports[1].rp_mon_type = RADEON_MT_UNKNOWN; 1545 sc->sc_ports[1].rp_ddc_type = RADEON_DDC_VGA; 1546 sc->sc_ports[1].rp_dac_type = RADEON_DAC_PRIMARY; 1547 sc->sc_ports[1].rp_conn_type = RADEON_CONN_CRT; 1548 sc->sc_ports[1].rp_tmds_type = RADEON_TMDS_EXT; 1549 } 1550 1551 /* 1552 * Fixup for RS300/RS350/RS400 chips, that lack a primary DAC. 1553 * these chips should use TVDAC for the VGA port. 1554 */ 1555 if (HAS_SDAC(sc)) { 1556 if (sc->sc_ports[0].rp_conn_type == RADEON_CONN_CRT) { 1557 sc->sc_ports[0].rp_dac_type = RADEON_DAC_TVDAC; 1558 sc->sc_ports[1].rp_dac_type = RADEON_DAC_PRIMARY; 1559 } else { 1560 sc->sc_ports[1].rp_dac_type = RADEON_DAC_TVDAC; 1561 sc->sc_ports[0].rp_dac_type = RADEON_DAC_PRIMARY; 1562 } 1563 } else if (!HAS_CRTC2(sc)) { 1564 sc->sc_ports[0].rp_dac_type = RADEON_DAC_PRIMARY; 1565 } 1566 1567 for (i = 0; i < 2; i++) { 1568 char edid[128]; 1569 uint8_t ddc; 1570 struct edid_info *eip = &sc->sc_ports[i].rp_edid; 1571 prop_data_t edid_data; 1572 1573 DPRINTF(("Port #%d:\n", i)); 1574 DPRINTF((" conn = %d\n", sc->sc_ports[i].rp_conn_type)); 1575 DPRINTF((" ddc = %d\n", sc->sc_ports[i].rp_ddc_type)); 1576 DPRINTF((" dac = %d\n", sc->sc_ports[i].rp_dac_type)); 1577 DPRINTF((" tmds = %d\n", sc->sc_ports[i].rp_tmds_type)); 1578 1579 sc->sc_ports[i].rp_edid_valid = 0; 1580 /* first look for static EDID data */ 1581 if ((edid_data = prop_dictionary_get(device_properties( 1582 &sc->sc_dev), "EDID")) != NULL) { 1583 1584 aprint_normal("%s: using static EDID\n", 1585 sc->sc_dev.dv_xname); 1586 memcpy(edid, prop_data_data_nocopy(edid_data), 128); 1587 if (edid_parse(edid, eip) == 0) { 1588 1589 sc->sc_ports[i].rp_edid_valid = 1; 1590 edid_print(eip); 1591 } 1592 } 1593 /* if we didn't find any we'll try to talk to the monitor */ 1594 if (sc->sc_ports[i].rp_edid_valid != 1) { 1595 1596 ddc = sc->sc_ports[i].rp_ddc_type; 1597 if (ddc != RADEON_DDC_NONE) { 1598 if ((radeonfb_i2c_read_edid(sc, ddc, edid) 1599 == 0) && (edid_parse(edid, eip) == 0)) { 1600 1601 sc->sc_ports[i].rp_edid_valid = 1; 1602 edid_print(eip); 1603 } 1604 } 1605 } 1606 } 1607 1608 return found; 1609 } 1610 1611 int 1612 radeonfb_gettmds(struct radeonfb_softc *sc) 1613 { 1614 int i; 1615 1616 if (!sc->sc_biossz) { 1617 goto nobios; 1618 } 1619 1620 if (IS_ATOM(sc)) { 1621 /* XXX: not done yet */ 1622 } else { 1623 uint16_t ptr; 1624 int n; 1625 1626 ptr = GETBIOS16(sc, 0x48); 1627 ptr = GETBIOS16(sc, ptr + 0x34); 1628 DPRINTF(("DFP table revision %d\n", GETBIOS8(sc, ptr))); 1629 if (GETBIOS8(sc, ptr) == 3) { 1630 /* revision three table */ 1631 n = GETBIOS8(sc, ptr + 5) + 1; 1632 n = min(n, 4); 1633 1634 memset(sc->sc_tmds_pll, 0, sizeof (sc->sc_tmds_pll)); 1635 for (i = 0; i < n; i++) { 1636 sc->sc_tmds_pll[i].rtp_pll = GETBIOS32(sc, 1637 ptr + i * 10 + 8); 1638 sc->sc_tmds_pll[i].rtp_freq = GETBIOS16(sc, 1639 ptr + i * 10 + 0x10); 1640 DPRINTF(("TMDS_PLL dot clock %d pll %x\n", 1641 sc->sc_tmds_pll[i].rtp_freq, 1642 sc->sc_tmds_pll[i].rtp_pll)); 1643 } 1644 return 0; 1645 } 1646 } 1647 1648 nobios: 1649 DPRINTF(("no suitable DFP table present\n")); 1650 for (i = 0; 1651 i < sizeof (radeonfb_tmds_pll) / sizeof (radeonfb_tmds_pll[0]); 1652 i++) { 1653 int j; 1654 1655 if (radeonfb_tmds_pll[i].family != sc->sc_family) 1656 continue; 1657 1658 for (j = 0; j < 4; j++) { 1659 sc->sc_tmds_pll[j] = radeonfb_tmds_pll[i].plls[j]; 1660 DPRINTF(("TMDS_PLL dot clock %d pll %x\n", 1661 sc->sc_tmds_pll[j].rtp_freq, 1662 sc->sc_tmds_pll[j].rtp_pll)); 1663 } 1664 return 0; 1665 } 1666 1667 return -1; 1668 } 1669 1670 const struct videomode * 1671 radeonfb_modelookup(const char *name) 1672 { 1673 int i; 1674 1675 for (i = 0; i < videomode_count; i++) 1676 if (!strcmp(name, videomode_list[i].name)) 1677 return &videomode_list[i]; 1678 1679 return NULL; 1680 } 1681 1682 void 1683 radeonfb_pllwriteupdate(struct radeonfb_softc *sc, int crtc) 1684 { 1685 if (crtc) { 1686 while (GETPLL(sc, RADEON_P2PLL_REF_DIV) & 1687 RADEON_P2PLL_ATOMIC_UPDATE_R); 1688 SETPLL(sc, RADEON_P2PLL_REF_DIV, RADEON_P2PLL_ATOMIC_UPDATE_W); 1689 } else { 1690 while (GETPLL(sc, RADEON_PPLL_REF_DIV) & 1691 RADEON_PPLL_ATOMIC_UPDATE_R); 1692 SETPLL(sc, RADEON_PPLL_REF_DIV, RADEON_PPLL_ATOMIC_UPDATE_W); 1693 } 1694 } 1695 1696 void 1697 radeonfb_pllwaitatomicread(struct radeonfb_softc *sc, int crtc) 1698 { 1699 int i; 1700 1701 for (i = 10000; i; i--) { 1702 if (crtc) { 1703 if (GETPLL(sc, RADEON_P2PLL_REF_DIV) & 1704 RADEON_P2PLL_ATOMIC_UPDATE_R) 1705 break; 1706 } else { 1707 if (GETPLL(sc, RADEON_PPLL_REF_DIV) & 1708 RADEON_PPLL_ATOMIC_UPDATE_R) 1709 break; 1710 } 1711 } 1712 } 1713 1714 void 1715 radeonfb_program_vclk(struct radeonfb_softc *sc, int dotclock, int crtc) 1716 { 1717 uint32_t pbit = 0; 1718 uint32_t feed = 0; 1719 uint32_t data; 1720 #if 1 1721 int i; 1722 #endif 1723 1724 radeonfb_calc_dividers(sc, dotclock, &pbit, &feed); 1725 1726 if (crtc == 0) { 1727 1728 /* XXXX: mobility workaround missing */ 1729 /* XXXX: R300 stuff missing */ 1730 1731 PATCHPLL(sc, RADEON_VCLK_ECP_CNTL, 1732 RADEON_VCLK_SRC_SEL_CPUCLK, 1733 ~RADEON_VCLK_SRC_SEL_MASK); 1734 1735 /* put vclk into reset, use atomic updates */ 1736 SETPLL(sc, RADEON_PPLL_CNTL, 1737 RADEON_PPLL_REFCLK_SEL | 1738 RADEON_PPLL_FBCLK_SEL | 1739 RADEON_PPLL_RESET | 1740 RADEON_PPLL_ATOMIC_UPDATE_EN | 1741 RADEON_PPLL_VGA_ATOMIC_UPDATE_EN); 1742 1743 /* select clock 3 */ 1744 #if 0 1745 PATCH32(sc, RADEON_CLOCK_CNTL_INDEX, RADEON_PLL_DIV_SEL, 1746 ~RADEON_PLL_DIV_SEL); 1747 #else 1748 PATCH32(sc, RADEON_CLOCK_CNTL_INDEX, 0, 1749 ~RADEON_PLL_DIV_SEL); 1750 #endif 1751 1752 /* XXX: R300 family -- program divider differently? */ 1753 1754 /* program reference divider */ 1755 PATCHPLL(sc, RADEON_PPLL_REF_DIV, sc->sc_refdiv, 1756 ~RADEON_PPLL_REF_DIV_MASK); 1757 PRINTPLL(RADEON_PPLL_REF_DIV); 1758 1759 #if 0 1760 data = GETPLL(sc, RADEON_PPLL_DIV_3); 1761 data &= ~(RADEON_PPLL_FB3_DIV_MASK | 1762 RADEON_PPLL_POST3_DIV_MASK); 1763 data |= pbit; 1764 data |= (feed & RADEON_PPLL_FB3_DIV_MASK); 1765 PUTPLL(sc, RADEON_PPLL_DIV_3, data); 1766 #else 1767 for (i = 0; i < 4; i++) { 1768 } 1769 #endif 1770 1771 /* use the atomic update */ 1772 radeonfb_pllwriteupdate(sc, crtc); 1773 1774 /* and wait for it to complete */ 1775 radeonfb_pllwaitatomicread(sc, crtc); 1776 1777 /* program HTOTAL (why?) */ 1778 PUTPLL(sc, RADEON_HTOTAL_CNTL, 0); 1779 1780 /* drop reset */ 1781 CLRPLL(sc, RADEON_PPLL_CNTL, 1782 RADEON_PPLL_RESET | RADEON_PPLL_SLEEP | 1783 RADEON_PPLL_ATOMIC_UPDATE_EN | 1784 RADEON_PPLL_VGA_ATOMIC_UPDATE_EN); 1785 1786 PRINTPLL(RADEON_PPLL_CNTL); 1787 1788 /* give clock time to lock */ 1789 delay(50000); 1790 1791 PATCHPLL(sc, RADEON_VCLK_ECP_CNTL, 1792 RADEON_VCLK_SRC_SEL_PPLLCLK, 1793 ~RADEON_VCLK_SRC_SEL_MASK); 1794 1795 } else { 1796 1797 PATCHPLL(sc, RADEON_PIXCLKS_CNTL, 1798 RADEON_PIX2CLK_SRC_SEL_CPUCLK, 1799 ~RADEON_PIX2CLK_SRC_SEL_MASK); 1800 1801 /* put vclk into reset, use atomic updates */ 1802 SETPLL(sc, RADEON_P2PLL_CNTL, 1803 RADEON_P2PLL_RESET | 1804 RADEON_P2PLL_ATOMIC_UPDATE_EN | 1805 RADEON_P2PLL_VGA_ATOMIC_UPDATE_EN); 1806 1807 /* XXX: R300 family -- program divider differently? */ 1808 1809 /* program reference divider */ 1810 PATCHPLL(sc, RADEON_P2PLL_REF_DIV, sc->sc_refdiv, 1811 ~RADEON_P2PLL_REF_DIV_MASK); 1812 1813 /* program feedback and post dividers */ 1814 data = GETPLL(sc, RADEON_P2PLL_DIV_0); 1815 data &= ~(RADEON_P2PLL_FB0_DIV_MASK | 1816 RADEON_P2PLL_POST0_DIV_MASK); 1817 data |= pbit; 1818 data |= (feed & RADEON_P2PLL_FB0_DIV_MASK); 1819 PUTPLL(sc, RADEON_P2PLL_DIV_0, data); 1820 1821 /* use the atomic update */ 1822 radeonfb_pllwriteupdate(sc, crtc); 1823 1824 /* and wait for it to complete */ 1825 radeonfb_pllwaitatomicread(sc, crtc); 1826 1827 /* program HTOTAL (why?) */ 1828 PUTPLL(sc, RADEON_HTOTAL2_CNTL, 0); 1829 1830 /* drop reset */ 1831 CLRPLL(sc, RADEON_P2PLL_CNTL, 1832 RADEON_P2PLL_RESET | RADEON_P2PLL_SLEEP | 1833 RADEON_P2PLL_ATOMIC_UPDATE_EN | 1834 RADEON_P2PLL_VGA_ATOMIC_UPDATE_EN); 1835 1836 /* allow time for clock to lock */ 1837 delay(50000); 1838 1839 PATCHPLL(sc, RADEON_PIXCLKS_CNTL, 1840 RADEON_PIX2CLK_SRC_SEL_P2PLLCLK, 1841 ~RADEON_PIX2CLK_SRC_SEL_MASK); 1842 } 1843 PRINTREG(RADEON_CRTC_MORE_CNTL); 1844 } 1845 1846 void 1847 radeonfb_modeswitch(struct radeonfb_display *dp) 1848 { 1849 struct radeonfb_softc *sc = dp->rd_softc; 1850 int i; 1851 1852 /* blank the display while we switch modes */ 1853 //radeonfb_blank(dp, 1); 1854 1855 #if 0 1856 SET32(sc, RADEON_CRTC_EXT_CNTL, 1857 RADEON_CRTC_VSYNC_DIS | RADEON_CRTC_HSYNC_DIS | 1858 RADEON_CRTC_DISPLAY_DIS /* | RADEON_CRTC_DISP_REQ_EN_B */); 1859 #endif 1860 1861 /* these registers might get in the way... */ 1862 PUT32(sc, RADEON_OVR_CLR, 0); 1863 PUT32(sc, RADEON_OVR_WID_LEFT_RIGHT, 0); 1864 PUT32(sc, RADEON_OVR_WID_TOP_BOTTOM, 0); 1865 PUT32(sc, RADEON_OV0_SCALE_CNTL, 0); 1866 PUT32(sc, RADEON_SUBPIC_CNTL, 0); 1867 PUT32(sc, RADEON_VIPH_CONTROL, 0); 1868 PUT32(sc, RADEON_I2C_CNTL_1, 0); 1869 PUT32(sc, RADEON_GEN_INT_CNTL, 0); 1870 PUT32(sc, RADEON_CAP0_TRIG_CNTL, 0); 1871 PUT32(sc, RADEON_CAP1_TRIG_CNTL, 0); 1872 PUT32(sc, RADEON_SURFACE_CNTL, 0); 1873 1874 for (i = 0; i < dp->rd_ncrtcs; i++) 1875 radeonfb_setcrtc(dp, i); 1876 1877 /* activate the display */ 1878 //radeonfb_blank(dp, 0); 1879 } 1880 1881 void 1882 radeonfb_setcrtc(struct radeonfb_display *dp, int index) 1883 { 1884 int crtc; 1885 struct videomode *mode; 1886 struct radeonfb_softc *sc; 1887 struct radeonfb_crtc *cp; 1888 uint32_t v; 1889 uint32_t gencntl; 1890 uint32_t htotaldisp; 1891 uint32_t hsyncstrt; 1892 uint32_t vtotaldisp; 1893 uint32_t vsyncstrt; 1894 uint32_t fphsyncstrt; 1895 uint32_t fpvsyncstrt; 1896 uint32_t fphtotaldisp; 1897 uint32_t fpvtotaldisp; 1898 uint32_t pitch; 1899 1900 sc = dp->rd_softc; 1901 cp = &dp->rd_crtcs[index]; 1902 crtc = cp->rc_number; 1903 mode = &cp->rc_videomode; 1904 1905 #if 1 1906 pitch = (((dp->rd_virtx * dp->rd_bpp) + ((dp->rd_bpp * 8) - 1)) / 1907 (dp->rd_bpp * 8)); 1908 #else 1909 pitch = (((sc->sc_maxx * sc->sc_maxbpp) + ((sc->sc_maxbpp * 8) - 1)) / 1910 (sc->sc_maxbpp * 8)); 1911 #endif 1912 //pitch = pitch | (pitch << 16); 1913 1914 switch (crtc) { 1915 case 0: 1916 gencntl = RADEON_CRTC_GEN_CNTL; 1917 htotaldisp = RADEON_CRTC_H_TOTAL_DISP; 1918 hsyncstrt = RADEON_CRTC_H_SYNC_STRT_WID; 1919 vtotaldisp = RADEON_CRTC_V_TOTAL_DISP; 1920 vsyncstrt = RADEON_CRTC_V_SYNC_STRT_WID; 1921 fpvsyncstrt = RADEON_FP_V_SYNC_STRT_WID; 1922 fphsyncstrt = RADEON_FP_H_SYNC_STRT_WID; 1923 fpvtotaldisp = RADEON_FP_CRTC_V_TOTAL_DISP; 1924 fphtotaldisp = RADEON_FP_CRTC_H_TOTAL_DISP; 1925 break; 1926 case 1: 1927 gencntl = RADEON_CRTC2_GEN_CNTL; 1928 htotaldisp = RADEON_CRTC2_H_TOTAL_DISP; 1929 hsyncstrt = RADEON_CRTC2_H_SYNC_STRT_WID; 1930 vtotaldisp = RADEON_CRTC2_V_TOTAL_DISP; 1931 vsyncstrt = RADEON_CRTC2_V_SYNC_STRT_WID; 1932 fpvsyncstrt = RADEON_FP_V2_SYNC_STRT_WID; 1933 fphsyncstrt = RADEON_FP_H2_SYNC_STRT_WID; 1934 fpvtotaldisp = RADEON_FP_CRTC2_V_TOTAL_DISP; 1935 fphtotaldisp = RADEON_FP_CRTC2_H_TOTAL_DISP; 1936 break; 1937 default: 1938 panic("Bad CRTC!"); 1939 break; 1940 } 1941 1942 /* 1943 * CRTC_GEN_CNTL - depth, accelerator mode, etc. 1944 */ 1945 /* only bother with 32bpp and 8bpp */ 1946 v = dp->rd_format << RADEON_CRTC_PIX_WIDTH_SHIFT; 1947 1948 if (crtc == 1) { 1949 v |= RADEON_CRTC2_CRT2_ON | RADEON_CRTC2_EN; 1950 } else { 1951 v |= RADEON_CRTC_EXT_DISP_EN | RADEON_CRTC_EN; 1952 } 1953 1954 if (mode->flags & VID_DBLSCAN) 1955 v |= RADEON_CRTC2_DBL_SCAN_EN; 1956 1957 if (mode->flags & VID_INTERLACE) 1958 v |= RADEON_CRTC2_INTERLACE_EN; 1959 1960 if (mode->flags & VID_CSYNC) { 1961 v |= RADEON_CRTC2_CSYNC_EN; 1962 if (crtc == 1) 1963 v |= RADEON_CRTC2_VSYNC_TRISTAT; 1964 } 1965 1966 PUT32(sc, gencntl, v); 1967 DPRINTF(("CRTC%s_GEN_CNTL = %08x\n", crtc ? "2" : "", v)); 1968 1969 /* 1970 * CRTC_EXT_CNTL - preserve disable flags, set ATI linear and EXT_CNT 1971 */ 1972 v = GET32(sc, RADEON_CRTC_EXT_CNTL); 1973 if (crtc == 0) { 1974 v &= (RADEON_CRTC_VSYNC_DIS | RADEON_CRTC_HSYNC_DIS | 1975 RADEON_CRTC_DISPLAY_DIS); 1976 v |= RADEON_XCRT_CNT_EN | RADEON_VGA_ATI_LINEAR; 1977 if (mode->flags & VID_CSYNC) 1978 v |= RADEON_CRTC_VSYNC_TRISTAT; 1979 } 1980 /* unconditional turn on CRT, in case first CRTC is DFP */ 1981 v |= RADEON_CRTC_CRT_ON; 1982 PUT32(sc, RADEON_CRTC_EXT_CNTL, v); 1983 PRINTREG(RADEON_CRTC_EXT_CNTL); 1984 1985 /* 1986 * H_TOTAL_DISP 1987 */ 1988 v = ((mode->hdisplay / 8) - 1) << 16; 1989 v |= (mode->htotal / 8) - 1; 1990 PUT32(sc, htotaldisp, v); 1991 DPRINTF(("CRTC%s_H_TOTAL_DISP = %08x\n", crtc ? "2" : "", v)); 1992 PUT32(sc, fphtotaldisp, v); 1993 DPRINTF(("FP_H%s_TOTAL_DISP = %08x\n", crtc ? "2" : "", v)); 1994 1995 /* 1996 * H_SYNC_STRT_WID 1997 */ 1998 v = (((mode->hsync_end - mode->hsync_start) / 8) << 16); 1999 v |= mode->hsync_start; 2000 if (mode->flags & VID_NHSYNC) 2001 v |= RADEON_CRTC_H_SYNC_POL; 2002 PUT32(sc, hsyncstrt, v); 2003 DPRINTF(("CRTC%s_H_SYNC_STRT_WID = %08x\n", crtc ? "2" : "", v)); 2004 PUT32(sc, fphsyncstrt, v); 2005 DPRINTF(("FP_H%s_SYNC_STRT_WID = %08x\n", crtc ? "2" : "", v)); 2006 2007 /* 2008 * V_TOTAL_DISP 2009 */ 2010 v = ((mode->vdisplay - 1) << 16); 2011 v |= (mode->vtotal - 1); 2012 PUT32(sc, vtotaldisp, v); 2013 DPRINTF(("CRTC%s_V_TOTAL_DISP = %08x\n", crtc ? "2" : "", v)); 2014 PUT32(sc, fpvtotaldisp, v); 2015 DPRINTF(("FP_V%s_TOTAL_DISP = %08x\n", crtc ? "2" : "", v)); 2016 2017 /* 2018 * V_SYNC_STRT_WID 2019 */ 2020 v = ((mode->vsync_end - mode->vsync_start) << 16); 2021 v |= (mode->vsync_start - 1); 2022 if (mode->flags & VID_NVSYNC) 2023 v |= RADEON_CRTC_V_SYNC_POL; 2024 PUT32(sc, vsyncstrt, v); 2025 DPRINTF(("CRTC%s_V_SYNC_STRT_WID = %08x\n", crtc ? "2" : "", v)); 2026 PUT32(sc, fpvsyncstrt, v); 2027 DPRINTF(("FP_V%s_SYNC_STRT_WID = %08x\n", crtc ? "2" : "", v)); 2028 2029 radeonfb_program_vclk(sc, mode->dot_clock, crtc); 2030 2031 switch (crtc) { 2032 case 0: 2033 PUT32(sc, RADEON_CRTC_OFFSET, 0); 2034 PUT32(sc, RADEON_CRTC_OFFSET_CNTL, 0); 2035 PUT32(sc, RADEON_CRTC_PITCH, pitch); 2036 CLR32(sc, RADEON_DISP_MERGE_CNTL, RADEON_DISP_RGB_OFFSET_EN); 2037 2038 CLR32(sc, RADEON_CRTC_EXT_CNTL, 2039 RADEON_CRTC_VSYNC_DIS | RADEON_CRTC_HSYNC_DIS | 2040 RADEON_CRTC_DISPLAY_DIS /* | RADEON_CRTC_DISP_REQ_EN_B */); 2041 CLR32(sc, RADEON_CRTC_GEN_CNTL, RADEON_CRTC_DISP_REQ_EN_B); 2042 PRINTREG(RADEON_CRTC_EXT_CNTL); 2043 PRINTREG(RADEON_CRTC_GEN_CNTL); 2044 PRINTREG(RADEON_CLOCK_CNTL_INDEX); 2045 break; 2046 2047 case 1: 2048 PUT32(sc, RADEON_CRTC2_OFFSET, 0); 2049 PUT32(sc, RADEON_CRTC2_OFFSET_CNTL, 0); 2050 PUT32(sc, RADEON_CRTC2_PITCH, pitch); 2051 CLR32(sc, RADEON_DISP2_MERGE_CNTL, RADEON_DISP2_RGB_OFFSET_EN); 2052 CLR32(sc, RADEON_CRTC2_GEN_CNTL, 2053 RADEON_CRTC2_VSYNC_DIS | 2054 RADEON_CRTC2_HSYNC_DIS | 2055 RADEON_CRTC2_DISP_DIS | RADEON_CRTC2_DISP_REQ_EN_B); 2056 PRINTREG(RADEON_CRTC2_GEN_CNTL); 2057 break; 2058 } 2059 } 2060 2061 int 2062 radeonfb_isblank(struct radeonfb_display *dp) 2063 { 2064 uint32_t reg, mask; 2065 2066 if (dp->rd_crtcs[0].rc_number) { 2067 reg = RADEON_CRTC2_GEN_CNTL; 2068 mask = RADEON_CRTC2_DISP_DIS; 2069 } else { 2070 reg = RADEON_CRTC_EXT_CNTL; 2071 mask = RADEON_CRTC_DISPLAY_DIS; 2072 } 2073 return ((GET32(dp->rd_softc, reg) & mask) ? 1 : 0); 2074 } 2075 2076 void 2077 radeonfb_blank(struct radeonfb_display *dp, int blank) 2078 { 2079 struct radeonfb_softc *sc = dp->rd_softc; 2080 uint32_t reg, mask; 2081 uint32_t fpreg, fpval; 2082 int i; 2083 2084 for (i = 0; i < dp->rd_ncrtcs; i++) { 2085 2086 if (dp->rd_crtcs[i].rc_number) { 2087 reg = RADEON_CRTC2_GEN_CNTL; 2088 mask = RADEON_CRTC2_DISP_DIS; 2089 fpreg = RADEON_FP2_GEN_CNTL; 2090 fpval = RADEON_FP2_ON; 2091 } else { 2092 reg = RADEON_CRTC_EXT_CNTL; 2093 mask = RADEON_CRTC_DISPLAY_DIS; 2094 fpreg = RADEON_FP_GEN_CNTL; 2095 fpval = RADEON_FP_FPON; 2096 } 2097 2098 if (blank) { 2099 SET32(sc, reg, mask); 2100 CLR32(sc, fpreg, fpval); 2101 } else { 2102 CLR32(sc, reg, mask); 2103 SET32(sc, fpreg, fpval); 2104 } 2105 } 2106 PRINTREG(RADEON_FP_GEN_CNTL); 2107 PRINTREG(RADEON_FP2_GEN_CNTL); 2108 } 2109 2110 void 2111 radeonfb_init_screen(void *cookie, struct vcons_screen *scr, int existing, 2112 long *defattr) 2113 { 2114 struct radeonfb_display *dp = cookie; 2115 struct rasops_info *ri = &scr->scr_ri; 2116 2117 /* initialize font subsystem */ 2118 wsfont_init(); 2119 2120 DPRINTF(("init screen called, existing %d\n", existing)); 2121 2122 ri->ri_depth = dp->rd_bpp; 2123 ri->ri_width = dp->rd_virtx; 2124 ri->ri_height = dp->rd_virty; 2125 ri->ri_stride = dp->rd_stride; 2126 ri->ri_flg = RI_CENTER; 2127 ri->ri_bits = (void *)dp->rd_fbptr; 2128 2129 /* XXX: 32 bpp only */ 2130 /* this is rgb in "big-endian order..." */ 2131 ri->ri_rnum = 8; 2132 ri->ri_gnum = 8; 2133 ri->ri_bnum = 8; 2134 ri->ri_rpos = 16; 2135 ri->ri_gpos = 8; 2136 ri->ri_bpos = 0; 2137 2138 if (existing) { 2139 ri->ri_flg |= RI_CLEAR; 2140 2141 /* start a modeswitch now */ 2142 radeonfb_modeswitch(dp); 2143 } 2144 2145 /* 2146 * XXX: font selection should be based on properties, with some 2147 * normal/reasonable default. 2148 */ 2149 ri->ri_caps = WSSCREEN_WSCOLORS; 2150 2151 /* initialize and look for an initial font */ 2152 rasops_init(ri, dp->rd_virty/8, dp->rd_virtx/8); 2153 2154 rasops_reconfig(ri, dp->rd_virty / ri->ri_font->fontheight, 2155 dp->rd_virtx / ri->ri_font->fontwidth); 2156 2157 /* enable acceleration */ 2158 ri->ri_ops.copyrows = radeonfb_copyrows; 2159 ri->ri_ops.copycols = radeonfb_copycols; 2160 ri->ri_ops.eraserows = radeonfb_eraserows; 2161 ri->ri_ops.erasecols = radeonfb_erasecols; 2162 ri->ri_ops.allocattr = radeonfb_allocattr; 2163 if (!IS_R300(dp->rd_softc)) { 2164 ri->ri_ops.putchar = radeonfb_putchar; 2165 } 2166 ri->ri_ops.cursor = radeonfb_cursor; 2167 } 2168 2169 void 2170 radeonfb_set_fbloc(struct radeonfb_softc *sc) 2171 { 2172 uint32_t gen, ext, gen2 = 0; 2173 uint32_t agploc, aperbase, apersize, mcfbloc; 2174 2175 gen = GET32(sc, RADEON_CRTC_GEN_CNTL); 2176 ext = GET32(sc, RADEON_CRTC_EXT_CNTL); 2177 agploc = GET32(sc, RADEON_MC_AGP_LOCATION); 2178 aperbase = GET32(sc, RADEON_CONFIG_APER_0_BASE); 2179 apersize = GET32(sc, RADEON_CONFIG_APER_SIZE); 2180 2181 PUT32(sc, RADEON_CRTC_GEN_CNTL, gen | RADEON_CRTC_DISP_REQ_EN_B); 2182 PUT32(sc, RADEON_CRTC_EXT_CNTL, ext | RADEON_CRTC_DISPLAY_DIS); 2183 //PUT32(sc, RADEON_CRTC_GEN_CNTL, gen | RADEON_CRTC_DISPLAY_DIS); 2184 //PUT32(sc, RADEON_CRTC_EXT_CNTL, ext | RADEON_CRTC_DISP_REQ_EN_B); 2185 2186 if (HAS_CRTC2(sc)) { 2187 gen2 = GET32(sc, RADEON_CRTC2_GEN_CNTL); 2188 PUT32(sc, RADEON_CRTC2_GEN_CNTL, 2189 gen2 | RADEON_CRTC2_DISP_REQ_EN_B); 2190 } 2191 2192 delay(100000); 2193 2194 mcfbloc = (aperbase >> 16) | 2195 ((aperbase + (apersize - 1)) & 0xffff0000); 2196 2197 sc->sc_aperbase = (mcfbloc & 0xffff) << 16; 2198 sc->sc_memsz = apersize; 2199 2200 if (((agploc & 0xffff) << 16) != 2201 ((mcfbloc & 0xffff0000U) + 0x10000)) { 2202 agploc = mcfbloc & 0xffff0000U; 2203 agploc |= ((agploc + 0x10000) >> 16); 2204 } 2205 2206 PUT32(sc, RADEON_HOST_PATH_CNTL, 0); 2207 2208 PUT32(sc, RADEON_MC_FB_LOCATION, mcfbloc); 2209 PUT32(sc, RADEON_MC_AGP_LOCATION, agploc); 2210 2211 DPRINTF(("aperbase = %u\n", aperbase)); 2212 PRINTREG(RADEON_MC_FB_LOCATION); 2213 PRINTREG(RADEON_MC_AGP_LOCATION); 2214 2215 PUT32(sc, RADEON_DISPLAY_BASE_ADDR, sc->sc_aperbase); 2216 2217 if (HAS_CRTC2(sc)) 2218 PUT32(sc, RADEON_DISPLAY2_BASE_ADDR, sc->sc_aperbase); 2219 2220 PUT32(sc, RADEON_OV0_BASE_ADDR, sc->sc_aperbase); 2221 2222 #if 0 2223 /* XXX: what is this AGP garbage? :-) */ 2224 PUT32(sc, RADEON_AGP_CNTL, 0x00100000); 2225 #endif 2226 2227 delay(100000); 2228 2229 PUT32(sc, RADEON_CRTC_GEN_CNTL, gen); 2230 PUT32(sc, RADEON_CRTC_EXT_CNTL, ext); 2231 2232 if (HAS_CRTC2(sc)) 2233 PUT32(sc, RADEON_CRTC2_GEN_CNTL, gen2); 2234 } 2235 2236 void 2237 radeonfb_init_misc(struct radeonfb_softc *sc) 2238 { 2239 PUT32(sc, RADEON_BUS_CNTL, 2240 RADEON_BUS_MASTER_DIS | 2241 RADEON_BUS_PREFETCH_MODE_ACT | 2242 RADEON_BUS_PCI_READ_RETRY_EN | 2243 RADEON_BUS_PCI_WRT_RETRY_EN | 2244 (3 << RADEON_BUS_RETRY_WS_SHIFT) | 2245 RADEON_BUS_MSTR_RD_MULT | 2246 RADEON_BUS_MSTR_RD_LINE | 2247 RADEON_BUS_RD_DISCARD_EN | 2248 RADEON_BUS_MSTR_DISCONNECT_EN | 2249 RADEON_BUS_READ_BURST); 2250 2251 PUT32(sc, RADEON_BUS_CNTL1, 0xf0); 2252 /* PUT32(sc, RADEON_SEPROM_CNTL1, 0x09ff0000); */ 2253 PUT32(sc, RADEON_FCP_CNTL, RADEON_FCP0_SRC_GND); 2254 PUT32(sc, RADEON_RBBM_CNTL, 2255 (3 << RADEON_RB_SETTLE_SHIFT) | 2256 (4 << RADEON_ABORTCLKS_HI_SHIFT) | 2257 (4 << RADEON_ABORTCLKS_CP_SHIFT) | 2258 (4 << RADEON_ABORTCLKS_CFIFO_SHIFT)); 2259 2260 /* XXX: figure out what these mean! */ 2261 PUT32(sc, RADEON_AGP_CNTL, 0x00100000); 2262 PUT32(sc, RADEON_HOST_PATH_CNTL, 0); 2263 //PUT32(sc, RADEON_DISP_MISC_CNTL, 0x5bb00400); 2264 2265 PUT32(sc, RADEON_GEN_INT_CNTL, 0); 2266 PUT32(sc, RADEON_GEN_INT_STATUS, GET32(sc, RADEON_GEN_INT_STATUS)); 2267 } 2268 2269 /* 2270 * This loads a linear color map for true color. 2271 */ 2272 void 2273 radeonfb_init_palette(struct radeonfb_softc *sc, int crtc) 2274 { 2275 int i; 2276 uint32_t vclk; 2277 2278 #define DAC_WIDTH ((1 << 10) - 1) 2279 #define CLUT_WIDTH ((1 << 8) - 1) 2280 #define CLUT_COLOR(i) ((i * DAC_WIDTH * 2 / CLUT_WIDTH + 1) / 2) 2281 2282 vclk = GETPLL(sc, RADEON_VCLK_ECP_CNTL); 2283 PUTPLL(sc, RADEON_VCLK_ECP_CNTL, vclk & ~RADEON_PIXCLK_DAC_ALWAYS_ONb); 2284 2285 if (crtc) 2286 SET32(sc, RADEON_DAC_CNTL2, RADEON_DAC2_PALETTE_ACC_CTL); 2287 else 2288 CLR32(sc, RADEON_DAC_CNTL2, RADEON_DAC2_PALETTE_ACC_CTL); 2289 2290 PUT32(sc, RADEON_PALETTE_INDEX, 0); 2291 for (i = 0; i <= CLUT_WIDTH; ++i) { 2292 PUT32(sc, RADEON_PALETTE_30_DATA, 2293 (CLUT_COLOR(i) << 10) | 2294 (CLUT_COLOR(i) << 20) | 2295 (CLUT_COLOR(i))); 2296 } 2297 2298 CLR32(sc, RADEON_DAC_CNTL2, RADEON_DAC2_PALETTE_ACC_CTL); 2299 PRINTREG(RADEON_DAC_CNTL2); 2300 2301 PUTPLL(sc, RADEON_VCLK_ECP_CNTL, vclk); 2302 } 2303 2304 /* 2305 * Bugs in some R300 hardware requires this when accessing CLOCK_CNTL_INDEX. 2306 */ 2307 void 2308 radeonfb_r300cg_workaround(struct radeonfb_softc *sc) 2309 { 2310 uint32_t tmp, save; 2311 2312 save = GET32(sc, RADEON_CLOCK_CNTL_INDEX); 2313 tmp = save & ~(0x3f | RADEON_PLL_WR_EN); 2314 PUT32(sc, RADEON_CLOCK_CNTL_INDEX, tmp); 2315 tmp = GET32(sc, RADEON_CLOCK_CNTL_DATA); 2316 PUT32(sc, RADEON_CLOCK_CNTL_INDEX, save); 2317 } 2318 2319 /* 2320 * Acceleration entry points. 2321 */ 2322 static void 2323 radeonfb_putchar(void *cookie, int row, int col, u_int c, long attr) 2324 { 2325 struct rasops_info *ri = cookie; 2326 struct vcons_screen *scr = ri->ri_hw; 2327 struct radeonfb_display *dp = scr->scr_cookie; 2328 uint32_t x, y, w, h; 2329 uint32_t bg, fg; 2330 uint8_t *data; 2331 2332 if (dp->rd_wsmode != WSDISPLAYIO_MODE_EMUL) 2333 return; 2334 2335 if (!CHAR_IN_FONT(c, ri->ri_font)) 2336 return; 2337 2338 w = ri->ri_font->fontwidth; 2339 h = ri->ri_font->fontheight; 2340 2341 bg = ri->ri_devcmap[(attr >> 16) & 0xf]; 2342 fg = ri->ri_devcmap[(attr >> 24) & 0xf]; 2343 2344 x = ri->ri_xorigin + col * w; 2345 y = ri->ri_yorigin + row * h; 2346 2347 if (c == 0x20) { 2348 radeonfb_rectfill(dp, x, y, w, h, bg); 2349 } else { 2350 data = (uint8_t *)ri->ri_font->data + 2351 (c - ri->ri_font->firstchar) * ri->ri_fontscale; 2352 2353 radeonfb_setup_mono(dp, x, y, w, h, fg, bg); 2354 radeonfb_feed_bytes(dp, ri->ri_fontscale, data); 2355 } 2356 } 2357 2358 static void 2359 radeonfb_eraserows(void *cookie, int row, int nrows, long fillattr) 2360 { 2361 struct rasops_info *ri = cookie; 2362 struct vcons_screen *scr = ri->ri_hw; 2363 struct radeonfb_display *dp = scr->scr_cookie; 2364 uint32_t x, y, w, h, fg, bg, ul; 2365 2366 /* XXX: check for full emulation mode? */ 2367 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 2368 x = ri->ri_xorigin; 2369 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 2370 w = ri->ri_emuwidth; 2371 h = ri->ri_font->fontheight * nrows; 2372 2373 rasops_unpack_attr(fillattr, &fg, &bg, &ul); 2374 radeonfb_rectfill(dp, x, y, w, h, ri->ri_devcmap[bg & 0xf]); 2375 } 2376 } 2377 2378 static void 2379 radeonfb_copyrows(void *cookie, int srcrow, int dstrow, int nrows) 2380 { 2381 struct rasops_info *ri = cookie; 2382 struct vcons_screen *scr = ri->ri_hw; 2383 struct radeonfb_display *dp = scr->scr_cookie; 2384 uint32_t x, ys, yd, w, h; 2385 2386 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 2387 x = ri->ri_xorigin; 2388 ys = ri->ri_yorigin + ri->ri_font->fontheight * srcrow; 2389 yd = ri->ri_yorigin + ri->ri_font->fontheight * dstrow; 2390 w = ri->ri_emuwidth; 2391 h = ri->ri_font->fontheight * nrows; 2392 radeonfb_bitblt(dp, x, ys, x, yd, w, h, 2393 RADEON_ROP3_S, 0xffffffff); 2394 } 2395 } 2396 2397 static void 2398 radeonfb_copycols(void *cookie, int row, int srccol, int dstcol, int ncols) 2399 { 2400 struct rasops_info *ri = cookie; 2401 struct vcons_screen *scr = ri->ri_hw; 2402 struct radeonfb_display *dp = scr->scr_cookie; 2403 uint32_t xs, xd, y, w, h; 2404 2405 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 2406 xs = ri->ri_xorigin + ri->ri_font->fontwidth * srccol; 2407 xd = ri->ri_xorigin + ri->ri_font->fontwidth * dstcol; 2408 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 2409 w = ri->ri_font->fontwidth * ncols; 2410 h = ri->ri_font->fontheight; 2411 radeonfb_bitblt(dp, xs, y, xd, y, w, h, 2412 RADEON_ROP3_S, 0xffffffff); 2413 } 2414 } 2415 2416 static void 2417 radeonfb_erasecols(void *cookie, int row, int startcol, int ncols, 2418 long fillattr) 2419 { 2420 struct rasops_info *ri = cookie; 2421 struct vcons_screen *scr = ri->ri_hw; 2422 struct radeonfb_display *dp = scr->scr_cookie; 2423 uint32_t x, y, w, h, fg, bg, ul; 2424 2425 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 2426 x = ri->ri_xorigin + ri->ri_font->fontwidth * startcol; 2427 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 2428 w = ri->ri_font->fontwidth * ncols; 2429 h = ri->ri_font->fontheight; 2430 2431 rasops_unpack_attr(fillattr, &fg, &bg, &ul); 2432 radeonfb_rectfill(dp, x, y, w, h, ri->ri_devcmap[bg & 0xf]); 2433 } 2434 } 2435 2436 static void 2437 radeonfb_cursor(void *cookie, int on, int row, int col) 2438 { 2439 struct rasops_info *ri = cookie; 2440 struct vcons_screen *scr = ri->ri_hw; 2441 struct radeonfb_display *dp = scr->scr_cookie; 2442 int x, y, wi, he; 2443 2444 wi = ri->ri_font->fontwidth; 2445 he = ri->ri_font->fontheight; 2446 2447 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 2448 x = ri->ri_ccol * wi + ri->ri_xorigin; 2449 y = ri->ri_crow * he + ri->ri_yorigin; 2450 /* first turn off the old cursor */ 2451 if (ri->ri_flg & RI_CURSOR) { 2452 radeonfb_bitblt(dp, x, y, x, y, wi, he, 2453 RADEON_ROP3_Dn, 0xffffffff); 2454 ri->ri_flg &= ~RI_CURSOR; 2455 } 2456 ri->ri_crow = row; 2457 ri->ri_ccol = col; 2458 /* then (possibly) turn on the new one */ 2459 if (on) { 2460 x = ri->ri_ccol * wi + ri->ri_xorigin; 2461 y = ri->ri_crow * he + ri->ri_yorigin; 2462 radeonfb_bitblt(dp, x, y, x, y, wi, he, 2463 RADEON_ROP3_Dn, 0xffffffff); 2464 ri->ri_flg |= RI_CURSOR; 2465 } 2466 } else { 2467 scr->scr_ri.ri_crow = row; 2468 scr->scr_ri.ri_ccol = col; 2469 scr->scr_ri.ri_flg &= ~RI_CURSOR; 2470 } 2471 } 2472 2473 static int 2474 radeonfb_allocattr(void *cookie, int fg, int bg, int flags, long *attrp) 2475 { 2476 if ((fg == 0) && (bg == 0)) { 2477 fg = WS_DEFAULT_FG; 2478 bg = WS_DEFAULT_BG; 2479 } 2480 *attrp = ((fg & 0xf) << 24) | ((bg & 0xf) << 16) | (flags & 0xff) << 8; 2481 return 0; 2482 } 2483 2484 /* 2485 * Underlying acceleration support. 2486 */ 2487 static void 2488 radeonfb_setup_mono(struct radeonfb_display *dp, int xd, int yd, int width, 2489 int height, uint32_t fg, uint32_t bg) 2490 { 2491 struct radeonfb_softc *sc = dp->rd_softc; 2492 uint32_t gmc; 2493 uint32_t padded_width = (width+7) & 0xfff8; 2494 uint32_t topleft, bottomright; 2495 2496 gmc = dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT; 2497 2498 if (width != padded_width) { 2499 2500 radeonfb_wait_fifo(sc, 2); 2501 topleft = ((yd << 16) & 0x1fff0000) | (xd & 0x1fff); 2502 bottomright = (((yd + height) << 16) & 0x1fff0000) | 2503 ((xd + width) & 0x1fff); 2504 PUT32(sc, RADEON_SC_TOP_LEFT, topleft); 2505 PUT32(sc, RADEON_SC_BOTTOM_RIGHT, bottomright); 2506 } 2507 2508 radeonfb_wait_fifo(sc, 5); 2509 2510 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 2511 RADEON_GMC_BRUSH_NONE | 2512 RADEON_GMC_SRC_DATATYPE_MONO_FG_BG | 2513 //RADEON_GMC_BYTE_LSB_TO_MSB | 2514 RADEON_GMC_DST_CLIPPING | 2515 RADEON_ROP3_S | 2516 RADEON_DP_SRC_SOURCE_HOST_DATA | 2517 RADEON_GMC_CLR_CMP_CNTL_DIS | 2518 RADEON_GMC_WR_MSK_DIS | 2519 gmc); 2520 2521 PUT32(sc, RADEON_DP_SRC_FRGD_CLR, fg); 2522 PUT32(sc, RADEON_DP_SRC_BKGD_CLR, bg); 2523 2524 PUT32(sc, RADEON_DST_X_Y, (xd << 16) | yd); 2525 PUT32(sc, RADEON_DST_WIDTH_HEIGHT, (padded_width << 16) | height); 2526 2527 } 2528 2529 static void 2530 radeonfb_feed_bytes(struct radeonfb_display *dp, int count, uint8_t *data) 2531 { 2532 struct radeonfb_softc *sc = dp->rd_softc; 2533 int i; 2534 uint32_t latch = 0; 2535 int shift = 0; 2536 2537 for (i = 0; i < count; i++) { 2538 latch |= (data[i] << shift); 2539 if (shift == 24) { 2540 radeonfb_wait_fifo(sc, 1); 2541 PUT32(sc, RADEON_HOST_DATA0, latch); 2542 latch = 0; 2543 shift = 0; 2544 } else 2545 shift += 8; 2546 } 2547 if (shift != 0) { 2548 radeonfb_wait_fifo(sc, 1); 2549 PUT32(sc, RADEON_HOST_DATA0, latch); 2550 } 2551 radeonfb_unclip(sc); 2552 } 2553 2554 static void 2555 radeonfb_rectfill(struct radeonfb_display *dp, int dstx, int dsty, 2556 int width, int height, uint32_t color) 2557 { 2558 struct radeonfb_softc *sc = dp->rd_softc; 2559 uint32_t gmc; 2560 2561 gmc = dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT; 2562 2563 radeonfb_wait_fifo(sc, 6); 2564 2565 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 2566 RADEON_GMC_BRUSH_SOLID_COLOR | 2567 RADEON_GMC_SRC_DATATYPE_COLOR | 2568 RADEON_GMC_CLR_CMP_CNTL_DIS | 2569 RADEON_ROP3_P | gmc); 2570 2571 PUT32(sc, RADEON_DP_BRUSH_FRGD_CLR, color); 2572 PUT32(sc, RADEON_DP_WRITE_MASK, 0xffffffff); 2573 PUT32(sc, RADEON_DP_CNTL, 2574 RADEON_DST_X_LEFT_TO_RIGHT | 2575 RADEON_DST_Y_TOP_TO_BOTTOM); 2576 PUT32(sc, RADEON_DST_Y_X, (dsty << 16) | dstx); 2577 PUT32(sc, RADEON_DST_WIDTH_HEIGHT, (width << 16) | (height)); 2578 2579 /* 2580 * XXX: we don't wait for the fifo to empty -- that would slow 2581 * things down! The linux radeonfb driver waits, but xfree doesn't 2582 */ 2583 /* XXX: for now we do, to make it safe for direct drawing */ 2584 radeonfb_engine_idle(sc); 2585 } 2586 2587 static void 2588 radeonfb_bitblt(struct radeonfb_display *dp, int srcx, int srcy, 2589 int dstx, int dsty, int width, int height, int rop, uint32_t mask) 2590 { 2591 struct radeonfb_softc *sc = dp->rd_softc; 2592 uint32_t gmc; 2593 uint32_t dir; 2594 2595 if (dsty < srcy) { 2596 dir = RADEON_DST_Y_TOP_TO_BOTTOM; 2597 } else { 2598 srcy += height - 1; 2599 dsty += height - 1; 2600 dir = 0; 2601 } 2602 if (dstx < srcx) { 2603 dir |= RADEON_DST_X_LEFT_TO_RIGHT; 2604 } else { 2605 srcx += width - 1; 2606 dstx += width - 1; 2607 } 2608 2609 gmc = dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT; 2610 2611 radeonfb_wait_fifo(sc, 6); 2612 2613 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 2614 //RADEON_GMC_SRC_CLIPPING | 2615 RADEON_GMC_BRUSH_SOLID_COLOR | 2616 RADEON_GMC_SRC_DATATYPE_COLOR | 2617 RADEON_GMC_CLR_CMP_CNTL_DIS | 2618 RADEON_DP_SRC_SOURCE_MEMORY | 2619 rop | gmc); 2620 2621 PUT32(sc, RADEON_DP_WRITE_MASK, mask); 2622 PUT32(sc, RADEON_DP_CNTL, dir); 2623 PUT32(sc, RADEON_SRC_Y_X, (srcy << 16) | srcx); 2624 PUT32(sc, RADEON_DST_Y_X, (dsty << 16) | dstx); 2625 PUT32(sc, RADEON_DST_WIDTH_HEIGHT, (width << 16) | (height)); 2626 2627 /* 2628 * XXX: we don't wait for the fifo to empty -- that would slow 2629 * things down! The linux radeonfb driver waits, but xfree doesn't 2630 */ 2631 /* XXX: for now we do, to make it safe for direct drawing */ 2632 radeonfb_engine_idle(sc); 2633 } 2634 2635 static void 2636 radeonfb_engine_idle(struct radeonfb_softc *sc) 2637 { 2638 int i; 2639 2640 radeonfb_wait_fifo(sc, 64); 2641 for (i = RADEON_TIMEOUT; i; i--) { 2642 if ((GET32(sc, RADEON_RBBM_STATUS) & 2643 RADEON_RBBM_ACTIVE) == 0) { 2644 radeonfb_engine_flush(sc); 2645 break; 2646 } 2647 } 2648 } 2649 2650 static void 2651 radeonfb_wait_fifo(struct radeonfb_softc *sc, int n) 2652 { 2653 int i; 2654 2655 for (i = RADEON_TIMEOUT; i; i--) { 2656 if ((GET32(sc, RADEON_RBBM_STATUS) & 2657 RADEON_RBBM_FIFOCNT_MASK) >= n) 2658 return; 2659 } 2660 #ifdef DIAGNOSTIC 2661 if (!i) 2662 printf("%s: timed out waiting for fifo (%x)\n", 2663 XNAME(sc), GET32(sc, RADEON_RBBM_STATUS)); 2664 #endif 2665 } 2666 2667 static void 2668 radeonfb_engine_flush(struct radeonfb_softc *sc) 2669 { 2670 int i; 2671 SET32(sc, RADEON_RB2D_DSTCACHE_CTLSTAT, RADEON_RB2D_DC_FLUSH_ALL); 2672 for (i = RADEON_TIMEOUT; i; i--) { 2673 if ((GET32(sc, RADEON_RB2D_DSTCACHE_CTLSTAT) & 2674 RADEON_RB2D_DC_BUSY) == 0) 2675 break; 2676 } 2677 #ifdef DIAGNOSTIC 2678 if (!i) 2679 printf("%s: engine flush timed out!\n", XNAME(sc)); 2680 #endif 2681 } 2682 2683 static inline void 2684 radeonfb_unclip(struct radeonfb_softc *sc) 2685 { 2686 2687 radeonfb_wait_fifo(sc, 2); 2688 PUT32(sc, RADEON_SC_TOP_LEFT, 0); 2689 PUT32(sc, RADEON_SC_BOTTOM_RIGHT, 0x1fff1fff); 2690 } 2691 2692 static void 2693 radeonfb_engine_init(struct radeonfb_display *dp) 2694 { 2695 struct radeonfb_softc *sc = dp->rd_softc; 2696 uint32_t pitch; 2697 2698 /* no 3D */ 2699 PUT32(sc, RADEON_RB3D_CNTL, 0); 2700 2701 radeonfb_engine_reset(sc); 2702 pitch = ((dp->rd_virtx * (dp->rd_bpp / 8) + 0x3f)) >> 6; 2703 //pitch = ((sc->sc_maxx * (sc->sc_maxbpp / 8) + 0x3f)) >> 6; 2704 2705 radeonfb_wait_fifo(sc, 1); 2706 if (!IS_R300(sc)) 2707 PUT32(sc, RADEON_RB2D_DSTCACHE_MODE, 0); 2708 2709 radeonfb_wait_fifo(sc, 3); 2710 PUT32(sc, RADEON_DEFAULT_PITCH_OFFSET, 2711 (pitch << 22) | (sc->sc_aperbase >> 10)); 2712 2713 2714 PUT32(sc, RADEON_DST_PITCH_OFFSET, 2715 (pitch << 22) | (sc->sc_aperbase >> 10)); 2716 PUT32(sc, RADEON_SRC_PITCH_OFFSET, 2717 (pitch << 22) | (sc->sc_aperbase >> 10)); 2718 2719 radeonfb_wait_fifo(sc, 1); 2720 #if _BYTE_ORDER == _BIG_ENDIAN 2721 SET32(sc, RADEON_DP_DATATYPE, RADEON_HOST_BIG_ENDIAN_EN); 2722 #else 2723 CLR32(sc, RADEON_DP_DATATYPE, RADEON_HOST_BIG_ENDIAN_EN); 2724 #endif 2725 2726 /* default scissors -- no clipping */ 2727 radeonfb_wait_fifo(sc, 1); 2728 PUT32(sc, RADEON_DEFAULT_SC_BOTTOM_RIGHT, 2729 RADEON_DEFAULT_SC_RIGHT_MAX | RADEON_DEFAULT_SC_BOTTOM_MAX); 2730 2731 radeonfb_wait_fifo(sc, 1); 2732 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 2733 (dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT) | 2734 RADEON_GMC_CLR_CMP_CNTL_DIS | 2735 RADEON_GMC_BRUSH_SOLID_COLOR | 2736 RADEON_GMC_SRC_DATATYPE_COLOR); 2737 2738 radeonfb_wait_fifo(sc, 7); 2739 PUT32(sc, RADEON_DST_LINE_START, 0); 2740 PUT32(sc, RADEON_DST_LINE_END, 0); 2741 PUT32(sc, RADEON_DP_BRUSH_FRGD_CLR, 0xffffffff); 2742 PUT32(sc, RADEON_DP_BRUSH_BKGD_CLR, 0); 2743 PUT32(sc, RADEON_DP_SRC_FRGD_CLR, 0xffffffff); 2744 PUT32(sc, RADEON_DP_SRC_BKGD_CLR, 0); 2745 PUT32(sc, RADEON_DP_WRITE_MASK, 0xffffffff); 2746 2747 radeonfb_engine_idle(sc); 2748 } 2749 2750 static void 2751 radeonfb_engine_reset(struct radeonfb_softc *sc) 2752 { 2753 uint32_t hpc, rbbm, mclkcntl, clkindex; 2754 2755 radeonfb_engine_flush(sc); 2756 2757 clkindex = GET32(sc, RADEON_CLOCK_CNTL_INDEX); 2758 if (HAS_R300CG(sc)) 2759 radeonfb_r300cg_workaround(sc); 2760 mclkcntl = GETPLL(sc, RADEON_MCLK_CNTL); 2761 2762 /* 2763 * According to comments in XFree code, resetting the HDP via 2764 * the RBBM_SOFT_RESET can cause bad behavior on some systems. 2765 * So we use HOST_PATH_CNTL instead. 2766 */ 2767 2768 hpc = GET32(sc, RADEON_HOST_PATH_CNTL); 2769 rbbm = GET32(sc, RADEON_RBBM_SOFT_RESET); 2770 if (IS_R300(sc)) { 2771 PUT32(sc, RADEON_RBBM_SOFT_RESET, rbbm | 2772 RADEON_SOFT_RESET_CP | 2773 RADEON_SOFT_RESET_HI | 2774 RADEON_SOFT_RESET_E2); 2775 GET32(sc, RADEON_RBBM_SOFT_RESET); 2776 PUT32(sc, RADEON_RBBM_SOFT_RESET, 0); 2777 /* 2778 * XXX: this bit is not defined in any ATI docs I have, 2779 * nor in the XFree code, but XFree does it. Why? 2780 */ 2781 SET32(sc, RADEON_RB2D_DSTCACHE_MODE, (1<<17)); 2782 } else { 2783 PUT32(sc, RADEON_RBBM_SOFT_RESET, rbbm | 2784 RADEON_SOFT_RESET_CP | 2785 RADEON_SOFT_RESET_SE | 2786 RADEON_SOFT_RESET_RE | 2787 RADEON_SOFT_RESET_PP | 2788 RADEON_SOFT_RESET_E2 | 2789 RADEON_SOFT_RESET_RB); 2790 GET32(sc, RADEON_RBBM_SOFT_RESET); 2791 PUT32(sc, RADEON_RBBM_SOFT_RESET, rbbm & 2792 ~(RADEON_SOFT_RESET_CP | 2793 RADEON_SOFT_RESET_SE | 2794 RADEON_SOFT_RESET_RE | 2795 RADEON_SOFT_RESET_PP | 2796 RADEON_SOFT_RESET_E2 | 2797 RADEON_SOFT_RESET_RB)); 2798 GET32(sc, RADEON_RBBM_SOFT_RESET); 2799 } 2800 2801 PUT32(sc, RADEON_HOST_PATH_CNTL, hpc | RADEON_HDP_SOFT_RESET); 2802 GET32(sc, RADEON_HOST_PATH_CNTL); 2803 PUT32(sc, RADEON_HOST_PATH_CNTL, hpc); 2804 2805 if (IS_R300(sc)) 2806 PUT32(sc, RADEON_RBBM_SOFT_RESET, rbbm); 2807 2808 PUT32(sc, RADEON_CLOCK_CNTL_INDEX, clkindex); 2809 PUTPLL(sc, RADEON_MCLK_CNTL, mclkcntl); 2810 2811 if (HAS_R300CG(sc)) 2812 radeonfb_r300cg_workaround(sc); 2813 } 2814 2815 static int 2816 radeonfb_set_curpos(struct radeonfb_display *dp, struct wsdisplay_curpos *pos) 2817 { 2818 int x, y; 2819 2820 x = pos->x; 2821 y = pos->y; 2822 2823 /* 2824 * This doesn't let a cursor move off the screen. I'm not 2825 * sure if this will have negative effects for e.g. Xinerama. 2826 * I'd guess Xinerama handles it by changing the cursor shape, 2827 * but that needs verification. 2828 */ 2829 if (x >= dp->rd_virtx) 2830 x = dp->rd_virtx - 1; 2831 if (x < 0) 2832 x = 0; 2833 if (y >= dp->rd_virty) 2834 y = dp->rd_virty - 1; 2835 if (y < 0) 2836 y = 0; 2837 2838 dp->rd_cursor.rc_pos.x = x; 2839 dp->rd_cursor.rc_pos.y = y; 2840 2841 radeonfb_cursor_position(dp); 2842 return 0; 2843 } 2844 2845 static int 2846 radeonfb_set_cursor(struct radeonfb_display *dp, struct wsdisplay_cursor *wc) 2847 { 2848 unsigned flags; 2849 2850 uint8_t r[2], g[2], b[2]; 2851 unsigned index, count; 2852 int i, err; 2853 int pitch, size; 2854 struct radeonfb_cursor nc; 2855 2856 flags = wc->which; 2857 2858 /* copy old values */ 2859 nc = dp->rd_cursor; 2860 2861 if (flags & WSDISPLAY_CURSOR_DOCMAP) { 2862 index = wc->cmap.index; 2863 count = wc->cmap.count; 2864 2865 if (index >= 2 || (index + count) > 2) 2866 return EINVAL; 2867 2868 err = copyin(wc->cmap.red, &r[index], count); 2869 if (err) 2870 return err; 2871 err = copyin(wc->cmap.green, &g[index], count); 2872 if (err) 2873 return err; 2874 err = copyin(wc->cmap.blue, &b[index], count); 2875 if (err) 2876 return err; 2877 2878 for (i = index; i < index + count; i++) { 2879 nc.rc_cmap[i] = 2880 (r[i] << 16) + (g[i] << 8) + (b[i] << 0); 2881 } 2882 } 2883 2884 if (flags & WSDISPLAY_CURSOR_DOSHAPE) { 2885 if ((wc->size.x > RADEON_CURSORMAXX) || 2886 (wc->size.y > RADEON_CURSORMAXY)) 2887 return EINVAL; 2888 2889 /* figure bytes per line */ 2890 pitch = (wc->size.x + 7) / 8; 2891 size = pitch * wc->size.y; 2892 2893 /* clear the old cursor and mask */ 2894 memset(nc.rc_image, 0, 512); 2895 memset(nc.rc_mask, 0, 512); 2896 2897 nc.rc_size = wc->size; 2898 2899 if ((err = copyin(wc->image, nc.rc_image, size)) != 0) 2900 return err; 2901 2902 if ((err = copyin(wc->mask, nc.rc_mask, size)) != 0) 2903 return err; 2904 } 2905 2906 if (flags & WSDISPLAY_CURSOR_DOHOT) { 2907 nc.rc_hot = wc->hot; 2908 if (nc.rc_hot.x >= nc.rc_size.x) 2909 nc.rc_hot.x = nc.rc_size.x - 1; 2910 if (nc.rc_hot.y >= nc.rc_size.y) 2911 nc.rc_hot.y = nc.rc_size.y - 1; 2912 } 2913 2914 if (flags & WSDISPLAY_CURSOR_DOPOS) { 2915 nc.rc_pos = wc->pos; 2916 if (nc.rc_pos.x >= dp->rd_virtx) 2917 nc.rc_pos.x = dp->rd_virtx - 1; 2918 #if 0 2919 if (nc.rc_pos.x < 0) 2920 nc.rc_pos.x = 0; 2921 #endif 2922 if (nc.rc_pos.y >= dp->rd_virty) 2923 nc.rc_pos.y = dp->rd_virty - 1; 2924 #if 0 2925 if (nc.rc_pos.y < 0) 2926 nc.rc_pos.y = 0; 2927 #endif 2928 } 2929 if (flags & WSDISPLAY_CURSOR_DOCUR) { 2930 nc.rc_visible = wc->enable; 2931 } 2932 2933 dp->rd_cursor = nc; 2934 radeonfb_cursor_update(dp, wc->which); 2935 2936 return 0; 2937 } 2938 2939 /* 2940 * Change the cursor shape. Call this with the cursor locked to avoid 2941 * flickering/tearing. 2942 */ 2943 static void 2944 radeonfb_cursor_shape(struct radeonfb_display *dp) 2945 { 2946 uint8_t and[512], xor[512]; 2947 int i, j, src, dst, pitch; 2948 const uint8_t *msk = dp->rd_cursor.rc_mask; 2949 const uint8_t *img = dp->rd_cursor.rc_image; 2950 2951 /* 2952 * Radeon cursor data interleaves one line of AND data followed 2953 * by a line of XOR data. (Each line corresponds to a whole hardware 2954 * pitch - i.e. 64 pixels or 8 bytes.) 2955 * 2956 * The cursor is displayed using the following table: 2957 * 2958 * AND XOR Result 2959 * ---------------------- 2960 * 0 0 Cursor color 0 2961 * 0 1 Cursor color 1 2962 * 1 0 Transparent 2963 * 1 1 Complement of background 2964 * 2965 * Our masks are therefore different from what we were passed. 2966 * Passed in, I'm assuming the data represents either color 0 or 1, 2967 * and a mask, so the passed in table looks like: 2968 * 2969 * IMG Mask Result 2970 * ----------------------- 2971 * 0 0 Transparent 2972 * 0 1 Cursor color 0 2973 * 1 0 Transparent 2974 * 1 1 Cursor color 1 2975 * 2976 * IF mask bit == 1, AND = 0, XOR = color. 2977 * IF mask bit == 0, AND = 1, XOR = 0. 2978 * 2979 * hence: AND = ~(mask); XOR = color & ~(mask); 2980 */ 2981 2982 pitch = ((dp->rd_cursor.rc_size.x + 7) / 8); 2983 2984 /* start by assuming all bits are transparent */ 2985 memset(and, 0xff, 512); 2986 memset(xor, 0x00, 512); 2987 2988 src = 0; 2989 dst = 0; 2990 for (i = 0; i < 64; i++) { 2991 for (j = 0; j < 64; j += 8) { 2992 if ((i < dp->rd_cursor.rc_size.y) && 2993 (j < dp->rd_cursor.rc_size.x)) { 2994 2995 /* take care to leave odd bits alone */ 2996 and[dst] &= ~(msk[src]); 2997 xor[dst] = img[src] & msk[src]; 2998 src++; 2999 } 3000 dst++; 3001 } 3002 } 3003 3004 /* copy the image into place */ 3005 for (i = 0; i < 64; i++) { 3006 memcpy((uint8_t *)dp->rd_curptr + (i * 16), 3007 &and[i * 8], 8); 3008 memcpy((uint8_t *)dp->rd_curptr + (i * 16) + 8, 3009 &xor[i * 8], 8); 3010 } 3011 } 3012 3013 static void 3014 radeonfb_cursor_position(struct radeonfb_display *dp) 3015 { 3016 struct radeonfb_softc *sc = dp->rd_softc; 3017 uint32_t offset, hvoff, hvpos; /* registers */ 3018 uint32_t coff; /* cursor offset */ 3019 int i, x, y, xoff, yoff, crtcoff; 3020 3021 /* 3022 * XXX: this also needs to handle pan/scan 3023 */ 3024 for (i = 0; i < dp->rd_ncrtcs; i++) { 3025 3026 struct radeonfb_crtc *rcp = &dp->rd_crtcs[i]; 3027 3028 if (rcp->rc_number) { 3029 offset = RADEON_CUR2_OFFSET; 3030 hvoff = RADEON_CUR2_HORZ_VERT_OFF; 3031 hvpos = RADEON_CUR2_HORZ_VERT_POSN; 3032 crtcoff = RADEON_CRTC2_OFFSET; 3033 } else { 3034 offset = RADEON_CUR_OFFSET; 3035 hvoff = RADEON_CUR_HORZ_VERT_OFF; 3036 hvpos = RADEON_CUR_HORZ_VERT_POSN; 3037 crtcoff = RADEON_CRTC_OFFSET; 3038 } 3039 3040 x = dp->rd_cursor.rc_pos.x; 3041 y = dp->rd_cursor.rc_pos.y; 3042 3043 while (y < rcp->rc_yoffset) { 3044 rcp->rc_yoffset -= RADEON_PANINCREMENT; 3045 } 3046 while (y >= (rcp->rc_yoffset + rcp->rc_videomode.vdisplay)) { 3047 rcp->rc_yoffset += RADEON_PANINCREMENT; 3048 } 3049 while (x < rcp->rc_xoffset) { 3050 rcp->rc_xoffset -= RADEON_PANINCREMENT; 3051 } 3052 while (x >= (rcp->rc_xoffset + rcp->rc_videomode.hdisplay)) { 3053 rcp->rc_xoffset += RADEON_PANINCREMENT; 3054 } 3055 3056 /* adjust for the cursor's hotspot */ 3057 x -= dp->rd_cursor.rc_hot.x; 3058 y -= dp->rd_cursor.rc_hot.y; 3059 xoff = yoff = 0; 3060 3061 if (x >= dp->rd_virtx) 3062 x = dp->rd_virtx - 1; 3063 if (y >= dp->rd_virty) 3064 y = dp->rd_virty - 1; 3065 3066 /* now adjust cursor so it is relative to viewport */ 3067 x -= rcp->rc_xoffset; 3068 y -= rcp->rc_yoffset; 3069 3070 /* 3071 * no need to check for fall off, because we should 3072 * never move off the screen entirely! 3073 */ 3074 coff = 0; 3075 if (x < 0) { 3076 xoff = -x; 3077 x = 0; 3078 } 3079 if (y < 0) { 3080 yoff = -y; 3081 y = 0; 3082 coff = (yoff * 2) * 8; 3083 } 3084 3085 /* pan the display */ 3086 PUT32(sc, crtcoff, (rcp->rc_yoffset * dp->rd_stride) + 3087 rcp->rc_xoffset); 3088 3089 PUT32(sc, offset, (dp->rd_curoff + coff) | RADEON_CUR_LOCK); 3090 PUT32(sc, hvoff, (xoff << 16) | (yoff) | RADEON_CUR_LOCK); 3091 /* NB: this unlocks the cursor */ 3092 PUT32(sc, hvpos, (x << 16) | y); 3093 } 3094 } 3095 3096 static void 3097 radeonfb_cursor_visible(struct radeonfb_display *dp) 3098 { 3099 int i; 3100 uint32_t gencntl, bit; 3101 3102 for (i = 0; i < dp->rd_ncrtcs; i++) { 3103 if (dp->rd_crtcs[i].rc_number) { 3104 gencntl = RADEON_CRTC2_GEN_CNTL; 3105 bit = RADEON_CRTC2_CUR_EN; 3106 } else { 3107 gencntl = RADEON_CRTC_GEN_CNTL; 3108 bit = RADEON_CRTC_CUR_EN; 3109 } 3110 3111 if (dp->rd_cursor.rc_visible) 3112 SET32(dp->rd_softc, gencntl, bit); 3113 else 3114 CLR32(dp->rd_softc, gencntl, bit); 3115 } 3116 } 3117 3118 static void 3119 radeonfb_cursor_cmap(struct radeonfb_display *dp) 3120 { 3121 int i; 3122 uint32_t c0reg, c1reg; 3123 struct radeonfb_softc *sc = dp->rd_softc; 3124 3125 for (i = 0; i < dp->rd_ncrtcs; i++) { 3126 if (dp->rd_crtcs[i].rc_number) { 3127 c0reg = RADEON_CUR2_CLR0; 3128 c1reg = RADEON_CUR2_CLR1; 3129 } else { 3130 c0reg = RADEON_CUR_CLR0; 3131 c1reg = RADEON_CUR_CLR1; 3132 } 3133 3134 PUT32(sc, c0reg, dp->rd_cursor.rc_cmap[0]); 3135 PUT32(sc, c1reg, dp->rd_cursor.rc_cmap[1]); 3136 } 3137 } 3138 3139 static void 3140 radeonfb_cursor_update(struct radeonfb_display *dp, unsigned which) 3141 { 3142 struct radeonfb_softc *sc; 3143 int i; 3144 3145 sc = dp->rd_softc; 3146 for (i = 0; i < dp->rd_ncrtcs; i++) { 3147 if (dp->rd_crtcs[i].rc_number) { 3148 SET32(sc, RADEON_CUR2_OFFSET, RADEON_CUR_LOCK); 3149 } else { 3150 SET32(sc, RADEON_CUR_OFFSET,RADEON_CUR_LOCK); 3151 } 3152 } 3153 3154 if (which & WSDISPLAY_CURSOR_DOCMAP) 3155 radeonfb_cursor_cmap(dp); 3156 3157 if (which & WSDISPLAY_CURSOR_DOSHAPE) 3158 radeonfb_cursor_shape(dp); 3159 3160 if (which & WSDISPLAY_CURSOR_DOCUR) 3161 radeonfb_cursor_visible(dp); 3162 3163 /* this one is unconditional, because it updates other stuff */ 3164 radeonfb_cursor_position(dp); 3165 } 3166 3167 static struct videomode * 3168 radeonfb_best_refresh(struct videomode *m1, struct videomode *m2) 3169 { 3170 int r1, r2; 3171 3172 /* otherwise pick the higher refresh rate */ 3173 r1 = DIVIDE(DIVIDE(m1->dot_clock, m1->htotal), m1->vtotal); 3174 r2 = DIVIDE(DIVIDE(m2->dot_clock, m2->htotal), m2->vtotal); 3175 3176 return (r1 < r2 ? m2 : m1); 3177 } 3178 3179 static const struct videomode * 3180 radeonfb_port_mode(struct radeonfb_softc *sc, struct radeonfb_port *rp, 3181 int x, int y) 3182 { 3183 struct edid_info *ep = &rp->rp_edid; 3184 struct videomode *vmp = NULL; 3185 int i; 3186 3187 if (!rp->rp_edid_valid) { 3188 /* fallback to safe mode */ 3189 return radeonfb_modelookup(sc->sc_defaultmode); 3190 } 3191 3192 /* always choose the preferred mode first! */ 3193 if (ep->edid_preferred_mode) { 3194 3195 /* XXX: add auto-stretching support for native mode */ 3196 3197 /* this may want panning to occur, btw */ 3198 if ((ep->edid_preferred_mode->hdisplay <= x) && 3199 (ep->edid_preferred_mode->vdisplay <= y)) 3200 return ep->edid_preferred_mode; 3201 } 3202 3203 for (i = 0; i < ep->edid_nmodes; i++) { 3204 /* 3205 * We elect to pick a resolution that is too large for 3206 * the monitor than one that is too small. This means 3207 * that we will prefer to pan rather than to try to 3208 * center a smaller display on a larger screen. In 3209 * practice, this shouldn't matter because if a 3210 * monitor can support a larger resolution, it can 3211 * probably also support the smaller. A specific 3212 * exception is fixed format panels, but hopefully 3213 * they are properly dealt with by the "autostretch" 3214 * logic above. 3215 */ 3216 if ((ep->edid_modes[i].hdisplay > x) || 3217 (ep->edid_modes[i].vdisplay > y)) { 3218 continue; 3219 } 3220 3221 /* 3222 * at this point, the display mode is no larger than 3223 * what we've requested. 3224 */ 3225 if (vmp == NULL) 3226 vmp = &ep->edid_modes[i]; 3227 3228 /* eliminate smaller modes */ 3229 if ((vmp->hdisplay >= ep->edid_modes[i].hdisplay) || 3230 (vmp->vdisplay >= ep->edid_modes[i].vdisplay)) 3231 continue; 3232 3233 if ((vmp->hdisplay < ep->edid_modes[i].hdisplay) || 3234 (vmp->vdisplay < ep->edid_modes[i].vdisplay)) { 3235 vmp = &ep->edid_modes[i]; 3236 continue; 3237 } 3238 3239 KASSERT(vmp->hdisplay == ep->edid_modes[i].hdisplay); 3240 KASSERT(vmp->vdisplay == ep->edid_modes[i].vdisplay); 3241 3242 vmp = radeonfb_best_refresh(vmp, &ep->edid_modes[i]); 3243 } 3244 3245 return (vmp ? vmp : radeonfb_modelookup(sc->sc_defaultmode)); 3246 } 3247 3248 static int 3249 radeonfb_hasres(struct videomode *list, int nlist, int x, int y) 3250 { 3251 int i; 3252 3253 for (i = 0; i < nlist; i++) { 3254 if ((x == list[i].hdisplay) && 3255 (y == list[i].vdisplay)) { 3256 return 1; 3257 } 3258 } 3259 return 0; 3260 } 3261 3262 static void 3263 radeonfb_pickres(struct radeonfb_display *dp, uint16_t *x, uint16_t *y, 3264 int pan) 3265 { 3266 struct radeonfb_port *rp; 3267 struct edid_info *ep; 3268 int i, j; 3269 3270 *x = 0; 3271 *y = 0; 3272 3273 if (pan) { 3274 for (i = 0; i < dp->rd_ncrtcs; i++) { 3275 rp = dp->rd_crtcs[i].rc_port; 3276 ep = &rp->rp_edid; 3277 if (!rp->rp_edid_valid) { 3278 /* monitor not present */ 3279 continue; 3280 } 3281 3282 /* 3283 * For now we are ignoring "conflict" that 3284 * could occur when mixing some modes like 3285 * 1280x1024 and 1400x800. It isn't clear 3286 * which is better, so the first one wins. 3287 */ 3288 for (j = 0; j < ep->edid_nmodes; j++) { 3289 /* 3290 * ignore resolutions that are too big for 3291 * the radeon 3292 */ 3293 if (ep->edid_modes[j].hdisplay > 3294 dp->rd_softc->sc_maxx) 3295 continue; 3296 if (ep->edid_modes[j].vdisplay > 3297 dp->rd_softc->sc_maxy) 3298 continue; 3299 3300 /* 3301 * pick largest resolution, the 3302 * smaller monitor will pan 3303 */ 3304 if ((ep->edid_modes[j].hdisplay >= *x) && 3305 (ep->edid_modes[j].vdisplay >= *y)) { 3306 *x = ep->edid_modes[j].hdisplay; 3307 *y = ep->edid_modes[j].vdisplay; 3308 } 3309 } 3310 } 3311 3312 } else { 3313 struct videomode modes[64]; 3314 int nmodes = 0; 3315 int valid = 0; 3316 3317 for (i = 0; i < dp->rd_ncrtcs; i++) { 3318 /* 3319 * pick the largest resolution in common. 3320 */ 3321 rp = dp->rd_crtcs[i].rc_port; 3322 ep = &rp->rp_edid; 3323 3324 if (!rp->rp_edid_valid) 3325 continue; 3326 3327 if (!valid) { 3328 /* initialize starting list */ 3329 for (j = 0; j < ep->edid_nmodes; j++) { 3330 /* 3331 * ignore resolutions that are 3332 * too big for the radeon 3333 */ 3334 if (ep->edid_modes[j].hdisplay > 3335 dp->rd_softc->sc_maxx) 3336 continue; 3337 if (ep->edid_modes[j].vdisplay > 3338 dp->rd_softc->sc_maxy) 3339 continue; 3340 3341 modes[nmodes] = ep->edid_modes[j]; 3342 nmodes++; 3343 } 3344 valid = 1; 3345 } else { 3346 /* merge into preexisting list */ 3347 for (j = 0; j < nmodes; j++) { 3348 if (!radeonfb_hasres(ep->edid_modes, 3349 ep->edid_nmodes, 3350 modes[j].hdisplay, 3351 modes[j].vdisplay)) { 3352 modes[j] = modes[nmodes]; 3353 j--; 3354 nmodes--; 3355 } 3356 } 3357 } 3358 } 3359 3360 /* now we have to pick from the merged list */ 3361 for (i = 0; i < nmodes; i++) { 3362 if ((modes[i].hdisplay >= *x) && 3363 (modes[i].vdisplay >= *y)) { 3364 *x = modes[i].hdisplay; 3365 *y = modes[i].vdisplay; 3366 } 3367 } 3368 } 3369 3370 if ((*x == 0) || (*y == 0)) { 3371 /* fallback to safe mode */ 3372 *x = 640; 3373 *y = 480; 3374 } 3375 } 3376 3377 /* 3378 * backlight levels are linear on: 3379 * - RV200, RV250, RV280, RV350 3380 * - but NOT on PowerBook4,3 6,3 6,5 3381 * according to Linux' radeonfb 3382 */ 3383 3384 /* Get the current backlight level for the display. */ 3385 3386 static int 3387 radeonfb_get_backlight(struct radeonfb_display *dp) 3388 { 3389 int s; 3390 uint32_t level; 3391 3392 s = spltty(); 3393 3394 level = radeonfb_get32(dp->rd_softc, RADEON_LVDS_GEN_CNTL); 3395 level &= RADEON_LVDS_BL_MOD_LEV_MASK; 3396 level >>= RADEON_LVDS_BL_MOD_LEV_SHIFT; 3397 3398 /* 3399 * On some chips, we should negate the backlight level. 3400 * XXX Find out on which chips. 3401 */ 3402 if (dp->rd_softc->sc_flags & RFB_INV_BLIGHT) 3403 level = RADEONFB_BACKLIGHT_MAX - level; 3404 3405 splx(s); 3406 3407 return level; 3408 } 3409 3410 /* Set the backlight to the given level for the display. */ 3411 3412 static int 3413 radeonfb_set_backlight(struct radeonfb_display *dp, int level) 3414 { 3415 struct radeonfb_softc *sc; 3416 int rlevel, s; 3417 uint32_t lvds; 3418 3419 s = spltty(); 3420 3421 if (level < 0) 3422 level = 0; 3423 else if (level >= RADEONFB_BACKLIGHT_MAX) 3424 level = RADEONFB_BACKLIGHT_MAX; 3425 3426 sc = dp->rd_softc; 3427 3428 /* On some chips, we should negate the backlight level. */ 3429 if (dp->rd_softc->sc_flags & RFB_INV_BLIGHT) { 3430 rlevel = RADEONFB_BACKLIGHT_MAX - level; 3431 } else 3432 rlevel = level; 3433 3434 callout_stop(&dp->rd_bl_lvds_co); 3435 radeonfb_engine_idle(sc); 3436 3437 /* 3438 * Turn off the display if the backlight is set to 0, since the 3439 * display is useless without backlight anyway. 3440 */ 3441 if (level == 0) 3442 radeonfb_blank(dp, 1); 3443 else if (radeonfb_get_backlight(dp) == 0) 3444 radeonfb_blank(dp, 0); 3445 3446 lvds = radeonfb_get32(sc, RADEON_LVDS_GEN_CNTL); 3447 lvds &= ~RADEON_LVDS_DISPLAY_DIS; 3448 if (!(lvds & RADEON_LVDS_BLON) || !(lvds & RADEON_LVDS_ON)) { 3449 lvds |= dp->rd_bl_lvds_val & RADEON_LVDS_DIGON; 3450 lvds |= RADEON_LVDS_BLON | RADEON_LVDS_EN; 3451 radeonfb_put32(sc, RADEON_LVDS_GEN_CNTL, lvds); 3452 lvds &= ~RADEON_LVDS_BL_MOD_LEV_MASK; 3453 lvds |= rlevel << RADEON_LVDS_BL_MOD_LEV_SHIFT; 3454 lvds |= RADEON_LVDS_ON; 3455 lvds |= dp->rd_bl_lvds_val & RADEON_LVDS_BL_MOD_EN; 3456 } else { 3457 lvds &= ~RADEON_LVDS_BL_MOD_LEV_MASK; 3458 lvds |= rlevel << RADEON_LVDS_BL_MOD_LEV_SHIFT; 3459 radeonfb_put32(sc, RADEON_LVDS_GEN_CNTL, lvds); 3460 } 3461 3462 dp->rd_bl_lvds_val &= ~RADEON_LVDS_STATE_MASK; 3463 dp->rd_bl_lvds_val |= lvds & RADEON_LVDS_STATE_MASK; 3464 /* XXX What is the correct delay? */ 3465 callout_schedule(&dp->rd_bl_lvds_co, 200 * hz); 3466 3467 splx(s); 3468 3469 return 0; 3470 } 3471 3472 /* 3473 * Callout function for delayed operations on the LVDS_GEN_CNTL register. 3474 * Set the delayed bits in the register, and clear the stored delayed 3475 * value. 3476 */ 3477 3478 static void radeonfb_lvds_callout(void *arg) 3479 { 3480 struct radeonfb_display *dp = arg; 3481 int s; 3482 3483 s = splhigh(); 3484 3485 radeonfb_mask32(dp->rd_softc, RADEON_LVDS_GEN_CNTL, ~0, 3486 dp->rd_bl_lvds_val); 3487 dp->rd_bl_lvds_val = 0; 3488 3489 splx(s); 3490 } 3491
Indexes created Wed Sep 24 05:09:52 GMT 2025