radeonfb.c revision 1.24.10.1
1 /* $NetBSD: radeonfb.c,v 1.24.10.1 2008/03/24 07:15:49 keiichi Exp $ */ 2 3 /*- 4 * Copyright (c) 2006 Itronix Inc. 5 * All rights reserved. 6 * 7 * Written by Garrett D'Amore for Itronix Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. The name of Itronix Inc. may not be used to endorse 18 * or promote products derived from this software without specific 19 * prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY ITRONIX INC. ``AS IS'' AND ANY EXPRESS 22 * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 23 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL ITRONIX INC. BE LIABLE FOR ANY 25 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE 27 * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 29 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 30 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 31 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * ATI Technologies Inc. ("ATI") has not assisted in the creation of, and 36 * does not endorse, this software. ATI will not be responsible or liable 37 * for any actual or alleged damage or loss caused by or in connection with 38 * the use of or reliance on this software. 39 */ 40 41 /* 42 * Portions of this code were taken from XFree86's Radeon driver, which bears 43 * this notice: 44 * 45 * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and 46 * VA Linux Systems Inc., Fremont, California. 47 * 48 * All Rights Reserved. 49 * 50 * Permission is hereby granted, free of charge, to any person obtaining 51 * a copy of this software and associated documentation files (the 52 * "Software"), to deal in the Software without restriction, including 53 * without limitation on the rights to use, copy, modify, merge, 54 * publish, distribute, sublicense, and/or sell copies of the Software, 55 * and to permit persons to whom the Software is furnished to do so, 56 * subject to the following conditions: 57 * 58 * The above copyright notice and this permission notice (including the 59 * next paragraph) shall be included in all copies or substantial 60 * portions of the Software. 61 * 62 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 63 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 64 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 65 * NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR 66 * THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 67 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 68 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 69 * DEALINGS IN THE SOFTWARE. 70 */ 71 72 #include <sys/cdefs.h> 73 __KERNEL_RCSID(0, "$NetBSD: radeonfb.c,v 1.24.10.1 2008/03/24 07:15:49 keiichi Exp $"); 74 75 #define RADEONFB_DEFAULT_DEPTH 32 76 77 #include <sys/param.h> 78 #include <sys/systm.h> 79 #include <sys/device.h> 80 #include <sys/malloc.h> 81 #include <sys/bus.h> 82 #include <sys/kernel.h> 83 #include <sys/lwp.h> 84 #include <sys/kauth.h> 85 86 #include <dev/wscons/wsdisplayvar.h> 87 #include <dev/wscons/wsconsio.h> 88 #include <dev/wsfont/wsfont.h> 89 #include <dev/rasops/rasops.h> 90 #include <dev/videomode/videomode.h> 91 #include <dev/videomode/edidvar.h> 92 #include <dev/wscons/wsdisplay_vconsvar.h> 93 94 #include <dev/pci/pcidevs.h> 95 #include <dev/pci/pcireg.h> 96 #include <dev/pci/pcivar.h> 97 #include <dev/pci/pciio.h> 98 #include <dev/pci/radeonfbreg.h> 99 #include <dev/pci/radeonfbvar.h> 100 #include "opt_radeonfb.h" 101 102 static int radeonfb_match(struct device *, struct cfdata *, void *); 103 static void radeonfb_attach(struct device *, struct device *, void *); 104 static int radeonfb_ioctl(void *, void *, unsigned long, void *, int, 105 struct lwp *); 106 static paddr_t radeonfb_mmap(void *, void *, off_t, int); 107 static int radeonfb_scratch_test(struct radeonfb_softc *, int, uint32_t); 108 static void radeonfb_loadbios(struct radeonfb_softc *, 109 struct pci_attach_args *); 110 111 static uintmax_t radeonfb_getprop_num(struct radeonfb_softc *, const char *, 112 uintmax_t); 113 static int radeonfb_getclocks(struct radeonfb_softc *); 114 static int radeonfb_gettmds(struct radeonfb_softc *); 115 static int radeonfb_calc_dividers(struct radeonfb_softc *, uint32_t, 116 uint32_t *, uint32_t *); 117 static int radeonfb_getconnectors(struct radeonfb_softc *); 118 static const struct videomode *radeonfb_modelookup(const char *); 119 static void radeonfb_init_screen(void *, struct vcons_screen *, int, long *); 120 static void radeonfb_pllwriteupdate(struct radeonfb_softc *, int); 121 static void radeonfb_pllwaitatomicread(struct radeonfb_softc *, int); 122 static void radeonfb_program_vclk(struct radeonfb_softc *, int, int); 123 static void radeonfb_modeswitch(struct radeonfb_display *); 124 static void radeonfb_setcrtc(struct radeonfb_display *, int); 125 static void radeonfb_init_misc(struct radeonfb_softc *); 126 static void radeonfb_set_fbloc(struct radeonfb_softc *); 127 static void radeonfb_init_palette(struct radeonfb_softc *, int); 128 static void radeonfb_r300cg_workaround(struct radeonfb_softc *); 129 130 static int radeonfb_isblank(struct radeonfb_display *); 131 static void radeonfb_blank(struct radeonfb_display *, int); 132 static int radeonfb_set_cursor(struct radeonfb_display *, 133 struct wsdisplay_cursor *); 134 static int radeonfb_set_curpos(struct radeonfb_display *, 135 struct wsdisplay_curpos *); 136 137 /* acceleration support */ 138 static void radeonfb_rectfill(struct radeonfb_display *, int dstx, int dsty, 139 int width, int height, uint32_t color); 140 static void radeonfb_bitblt(struct radeonfb_display *, int srcx, int srcy, 141 int dstx, int dsty, int width, int height, int rop, uint32_t mask); 142 static void radeonfb_feed_bytes(struct radeonfb_display *, int, uint8_t *); 143 static void radeonfb_setup_mono(struct radeonfb_display *, int, int, int, 144 int, uint32_t, uint32_t); 145 146 /* hw cursor support */ 147 static void radeonfb_cursor_cmap(struct radeonfb_display *); 148 static void radeonfb_cursor_shape(struct radeonfb_display *); 149 static void radeonfb_cursor_position(struct radeonfb_display *); 150 static void radeonfb_cursor_visible(struct radeonfb_display *); 151 static void radeonfb_cursor_update(struct radeonfb_display *, unsigned); 152 153 static void radeonfb_wait_fifo(struct radeonfb_softc *, int); 154 static void radeonfb_engine_idle(struct radeonfb_softc *); 155 static void radeonfb_engine_flush(struct radeonfb_softc *); 156 static void radeonfb_engine_reset(struct radeonfb_softc *); 157 static void radeonfb_engine_init(struct radeonfb_display *); 158 static inline void radeonfb_unclip(struct radeonfb_softc *); 159 160 static void radeonfb_eraserows(void *, int, int, long); 161 static void radeonfb_erasecols(void *, int, int, int, long); 162 static void radeonfb_copyrows(void *, int, int, int); 163 static void radeonfb_copycols(void *, int, int, int, int); 164 static void radeonfb_cursor(void *, int, int, int); 165 static void radeonfb_putchar(void *, int, int, unsigned, long); 166 static int radeonfb_allocattr(void *, int, int, int, long *); 167 168 static int radeonfb_get_backlight(struct radeonfb_display *); 169 static int radeonfb_set_backlight(struct radeonfb_display *, int); 170 static void radeonfb_lvds_callout(void *); 171 172 static struct videomode *radeonfb_best_refresh(struct videomode *, 173 struct videomode *); 174 static void radeonfb_pickres(struct radeonfb_display *, uint16_t *, 175 uint16_t *, int); 176 static const struct videomode *radeonfb_port_mode(struct radeonfb_softc *, 177 struct radeonfb_port *, int, int); 178 179 static int radeonfb_drm_print(void *, const char *); 180 181 #ifdef RADEON_DEBUG 182 int radeon_debug = 1; 183 #define DPRINTF(x) \ 184 if (radeon_debug) printf x 185 #define PRINTREG(r) DPRINTF((#r " = %08x\n", GET32(sc, r))) 186 #define PRINTPLL(r) DPRINTF((#r " = %08x\n", GETPLL(sc, r))) 187 #else 188 #define DPRINTF(x) 189 #define PRINTREG(r) 190 #define PRINTPLL(r) 191 #endif 192 193 #define ROUNDUP(x,y) (((x) + ((y) - 1)) & ~((y) - 1)) 194 195 #ifndef RADEON_DEFAULT_MODE 196 /* any reasonably modern display should handle this */ 197 #define RADEON_DEFAULT_MODE "1024x768x60" 198 #endif 199 200 const char *radeonfb_default_mode = RADEON_DEFAULT_MODE; 201 202 static struct { 203 int size; /* minimum memory size (MB) */ 204 int maxx; /* maximum x dimension */ 205 int maxy; /* maximum y dimension */ 206 int maxbpp; /* maximum bpp */ 207 int maxdisp; /* maximum logical display count */ 208 } radeonfb_limits[] = { 209 { 32, 2048, 1536, 32, 2 }, 210 { 16, 1600, 1200, 32, 2 }, 211 { 8, 1600, 1200, 32, 1 }, 212 { 0, 0, 0, 0, 0 }, 213 }; 214 215 static struct wsscreen_descr radeonfb_stdscreen = { 216 "fb", /* name */ 217 0, 0, /* ncols, nrows */ 218 NULL, /* textops */ 219 8, 16, /* fontwidth, fontheight */ 220 WSSCREEN_WSCOLORS, /* capabilities */ 221 0, /* modecookie */ 222 }; 223 224 struct wsdisplay_accessops radeonfb_accessops = { 225 radeonfb_ioctl, 226 radeonfb_mmap, 227 NULL, /* vcons_alloc_screen */ 228 NULL, /* vcons_free_screen */ 229 NULL, /* vcons_show_screen */ 230 NULL, /* load_font */ 231 NULL, /* pollc */ 232 NULL, /* scroll */ 233 }; 234 235 static struct { 236 uint16_t devid; 237 uint16_t family; 238 uint16_t flags; 239 } radeonfb_devices[] = 240 { 241 /* R100 family */ 242 { PCI_PRODUCT_ATI_RADEON_R100_QD, RADEON_R100, 0 }, 243 { PCI_PRODUCT_ATI_RADEON_R100_QE, RADEON_R100, 0 }, 244 { PCI_PRODUCT_ATI_RADEON_R100_QF, RADEON_R100, 0 }, 245 { PCI_PRODUCT_ATI_RADEON_R100_QG, RADEON_R100, 0 }, 246 247 /* RV100 family */ 248 { PCI_PRODUCT_ATI_RADEON_RV100_LY, RADEON_RV100, RFB_MOB }, 249 { PCI_PRODUCT_ATI_RADEON_RV100_LZ, RADEON_RV100, RFB_MOB }, 250 { PCI_PRODUCT_ATI_RADEON_RV100_QY, RADEON_RV100, 0 }, 251 { PCI_PRODUCT_ATI_RADEON_RV100_QZ, RADEON_RV100, 0 }, 252 253 /* RS100 family */ 254 { PCI_PRODUCT_ATI_RADEON_RS100_4136, RADEON_RS100, 0 }, 255 { PCI_PRODUCT_ATI_RADEON_RS100_4336, RADEON_RS100, RFB_MOB }, 256 257 /* RS200/RS250 family */ 258 { PCI_PRODUCT_ATI_RADEON_RS200_4337, RADEON_RS200, RFB_MOB }, 259 { PCI_PRODUCT_ATI_RADEON_RS200_A7, RADEON_RS200, 0 }, 260 { PCI_PRODUCT_ATI_RADEON_RS250_B7, RADEON_RS200, RFB_MOB }, 261 { PCI_PRODUCT_ATI_RADEON_RS250_D7, RADEON_RS200, 0 }, 262 263 /* R200 family */ 264 /* add more R200 products? , 5148 */ 265 { PCI_PRODUCT_ATI_RADEON_R200_BB, RADEON_R200, 0 }, 266 { PCI_PRODUCT_ATI_RADEON_R200_BC, RADEON_R200, 0 }, 267 { PCI_PRODUCT_ATI_RADEON_R200_QH, RADEON_R200, 0 }, 268 { PCI_PRODUCT_ATI_RADEON_R200_QL, RADEON_R200, 0 }, 269 { PCI_PRODUCT_ATI_RADEON_R200_QM, RADEON_R200, 0 }, 270 271 /* RV200 family */ 272 { PCI_PRODUCT_ATI_RADEON_RV200_LW, RADEON_RV200, RFB_MOB }, 273 { PCI_PRODUCT_ATI_RADEON_RV200_LX, RADEON_RV200, RFB_MOB }, 274 { PCI_PRODUCT_ATI_RADEON_RV200_QW, RADEON_RV200, 0 }, 275 { PCI_PRODUCT_ATI_RADEON_RV200_QX, RADEON_RV200, 0 }, 276 277 /* RV250 family */ 278 { PCI_PRODUCT_ATI_RADEON_RV250_4966, RADEON_RV250, 0 }, 279 { PCI_PRODUCT_ATI_RADEON_RV250_4967, RADEON_RV250, 0 }, 280 { PCI_PRODUCT_ATI_RADEON_RV250_4C64, RADEON_RV250, RFB_MOB }, 281 { PCI_PRODUCT_ATI_RADEON_RV250_4C66, RADEON_RV250, RFB_MOB }, 282 { PCI_PRODUCT_ATI_RADEON_RV250_4C67, RADEON_RV250, RFB_MOB }, 283 284 /* RS300 family */ 285 { PCI_PRODUCT_ATI_RADEON_RS300_X5, RADEON_RS300, 0 }, 286 { PCI_PRODUCT_ATI_RADEON_RS300_X4, RADEON_RS300, 0 }, 287 { PCI_PRODUCT_ATI_RADEON_RS300_7834, RADEON_RS300, 0 }, 288 { PCI_PRODUCT_ATI_RADEON_RS300_7835, RADEON_RS300, RFB_MOB }, 289 290 /* RV280 family */ 291 { PCI_PRODUCT_ATI_RADEON_RV280_5960, RADEON_RV280, 0 }, 292 { PCI_PRODUCT_ATI_RADEON_RV280_5961, RADEON_RV280, 0 }, 293 { PCI_PRODUCT_ATI_RADEON_RV280_5962, RADEON_RV280, 0 }, 294 { PCI_PRODUCT_ATI_RADEON_RV280_5963, RADEON_RV280, 0 }, 295 { PCI_PRODUCT_ATI_RADEON_RV280_5964, RADEON_RV280, 0 }, 296 { PCI_PRODUCT_ATI_RADEON_RV280_5C61, RADEON_RV280, RFB_MOB }, 297 { PCI_PRODUCT_ATI_RADEON_RV280_5C63, RADEON_RV280, RFB_MOB }, 298 299 /* R300 family */ 300 { PCI_PRODUCT_ATI_RADEON_R300_AD, RADEON_R300, 0 }, 301 { PCI_PRODUCT_ATI_RADEON_R300_AE, RADEON_R300, 0 }, 302 { PCI_PRODUCT_ATI_RADEON_R300_AF, RADEON_R300, 0 }, 303 { PCI_PRODUCT_ATI_RADEON_R300_AG, RADEON_R300, 0 }, 304 { PCI_PRODUCT_ATI_RADEON_R300_ND, RADEON_R300, 0 }, 305 { PCI_PRODUCT_ATI_RADEON_R300_NE, RADEON_R300, 0 }, 306 { PCI_PRODUCT_ATI_RADEON_R300_NF, RADEON_R300, 0 }, 307 { PCI_PRODUCT_ATI_RADEON_R300_NG, RADEON_R300, 0 }, 308 309 /* RV350/RV360 family */ 310 { PCI_PRODUCT_ATI_RADEON_RV350_AP, RADEON_RV350, 0 }, 311 { PCI_PRODUCT_ATI_RADEON_RV350_AQ, RADEON_RV350, 0 }, 312 { PCI_PRODUCT_ATI_RADEON_RV360_AR, RADEON_RV350, 0 }, 313 { PCI_PRODUCT_ATI_RADEON_RV350_AS, RADEON_RV350, 0 }, 314 { PCI_PRODUCT_ATI_RADEON_RV350_AT, RADEON_RV350, 0 }, 315 { PCI_PRODUCT_ATI_RADEON_RV350_AV, RADEON_RV350, 0 }, 316 { PCI_PRODUCT_ATI_RADEON_RV350_NP, RADEON_RV350, RFB_MOB }, 317 { PCI_PRODUCT_ATI_RADEON_RV350_NQ, RADEON_RV350, RFB_MOB }, 318 { PCI_PRODUCT_ATI_RADEON_RV350_NR, RADEON_RV350, RFB_MOB }, 319 { PCI_PRODUCT_ATI_RADEON_RV350_NS, RADEON_RV350, RFB_MOB }, 320 { PCI_PRODUCT_ATI_RADEON_RV350_NT, RADEON_RV350, RFB_MOB }, 321 { PCI_PRODUCT_ATI_RADEON_RV350_NV, RADEON_RV350, RFB_MOB }, 322 323 /* R350/R360 family */ 324 { PCI_PRODUCT_ATI_RADEON_R350_AH, RADEON_R350, 0 }, 325 { PCI_PRODUCT_ATI_RADEON_R350_AI, RADEON_R350, 0 }, 326 { PCI_PRODUCT_ATI_RADEON_R350_AJ, RADEON_R350, 0 }, 327 { PCI_PRODUCT_ATI_RADEON_R350_AK, RADEON_R350, 0 }, 328 { PCI_PRODUCT_ATI_RADEON_R350_NH, RADEON_R350, 0 }, 329 { PCI_PRODUCT_ATI_RADEON_R350_NI, RADEON_R350, 0 }, 330 { PCI_PRODUCT_ATI_RADEON_R350_NK, RADEON_R350, 0 }, 331 { PCI_PRODUCT_ATI_RADEON_R360_NJ, RADEON_R350, 0 }, 332 333 /* RV380/RV370 family */ 334 { PCI_PRODUCT_ATI_RADEON_RV380_3150, RADEON_RV380, RFB_MOB }, 335 { PCI_PRODUCT_ATI_RADEON_RV380_3154, RADEON_RV380, RFB_MOB }, 336 { PCI_PRODUCT_ATI_RADEON_RV380_3E50, RADEON_RV380, 0 }, 337 { PCI_PRODUCT_ATI_RADEON_RV380_3E54, RADEON_RV380, 0 }, 338 { PCI_PRODUCT_ATI_RADEON_RV370_5460, RADEON_RV380, RFB_MOB }, 339 { PCI_PRODUCT_ATI_RADEON_RV370_5464, RADEON_RV380, RFB_MOB }, 340 { PCI_PRODUCT_ATI_RADEON_RV370_5B60, RADEON_RV380, 0 }, 341 { PCI_PRODUCT_ATI_RADEON_RV370_5B64, RADEON_RV380, 0 }, 342 { PCI_PRODUCT_ATI_RADEON_RV370_5B65, RADEON_RV380, 0 }, 343 344 /* R420/R423 family */ 345 { PCI_PRODUCT_ATI_RADEON_R420_JH, RADEON_R420, 0 }, 346 { PCI_PRODUCT_ATI_RADEON_R420_JI, RADEON_R420, 0 }, 347 { PCI_PRODUCT_ATI_RADEON_R420_JJ, RADEON_R420, 0 }, 348 { PCI_PRODUCT_ATI_RADEON_R420_JK, RADEON_R420, 0 }, 349 { PCI_PRODUCT_ATI_RADEON_R420_JL, RADEON_R420, 0 }, 350 { PCI_PRODUCT_ATI_RADEON_R420_JM, RADEON_R420, 0 }, 351 { PCI_PRODUCT_ATI_RADEON_R420_JN, RADEON_R420, RFB_MOB }, 352 { PCI_PRODUCT_ATI_RADEON_R420_JP, RADEON_R420, 0 }, 353 { PCI_PRODUCT_ATI_RADEON_R423_UH, RADEON_R420, 0 }, 354 { PCI_PRODUCT_ATI_RADEON_R423_UI, RADEON_R420, 0 }, 355 { PCI_PRODUCT_ATI_RADEON_R423_UJ, RADEON_R420, 0 }, 356 { PCI_PRODUCT_ATI_RADEON_R423_UK, RADEON_R420, 0 }, 357 { PCI_PRODUCT_ATI_RADEON_R423_UQ, RADEON_R420, 0 }, 358 { PCI_PRODUCT_ATI_RADEON_R423_UR, RADEON_R420, 0 }, 359 { PCI_PRODUCT_ATI_RADEON_R423_UT, RADEON_R420, 0 }, 360 { PCI_PRODUCT_ATI_RADEON_R423_5D57, RADEON_R420, 0 }, 361 { PCI_PRODUCT_ATI_RADEON_R430_554F, RADEON_R420, 0 }, 362 363 { 0, 0, 0 } 364 }; 365 366 static struct { 367 int divider; 368 int mask; 369 } radeonfb_dividers[] = { 370 { 1, 0 }, 371 { 2, 1 }, 372 { 3, 4 }, 373 { 4, 2 }, 374 { 6, 6 }, 375 { 8, 3 }, 376 { 12, 7 }, 377 { 0, 0 } 378 }; 379 380 /* 381 * This table taken from X11. 382 */ 383 static const struct { 384 int family; 385 struct radeon_tmds_pll plls[4]; 386 } radeonfb_tmds_pll[] = { 387 { RADEON_R100, {{12000, 0xa1b}, {-1, 0xa3f}}}, 388 { RADEON_RV100, {{12000, 0xa1b}, {-1, 0xa3f}}}, 389 { RADEON_RS100, {{0, 0}}}, 390 { RADEON_RV200, {{15000, 0xa1b}, {-1, 0xa3f}}}, 391 { RADEON_RS200, {{15000, 0xa1b}, {-1, 0xa3f}}}, 392 { RADEON_R200, {{15000, 0xa1b}, {-1, 0xa3f}}}, 393 { RADEON_RV250, {{15500, 0x81b}, {-1, 0x83f}}}, 394 { RADEON_RS300, {{0, 0}}}, 395 { RADEON_RV280, {{13000, 0x400f4}, {15000, 0x400f7}}}, 396 { RADEON_R300, {{-1, 0xb01cb}}}, 397 { RADEON_R350, {{-1, 0xb01cb}}}, 398 { RADEON_RV350, {{15000, 0xb0155}, {-1, 0xb01cb}}}, 399 { RADEON_RV380, {{15000, 0xb0155}, {-1, 0xb01cb}}}, 400 { RADEON_R420, {{-1, 0xb01cb}}}, 401 }; 402 403 #define RADEONFB_BACKLIGHT_MAX 255 /* Maximum backlight level. */ 404 405 406 CFATTACH_DECL(radeonfb, sizeof (struct radeonfb_softc), 407 radeonfb_match, radeonfb_attach, NULL, NULL); 408 409 static int 410 radeonfb_match(struct device *parent, struct cfdata *match, void *aux) 411 { 412 struct pci_attach_args *pa = aux; 413 int i; 414 415 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_ATI) 416 return 0; 417 418 for (i = 0; radeonfb_devices[i].devid; i++) { 419 if (PCI_PRODUCT(pa->pa_id) == radeonfb_devices[i].devid) 420 return 100; /* high to defeat VGA/VESA */ 421 } 422 423 return 0; 424 } 425 426 static void 427 radeonfb_attach(struct device *parent, struct device *dev, void *aux) 428 { 429 struct radeonfb_softc *sc = (struct radeonfb_softc *)dev; 430 struct pci_attach_args *pa = aux; 431 const char *mptr; 432 bus_size_t bsz; 433 pcireg_t screg; 434 int i, j, fg, bg, ul; 435 uint32_t v; 436 437 sc->sc_id = pa->pa_id; 438 for (i = 0; radeonfb_devices[i].devid; i++) { 439 if (PCI_PRODUCT(sc->sc_id) == radeonfb_devices[i].devid) 440 break; 441 } 442 443 pci_devinfo(sc->sc_id, pa->pa_class, 0, sc->sc_devinfo, 444 sizeof(sc->sc_devinfo)); 445 446 aprint_naive("\n"); 447 aprint_normal(": %s\n", sc->sc_devinfo); 448 449 DPRINTF((prop_dictionary_externalize(device_properties(dev)))); 450 451 KASSERT(radeonfb_devices[i].devid != 0); 452 sc->sc_pt = pa->pa_tag; 453 sc->sc_iot = pa->pa_iot; 454 sc->sc_pc = pa->pa_pc; 455 sc->sc_family = radeonfb_devices[i].family; 456 sc->sc_flags = radeonfb_devices[i].flags; 457 458 /* enable memory and IO access */ 459 screg = pci_conf_read(sc->sc_pc, sc->sc_pt, PCI_COMMAND_STATUS_REG); 460 screg |= PCI_FLAGS_IO_ENABLED | PCI_FLAGS_MEM_ENABLED; 461 pci_conf_write(sc->sc_pc, sc->sc_pt, PCI_COMMAND_STATUS_REG, screg); 462 463 /* 464 * Some flags are general to entire chip families, and rather 465 * than clutter up the table with them, we go ahead and set 466 * them here. 467 */ 468 switch (sc->sc_family) { 469 case RADEON_RS100: 470 case RADEON_RS200: 471 sc->sc_flags |= RFB_IGP | RFB_RV100; 472 break; 473 474 case RADEON_RV100: 475 case RADEON_RV200: 476 case RADEON_RV250: 477 case RADEON_RV280: 478 sc->sc_flags |= RFB_RV100; 479 break; 480 481 case RADEON_RS300: 482 sc->sc_flags |= RFB_SDAC | RFB_IGP | RFB_RV100; 483 break; 484 485 case RADEON_R300: 486 case RADEON_RV350: 487 case RADEON_R350: 488 case RADEON_RV380: 489 case RADEON_R420: 490 /* newer chips */ 491 sc->sc_flags |= RFB_R300; 492 break; 493 494 case RADEON_R100: 495 sc->sc_flags |= RFB_NCRTC2; 496 break; 497 } 498 499 if ((sc->sc_family == RADEON_RV200) || 500 (sc->sc_family == RADEON_RV250) || 501 (sc->sc_family == RADEON_RV280) || 502 (sc->sc_family == RADEON_RV350)) { 503 bool inverted = 0; 504 /* backlight level is linear */ 505 DPRINTF(("found RV* chip, backlight is supposedly linear\n")); 506 prop_dictionary_get_bool(device_properties(&sc->sc_dev), 507 "backlight_level_reverted", &inverted); 508 if (inverted) { 509 DPRINTF(("nope, it's inverted\n")); 510 sc->sc_flags |= RFB_INV_BLIGHT; 511 } 512 } else 513 sc->sc_flags |= RFB_INV_BLIGHT; 514 515 /* 516 * XXX: to support true multihead, this must change. 517 */ 518 sc->sc_ndisplays = 1; 519 520 /* XXX: */ 521 if (!HAS_CRTC2(sc)) { 522 sc->sc_ndisplays = 1; 523 } 524 525 if (pci_mapreg_map(pa, RADEON_MAPREG_MMIO, PCI_MAPREG_TYPE_MEM, 0, 526 &sc->sc_regt, &sc->sc_regh, &sc->sc_regaddr, 527 &sc->sc_regsz) != 0) { 528 aprint_error("%s: unable to map registers!\n", XNAME(sc)); 529 goto error; 530 } 531 532 /* scratch register test... */ 533 if (radeonfb_scratch_test(sc, RADEON_BIOS_0_SCRATCH, 0x55555555) || 534 radeonfb_scratch_test(sc, RADEON_BIOS_0_SCRATCH, 0xaaaaaaaa)) { 535 aprint_error("%s: scratch register test failed!\n", XNAME(sc)); 536 goto error; 537 } 538 539 PRINTREG(RADEON_BIOS_4_SCRATCH); 540 PRINTREG(RADEON_FP_GEN_CNTL); 541 PRINTREG(RADEON_FP2_GEN_CNTL); 542 PRINTREG(RADEON_TMDS_CNTL); 543 PRINTREG(RADEON_TMDS_TRANSMITTER_CNTL); 544 PRINTREG(RADEON_TMDS_PLL_CNTL); 545 PRINTREG(RADEON_LVDS_GEN_CNTL); 546 PRINTREG(RADEON_FP_HORZ_STRETCH); 547 PRINTREG(RADEON_FP_VERT_STRETCH); 548 549 /* XXX: RV100 specific */ 550 PUT32(sc, RADEON_TMDS_PLL_CNTL, 0xa27); 551 552 PATCH32(sc, RADEON_TMDS_TRANSMITTER_CNTL, 553 RADEON_TMDS_TRANSMITTER_PLLEN, 554 RADEON_TMDS_TRANSMITTER_PLLEN | RADEON_TMDS_TRANSMITTER_PLLRST); 555 556 radeonfb_i2c_init(sc); 557 558 radeonfb_loadbios(sc, pa); 559 560 #ifdef RADEON_BIOS_INIT 561 if (radeonfb_bios_init(sc)) { 562 aprint_error("%s: BIOS inititialization failed\n", XNAME(sc)); 563 goto error; 564 } 565 #endif 566 567 if (radeonfb_getclocks(sc)) { 568 aprint_error("%s: Unable to get reference clocks from BIOS\n", 569 XNAME(sc)); 570 goto error; 571 } 572 573 if (radeonfb_gettmds(sc)) { 574 aprint_error("%s: Unable to identify TMDS PLL settings\n", 575 XNAME(sc)); 576 goto error; 577 } 578 579 aprint_verbose("%s: refclk = %d.%03d MHz, refdiv = %d " 580 "minpll = %d, maxpll = %d\n", XNAME(sc), 581 (int)sc->sc_refclk / 1000, (int)sc->sc_refclk % 1000, 582 (int)sc->sc_refdiv, (int)sc->sc_minpll, (int)sc->sc_maxpll); 583 584 radeonfb_getconnectors(sc); 585 586 radeonfb_set_fbloc(sc); 587 588 for (i = 0; radeonfb_limits[i].size; i++) { 589 if (sc->sc_memsz >= radeonfb_limits[i].size) { 590 sc->sc_maxx = radeonfb_limits[i].maxx; 591 sc->sc_maxy = radeonfb_limits[i].maxy; 592 sc->sc_maxbpp = radeonfb_limits[i].maxbpp; 593 /* framebuffer offset, start at a 4K page */ 594 sc->sc_fboffset = sc->sc_memsz / 595 radeonfb_limits[i].maxdisp; 596 /* 597 * we use the fbsize to figure out where we can store 598 * things like cursor data. 599 */ 600 sc->sc_fbsize = 601 ROUNDUP(ROUNDUP(sc->sc_maxx * sc->sc_maxbpp / 8 , 602 RADEON_STRIDEALIGN) * sc->sc_maxy, 603 4096); 604 break; 605 } 606 } 607 608 609 radeonfb_init_misc(sc); 610 radeonfb_init_palette(sc, 0); 611 if (HAS_CRTC2(sc)) 612 radeonfb_init_palette(sc, 1); 613 614 /* program the DAC wirings */ 615 for (i = 0; i < (HAS_CRTC2(sc) ? 2 : 1); i++) { 616 switch (sc->sc_ports[i].rp_dac_type) { 617 case RADEON_DAC_PRIMARY: 618 PATCH32(sc, RADEON_DAC_CNTL2, 619 i ? RADEON_DAC2_DAC_CLK_SEL : 0, 620 ~RADEON_DAC2_DAC_CLK_SEL); 621 break; 622 case RADEON_DAC_TVDAC: 623 /* we always use the TVDAC to drive a secondary analog 624 * CRT for now. if we ever support TV-out this will 625 * have to change. 626 */ 627 SET32(sc, RADEON_DAC_CNTL2, 628 RADEON_DAC2_DAC2_CLK_SEL); 629 PATCH32(sc, RADEON_DISP_HW_DEBUG, 630 i ? 0 : RADEON_CRT2_DISP1_SEL, 631 ~RADEON_CRT2_DISP1_SEL); 632 break; 633 } 634 } 635 PRINTREG(RADEON_DAC_CNTL2); 636 PRINTREG(RADEON_DISP_HW_DEBUG); 637 638 /* other DAC programming */ 639 v = GET32(sc, RADEON_DAC_CNTL); 640 v &= (RADEON_DAC_RANGE_CNTL_MASK | RADEON_DAC_BLANKING); 641 v |= RADEON_DAC_MASK_ALL | RADEON_DAC_8BIT_EN; 642 PUT32(sc, RADEON_DAC_CNTL, v); 643 PRINTREG(RADEON_DAC_CNTL); 644 645 /* XXX: this may need more investigation */ 646 PUT32(sc, RADEON_TV_DAC_CNTL, 0x00280203); 647 PRINTREG(RADEON_TV_DAC_CNTL); 648 649 /* enable TMDS */ 650 SET32(sc, RADEON_FP_GEN_CNTL, 651 RADEON_FP_TMDS_EN | 652 RADEON_FP_CRTC_DONT_SHADOW_VPAR | 653 RADEON_FP_CRTC_DONT_SHADOW_HEND); 654 CLR32(sc, RADEON_FP_GEN_CNTL, RADEON_FP_SEL_CRTC2); 655 if (HAS_CRTC2(sc)) 656 SET32(sc, RADEON_FP2_GEN_CNTL, RADEON_FP2_SRC_SEL_CRTC2); 657 658 /* 659 * we use bus_space_map instead of pci_mapreg, because we don't 660 * need the full aperature space. no point in wasting virtual 661 * address space we don't intend to use, right? 662 */ 663 if ((sc->sc_memsz < (4096 * 1024)) || 664 (pci_mapreg_info(sc->sc_pc, sc->sc_pt, RADEON_MAPREG_VRAM, 665 PCI_MAPREG_TYPE_MEM, &sc->sc_memaddr, &bsz, NULL) != 0) || 666 (bsz < sc->sc_memsz)) { 667 sc->sc_memsz = 0; 668 aprint_error("%s: Bad frame buffer configuration\n", 669 XNAME(sc)); 670 goto error; 671 } 672 673 /* 64 MB should be enough -- more just wastes map entries */ 674 if (sc->sc_memsz > (64 << 20)) 675 sc->sc_memsz = (64 << 20); 676 677 sc->sc_memt = pa->pa_memt; 678 if (bus_space_map(sc->sc_memt, sc->sc_memaddr, sc->sc_memsz, 679 BUS_SPACE_MAP_LINEAR, &sc->sc_memh) != 0) { 680 sc->sc_memsz = 0; 681 aprint_error("%s: Unable to map frame buffer\n", XNAME(sc)); 682 goto error; 683 } 684 685 aprint_normal("%s: %d MB aperture at 0x%08x, " 686 "%d KB registers at 0x%08x\n", XNAME(sc), 687 (int)sc->sc_memsz >> 20, (unsigned)sc->sc_memaddr, 688 (int)sc->sc_regsz >> 10, (unsigned)sc->sc_regaddr); 689 690 /* setup default video mode from devprop (allows PROM override) */ 691 sc->sc_defaultmode = radeonfb_default_mode; 692 if (prop_dictionary_get_cstring_nocopy(device_properties(&sc->sc_dev), 693 "videomode", &mptr)) { 694 695 strncpy(sc->sc_modebuf, mptr, sizeof(sc->sc_modebuf)); 696 sc->sc_defaultmode = sc->sc_modebuf; 697 } 698 699 /* initialize some basic display parameters */ 700 for (i = 0; i < sc->sc_ndisplays; i++) { 701 struct radeonfb_display *dp = &sc->sc_displays[i]; 702 struct rasops_info *ri; 703 long defattr; 704 struct wsemuldisplaydev_attach_args aa; 705 706 /* 707 * Figure out how many "displays" (desktops) we are going to 708 * support. If more than one, then each CRTC gets its own 709 * programming. 710 * 711 * XXX: this code needs to change to support mergedfb. 712 * XXX: would be nice to allow this to be overridden 713 */ 714 if (HAS_CRTC2(sc) && (sc->sc_ndisplays == 1)) { 715 DPRINTF(("dual crtcs!\n")); 716 dp->rd_ncrtcs = 2; 717 dp->rd_crtcs[0].rc_number = 0; 718 dp->rd_crtcs[1].rc_number = 1; 719 } else { 720 dp->rd_ncrtcs = 1; 721 dp->rd_crtcs[0].rc_number = i; 722 } 723 724 /* set up port pointer */ 725 for (j = 0; j < dp->rd_ncrtcs; j++) { 726 dp->rd_crtcs[j].rc_port = 727 &sc->sc_ports[dp->rd_crtcs[j].rc_number]; 728 } 729 730 dp->rd_softc = sc; 731 dp->rd_wsmode = WSDISPLAYIO_MODE_EMUL; 732 dp->rd_bg = WS_DEFAULT_BG; 733 #if 0 734 dp->rd_bpp = sc->sc_maxbpp; /* XXX: for now */ 735 #else 736 dp->rd_bpp = RADEONFB_DEFAULT_DEPTH; /* XXX */ 737 #endif 738 /* for text mode, we pick a resolution that won't 739 * require panning */ 740 radeonfb_pickres(dp, &dp->rd_virtx, &dp->rd_virty, 0); 741 742 aprint_normal("%s: display %d: " 743 "initial virtual resolution %dx%d at %d bpp\n", 744 XNAME(sc), i, dp->rd_virtx, dp->rd_virty, dp->rd_bpp); 745 746 /* now select the *video mode* that we will use */ 747 for (j = 0; j < dp->rd_ncrtcs; j++) { 748 const struct videomode *vmp; 749 vmp = radeonfb_port_mode(sc, dp->rd_crtcs[j].rc_port, 750 dp->rd_virtx, dp->rd_virty); 751 752 /* 753 * virtual resolution should be at least as high as 754 * physical 755 */ 756 if (dp->rd_virtx < vmp->hdisplay || 757 dp->rd_virty < vmp->vdisplay) { 758 dp->rd_virtx = vmp->hdisplay; 759 dp->rd_virty = vmp->vdisplay; 760 } 761 762 dp->rd_crtcs[j].rc_videomode = *vmp; 763 printf("%s: port %d: physical %dx%d %dHz\n", 764 XNAME(sc), j, vmp->hdisplay, vmp->vdisplay, 765 DIVIDE(DIVIDE(vmp->dot_clock * 1000, 766 vmp->htotal), vmp->vtotal)); 767 } 768 769 /* N.B.: radeon wants 64-byte aligned stride */ 770 dp->rd_stride = dp->rd_virtx * dp->rd_bpp / 8; 771 dp->rd_stride = ROUNDUP(dp->rd_stride, RADEON_STRIDEALIGN); 772 773 dp->rd_offset = sc->sc_fboffset * i; 774 dp->rd_fbptr = (vaddr_t)bus_space_vaddr(sc->sc_memt, 775 sc->sc_memh) + dp->rd_offset; 776 dp->rd_curoff = sc->sc_fbsize; 777 dp->rd_curptr = dp->rd_fbptr + dp->rd_curoff; 778 779 DPRINTF(("fpbtr = %p\n", (void *)dp->rd_fbptr)); 780 781 switch (dp->rd_bpp) { 782 case 8: 783 dp->rd_format = 2; 784 break; 785 case 32: 786 dp->rd_format = 6; 787 break; 788 default: 789 aprint_error("%s: bad depth %d\n", XNAME(sc), 790 dp->rd_bpp); 791 goto error; 792 } 793 794 printf("init engine\n"); 795 /* XXX: this seems suspicious - per display engine 796 initialization? */ 797 radeonfb_engine_init(dp); 798 799 /* copy the template into place */ 800 dp->rd_wsscreens_storage[0] = radeonfb_stdscreen; 801 dp->rd_wsscreens = dp->rd_wsscreens_storage; 802 803 /* and make up the list */ 804 dp->rd_wsscreenlist.nscreens = 1; 805 dp->rd_wsscreenlist.screens = 806 (const struct wsscreen_descr **)&dp->rd_wsscreens; 807 808 vcons_init(&dp->rd_vd, dp, dp->rd_wsscreens, 809 &radeonfb_accessops); 810 811 dp->rd_vd.init_screen = radeonfb_init_screen; 812 813 dp->rd_console = 1; 814 815 dp->rd_vscreen.scr_flags |= VCONS_SCREEN_IS_STATIC; 816 817 818 vcons_init_screen(&dp->rd_vd, &dp->rd_vscreen, 819 dp->rd_console, &defattr); 820 821 ri = &dp->rd_vscreen.scr_ri; 822 823 /* clear the screen */ 824 rasops_unpack_attr(defattr, &fg, &bg, &ul); 825 radeonfb_rectfill(dp, 0, 0, ri->ri_width, ri->ri_height, 826 ri->ri_devcmap[bg & 0xf]); 827 828 dp->rd_wsscreens->textops = &ri->ri_ops; 829 dp->rd_wsscreens->capabilities = ri->ri_caps; 830 dp->rd_wsscreens->nrows = ri->ri_rows; 831 dp->rd_wsscreens->ncols = ri->ri_cols; 832 833 #ifdef SPLASHSCREEN 834 dp->rd_splash.si_depth = ri->ri_depth; 835 dp->rd_splash.si_bits = ri->ri_bits; 836 dp->rd_splash.si_hwbits = ri->ri_hwbits; 837 dp->rd_splash.si_width = ri->ri_width; 838 dp->rd_splash.si_height = ri->ri_height; 839 dp->rd_splash.si_stride = ri->ri_stride; 840 dp->rd_splash.si_fillrect = NULL; 841 #endif 842 if (dp->rd_console) { 843 844 wsdisplay_cnattach(dp->rd_wsscreens, ri, 0, 0, 845 defattr); 846 #ifdef SPLASHSCREEN 847 splash_render(&dp->rd_splash, 848 SPLASH_F_CENTER|SPLASH_F_FILL); 849 #endif 850 851 #ifdef SPLASHSCREEN_PROGRESS 852 dp->rd_progress.sp_top = (dp->rd_virty / 8) * 7; 853 dp->rd_progress.sp_width = (dp->rd_virtx / 4) * 3; 854 dp->rd_progress.sp_left = (dp->rd_virtx - 855 dp->rd_progress.sp_width) / 2; 856 dp->rd_progress.sp_height = 20; 857 dp->rd_progress.sp_state = -1; 858 dp->rd_progress.sp_si = &dp->rd_splash; 859 splash_progress_init(&dp->rd_progress); 860 SCREEN_DISABLE_DRAWING(&dp->rd_vscreen); 861 #endif 862 863 } else { 864 865 /* 866 * since we're not the console we can postpone 867 * the rest until someone actually allocates a 868 * screen for us. but we do clear the screen 869 * at least. 870 */ 871 memset(ri->ri_bits, 0, 1024); 872 873 radeonfb_modeswitch(dp); 874 #ifdef SPLASHSCREEN 875 splash_render(&dp->rd_splash, 876 SPLASH_F_CENTER|SPLASH_F_FILL); 877 SCREEN_DISABLE_DRAWING(&dp->rd_vscreen); 878 #endif 879 } 880 881 aa.console = dp->rd_console; 882 aa.scrdata = &dp->rd_wsscreenlist; 883 aa.accessops = &radeonfb_accessops; 884 aa.accesscookie = &dp->rd_vd; 885 886 config_found(&sc->sc_dev, &aa, wsemuldisplaydevprint); 887 radeonfb_blank(dp, 0); 888 889 /* Initialise delayed lvds operations for backlight. */ 890 callout_init(&dp->rd_bl_lvds_co, 0); 891 callout_setfunc(&dp->rd_bl_lvds_co, 892 radeonfb_lvds_callout, dp); 893 } 894 895 config_found_ia(dev, "drm", aux, radeonfb_drm_print); 896 897 return; 898 899 error: 900 if (sc->sc_biossz) 901 free(sc->sc_bios, M_DEVBUF); 902 903 if (sc->sc_regsz) 904 bus_space_unmap(sc->sc_regt, sc->sc_regh, sc->sc_regsz); 905 906 if (sc->sc_memsz) 907 bus_space_unmap(sc->sc_memt, sc->sc_memh, sc->sc_memsz); 908 } 909 910 static int 911 radeonfb_drm_print(void *aux, const char *pnp) 912 { 913 if (pnp) 914 aprint_normal("direct rendering for %s", pnp); 915 return (UNSUPP); 916 } 917 918 int 919 radeonfb_ioctl(void *v, void *vs, 920 unsigned long cmd, void *d, int flag, struct lwp *l) 921 { 922 struct vcons_data *vd; 923 struct radeonfb_display *dp; 924 struct radeonfb_softc *sc; 925 struct wsdisplay_param *param; 926 927 vd = (struct vcons_data *)v; 928 dp = (struct radeonfb_display *)vd->cookie; 929 sc = dp->rd_softc; 930 931 switch (cmd) { 932 case WSDISPLAYIO_GTYPE: 933 *(unsigned *)d = WSDISPLAY_TYPE_PCIMISC; 934 return 0; 935 936 case WSDISPLAYIO_GINFO: 937 if (vd->active != NULL) { 938 struct wsdisplay_fbinfo *fb; 939 fb = (struct wsdisplay_fbinfo *)d; 940 fb->width = dp->rd_virtx; 941 fb->height = dp->rd_virty; 942 fb->depth = dp->rd_bpp; 943 fb->cmsize = 256; 944 return 0; 945 } else 946 return ENODEV; 947 case WSDISPLAYIO_GVIDEO: 948 if (radeonfb_isblank(dp)) 949 *(unsigned *)d = WSDISPLAYIO_VIDEO_OFF; 950 else 951 *(unsigned *)d = WSDISPLAYIO_VIDEO_ON; 952 return 0; 953 954 case WSDISPLAYIO_SVIDEO: 955 radeonfb_blank(dp, 956 (*(unsigned int *)d == WSDISPLAYIO_VIDEO_OFF)); 957 return 0; 958 959 case WSDISPLAYIO_GETCMAP: 960 #if 0 961 if (dp->rd_bpp == 8) 962 return radeonfb_getcmap(sc, 963 (struct wsdisplay_cmap *)d); 964 #endif 965 return EINVAL; 966 967 case WSDISPLAYIO_PUTCMAP: 968 #if 0 969 if (dp->rd_bpp == 8) 970 return radeonfb_putcmap(sc, 971 (struct wsdisplay_cmap *)d); 972 #endif 973 return EINVAL; 974 975 case WSDISPLAYIO_LINEBYTES: 976 *(unsigned *)d = dp->rd_stride; 977 return 0; 978 979 case WSDISPLAYIO_SMODE: 980 if (*(int *)d != dp->rd_wsmode) { 981 dp->rd_wsmode = *(int *)d; 982 if ((dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) && 983 (dp->rd_vd.active)) { 984 radeonfb_engine_init(dp); 985 radeonfb_modeswitch(dp); 986 vcons_redraw_screen(dp->rd_vd.active); 987 } 988 } 989 return 0; 990 991 case WSDISPLAYIO_GCURMAX: 992 ((struct wsdisplay_curpos *)d)->x = RADEON_CURSORMAXX; 993 ((struct wsdisplay_curpos *)d)->y = RADEON_CURSORMAXY; 994 return 0; 995 996 case WSDISPLAYIO_SCURSOR: 997 return radeonfb_set_cursor(dp, (struct wsdisplay_cursor *)d); 998 999 case WSDISPLAYIO_GCURSOR: 1000 return EPASSTHROUGH; 1001 1002 case WSDISPLAYIO_GCURPOS: 1003 ((struct wsdisplay_curpos *)d)->x = dp->rd_cursor.rc_pos.x; 1004 ((struct wsdisplay_curpos *)d)->y = dp->rd_cursor.rc_pos.y; 1005 return 0; 1006 1007 case WSDISPLAYIO_SCURPOS: 1008 return radeonfb_set_curpos(dp, (struct wsdisplay_curpos *)d); 1009 1010 case WSDISPLAYIO_SSPLASH: 1011 #if defined(SPLASHSCREEN) 1012 if (*(int *)d == 1) { 1013 SCREEN_DISABLE_DRAWING(&dp->rd_vscreen); 1014 splash_render(&dp->rd_splash, 1015 SPLASH_F_CENTER|SPLASH_F_FILL); 1016 } else 1017 SCREEN_ENABLE_DRAWING(&dp->rd_vscreen); 1018 return 0; 1019 #else 1020 return ENODEV; 1021 #endif 1022 case WSDISPLAYIO_SPROGRESS: 1023 #if defined(SPLASHSCREEN) && defined(SPLASHSCREEN_PROGRESS) 1024 dp->rd_progress.sp_force = 1; 1025 splash_progress_update(&dp->rd_progress); 1026 dp->rd_progress.sp_force = 0; 1027 return 0; 1028 #else 1029 return ENODEV; 1030 #endif 1031 case WSDISPLAYIO_GETPARAM: 1032 param = (struct wsdisplay_param *)d; 1033 if (param->param == WSDISPLAYIO_PARAM_BACKLIGHT) { 1034 param->min = 0; 1035 param->max = RADEONFB_BACKLIGHT_MAX; 1036 param->curval = radeonfb_get_backlight(dp); 1037 return 0; 1038 } 1039 return EPASSTHROUGH; 1040 1041 case WSDISPLAYIO_SETPARAM: 1042 param = (struct wsdisplay_param *)d; 1043 if (param->param == WSDISPLAYIO_PARAM_BACKLIGHT) { 1044 return radeonfb_set_backlight(dp, param->curval); 1045 } 1046 return EPASSTHROUGH; 1047 1048 /* PCI config read/write passthrough. */ 1049 case PCI_IOC_CFGREAD: 1050 case PCI_IOC_CFGWRITE: 1051 return (pci_devioctl(sc->sc_pc, sc->sc_pt, cmd, d, flag, l)); 1052 1053 default: 1054 return EPASSTHROUGH; 1055 } 1056 } 1057 1058 paddr_t 1059 radeonfb_mmap(void *v, void *vs, off_t offset, int prot) 1060 { 1061 struct vcons_data *vd; 1062 struct radeonfb_display *dp; 1063 struct radeonfb_softc *sc; 1064 #ifdef RADEONFB_MMAP_BARS 1065 struct lwp *me; 1066 #endif 1067 paddr_t pa; 1068 1069 vd = (struct vcons_data *)v; 1070 dp = (struct radeonfb_display *)vd->cookie; 1071 sc = dp->rd_softc; 1072 1073 /* XXX: note that we don't allow mapping of registers right now */ 1074 /* XXX: this means that the XFree86 radeon driver won't work */ 1075 1076 if ((offset >= 0) && (offset < (dp->rd_virty * dp->rd_stride))) { 1077 pa = bus_space_mmap(sc->sc_memt, 1078 sc->sc_memaddr + dp->rd_offset + offset, 0, 1079 prot, BUS_SPACE_MAP_LINEAR); 1080 return pa; 1081 } 1082 1083 #ifdef RADEONFB_MMAP_BARS 1084 /* 1085 * restrict all other mappings to processes with superuser privileges 1086 * or the kernel itself 1087 */ 1088 me = curlwp; 1089 if (me != NULL) { 1090 if (kauth_authorize_generic(me->l_cred, KAUTH_GENERIC_ISSUSER, 1091 NULL) != 0) { 1092 printf("%s: mmap() rejected.\n", sc->sc_dev.dv_xname); 1093 return -1; 1094 } 1095 } 1096 1097 if ((offset >= sc->sc_regaddr) && 1098 (offset < sc->sc_regaddr + sc->sc_regsz)) { 1099 return bus_space_mmap(sc->sc_regt, offset, 0, prot, 1100 BUS_SPACE_MAP_LINEAR); 1101 } 1102 1103 if ((offset >= sc->sc_memaddr) && 1104 (offset < sc->sc_memaddr + sc->sc_memsz)) { 1105 return bus_space_mmap(sc->sc_memt, offset, 0, prot, 1106 BUS_SPACE_MAP_LINEAR); 1107 } 1108 1109 #ifdef PCI_MAGIC_IO_RANGE 1110 /* allow mapping of IO space */ 1111 if ((offset >= PCI_MAGIC_IO_RANGE) && 1112 (offset < PCI_MAGIC_IO_RANGE + 0x10000)) { 1113 pa = bus_space_mmap(sc->sc_iot, offset - PCI_MAGIC_IO_RANGE, 1114 0, prot, 0); 1115 return pa; 1116 } 1117 #endif /* macppc */ 1118 1119 #endif /* RADEONFB_MMAP_BARS */ 1120 1121 return -1; 1122 } 1123 1124 static void 1125 radeonfb_loadbios(struct radeonfb_softc *sc, struct pci_attach_args *pa) 1126 { 1127 bus_space_tag_t romt; 1128 bus_space_handle_t romh, biosh; 1129 bus_size_t romsz; 1130 bus_addr_t ptr; 1131 1132 if (pci_mapreg_map(pa, PCI_MAPREG_ROM, PCI_MAPREG_TYPE_ROM, 1133 BUS_SPACE_MAP_PREFETCHABLE, &romt, &romh, NULL, &romsz) != 0) { 1134 aprint_verbose("%s: unable to map BIOS!\n", XNAME(sc)); 1135 return; 1136 } 1137 1138 pci_find_rom(pa, romt, romh, PCI_ROM_CODE_TYPE_X86, &biosh, 1139 &sc->sc_biossz); 1140 if (sc->sc_biossz == 0) { 1141 aprint_verbose("%s: Video BIOS not present\n", XNAME(sc)); 1142 return; 1143 } 1144 1145 sc->sc_bios = malloc(sc->sc_biossz, M_DEVBUF, M_WAITOK); 1146 bus_space_read_region_1(romt, biosh, 0, sc->sc_bios, sc->sc_biossz); 1147 1148 /* unmap the PCI expansion rom */ 1149 bus_space_unmap(romt, romh, romsz); 1150 1151 /* turn off rom decoder now */ 1152 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM, 1153 pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM) & 1154 ~PCI_MAPREG_ROM_ENABLE); 1155 1156 ptr = GETBIOS16(sc, 0x48); 1157 if ((GETBIOS32(sc, ptr + 4) == 0x41544f4d /* "ATOM" */) || 1158 (GETBIOS32(sc, ptr + 4) == 0x4d4f5441 /* "MOTA" */)) { 1159 sc->sc_flags |= RFB_ATOM; 1160 } 1161 1162 aprint_verbose("%s: Found %d KB %s BIOS\n", XNAME(sc), 1163 (unsigned)sc->sc_biossz >> 10, IS_ATOM(sc) ? "ATOM" : "Legacy"); 1164 } 1165 1166 1167 uint32_t 1168 radeonfb_get32(struct radeonfb_softc *sc, uint32_t reg) 1169 { 1170 1171 return bus_space_read_4(sc->sc_regt, sc->sc_regh, reg); 1172 } 1173 1174 void 1175 radeonfb_put32(struct radeonfb_softc *sc, uint32_t reg, uint32_t val) 1176 { 1177 1178 bus_space_write_4(sc->sc_regt, sc->sc_regh, reg, val); 1179 } 1180 1181 void 1182 radeonfb_mask32(struct radeonfb_softc *sc, uint32_t reg, 1183 uint32_t andmask, uint32_t ormask) 1184 { 1185 int s; 1186 uint32_t val; 1187 1188 s = splhigh(); 1189 val = radeonfb_get32(sc, reg); 1190 val = (val & andmask) | ormask; 1191 radeonfb_put32(sc, reg, val); 1192 splx(s); 1193 } 1194 1195 uint32_t 1196 radeonfb_getindex(struct radeonfb_softc *sc, uint32_t idx) 1197 { 1198 int s; 1199 uint32_t val; 1200 1201 s = splhigh(); 1202 radeonfb_put32(sc, RADEON_MM_INDEX, idx); 1203 val = radeonfb_get32(sc, RADEON_MM_DATA); 1204 splx(s); 1205 1206 return (val); 1207 } 1208 1209 void 1210 radeonfb_putindex(struct radeonfb_softc *sc, uint32_t idx, uint32_t val) 1211 { 1212 int s; 1213 1214 s = splhigh(); 1215 radeonfb_put32(sc, RADEON_MM_INDEX, idx); 1216 radeonfb_put32(sc, RADEON_MM_DATA, val); 1217 splx(s); 1218 } 1219 1220 void 1221 radeonfb_maskindex(struct radeonfb_softc *sc, uint32_t idx, 1222 uint32_t andmask, uint32_t ormask) 1223 { 1224 int s; 1225 uint32_t val; 1226 1227 s = splhigh(); 1228 radeonfb_put32(sc, RADEON_MM_INDEX, idx); 1229 val = radeonfb_get32(sc, RADEON_MM_DATA); 1230 val = (val & andmask) | ormask; 1231 radeonfb_put32(sc, RADEON_MM_DATA, val); 1232 splx(s); 1233 } 1234 1235 uint32_t 1236 radeonfb_getpll(struct radeonfb_softc *sc, uint32_t idx) 1237 { 1238 int s; 1239 uint32_t val; 1240 1241 s = splhigh(); 1242 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, idx & 0x3f); 1243 val = radeonfb_get32(sc, RADEON_CLOCK_CNTL_DATA); 1244 if (HAS_R300CG(sc)) 1245 radeonfb_r300cg_workaround(sc); 1246 splx(s); 1247 1248 return (val); 1249 } 1250 1251 void 1252 radeonfb_putpll(struct radeonfb_softc *sc, uint32_t idx, uint32_t val) 1253 { 1254 int s; 1255 1256 s = splhigh(); 1257 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, (idx & 0x3f) | 1258 RADEON_PLL_WR_EN); 1259 radeonfb_put32(sc, RADEON_CLOCK_CNTL_DATA, val); 1260 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, 0); 1261 splx(s); 1262 } 1263 1264 void 1265 radeonfb_maskpll(struct radeonfb_softc *sc, uint32_t idx, 1266 uint32_t andmask, uint32_t ormask) 1267 { 1268 int s; 1269 uint32_t val; 1270 1271 s = splhigh(); 1272 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, (idx & 0x3f) | 1273 RADEON_PLL_WR_EN); 1274 val = radeonfb_get32(sc, RADEON_CLOCK_CNTL_DATA); 1275 val = (val & andmask) | ormask; 1276 radeonfb_put32(sc, RADEON_CLOCK_CNTL_DATA, val); 1277 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, 0); 1278 splx(s); 1279 } 1280 1281 int 1282 radeonfb_scratch_test(struct radeonfb_softc *sc, int reg, uint32_t v) 1283 { 1284 uint32_t saved; 1285 1286 saved = GET32(sc, reg); 1287 PUT32(sc, reg, v); 1288 if (GET32(sc, reg) != v) { 1289 return -1; 1290 } 1291 PUT32(sc, reg, saved); 1292 return 0; 1293 } 1294 1295 uintmax_t 1296 radeonfb_getprop_num(struct radeonfb_softc *sc, const char *name, 1297 uintmax_t defval) 1298 { 1299 prop_number_t pn; 1300 pn = prop_dictionary_get(device_properties(&sc->sc_dev), name); 1301 if (pn == NULL) { 1302 return defval; 1303 } 1304 KASSERT(prop_object_type(pn) == PROP_TYPE_NUMBER); 1305 return (prop_number_integer_value(pn)); 1306 } 1307 1308 int 1309 radeonfb_getclocks(struct radeonfb_softc *sc) 1310 { 1311 bus_addr_t ptr; 1312 int refclk = 0; 1313 int refdiv = 0; 1314 int minpll = 0; 1315 int maxpll = 0; 1316 1317 /* load initial property values if port/board provides them */ 1318 refclk = radeonfb_getprop_num(sc, "refclk", 0) & 0xffff; 1319 refdiv = radeonfb_getprop_num(sc, "refdiv", 0) & 0xffff; 1320 minpll = radeonfb_getprop_num(sc, "minpll", 0) & 0xffffffffU; 1321 maxpll = radeonfb_getprop_num(sc, "maxpll", 0) & 0xffffffffU; 1322 1323 if (refclk && refdiv && minpll && maxpll) 1324 goto dontprobe; 1325 1326 if (!sc->sc_biossz) { 1327 /* no BIOS */ 1328 aprint_verbose("%s: No video BIOS, using default clocks\n", 1329 XNAME(sc)); 1330 if (IS_IGP(sc)) 1331 refclk = refclk ? refclk : 1432; 1332 else 1333 refclk = refclk ? refclk : 2700; 1334 refdiv = refdiv ? refdiv : 12; 1335 minpll = minpll ? minpll : 12500; 1336 maxpll = maxpll ? maxpll : 35000; 1337 } else if (IS_ATOM(sc)) { 1338 /* ATOM BIOS */ 1339 ptr = GETBIOS16(sc, 0x48); 1340 ptr = GETBIOS16(sc, ptr + 32); /* aka MasterDataStart */ 1341 ptr = GETBIOS16(sc, ptr + 12); /* pll info block */ 1342 refclk = refclk ? refclk : GETBIOS16(sc, ptr + 82); 1343 minpll = minpll ? minpll : GETBIOS16(sc, ptr + 78); 1344 maxpll = maxpll ? maxpll : GETBIOS16(sc, ptr + 32); 1345 /* 1346 * ATOM BIOS doesn't supply a reference divider, so we 1347 * have to probe for it. 1348 */ 1349 if (refdiv < 2) 1350 refdiv = GETPLL(sc, RADEON_PPLL_REF_DIV) & 1351 RADEON_PPLL_REF_DIV_MASK; 1352 /* 1353 * if probe is zero, just assume one that should work 1354 * for most parts 1355 */ 1356 if (refdiv < 2) 1357 refdiv = 12; 1358 1359 } else { 1360 /* Legacy BIOS */ 1361 ptr = GETBIOS16(sc, 0x48); 1362 ptr = GETBIOS16(sc, ptr + 0x30); 1363 refclk = refclk ? refclk : GETBIOS16(sc, ptr + 0x0E); 1364 refdiv = refdiv ? refdiv : GETBIOS16(sc, ptr + 0x10); 1365 minpll = minpll ? minpll : GETBIOS32(sc, ptr + 0x12); 1366 maxpll = maxpll ? maxpll : GETBIOS32(sc, ptr + 0x16); 1367 } 1368 1369 1370 dontprobe: 1371 sc->sc_refclk = refclk * 10; 1372 sc->sc_refdiv = refdiv; 1373 sc->sc_minpll = minpll * 10; 1374 sc->sc_maxpll = maxpll * 10; 1375 return 0; 1376 } 1377 1378 int 1379 radeonfb_calc_dividers(struct radeonfb_softc *sc, uint32_t dotclock, 1380 uint32_t *postdivbit, uint32_t *feedbackdiv) 1381 { 1382 int i; 1383 uint32_t outfreq; 1384 int div; 1385 1386 DPRINTF(("dot clock: %u\n", dotclock)); 1387 for (i = 0; (div = radeonfb_dividers[i].divider) != 0; i++) { 1388 outfreq = div * dotclock; 1389 if ((outfreq >= sc->sc_minpll) && 1390 (outfreq <= sc->sc_maxpll)) { 1391 DPRINTF(("outfreq: %u\n", outfreq)); 1392 *postdivbit = 1393 ((uint32_t)radeonfb_dividers[i].mask << 16); 1394 DPRINTF(("post divider: %d (mask %x)\n", div, 1395 *postdivbit)); 1396 break; 1397 } 1398 } 1399 1400 if (div == 0) 1401 return 1; 1402 1403 *feedbackdiv = DIVIDE(sc->sc_refdiv * outfreq, sc->sc_refclk); 1404 DPRINTF(("feedback divider: %d\n", *feedbackdiv)); 1405 return 0; 1406 } 1407 1408 #if 0 1409 #ifdef RADEON_DEBUG 1410 static void 1411 dump_buffer(const char *pfx, void *buffer, unsigned int size) 1412 { 1413 char asc[17]; 1414 unsigned ptr = (unsigned)buffer; 1415 char *start = (char *)(ptr & ~0xf); 1416 char *end = (char *)(ptr + size); 1417 1418 end = (char *)(((unsigned)end + 0xf) & ~0xf); 1419 1420 if (pfx == NULL) { 1421 pfx = ""; 1422 } 1423 1424 while (start < end) { 1425 unsigned offset = (unsigned)start & 0xf; 1426 if (offset == 0) { 1427 printf("%s%x: ", pfx, (unsigned)start); 1428 } 1429 if (((unsigned)start < ptr) || 1430 ((unsigned)start >= (ptr + size))) { 1431 printf(" "); 1432 asc[offset] = ' '; 1433 } else { 1434 printf("%02x", *(unsigned char *)start); 1435 if ((*start >= ' ') && (*start <= '~')) { 1436 asc[offset] = *start; 1437 } else { 1438 asc[offset] = '.'; 1439 } 1440 } 1441 asc[offset + 1] = 0; 1442 if (offset % 2) { 1443 printf(" "); 1444 } 1445 if (offset == 15) { 1446 printf(" %s\n", asc); 1447 } 1448 start++; 1449 } 1450 } 1451 #endif 1452 #endif 1453 1454 int 1455 radeonfb_getconnectors(struct radeonfb_softc *sc) 1456 { 1457 int i; 1458 int found = 0; 1459 1460 for (i = 0; i < 2; i++) { 1461 sc->sc_ports[i].rp_mon_type = RADEON_MT_UNKNOWN; 1462 sc->sc_ports[i].rp_ddc_type = RADEON_DDC_NONE; 1463 sc->sc_ports[i].rp_dac_type = RADEON_DAC_UNKNOWN; 1464 sc->sc_ports[i].rp_conn_type = RADEON_CONN_NONE; 1465 sc->sc_ports[i].rp_tmds_type = RADEON_TMDS_UNKNOWN; 1466 } 1467 1468 /* 1469 * This logic is borrowed from Xorg's radeon driver. 1470 */ 1471 if (!sc->sc_biossz) 1472 goto nobios; 1473 1474 if (IS_ATOM(sc)) { 1475 /* not done yet */ 1476 } else { 1477 uint16_t ptr; 1478 int port = 0; 1479 1480 ptr = GETBIOS16(sc, 0x48); 1481 ptr = GETBIOS16(sc, ptr + 0x50); 1482 for (i = 1; i < 4; i++) { 1483 uint16_t entry; 1484 uint8_t conn, ddc, dac, tmds; 1485 1486 /* 1487 * Parse the connector table. From reading the code, 1488 * it appears to made up of 16-bit entries for each 1489 * connector. The 16-bits are defined as: 1490 * 1491 * bits 12-15 - connector type (0 == end of table) 1492 * bits 8-11 - DDC type 1493 * bits 5-7 - ??? 1494 * bit 4 - TMDS type (1 = EXT, 0 = INT) 1495 * bits 1-3 - ??? 1496 * bit 0 - DAC, 1 = TVDAC, 0 = primary 1497 */ 1498 if (!GETBIOS8(sc, ptr + i * 2) && i > 1) 1499 break; 1500 entry = GETBIOS16(sc, ptr + i * 2); 1501 1502 conn = (entry >> 12) & 0xf; 1503 ddc = (entry >> 8) & 0xf; 1504 dac = (entry & 0x1) ? RADEON_DAC_TVDAC : 1505 RADEON_DAC_PRIMARY; 1506 tmds = ((entry >> 4) & 0x1) ? RADEON_TMDS_EXT : 1507 RADEON_TMDS_INT; 1508 1509 if (conn == RADEON_CONN_NONE) 1510 continue; /* no connector */ 1511 1512 if ((found > 0) && 1513 (sc->sc_ports[port].rp_ddc_type == ddc)) { 1514 /* duplicate entry for same connector */ 1515 continue; 1516 } 1517 1518 /* internal DDC_DVI port gets priority */ 1519 if ((ddc == RADEON_DDC_DVI) || (port == 1)) 1520 port = 0; 1521 else 1522 port = 1; 1523 1524 sc->sc_ports[port].rp_ddc_type = 1525 ddc > RADEON_DDC_CRT2 ? RADEON_DDC_NONE : ddc; 1526 sc->sc_ports[port].rp_dac_type = dac; 1527 sc->sc_ports[port].rp_conn_type = 1528 min(conn, RADEON_CONN_UNSUPPORTED) ; 1529 1530 sc->sc_ports[port].rp_tmds_type = tmds; 1531 1532 if ((conn != RADEON_CONN_DVI_I) && 1533 (conn != RADEON_CONN_DVI_D) && 1534 (tmds == RADEON_TMDS_INT)) 1535 sc->sc_ports[port].rp_tmds_type = 1536 RADEON_TMDS_UNKNOWN; 1537 1538 found += (port + 1); 1539 } 1540 } 1541 1542 nobios: 1543 if (!found) { 1544 DPRINTF(("No connector info in BIOS!\n")); 1545 /* default, port 0 = internal TMDS, port 1 = CRT */ 1546 sc->sc_ports[0].rp_mon_type = RADEON_MT_UNKNOWN; 1547 sc->sc_ports[0].rp_ddc_type = RADEON_DDC_DVI; 1548 sc->sc_ports[0].rp_dac_type = RADEON_DAC_TVDAC; 1549 sc->sc_ports[0].rp_conn_type = RADEON_CONN_DVI_D; 1550 sc->sc_ports[0].rp_tmds_type = RADEON_TMDS_INT; 1551 1552 sc->sc_ports[1].rp_mon_type = RADEON_MT_UNKNOWN; 1553 sc->sc_ports[1].rp_ddc_type = RADEON_DDC_VGA; 1554 sc->sc_ports[1].rp_dac_type = RADEON_DAC_PRIMARY; 1555 sc->sc_ports[1].rp_conn_type = RADEON_CONN_CRT; 1556 sc->sc_ports[1].rp_tmds_type = RADEON_TMDS_EXT; 1557 } 1558 1559 /* 1560 * Fixup for RS300/RS350/RS400 chips, that lack a primary DAC. 1561 * these chips should use TVDAC for the VGA port. 1562 */ 1563 if (HAS_SDAC(sc)) { 1564 if (sc->sc_ports[0].rp_conn_type == RADEON_CONN_CRT) { 1565 sc->sc_ports[0].rp_dac_type = RADEON_DAC_TVDAC; 1566 sc->sc_ports[1].rp_dac_type = RADEON_DAC_PRIMARY; 1567 } else { 1568 sc->sc_ports[1].rp_dac_type = RADEON_DAC_TVDAC; 1569 sc->sc_ports[0].rp_dac_type = RADEON_DAC_PRIMARY; 1570 } 1571 } else if (!HAS_CRTC2(sc)) { 1572 sc->sc_ports[0].rp_dac_type = RADEON_DAC_PRIMARY; 1573 } 1574 1575 for (i = 0; i < 2; i++) { 1576 char edid[128]; 1577 uint8_t ddc; 1578 struct edid_info *eip = &sc->sc_ports[i].rp_edid; 1579 prop_data_t edid_data; 1580 1581 DPRINTF(("Port #%d:\n", i)); 1582 DPRINTF((" conn = %d\n", sc->sc_ports[i].rp_conn_type)); 1583 DPRINTF((" ddc = %d\n", sc->sc_ports[i].rp_ddc_type)); 1584 DPRINTF((" dac = %d\n", sc->sc_ports[i].rp_dac_type)); 1585 DPRINTF((" tmds = %d\n", sc->sc_ports[i].rp_tmds_type)); 1586 1587 sc->sc_ports[i].rp_edid_valid = 0; 1588 /* first look for static EDID data */ 1589 if ((edid_data = prop_dictionary_get(device_properties( 1590 &sc->sc_dev), "EDID")) != NULL) { 1591 1592 aprint_normal("%s: using static EDID\n", 1593 sc->sc_dev.dv_xname); 1594 memcpy(edid, prop_data_data_nocopy(edid_data), 128); 1595 if (edid_parse(edid, eip) == 0) { 1596 1597 sc->sc_ports[i].rp_edid_valid = 1; 1598 edid_print(eip); 1599 } 1600 } 1601 /* if we didn't find any we'll try to talk to the monitor */ 1602 if (sc->sc_ports[i].rp_edid_valid != 1) { 1603 1604 ddc = sc->sc_ports[i].rp_ddc_type; 1605 if (ddc != RADEON_DDC_NONE) { 1606 if ((radeonfb_i2c_read_edid(sc, ddc, edid) 1607 == 0) && (edid_parse(edid, eip) == 0)) { 1608 1609 sc->sc_ports[i].rp_edid_valid = 1; 1610 edid_print(eip); 1611 } 1612 } 1613 } 1614 } 1615 1616 return found; 1617 } 1618 1619 int 1620 radeonfb_gettmds(struct radeonfb_softc *sc) 1621 { 1622 int i; 1623 1624 if (!sc->sc_biossz) { 1625 goto nobios; 1626 } 1627 1628 if (IS_ATOM(sc)) { 1629 /* XXX: not done yet */ 1630 } else { 1631 uint16_t ptr; 1632 int n; 1633 1634 ptr = GETBIOS16(sc, 0x48); 1635 ptr = GETBIOS16(sc, ptr + 0x34); 1636 DPRINTF(("DFP table revision %d\n", GETBIOS8(sc, ptr))); 1637 if (GETBIOS8(sc, ptr) == 3) { 1638 /* revision three table */ 1639 n = GETBIOS8(sc, ptr + 5) + 1; 1640 n = min(n, 4); 1641 1642 memset(sc->sc_tmds_pll, 0, sizeof (sc->sc_tmds_pll)); 1643 for (i = 0; i < n; i++) { 1644 sc->sc_tmds_pll[i].rtp_pll = GETBIOS32(sc, 1645 ptr + i * 10 + 8); 1646 sc->sc_tmds_pll[i].rtp_freq = GETBIOS16(sc, 1647 ptr + i * 10 + 0x10); 1648 DPRINTF(("TMDS_PLL dot clock %d pll %x\n", 1649 sc->sc_tmds_pll[i].rtp_freq, 1650 sc->sc_tmds_pll[i].rtp_pll)); 1651 } 1652 return 0; 1653 } 1654 } 1655 1656 nobios: 1657 DPRINTF(("no suitable DFP table present\n")); 1658 for (i = 0; 1659 i < sizeof (radeonfb_tmds_pll) / sizeof (radeonfb_tmds_pll[0]); 1660 i++) { 1661 int j; 1662 1663 if (radeonfb_tmds_pll[i].family != sc->sc_family) 1664 continue; 1665 1666 for (j = 0; j < 4; j++) { 1667 sc->sc_tmds_pll[j] = radeonfb_tmds_pll[i].plls[j]; 1668 DPRINTF(("TMDS_PLL dot clock %d pll %x\n", 1669 sc->sc_tmds_pll[j].rtp_freq, 1670 sc->sc_tmds_pll[j].rtp_pll)); 1671 } 1672 return 0; 1673 } 1674 1675 return -1; 1676 } 1677 1678 const struct videomode * 1679 radeonfb_modelookup(const char *name) 1680 { 1681 int i; 1682 1683 for (i = 0; i < videomode_count; i++) 1684 if (!strcmp(name, videomode_list[i].name)) 1685 return &videomode_list[i]; 1686 1687 return NULL; 1688 } 1689 1690 void 1691 radeonfb_pllwriteupdate(struct radeonfb_softc *sc, int crtc) 1692 { 1693 if (crtc) { 1694 while (GETPLL(sc, RADEON_P2PLL_REF_DIV) & 1695 RADEON_P2PLL_ATOMIC_UPDATE_R); 1696 SETPLL(sc, RADEON_P2PLL_REF_DIV, RADEON_P2PLL_ATOMIC_UPDATE_W); 1697 } else { 1698 while (GETPLL(sc, RADEON_PPLL_REF_DIV) & 1699 RADEON_PPLL_ATOMIC_UPDATE_R); 1700 SETPLL(sc, RADEON_PPLL_REF_DIV, RADEON_PPLL_ATOMIC_UPDATE_W); 1701 } 1702 } 1703 1704 void 1705 radeonfb_pllwaitatomicread(struct radeonfb_softc *sc, int crtc) 1706 { 1707 int i; 1708 1709 for (i = 10000; i; i--) { 1710 if (crtc) { 1711 if (GETPLL(sc, RADEON_P2PLL_REF_DIV) & 1712 RADEON_P2PLL_ATOMIC_UPDATE_R) 1713 break; 1714 } else { 1715 if (GETPLL(sc, RADEON_PPLL_REF_DIV) & 1716 RADEON_PPLL_ATOMIC_UPDATE_R) 1717 break; 1718 } 1719 } 1720 } 1721 1722 void 1723 radeonfb_program_vclk(struct radeonfb_softc *sc, int dotclock, int crtc) 1724 { 1725 uint32_t pbit = 0; 1726 uint32_t feed = 0; 1727 uint32_t data; 1728 #if 1 1729 int i; 1730 #endif 1731 1732 radeonfb_calc_dividers(sc, dotclock, &pbit, &feed); 1733 1734 if (crtc == 0) { 1735 1736 /* XXXX: mobility workaround missing */ 1737 /* XXXX: R300 stuff missing */ 1738 1739 PATCHPLL(sc, RADEON_VCLK_ECP_CNTL, 1740 RADEON_VCLK_SRC_SEL_CPUCLK, 1741 ~RADEON_VCLK_SRC_SEL_MASK); 1742 1743 /* put vclk into reset, use atomic updates */ 1744 SETPLL(sc, RADEON_PPLL_CNTL, 1745 RADEON_PPLL_REFCLK_SEL | 1746 RADEON_PPLL_FBCLK_SEL | 1747 RADEON_PPLL_RESET | 1748 RADEON_PPLL_ATOMIC_UPDATE_EN | 1749 RADEON_PPLL_VGA_ATOMIC_UPDATE_EN); 1750 1751 /* select clock 3 */ 1752 #if 0 1753 PATCH32(sc, RADEON_CLOCK_CNTL_INDEX, RADEON_PLL_DIV_SEL, 1754 ~RADEON_PLL_DIV_SEL); 1755 #else 1756 PATCH32(sc, RADEON_CLOCK_CNTL_INDEX, 0, 1757 ~RADEON_PLL_DIV_SEL); 1758 #endif 1759 1760 /* XXX: R300 family -- program divider differently? */ 1761 1762 /* program reference divider */ 1763 PATCHPLL(sc, RADEON_PPLL_REF_DIV, sc->sc_refdiv, 1764 ~RADEON_PPLL_REF_DIV_MASK); 1765 PRINTPLL(RADEON_PPLL_REF_DIV); 1766 1767 #if 0 1768 data = GETPLL(sc, RADEON_PPLL_DIV_3); 1769 data &= ~(RADEON_PPLL_FB3_DIV_MASK | 1770 RADEON_PPLL_POST3_DIV_MASK); 1771 data |= pbit; 1772 data |= (feed & RADEON_PPLL_FB3_DIV_MASK); 1773 PUTPLL(sc, RADEON_PPLL_DIV_3, data); 1774 #else 1775 for (i = 0; i < 4; i++) { 1776 } 1777 #endif 1778 1779 /* use the atomic update */ 1780 radeonfb_pllwriteupdate(sc, crtc); 1781 1782 /* and wait for it to complete */ 1783 radeonfb_pllwaitatomicread(sc, crtc); 1784 1785 /* program HTOTAL (why?) */ 1786 PUTPLL(sc, RADEON_HTOTAL_CNTL, 0); 1787 1788 /* drop reset */ 1789 CLRPLL(sc, RADEON_PPLL_CNTL, 1790 RADEON_PPLL_RESET | RADEON_PPLL_SLEEP | 1791 RADEON_PPLL_ATOMIC_UPDATE_EN | 1792 RADEON_PPLL_VGA_ATOMIC_UPDATE_EN); 1793 1794 PRINTPLL(RADEON_PPLL_CNTL); 1795 1796 /* give clock time to lock */ 1797 delay(50000); 1798 1799 PATCHPLL(sc, RADEON_VCLK_ECP_CNTL, 1800 RADEON_VCLK_SRC_SEL_PPLLCLK, 1801 ~RADEON_VCLK_SRC_SEL_MASK); 1802 1803 } else { 1804 1805 PATCHPLL(sc, RADEON_PIXCLKS_CNTL, 1806 RADEON_PIX2CLK_SRC_SEL_CPUCLK, 1807 ~RADEON_PIX2CLK_SRC_SEL_MASK); 1808 1809 /* put vclk into reset, use atomic updates */ 1810 SETPLL(sc, RADEON_P2PLL_CNTL, 1811 RADEON_P2PLL_RESET | 1812 RADEON_P2PLL_ATOMIC_UPDATE_EN | 1813 RADEON_P2PLL_VGA_ATOMIC_UPDATE_EN); 1814 1815 /* XXX: R300 family -- program divider differently? */ 1816 1817 /* program reference divider */ 1818 PATCHPLL(sc, RADEON_P2PLL_REF_DIV, sc->sc_refdiv, 1819 ~RADEON_P2PLL_REF_DIV_MASK); 1820 1821 /* program feedback and post dividers */ 1822 data = GETPLL(sc, RADEON_P2PLL_DIV_0); 1823 data &= ~(RADEON_P2PLL_FB0_DIV_MASK | 1824 RADEON_P2PLL_POST0_DIV_MASK); 1825 data |= pbit; 1826 data |= (feed & RADEON_P2PLL_FB0_DIV_MASK); 1827 PUTPLL(sc, RADEON_P2PLL_DIV_0, data); 1828 1829 /* use the atomic update */ 1830 radeonfb_pllwriteupdate(sc, crtc); 1831 1832 /* and wait for it to complete */ 1833 radeonfb_pllwaitatomicread(sc, crtc); 1834 1835 /* program HTOTAL (why?) */ 1836 PUTPLL(sc, RADEON_HTOTAL2_CNTL, 0); 1837 1838 /* drop reset */ 1839 CLRPLL(sc, RADEON_P2PLL_CNTL, 1840 RADEON_P2PLL_RESET | RADEON_P2PLL_SLEEP | 1841 RADEON_P2PLL_ATOMIC_UPDATE_EN | 1842 RADEON_P2PLL_VGA_ATOMIC_UPDATE_EN); 1843 1844 /* allow time for clock to lock */ 1845 delay(50000); 1846 1847 PATCHPLL(sc, RADEON_PIXCLKS_CNTL, 1848 RADEON_PIX2CLK_SRC_SEL_P2PLLCLK, 1849 ~RADEON_PIX2CLK_SRC_SEL_MASK); 1850 } 1851 PRINTREG(RADEON_CRTC_MORE_CNTL); 1852 } 1853 1854 void 1855 radeonfb_modeswitch(struct radeonfb_display *dp) 1856 { 1857 struct radeonfb_softc *sc = dp->rd_softc; 1858 int i; 1859 1860 /* blank the display while we switch modes */ 1861 //radeonfb_blank(dp, 1); 1862 1863 #if 0 1864 SET32(sc, RADEON_CRTC_EXT_CNTL, 1865 RADEON_CRTC_VSYNC_DIS | RADEON_CRTC_HSYNC_DIS | 1866 RADEON_CRTC_DISPLAY_DIS /* | RADEON_CRTC_DISP_REQ_EN_B */); 1867 #endif 1868 1869 /* these registers might get in the way... */ 1870 PUT32(sc, RADEON_OVR_CLR, 0); 1871 PUT32(sc, RADEON_OVR_WID_LEFT_RIGHT, 0); 1872 PUT32(sc, RADEON_OVR_WID_TOP_BOTTOM, 0); 1873 PUT32(sc, RADEON_OV0_SCALE_CNTL, 0); 1874 PUT32(sc, RADEON_SUBPIC_CNTL, 0); 1875 PUT32(sc, RADEON_VIPH_CONTROL, 0); 1876 PUT32(sc, RADEON_I2C_CNTL_1, 0); 1877 PUT32(sc, RADEON_GEN_INT_CNTL, 0); 1878 PUT32(sc, RADEON_CAP0_TRIG_CNTL, 0); 1879 PUT32(sc, RADEON_CAP1_TRIG_CNTL, 0); 1880 PUT32(sc, RADEON_SURFACE_CNTL, 0); 1881 1882 for (i = 0; i < dp->rd_ncrtcs; i++) 1883 radeonfb_setcrtc(dp, i); 1884 1885 /* activate the display */ 1886 //radeonfb_blank(dp, 0); 1887 } 1888 1889 void 1890 radeonfb_setcrtc(struct radeonfb_display *dp, int index) 1891 { 1892 int crtc; 1893 struct videomode *mode; 1894 struct radeonfb_softc *sc; 1895 struct radeonfb_crtc *cp; 1896 uint32_t v; 1897 uint32_t gencntl; 1898 uint32_t htotaldisp; 1899 uint32_t hsyncstrt; 1900 uint32_t vtotaldisp; 1901 uint32_t vsyncstrt; 1902 uint32_t fphsyncstrt; 1903 uint32_t fpvsyncstrt; 1904 uint32_t fphtotaldisp; 1905 uint32_t fpvtotaldisp; 1906 uint32_t pitch; 1907 1908 sc = dp->rd_softc; 1909 cp = &dp->rd_crtcs[index]; 1910 crtc = cp->rc_number; 1911 mode = &cp->rc_videomode; 1912 1913 #if 1 1914 pitch = (((dp->rd_virtx * dp->rd_bpp) + ((dp->rd_bpp * 8) - 1)) / 1915 (dp->rd_bpp * 8)); 1916 #else 1917 pitch = (((sc->sc_maxx * sc->sc_maxbpp) + ((sc->sc_maxbpp * 8) - 1)) / 1918 (sc->sc_maxbpp * 8)); 1919 #endif 1920 //pitch = pitch | (pitch << 16); 1921 1922 switch (crtc) { 1923 case 0: 1924 gencntl = RADEON_CRTC_GEN_CNTL; 1925 htotaldisp = RADEON_CRTC_H_TOTAL_DISP; 1926 hsyncstrt = RADEON_CRTC_H_SYNC_STRT_WID; 1927 vtotaldisp = RADEON_CRTC_V_TOTAL_DISP; 1928 vsyncstrt = RADEON_CRTC_V_SYNC_STRT_WID; 1929 fpvsyncstrt = RADEON_FP_V_SYNC_STRT_WID; 1930 fphsyncstrt = RADEON_FP_H_SYNC_STRT_WID; 1931 fpvtotaldisp = RADEON_FP_CRTC_V_TOTAL_DISP; 1932 fphtotaldisp = RADEON_FP_CRTC_H_TOTAL_DISP; 1933 break; 1934 case 1: 1935 gencntl = RADEON_CRTC2_GEN_CNTL; 1936 htotaldisp = RADEON_CRTC2_H_TOTAL_DISP; 1937 hsyncstrt = RADEON_CRTC2_H_SYNC_STRT_WID; 1938 vtotaldisp = RADEON_CRTC2_V_TOTAL_DISP; 1939 vsyncstrt = RADEON_CRTC2_V_SYNC_STRT_WID; 1940 fpvsyncstrt = RADEON_FP_V2_SYNC_STRT_WID; 1941 fphsyncstrt = RADEON_FP_H2_SYNC_STRT_WID; 1942 fpvtotaldisp = RADEON_FP_CRTC2_V_TOTAL_DISP; 1943 fphtotaldisp = RADEON_FP_CRTC2_H_TOTAL_DISP; 1944 break; 1945 default: 1946 panic("Bad CRTC!"); 1947 break; 1948 } 1949 1950 /* 1951 * CRTC_GEN_CNTL - depth, accelerator mode, etc. 1952 */ 1953 /* only bother with 32bpp and 8bpp */ 1954 v = dp->rd_format << RADEON_CRTC_PIX_WIDTH_SHIFT; 1955 1956 if (crtc == 1) { 1957 v |= RADEON_CRTC2_CRT2_ON | RADEON_CRTC2_EN; 1958 } else { 1959 v |= RADEON_CRTC_EXT_DISP_EN | RADEON_CRTC_EN; 1960 } 1961 1962 if (mode->flags & VID_DBLSCAN) 1963 v |= RADEON_CRTC2_DBL_SCAN_EN; 1964 1965 if (mode->flags & VID_INTERLACE) 1966 v |= RADEON_CRTC2_INTERLACE_EN; 1967 1968 if (mode->flags & VID_CSYNC) { 1969 v |= RADEON_CRTC2_CSYNC_EN; 1970 if (crtc == 1) 1971 v |= RADEON_CRTC2_VSYNC_TRISTAT; 1972 } 1973 1974 PUT32(sc, gencntl, v); 1975 DPRINTF(("CRTC%s_GEN_CNTL = %08x\n", crtc ? "2" : "", v)); 1976 1977 /* 1978 * CRTC_EXT_CNTL - preserve disable flags, set ATI linear and EXT_CNT 1979 */ 1980 v = GET32(sc, RADEON_CRTC_EXT_CNTL); 1981 if (crtc == 0) { 1982 v &= (RADEON_CRTC_VSYNC_DIS | RADEON_CRTC_HSYNC_DIS | 1983 RADEON_CRTC_DISPLAY_DIS); 1984 v |= RADEON_XCRT_CNT_EN | RADEON_VGA_ATI_LINEAR; 1985 if (mode->flags & VID_CSYNC) 1986 v |= RADEON_CRTC_VSYNC_TRISTAT; 1987 } 1988 /* unconditional turn on CRT, in case first CRTC is DFP */ 1989 v |= RADEON_CRTC_CRT_ON; 1990 PUT32(sc, RADEON_CRTC_EXT_CNTL, v); 1991 PRINTREG(RADEON_CRTC_EXT_CNTL); 1992 1993 /* 1994 * H_TOTAL_DISP 1995 */ 1996 v = ((mode->hdisplay / 8) - 1) << 16; 1997 v |= (mode->htotal / 8) - 1; 1998 PUT32(sc, htotaldisp, v); 1999 DPRINTF(("CRTC%s_H_TOTAL_DISP = %08x\n", crtc ? "2" : "", v)); 2000 PUT32(sc, fphtotaldisp, v); 2001 DPRINTF(("FP_H%s_TOTAL_DISP = %08x\n", crtc ? "2" : "", v)); 2002 2003 /* 2004 * H_SYNC_STRT_WID 2005 */ 2006 v = (((mode->hsync_end - mode->hsync_start) / 8) << 16); 2007 v |= mode->hsync_start; 2008 if (mode->flags & VID_NHSYNC) 2009 v |= RADEON_CRTC_H_SYNC_POL; 2010 PUT32(sc, hsyncstrt, v); 2011 DPRINTF(("CRTC%s_H_SYNC_STRT_WID = %08x\n", crtc ? "2" : "", v)); 2012 PUT32(sc, fphsyncstrt, v); 2013 DPRINTF(("FP_H%s_SYNC_STRT_WID = %08x\n", crtc ? "2" : "", v)); 2014 2015 /* 2016 * V_TOTAL_DISP 2017 */ 2018 v = ((mode->vdisplay - 1) << 16); 2019 v |= (mode->vtotal - 1); 2020 PUT32(sc, vtotaldisp, v); 2021 DPRINTF(("CRTC%s_V_TOTAL_DISP = %08x\n", crtc ? "2" : "", v)); 2022 PUT32(sc, fpvtotaldisp, v); 2023 DPRINTF(("FP_V%s_TOTAL_DISP = %08x\n", crtc ? "2" : "", v)); 2024 2025 /* 2026 * V_SYNC_STRT_WID 2027 */ 2028 v = ((mode->vsync_end - mode->vsync_start) << 16); 2029 v |= (mode->vsync_start - 1); 2030 if (mode->flags & VID_NVSYNC) 2031 v |= RADEON_CRTC_V_SYNC_POL; 2032 PUT32(sc, vsyncstrt, v); 2033 DPRINTF(("CRTC%s_V_SYNC_STRT_WID = %08x\n", crtc ? "2" : "", v)); 2034 PUT32(sc, fpvsyncstrt, v); 2035 DPRINTF(("FP_V%s_SYNC_STRT_WID = %08x\n", crtc ? "2" : "", v)); 2036 2037 radeonfb_program_vclk(sc, mode->dot_clock, crtc); 2038 2039 switch (crtc) { 2040 case 0: 2041 PUT32(sc, RADEON_CRTC_OFFSET, 0); 2042 PUT32(sc, RADEON_CRTC_OFFSET_CNTL, 0); 2043 PUT32(sc, RADEON_CRTC_PITCH, pitch); 2044 CLR32(sc, RADEON_DISP_MERGE_CNTL, RADEON_DISP_RGB_OFFSET_EN); 2045 2046 CLR32(sc, RADEON_CRTC_EXT_CNTL, 2047 RADEON_CRTC_VSYNC_DIS | RADEON_CRTC_HSYNC_DIS | 2048 RADEON_CRTC_DISPLAY_DIS /* | RADEON_CRTC_DISP_REQ_EN_B */); 2049 CLR32(sc, RADEON_CRTC_GEN_CNTL, RADEON_CRTC_DISP_REQ_EN_B); 2050 PRINTREG(RADEON_CRTC_EXT_CNTL); 2051 PRINTREG(RADEON_CRTC_GEN_CNTL); 2052 PRINTREG(RADEON_CLOCK_CNTL_INDEX); 2053 break; 2054 2055 case 1: 2056 PUT32(sc, RADEON_CRTC2_OFFSET, 0); 2057 PUT32(sc, RADEON_CRTC2_OFFSET_CNTL, 0); 2058 PUT32(sc, RADEON_CRTC2_PITCH, pitch); 2059 CLR32(sc, RADEON_DISP2_MERGE_CNTL, RADEON_DISP2_RGB_OFFSET_EN); 2060 CLR32(sc, RADEON_CRTC2_GEN_CNTL, 2061 RADEON_CRTC2_VSYNC_DIS | 2062 RADEON_CRTC2_HSYNC_DIS | 2063 RADEON_CRTC2_DISP_DIS | RADEON_CRTC2_DISP_REQ_EN_B); 2064 PRINTREG(RADEON_CRTC2_GEN_CNTL); 2065 break; 2066 } 2067 } 2068 2069 int 2070 radeonfb_isblank(struct radeonfb_display *dp) 2071 { 2072 uint32_t reg, mask; 2073 2074 if (dp->rd_crtcs[0].rc_number) { 2075 reg = RADEON_CRTC2_GEN_CNTL; 2076 mask = RADEON_CRTC2_DISP_DIS; 2077 } else { 2078 reg = RADEON_CRTC_EXT_CNTL; 2079 mask = RADEON_CRTC_DISPLAY_DIS; 2080 } 2081 return ((GET32(dp->rd_softc, reg) & mask) ? 1 : 0); 2082 } 2083 2084 void 2085 radeonfb_blank(struct radeonfb_display *dp, int blank) 2086 { 2087 struct radeonfb_softc *sc = dp->rd_softc; 2088 uint32_t reg, mask; 2089 uint32_t fpreg, fpval; 2090 int i; 2091 2092 for (i = 0; i < dp->rd_ncrtcs; i++) { 2093 2094 if (dp->rd_crtcs[i].rc_number) { 2095 reg = RADEON_CRTC2_GEN_CNTL; 2096 mask = RADEON_CRTC2_DISP_DIS; 2097 fpreg = RADEON_FP2_GEN_CNTL; 2098 fpval = RADEON_FP2_ON; 2099 } else { 2100 reg = RADEON_CRTC_EXT_CNTL; 2101 mask = RADEON_CRTC_DISPLAY_DIS; 2102 fpreg = RADEON_FP_GEN_CNTL; 2103 fpval = RADEON_FP_FPON; 2104 } 2105 2106 if (blank) { 2107 SET32(sc, reg, mask); 2108 CLR32(sc, fpreg, fpval); 2109 } else { 2110 CLR32(sc, reg, mask); 2111 SET32(sc, fpreg, fpval); 2112 } 2113 } 2114 PRINTREG(RADEON_FP_GEN_CNTL); 2115 PRINTREG(RADEON_FP2_GEN_CNTL); 2116 } 2117 2118 void 2119 radeonfb_init_screen(void *cookie, struct vcons_screen *scr, int existing, 2120 long *defattr) 2121 { 2122 struct radeonfb_display *dp = cookie; 2123 struct rasops_info *ri = &scr->scr_ri; 2124 2125 /* initialize font subsystem */ 2126 wsfont_init(); 2127 2128 DPRINTF(("init screen called, existing %d\n", existing)); 2129 2130 ri->ri_depth = dp->rd_bpp; 2131 ri->ri_width = dp->rd_virtx; 2132 ri->ri_height = dp->rd_virty; 2133 ri->ri_stride = dp->rd_stride; 2134 ri->ri_flg = RI_CENTER; 2135 ri->ri_bits = (void *)dp->rd_fbptr; 2136 2137 /* XXX: 32 bpp only */ 2138 /* this is rgb in "big-endian order..." */ 2139 ri->ri_rnum = 8; 2140 ri->ri_gnum = 8; 2141 ri->ri_bnum = 8; 2142 ri->ri_rpos = 16; 2143 ri->ri_gpos = 8; 2144 ri->ri_bpos = 0; 2145 2146 if (existing) { 2147 ri->ri_flg |= RI_CLEAR; 2148 2149 /* start a modeswitch now */ 2150 radeonfb_modeswitch(dp); 2151 } 2152 2153 /* 2154 * XXX: font selection should be based on properties, with some 2155 * normal/reasonable default. 2156 */ 2157 ri->ri_caps = WSSCREEN_WSCOLORS; 2158 2159 /* initialize and look for an initial font */ 2160 rasops_init(ri, dp->rd_virty/8, dp->rd_virtx/8); 2161 2162 rasops_reconfig(ri, dp->rd_virty / ri->ri_font->fontheight, 2163 dp->rd_virtx / ri->ri_font->fontwidth); 2164 2165 /* enable acceleration */ 2166 ri->ri_ops.copyrows = radeonfb_copyrows; 2167 ri->ri_ops.copycols = radeonfb_copycols; 2168 ri->ri_ops.eraserows = radeonfb_eraserows; 2169 ri->ri_ops.erasecols = radeonfb_erasecols; 2170 ri->ri_ops.allocattr = radeonfb_allocattr; 2171 if (!IS_R300(dp->rd_softc)) { 2172 ri->ri_ops.putchar = radeonfb_putchar; 2173 } 2174 ri->ri_ops.cursor = radeonfb_cursor; 2175 } 2176 2177 void 2178 radeonfb_set_fbloc(struct radeonfb_softc *sc) 2179 { 2180 uint32_t gen, ext, gen2 = 0; 2181 uint32_t agploc, aperbase, apersize, mcfbloc; 2182 2183 gen = GET32(sc, RADEON_CRTC_GEN_CNTL); 2184 ext = GET32(sc, RADEON_CRTC_EXT_CNTL); 2185 agploc = GET32(sc, RADEON_MC_AGP_LOCATION); 2186 aperbase = GET32(sc, RADEON_CONFIG_APER_0_BASE); 2187 apersize = GET32(sc, RADEON_CONFIG_APER_SIZE); 2188 2189 PUT32(sc, RADEON_CRTC_GEN_CNTL, gen | RADEON_CRTC_DISP_REQ_EN_B); 2190 PUT32(sc, RADEON_CRTC_EXT_CNTL, ext | RADEON_CRTC_DISPLAY_DIS); 2191 //PUT32(sc, RADEON_CRTC_GEN_CNTL, gen | RADEON_CRTC_DISPLAY_DIS); 2192 //PUT32(sc, RADEON_CRTC_EXT_CNTL, ext | RADEON_CRTC_DISP_REQ_EN_B); 2193 2194 if (HAS_CRTC2(sc)) { 2195 gen2 = GET32(sc, RADEON_CRTC2_GEN_CNTL); 2196 PUT32(sc, RADEON_CRTC2_GEN_CNTL, 2197 gen2 | RADEON_CRTC2_DISP_REQ_EN_B); 2198 } 2199 2200 delay(100000); 2201 2202 mcfbloc = (aperbase >> 16) | 2203 ((aperbase + (apersize - 1)) & 0xffff0000); 2204 2205 sc->sc_aperbase = (mcfbloc & 0xffff) << 16; 2206 sc->sc_memsz = apersize; 2207 2208 if (((agploc & 0xffff) << 16) != 2209 ((mcfbloc & 0xffff0000U) + 0x10000)) { 2210 agploc = mcfbloc & 0xffff0000U; 2211 agploc |= ((agploc + 0x10000) >> 16); 2212 } 2213 2214 PUT32(sc, RADEON_HOST_PATH_CNTL, 0); 2215 2216 PUT32(sc, RADEON_MC_FB_LOCATION, mcfbloc); 2217 PUT32(sc, RADEON_MC_AGP_LOCATION, agploc); 2218 2219 DPRINTF(("aperbase = %u\n", aperbase)); 2220 PRINTREG(RADEON_MC_FB_LOCATION); 2221 PRINTREG(RADEON_MC_AGP_LOCATION); 2222 2223 PUT32(sc, RADEON_DISPLAY_BASE_ADDR, sc->sc_aperbase); 2224 2225 if (HAS_CRTC2(sc)) 2226 PUT32(sc, RADEON_DISPLAY2_BASE_ADDR, sc->sc_aperbase); 2227 2228 PUT32(sc, RADEON_OV0_BASE_ADDR, sc->sc_aperbase); 2229 2230 #if 0 2231 /* XXX: what is this AGP garbage? :-) */ 2232 PUT32(sc, RADEON_AGP_CNTL, 0x00100000); 2233 #endif 2234 2235 delay(100000); 2236 2237 PUT32(sc, RADEON_CRTC_GEN_CNTL, gen); 2238 PUT32(sc, RADEON_CRTC_EXT_CNTL, ext); 2239 2240 if (HAS_CRTC2(sc)) 2241 PUT32(sc, RADEON_CRTC2_GEN_CNTL, gen2); 2242 } 2243 2244 void 2245 radeonfb_init_misc(struct radeonfb_softc *sc) 2246 { 2247 PUT32(sc, RADEON_BUS_CNTL, 2248 RADEON_BUS_MASTER_DIS | 2249 RADEON_BUS_PREFETCH_MODE_ACT | 2250 RADEON_BUS_PCI_READ_RETRY_EN | 2251 RADEON_BUS_PCI_WRT_RETRY_EN | 2252 (3 << RADEON_BUS_RETRY_WS_SHIFT) | 2253 RADEON_BUS_MSTR_RD_MULT | 2254 RADEON_BUS_MSTR_RD_LINE | 2255 RADEON_BUS_RD_DISCARD_EN | 2256 RADEON_BUS_MSTR_DISCONNECT_EN | 2257 RADEON_BUS_READ_BURST); 2258 2259 PUT32(sc, RADEON_BUS_CNTL1, 0xf0); 2260 /* PUT32(sc, RADEON_SEPROM_CNTL1, 0x09ff0000); */ 2261 PUT32(sc, RADEON_FCP_CNTL, RADEON_FCP0_SRC_GND); 2262 PUT32(sc, RADEON_RBBM_CNTL, 2263 (3 << RADEON_RB_SETTLE_SHIFT) | 2264 (4 << RADEON_ABORTCLKS_HI_SHIFT) | 2265 (4 << RADEON_ABORTCLKS_CP_SHIFT) | 2266 (4 << RADEON_ABORTCLKS_CFIFO_SHIFT)); 2267 2268 /* XXX: figure out what these mean! */ 2269 PUT32(sc, RADEON_AGP_CNTL, 0x00100000); 2270 PUT32(sc, RADEON_HOST_PATH_CNTL, 0); 2271 //PUT32(sc, RADEON_DISP_MISC_CNTL, 0x5bb00400); 2272 2273 PUT32(sc, RADEON_GEN_INT_CNTL, 0); 2274 PUT32(sc, RADEON_GEN_INT_STATUS, GET32(sc, RADEON_GEN_INT_STATUS)); 2275 } 2276 2277 /* 2278 * This loads a linear color map for true color. 2279 */ 2280 void 2281 radeonfb_init_palette(struct radeonfb_softc *sc, int crtc) 2282 { 2283 int i; 2284 uint32_t vclk; 2285 2286 #define DAC_WIDTH ((1 << 10) - 1) 2287 #define CLUT_WIDTH ((1 << 8) - 1) 2288 #define CLUT_COLOR(i) ((i * DAC_WIDTH * 2 / CLUT_WIDTH + 1) / 2) 2289 2290 vclk = GETPLL(sc, RADEON_VCLK_ECP_CNTL); 2291 PUTPLL(sc, RADEON_VCLK_ECP_CNTL, vclk & ~RADEON_PIXCLK_DAC_ALWAYS_ONb); 2292 2293 if (crtc) 2294 SET32(sc, RADEON_DAC_CNTL2, RADEON_DAC2_PALETTE_ACC_CTL); 2295 else 2296 CLR32(sc, RADEON_DAC_CNTL2, RADEON_DAC2_PALETTE_ACC_CTL); 2297 2298 PUT32(sc, RADEON_PALETTE_INDEX, 0); 2299 for (i = 0; i <= CLUT_WIDTH; ++i) { 2300 PUT32(sc, RADEON_PALETTE_30_DATA, 2301 (CLUT_COLOR(i) << 10) | 2302 (CLUT_COLOR(i) << 20) | 2303 (CLUT_COLOR(i))); 2304 } 2305 2306 CLR32(sc, RADEON_DAC_CNTL2, RADEON_DAC2_PALETTE_ACC_CTL); 2307 PRINTREG(RADEON_DAC_CNTL2); 2308 2309 PUTPLL(sc, RADEON_VCLK_ECP_CNTL, vclk); 2310 } 2311 2312 /* 2313 * Bugs in some R300 hardware requires this when accessing CLOCK_CNTL_INDEX. 2314 */ 2315 void 2316 radeonfb_r300cg_workaround(struct radeonfb_softc *sc) 2317 { 2318 uint32_t tmp, save; 2319 2320 save = GET32(sc, RADEON_CLOCK_CNTL_INDEX); 2321 tmp = save & ~(0x3f | RADEON_PLL_WR_EN); 2322 PUT32(sc, RADEON_CLOCK_CNTL_INDEX, tmp); 2323 tmp = GET32(sc, RADEON_CLOCK_CNTL_DATA); 2324 PUT32(sc, RADEON_CLOCK_CNTL_INDEX, save); 2325 } 2326 2327 /* 2328 * Acceleration entry points. 2329 */ 2330 static void 2331 radeonfb_putchar(void *cookie, int row, int col, u_int c, long attr) 2332 { 2333 struct rasops_info *ri = cookie; 2334 struct vcons_screen *scr = ri->ri_hw; 2335 struct radeonfb_display *dp = scr->scr_cookie; 2336 uint32_t x, y, w, h; 2337 uint32_t bg, fg; 2338 uint8_t *data; 2339 2340 if (dp->rd_wsmode != WSDISPLAYIO_MODE_EMUL) 2341 return; 2342 2343 if (!CHAR_IN_FONT(c, ri->ri_font)) 2344 return; 2345 2346 w = ri->ri_font->fontwidth; 2347 h = ri->ri_font->fontheight; 2348 2349 bg = ri->ri_devcmap[(attr >> 16) & 0xf]; 2350 fg = ri->ri_devcmap[(attr >> 24) & 0xf]; 2351 2352 x = ri->ri_xorigin + col * w; 2353 y = ri->ri_yorigin + row * h; 2354 2355 if (c == 0x20) { 2356 radeonfb_rectfill(dp, x, y, w, h, bg); 2357 } else { 2358 data = (uint8_t *)ri->ri_font->data + 2359 (c - ri->ri_font->firstchar) * ri->ri_fontscale; 2360 2361 radeonfb_setup_mono(dp, x, y, w, h, fg, bg); 2362 radeonfb_feed_bytes(dp, ri->ri_fontscale, data); 2363 } 2364 } 2365 2366 static void 2367 radeonfb_eraserows(void *cookie, int row, int nrows, long fillattr) 2368 { 2369 struct rasops_info *ri = cookie; 2370 struct vcons_screen *scr = ri->ri_hw; 2371 struct radeonfb_display *dp = scr->scr_cookie; 2372 uint32_t x, y, w, h, fg, bg, ul; 2373 2374 /* XXX: check for full emulation mode? */ 2375 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 2376 x = ri->ri_xorigin; 2377 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 2378 w = ri->ri_emuwidth; 2379 h = ri->ri_font->fontheight * nrows; 2380 2381 rasops_unpack_attr(fillattr, &fg, &bg, &ul); 2382 radeonfb_rectfill(dp, x, y, w, h, ri->ri_devcmap[bg & 0xf]); 2383 } 2384 } 2385 2386 static void 2387 radeonfb_copyrows(void *cookie, int srcrow, int dstrow, int nrows) 2388 { 2389 struct rasops_info *ri = cookie; 2390 struct vcons_screen *scr = ri->ri_hw; 2391 struct radeonfb_display *dp = scr->scr_cookie; 2392 uint32_t x, ys, yd, w, h; 2393 2394 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 2395 x = ri->ri_xorigin; 2396 ys = ri->ri_yorigin + ri->ri_font->fontheight * srcrow; 2397 yd = ri->ri_yorigin + ri->ri_font->fontheight * dstrow; 2398 w = ri->ri_emuwidth; 2399 h = ri->ri_font->fontheight * nrows; 2400 radeonfb_bitblt(dp, x, ys, x, yd, w, h, 2401 RADEON_ROP3_S, 0xffffffff); 2402 } 2403 } 2404 2405 static void 2406 radeonfb_copycols(void *cookie, int row, int srccol, int dstcol, int ncols) 2407 { 2408 struct rasops_info *ri = cookie; 2409 struct vcons_screen *scr = ri->ri_hw; 2410 struct radeonfb_display *dp = scr->scr_cookie; 2411 uint32_t xs, xd, y, w, h; 2412 2413 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 2414 xs = ri->ri_xorigin + ri->ri_font->fontwidth * srccol; 2415 xd = ri->ri_xorigin + ri->ri_font->fontwidth * dstcol; 2416 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 2417 w = ri->ri_font->fontwidth * ncols; 2418 h = ri->ri_font->fontheight; 2419 radeonfb_bitblt(dp, xs, y, xd, y, w, h, 2420 RADEON_ROP3_S, 0xffffffff); 2421 } 2422 } 2423 2424 static void 2425 radeonfb_erasecols(void *cookie, int row, int startcol, int ncols, 2426 long fillattr) 2427 { 2428 struct rasops_info *ri = cookie; 2429 struct vcons_screen *scr = ri->ri_hw; 2430 struct radeonfb_display *dp = scr->scr_cookie; 2431 uint32_t x, y, w, h, fg, bg, ul; 2432 2433 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 2434 x = ri->ri_xorigin + ri->ri_font->fontwidth * startcol; 2435 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 2436 w = ri->ri_font->fontwidth * ncols; 2437 h = ri->ri_font->fontheight; 2438 2439 rasops_unpack_attr(fillattr, &fg, &bg, &ul); 2440 radeonfb_rectfill(dp, x, y, w, h, ri->ri_devcmap[bg & 0xf]); 2441 } 2442 } 2443 2444 static void 2445 radeonfb_cursor(void *cookie, int on, int row, int col) 2446 { 2447 struct rasops_info *ri = cookie; 2448 struct vcons_screen *scr = ri->ri_hw; 2449 struct radeonfb_display *dp = scr->scr_cookie; 2450 int x, y, wi, he; 2451 2452 wi = ri->ri_font->fontwidth; 2453 he = ri->ri_font->fontheight; 2454 2455 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 2456 x = ri->ri_ccol * wi + ri->ri_xorigin; 2457 y = ri->ri_crow * he + ri->ri_yorigin; 2458 /* first turn off the old cursor */ 2459 if (ri->ri_flg & RI_CURSOR) { 2460 radeonfb_bitblt(dp, x, y, x, y, wi, he, 2461 RADEON_ROP3_Dn, 0xffffffff); 2462 ri->ri_flg &= ~RI_CURSOR; 2463 } 2464 ri->ri_crow = row; 2465 ri->ri_ccol = col; 2466 /* then (possibly) turn on the new one */ 2467 if (on) { 2468 x = ri->ri_ccol * wi + ri->ri_xorigin; 2469 y = ri->ri_crow * he + ri->ri_yorigin; 2470 radeonfb_bitblt(dp, x, y, x, y, wi, he, 2471 RADEON_ROP3_Dn, 0xffffffff); 2472 ri->ri_flg |= RI_CURSOR; 2473 } 2474 } else { 2475 scr->scr_ri.ri_crow = row; 2476 scr->scr_ri.ri_ccol = col; 2477 scr->scr_ri.ri_flg &= ~RI_CURSOR; 2478 } 2479 } 2480 2481 static int 2482 radeonfb_allocattr(void *cookie, int fg, int bg, int flags, long *attrp) 2483 { 2484 if ((fg == 0) && (bg == 0)) { 2485 fg = WS_DEFAULT_FG; 2486 bg = WS_DEFAULT_BG; 2487 } 2488 *attrp = ((fg & 0xf) << 24) | ((bg & 0xf) << 16) | (flags & 0xff) << 8; 2489 return 0; 2490 } 2491 2492 /* 2493 * Underlying acceleration support. 2494 */ 2495 static void 2496 radeonfb_setup_mono(struct radeonfb_display *dp, int xd, int yd, int width, 2497 int height, uint32_t fg, uint32_t bg) 2498 { 2499 struct radeonfb_softc *sc = dp->rd_softc; 2500 uint32_t gmc; 2501 uint32_t padded_width = (width+7) & 0xfff8; 2502 uint32_t topleft, bottomright; 2503 2504 gmc = dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT; 2505 2506 if (width != padded_width) { 2507 2508 radeonfb_wait_fifo(sc, 2); 2509 topleft = ((yd << 16) & 0x1fff0000) | (xd & 0x1fff); 2510 bottomright = (((yd + height) << 16) & 0x1fff0000) | 2511 ((xd + width) & 0x1fff); 2512 PUT32(sc, RADEON_SC_TOP_LEFT, topleft); 2513 PUT32(sc, RADEON_SC_BOTTOM_RIGHT, bottomright); 2514 } 2515 2516 radeonfb_wait_fifo(sc, 5); 2517 2518 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 2519 RADEON_GMC_BRUSH_NONE | 2520 RADEON_GMC_SRC_DATATYPE_MONO_FG_BG | 2521 //RADEON_GMC_BYTE_LSB_TO_MSB | 2522 RADEON_GMC_DST_CLIPPING | 2523 RADEON_ROP3_S | 2524 RADEON_DP_SRC_SOURCE_HOST_DATA | 2525 RADEON_GMC_CLR_CMP_CNTL_DIS | 2526 RADEON_GMC_WR_MSK_DIS | 2527 gmc); 2528 2529 PUT32(sc, RADEON_DP_SRC_FRGD_CLR, fg); 2530 PUT32(sc, RADEON_DP_SRC_BKGD_CLR, bg); 2531 2532 PUT32(sc, RADEON_DST_X_Y, (xd << 16) | yd); 2533 PUT32(sc, RADEON_DST_WIDTH_HEIGHT, (padded_width << 16) | height); 2534 2535 } 2536 2537 static void 2538 radeonfb_feed_bytes(struct radeonfb_display *dp, int count, uint8_t *data) 2539 { 2540 struct radeonfb_softc *sc = dp->rd_softc; 2541 int i; 2542 uint32_t latch = 0; 2543 int shift = 0; 2544 2545 for (i = 0; i < count; i++) { 2546 latch |= (data[i] << shift); 2547 if (shift == 24) { 2548 radeonfb_wait_fifo(sc, 1); 2549 PUT32(sc, RADEON_HOST_DATA0, latch); 2550 latch = 0; 2551 shift = 0; 2552 } else 2553 shift += 8; 2554 } 2555 if (shift != 0) { 2556 radeonfb_wait_fifo(sc, 1); 2557 PUT32(sc, RADEON_HOST_DATA0, latch); 2558 } 2559 radeonfb_unclip(sc); 2560 } 2561 2562 static void 2563 radeonfb_rectfill(struct radeonfb_display *dp, int dstx, int dsty, 2564 int width, int height, uint32_t color) 2565 { 2566 struct radeonfb_softc *sc = dp->rd_softc; 2567 uint32_t gmc; 2568 2569 gmc = dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT; 2570 2571 radeonfb_wait_fifo(sc, 6); 2572 2573 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 2574 RADEON_GMC_BRUSH_SOLID_COLOR | 2575 RADEON_GMC_SRC_DATATYPE_COLOR | 2576 RADEON_GMC_CLR_CMP_CNTL_DIS | 2577 RADEON_ROP3_P | gmc); 2578 2579 PUT32(sc, RADEON_DP_BRUSH_FRGD_CLR, color); 2580 PUT32(sc, RADEON_DP_WRITE_MASK, 0xffffffff); 2581 PUT32(sc, RADEON_DP_CNTL, 2582 RADEON_DST_X_LEFT_TO_RIGHT | 2583 RADEON_DST_Y_TOP_TO_BOTTOM); 2584 PUT32(sc, RADEON_DST_Y_X, (dsty << 16) | dstx); 2585 PUT32(sc, RADEON_DST_WIDTH_HEIGHT, (width << 16) | (height)); 2586 2587 /* 2588 * XXX: we don't wait for the fifo to empty -- that would slow 2589 * things down! The linux radeonfb driver waits, but xfree doesn't 2590 */ 2591 /* XXX: for now we do, to make it safe for direct drawing */ 2592 radeonfb_engine_idle(sc); 2593 } 2594 2595 static void 2596 radeonfb_bitblt(struct radeonfb_display *dp, int srcx, int srcy, 2597 int dstx, int dsty, int width, int height, int rop, uint32_t mask) 2598 { 2599 struct radeonfb_softc *sc = dp->rd_softc; 2600 uint32_t gmc; 2601 uint32_t dir; 2602 2603 if (dsty < srcy) { 2604 dir = RADEON_DST_Y_TOP_TO_BOTTOM; 2605 } else { 2606 srcy += height - 1; 2607 dsty += height - 1; 2608 dir = 0; 2609 } 2610 if (dstx < srcx) { 2611 dir |= RADEON_DST_X_LEFT_TO_RIGHT; 2612 } else { 2613 srcx += width - 1; 2614 dstx += width - 1; 2615 } 2616 2617 gmc = dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT; 2618 2619 radeonfb_wait_fifo(sc, 6); 2620 2621 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 2622 //RADEON_GMC_SRC_CLIPPING | 2623 RADEON_GMC_BRUSH_SOLID_COLOR | 2624 RADEON_GMC_SRC_DATATYPE_COLOR | 2625 RADEON_GMC_CLR_CMP_CNTL_DIS | 2626 RADEON_DP_SRC_SOURCE_MEMORY | 2627 rop | gmc); 2628 2629 PUT32(sc, RADEON_DP_WRITE_MASK, mask); 2630 PUT32(sc, RADEON_DP_CNTL, dir); 2631 PUT32(sc, RADEON_SRC_Y_X, (srcy << 16) | srcx); 2632 PUT32(sc, RADEON_DST_Y_X, (dsty << 16) | dstx); 2633 PUT32(sc, RADEON_DST_WIDTH_HEIGHT, (width << 16) | (height)); 2634 2635 /* 2636 * XXX: we don't wait for the fifo to empty -- that would slow 2637 * things down! The linux radeonfb driver waits, but xfree doesn't 2638 */ 2639 /* XXX: for now we do, to make it safe for direct drawing */ 2640 radeonfb_engine_idle(sc); 2641 } 2642 2643 static void 2644 radeonfb_engine_idle(struct radeonfb_softc *sc) 2645 { 2646 int i; 2647 2648 radeonfb_wait_fifo(sc, 64); 2649 for (i = RADEON_TIMEOUT; i; i--) { 2650 if ((GET32(sc, RADEON_RBBM_STATUS) & 2651 RADEON_RBBM_ACTIVE) == 0) { 2652 radeonfb_engine_flush(sc); 2653 break; 2654 } 2655 } 2656 } 2657 2658 static void 2659 radeonfb_wait_fifo(struct radeonfb_softc *sc, int n) 2660 { 2661 int i; 2662 2663 for (i = RADEON_TIMEOUT; i; i--) { 2664 if ((GET32(sc, RADEON_RBBM_STATUS) & 2665 RADEON_RBBM_FIFOCNT_MASK) >= n) 2666 return; 2667 } 2668 #ifdef DIAGNOSTIC 2669 if (!i) 2670 printf("%s: timed out waiting for fifo (%x)\n", 2671 XNAME(sc), GET32(sc, RADEON_RBBM_STATUS)); 2672 #endif 2673 } 2674 2675 static void 2676 radeonfb_engine_flush(struct radeonfb_softc *sc) 2677 { 2678 int i; 2679 SET32(sc, RADEON_RB2D_DSTCACHE_CTLSTAT, RADEON_RB2D_DC_FLUSH_ALL); 2680 for (i = RADEON_TIMEOUT; i; i--) { 2681 if ((GET32(sc, RADEON_RB2D_DSTCACHE_CTLSTAT) & 2682 RADEON_RB2D_DC_BUSY) == 0) 2683 break; 2684 } 2685 #ifdef DIAGNOSTIC 2686 if (!i) 2687 printf("%s: engine flush timed out!\n", XNAME(sc)); 2688 #endif 2689 } 2690 2691 static inline void 2692 radeonfb_unclip(struct radeonfb_softc *sc) 2693 { 2694 2695 radeonfb_wait_fifo(sc, 2); 2696 PUT32(sc, RADEON_SC_TOP_LEFT, 0); 2697 PUT32(sc, RADEON_SC_BOTTOM_RIGHT, 0x1fff1fff); 2698 } 2699 2700 static void 2701 radeonfb_engine_init(struct radeonfb_display *dp) 2702 { 2703 struct radeonfb_softc *sc = dp->rd_softc; 2704 uint32_t pitch; 2705 2706 /* no 3D */ 2707 PUT32(sc, RADEON_RB3D_CNTL, 0); 2708 2709 radeonfb_engine_reset(sc); 2710 pitch = ((dp->rd_virtx * (dp->rd_bpp / 8) + 0x3f)) >> 6; 2711 //pitch = ((sc->sc_maxx * (sc->sc_maxbpp / 8) + 0x3f)) >> 6; 2712 2713 radeonfb_wait_fifo(sc, 1); 2714 if (!IS_R300(sc)) 2715 PUT32(sc, RADEON_RB2D_DSTCACHE_MODE, 0); 2716 2717 radeonfb_wait_fifo(sc, 3); 2718 PUT32(sc, RADEON_DEFAULT_PITCH_OFFSET, 2719 (pitch << 22) | (sc->sc_aperbase >> 10)); 2720 2721 2722 PUT32(sc, RADEON_DST_PITCH_OFFSET, 2723 (pitch << 22) | (sc->sc_aperbase >> 10)); 2724 PUT32(sc, RADEON_SRC_PITCH_OFFSET, 2725 (pitch << 22) | (sc->sc_aperbase >> 10)); 2726 2727 radeonfb_wait_fifo(sc, 1); 2728 #if _BYTE_ORDER == _BIG_ENDIAN 2729 SET32(sc, RADEON_DP_DATATYPE, RADEON_HOST_BIG_ENDIAN_EN); 2730 #else 2731 CLR32(sc, RADEON_DP_DATATYPE, RADEON_HOST_BIG_ENDIAN_EN); 2732 #endif 2733 2734 /* default scissors -- no clipping */ 2735 radeonfb_wait_fifo(sc, 1); 2736 PUT32(sc, RADEON_DEFAULT_SC_BOTTOM_RIGHT, 2737 RADEON_DEFAULT_SC_RIGHT_MAX | RADEON_DEFAULT_SC_BOTTOM_MAX); 2738 2739 radeonfb_wait_fifo(sc, 1); 2740 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 2741 (dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT) | 2742 RADEON_GMC_CLR_CMP_CNTL_DIS | 2743 RADEON_GMC_BRUSH_SOLID_COLOR | 2744 RADEON_GMC_SRC_DATATYPE_COLOR); 2745 2746 radeonfb_wait_fifo(sc, 7); 2747 PUT32(sc, RADEON_DST_LINE_START, 0); 2748 PUT32(sc, RADEON_DST_LINE_END, 0); 2749 PUT32(sc, RADEON_DP_BRUSH_FRGD_CLR, 0xffffffff); 2750 PUT32(sc, RADEON_DP_BRUSH_BKGD_CLR, 0); 2751 PUT32(sc, RADEON_DP_SRC_FRGD_CLR, 0xffffffff); 2752 PUT32(sc, RADEON_DP_SRC_BKGD_CLR, 0); 2753 PUT32(sc, RADEON_DP_WRITE_MASK, 0xffffffff); 2754 2755 radeonfb_engine_idle(sc); 2756 } 2757 2758 static void 2759 radeonfb_engine_reset(struct radeonfb_softc *sc) 2760 { 2761 uint32_t hpc, rbbm, mclkcntl, clkindex; 2762 2763 radeonfb_engine_flush(sc); 2764 2765 clkindex = GET32(sc, RADEON_CLOCK_CNTL_INDEX); 2766 if (HAS_R300CG(sc)) 2767 radeonfb_r300cg_workaround(sc); 2768 mclkcntl = GETPLL(sc, RADEON_MCLK_CNTL); 2769 2770 /* 2771 * According to comments in XFree code, resetting the HDP via 2772 * the RBBM_SOFT_RESET can cause bad behavior on some systems. 2773 * So we use HOST_PATH_CNTL instead. 2774 */ 2775 2776 hpc = GET32(sc, RADEON_HOST_PATH_CNTL); 2777 rbbm = GET32(sc, RADEON_RBBM_SOFT_RESET); 2778 if (IS_R300(sc)) { 2779 PUT32(sc, RADEON_RBBM_SOFT_RESET, rbbm | 2780 RADEON_SOFT_RESET_CP | 2781 RADEON_SOFT_RESET_HI | 2782 RADEON_SOFT_RESET_E2); 2783 GET32(sc, RADEON_RBBM_SOFT_RESET); 2784 PUT32(sc, RADEON_RBBM_SOFT_RESET, 0); 2785 /* 2786 * XXX: this bit is not defined in any ATI docs I have, 2787 * nor in the XFree code, but XFree does it. Why? 2788 */ 2789 SET32(sc, RADEON_RB2D_DSTCACHE_MODE, (1<<17)); 2790 } else { 2791 PUT32(sc, RADEON_RBBM_SOFT_RESET, rbbm | 2792 RADEON_SOFT_RESET_CP | 2793 RADEON_SOFT_RESET_SE | 2794 RADEON_SOFT_RESET_RE | 2795 RADEON_SOFT_RESET_PP | 2796 RADEON_SOFT_RESET_E2 | 2797 RADEON_SOFT_RESET_RB); 2798 GET32(sc, RADEON_RBBM_SOFT_RESET); 2799 PUT32(sc, RADEON_RBBM_SOFT_RESET, rbbm & 2800 ~(RADEON_SOFT_RESET_CP | 2801 RADEON_SOFT_RESET_SE | 2802 RADEON_SOFT_RESET_RE | 2803 RADEON_SOFT_RESET_PP | 2804 RADEON_SOFT_RESET_E2 | 2805 RADEON_SOFT_RESET_RB)); 2806 GET32(sc, RADEON_RBBM_SOFT_RESET); 2807 } 2808 2809 PUT32(sc, RADEON_HOST_PATH_CNTL, hpc | RADEON_HDP_SOFT_RESET); 2810 GET32(sc, RADEON_HOST_PATH_CNTL); 2811 PUT32(sc, RADEON_HOST_PATH_CNTL, hpc); 2812 2813 if (IS_R300(sc)) 2814 PUT32(sc, RADEON_RBBM_SOFT_RESET, rbbm); 2815 2816 PUT32(sc, RADEON_CLOCK_CNTL_INDEX, clkindex); 2817 PUTPLL(sc, RADEON_MCLK_CNTL, mclkcntl); 2818 2819 if (HAS_R300CG(sc)) 2820 radeonfb_r300cg_workaround(sc); 2821 } 2822 2823 static int 2824 radeonfb_set_curpos(struct radeonfb_display *dp, struct wsdisplay_curpos *pos) 2825 { 2826 int x, y; 2827 2828 x = pos->x; 2829 y = pos->y; 2830 2831 /* 2832 * This doesn't let a cursor move off the screen. I'm not 2833 * sure if this will have negative effects for e.g. Xinerama. 2834 * I'd guess Xinerama handles it by changing the cursor shape, 2835 * but that needs verification. 2836 */ 2837 if (x >= dp->rd_virtx) 2838 x = dp->rd_virtx - 1; 2839 if (x < 0) 2840 x = 0; 2841 if (y >= dp->rd_virty) 2842 y = dp->rd_virty - 1; 2843 if (y < 0) 2844 y = 0; 2845 2846 dp->rd_cursor.rc_pos.x = x; 2847 dp->rd_cursor.rc_pos.y = y; 2848 2849 radeonfb_cursor_position(dp); 2850 return 0; 2851 } 2852 2853 static int 2854 radeonfb_set_cursor(struct radeonfb_display *dp, struct wsdisplay_cursor *wc) 2855 { 2856 unsigned flags; 2857 2858 uint8_t r[2], g[2], b[2]; 2859 unsigned index, count; 2860 int i, err; 2861 int pitch, size; 2862 struct radeonfb_cursor nc; 2863 2864 flags = wc->which; 2865 2866 /* copy old values */ 2867 nc = dp->rd_cursor; 2868 2869 if (flags & WSDISPLAY_CURSOR_DOCMAP) { 2870 index = wc->cmap.index; 2871 count = wc->cmap.count; 2872 2873 if (index >= 2 || (index + count) > 2) 2874 return EINVAL; 2875 2876 err = copyin(wc->cmap.red, &r[index], count); 2877 if (err) 2878 return err; 2879 err = copyin(wc->cmap.green, &g[index], count); 2880 if (err) 2881 return err; 2882 err = copyin(wc->cmap.blue, &b[index], count); 2883 if (err) 2884 return err; 2885 2886 for (i = index; i < index + count; i++) { 2887 nc.rc_cmap[i] = 2888 (r[i] << 16) + (g[i] << 8) + (b[i] << 0); 2889 } 2890 } 2891 2892 if (flags & WSDISPLAY_CURSOR_DOSHAPE) { 2893 if ((wc->size.x > RADEON_CURSORMAXX) || 2894 (wc->size.y > RADEON_CURSORMAXY)) 2895 return EINVAL; 2896 2897 /* figure bytes per line */ 2898 pitch = (wc->size.x + 7) / 8; 2899 size = pitch * wc->size.y; 2900 2901 /* clear the old cursor and mask */ 2902 memset(nc.rc_image, 0, 512); 2903 memset(nc.rc_mask, 0, 512); 2904 2905 nc.rc_size = wc->size; 2906 2907 if ((err = copyin(wc->image, nc.rc_image, size)) != 0) 2908 return err; 2909 2910 if ((err = copyin(wc->mask, nc.rc_mask, size)) != 0) 2911 return err; 2912 } 2913 2914 if (flags & WSDISPLAY_CURSOR_DOHOT) { 2915 nc.rc_hot = wc->hot; 2916 if (nc.rc_hot.x >= nc.rc_size.x) 2917 nc.rc_hot.x = nc.rc_size.x - 1; 2918 if (nc.rc_hot.y >= nc.rc_size.y) 2919 nc.rc_hot.y = nc.rc_size.y - 1; 2920 } 2921 2922 if (flags & WSDISPLAY_CURSOR_DOPOS) { 2923 nc.rc_pos = wc->pos; 2924 if (nc.rc_pos.x >= dp->rd_virtx) 2925 nc.rc_pos.x = dp->rd_virtx - 1; 2926 #if 0 2927 if (nc.rc_pos.x < 0) 2928 nc.rc_pos.x = 0; 2929 #endif 2930 if (nc.rc_pos.y >= dp->rd_virty) 2931 nc.rc_pos.y = dp->rd_virty - 1; 2932 #if 0 2933 if (nc.rc_pos.y < 0) 2934 nc.rc_pos.y = 0; 2935 #endif 2936 } 2937 if (flags & WSDISPLAY_CURSOR_DOCUR) { 2938 nc.rc_visible = wc->enable; 2939 } 2940 2941 dp->rd_cursor = nc; 2942 radeonfb_cursor_update(dp, wc->which); 2943 2944 return 0; 2945 } 2946 2947 /* 2948 * Change the cursor shape. Call this with the cursor locked to avoid 2949 * flickering/tearing. 2950 */ 2951 static void 2952 radeonfb_cursor_shape(struct radeonfb_display *dp) 2953 { 2954 uint8_t and[512], xor[512]; 2955 int i, j, src, dst, pitch; 2956 const uint8_t *msk = dp->rd_cursor.rc_mask; 2957 const uint8_t *img = dp->rd_cursor.rc_image; 2958 2959 /* 2960 * Radeon cursor data interleaves one line of AND data followed 2961 * by a line of XOR data. (Each line corresponds to a whole hardware 2962 * pitch - i.e. 64 pixels or 8 bytes.) 2963 * 2964 * The cursor is displayed using the following table: 2965 * 2966 * AND XOR Result 2967 * ---------------------- 2968 * 0 0 Cursor color 0 2969 * 0 1 Cursor color 1 2970 * 1 0 Transparent 2971 * 1 1 Complement of background 2972 * 2973 * Our masks are therefore different from what we were passed. 2974 * Passed in, I'm assuming the data represents either color 0 or 1, 2975 * and a mask, so the passed in table looks like: 2976 * 2977 * IMG Mask Result 2978 * ----------------------- 2979 * 0 0 Transparent 2980 * 0 1 Cursor color 0 2981 * 1 0 Transparent 2982 * 1 1 Cursor color 1 2983 * 2984 * IF mask bit == 1, AND = 0, XOR = color. 2985 * IF mask bit == 0, AND = 1, XOR = 0. 2986 * 2987 * hence: AND = ~(mask); XOR = color & ~(mask); 2988 */ 2989 2990 pitch = ((dp->rd_cursor.rc_size.x + 7) / 8); 2991 2992 /* start by assuming all bits are transparent */ 2993 memset(and, 0xff, 512); 2994 memset(xor, 0x00, 512); 2995 2996 src = 0; 2997 dst = 0; 2998 for (i = 0; i < 64; i++) { 2999 for (j = 0; j < 64; j += 8) { 3000 if ((i < dp->rd_cursor.rc_size.y) && 3001 (j < dp->rd_cursor.rc_size.x)) { 3002 3003 /* take care to leave odd bits alone */ 3004 and[dst] &= ~(msk[src]); 3005 xor[dst] = img[src] & msk[src]; 3006 src++; 3007 } 3008 dst++; 3009 } 3010 } 3011 3012 /* copy the image into place */ 3013 for (i = 0; i < 64; i++) { 3014 memcpy((uint8_t *)dp->rd_curptr + (i * 16), 3015 &and[i * 8], 8); 3016 memcpy((uint8_t *)dp->rd_curptr + (i * 16) + 8, 3017 &xor[i * 8], 8); 3018 } 3019 } 3020 3021 static void 3022 radeonfb_cursor_position(struct radeonfb_display *dp) 3023 { 3024 struct radeonfb_softc *sc = dp->rd_softc; 3025 uint32_t offset, hvoff, hvpos; /* registers */ 3026 uint32_t coff; /* cursor offset */ 3027 int i, x, y, xoff, yoff, crtcoff; 3028 3029 /* 3030 * XXX: this also needs to handle pan/scan 3031 */ 3032 for (i = 0; i < dp->rd_ncrtcs; i++) { 3033 3034 struct radeonfb_crtc *rcp = &dp->rd_crtcs[i]; 3035 3036 if (rcp->rc_number) { 3037 offset = RADEON_CUR2_OFFSET; 3038 hvoff = RADEON_CUR2_HORZ_VERT_OFF; 3039 hvpos = RADEON_CUR2_HORZ_VERT_POSN; 3040 crtcoff = RADEON_CRTC2_OFFSET; 3041 } else { 3042 offset = RADEON_CUR_OFFSET; 3043 hvoff = RADEON_CUR_HORZ_VERT_OFF; 3044 hvpos = RADEON_CUR_HORZ_VERT_POSN; 3045 crtcoff = RADEON_CRTC_OFFSET; 3046 } 3047 3048 x = dp->rd_cursor.rc_pos.x; 3049 y = dp->rd_cursor.rc_pos.y; 3050 3051 while (y < rcp->rc_yoffset) { 3052 rcp->rc_yoffset -= RADEON_PANINCREMENT; 3053 } 3054 while (y >= (rcp->rc_yoffset + rcp->rc_videomode.vdisplay)) { 3055 rcp->rc_yoffset += RADEON_PANINCREMENT; 3056 } 3057 while (x < rcp->rc_xoffset) { 3058 rcp->rc_xoffset -= RADEON_PANINCREMENT; 3059 } 3060 while (x >= (rcp->rc_xoffset + rcp->rc_videomode.hdisplay)) { 3061 rcp->rc_xoffset += RADEON_PANINCREMENT; 3062 } 3063 3064 /* adjust for the cursor's hotspot */ 3065 x -= dp->rd_cursor.rc_hot.x; 3066 y -= dp->rd_cursor.rc_hot.y; 3067 xoff = yoff = 0; 3068 3069 if (x >= dp->rd_virtx) 3070 x = dp->rd_virtx - 1; 3071 if (y >= dp->rd_virty) 3072 y = dp->rd_virty - 1; 3073 3074 /* now adjust cursor so it is relative to viewport */ 3075 x -= rcp->rc_xoffset; 3076 y -= rcp->rc_yoffset; 3077 3078 /* 3079 * no need to check for fall off, because we should 3080 * never move off the screen entirely! 3081 */ 3082 coff = 0; 3083 if (x < 0) { 3084 xoff = -x; 3085 x = 0; 3086 } 3087 if (y < 0) { 3088 yoff = -y; 3089 y = 0; 3090 coff = (yoff * 2) * 8; 3091 } 3092 3093 /* pan the display */ 3094 PUT32(sc, crtcoff, (rcp->rc_yoffset * dp->rd_stride) + 3095 rcp->rc_xoffset); 3096 3097 PUT32(sc, offset, (dp->rd_curoff + coff) | RADEON_CUR_LOCK); 3098 PUT32(sc, hvoff, (xoff << 16) | (yoff) | RADEON_CUR_LOCK); 3099 /* NB: this unlocks the cursor */ 3100 PUT32(sc, hvpos, (x << 16) | y); 3101 } 3102 } 3103 3104 static void 3105 radeonfb_cursor_visible(struct radeonfb_display *dp) 3106 { 3107 int i; 3108 uint32_t gencntl, bit; 3109 3110 for (i = 0; i < dp->rd_ncrtcs; i++) { 3111 if (dp->rd_crtcs[i].rc_number) { 3112 gencntl = RADEON_CRTC2_GEN_CNTL; 3113 bit = RADEON_CRTC2_CUR_EN; 3114 } else { 3115 gencntl = RADEON_CRTC_GEN_CNTL; 3116 bit = RADEON_CRTC_CUR_EN; 3117 } 3118 3119 if (dp->rd_cursor.rc_visible) 3120 SET32(dp->rd_softc, gencntl, bit); 3121 else 3122 CLR32(dp->rd_softc, gencntl, bit); 3123 } 3124 } 3125 3126 static void 3127 radeonfb_cursor_cmap(struct radeonfb_display *dp) 3128 { 3129 int i; 3130 uint32_t c0reg, c1reg; 3131 struct radeonfb_softc *sc = dp->rd_softc; 3132 3133 for (i = 0; i < dp->rd_ncrtcs; i++) { 3134 if (dp->rd_crtcs[i].rc_number) { 3135 c0reg = RADEON_CUR2_CLR0; 3136 c1reg = RADEON_CUR2_CLR1; 3137 } else { 3138 c0reg = RADEON_CUR_CLR0; 3139 c1reg = RADEON_CUR_CLR1; 3140 } 3141 3142 PUT32(sc, c0reg, dp->rd_cursor.rc_cmap[0]); 3143 PUT32(sc, c1reg, dp->rd_cursor.rc_cmap[1]); 3144 } 3145 } 3146 3147 static void 3148 radeonfb_cursor_update(struct radeonfb_display *dp, unsigned which) 3149 { 3150 struct radeonfb_softc *sc; 3151 int i; 3152 3153 sc = dp->rd_softc; 3154 for (i = 0; i < dp->rd_ncrtcs; i++) { 3155 if (dp->rd_crtcs[i].rc_number) { 3156 SET32(sc, RADEON_CUR2_OFFSET, RADEON_CUR_LOCK); 3157 } else { 3158 SET32(sc, RADEON_CUR_OFFSET,RADEON_CUR_LOCK); 3159 } 3160 } 3161 3162 if (which & WSDISPLAY_CURSOR_DOCMAP) 3163 radeonfb_cursor_cmap(dp); 3164 3165 if (which & WSDISPLAY_CURSOR_DOSHAPE) 3166 radeonfb_cursor_shape(dp); 3167 3168 if (which & WSDISPLAY_CURSOR_DOCUR) 3169 radeonfb_cursor_visible(dp); 3170 3171 /* this one is unconditional, because it updates other stuff */ 3172 radeonfb_cursor_position(dp); 3173 } 3174 3175 static struct videomode * 3176 radeonfb_best_refresh(struct videomode *m1, struct videomode *m2) 3177 { 3178 int r1, r2; 3179 3180 /* otherwise pick the higher refresh rate */ 3181 r1 = DIVIDE(DIVIDE(m1->dot_clock, m1->htotal), m1->vtotal); 3182 r2 = DIVIDE(DIVIDE(m2->dot_clock, m2->htotal), m2->vtotal); 3183 3184 return (r1 < r2 ? m2 : m1); 3185 } 3186 3187 static const struct videomode * 3188 radeonfb_port_mode(struct radeonfb_softc *sc, struct radeonfb_port *rp, 3189 int x, int y) 3190 { 3191 struct edid_info *ep = &rp->rp_edid; 3192 struct videomode *vmp = NULL; 3193 int i; 3194 3195 if (!rp->rp_edid_valid) { 3196 /* fallback to safe mode */ 3197 return radeonfb_modelookup(sc->sc_defaultmode); 3198 } 3199 3200 /* always choose the preferred mode first! */ 3201 if (ep->edid_preferred_mode) { 3202 3203 /* XXX: add auto-stretching support for native mode */ 3204 3205 /* this may want panning to occur, btw */ 3206 if ((ep->edid_preferred_mode->hdisplay <= x) && 3207 (ep->edid_preferred_mode->vdisplay <= y)) 3208 return ep->edid_preferred_mode; 3209 } 3210 3211 for (i = 0; i < ep->edid_nmodes; i++) { 3212 /* 3213 * We elect to pick a resolution that is too large for 3214 * the monitor than one that is too small. This means 3215 * that we will prefer to pan rather than to try to 3216 * center a smaller display on a larger screen. In 3217 * practice, this shouldn't matter because if a 3218 * monitor can support a larger resolution, it can 3219 * probably also support the smaller. A specific 3220 * exception is fixed format panels, but hopefully 3221 * they are properly dealt with by the "autostretch" 3222 * logic above. 3223 */ 3224 if ((ep->edid_modes[i].hdisplay > x) || 3225 (ep->edid_modes[i].vdisplay > y)) { 3226 continue; 3227 } 3228 3229 /* 3230 * at this point, the display mode is no larger than 3231 * what we've requested. 3232 */ 3233 if (vmp == NULL) 3234 vmp = &ep->edid_modes[i]; 3235 3236 /* eliminate smaller modes */ 3237 if ((vmp->hdisplay >= ep->edid_modes[i].hdisplay) || 3238 (vmp->vdisplay >= ep->edid_modes[i].vdisplay)) 3239 continue; 3240 3241 if ((vmp->hdisplay < ep->edid_modes[i].hdisplay) || 3242 (vmp->vdisplay < ep->edid_modes[i].vdisplay)) { 3243 vmp = &ep->edid_modes[i]; 3244 continue; 3245 } 3246 3247 KASSERT(vmp->hdisplay == ep->edid_modes[i].hdisplay); 3248 KASSERT(vmp->vdisplay == ep->edid_modes[i].vdisplay); 3249 3250 vmp = radeonfb_best_refresh(vmp, &ep->edid_modes[i]); 3251 } 3252 3253 return (vmp ? vmp : radeonfb_modelookup(sc->sc_defaultmode)); 3254 } 3255 3256 static int 3257 radeonfb_hasres(struct videomode *list, int nlist, int x, int y) 3258 { 3259 int i; 3260 3261 for (i = 0; i < nlist; i++) { 3262 if ((x == list[i].hdisplay) && 3263 (y == list[i].vdisplay)) { 3264 return 1; 3265 } 3266 } 3267 return 0; 3268 } 3269 3270 static void 3271 radeonfb_pickres(struct radeonfb_display *dp, uint16_t *x, uint16_t *y, 3272 int pan) 3273 { 3274 struct radeonfb_port *rp; 3275 struct edid_info *ep; 3276 int i, j; 3277 3278 *x = 0; 3279 *y = 0; 3280 3281 if (pan) { 3282 for (i = 0; i < dp->rd_ncrtcs; i++) { 3283 rp = dp->rd_crtcs[i].rc_port; 3284 ep = &rp->rp_edid; 3285 if (!rp->rp_edid_valid) { 3286 /* monitor not present */ 3287 continue; 3288 } 3289 3290 /* 3291 * For now we are ignoring "conflict" that 3292 * could occur when mixing some modes like 3293 * 1280x1024 and 1400x800. It isn't clear 3294 * which is better, so the first one wins. 3295 */ 3296 for (j = 0; j < ep->edid_nmodes; j++) { 3297 /* 3298 * ignore resolutions that are too big for 3299 * the radeon 3300 */ 3301 if (ep->edid_modes[j].hdisplay > 3302 dp->rd_softc->sc_maxx) 3303 continue; 3304 if (ep->edid_modes[j].vdisplay > 3305 dp->rd_softc->sc_maxy) 3306 continue; 3307 3308 /* 3309 * pick largest resolution, the 3310 * smaller monitor will pan 3311 */ 3312 if ((ep->edid_modes[j].hdisplay >= *x) && 3313 (ep->edid_modes[j].vdisplay >= *y)) { 3314 *x = ep->edid_modes[j].hdisplay; 3315 *y = ep->edid_modes[j].vdisplay; 3316 } 3317 } 3318 } 3319 3320 } else { 3321 struct videomode modes[64]; 3322 int nmodes = 0; 3323 int valid = 0; 3324 3325 for (i = 0; i < dp->rd_ncrtcs; i++) { 3326 /* 3327 * pick the largest resolution in common. 3328 */ 3329 rp = dp->rd_crtcs[i].rc_port; 3330 ep = &rp->rp_edid; 3331 3332 if (!rp->rp_edid_valid) 3333 continue; 3334 3335 if (!valid) { 3336 /* initialize starting list */ 3337 for (j = 0; j < ep->edid_nmodes; j++) { 3338 /* 3339 * ignore resolutions that are 3340 * too big for the radeon 3341 */ 3342 if (ep->edid_modes[j].hdisplay > 3343 dp->rd_softc->sc_maxx) 3344 continue; 3345 if (ep->edid_modes[j].vdisplay > 3346 dp->rd_softc->sc_maxy) 3347 continue; 3348 3349 modes[nmodes] = ep->edid_modes[j]; 3350 nmodes++; 3351 } 3352 valid = 1; 3353 } else { 3354 /* merge into preexisting list */ 3355 for (j = 0; j < nmodes; j++) { 3356 if (!radeonfb_hasres(ep->edid_modes, 3357 ep->edid_nmodes, 3358 modes[j].hdisplay, 3359 modes[j].vdisplay)) { 3360 modes[j] = modes[nmodes]; 3361 j--; 3362 nmodes--; 3363 } 3364 } 3365 } 3366 } 3367 3368 /* now we have to pick from the merged list */ 3369 for (i = 0; i < nmodes; i++) { 3370 if ((modes[i].hdisplay >= *x) && 3371 (modes[i].vdisplay >= *y)) { 3372 *x = modes[i].hdisplay; 3373 *y = modes[i].vdisplay; 3374 } 3375 } 3376 } 3377 3378 if ((*x == 0) || (*y == 0)) { 3379 /* fallback to safe mode */ 3380 *x = 640; 3381 *y = 480; 3382 } 3383 } 3384 3385 /* 3386 * backlight levels are linear on: 3387 * - RV200, RV250, RV280, RV350 3388 * - but NOT on PowerBook4,3 6,3 6,5 3389 * according to Linux' radeonfb 3390 */ 3391 3392 /* Get the current backlight level for the display. */ 3393 3394 static int 3395 radeonfb_get_backlight(struct radeonfb_display *dp) 3396 { 3397 int s; 3398 uint32_t level; 3399 3400 s = spltty(); 3401 3402 level = radeonfb_get32(dp->rd_softc, RADEON_LVDS_GEN_CNTL); 3403 level &= RADEON_LVDS_BL_MOD_LEV_MASK; 3404 level >>= RADEON_LVDS_BL_MOD_LEV_SHIFT; 3405 3406 /* 3407 * On some chips, we should negate the backlight level. 3408 * XXX Find out on which chips. 3409 */ 3410 if (dp->rd_softc->sc_flags & RFB_INV_BLIGHT) 3411 level = RADEONFB_BACKLIGHT_MAX - level; 3412 3413 splx(s); 3414 3415 return level; 3416 } 3417 3418 /* Set the backlight to the given level for the display. */ 3419 3420 static int 3421 radeonfb_set_backlight(struct radeonfb_display *dp, int level) 3422 { 3423 struct radeonfb_softc *sc; 3424 int rlevel, s; 3425 uint32_t lvds; 3426 3427 s = spltty(); 3428 3429 if (level < 0) 3430 level = 0; 3431 else if (level >= RADEONFB_BACKLIGHT_MAX) 3432 level = RADEONFB_BACKLIGHT_MAX; 3433 3434 sc = dp->rd_softc; 3435 3436 /* On some chips, we should negate the backlight level. */ 3437 if (dp->rd_softc->sc_flags & RFB_INV_BLIGHT) { 3438 rlevel = RADEONFB_BACKLIGHT_MAX - level; 3439 } else 3440 rlevel = level; 3441 3442 callout_stop(&dp->rd_bl_lvds_co); 3443 radeonfb_engine_idle(sc); 3444 3445 /* 3446 * Turn off the display if the backlight is set to 0, since the 3447 * display is useless without backlight anyway. 3448 */ 3449 if (level == 0) 3450 radeonfb_blank(dp, 1); 3451 else if (radeonfb_get_backlight(dp) == 0) 3452 radeonfb_blank(dp, 0); 3453 3454 lvds = radeonfb_get32(sc, RADEON_LVDS_GEN_CNTL); 3455 lvds &= ~RADEON_LVDS_DISPLAY_DIS; 3456 if (!(lvds & RADEON_LVDS_BLON) || !(lvds & RADEON_LVDS_ON)) { 3457 lvds |= dp->rd_bl_lvds_val & RADEON_LVDS_DIGON; 3458 lvds |= RADEON_LVDS_BLON | RADEON_LVDS_EN; 3459 radeonfb_put32(sc, RADEON_LVDS_GEN_CNTL, lvds); 3460 lvds &= ~RADEON_LVDS_BL_MOD_LEV_MASK; 3461 lvds |= rlevel << RADEON_LVDS_BL_MOD_LEV_SHIFT; 3462 lvds |= RADEON_LVDS_ON; 3463 lvds |= dp->rd_bl_lvds_val & RADEON_LVDS_BL_MOD_EN; 3464 } else { 3465 lvds &= ~RADEON_LVDS_BL_MOD_LEV_MASK; 3466 lvds |= rlevel << RADEON_LVDS_BL_MOD_LEV_SHIFT; 3467 radeonfb_put32(sc, RADEON_LVDS_GEN_CNTL, lvds); 3468 } 3469 3470 dp->rd_bl_lvds_val &= ~RADEON_LVDS_STATE_MASK; 3471 dp->rd_bl_lvds_val |= lvds & RADEON_LVDS_STATE_MASK; 3472 /* XXX What is the correct delay? */ 3473 callout_schedule(&dp->rd_bl_lvds_co, 200 * hz); 3474 3475 splx(s); 3476 3477 return 0; 3478 } 3479 3480 /* 3481 * Callout function for delayed operations on the LVDS_GEN_CNTL register. 3482 * Set the delayed bits in the register, and clear the stored delayed 3483 * value. 3484 */ 3485 3486 static void radeonfb_lvds_callout(void *arg) 3487 { 3488 struct radeonfb_display *dp = arg; 3489 int s; 3490 3491 s = splhigh(); 3492 3493 radeonfb_mask32(dp->rd_softc, RADEON_LVDS_GEN_CNTL, ~0, 3494 dp->rd_bl_lvds_val); 3495 dp->rd_bl_lvds_val = 0; 3496 3497 splx(s); 3498 } 3499
Indexes created Fri Oct 17 17:09:57 GMT 2025