radeonfb.c revision 1.25
1 /* $NetBSD: radeonfb.c,v 1.25 2008/02/28 00:21:38 macallan Exp $ */ 2 3 /*- 4 * Copyright (c) 2006 Itronix Inc. 5 * All rights reserved. 6 * 7 * Written by Garrett D'Amore for Itronix Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. The name of Itronix Inc. may not be used to endorse 18 * or promote products derived from this software without specific 19 * prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY ITRONIX INC. ``AS IS'' AND ANY EXPRESS 22 * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 23 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL ITRONIX INC. BE LIABLE FOR ANY 25 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE 27 * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 29 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 30 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 31 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * ATI Technologies Inc. ("ATI") has not assisted in the creation of, and 36 * does not endorse, this software. ATI will not be responsible or liable 37 * for any actual or alleged damage or loss caused by or in connection with 38 * the use of or reliance on this software. 39 */ 40 41 /* 42 * Portions of this code were taken from XFree86's Radeon driver, which bears 43 * this notice: 44 * 45 * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and 46 * VA Linux Systems Inc., Fremont, California. 47 * 48 * All Rights Reserved. 49 * 50 * Permission is hereby granted, free of charge, to any person obtaining 51 * a copy of this software and associated documentation files (the 52 * "Software"), to deal in the Software without restriction, including 53 * without limitation on the rights to use, copy, modify, merge, 54 * publish, distribute, sublicense, and/or sell copies of the Software, 55 * and to permit persons to whom the Software is furnished to do so, 56 * subject to the following conditions: 57 * 58 * The above copyright notice and this permission notice (including the 59 * next paragraph) shall be included in all copies or substantial 60 * portions of the Software. 61 * 62 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 63 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 64 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 65 * NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR 66 * THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 67 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 68 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 69 * DEALINGS IN THE SOFTWARE. 70 */ 71 72 #include <sys/cdefs.h> 73 __KERNEL_RCSID(0, "$NetBSD: radeonfb.c,v 1.25 2008/02/28 00:21:38 macallan Exp $"); 74 75 #define RADEONFB_DEFAULT_DEPTH 32 76 77 #include <sys/param.h> 78 #include <sys/systm.h> 79 #include <sys/device.h> 80 #include <sys/malloc.h> 81 #include <sys/bus.h> 82 #include <sys/kernel.h> 83 #include <sys/lwp.h> 84 #include <sys/kauth.h> 85 86 #include <dev/wscons/wsdisplayvar.h> 87 #include <dev/wscons/wsconsio.h> 88 #include <dev/wsfont/wsfont.h> 89 #include <dev/rasops/rasops.h> 90 #include <dev/videomode/videomode.h> 91 #include <dev/videomode/edidvar.h> 92 #include <dev/wscons/wsdisplay_vconsvar.h> 93 94 #include <dev/pci/pcidevs.h> 95 #include <dev/pci/pcireg.h> 96 #include <dev/pci/pcivar.h> 97 #include <dev/pci/radeonfbreg.h> 98 #include <dev/pci/radeonfbvar.h> 99 #include "opt_radeonfb.h" 100 101 static int radeonfb_match(struct device *, struct cfdata *, void *); 102 static void radeonfb_attach(struct device *, struct device *, void *); 103 static int radeonfb_ioctl(void *, void *, unsigned long, void *, int, 104 struct lwp *); 105 static paddr_t radeonfb_mmap(void *, void *, off_t, int); 106 static int radeonfb_scratch_test(struct radeonfb_softc *, int, uint32_t); 107 static void radeonfb_loadbios(struct radeonfb_softc *, 108 struct pci_attach_args *); 109 110 static uintmax_t radeonfb_getprop_num(struct radeonfb_softc *, const char *, 111 uintmax_t); 112 static int radeonfb_getclocks(struct radeonfb_softc *); 113 static int radeonfb_gettmds(struct radeonfb_softc *); 114 static int radeonfb_calc_dividers(struct radeonfb_softc *, uint32_t, 115 uint32_t *, uint32_t *); 116 static int radeonfb_getconnectors(struct radeonfb_softc *); 117 static const struct videomode *radeonfb_modelookup(const char *); 118 static void radeonfb_init_screen(void *, struct vcons_screen *, int, long *); 119 static void radeonfb_pllwriteupdate(struct radeonfb_softc *, int); 120 static void radeonfb_pllwaitatomicread(struct radeonfb_softc *, int); 121 static void radeonfb_program_vclk(struct radeonfb_softc *, int, int); 122 static void radeonfb_modeswitch(struct radeonfb_display *); 123 static void radeonfb_setcrtc(struct radeonfb_display *, int); 124 static void radeonfb_init_misc(struct radeonfb_softc *); 125 static void radeonfb_set_fbloc(struct radeonfb_softc *); 126 static void radeonfb_init_palette(struct radeonfb_softc *, int); 127 static void radeonfb_r300cg_workaround(struct radeonfb_softc *); 128 129 static int radeonfb_isblank(struct radeonfb_display *); 130 static void radeonfb_blank(struct radeonfb_display *, int); 131 static int radeonfb_set_cursor(struct radeonfb_display *, 132 struct wsdisplay_cursor *); 133 static int radeonfb_set_curpos(struct radeonfb_display *, 134 struct wsdisplay_curpos *); 135 136 /* acceleration support */ 137 static void radeonfb_rectfill(struct radeonfb_display *, int dstx, int dsty, 138 int width, int height, uint32_t color); 139 static void radeonfb_bitblt(struct radeonfb_display *, int srcx, int srcy, 140 int dstx, int dsty, int width, int height, int rop, uint32_t mask); 141 static void radeonfb_feed_bytes(struct radeonfb_display *, int, uint8_t *); 142 static void radeonfb_setup_mono(struct radeonfb_display *, int, int, int, 143 int, uint32_t, uint32_t); 144 145 /* hw cursor support */ 146 static void radeonfb_cursor_cmap(struct radeonfb_display *); 147 static void radeonfb_cursor_shape(struct radeonfb_display *); 148 static void radeonfb_cursor_position(struct radeonfb_display *); 149 static void radeonfb_cursor_visible(struct radeonfb_display *); 150 static void radeonfb_cursor_update(struct radeonfb_display *, unsigned); 151 152 static void radeonfb_wait_fifo(struct radeonfb_softc *, int); 153 static void radeonfb_engine_idle(struct radeonfb_softc *); 154 static void radeonfb_engine_flush(struct radeonfb_softc *); 155 static void radeonfb_engine_reset(struct radeonfb_softc *); 156 static void radeonfb_engine_init(struct radeonfb_display *); 157 static inline void radeonfb_unclip(struct radeonfb_softc *); 158 159 static void radeonfb_eraserows(void *, int, int, long); 160 static void radeonfb_erasecols(void *, int, int, int, long); 161 static void radeonfb_copyrows(void *, int, int, int); 162 static void radeonfb_copycols(void *, int, int, int, int); 163 static void radeonfb_cursor(void *, int, int, int); 164 static void radeonfb_putchar(void *, int, int, unsigned, long); 165 static int radeonfb_allocattr(void *, int, int, int, long *); 166 167 static int radeonfb_get_backlight(struct radeonfb_display *); 168 static int radeonfb_set_backlight(struct radeonfb_display *, int); 169 static void radeonfb_lvds_callout(void *); 170 171 static struct videomode *radeonfb_best_refresh(struct videomode *, 172 struct videomode *); 173 static void radeonfb_pickres(struct radeonfb_display *, uint16_t *, 174 uint16_t *, int); 175 static const struct videomode *radeonfb_port_mode(struct radeonfb_softc *, 176 struct radeonfb_port *, int, int); 177 178 static int radeonfb_drm_print(void *, const char *); 179 180 #ifdef RADEON_DEBUG 181 int radeon_debug = 1; 182 #define DPRINTF(x) \ 183 if (radeon_debug) printf x 184 #define PRINTREG(r) DPRINTF((#r " = %08x\n", GET32(sc, r))) 185 #define PRINTPLL(r) DPRINTF((#r " = %08x\n", GETPLL(sc, r))) 186 #else 187 #define DPRINTF(x) 188 #define PRINTREG(r) 189 #define PRINTPLL(r) 190 #endif 191 192 #define ROUNDUP(x,y) (((x) + ((y) - 1)) & ~((y) - 1)) 193 194 #ifndef RADEON_DEFAULT_MODE 195 /* any reasonably modern display should handle this */ 196 #define RADEON_DEFAULT_MODE "1024x768x60" 197 #endif 198 199 const char *radeonfb_default_mode = RADEON_DEFAULT_MODE; 200 201 static struct { 202 int size; /* minimum memory size (MB) */ 203 int maxx; /* maximum x dimension */ 204 int maxy; /* maximum y dimension */ 205 int maxbpp; /* maximum bpp */ 206 int maxdisp; /* maximum logical display count */ 207 } radeonfb_limits[] = { 208 { 32, 2048, 1536, 32, 2 }, 209 { 16, 1600, 1200, 32, 2 }, 210 { 8, 1600, 1200, 32, 1 }, 211 { 0, 0, 0, 0, 0 }, 212 }; 213 214 static struct wsscreen_descr radeonfb_stdscreen = { 215 "fb", /* name */ 216 0, 0, /* ncols, nrows */ 217 NULL, /* textops */ 218 8, 16, /* fontwidth, fontheight */ 219 WSSCREEN_WSCOLORS, /* capabilities */ 220 0, /* modecookie */ 221 }; 222 223 struct wsdisplay_accessops radeonfb_accessops = { 224 radeonfb_ioctl, 225 radeonfb_mmap, 226 NULL, /* vcons_alloc_screen */ 227 NULL, /* vcons_free_screen */ 228 NULL, /* vcons_show_screen */ 229 NULL, /* load_font */ 230 NULL, /* pollc */ 231 NULL, /* scroll */ 232 }; 233 234 static struct { 235 uint16_t devid; 236 uint16_t family; 237 uint16_t flags; 238 } radeonfb_devices[] = 239 { 240 /* R100 family */ 241 { PCI_PRODUCT_ATI_RADEON_R100_QD, RADEON_R100, 0 }, 242 { PCI_PRODUCT_ATI_RADEON_R100_QE, RADEON_R100, 0 }, 243 { PCI_PRODUCT_ATI_RADEON_R100_QF, RADEON_R100, 0 }, 244 { PCI_PRODUCT_ATI_RADEON_R100_QG, RADEON_R100, 0 }, 245 246 /* RV100 family */ 247 { PCI_PRODUCT_ATI_RADEON_RV100_LY, RADEON_RV100, RFB_MOB }, 248 { PCI_PRODUCT_ATI_RADEON_RV100_LZ, RADEON_RV100, RFB_MOB }, 249 { PCI_PRODUCT_ATI_RADEON_RV100_QY, RADEON_RV100, 0 }, 250 { PCI_PRODUCT_ATI_RADEON_RV100_QZ, RADEON_RV100, 0 }, 251 252 /* RS100 family */ 253 { PCI_PRODUCT_ATI_RADEON_RS100_4136, RADEON_RS100, 0 }, 254 { PCI_PRODUCT_ATI_RADEON_RS100_4336, RADEON_RS100, RFB_MOB }, 255 256 /* RS200/RS250 family */ 257 { PCI_PRODUCT_ATI_RADEON_RS200_4337, RADEON_RS200, RFB_MOB }, 258 { PCI_PRODUCT_ATI_RADEON_RS200_A7, RADEON_RS200, 0 }, 259 { PCI_PRODUCT_ATI_RADEON_RS250_B7, RADEON_RS200, RFB_MOB }, 260 { PCI_PRODUCT_ATI_RADEON_RS250_D7, RADEON_RS200, 0 }, 261 262 /* R200 family */ 263 /* add more R200 products? , 5148 */ 264 { PCI_PRODUCT_ATI_RADEON_R200_BB, RADEON_R200, 0 }, 265 { PCI_PRODUCT_ATI_RADEON_R200_BC, RADEON_R200, 0 }, 266 { PCI_PRODUCT_ATI_RADEON_R200_QH, RADEON_R200, 0 }, 267 { PCI_PRODUCT_ATI_RADEON_R200_QL, RADEON_R200, 0 }, 268 { PCI_PRODUCT_ATI_RADEON_R200_QM, RADEON_R200, 0 }, 269 270 /* RV200 family */ 271 { PCI_PRODUCT_ATI_RADEON_RV200_LW, RADEON_RV200, RFB_MOB }, 272 { PCI_PRODUCT_ATI_RADEON_RV200_LX, RADEON_RV200, RFB_MOB }, 273 { PCI_PRODUCT_ATI_RADEON_RV200_QW, RADEON_RV200, 0 }, 274 { PCI_PRODUCT_ATI_RADEON_RV200_QX, RADEON_RV200, 0 }, 275 276 /* RV250 family */ 277 { PCI_PRODUCT_ATI_RADEON_RV250_4966, RADEON_RV250, 0 }, 278 { PCI_PRODUCT_ATI_RADEON_RV250_4967, RADEON_RV250, 0 }, 279 { PCI_PRODUCT_ATI_RADEON_RV250_4C64, RADEON_RV250, RFB_MOB }, 280 { PCI_PRODUCT_ATI_RADEON_RV250_4C66, RADEON_RV250, RFB_MOB }, 281 { PCI_PRODUCT_ATI_RADEON_RV250_4C67, RADEON_RV250, RFB_MOB }, 282 283 /* RS300 family */ 284 { PCI_PRODUCT_ATI_RADEON_RS300_X5, RADEON_RS300, 0 }, 285 { PCI_PRODUCT_ATI_RADEON_RS300_X4, RADEON_RS300, 0 }, 286 { PCI_PRODUCT_ATI_RADEON_RS300_7834, RADEON_RS300, 0 }, 287 { PCI_PRODUCT_ATI_RADEON_RS300_7835, RADEON_RS300, RFB_MOB }, 288 289 /* RV280 family */ 290 { PCI_PRODUCT_ATI_RADEON_RV280_5960, RADEON_RV280, 0 }, 291 { PCI_PRODUCT_ATI_RADEON_RV280_5961, RADEON_RV280, 0 }, 292 { PCI_PRODUCT_ATI_RADEON_RV280_5962, RADEON_RV280, 0 }, 293 { PCI_PRODUCT_ATI_RADEON_RV280_5963, RADEON_RV280, 0 }, 294 { PCI_PRODUCT_ATI_RADEON_RV280_5964, RADEON_RV280, 0 }, 295 { PCI_PRODUCT_ATI_RADEON_RV280_5C61, RADEON_RV280, RFB_MOB }, 296 { PCI_PRODUCT_ATI_RADEON_RV280_5C63, RADEON_RV280, RFB_MOB }, 297 298 /* R300 family */ 299 { PCI_PRODUCT_ATI_RADEON_R300_AD, RADEON_R300, 0 }, 300 { PCI_PRODUCT_ATI_RADEON_R300_AE, RADEON_R300, 0 }, 301 { PCI_PRODUCT_ATI_RADEON_R300_AF, RADEON_R300, 0 }, 302 { PCI_PRODUCT_ATI_RADEON_R300_AG, RADEON_R300, 0 }, 303 { PCI_PRODUCT_ATI_RADEON_R300_ND, RADEON_R300, 0 }, 304 { PCI_PRODUCT_ATI_RADEON_R300_NE, RADEON_R300, 0 }, 305 { PCI_PRODUCT_ATI_RADEON_R300_NF, RADEON_R300, 0 }, 306 { PCI_PRODUCT_ATI_RADEON_R300_NG, RADEON_R300, 0 }, 307 308 /* RV350/RV360 family */ 309 { PCI_PRODUCT_ATI_RADEON_RV350_AP, RADEON_RV350, 0 }, 310 { PCI_PRODUCT_ATI_RADEON_RV350_AQ, RADEON_RV350, 0 }, 311 { PCI_PRODUCT_ATI_RADEON_RV360_AR, RADEON_RV350, 0 }, 312 { PCI_PRODUCT_ATI_RADEON_RV350_AS, RADEON_RV350, 0 }, 313 { PCI_PRODUCT_ATI_RADEON_RV350_AT, RADEON_RV350, 0 }, 314 { PCI_PRODUCT_ATI_RADEON_RV350_AV, RADEON_RV350, 0 }, 315 { PCI_PRODUCT_ATI_RADEON_RV350_NP, RADEON_RV350, RFB_MOB }, 316 { PCI_PRODUCT_ATI_RADEON_RV350_NQ, RADEON_RV350, RFB_MOB }, 317 { PCI_PRODUCT_ATI_RADEON_RV350_NR, RADEON_RV350, RFB_MOB }, 318 { PCI_PRODUCT_ATI_RADEON_RV350_NS, RADEON_RV350, RFB_MOB }, 319 { PCI_PRODUCT_ATI_RADEON_RV350_NT, RADEON_RV350, RFB_MOB }, 320 { PCI_PRODUCT_ATI_RADEON_RV350_NV, RADEON_RV350, RFB_MOB }, 321 322 /* R350/R360 family */ 323 { PCI_PRODUCT_ATI_RADEON_R350_AH, RADEON_R350, 0 }, 324 { PCI_PRODUCT_ATI_RADEON_R350_AI, RADEON_R350, 0 }, 325 { PCI_PRODUCT_ATI_RADEON_R350_AJ, RADEON_R350, 0 }, 326 { PCI_PRODUCT_ATI_RADEON_R350_AK, RADEON_R350, 0 }, 327 { PCI_PRODUCT_ATI_RADEON_R350_NH, RADEON_R350, 0 }, 328 { PCI_PRODUCT_ATI_RADEON_R350_NI, RADEON_R350, 0 }, 329 { PCI_PRODUCT_ATI_RADEON_R350_NK, RADEON_R350, 0 }, 330 { PCI_PRODUCT_ATI_RADEON_R360_NJ, RADEON_R350, 0 }, 331 332 /* RV380/RV370 family */ 333 { PCI_PRODUCT_ATI_RADEON_RV380_3150, RADEON_RV380, RFB_MOB }, 334 { PCI_PRODUCT_ATI_RADEON_RV380_3154, RADEON_RV380, RFB_MOB }, 335 { PCI_PRODUCT_ATI_RADEON_RV380_3E50, RADEON_RV380, 0 }, 336 { PCI_PRODUCT_ATI_RADEON_RV380_3E54, RADEON_RV380, 0 }, 337 { PCI_PRODUCT_ATI_RADEON_RV370_5460, RADEON_RV380, RFB_MOB }, 338 { PCI_PRODUCT_ATI_RADEON_RV370_5464, RADEON_RV380, RFB_MOB }, 339 { PCI_PRODUCT_ATI_RADEON_RV370_5B60, RADEON_RV380, 0 }, 340 { PCI_PRODUCT_ATI_RADEON_RV370_5B64, RADEON_RV380, 0 }, 341 { PCI_PRODUCT_ATI_RADEON_RV370_5B65, RADEON_RV380, 0 }, 342 343 /* R420/R423 family */ 344 { PCI_PRODUCT_ATI_RADEON_R420_JH, RADEON_R420, 0 }, 345 { PCI_PRODUCT_ATI_RADEON_R420_JI, RADEON_R420, 0 }, 346 { PCI_PRODUCT_ATI_RADEON_R420_JJ, RADEON_R420, 0 }, 347 { PCI_PRODUCT_ATI_RADEON_R420_JK, RADEON_R420, 0 }, 348 { PCI_PRODUCT_ATI_RADEON_R420_JL, RADEON_R420, 0 }, 349 { PCI_PRODUCT_ATI_RADEON_R420_JM, RADEON_R420, 0 }, 350 { PCI_PRODUCT_ATI_RADEON_R420_JN, RADEON_R420, RFB_MOB }, 351 { PCI_PRODUCT_ATI_RADEON_R420_JP, RADEON_R420, 0 }, 352 { PCI_PRODUCT_ATI_RADEON_R423_UH, RADEON_R420, 0 }, 353 { PCI_PRODUCT_ATI_RADEON_R423_UI, RADEON_R420, 0 }, 354 { PCI_PRODUCT_ATI_RADEON_R423_UJ, RADEON_R420, 0 }, 355 { PCI_PRODUCT_ATI_RADEON_R423_UK, RADEON_R420, 0 }, 356 { PCI_PRODUCT_ATI_RADEON_R423_UQ, RADEON_R420, 0 }, 357 { PCI_PRODUCT_ATI_RADEON_R423_UR, RADEON_R420, 0 }, 358 { PCI_PRODUCT_ATI_RADEON_R423_UT, RADEON_R420, 0 }, 359 { PCI_PRODUCT_ATI_RADEON_R423_5D57, RADEON_R420, 0 }, 360 { PCI_PRODUCT_ATI_RADEON_R430_554F, RADEON_R420, 0 }, 361 362 { 0, 0, 0 } 363 }; 364 365 static struct { 366 int divider; 367 int mask; 368 } radeonfb_dividers[] = { 369 { 1, 0 }, 370 { 2, 1 }, 371 { 3, 4 }, 372 { 4, 2 }, 373 { 6, 6 }, 374 { 8, 3 }, 375 { 12, 7 }, 376 { 0, 0 } 377 }; 378 379 /* 380 * This table taken from X11. 381 */ 382 static const struct { 383 int family; 384 struct radeon_tmds_pll plls[4]; 385 } radeonfb_tmds_pll[] = { 386 { RADEON_R100, {{12000, 0xa1b}, {-1, 0xa3f}}}, 387 { RADEON_RV100, {{12000, 0xa1b}, {-1, 0xa3f}}}, 388 { RADEON_RS100, {{0, 0}}}, 389 { RADEON_RV200, {{15000, 0xa1b}, {-1, 0xa3f}}}, 390 { RADEON_RS200, {{15000, 0xa1b}, {-1, 0xa3f}}}, 391 { RADEON_R200, {{15000, 0xa1b}, {-1, 0xa3f}}}, 392 { RADEON_RV250, {{15500, 0x81b}, {-1, 0x83f}}}, 393 { RADEON_RS300, {{0, 0}}}, 394 { RADEON_RV280, {{13000, 0x400f4}, {15000, 0x400f7}}}, 395 { RADEON_R300, {{-1, 0xb01cb}}}, 396 { RADEON_R350, {{-1, 0xb01cb}}}, 397 { RADEON_RV350, {{15000, 0xb0155}, {-1, 0xb01cb}}}, 398 { RADEON_RV380, {{15000, 0xb0155}, {-1, 0xb01cb}}}, 399 { RADEON_R420, {{-1, 0xb01cb}}}, 400 }; 401 402 #define RADEONFB_BACKLIGHT_MAX 255 /* Maximum backlight level. */ 403 404 405 CFATTACH_DECL(radeonfb, sizeof (struct radeonfb_softc), 406 radeonfb_match, radeonfb_attach, NULL, NULL); 407 408 static int 409 radeonfb_match(struct device *parent, struct cfdata *match, void *aux) 410 { 411 struct pci_attach_args *pa = aux; 412 int i; 413 414 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_ATI) 415 return 0; 416 417 for (i = 0; radeonfb_devices[i].devid; i++) { 418 if (PCI_PRODUCT(pa->pa_id) == radeonfb_devices[i].devid) 419 return 100; /* high to defeat VGA/VESA */ 420 } 421 422 return 0; 423 } 424 425 static void 426 radeonfb_attach(struct device *parent, struct device *dev, void *aux) 427 { 428 struct radeonfb_softc *sc = (struct radeonfb_softc *)dev; 429 struct pci_attach_args *pa = aux; 430 const char *mptr; 431 bus_size_t bsz; 432 pcireg_t screg; 433 int i, j, fg, bg, ul; 434 uint32_t v; 435 436 sc->sc_id = pa->pa_id; 437 for (i = 0; radeonfb_devices[i].devid; i++) { 438 if (PCI_PRODUCT(sc->sc_id) == radeonfb_devices[i].devid) 439 break; 440 } 441 442 pci_devinfo(sc->sc_id, pa->pa_class, 0, sc->sc_devinfo, 443 sizeof(sc->sc_devinfo)); 444 445 aprint_naive("\n"); 446 aprint_normal(": %s\n", sc->sc_devinfo); 447 448 DPRINTF((prop_dictionary_externalize(device_properties(dev)))); 449 450 KASSERT(radeonfb_devices[i].devid != 0); 451 sc->sc_pt = pa->pa_tag; 452 sc->sc_iot = pa->pa_iot; 453 sc->sc_pc = pa->pa_pc; 454 sc->sc_family = radeonfb_devices[i].family; 455 sc->sc_flags = radeonfb_devices[i].flags; 456 457 /* enable memory and IO access */ 458 screg = pci_conf_read(sc->sc_pc, sc->sc_pt, PCI_COMMAND_STATUS_REG); 459 screg |= PCI_FLAGS_IO_ENABLED | PCI_FLAGS_MEM_ENABLED; 460 pci_conf_write(sc->sc_pc, sc->sc_pt, PCI_COMMAND_STATUS_REG, screg); 461 462 /* 463 * Some flags are general to entire chip families, and rather 464 * than clutter up the table with them, we go ahead and set 465 * them here. 466 */ 467 switch (sc->sc_family) { 468 case RADEON_RS100: 469 case RADEON_RS200: 470 sc->sc_flags |= RFB_IGP | RFB_RV100; 471 break; 472 473 case RADEON_RV100: 474 case RADEON_RV200: 475 case RADEON_RV250: 476 case RADEON_RV280: 477 sc->sc_flags |= RFB_RV100; 478 break; 479 480 case RADEON_RS300: 481 sc->sc_flags |= RFB_SDAC | RFB_IGP | RFB_RV100; 482 break; 483 484 case RADEON_R300: 485 case RADEON_RV350: 486 case RADEON_R350: 487 case RADEON_RV380: 488 case RADEON_R420: 489 /* newer chips */ 490 sc->sc_flags |= RFB_R300; 491 break; 492 493 case RADEON_R100: 494 sc->sc_flags |= RFB_NCRTC2; 495 break; 496 } 497 498 if ((sc->sc_family == RADEON_RV200) || 499 (sc->sc_family == RADEON_RV250) || 500 (sc->sc_family == RADEON_RV280) || 501 (sc->sc_family == RADEON_RV350)) { 502 bool inverted = 0; 503 /* backlight level is linear */ 504 DPRINTF(("found RV* chip, backlight is supposedly linear\n")); 505 prop_dictionary_get_bool(device_properties(&sc->sc_dev), 506 "backlight_level_reverted", &inverted); 507 if (inverted) { 508 DPRINTF(("nope, it's inverted\n")); 509 sc->sc_flags |= RFB_INV_BLIGHT; 510 } 511 } else 512 sc->sc_flags |= RFB_INV_BLIGHT; 513 514 /* 515 * XXX: to support true multihead, this must change. 516 */ 517 sc->sc_ndisplays = 1; 518 519 /* XXX: */ 520 if (!HAS_CRTC2(sc)) { 521 sc->sc_ndisplays = 1; 522 } 523 524 if (pci_mapreg_map(pa, RADEON_MAPREG_MMIO, PCI_MAPREG_TYPE_MEM, 0, 525 &sc->sc_regt, &sc->sc_regh, &sc->sc_regaddr, 526 &sc->sc_regsz) != 0) { 527 aprint_error("%s: unable to map registers!\n", XNAME(sc)); 528 goto error; 529 } 530 531 /* scratch register test... */ 532 if (radeonfb_scratch_test(sc, RADEON_BIOS_0_SCRATCH, 0x55555555) || 533 radeonfb_scratch_test(sc, RADEON_BIOS_0_SCRATCH, 0xaaaaaaaa)) { 534 aprint_error("%s: scratch register test failed!\n", XNAME(sc)); 535 goto error; 536 } 537 538 PRINTREG(RADEON_BIOS_4_SCRATCH); 539 PRINTREG(RADEON_FP_GEN_CNTL); 540 PRINTREG(RADEON_FP2_GEN_CNTL); 541 PRINTREG(RADEON_TMDS_CNTL); 542 PRINTREG(RADEON_TMDS_TRANSMITTER_CNTL); 543 PRINTREG(RADEON_TMDS_PLL_CNTL); 544 PRINTREG(RADEON_LVDS_GEN_CNTL); 545 PRINTREG(RADEON_FP_HORZ_STRETCH); 546 PRINTREG(RADEON_FP_VERT_STRETCH); 547 548 /* XXX: RV100 specific */ 549 PUT32(sc, RADEON_TMDS_PLL_CNTL, 0xa27); 550 551 PATCH32(sc, RADEON_TMDS_TRANSMITTER_CNTL, 552 RADEON_TMDS_TRANSMITTER_PLLEN, 553 RADEON_TMDS_TRANSMITTER_PLLEN | RADEON_TMDS_TRANSMITTER_PLLRST); 554 555 radeonfb_i2c_init(sc); 556 557 radeonfb_loadbios(sc, pa); 558 559 #ifdef RADEON_BIOS_INIT 560 if (radeonfb_bios_init(sc)) { 561 aprint_error("%s: BIOS inititialization failed\n", XNAME(sc)); 562 goto error; 563 } 564 #endif 565 566 if (radeonfb_getclocks(sc)) { 567 aprint_error("%s: Unable to get reference clocks from BIOS\n", 568 XNAME(sc)); 569 goto error; 570 } 571 572 if (radeonfb_gettmds(sc)) { 573 aprint_error("%s: Unable to identify TMDS PLL settings\n", 574 XNAME(sc)); 575 goto error; 576 } 577 578 aprint_verbose("%s: refclk = %d.%03d MHz, refdiv = %d " 579 "minpll = %d, maxpll = %d\n", XNAME(sc), 580 (int)sc->sc_refclk / 1000, (int)sc->sc_refclk % 1000, 581 (int)sc->sc_refdiv, (int)sc->sc_minpll, (int)sc->sc_maxpll); 582 583 radeonfb_getconnectors(sc); 584 585 radeonfb_set_fbloc(sc); 586 587 for (i = 0; radeonfb_limits[i].size; i++) { 588 if (sc->sc_memsz >= radeonfb_limits[i].size) { 589 sc->sc_maxx = radeonfb_limits[i].maxx; 590 sc->sc_maxy = radeonfb_limits[i].maxy; 591 sc->sc_maxbpp = radeonfb_limits[i].maxbpp; 592 /* framebuffer offset, start at a 4K page */ 593 sc->sc_fboffset = sc->sc_memsz / 594 radeonfb_limits[i].maxdisp; 595 /* 596 * we use the fbsize to figure out where we can store 597 * things like cursor data. 598 */ 599 sc->sc_fbsize = 600 ROUNDUP(ROUNDUP(sc->sc_maxx * sc->sc_maxbpp / 8 , 601 RADEON_STRIDEALIGN) * sc->sc_maxy, 602 4096); 603 break; 604 } 605 } 606 607 608 radeonfb_init_misc(sc); 609 radeonfb_init_palette(sc, 0); 610 if (HAS_CRTC2(sc)) 611 radeonfb_init_palette(sc, 1); 612 613 /* program the DAC wirings */ 614 for (i = 0; i < (HAS_CRTC2(sc) ? 2 : 1); i++) { 615 switch (sc->sc_ports[i].rp_dac_type) { 616 case RADEON_DAC_PRIMARY: 617 PATCH32(sc, RADEON_DAC_CNTL2, 618 i ? RADEON_DAC2_DAC_CLK_SEL : 0, 619 ~RADEON_DAC2_DAC_CLK_SEL); 620 break; 621 case RADEON_DAC_TVDAC: 622 /* we always use the TVDAC to drive a secondary analog 623 * CRT for now. if we ever support TV-out this will 624 * have to change. 625 */ 626 SET32(sc, RADEON_DAC_CNTL2, 627 RADEON_DAC2_DAC2_CLK_SEL); 628 PATCH32(sc, RADEON_DISP_HW_DEBUG, 629 i ? 0 : RADEON_CRT2_DISP1_SEL, 630 ~RADEON_CRT2_DISP1_SEL); 631 break; 632 } 633 } 634 PRINTREG(RADEON_DAC_CNTL2); 635 PRINTREG(RADEON_DISP_HW_DEBUG); 636 637 /* other DAC programming */ 638 v = GET32(sc, RADEON_DAC_CNTL); 639 v &= (RADEON_DAC_RANGE_CNTL_MASK | RADEON_DAC_BLANKING); 640 v |= RADEON_DAC_MASK_ALL | RADEON_DAC_8BIT_EN; 641 PUT32(sc, RADEON_DAC_CNTL, v); 642 PRINTREG(RADEON_DAC_CNTL); 643 644 /* XXX: this may need more investigation */ 645 PUT32(sc, RADEON_TV_DAC_CNTL, 0x00280203); 646 PRINTREG(RADEON_TV_DAC_CNTL); 647 648 /* enable TMDS */ 649 SET32(sc, RADEON_FP_GEN_CNTL, 650 RADEON_FP_TMDS_EN | 651 RADEON_FP_CRTC_DONT_SHADOW_VPAR | 652 RADEON_FP_CRTC_DONT_SHADOW_HEND); 653 CLR32(sc, RADEON_FP_GEN_CNTL, RADEON_FP_SEL_CRTC2); 654 if (HAS_CRTC2(sc)) 655 SET32(sc, RADEON_FP2_GEN_CNTL, RADEON_FP2_SRC_SEL_CRTC2); 656 657 /* 658 * we use bus_space_map instead of pci_mapreg, because we don't 659 * need the full aperature space. no point in wasting virtual 660 * address space we don't intend to use, right? 661 */ 662 if ((sc->sc_memsz < (4096 * 1024)) || 663 (pci_mapreg_info(sc->sc_pc, sc->sc_pt, RADEON_MAPREG_VRAM, 664 PCI_MAPREG_TYPE_MEM, &sc->sc_memaddr, &bsz, NULL) != 0) || 665 (bsz < sc->sc_memsz)) { 666 sc->sc_memsz = 0; 667 aprint_error("%s: Bad frame buffer configuration\n", 668 XNAME(sc)); 669 goto error; 670 } 671 672 /* 64 MB should be enough -- more just wastes map entries */ 673 if (sc->sc_memsz > (64 << 20)) 674 sc->sc_memsz = (64 << 20); 675 676 sc->sc_memt = pa->pa_memt; 677 if (bus_space_map(sc->sc_memt, sc->sc_memaddr, sc->sc_memsz, 678 BUS_SPACE_MAP_LINEAR, &sc->sc_memh) != 0) { 679 sc->sc_memsz = 0; 680 aprint_error("%s: Unable to map frame buffer\n", XNAME(sc)); 681 goto error; 682 } 683 684 aprint_normal("%s: %d MB aperture at 0x%08x, " 685 "%d KB registers at 0x%08x\n", XNAME(sc), 686 (int)sc->sc_memsz >> 20, (unsigned)sc->sc_memaddr, 687 (int)sc->sc_regsz >> 10, (unsigned)sc->sc_regaddr); 688 689 /* setup default video mode from devprop (allows PROM override) */ 690 sc->sc_defaultmode = radeonfb_default_mode; 691 if (prop_dictionary_get_cstring_nocopy(device_properties(&sc->sc_dev), 692 "videomode", &mptr)) { 693 694 strncpy(sc->sc_modebuf, mptr, sizeof(sc->sc_modebuf)); 695 sc->sc_defaultmode = sc->sc_modebuf; 696 } 697 698 /* initialize some basic display parameters */ 699 for (i = 0; i < sc->sc_ndisplays; i++) { 700 struct radeonfb_display *dp = &sc->sc_displays[i]; 701 struct rasops_info *ri; 702 long defattr; 703 struct wsemuldisplaydev_attach_args aa; 704 705 /* 706 * Figure out how many "displays" (desktops) we are going to 707 * support. If more than one, then each CRTC gets its own 708 * programming. 709 * 710 * XXX: this code needs to change to support mergedfb. 711 * XXX: would be nice to allow this to be overridden 712 */ 713 if (HAS_CRTC2(sc) && (sc->sc_ndisplays == 1)) { 714 DPRINTF(("dual crtcs!\n")); 715 dp->rd_ncrtcs = 2; 716 dp->rd_crtcs[0].rc_number = 0; 717 dp->rd_crtcs[1].rc_number = 1; 718 } else { 719 dp->rd_ncrtcs = 1; 720 dp->rd_crtcs[0].rc_number = i; 721 } 722 723 /* set up port pointer */ 724 for (j = 0; j < dp->rd_ncrtcs; j++) { 725 dp->rd_crtcs[j].rc_port = 726 &sc->sc_ports[dp->rd_crtcs[j].rc_number]; 727 } 728 729 dp->rd_softc = sc; 730 dp->rd_wsmode = WSDISPLAYIO_MODE_EMUL; 731 dp->rd_bg = WS_DEFAULT_BG; 732 #if 0 733 dp->rd_bpp = sc->sc_maxbpp; /* XXX: for now */ 734 #else 735 dp->rd_bpp = RADEONFB_DEFAULT_DEPTH; /* XXX */ 736 #endif 737 /* for text mode, we pick a resolution that won't 738 * require panning */ 739 radeonfb_pickres(dp, &dp->rd_virtx, &dp->rd_virty, 0); 740 741 aprint_normal("%s: display %d: " 742 "initial virtual resolution %dx%d at %d bpp\n", 743 XNAME(sc), i, dp->rd_virtx, dp->rd_virty, dp->rd_bpp); 744 745 /* now select the *video mode* that we will use */ 746 for (j = 0; j < dp->rd_ncrtcs; j++) { 747 const struct videomode *vmp; 748 vmp = radeonfb_port_mode(sc, dp->rd_crtcs[j].rc_port, 749 dp->rd_virtx, dp->rd_virty); 750 751 /* 752 * virtual resolution should be at least as high as 753 * physical 754 */ 755 if (dp->rd_virtx < vmp->hdisplay || 756 dp->rd_virty < vmp->vdisplay) { 757 dp->rd_virtx = vmp->hdisplay; 758 dp->rd_virty = vmp->vdisplay; 759 } 760 761 dp->rd_crtcs[j].rc_videomode = *vmp; 762 printf("%s: port %d: physical %dx%d %dHz\n", 763 XNAME(sc), j, vmp->hdisplay, vmp->vdisplay, 764 DIVIDE(DIVIDE(vmp->dot_clock * 1000, 765 vmp->htotal), vmp->vtotal)); 766 } 767 768 /* N.B.: radeon wants 64-byte aligned stride */ 769 dp->rd_stride = dp->rd_virtx * dp->rd_bpp / 8; 770 dp->rd_stride = ROUNDUP(dp->rd_stride, RADEON_STRIDEALIGN); 771 772 dp->rd_offset = sc->sc_fboffset * i; 773 dp->rd_fbptr = (vaddr_t)bus_space_vaddr(sc->sc_memt, 774 sc->sc_memh) + dp->rd_offset; 775 dp->rd_curoff = sc->sc_fbsize; 776 dp->rd_curptr = dp->rd_fbptr + dp->rd_curoff; 777 778 DPRINTF(("fpbtr = %p\n", (void *)dp->rd_fbptr)); 779 780 switch (dp->rd_bpp) { 781 case 8: 782 dp->rd_format = 2; 783 break; 784 case 32: 785 dp->rd_format = 6; 786 break; 787 default: 788 aprint_error("%s: bad depth %d\n", XNAME(sc), 789 dp->rd_bpp); 790 goto error; 791 } 792 793 printf("init engine\n"); 794 /* XXX: this seems suspicious - per display engine 795 initialization? */ 796 radeonfb_engine_init(dp); 797 798 /* copy the template into place */ 799 dp->rd_wsscreens_storage[0] = radeonfb_stdscreen; 800 dp->rd_wsscreens = dp->rd_wsscreens_storage; 801 802 /* and make up the list */ 803 dp->rd_wsscreenlist.nscreens = 1; 804 dp->rd_wsscreenlist.screens = 805 (const struct wsscreen_descr **)&dp->rd_wsscreens; 806 807 vcons_init(&dp->rd_vd, dp, dp->rd_wsscreens, 808 &radeonfb_accessops); 809 810 dp->rd_vd.init_screen = radeonfb_init_screen; 811 812 dp->rd_console = 1; 813 814 dp->rd_vscreen.scr_flags |= VCONS_SCREEN_IS_STATIC; 815 816 817 vcons_init_screen(&dp->rd_vd, &dp->rd_vscreen, 818 dp->rd_console, &defattr); 819 820 ri = &dp->rd_vscreen.scr_ri; 821 822 /* clear the screen */ 823 rasops_unpack_attr(defattr, &fg, &bg, &ul); 824 radeonfb_rectfill(dp, 0, 0, ri->ri_width, ri->ri_height, 825 ri->ri_devcmap[bg & 0xf]); 826 827 dp->rd_wsscreens->textops = &ri->ri_ops; 828 dp->rd_wsscreens->capabilities = ri->ri_caps; 829 dp->rd_wsscreens->nrows = ri->ri_rows; 830 dp->rd_wsscreens->ncols = ri->ri_cols; 831 832 #ifdef SPLASHSCREEN 833 dp->rd_splash.si_depth = ri->ri_depth; 834 dp->rd_splash.si_bits = ri->ri_bits; 835 dp->rd_splash.si_hwbits = ri->ri_hwbits; 836 dp->rd_splash.si_width = ri->ri_width; 837 dp->rd_splash.si_height = ri->ri_height; 838 dp->rd_splash.si_stride = ri->ri_stride; 839 dp->rd_splash.si_fillrect = NULL; 840 #endif 841 if (dp->rd_console) { 842 843 wsdisplay_cnattach(dp->rd_wsscreens, ri, 0, 0, 844 defattr); 845 #ifdef SPLASHSCREEN 846 splash_render(&dp->rd_splash, 847 SPLASH_F_CENTER|SPLASH_F_FILL); 848 #endif 849 850 #ifdef SPLASHSCREEN_PROGRESS 851 dp->rd_progress.sp_top = (dp->rd_virty / 8) * 7; 852 dp->rd_progress.sp_width = (dp->rd_virtx / 4) * 3; 853 dp->rd_progress.sp_left = (dp->rd_virtx - 854 dp->rd_progress.sp_width) / 2; 855 dp->rd_progress.sp_height = 20; 856 dp->rd_progress.sp_state = -1; 857 dp->rd_progress.sp_si = &dp->rd_splash; 858 splash_progress_init(&dp->rd_progress); 859 SCREEN_DISABLE_DRAWING(&dp->rd_vscreen); 860 #endif 861 862 } else { 863 864 /* 865 * since we're not the console we can postpone 866 * the rest until someone actually allocates a 867 * screen for us. but we do clear the screen 868 * at least. 869 */ 870 memset(ri->ri_bits, 0, 1024); 871 872 radeonfb_modeswitch(dp); 873 #ifdef SPLASHSCREEN 874 splash_render(&dp->rd_splash, 875 SPLASH_F_CENTER|SPLASH_F_FILL); 876 SCREEN_DISABLE_DRAWING(&dp->rd_vscreen); 877 #endif 878 } 879 880 aa.console = dp->rd_console; 881 aa.scrdata = &dp->rd_wsscreenlist; 882 aa.accessops = &radeonfb_accessops; 883 aa.accesscookie = &dp->rd_vd; 884 885 config_found(&sc->sc_dev, &aa, wsemuldisplaydevprint); 886 radeonfb_blank(dp, 0); 887 888 /* Initialise delayed lvds operations for backlight. */ 889 callout_init(&dp->rd_bl_lvds_co, 0); 890 callout_setfunc(&dp->rd_bl_lvds_co, 891 radeonfb_lvds_callout, dp); 892 } 893 894 config_found_ia(dev, "drm", aux, radeonfb_drm_print); 895 896 return; 897 898 error: 899 if (sc->sc_biossz) 900 free(sc->sc_bios, M_DEVBUF); 901 902 if (sc->sc_regsz) 903 bus_space_unmap(sc->sc_regt, sc->sc_regh, sc->sc_regsz); 904 905 if (sc->sc_memsz) 906 bus_space_unmap(sc->sc_memt, sc->sc_memh, sc->sc_memsz); 907 } 908 909 static int 910 radeonfb_drm_print(void *aux, const char *pnp) 911 { 912 if (pnp) 913 aprint_normal("direct rendering for %s", pnp); 914 return (UNSUPP); 915 } 916 917 int 918 radeonfb_ioctl(void *v, void *vs, 919 unsigned long cmd, void *d, int flag, struct lwp *l) 920 { 921 struct vcons_data *vd; 922 struct radeonfb_display *dp; 923 struct radeonfb_softc *sc; 924 struct wsdisplay_param *param; 925 926 vd = (struct vcons_data *)v; 927 dp = (struct radeonfb_display *)vd->cookie; 928 sc = dp->rd_softc; 929 930 switch (cmd) { 931 case WSDISPLAYIO_GTYPE: 932 *(unsigned *)d = WSDISPLAY_TYPE_PCIMISC; 933 return 0; 934 935 case WSDISPLAYIO_GINFO: 936 if (vd->active != NULL) { 937 struct wsdisplay_fbinfo *fb; 938 fb = (struct wsdisplay_fbinfo *)d; 939 fb->width = dp->rd_virtx; 940 fb->height = dp->rd_virty; 941 fb->depth = dp->rd_bpp; 942 fb->cmsize = 256; 943 return 0; 944 } else 945 return ENODEV; 946 case WSDISPLAYIO_GVIDEO: 947 if (radeonfb_isblank(dp)) 948 *(unsigned *)d = WSDISPLAYIO_VIDEO_OFF; 949 else 950 *(unsigned *)d = WSDISPLAYIO_VIDEO_ON; 951 return 0; 952 953 case WSDISPLAYIO_SVIDEO: 954 radeonfb_blank(dp, 955 (*(unsigned int *)d == WSDISPLAYIO_VIDEO_OFF)); 956 return 0; 957 958 case WSDISPLAYIO_GETCMAP: 959 #if 0 960 if (dp->rd_bpp == 8) 961 return radeonfb_getcmap(sc, 962 (struct wsdisplay_cmap *)d); 963 #endif 964 return EINVAL; 965 966 case WSDISPLAYIO_PUTCMAP: 967 #if 0 968 if (dp->rd_bpp == 8) 969 return radeonfb_putcmap(sc, 970 (struct wsdisplay_cmap *)d); 971 #endif 972 return EINVAL; 973 974 case WSDISPLAYIO_LINEBYTES: 975 *(unsigned *)d = dp->rd_stride; 976 return 0; 977 978 case WSDISPLAYIO_SMODE: 979 if (*(int *)d != dp->rd_wsmode) { 980 dp->rd_wsmode = *(int *)d; 981 if ((dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) && 982 (dp->rd_vd.active)) { 983 radeonfb_engine_init(dp); 984 radeonfb_modeswitch(dp); 985 vcons_redraw_screen(dp->rd_vd.active); 986 } 987 } 988 return 0; 989 990 case WSDISPLAYIO_GCURMAX: 991 ((struct wsdisplay_curpos *)d)->x = RADEON_CURSORMAXX; 992 ((struct wsdisplay_curpos *)d)->y = RADEON_CURSORMAXY; 993 return 0; 994 995 case WSDISPLAYIO_SCURSOR: 996 return radeonfb_set_cursor(dp, (struct wsdisplay_cursor *)d); 997 998 case WSDISPLAYIO_GCURSOR: 999 return EPASSTHROUGH; 1000 1001 case WSDISPLAYIO_GCURPOS: 1002 ((struct wsdisplay_curpos *)d)->x = dp->rd_cursor.rc_pos.x; 1003 ((struct wsdisplay_curpos *)d)->y = dp->rd_cursor.rc_pos.y; 1004 return 0; 1005 1006 case WSDISPLAYIO_SCURPOS: 1007 return radeonfb_set_curpos(dp, (struct wsdisplay_curpos *)d); 1008 1009 case WSDISPLAYIO_SSPLASH: 1010 #if defined(SPLASHSCREEN) 1011 if (*(int *)d == 1) { 1012 SCREEN_DISABLE_DRAWING(&dp->rd_vscreen); 1013 splash_render(&dp->rd_splash, 1014 SPLASH_F_CENTER|SPLASH_F_FILL); 1015 } else 1016 SCREEN_ENABLE_DRAWING(&dp->rd_vscreen); 1017 return 0; 1018 #else 1019 return ENODEV; 1020 #endif 1021 case WSDISPLAYIO_SPROGRESS: 1022 #if defined(SPLASHSCREEN) && defined(SPLASHSCREEN_PROGRESS) 1023 dp->rd_progress.sp_force = 1; 1024 splash_progress_update(&dp->rd_progress); 1025 dp->rd_progress.sp_force = 0; 1026 return 0; 1027 #else 1028 return ENODEV; 1029 #endif 1030 case WSDISPLAYIO_GETPARAM: 1031 param = (struct wsdisplay_param *)d; 1032 if (param->param == WSDISPLAYIO_PARAM_BACKLIGHT) { 1033 param->min = 0; 1034 param->max = RADEONFB_BACKLIGHT_MAX; 1035 param->curval = radeonfb_get_backlight(dp); 1036 return 0; 1037 } 1038 return EPASSTHROUGH; 1039 1040 case WSDISPLAYIO_SETPARAM: 1041 param = (struct wsdisplay_param *)d; 1042 if (param->param == WSDISPLAYIO_PARAM_BACKLIGHT) { 1043 return radeonfb_set_backlight(dp, param->curval); 1044 } 1045 return EPASSTHROUGH; 1046 1047 default: 1048 return EPASSTHROUGH; 1049 } 1050 } 1051 1052 paddr_t 1053 radeonfb_mmap(void *v, void *vs, off_t offset, int prot) 1054 { 1055 struct vcons_data *vd; 1056 struct radeonfb_display *dp; 1057 struct radeonfb_softc *sc; 1058 #ifdef RADEONFB_MMAP_BARS 1059 struct lwp *me; 1060 #endif 1061 paddr_t pa; 1062 1063 vd = (struct vcons_data *)v; 1064 dp = (struct radeonfb_display *)vd->cookie; 1065 sc = dp->rd_softc; 1066 1067 /* XXX: note that we don't allow mapping of registers right now */ 1068 /* XXX: this means that the XFree86 radeon driver won't work */ 1069 1070 if ((offset >= 0) && (offset < (dp->rd_virty * dp->rd_stride))) { 1071 pa = bus_space_mmap(sc->sc_memt, 1072 sc->sc_memaddr + dp->rd_offset + offset, 0, 1073 prot, BUS_SPACE_MAP_LINEAR); 1074 return pa; 1075 } 1076 1077 #ifdef RADEONFB_MMAP_BARS 1078 /* 1079 * restrict all other mappings to processes with superuser privileges 1080 * or the kernel itself 1081 */ 1082 me = curlwp; 1083 if (me != NULL) { 1084 if (kauth_authorize_generic(me->l_cred, KAUTH_GENERIC_ISSUSER, 1085 NULL) != 0) { 1086 printf("%s: mmap() rejected.\n", sc->sc_dev.dv_xname); 1087 return -1; 1088 } 1089 } 1090 1091 if ((offset >= sc->sc_regaddr) && 1092 (offset < sc->sc_regaddr + sc->sc_regsz)) { 1093 return bus_space_mmap(sc->sc_regt, offset, 0, prot, 1094 BUS_SPACE_MAP_LINEAR); 1095 } 1096 1097 if ((offset >= sc->sc_memaddr) && 1098 (offset < sc->sc_memaddr + sc->sc_memsz)) { 1099 return bus_space_mmap(sc->sc_memt, offset, 0, prot, 1100 BUS_SPACE_MAP_LINEAR); 1101 } 1102 1103 #ifdef PCI_MAGIC_IO_RANGE 1104 /* allow mapping of IO space */ 1105 if ((offset >= PCI_MAGIC_IO_RANGE) && 1106 (offset < PCI_MAGIC_IO_RANGE + 0x10000)) { 1107 pa = bus_space_mmap(sc->sc_iot, offset - PCI_MAGIC_IO_RANGE, 1108 0, prot, 0); 1109 return pa; 1110 } 1111 #endif /* macppc */ 1112 1113 #endif /* RADEONFB_MMAP_BARS */ 1114 1115 return -1; 1116 } 1117 1118 static void 1119 radeonfb_loadbios(struct radeonfb_softc *sc, struct pci_attach_args *pa) 1120 { 1121 bus_space_tag_t romt; 1122 bus_space_handle_t romh, biosh; 1123 bus_size_t romsz; 1124 bus_addr_t ptr; 1125 1126 if (pci_mapreg_map(pa, PCI_MAPREG_ROM, PCI_MAPREG_TYPE_ROM, 1127 BUS_SPACE_MAP_PREFETCHABLE, &romt, &romh, NULL, &romsz) != 0) { 1128 aprint_verbose("%s: unable to map BIOS!\n", XNAME(sc)); 1129 return; 1130 } 1131 1132 pci_find_rom(pa, romt, romh, PCI_ROM_CODE_TYPE_X86, &biosh, 1133 &sc->sc_biossz); 1134 if (sc->sc_biossz == 0) { 1135 aprint_verbose("%s: Video BIOS not present\n", XNAME(sc)); 1136 return; 1137 } 1138 1139 sc->sc_bios = malloc(sc->sc_biossz, M_DEVBUF, M_WAITOK); 1140 bus_space_read_region_1(romt, biosh, 0, sc->sc_bios, sc->sc_biossz); 1141 1142 /* unmap the PCI expansion rom */ 1143 bus_space_unmap(romt, romh, romsz); 1144 1145 /* turn off rom decoder now */ 1146 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM, 1147 pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM) & 1148 ~PCI_MAPREG_ROM_ENABLE); 1149 1150 ptr = GETBIOS16(sc, 0x48); 1151 if ((GETBIOS32(sc, ptr + 4) == 0x41544f4d /* "ATOM" */) || 1152 (GETBIOS32(sc, ptr + 4) == 0x4d4f5441 /* "MOTA" */)) { 1153 sc->sc_flags |= RFB_ATOM; 1154 } 1155 1156 aprint_verbose("%s: Found %d KB %s BIOS\n", XNAME(sc), 1157 (unsigned)sc->sc_biossz >> 10, IS_ATOM(sc) ? "ATOM" : "Legacy"); 1158 } 1159 1160 1161 uint32_t 1162 radeonfb_get32(struct radeonfb_softc *sc, uint32_t reg) 1163 { 1164 1165 return bus_space_read_4(sc->sc_regt, sc->sc_regh, reg); 1166 } 1167 1168 void 1169 radeonfb_put32(struct radeonfb_softc *sc, uint32_t reg, uint32_t val) 1170 { 1171 1172 bus_space_write_4(sc->sc_regt, sc->sc_regh, reg, val); 1173 } 1174 1175 void 1176 radeonfb_mask32(struct radeonfb_softc *sc, uint32_t reg, 1177 uint32_t andmask, uint32_t ormask) 1178 { 1179 int s; 1180 uint32_t val; 1181 1182 s = splhigh(); 1183 val = radeonfb_get32(sc, reg); 1184 val = (val & andmask) | ormask; 1185 radeonfb_put32(sc, reg, val); 1186 splx(s); 1187 } 1188 1189 uint32_t 1190 radeonfb_getindex(struct radeonfb_softc *sc, uint32_t idx) 1191 { 1192 int s; 1193 uint32_t val; 1194 1195 s = splhigh(); 1196 radeonfb_put32(sc, RADEON_MM_INDEX, idx); 1197 val = radeonfb_get32(sc, RADEON_MM_DATA); 1198 splx(s); 1199 1200 return (val); 1201 } 1202 1203 void 1204 radeonfb_putindex(struct radeonfb_softc *sc, uint32_t idx, uint32_t val) 1205 { 1206 int s; 1207 1208 s = splhigh(); 1209 radeonfb_put32(sc, RADEON_MM_INDEX, idx); 1210 radeonfb_put32(sc, RADEON_MM_DATA, val); 1211 splx(s); 1212 } 1213 1214 void 1215 radeonfb_maskindex(struct radeonfb_softc *sc, uint32_t idx, 1216 uint32_t andmask, uint32_t ormask) 1217 { 1218 int s; 1219 uint32_t val; 1220 1221 s = splhigh(); 1222 radeonfb_put32(sc, RADEON_MM_INDEX, idx); 1223 val = radeonfb_get32(sc, RADEON_MM_DATA); 1224 val = (val & andmask) | ormask; 1225 radeonfb_put32(sc, RADEON_MM_DATA, val); 1226 splx(s); 1227 } 1228 1229 uint32_t 1230 radeonfb_getpll(struct radeonfb_softc *sc, uint32_t idx) 1231 { 1232 int s; 1233 uint32_t val; 1234 1235 s = splhigh(); 1236 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, idx & 0x3f); 1237 val = radeonfb_get32(sc, RADEON_CLOCK_CNTL_DATA); 1238 if (HAS_R300CG(sc)) 1239 radeonfb_r300cg_workaround(sc); 1240 splx(s); 1241 1242 return (val); 1243 } 1244 1245 void 1246 radeonfb_putpll(struct radeonfb_softc *sc, uint32_t idx, uint32_t val) 1247 { 1248 int s; 1249 1250 s = splhigh(); 1251 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, (idx & 0x3f) | 1252 RADEON_PLL_WR_EN); 1253 radeonfb_put32(sc, RADEON_CLOCK_CNTL_DATA, val); 1254 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, 0); 1255 splx(s); 1256 } 1257 1258 void 1259 radeonfb_maskpll(struct radeonfb_softc *sc, uint32_t idx, 1260 uint32_t andmask, uint32_t ormask) 1261 { 1262 int s; 1263 uint32_t val; 1264 1265 s = splhigh(); 1266 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, (idx & 0x3f) | 1267 RADEON_PLL_WR_EN); 1268 val = radeonfb_get32(sc, RADEON_CLOCK_CNTL_DATA); 1269 val = (val & andmask) | ormask; 1270 radeonfb_put32(sc, RADEON_CLOCK_CNTL_DATA, val); 1271 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, 0); 1272 splx(s); 1273 } 1274 1275 int 1276 radeonfb_scratch_test(struct radeonfb_softc *sc, int reg, uint32_t v) 1277 { 1278 uint32_t saved; 1279 1280 saved = GET32(sc, reg); 1281 PUT32(sc, reg, v); 1282 if (GET32(sc, reg) != v) { 1283 return -1; 1284 } 1285 PUT32(sc, reg, saved); 1286 return 0; 1287 } 1288 1289 uintmax_t 1290 radeonfb_getprop_num(struct radeonfb_softc *sc, const char *name, 1291 uintmax_t defval) 1292 { 1293 prop_number_t pn; 1294 pn = prop_dictionary_get(device_properties(&sc->sc_dev), name); 1295 if (pn == NULL) { 1296 return defval; 1297 } 1298 KASSERT(prop_object_type(pn) == PROP_TYPE_NUMBER); 1299 return (prop_number_integer_value(pn)); 1300 } 1301 1302 int 1303 radeonfb_getclocks(struct radeonfb_softc *sc) 1304 { 1305 bus_addr_t ptr; 1306 int refclk = 0; 1307 int refdiv = 0; 1308 int minpll = 0; 1309 int maxpll = 0; 1310 1311 /* load initial property values if port/board provides them */ 1312 refclk = radeonfb_getprop_num(sc, "refclk", 0) & 0xffff; 1313 refdiv = radeonfb_getprop_num(sc, "refdiv", 0) & 0xffff; 1314 minpll = radeonfb_getprop_num(sc, "minpll", 0) & 0xffffffffU; 1315 maxpll = radeonfb_getprop_num(sc, "maxpll", 0) & 0xffffffffU; 1316 1317 if (refclk && refdiv && minpll && maxpll) 1318 goto dontprobe; 1319 1320 if (!sc->sc_biossz) { 1321 /* no BIOS */ 1322 aprint_verbose("%s: No video BIOS, using default clocks\n", 1323 XNAME(sc)); 1324 if (IS_IGP(sc)) 1325 refclk = refclk ? refclk : 1432; 1326 else 1327 refclk = refclk ? refclk : 2700; 1328 refdiv = refdiv ? refdiv : 12; 1329 minpll = minpll ? minpll : 12500; 1330 maxpll = maxpll ? maxpll : 35000; 1331 } else if (IS_ATOM(sc)) { 1332 /* ATOM BIOS */ 1333 ptr = GETBIOS16(sc, 0x48); 1334 ptr = GETBIOS16(sc, ptr + 32); /* aka MasterDataStart */ 1335 ptr = GETBIOS16(sc, ptr + 12); /* pll info block */ 1336 refclk = refclk ? refclk : GETBIOS16(sc, ptr + 82); 1337 minpll = minpll ? minpll : GETBIOS16(sc, ptr + 78); 1338 maxpll = maxpll ? maxpll : GETBIOS16(sc, ptr + 32); 1339 /* 1340 * ATOM BIOS doesn't supply a reference divider, so we 1341 * have to probe for it. 1342 */ 1343 if (refdiv < 2) 1344 refdiv = GETPLL(sc, RADEON_PPLL_REF_DIV) & 1345 RADEON_PPLL_REF_DIV_MASK; 1346 /* 1347 * if probe is zero, just assume one that should work 1348 * for most parts 1349 */ 1350 if (refdiv < 2) 1351 refdiv = 12; 1352 1353 } else { 1354 /* Legacy BIOS */ 1355 ptr = GETBIOS16(sc, 0x48); 1356 ptr = GETBIOS16(sc, ptr + 0x30); 1357 refclk = refclk ? refclk : GETBIOS16(sc, ptr + 0x0E); 1358 refdiv = refdiv ? refdiv : GETBIOS16(sc, ptr + 0x10); 1359 minpll = minpll ? minpll : GETBIOS32(sc, ptr + 0x12); 1360 maxpll = maxpll ? maxpll : GETBIOS32(sc, ptr + 0x16); 1361 } 1362 1363 1364 dontprobe: 1365 sc->sc_refclk = refclk * 10; 1366 sc->sc_refdiv = refdiv; 1367 sc->sc_minpll = minpll * 10; 1368 sc->sc_maxpll = maxpll * 10; 1369 return 0; 1370 } 1371 1372 int 1373 radeonfb_calc_dividers(struct radeonfb_softc *sc, uint32_t dotclock, 1374 uint32_t *postdivbit, uint32_t *feedbackdiv) 1375 { 1376 int i; 1377 uint32_t outfreq; 1378 int div; 1379 1380 DPRINTF(("dot clock: %u\n", dotclock)); 1381 for (i = 0; (div = radeonfb_dividers[i].divider) != 0; i++) { 1382 outfreq = div * dotclock; 1383 if ((outfreq >= sc->sc_minpll) && 1384 (outfreq <= sc->sc_maxpll)) { 1385 DPRINTF(("outfreq: %u\n", outfreq)); 1386 *postdivbit = 1387 ((uint32_t)radeonfb_dividers[i].mask << 16); 1388 DPRINTF(("post divider: %d (mask %x)\n", div, 1389 *postdivbit)); 1390 break; 1391 } 1392 } 1393 1394 if (div == 0) 1395 return 1; 1396 1397 *feedbackdiv = DIVIDE(sc->sc_refdiv * outfreq, sc->sc_refclk); 1398 DPRINTF(("feedback divider: %d\n", *feedbackdiv)); 1399 return 0; 1400 } 1401 1402 #if 0 1403 #ifdef RADEON_DEBUG 1404 static void 1405 dump_buffer(const char *pfx, void *buffer, unsigned int size) 1406 { 1407 char asc[17]; 1408 unsigned ptr = (unsigned)buffer; 1409 char *start = (char *)(ptr & ~0xf); 1410 char *end = (char *)(ptr + size); 1411 1412 end = (char *)(((unsigned)end + 0xf) & ~0xf); 1413 1414 if (pfx == NULL) { 1415 pfx = ""; 1416 } 1417 1418 while (start < end) { 1419 unsigned offset = (unsigned)start & 0xf; 1420 if (offset == 0) { 1421 printf("%s%x: ", pfx, (unsigned)start); 1422 } 1423 if (((unsigned)start < ptr) || 1424 ((unsigned)start >= (ptr + size))) { 1425 printf(" "); 1426 asc[offset] = ' '; 1427 } else { 1428 printf("%02x", *(unsigned char *)start); 1429 if ((*start >= ' ') && (*start <= '~')) { 1430 asc[offset] = *start; 1431 } else { 1432 asc[offset] = '.'; 1433 } 1434 } 1435 asc[offset + 1] = 0; 1436 if (offset % 2) { 1437 printf(" "); 1438 } 1439 if (offset == 15) { 1440 printf(" %s\n", asc); 1441 } 1442 start++; 1443 } 1444 } 1445 #endif 1446 #endif 1447 1448 int 1449 radeonfb_getconnectors(struct radeonfb_softc *sc) 1450 { 1451 int i; 1452 int found = 0; 1453 1454 for (i = 0; i < 2; i++) { 1455 sc->sc_ports[i].rp_mon_type = RADEON_MT_UNKNOWN; 1456 sc->sc_ports[i].rp_ddc_type = RADEON_DDC_NONE; 1457 sc->sc_ports[i].rp_dac_type = RADEON_DAC_UNKNOWN; 1458 sc->sc_ports[i].rp_conn_type = RADEON_CONN_NONE; 1459 sc->sc_ports[i].rp_tmds_type = RADEON_TMDS_UNKNOWN; 1460 } 1461 1462 /* 1463 * This logic is borrowed from Xorg's radeon driver. 1464 */ 1465 if (!sc->sc_biossz) 1466 goto nobios; 1467 1468 if (IS_ATOM(sc)) { 1469 /* not done yet */ 1470 } else { 1471 uint16_t ptr; 1472 int port = 0; 1473 1474 ptr = GETBIOS16(sc, 0x48); 1475 ptr = GETBIOS16(sc, ptr + 0x50); 1476 for (i = 1; i < 4; i++) { 1477 uint16_t entry; 1478 uint8_t conn, ddc, dac, tmds; 1479 1480 /* 1481 * Parse the connector table. From reading the code, 1482 * it appears to made up of 16-bit entries for each 1483 * connector. The 16-bits are defined as: 1484 * 1485 * bits 12-15 - connector type (0 == end of table) 1486 * bits 8-11 - DDC type 1487 * bits 5-7 - ??? 1488 * bit 4 - TMDS type (1 = EXT, 0 = INT) 1489 * bits 1-3 - ??? 1490 * bit 0 - DAC, 1 = TVDAC, 0 = primary 1491 */ 1492 if (!GETBIOS8(sc, ptr + i * 2) && i > 1) 1493 break; 1494 entry = GETBIOS16(sc, ptr + i * 2); 1495 1496 conn = (entry >> 12) & 0xf; 1497 ddc = (entry >> 8) & 0xf; 1498 dac = (entry & 0x1) ? RADEON_DAC_TVDAC : 1499 RADEON_DAC_PRIMARY; 1500 tmds = ((entry >> 4) & 0x1) ? RADEON_TMDS_EXT : 1501 RADEON_TMDS_INT; 1502 1503 if (conn == RADEON_CONN_NONE) 1504 continue; /* no connector */ 1505 1506 if ((found > 0) && 1507 (sc->sc_ports[port].rp_ddc_type == ddc)) { 1508 /* duplicate entry for same connector */ 1509 continue; 1510 } 1511 1512 /* internal DDC_DVI port gets priority */ 1513 if ((ddc == RADEON_DDC_DVI) || (port == 1)) 1514 port = 0; 1515 else 1516 port = 1; 1517 1518 sc->sc_ports[port].rp_ddc_type = 1519 ddc > RADEON_DDC_CRT2 ? RADEON_DDC_NONE : ddc; 1520 sc->sc_ports[port].rp_dac_type = dac; 1521 sc->sc_ports[port].rp_conn_type = 1522 min(conn, RADEON_CONN_UNSUPPORTED) ; 1523 1524 sc->sc_ports[port].rp_tmds_type = tmds; 1525 1526 if ((conn != RADEON_CONN_DVI_I) && 1527 (conn != RADEON_CONN_DVI_D) && 1528 (tmds == RADEON_TMDS_INT)) 1529 sc->sc_ports[port].rp_tmds_type = 1530 RADEON_TMDS_UNKNOWN; 1531 1532 found += (port + 1); 1533 } 1534 } 1535 1536 nobios: 1537 if (!found) { 1538 DPRINTF(("No connector info in BIOS!\n")); 1539 /* default, port 0 = internal TMDS, port 1 = CRT */ 1540 sc->sc_ports[0].rp_mon_type = RADEON_MT_UNKNOWN; 1541 sc->sc_ports[0].rp_ddc_type = RADEON_DDC_DVI; 1542 sc->sc_ports[0].rp_dac_type = RADEON_DAC_TVDAC; 1543 sc->sc_ports[0].rp_conn_type = RADEON_CONN_DVI_D; 1544 sc->sc_ports[0].rp_tmds_type = RADEON_TMDS_INT; 1545 1546 sc->sc_ports[1].rp_mon_type = RADEON_MT_UNKNOWN; 1547 sc->sc_ports[1].rp_ddc_type = RADEON_DDC_VGA; 1548 sc->sc_ports[1].rp_dac_type = RADEON_DAC_PRIMARY; 1549 sc->sc_ports[1].rp_conn_type = RADEON_CONN_CRT; 1550 sc->sc_ports[1].rp_tmds_type = RADEON_TMDS_EXT; 1551 } 1552 1553 /* 1554 * Fixup for RS300/RS350/RS400 chips, that lack a primary DAC. 1555 * these chips should use TVDAC for the VGA port. 1556 */ 1557 if (HAS_SDAC(sc)) { 1558 if (sc->sc_ports[0].rp_conn_type == RADEON_CONN_CRT) { 1559 sc->sc_ports[0].rp_dac_type = RADEON_DAC_TVDAC; 1560 sc->sc_ports[1].rp_dac_type = RADEON_DAC_PRIMARY; 1561 } else { 1562 sc->sc_ports[1].rp_dac_type = RADEON_DAC_TVDAC; 1563 sc->sc_ports[0].rp_dac_type = RADEON_DAC_PRIMARY; 1564 } 1565 } else if (!HAS_CRTC2(sc)) { 1566 sc->sc_ports[0].rp_dac_type = RADEON_DAC_PRIMARY; 1567 } 1568 1569 for (i = 0; i < 2; i++) { 1570 char edid[128]; 1571 uint8_t ddc; 1572 struct edid_info *eip = &sc->sc_ports[i].rp_edid; 1573 prop_data_t edid_data; 1574 1575 DPRINTF(("Port #%d:\n", i)); 1576 DPRINTF((" conn = %d\n", sc->sc_ports[i].rp_conn_type)); 1577 DPRINTF((" ddc = %d\n", sc->sc_ports[i].rp_ddc_type)); 1578 DPRINTF((" dac = %d\n", sc->sc_ports[i].rp_dac_type)); 1579 DPRINTF((" tmds = %d\n", sc->sc_ports[i].rp_tmds_type)); 1580 1581 sc->sc_ports[i].rp_edid_valid = 0; 1582 /* first look for static EDID data */ 1583 if ((edid_data = prop_dictionary_get(device_properties( 1584 &sc->sc_dev), "EDID")) != NULL) { 1585 1586 aprint_normal("%s: using static EDID\n", 1587 sc->sc_dev.dv_xname); 1588 memcpy(edid, prop_data_data_nocopy(edid_data), 128); 1589 if (edid_parse(edid, eip) == 0) { 1590 1591 sc->sc_ports[i].rp_edid_valid = 1; 1592 edid_print(eip); 1593 } 1594 } 1595 /* if we didn't find any we'll try to talk to the monitor */ 1596 if (sc->sc_ports[i].rp_edid_valid != 1) { 1597 1598 ddc = sc->sc_ports[i].rp_ddc_type; 1599 if (ddc != RADEON_DDC_NONE) { 1600 if ((radeonfb_i2c_read_edid(sc, ddc, edid) 1601 == 0) && (edid_parse(edid, eip) == 0)) { 1602 1603 sc->sc_ports[i].rp_edid_valid = 1; 1604 edid_print(eip); 1605 } 1606 } 1607 } 1608 } 1609 1610 return found; 1611 } 1612 1613 int 1614 radeonfb_gettmds(struct radeonfb_softc *sc) 1615 { 1616 int i; 1617 1618 if (!sc->sc_biossz) { 1619 goto nobios; 1620 } 1621 1622 if (IS_ATOM(sc)) { 1623 /* XXX: not done yet */ 1624 } else { 1625 uint16_t ptr; 1626 int n; 1627 1628 ptr = GETBIOS16(sc, 0x48); 1629 ptr = GETBIOS16(sc, ptr + 0x34); 1630 DPRINTF(("DFP table revision %d\n", GETBIOS8(sc, ptr))); 1631 if (GETBIOS8(sc, ptr) == 3) { 1632 /* revision three table */ 1633 n = GETBIOS8(sc, ptr + 5) + 1; 1634 n = min(n, 4); 1635 1636 memset(sc->sc_tmds_pll, 0, sizeof (sc->sc_tmds_pll)); 1637 for (i = 0; i < n; i++) { 1638 sc->sc_tmds_pll[i].rtp_pll = GETBIOS32(sc, 1639 ptr + i * 10 + 8); 1640 sc->sc_tmds_pll[i].rtp_freq = GETBIOS16(sc, 1641 ptr + i * 10 + 0x10); 1642 DPRINTF(("TMDS_PLL dot clock %d pll %x\n", 1643 sc->sc_tmds_pll[i].rtp_freq, 1644 sc->sc_tmds_pll[i].rtp_pll)); 1645 } 1646 return 0; 1647 } 1648 } 1649 1650 nobios: 1651 DPRINTF(("no suitable DFP table present\n")); 1652 for (i = 0; 1653 i < sizeof (radeonfb_tmds_pll) / sizeof (radeonfb_tmds_pll[0]); 1654 i++) { 1655 int j; 1656 1657 if (radeonfb_tmds_pll[i].family != sc->sc_family) 1658 continue; 1659 1660 for (j = 0; j < 4; j++) { 1661 sc->sc_tmds_pll[j] = radeonfb_tmds_pll[i].plls[j]; 1662 DPRINTF(("TMDS_PLL dot clock %d pll %x\n", 1663 sc->sc_tmds_pll[j].rtp_freq, 1664 sc->sc_tmds_pll[j].rtp_pll)); 1665 } 1666 return 0; 1667 } 1668 1669 return -1; 1670 } 1671 1672 const struct videomode * 1673 radeonfb_modelookup(const char *name) 1674 { 1675 int i; 1676 1677 for (i = 0; i < videomode_count; i++) 1678 if (!strcmp(name, videomode_list[i].name)) 1679 return &videomode_list[i]; 1680 1681 return NULL; 1682 } 1683 1684 void 1685 radeonfb_pllwriteupdate(struct radeonfb_softc *sc, int crtc) 1686 { 1687 if (crtc) { 1688 while (GETPLL(sc, RADEON_P2PLL_REF_DIV) & 1689 RADEON_P2PLL_ATOMIC_UPDATE_R); 1690 SETPLL(sc, RADEON_P2PLL_REF_DIV, RADEON_P2PLL_ATOMIC_UPDATE_W); 1691 } else { 1692 while (GETPLL(sc, RADEON_PPLL_REF_DIV) & 1693 RADEON_PPLL_ATOMIC_UPDATE_R); 1694 SETPLL(sc, RADEON_PPLL_REF_DIV, RADEON_PPLL_ATOMIC_UPDATE_W); 1695 } 1696 } 1697 1698 void 1699 radeonfb_pllwaitatomicread(struct radeonfb_softc *sc, int crtc) 1700 { 1701 int i; 1702 1703 for (i = 10000; i; i--) { 1704 if (crtc) { 1705 if (GETPLL(sc, RADEON_P2PLL_REF_DIV) & 1706 RADEON_P2PLL_ATOMIC_UPDATE_R) 1707 break; 1708 } else { 1709 if (GETPLL(sc, RADEON_PPLL_REF_DIV) & 1710 RADEON_PPLL_ATOMIC_UPDATE_R) 1711 break; 1712 } 1713 } 1714 } 1715 1716 void 1717 radeonfb_program_vclk(struct radeonfb_softc *sc, int dotclock, int crtc) 1718 { 1719 uint32_t pbit = 0; 1720 uint32_t feed = 0; 1721 uint32_t data; 1722 #if 1 1723 int i; 1724 #endif 1725 1726 radeonfb_calc_dividers(sc, dotclock, &pbit, &feed); 1727 1728 if (crtc == 0) { 1729 1730 /* XXXX: mobility workaround missing */ 1731 /* XXXX: R300 stuff missing */ 1732 1733 PATCHPLL(sc, RADEON_VCLK_ECP_CNTL, 1734 RADEON_VCLK_SRC_SEL_CPUCLK, 1735 ~RADEON_VCLK_SRC_SEL_MASK); 1736 1737 /* put vclk into reset, use atomic updates */ 1738 SETPLL(sc, RADEON_PPLL_CNTL, 1739 RADEON_PPLL_REFCLK_SEL | 1740 RADEON_PPLL_FBCLK_SEL | 1741 RADEON_PPLL_RESET | 1742 RADEON_PPLL_ATOMIC_UPDATE_EN | 1743 RADEON_PPLL_VGA_ATOMIC_UPDATE_EN); 1744 1745 /* select clock 3 */ 1746 #if 0 1747 PATCH32(sc, RADEON_CLOCK_CNTL_INDEX, RADEON_PLL_DIV_SEL, 1748 ~RADEON_PLL_DIV_SEL); 1749 #else 1750 PATCH32(sc, RADEON_CLOCK_CNTL_INDEX, 0, 1751 ~RADEON_PLL_DIV_SEL); 1752 #endif 1753 1754 /* XXX: R300 family -- program divider differently? */ 1755 1756 /* program reference divider */ 1757 PATCHPLL(sc, RADEON_PPLL_REF_DIV, sc->sc_refdiv, 1758 ~RADEON_PPLL_REF_DIV_MASK); 1759 PRINTPLL(RADEON_PPLL_REF_DIV); 1760 1761 #if 0 1762 data = GETPLL(sc, RADEON_PPLL_DIV_3); 1763 data &= ~(RADEON_PPLL_FB3_DIV_MASK | 1764 RADEON_PPLL_POST3_DIV_MASK); 1765 data |= pbit; 1766 data |= (feed & RADEON_PPLL_FB3_DIV_MASK); 1767 PUTPLL(sc, RADEON_PPLL_DIV_3, data); 1768 #else 1769 for (i = 0; i < 4; i++) { 1770 } 1771 #endif 1772 1773 /* use the atomic update */ 1774 radeonfb_pllwriteupdate(sc, crtc); 1775 1776 /* and wait for it to complete */ 1777 radeonfb_pllwaitatomicread(sc, crtc); 1778 1779 /* program HTOTAL (why?) */ 1780 PUTPLL(sc, RADEON_HTOTAL_CNTL, 0); 1781 1782 /* drop reset */ 1783 CLRPLL(sc, RADEON_PPLL_CNTL, 1784 RADEON_PPLL_RESET | RADEON_PPLL_SLEEP | 1785 RADEON_PPLL_ATOMIC_UPDATE_EN | 1786 RADEON_PPLL_VGA_ATOMIC_UPDATE_EN); 1787 1788 PRINTPLL(RADEON_PPLL_CNTL); 1789 1790 /* give clock time to lock */ 1791 delay(50000); 1792 1793 PATCHPLL(sc, RADEON_VCLK_ECP_CNTL, 1794 RADEON_VCLK_SRC_SEL_PPLLCLK, 1795 ~RADEON_VCLK_SRC_SEL_MASK); 1796 1797 } else { 1798 1799 PATCHPLL(sc, RADEON_PIXCLKS_CNTL, 1800 RADEON_PIX2CLK_SRC_SEL_CPUCLK, 1801 ~RADEON_PIX2CLK_SRC_SEL_MASK); 1802 1803 /* put vclk into reset, use atomic updates */ 1804 SETPLL(sc, RADEON_P2PLL_CNTL, 1805 RADEON_P2PLL_RESET | 1806 RADEON_P2PLL_ATOMIC_UPDATE_EN | 1807 RADEON_P2PLL_VGA_ATOMIC_UPDATE_EN); 1808 1809 /* XXX: R300 family -- program divider differently? */ 1810 1811 /* program reference divider */ 1812 PATCHPLL(sc, RADEON_P2PLL_REF_DIV, sc->sc_refdiv, 1813 ~RADEON_P2PLL_REF_DIV_MASK); 1814 1815 /* program feedback and post dividers */ 1816 data = GETPLL(sc, RADEON_P2PLL_DIV_0); 1817 data &= ~(RADEON_P2PLL_FB0_DIV_MASK | 1818 RADEON_P2PLL_POST0_DIV_MASK); 1819 data |= pbit; 1820 data |= (feed & RADEON_P2PLL_FB0_DIV_MASK); 1821 PUTPLL(sc, RADEON_P2PLL_DIV_0, data); 1822 1823 /* use the atomic update */ 1824 radeonfb_pllwriteupdate(sc, crtc); 1825 1826 /* and wait for it to complete */ 1827 radeonfb_pllwaitatomicread(sc, crtc); 1828 1829 /* program HTOTAL (why?) */ 1830 PUTPLL(sc, RADEON_HTOTAL2_CNTL, 0); 1831 1832 /* drop reset */ 1833 CLRPLL(sc, RADEON_P2PLL_CNTL, 1834 RADEON_P2PLL_RESET | RADEON_P2PLL_SLEEP | 1835 RADEON_P2PLL_ATOMIC_UPDATE_EN | 1836 RADEON_P2PLL_VGA_ATOMIC_UPDATE_EN); 1837 1838 /* allow time for clock to lock */ 1839 delay(50000); 1840 1841 PATCHPLL(sc, RADEON_PIXCLKS_CNTL, 1842 RADEON_PIX2CLK_SRC_SEL_P2PLLCLK, 1843 ~RADEON_PIX2CLK_SRC_SEL_MASK); 1844 } 1845 PRINTREG(RADEON_CRTC_MORE_CNTL); 1846 } 1847 1848 void 1849 radeonfb_modeswitch(struct radeonfb_display *dp) 1850 { 1851 struct radeonfb_softc *sc = dp->rd_softc; 1852 int i; 1853 1854 /* blank the display while we switch modes */ 1855 //radeonfb_blank(dp, 1); 1856 1857 #if 0 1858 SET32(sc, RADEON_CRTC_EXT_CNTL, 1859 RADEON_CRTC_VSYNC_DIS | RADEON_CRTC_HSYNC_DIS | 1860 RADEON_CRTC_DISPLAY_DIS /* | RADEON_CRTC_DISP_REQ_EN_B */); 1861 #endif 1862 1863 /* these registers might get in the way... */ 1864 PUT32(sc, RADEON_OVR_CLR, 0); 1865 PUT32(sc, RADEON_OVR_WID_LEFT_RIGHT, 0); 1866 PUT32(sc, RADEON_OVR_WID_TOP_BOTTOM, 0); 1867 PUT32(sc, RADEON_OV0_SCALE_CNTL, 0); 1868 PUT32(sc, RADEON_SUBPIC_CNTL, 0); 1869 PUT32(sc, RADEON_VIPH_CONTROL, 0); 1870 PUT32(sc, RADEON_I2C_CNTL_1, 0); 1871 PUT32(sc, RADEON_GEN_INT_CNTL, 0); 1872 PUT32(sc, RADEON_CAP0_TRIG_CNTL, 0); 1873 PUT32(sc, RADEON_CAP1_TRIG_CNTL, 0); 1874 PUT32(sc, RADEON_SURFACE_CNTL, 0); 1875 1876 for (i = 0; i < dp->rd_ncrtcs; i++) 1877 radeonfb_setcrtc(dp, i); 1878 1879 /* activate the display */ 1880 //radeonfb_blank(dp, 0); 1881 } 1882 1883 void 1884 radeonfb_setcrtc(struct radeonfb_display *dp, int index) 1885 { 1886 int crtc; 1887 struct videomode *mode; 1888 struct radeonfb_softc *sc; 1889 struct radeonfb_crtc *cp; 1890 uint32_t v; 1891 uint32_t gencntl; 1892 uint32_t htotaldisp; 1893 uint32_t hsyncstrt; 1894 uint32_t vtotaldisp; 1895 uint32_t vsyncstrt; 1896 uint32_t fphsyncstrt; 1897 uint32_t fpvsyncstrt; 1898 uint32_t fphtotaldisp; 1899 uint32_t fpvtotaldisp; 1900 uint32_t pitch; 1901 1902 sc = dp->rd_softc; 1903 cp = &dp->rd_crtcs[index]; 1904 crtc = cp->rc_number; 1905 mode = &cp->rc_videomode; 1906 1907 #if 1 1908 pitch = (((dp->rd_virtx * dp->rd_bpp) + ((dp->rd_bpp * 8) - 1)) / 1909 (dp->rd_bpp * 8)); 1910 #else 1911 pitch = (((sc->sc_maxx * sc->sc_maxbpp) + ((sc->sc_maxbpp * 8) - 1)) / 1912 (sc->sc_maxbpp * 8)); 1913 #endif 1914 //pitch = pitch | (pitch << 16); 1915 1916 switch (crtc) { 1917 case 0: 1918 gencntl = RADEON_CRTC_GEN_CNTL; 1919 htotaldisp = RADEON_CRTC_H_TOTAL_DISP; 1920 hsyncstrt = RADEON_CRTC_H_SYNC_STRT_WID; 1921 vtotaldisp = RADEON_CRTC_V_TOTAL_DISP; 1922 vsyncstrt = RADEON_CRTC_V_SYNC_STRT_WID; 1923 fpvsyncstrt = RADEON_FP_V_SYNC_STRT_WID; 1924 fphsyncstrt = RADEON_FP_H_SYNC_STRT_WID; 1925 fpvtotaldisp = RADEON_FP_CRTC_V_TOTAL_DISP; 1926 fphtotaldisp = RADEON_FP_CRTC_H_TOTAL_DISP; 1927 break; 1928 case 1: 1929 gencntl = RADEON_CRTC2_GEN_CNTL; 1930 htotaldisp = RADEON_CRTC2_H_TOTAL_DISP; 1931 hsyncstrt = RADEON_CRTC2_H_SYNC_STRT_WID; 1932 vtotaldisp = RADEON_CRTC2_V_TOTAL_DISP; 1933 vsyncstrt = RADEON_CRTC2_V_SYNC_STRT_WID; 1934 fpvsyncstrt = RADEON_FP_V2_SYNC_STRT_WID; 1935 fphsyncstrt = RADEON_FP_H2_SYNC_STRT_WID; 1936 fpvtotaldisp = RADEON_FP_CRTC2_V_TOTAL_DISP; 1937 fphtotaldisp = RADEON_FP_CRTC2_H_TOTAL_DISP; 1938 break; 1939 default: 1940 panic("Bad CRTC!"); 1941 break; 1942 } 1943 1944 /* 1945 * CRTC_GEN_CNTL - depth, accelerator mode, etc. 1946 */ 1947 /* only bother with 32bpp and 8bpp */ 1948 v = dp->rd_format << RADEON_CRTC_PIX_WIDTH_SHIFT; 1949 1950 if (crtc == 1) { 1951 v |= RADEON_CRTC2_CRT2_ON | RADEON_CRTC2_EN; 1952 } else { 1953 v |= RADEON_CRTC_EXT_DISP_EN | RADEON_CRTC_EN; 1954 } 1955 1956 if (mode->flags & VID_DBLSCAN) 1957 v |= RADEON_CRTC2_DBL_SCAN_EN; 1958 1959 if (mode->flags & VID_INTERLACE) 1960 v |= RADEON_CRTC2_INTERLACE_EN; 1961 1962 if (mode->flags & VID_CSYNC) { 1963 v |= RADEON_CRTC2_CSYNC_EN; 1964 if (crtc == 1) 1965 v |= RADEON_CRTC2_VSYNC_TRISTAT; 1966 } 1967 1968 PUT32(sc, gencntl, v); 1969 DPRINTF(("CRTC%s_GEN_CNTL = %08x\n", crtc ? "2" : "", v)); 1970 1971 /* 1972 * CRTC_EXT_CNTL - preserve disable flags, set ATI linear and EXT_CNT 1973 */ 1974 v = GET32(sc, RADEON_CRTC_EXT_CNTL); 1975 if (crtc == 0) { 1976 v &= (RADEON_CRTC_VSYNC_DIS | RADEON_CRTC_HSYNC_DIS | 1977 RADEON_CRTC_DISPLAY_DIS); 1978 v |= RADEON_XCRT_CNT_EN | RADEON_VGA_ATI_LINEAR; 1979 if (mode->flags & VID_CSYNC) 1980 v |= RADEON_CRTC_VSYNC_TRISTAT; 1981 } 1982 /* unconditional turn on CRT, in case first CRTC is DFP */ 1983 v |= RADEON_CRTC_CRT_ON; 1984 PUT32(sc, RADEON_CRTC_EXT_CNTL, v); 1985 PRINTREG(RADEON_CRTC_EXT_CNTL); 1986 1987 /* 1988 * H_TOTAL_DISP 1989 */ 1990 v = ((mode->hdisplay / 8) - 1) << 16; 1991 v |= (mode->htotal / 8) - 1; 1992 PUT32(sc, htotaldisp, v); 1993 DPRINTF(("CRTC%s_H_TOTAL_DISP = %08x\n", crtc ? "2" : "", v)); 1994 PUT32(sc, fphtotaldisp, v); 1995 DPRINTF(("FP_H%s_TOTAL_DISP = %08x\n", crtc ? "2" : "", v)); 1996 1997 /* 1998 * H_SYNC_STRT_WID 1999 */ 2000 v = (((mode->hsync_end - mode->hsync_start) / 8) << 16); 2001 v |= mode->hsync_start; 2002 if (mode->flags & VID_NHSYNC) 2003 v |= RADEON_CRTC_H_SYNC_POL; 2004 PUT32(sc, hsyncstrt, v); 2005 DPRINTF(("CRTC%s_H_SYNC_STRT_WID = %08x\n", crtc ? "2" : "", v)); 2006 PUT32(sc, fphsyncstrt, v); 2007 DPRINTF(("FP_H%s_SYNC_STRT_WID = %08x\n", crtc ? "2" : "", v)); 2008 2009 /* 2010 * V_TOTAL_DISP 2011 */ 2012 v = ((mode->vdisplay - 1) << 16); 2013 v |= (mode->vtotal - 1); 2014 PUT32(sc, vtotaldisp, v); 2015 DPRINTF(("CRTC%s_V_TOTAL_DISP = %08x\n", crtc ? "2" : "", v)); 2016 PUT32(sc, fpvtotaldisp, v); 2017 DPRINTF(("FP_V%s_TOTAL_DISP = %08x\n", crtc ? "2" : "", v)); 2018 2019 /* 2020 * V_SYNC_STRT_WID 2021 */ 2022 v = ((mode->vsync_end - mode->vsync_start) << 16); 2023 v |= (mode->vsync_start - 1); 2024 if (mode->flags & VID_NVSYNC) 2025 v |= RADEON_CRTC_V_SYNC_POL; 2026 PUT32(sc, vsyncstrt, v); 2027 DPRINTF(("CRTC%s_V_SYNC_STRT_WID = %08x\n", crtc ? "2" : "", v)); 2028 PUT32(sc, fpvsyncstrt, v); 2029 DPRINTF(("FP_V%s_SYNC_STRT_WID = %08x\n", crtc ? "2" : "", v)); 2030 2031 radeonfb_program_vclk(sc, mode->dot_clock, crtc); 2032 2033 switch (crtc) { 2034 case 0: 2035 PUT32(sc, RADEON_CRTC_OFFSET, 0); 2036 PUT32(sc, RADEON_CRTC_OFFSET_CNTL, 0); 2037 PUT32(sc, RADEON_CRTC_PITCH, pitch); 2038 CLR32(sc, RADEON_DISP_MERGE_CNTL, RADEON_DISP_RGB_OFFSET_EN); 2039 2040 CLR32(sc, RADEON_CRTC_EXT_CNTL, 2041 RADEON_CRTC_VSYNC_DIS | RADEON_CRTC_HSYNC_DIS | 2042 RADEON_CRTC_DISPLAY_DIS /* | RADEON_CRTC_DISP_REQ_EN_B */); 2043 CLR32(sc, RADEON_CRTC_GEN_CNTL, RADEON_CRTC_DISP_REQ_EN_B); 2044 PRINTREG(RADEON_CRTC_EXT_CNTL); 2045 PRINTREG(RADEON_CRTC_GEN_CNTL); 2046 PRINTREG(RADEON_CLOCK_CNTL_INDEX); 2047 break; 2048 2049 case 1: 2050 PUT32(sc, RADEON_CRTC2_OFFSET, 0); 2051 PUT32(sc, RADEON_CRTC2_OFFSET_CNTL, 0); 2052 PUT32(sc, RADEON_CRTC2_PITCH, pitch); 2053 CLR32(sc, RADEON_DISP2_MERGE_CNTL, RADEON_DISP2_RGB_OFFSET_EN); 2054 CLR32(sc, RADEON_CRTC2_GEN_CNTL, 2055 RADEON_CRTC2_VSYNC_DIS | 2056 RADEON_CRTC2_HSYNC_DIS | 2057 RADEON_CRTC2_DISP_DIS | RADEON_CRTC2_DISP_REQ_EN_B); 2058 PRINTREG(RADEON_CRTC2_GEN_CNTL); 2059 break; 2060 } 2061 } 2062 2063 int 2064 radeonfb_isblank(struct radeonfb_display *dp) 2065 { 2066 uint32_t reg, mask; 2067 2068 if (dp->rd_crtcs[0].rc_number) { 2069 reg = RADEON_CRTC2_GEN_CNTL; 2070 mask = RADEON_CRTC2_DISP_DIS; 2071 } else { 2072 reg = RADEON_CRTC_EXT_CNTL; 2073 mask = RADEON_CRTC_DISPLAY_DIS; 2074 } 2075 return ((GET32(dp->rd_softc, reg) & mask) ? 1 : 0); 2076 } 2077 2078 void 2079 radeonfb_blank(struct radeonfb_display *dp, int blank) 2080 { 2081 struct radeonfb_softc *sc = dp->rd_softc; 2082 uint32_t reg, mask; 2083 uint32_t fpreg, fpval; 2084 int i; 2085 2086 for (i = 0; i < dp->rd_ncrtcs; i++) { 2087 2088 if (dp->rd_crtcs[i].rc_number) { 2089 reg = RADEON_CRTC2_GEN_CNTL; 2090 mask = RADEON_CRTC2_DISP_DIS; 2091 fpreg = RADEON_FP2_GEN_CNTL; 2092 fpval = RADEON_FP2_ON; 2093 } else { 2094 reg = RADEON_CRTC_EXT_CNTL; 2095 mask = RADEON_CRTC_DISPLAY_DIS; 2096 fpreg = RADEON_FP_GEN_CNTL; 2097 fpval = RADEON_FP_FPON; 2098 } 2099 2100 if (blank) { 2101 SET32(sc, reg, mask); 2102 CLR32(sc, fpreg, fpval); 2103 } else { 2104 CLR32(sc, reg, mask); 2105 SET32(sc, fpreg, fpval); 2106 } 2107 } 2108 PRINTREG(RADEON_FP_GEN_CNTL); 2109 PRINTREG(RADEON_FP2_GEN_CNTL); 2110 } 2111 2112 void 2113 radeonfb_init_screen(void *cookie, struct vcons_screen *scr, int existing, 2114 long *defattr) 2115 { 2116 struct radeonfb_display *dp = cookie; 2117 struct rasops_info *ri = &scr->scr_ri; 2118 2119 /* initialize font subsystem */ 2120 wsfont_init(); 2121 2122 DPRINTF(("init screen called, existing %d\n", existing)); 2123 2124 ri->ri_depth = dp->rd_bpp; 2125 ri->ri_width = dp->rd_virtx; 2126 ri->ri_height = dp->rd_virty; 2127 ri->ri_stride = dp->rd_stride; 2128 ri->ri_flg = RI_CENTER; 2129 ri->ri_bits = (void *)dp->rd_fbptr; 2130 2131 /* XXX: 32 bpp only */ 2132 /* this is rgb in "big-endian order..." */ 2133 ri->ri_rnum = 8; 2134 ri->ri_gnum = 8; 2135 ri->ri_bnum = 8; 2136 ri->ri_rpos = 16; 2137 ri->ri_gpos = 8; 2138 ri->ri_bpos = 0; 2139 2140 if (existing) { 2141 ri->ri_flg |= RI_CLEAR; 2142 2143 /* start a modeswitch now */ 2144 radeonfb_modeswitch(dp); 2145 } 2146 2147 /* 2148 * XXX: font selection should be based on properties, with some 2149 * normal/reasonable default. 2150 */ 2151 ri->ri_caps = WSSCREEN_WSCOLORS; 2152 2153 /* initialize and look for an initial font */ 2154 rasops_init(ri, dp->rd_virty/8, dp->rd_virtx/8); 2155 2156 rasops_reconfig(ri, dp->rd_virty / ri->ri_font->fontheight, 2157 dp->rd_virtx / ri->ri_font->fontwidth); 2158 2159 /* enable acceleration */ 2160 ri->ri_ops.copyrows = radeonfb_copyrows; 2161 ri->ri_ops.copycols = radeonfb_copycols; 2162 ri->ri_ops.eraserows = radeonfb_eraserows; 2163 ri->ri_ops.erasecols = radeonfb_erasecols; 2164 ri->ri_ops.allocattr = radeonfb_allocattr; 2165 if (!IS_R300(dp->rd_softc)) { 2166 ri->ri_ops.putchar = radeonfb_putchar; 2167 } 2168 ri->ri_ops.cursor = radeonfb_cursor; 2169 } 2170 2171 void 2172 radeonfb_set_fbloc(struct radeonfb_softc *sc) 2173 { 2174 uint32_t gen, ext, gen2 = 0; 2175 uint32_t agploc, aperbase, apersize, mcfbloc; 2176 2177 gen = GET32(sc, RADEON_CRTC_GEN_CNTL); 2178 ext = GET32(sc, RADEON_CRTC_EXT_CNTL); 2179 agploc = GET32(sc, RADEON_MC_AGP_LOCATION); 2180 aperbase = GET32(sc, RADEON_CONFIG_APER_0_BASE); 2181 apersize = GET32(sc, RADEON_CONFIG_APER_SIZE); 2182 2183 PUT32(sc, RADEON_CRTC_GEN_CNTL, gen | RADEON_CRTC_DISP_REQ_EN_B); 2184 PUT32(sc, RADEON_CRTC_EXT_CNTL, ext | RADEON_CRTC_DISPLAY_DIS); 2185 //PUT32(sc, RADEON_CRTC_GEN_CNTL, gen | RADEON_CRTC_DISPLAY_DIS); 2186 //PUT32(sc, RADEON_CRTC_EXT_CNTL, ext | RADEON_CRTC_DISP_REQ_EN_B); 2187 2188 if (HAS_CRTC2(sc)) { 2189 gen2 = GET32(sc, RADEON_CRTC2_GEN_CNTL); 2190 PUT32(sc, RADEON_CRTC2_GEN_CNTL, 2191 gen2 | RADEON_CRTC2_DISP_REQ_EN_B); 2192 } 2193 2194 delay(100000); 2195 2196 mcfbloc = (aperbase >> 16) | 2197 ((aperbase + (apersize - 1)) & 0xffff0000); 2198 2199 sc->sc_aperbase = (mcfbloc & 0xffff) << 16; 2200 sc->sc_memsz = apersize; 2201 2202 if (((agploc & 0xffff) << 16) != 2203 ((mcfbloc & 0xffff0000U) + 0x10000)) { 2204 agploc = mcfbloc & 0xffff0000U; 2205 agploc |= ((agploc + 0x10000) >> 16); 2206 } 2207 2208 PUT32(sc, RADEON_HOST_PATH_CNTL, 0); 2209 2210 PUT32(sc, RADEON_MC_FB_LOCATION, mcfbloc); 2211 PUT32(sc, RADEON_MC_AGP_LOCATION, agploc); 2212 2213 DPRINTF(("aperbase = %u\n", aperbase)); 2214 PRINTREG(RADEON_MC_FB_LOCATION); 2215 PRINTREG(RADEON_MC_AGP_LOCATION); 2216 2217 PUT32(sc, RADEON_DISPLAY_BASE_ADDR, sc->sc_aperbase); 2218 2219 if (HAS_CRTC2(sc)) 2220 PUT32(sc, RADEON_DISPLAY2_BASE_ADDR, sc->sc_aperbase); 2221 2222 PUT32(sc, RADEON_OV0_BASE_ADDR, sc->sc_aperbase); 2223 2224 #if 0 2225 /* XXX: what is this AGP garbage? :-) */ 2226 PUT32(sc, RADEON_AGP_CNTL, 0x00100000); 2227 #endif 2228 2229 delay(100000); 2230 2231 PUT32(sc, RADEON_CRTC_GEN_CNTL, gen); 2232 PUT32(sc, RADEON_CRTC_EXT_CNTL, ext); 2233 2234 if (HAS_CRTC2(sc)) 2235 PUT32(sc, RADEON_CRTC2_GEN_CNTL, gen2); 2236 } 2237 2238 void 2239 radeonfb_init_misc(struct radeonfb_softc *sc) 2240 { 2241 PUT32(sc, RADEON_BUS_CNTL, 2242 RADEON_BUS_MASTER_DIS | 2243 RADEON_BUS_PREFETCH_MODE_ACT | 2244 RADEON_BUS_PCI_READ_RETRY_EN | 2245 RADEON_BUS_PCI_WRT_RETRY_EN | 2246 (3 << RADEON_BUS_RETRY_WS_SHIFT) | 2247 RADEON_BUS_MSTR_RD_MULT | 2248 RADEON_BUS_MSTR_RD_LINE | 2249 RADEON_BUS_RD_DISCARD_EN | 2250 RADEON_BUS_MSTR_DISCONNECT_EN | 2251 RADEON_BUS_READ_BURST); 2252 2253 PUT32(sc, RADEON_BUS_CNTL1, 0xf0); 2254 /* PUT32(sc, RADEON_SEPROM_CNTL1, 0x09ff0000); */ 2255 PUT32(sc, RADEON_FCP_CNTL, RADEON_FCP0_SRC_GND); 2256 PUT32(sc, RADEON_RBBM_CNTL, 2257 (3 << RADEON_RB_SETTLE_SHIFT) | 2258 (4 << RADEON_ABORTCLKS_HI_SHIFT) | 2259 (4 << RADEON_ABORTCLKS_CP_SHIFT) | 2260 (4 << RADEON_ABORTCLKS_CFIFO_SHIFT)); 2261 2262 /* XXX: figure out what these mean! */ 2263 PUT32(sc, RADEON_AGP_CNTL, 0x00100000); 2264 PUT32(sc, RADEON_HOST_PATH_CNTL, 0); 2265 //PUT32(sc, RADEON_DISP_MISC_CNTL, 0x5bb00400); 2266 2267 PUT32(sc, RADEON_GEN_INT_CNTL, 0); 2268 PUT32(sc, RADEON_GEN_INT_STATUS, GET32(sc, RADEON_GEN_INT_STATUS)); 2269 } 2270 2271 /* 2272 * This loads a linear color map for true color. 2273 */ 2274 void 2275 radeonfb_init_palette(struct radeonfb_softc *sc, int crtc) 2276 { 2277 int i; 2278 uint32_t vclk; 2279 2280 #define DAC_WIDTH ((1 << 10) - 1) 2281 #define CLUT_WIDTH ((1 << 8) - 1) 2282 #define CLUT_COLOR(i) ((i * DAC_WIDTH * 2 / CLUT_WIDTH + 1) / 2) 2283 2284 vclk = GETPLL(sc, RADEON_VCLK_ECP_CNTL); 2285 PUTPLL(sc, RADEON_VCLK_ECP_CNTL, vclk & ~RADEON_PIXCLK_DAC_ALWAYS_ONb); 2286 2287 if (crtc) 2288 SET32(sc, RADEON_DAC_CNTL2, RADEON_DAC2_PALETTE_ACC_CTL); 2289 else 2290 CLR32(sc, RADEON_DAC_CNTL2, RADEON_DAC2_PALETTE_ACC_CTL); 2291 2292 PUT32(sc, RADEON_PALETTE_INDEX, 0); 2293 for (i = 0; i <= CLUT_WIDTH; ++i) { 2294 PUT32(sc, RADEON_PALETTE_30_DATA, 2295 (CLUT_COLOR(i) << 10) | 2296 (CLUT_COLOR(i) << 20) | 2297 (CLUT_COLOR(i))); 2298 } 2299 2300 CLR32(sc, RADEON_DAC_CNTL2, RADEON_DAC2_PALETTE_ACC_CTL); 2301 PRINTREG(RADEON_DAC_CNTL2); 2302 2303 PUTPLL(sc, RADEON_VCLK_ECP_CNTL, vclk); 2304 } 2305 2306 /* 2307 * Bugs in some R300 hardware requires this when accessing CLOCK_CNTL_INDEX. 2308 */ 2309 void 2310 radeonfb_r300cg_workaround(struct radeonfb_softc *sc) 2311 { 2312 uint32_t tmp, save; 2313 2314 save = GET32(sc, RADEON_CLOCK_CNTL_INDEX); 2315 tmp = save & ~(0x3f | RADEON_PLL_WR_EN); 2316 PUT32(sc, RADEON_CLOCK_CNTL_INDEX, tmp); 2317 tmp = GET32(sc, RADEON_CLOCK_CNTL_DATA); 2318 PUT32(sc, RADEON_CLOCK_CNTL_INDEX, save); 2319 } 2320 2321 /* 2322 * Acceleration entry points. 2323 */ 2324 static void 2325 radeonfb_putchar(void *cookie, int row, int col, u_int c, long attr) 2326 { 2327 struct rasops_info *ri = cookie; 2328 struct vcons_screen *scr = ri->ri_hw; 2329 struct radeonfb_display *dp = scr->scr_cookie; 2330 uint32_t x, y, w, h; 2331 uint32_t bg, fg; 2332 uint8_t *data; 2333 2334 if (dp->rd_wsmode != WSDISPLAYIO_MODE_EMUL) 2335 return; 2336 2337 if (!CHAR_IN_FONT(c, ri->ri_font)) 2338 return; 2339 2340 w = ri->ri_font->fontwidth; 2341 h = ri->ri_font->fontheight; 2342 2343 bg = ri->ri_devcmap[(attr >> 16) & 0xf]; 2344 fg = ri->ri_devcmap[(attr >> 24) & 0xf]; 2345 2346 x = ri->ri_xorigin + col * w; 2347 y = ri->ri_yorigin + row * h; 2348 2349 if (c == 0x20) { 2350 radeonfb_rectfill(dp, x, y, w, h, bg); 2351 } else { 2352 data = (uint8_t *)ri->ri_font->data + 2353 (c - ri->ri_font->firstchar) * ri->ri_fontscale; 2354 2355 radeonfb_setup_mono(dp, x, y, w, h, fg, bg); 2356 radeonfb_feed_bytes(dp, ri->ri_fontscale, data); 2357 } 2358 } 2359 2360 static void 2361 radeonfb_eraserows(void *cookie, int row, int nrows, long fillattr) 2362 { 2363 struct rasops_info *ri = cookie; 2364 struct vcons_screen *scr = ri->ri_hw; 2365 struct radeonfb_display *dp = scr->scr_cookie; 2366 uint32_t x, y, w, h, fg, bg, ul; 2367 2368 /* XXX: check for full emulation mode? */ 2369 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 2370 x = ri->ri_xorigin; 2371 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 2372 w = ri->ri_emuwidth; 2373 h = ri->ri_font->fontheight * nrows; 2374 2375 rasops_unpack_attr(fillattr, &fg, &bg, &ul); 2376 radeonfb_rectfill(dp, x, y, w, h, ri->ri_devcmap[bg & 0xf]); 2377 } 2378 } 2379 2380 static void 2381 radeonfb_copyrows(void *cookie, int srcrow, int dstrow, int nrows) 2382 { 2383 struct rasops_info *ri = cookie; 2384 struct vcons_screen *scr = ri->ri_hw; 2385 struct radeonfb_display *dp = scr->scr_cookie; 2386 uint32_t x, ys, yd, w, h; 2387 2388 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 2389 x = ri->ri_xorigin; 2390 ys = ri->ri_yorigin + ri->ri_font->fontheight * srcrow; 2391 yd = ri->ri_yorigin + ri->ri_font->fontheight * dstrow; 2392 w = ri->ri_emuwidth; 2393 h = ri->ri_font->fontheight * nrows; 2394 radeonfb_bitblt(dp, x, ys, x, yd, w, h, 2395 RADEON_ROP3_S, 0xffffffff); 2396 } 2397 } 2398 2399 static void 2400 radeonfb_copycols(void *cookie, int row, int srccol, int dstcol, int ncols) 2401 { 2402 struct rasops_info *ri = cookie; 2403 struct vcons_screen *scr = ri->ri_hw; 2404 struct radeonfb_display *dp = scr->scr_cookie; 2405 uint32_t xs, xd, y, w, h; 2406 2407 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 2408 xs = ri->ri_xorigin + ri->ri_font->fontwidth * srccol; 2409 xd = ri->ri_xorigin + ri->ri_font->fontwidth * dstcol; 2410 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 2411 w = ri->ri_font->fontwidth * ncols; 2412 h = ri->ri_font->fontheight; 2413 radeonfb_bitblt(dp, xs, y, xd, y, w, h, 2414 RADEON_ROP3_S, 0xffffffff); 2415 } 2416 } 2417 2418 static void 2419 radeonfb_erasecols(void *cookie, int row, int startcol, int ncols, 2420 long fillattr) 2421 { 2422 struct rasops_info *ri = cookie; 2423 struct vcons_screen *scr = ri->ri_hw; 2424 struct radeonfb_display *dp = scr->scr_cookie; 2425 uint32_t x, y, w, h, fg, bg, ul; 2426 2427 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 2428 x = ri->ri_xorigin + ri->ri_font->fontwidth * startcol; 2429 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 2430 w = ri->ri_font->fontwidth * ncols; 2431 h = ri->ri_font->fontheight; 2432 2433 rasops_unpack_attr(fillattr, &fg, &bg, &ul); 2434 radeonfb_rectfill(dp, x, y, w, h, ri->ri_devcmap[bg & 0xf]); 2435 } 2436 } 2437 2438 static void 2439 radeonfb_cursor(void *cookie, int on, int row, int col) 2440 { 2441 struct rasops_info *ri = cookie; 2442 struct vcons_screen *scr = ri->ri_hw; 2443 struct radeonfb_display *dp = scr->scr_cookie; 2444 int x, y, wi, he; 2445 2446 wi = ri->ri_font->fontwidth; 2447 he = ri->ri_font->fontheight; 2448 2449 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 2450 x = ri->ri_ccol * wi + ri->ri_xorigin; 2451 y = ri->ri_crow * he + ri->ri_yorigin; 2452 /* first turn off the old cursor */ 2453 if (ri->ri_flg & RI_CURSOR) { 2454 radeonfb_bitblt(dp, x, y, x, y, wi, he, 2455 RADEON_ROP3_Dn, 0xffffffff); 2456 ri->ri_flg &= ~RI_CURSOR; 2457 } 2458 ri->ri_crow = row; 2459 ri->ri_ccol = col; 2460 /* then (possibly) turn on the new one */ 2461 if (on) { 2462 x = ri->ri_ccol * wi + ri->ri_xorigin; 2463 y = ri->ri_crow * he + ri->ri_yorigin; 2464 radeonfb_bitblt(dp, x, y, x, y, wi, he, 2465 RADEON_ROP3_Dn, 0xffffffff); 2466 ri->ri_flg |= RI_CURSOR; 2467 } 2468 } else { 2469 scr->scr_ri.ri_crow = row; 2470 scr->scr_ri.ri_ccol = col; 2471 scr->scr_ri.ri_flg &= ~RI_CURSOR; 2472 } 2473 } 2474 2475 static int 2476 radeonfb_allocattr(void *cookie, int fg, int bg, int flags, long *attrp) 2477 { 2478 if ((fg == 0) && (bg == 0)) { 2479 fg = WS_DEFAULT_FG; 2480 bg = WS_DEFAULT_BG; 2481 } 2482 *attrp = ((fg & 0xf) << 24) | ((bg & 0xf) << 16) | (flags & 0xff) << 8; 2483 return 0; 2484 } 2485 2486 /* 2487 * Underlying acceleration support. 2488 */ 2489 static void 2490 radeonfb_setup_mono(struct radeonfb_display *dp, int xd, int yd, int width, 2491 int height, uint32_t fg, uint32_t bg) 2492 { 2493 struct radeonfb_softc *sc = dp->rd_softc; 2494 uint32_t gmc; 2495 uint32_t padded_width = (width+7) & 0xfff8; 2496 uint32_t topleft, bottomright; 2497 2498 gmc = dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT; 2499 2500 if (width != padded_width) { 2501 2502 radeonfb_wait_fifo(sc, 2); 2503 topleft = ((yd << 16) & 0x1fff0000) | (xd & 0x1fff); 2504 bottomright = (((yd + height) << 16) & 0x1fff0000) | 2505 ((xd + width) & 0x1fff); 2506 PUT32(sc, RADEON_SC_TOP_LEFT, topleft); 2507 PUT32(sc, RADEON_SC_BOTTOM_RIGHT, bottomright); 2508 } 2509 2510 radeonfb_wait_fifo(sc, 5); 2511 2512 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 2513 RADEON_GMC_BRUSH_NONE | 2514 RADEON_GMC_SRC_DATATYPE_MONO_FG_BG | 2515 //RADEON_GMC_BYTE_LSB_TO_MSB | 2516 RADEON_GMC_DST_CLIPPING | 2517 RADEON_ROP3_S | 2518 RADEON_DP_SRC_SOURCE_HOST_DATA | 2519 RADEON_GMC_CLR_CMP_CNTL_DIS | 2520 RADEON_GMC_WR_MSK_DIS | 2521 gmc); 2522 2523 PUT32(sc, RADEON_DP_SRC_FRGD_CLR, fg); 2524 PUT32(sc, RADEON_DP_SRC_BKGD_CLR, bg); 2525 2526 PUT32(sc, RADEON_DST_X_Y, (xd << 16) | yd); 2527 PUT32(sc, RADEON_DST_WIDTH_HEIGHT, (padded_width << 16) | height); 2528 2529 } 2530 2531 static void 2532 radeonfb_feed_bytes(struct radeonfb_display *dp, int count, uint8_t *data) 2533 { 2534 struct radeonfb_softc *sc = dp->rd_softc; 2535 int i; 2536 uint32_t latch = 0; 2537 int shift = 0; 2538 2539 for (i = 0; i < count; i++) { 2540 latch |= (data[i] << shift); 2541 if (shift == 24) { 2542 radeonfb_wait_fifo(sc, 1); 2543 PUT32(sc, RADEON_HOST_DATA0, latch); 2544 latch = 0; 2545 shift = 0; 2546 } else 2547 shift += 8; 2548 } 2549 if (shift != 0) { 2550 radeonfb_wait_fifo(sc, 1); 2551 PUT32(sc, RADEON_HOST_DATA0, latch); 2552 } 2553 radeonfb_unclip(sc); 2554 } 2555 2556 static void 2557 radeonfb_rectfill(struct radeonfb_display *dp, int dstx, int dsty, 2558 int width, int height, uint32_t color) 2559 { 2560 struct radeonfb_softc *sc = dp->rd_softc; 2561 uint32_t gmc; 2562 2563 gmc = dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT; 2564 2565 radeonfb_wait_fifo(sc, 6); 2566 2567 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 2568 RADEON_GMC_BRUSH_SOLID_COLOR | 2569 RADEON_GMC_SRC_DATATYPE_COLOR | 2570 RADEON_GMC_CLR_CMP_CNTL_DIS | 2571 RADEON_ROP3_P | gmc); 2572 2573 PUT32(sc, RADEON_DP_BRUSH_FRGD_CLR, color); 2574 PUT32(sc, RADEON_DP_WRITE_MASK, 0xffffffff); 2575 PUT32(sc, RADEON_DP_CNTL, 2576 RADEON_DST_X_LEFT_TO_RIGHT | 2577 RADEON_DST_Y_TOP_TO_BOTTOM); 2578 PUT32(sc, RADEON_DST_Y_X, (dsty << 16) | dstx); 2579 PUT32(sc, RADEON_DST_WIDTH_HEIGHT, (width << 16) | (height)); 2580 2581 /* 2582 * XXX: we don't wait for the fifo to empty -- that would slow 2583 * things down! The linux radeonfb driver waits, but xfree doesn't 2584 */ 2585 /* XXX: for now we do, to make it safe for direct drawing */ 2586 radeonfb_engine_idle(sc); 2587 } 2588 2589 static void 2590 radeonfb_bitblt(struct radeonfb_display *dp, int srcx, int srcy, 2591 int dstx, int dsty, int width, int height, int rop, uint32_t mask) 2592 { 2593 struct radeonfb_softc *sc = dp->rd_softc; 2594 uint32_t gmc; 2595 uint32_t dir; 2596 2597 if (dsty < srcy) { 2598 dir = RADEON_DST_Y_TOP_TO_BOTTOM; 2599 } else { 2600 srcy += height - 1; 2601 dsty += height - 1; 2602 dir = 0; 2603 } 2604 if (dstx < srcx) { 2605 dir |= RADEON_DST_X_LEFT_TO_RIGHT; 2606 } else { 2607 srcx += width - 1; 2608 dstx += width - 1; 2609 } 2610 2611 gmc = dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT; 2612 2613 radeonfb_wait_fifo(sc, 6); 2614 2615 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 2616 //RADEON_GMC_SRC_CLIPPING | 2617 RADEON_GMC_BRUSH_SOLID_COLOR | 2618 RADEON_GMC_SRC_DATATYPE_COLOR | 2619 RADEON_GMC_CLR_CMP_CNTL_DIS | 2620 RADEON_DP_SRC_SOURCE_MEMORY | 2621 rop | gmc); 2622 2623 PUT32(sc, RADEON_DP_WRITE_MASK, mask); 2624 PUT32(sc, RADEON_DP_CNTL, dir); 2625 PUT32(sc, RADEON_SRC_Y_X, (srcy << 16) | srcx); 2626 PUT32(sc, RADEON_DST_Y_X, (dsty << 16) | dstx); 2627 PUT32(sc, RADEON_DST_WIDTH_HEIGHT, (width << 16) | (height)); 2628 2629 /* 2630 * XXX: we don't wait for the fifo to empty -- that would slow 2631 * things down! The linux radeonfb driver waits, but xfree doesn't 2632 */ 2633 /* XXX: for now we do, to make it safe for direct drawing */ 2634 radeonfb_engine_idle(sc); 2635 } 2636 2637 static void 2638 radeonfb_engine_idle(struct radeonfb_softc *sc) 2639 { 2640 int i; 2641 2642 radeonfb_wait_fifo(sc, 64); 2643 for (i = RADEON_TIMEOUT; i; i--) { 2644 if ((GET32(sc, RADEON_RBBM_STATUS) & 2645 RADEON_RBBM_ACTIVE) == 0) { 2646 radeonfb_engine_flush(sc); 2647 break; 2648 } 2649 } 2650 } 2651 2652 static void 2653 radeonfb_wait_fifo(struct radeonfb_softc *sc, int n) 2654 { 2655 int i; 2656 2657 for (i = RADEON_TIMEOUT; i; i--) { 2658 if ((GET32(sc, RADEON_RBBM_STATUS) & 2659 RADEON_RBBM_FIFOCNT_MASK) >= n) 2660 return; 2661 } 2662 #ifdef DIAGNOSTIC 2663 if (!i) 2664 printf("%s: timed out waiting for fifo (%x)\n", 2665 XNAME(sc), GET32(sc, RADEON_RBBM_STATUS)); 2666 #endif 2667 } 2668 2669 static void 2670 radeonfb_engine_flush(struct radeonfb_softc *sc) 2671 { 2672 int i; 2673 SET32(sc, RADEON_RB2D_DSTCACHE_CTLSTAT, RADEON_RB2D_DC_FLUSH_ALL); 2674 for (i = RADEON_TIMEOUT; i; i--) { 2675 if ((GET32(sc, RADEON_RB2D_DSTCACHE_CTLSTAT) & 2676 RADEON_RB2D_DC_BUSY) == 0) 2677 break; 2678 } 2679 #ifdef DIAGNOSTIC 2680 if (!i) 2681 printf("%s: engine flush timed out!\n", XNAME(sc)); 2682 #endif 2683 } 2684 2685 static inline void 2686 radeonfb_unclip(struct radeonfb_softc *sc) 2687 { 2688 2689 radeonfb_wait_fifo(sc, 2); 2690 PUT32(sc, RADEON_SC_TOP_LEFT, 0); 2691 PUT32(sc, RADEON_SC_BOTTOM_RIGHT, 0x1fff1fff); 2692 } 2693 2694 static void 2695 radeonfb_engine_init(struct radeonfb_display *dp) 2696 { 2697 struct radeonfb_softc *sc = dp->rd_softc; 2698 uint32_t pitch; 2699 2700 /* no 3D */ 2701 PUT32(sc, RADEON_RB3D_CNTL, 0); 2702 2703 radeonfb_engine_reset(sc); 2704 pitch = ((dp->rd_virtx * (dp->rd_bpp / 8) + 0x3f)) >> 6; 2705 //pitch = ((sc->sc_maxx * (sc->sc_maxbpp / 8) + 0x3f)) >> 6; 2706 2707 radeonfb_wait_fifo(sc, 1); 2708 if (!IS_R300(sc)) 2709 PUT32(sc, RADEON_RB2D_DSTCACHE_MODE, 0); 2710 2711 radeonfb_wait_fifo(sc, 3); 2712 PUT32(sc, RADEON_DEFAULT_PITCH_OFFSET, 2713 (pitch << 22) | (sc->sc_aperbase >> 10)); 2714 2715 2716 PUT32(sc, RADEON_DST_PITCH_OFFSET, 2717 (pitch << 22) | (sc->sc_aperbase >> 10)); 2718 PUT32(sc, RADEON_SRC_PITCH_OFFSET, 2719 (pitch << 22) | (sc->sc_aperbase >> 10)); 2720 2721 radeonfb_wait_fifo(sc, 1); 2722 #if _BYTE_ORDER == _BIG_ENDIAN 2723 SET32(sc, RADEON_DP_DATATYPE, RADEON_HOST_BIG_ENDIAN_EN); 2724 #else 2725 CLR32(sc, RADEON_DP_DATATYPE, RADEON_HOST_BIG_ENDIAN_EN); 2726 #endif 2727 2728 /* default scissors -- no clipping */ 2729 radeonfb_wait_fifo(sc, 1); 2730 PUT32(sc, RADEON_DEFAULT_SC_BOTTOM_RIGHT, 2731 RADEON_DEFAULT_SC_RIGHT_MAX | RADEON_DEFAULT_SC_BOTTOM_MAX); 2732 2733 radeonfb_wait_fifo(sc, 1); 2734 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 2735 (dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT) | 2736 RADEON_GMC_CLR_CMP_CNTL_DIS | 2737 RADEON_GMC_BRUSH_SOLID_COLOR | 2738 RADEON_GMC_SRC_DATATYPE_COLOR); 2739 2740 radeonfb_wait_fifo(sc, 7); 2741 PUT32(sc, RADEON_DST_LINE_START, 0); 2742 PUT32(sc, RADEON_DST_LINE_END, 0); 2743 PUT32(sc, RADEON_DP_BRUSH_FRGD_CLR, 0xffffffff); 2744 PUT32(sc, RADEON_DP_BRUSH_BKGD_CLR, 0); 2745 PUT32(sc, RADEON_DP_SRC_FRGD_CLR, 0xffffffff); 2746 PUT32(sc, RADEON_DP_SRC_BKGD_CLR, 0); 2747 PUT32(sc, RADEON_DP_WRITE_MASK, 0xffffffff); 2748 2749 radeonfb_engine_idle(sc); 2750 } 2751 2752 static void 2753 radeonfb_engine_reset(struct radeonfb_softc *sc) 2754 { 2755 uint32_t hpc, rbbm, mclkcntl, clkindex; 2756 2757 radeonfb_engine_flush(sc); 2758 2759 clkindex = GET32(sc, RADEON_CLOCK_CNTL_INDEX); 2760 if (HAS_R300CG(sc)) 2761 radeonfb_r300cg_workaround(sc); 2762 mclkcntl = GETPLL(sc, RADEON_MCLK_CNTL); 2763 2764 /* 2765 * According to comments in XFree code, resetting the HDP via 2766 * the RBBM_SOFT_RESET can cause bad behavior on some systems. 2767 * So we use HOST_PATH_CNTL instead. 2768 */ 2769 2770 hpc = GET32(sc, RADEON_HOST_PATH_CNTL); 2771 rbbm = GET32(sc, RADEON_RBBM_SOFT_RESET); 2772 if (IS_R300(sc)) { 2773 PUT32(sc, RADEON_RBBM_SOFT_RESET, rbbm | 2774 RADEON_SOFT_RESET_CP | 2775 RADEON_SOFT_RESET_HI | 2776 RADEON_SOFT_RESET_E2); 2777 GET32(sc, RADEON_RBBM_SOFT_RESET); 2778 PUT32(sc, RADEON_RBBM_SOFT_RESET, 0); 2779 /* 2780 * XXX: this bit is not defined in any ATI docs I have, 2781 * nor in the XFree code, but XFree does it. Why? 2782 */ 2783 SET32(sc, RADEON_RB2D_DSTCACHE_MODE, (1<<17)); 2784 } else { 2785 PUT32(sc, RADEON_RBBM_SOFT_RESET, rbbm | 2786 RADEON_SOFT_RESET_CP | 2787 RADEON_SOFT_RESET_SE | 2788 RADEON_SOFT_RESET_RE | 2789 RADEON_SOFT_RESET_PP | 2790 RADEON_SOFT_RESET_E2 | 2791 RADEON_SOFT_RESET_RB); 2792 GET32(sc, RADEON_RBBM_SOFT_RESET); 2793 PUT32(sc, RADEON_RBBM_SOFT_RESET, rbbm & 2794 ~(RADEON_SOFT_RESET_CP | 2795 RADEON_SOFT_RESET_SE | 2796 RADEON_SOFT_RESET_RE | 2797 RADEON_SOFT_RESET_PP | 2798 RADEON_SOFT_RESET_E2 | 2799 RADEON_SOFT_RESET_RB)); 2800 GET32(sc, RADEON_RBBM_SOFT_RESET); 2801 } 2802 2803 PUT32(sc, RADEON_HOST_PATH_CNTL, hpc | RADEON_HDP_SOFT_RESET); 2804 GET32(sc, RADEON_HOST_PATH_CNTL); 2805 PUT32(sc, RADEON_HOST_PATH_CNTL, hpc); 2806 2807 if (IS_R300(sc)) 2808 PUT32(sc, RADEON_RBBM_SOFT_RESET, rbbm); 2809 2810 PUT32(sc, RADEON_CLOCK_CNTL_INDEX, clkindex); 2811 PUTPLL(sc, RADEON_MCLK_CNTL, mclkcntl); 2812 2813 if (HAS_R300CG(sc)) 2814 radeonfb_r300cg_workaround(sc); 2815 } 2816 2817 static int 2818 radeonfb_set_curpos(struct radeonfb_display *dp, struct wsdisplay_curpos *pos) 2819 { 2820 int x, y; 2821 2822 x = pos->x; 2823 y = pos->y; 2824 2825 /* 2826 * This doesn't let a cursor move off the screen. I'm not 2827 * sure if this will have negative effects for e.g. Xinerama. 2828 * I'd guess Xinerama handles it by changing the cursor shape, 2829 * but that needs verification. 2830 */ 2831 if (x >= dp->rd_virtx) 2832 x = dp->rd_virtx - 1; 2833 if (x < 0) 2834 x = 0; 2835 if (y >= dp->rd_virty) 2836 y = dp->rd_virty - 1; 2837 if (y < 0) 2838 y = 0; 2839 2840 dp->rd_cursor.rc_pos.x = x; 2841 dp->rd_cursor.rc_pos.y = y; 2842 2843 radeonfb_cursor_position(dp); 2844 return 0; 2845 } 2846 2847 static int 2848 radeonfb_set_cursor(struct radeonfb_display *dp, struct wsdisplay_cursor *wc) 2849 { 2850 unsigned flags; 2851 2852 uint8_t r[2], g[2], b[2]; 2853 unsigned index, count; 2854 int i, err; 2855 int pitch, size; 2856 struct radeonfb_cursor nc; 2857 2858 flags = wc->which; 2859 2860 /* copy old values */ 2861 nc = dp->rd_cursor; 2862 2863 if (flags & WSDISPLAY_CURSOR_DOCMAP) { 2864 index = wc->cmap.index; 2865 count = wc->cmap.count; 2866 2867 if (index >= 2 || (index + count) > 2) 2868 return EINVAL; 2869 2870 err = copyin(wc->cmap.red, &r[index], count); 2871 if (err) 2872 return err; 2873 err = copyin(wc->cmap.green, &g[index], count); 2874 if (err) 2875 return err; 2876 err = copyin(wc->cmap.blue, &b[index], count); 2877 if (err) 2878 return err; 2879 2880 for (i = index; i < index + count; i++) { 2881 nc.rc_cmap[i] = 2882 (r[i] << 16) + (g[i] << 8) + (b[i] << 0); 2883 } 2884 } 2885 2886 if (flags & WSDISPLAY_CURSOR_DOSHAPE) { 2887 if ((wc->size.x > RADEON_CURSORMAXX) || 2888 (wc->size.y > RADEON_CURSORMAXY)) 2889 return EINVAL; 2890 2891 /* figure bytes per line */ 2892 pitch = (wc->size.x + 7) / 8; 2893 size = pitch * wc->size.y; 2894 2895 /* clear the old cursor and mask */ 2896 memset(nc.rc_image, 0, 512); 2897 memset(nc.rc_mask, 0, 512); 2898 2899 nc.rc_size = wc->size; 2900 2901 if ((err = copyin(wc->image, nc.rc_image, size)) != 0) 2902 return err; 2903 2904 if ((err = copyin(wc->mask, nc.rc_mask, size)) != 0) 2905 return err; 2906 } 2907 2908 if (flags & WSDISPLAY_CURSOR_DOHOT) { 2909 nc.rc_hot = wc->hot; 2910 if (nc.rc_hot.x >= nc.rc_size.x) 2911 nc.rc_hot.x = nc.rc_size.x - 1; 2912 if (nc.rc_hot.y >= nc.rc_size.y) 2913 nc.rc_hot.y = nc.rc_size.y - 1; 2914 } 2915 2916 if (flags & WSDISPLAY_CURSOR_DOPOS) { 2917 nc.rc_pos = wc->pos; 2918 if (nc.rc_pos.x >= dp->rd_virtx) 2919 nc.rc_pos.x = dp->rd_virtx - 1; 2920 #if 0 2921 if (nc.rc_pos.x < 0) 2922 nc.rc_pos.x = 0; 2923 #endif 2924 if (nc.rc_pos.y >= dp->rd_virty) 2925 nc.rc_pos.y = dp->rd_virty - 1; 2926 #if 0 2927 if (nc.rc_pos.y < 0) 2928 nc.rc_pos.y = 0; 2929 #endif 2930 } 2931 if (flags & WSDISPLAY_CURSOR_DOCUR) { 2932 nc.rc_visible = wc->enable; 2933 } 2934 2935 dp->rd_cursor = nc; 2936 radeonfb_cursor_update(dp, wc->which); 2937 2938 return 0; 2939 } 2940 2941 /* 2942 * Change the cursor shape. Call this with the cursor locked to avoid 2943 * flickering/tearing. 2944 */ 2945 static void 2946 radeonfb_cursor_shape(struct radeonfb_display *dp) 2947 { 2948 uint8_t and[512], xor[512]; 2949 int i, j, src, dst, pitch; 2950 const uint8_t *msk = dp->rd_cursor.rc_mask; 2951 const uint8_t *img = dp->rd_cursor.rc_image; 2952 2953 /* 2954 * Radeon cursor data interleaves one line of AND data followed 2955 * by a line of XOR data. (Each line corresponds to a whole hardware 2956 * pitch - i.e. 64 pixels or 8 bytes.) 2957 * 2958 * The cursor is displayed using the following table: 2959 * 2960 * AND XOR Result 2961 * ---------------------- 2962 * 0 0 Cursor color 0 2963 * 0 1 Cursor color 1 2964 * 1 0 Transparent 2965 * 1 1 Complement of background 2966 * 2967 * Our masks are therefore different from what we were passed. 2968 * Passed in, I'm assuming the data represents either color 0 or 1, 2969 * and a mask, so the passed in table looks like: 2970 * 2971 * IMG Mask Result 2972 * ----------------------- 2973 * 0 0 Transparent 2974 * 0 1 Cursor color 0 2975 * 1 0 Transparent 2976 * 1 1 Cursor color 1 2977 * 2978 * IF mask bit == 1, AND = 0, XOR = color. 2979 * IF mask bit == 0, AND = 1, XOR = 0. 2980 * 2981 * hence: AND = ~(mask); XOR = color & ~(mask); 2982 */ 2983 2984 pitch = ((dp->rd_cursor.rc_size.x + 7) / 8); 2985 2986 /* start by assuming all bits are transparent */ 2987 memset(and, 0xff, 512); 2988 memset(xor, 0x00, 512); 2989 2990 src = 0; 2991 dst = 0; 2992 for (i = 0; i < 64; i++) { 2993 for (j = 0; j < 64; j += 8) { 2994 if ((i < dp->rd_cursor.rc_size.y) && 2995 (j < dp->rd_cursor.rc_size.x)) { 2996 2997 /* take care to leave odd bits alone */ 2998 and[dst] &= ~(msk[src]); 2999 xor[dst] = img[src] & msk[src]; 3000 src++; 3001 } 3002 dst++; 3003 } 3004 } 3005 3006 /* copy the image into place */ 3007 for (i = 0; i < 64; i++) { 3008 memcpy((uint8_t *)dp->rd_curptr + (i * 16), 3009 &and[i * 8], 8); 3010 memcpy((uint8_t *)dp->rd_curptr + (i * 16) + 8, 3011 &xor[i * 8], 8); 3012 } 3013 } 3014 3015 static void 3016 radeonfb_cursor_position(struct radeonfb_display *dp) 3017 { 3018 struct radeonfb_softc *sc = dp->rd_softc; 3019 uint32_t offset, hvoff, hvpos; /* registers */ 3020 uint32_t coff; /* cursor offset */ 3021 int i, x, y, xoff, yoff, crtcoff; 3022 3023 /* 3024 * XXX: this also needs to handle pan/scan 3025 */ 3026 for (i = 0; i < dp->rd_ncrtcs; i++) { 3027 3028 struct radeonfb_crtc *rcp = &dp->rd_crtcs[i]; 3029 3030 if (rcp->rc_number) { 3031 offset = RADEON_CUR2_OFFSET; 3032 hvoff = RADEON_CUR2_HORZ_VERT_OFF; 3033 hvpos = RADEON_CUR2_HORZ_VERT_POSN; 3034 crtcoff = RADEON_CRTC2_OFFSET; 3035 } else { 3036 offset = RADEON_CUR_OFFSET; 3037 hvoff = RADEON_CUR_HORZ_VERT_OFF; 3038 hvpos = RADEON_CUR_HORZ_VERT_POSN; 3039 crtcoff = RADEON_CRTC_OFFSET; 3040 } 3041 3042 x = dp->rd_cursor.rc_pos.x; 3043 y = dp->rd_cursor.rc_pos.y; 3044 3045 while (y < rcp->rc_yoffset) { 3046 rcp->rc_yoffset -= RADEON_PANINCREMENT; 3047 } 3048 while (y >= (rcp->rc_yoffset + rcp->rc_videomode.vdisplay)) { 3049 rcp->rc_yoffset += RADEON_PANINCREMENT; 3050 } 3051 while (x < rcp->rc_xoffset) { 3052 rcp->rc_xoffset -= RADEON_PANINCREMENT; 3053 } 3054 while (x >= (rcp->rc_xoffset + rcp->rc_videomode.hdisplay)) { 3055 rcp->rc_xoffset += RADEON_PANINCREMENT; 3056 } 3057 3058 /* adjust for the cursor's hotspot */ 3059 x -= dp->rd_cursor.rc_hot.x; 3060 y -= dp->rd_cursor.rc_hot.y; 3061 xoff = yoff = 0; 3062 3063 if (x >= dp->rd_virtx) 3064 x = dp->rd_virtx - 1; 3065 if (y >= dp->rd_virty) 3066 y = dp->rd_virty - 1; 3067 3068 /* now adjust cursor so it is relative to viewport */ 3069 x -= rcp->rc_xoffset; 3070 y -= rcp->rc_yoffset; 3071 3072 /* 3073 * no need to check for fall off, because we should 3074 * never move off the screen entirely! 3075 */ 3076 coff = 0; 3077 if (x < 0) { 3078 xoff = -x; 3079 x = 0; 3080 } 3081 if (y < 0) { 3082 yoff = -y; 3083 y = 0; 3084 coff = (yoff * 2) * 8; 3085 } 3086 3087 /* pan the display */ 3088 PUT32(sc, crtcoff, (rcp->rc_yoffset * dp->rd_stride) + 3089 rcp->rc_xoffset); 3090 3091 PUT32(sc, offset, (dp->rd_curoff + coff) | RADEON_CUR_LOCK); 3092 PUT32(sc, hvoff, (xoff << 16) | (yoff) | RADEON_CUR_LOCK); 3093 /* NB: this unlocks the cursor */ 3094 PUT32(sc, hvpos, (x << 16) | y); 3095 } 3096 } 3097 3098 static void 3099 radeonfb_cursor_visible(struct radeonfb_display *dp) 3100 { 3101 int i; 3102 uint32_t gencntl, bit; 3103 3104 for (i = 0; i < dp->rd_ncrtcs; i++) { 3105 if (dp->rd_crtcs[i].rc_number) { 3106 gencntl = RADEON_CRTC2_GEN_CNTL; 3107 bit = RADEON_CRTC2_CUR_EN; 3108 } else { 3109 gencntl = RADEON_CRTC_GEN_CNTL; 3110 bit = RADEON_CRTC_CUR_EN; 3111 } 3112 3113 if (dp->rd_cursor.rc_visible) 3114 SET32(dp->rd_softc, gencntl, bit); 3115 else 3116 CLR32(dp->rd_softc, gencntl, bit); 3117 } 3118 } 3119 3120 static void 3121 radeonfb_cursor_cmap(struct radeonfb_display *dp) 3122 { 3123 int i; 3124 uint32_t c0reg, c1reg; 3125 struct radeonfb_softc *sc = dp->rd_softc; 3126 3127 for (i = 0; i < dp->rd_ncrtcs; i++) { 3128 if (dp->rd_crtcs[i].rc_number) { 3129 c0reg = RADEON_CUR2_CLR0; 3130 c1reg = RADEON_CUR2_CLR1; 3131 } else { 3132 c0reg = RADEON_CUR_CLR0; 3133 c1reg = RADEON_CUR_CLR1; 3134 } 3135 3136 PUT32(sc, c0reg, dp->rd_cursor.rc_cmap[0]); 3137 PUT32(sc, c1reg, dp->rd_cursor.rc_cmap[1]); 3138 } 3139 } 3140 3141 static void 3142 radeonfb_cursor_update(struct radeonfb_display *dp, unsigned which) 3143 { 3144 struct radeonfb_softc *sc; 3145 int i; 3146 3147 sc = dp->rd_softc; 3148 for (i = 0; i < dp->rd_ncrtcs; i++) { 3149 if (dp->rd_crtcs[i].rc_number) { 3150 SET32(sc, RADEON_CUR2_OFFSET, RADEON_CUR_LOCK); 3151 } else { 3152 SET32(sc, RADEON_CUR_OFFSET,RADEON_CUR_LOCK); 3153 } 3154 } 3155 3156 if (which & WSDISPLAY_CURSOR_DOCMAP) 3157 radeonfb_cursor_cmap(dp); 3158 3159 if (which & WSDISPLAY_CURSOR_DOSHAPE) 3160 radeonfb_cursor_shape(dp); 3161 3162 if (which & WSDISPLAY_CURSOR_DOCUR) 3163 radeonfb_cursor_visible(dp); 3164 3165 /* this one is unconditional, because it updates other stuff */ 3166 radeonfb_cursor_position(dp); 3167 } 3168 3169 static struct videomode * 3170 radeonfb_best_refresh(struct videomode *m1, struct videomode *m2) 3171 { 3172 int r1, r2; 3173 3174 /* otherwise pick the higher refresh rate */ 3175 r1 = DIVIDE(DIVIDE(m1->dot_clock, m1->htotal), m1->vtotal); 3176 r2 = DIVIDE(DIVIDE(m2->dot_clock, m2->htotal), m2->vtotal); 3177 3178 return (r1 < r2 ? m2 : m1); 3179 } 3180 3181 static const struct videomode * 3182 radeonfb_port_mode(struct radeonfb_softc *sc, struct radeonfb_port *rp, 3183 int x, int y) 3184 { 3185 struct edid_info *ep = &rp->rp_edid; 3186 struct videomode *vmp = NULL; 3187 int i; 3188 3189 if (!rp->rp_edid_valid) { 3190 /* fallback to safe mode */ 3191 return radeonfb_modelookup(sc->sc_defaultmode); 3192 } 3193 3194 /* always choose the preferred mode first! */ 3195 if (ep->edid_preferred_mode) { 3196 3197 /* XXX: add auto-stretching support for native mode */ 3198 3199 /* this may want panning to occur, btw */ 3200 if ((ep->edid_preferred_mode->hdisplay <= x) && 3201 (ep->edid_preferred_mode->vdisplay <= y)) 3202 return ep->edid_preferred_mode; 3203 } 3204 3205 for (i = 0; i < ep->edid_nmodes; i++) { 3206 /* 3207 * We elect to pick a resolution that is too large for 3208 * the monitor than one that is too small. This means 3209 * that we will prefer to pan rather than to try to 3210 * center a smaller display on a larger screen. In 3211 * practice, this shouldn't matter because if a 3212 * monitor can support a larger resolution, it can 3213 * probably also support the smaller. A specific 3214 * exception is fixed format panels, but hopefully 3215 * they are properly dealt with by the "autostretch" 3216 * logic above. 3217 */ 3218 if ((ep->edid_modes[i].hdisplay > x) || 3219 (ep->edid_modes[i].vdisplay > y)) { 3220 continue; 3221 } 3222 3223 /* 3224 * at this point, the display mode is no larger than 3225 * what we've requested. 3226 */ 3227 if (vmp == NULL) 3228 vmp = &ep->edid_modes[i]; 3229 3230 /* eliminate smaller modes */ 3231 if ((vmp->hdisplay >= ep->edid_modes[i].hdisplay) || 3232 (vmp->vdisplay >= ep->edid_modes[i].vdisplay)) 3233 continue; 3234 3235 if ((vmp->hdisplay < ep->edid_modes[i].hdisplay) || 3236 (vmp->vdisplay < ep->edid_modes[i].vdisplay)) { 3237 vmp = &ep->edid_modes[i]; 3238 continue; 3239 } 3240 3241 KASSERT(vmp->hdisplay == ep->edid_modes[i].hdisplay); 3242 KASSERT(vmp->vdisplay == ep->edid_modes[i].vdisplay); 3243 3244 vmp = radeonfb_best_refresh(vmp, &ep->edid_modes[i]); 3245 } 3246 3247 return (vmp ? vmp : radeonfb_modelookup(sc->sc_defaultmode)); 3248 } 3249 3250 static int 3251 radeonfb_hasres(struct videomode *list, int nlist, int x, int y) 3252 { 3253 int i; 3254 3255 for (i = 0; i < nlist; i++) { 3256 if ((x == list[i].hdisplay) && 3257 (y == list[i].vdisplay)) { 3258 return 1; 3259 } 3260 } 3261 return 0; 3262 } 3263 3264 static void 3265 radeonfb_pickres(struct radeonfb_display *dp, uint16_t *x, uint16_t *y, 3266 int pan) 3267 { 3268 struct radeonfb_port *rp; 3269 struct edid_info *ep; 3270 int i, j; 3271 3272 *x = 0; 3273 *y = 0; 3274 3275 if (pan) { 3276 for (i = 0; i < dp->rd_ncrtcs; i++) { 3277 rp = dp->rd_crtcs[i].rc_port; 3278 ep = &rp->rp_edid; 3279 if (!rp->rp_edid_valid) { 3280 /* monitor not present */ 3281 continue; 3282 } 3283 3284 /* 3285 * For now we are ignoring "conflict" that 3286 * could occur when mixing some modes like 3287 * 1280x1024 and 1400x800. It isn't clear 3288 * which is better, so the first one wins. 3289 */ 3290 for (j = 0; j < ep->edid_nmodes; j++) { 3291 /* 3292 * ignore resolutions that are too big for 3293 * the radeon 3294 */ 3295 if (ep->edid_modes[j].hdisplay > 3296 dp->rd_softc->sc_maxx) 3297 continue; 3298 if (ep->edid_modes[j].vdisplay > 3299 dp->rd_softc->sc_maxy) 3300 continue; 3301 3302 /* 3303 * pick largest resolution, the 3304 * smaller monitor will pan 3305 */ 3306 if ((ep->edid_modes[j].hdisplay >= *x) && 3307 (ep->edid_modes[j].vdisplay >= *y)) { 3308 *x = ep->edid_modes[j].hdisplay; 3309 *y = ep->edid_modes[j].vdisplay; 3310 } 3311 } 3312 } 3313 3314 } else { 3315 struct videomode modes[64]; 3316 int nmodes = 0; 3317 int valid = 0; 3318 3319 for (i = 0; i < dp->rd_ncrtcs; i++) { 3320 /* 3321 * pick the largest resolution in common. 3322 */ 3323 rp = dp->rd_crtcs[i].rc_port; 3324 ep = &rp->rp_edid; 3325 3326 if (!rp->rp_edid_valid) 3327 continue; 3328 3329 if (!valid) { 3330 /* initialize starting list */ 3331 for (j = 0; j < ep->edid_nmodes; j++) { 3332 /* 3333 * ignore resolutions that are 3334 * too big for the radeon 3335 */ 3336 if (ep->edid_modes[j].hdisplay > 3337 dp->rd_softc->sc_maxx) 3338 continue; 3339 if (ep->edid_modes[j].vdisplay > 3340 dp->rd_softc->sc_maxy) 3341 continue; 3342 3343 modes[nmodes] = ep->edid_modes[j]; 3344 nmodes++; 3345 } 3346 valid = 1; 3347 } else { 3348 /* merge into preexisting list */ 3349 for (j = 0; j < nmodes; j++) { 3350 if (!radeonfb_hasres(ep->edid_modes, 3351 ep->edid_nmodes, 3352 modes[j].hdisplay, 3353 modes[j].vdisplay)) { 3354 modes[j] = modes[nmodes]; 3355 j--; 3356 nmodes--; 3357 } 3358 } 3359 } 3360 } 3361 3362 /* now we have to pick from the merged list */ 3363 for (i = 0; i < nmodes; i++) { 3364 if ((modes[i].hdisplay >= *x) && 3365 (modes[i].vdisplay >= *y)) { 3366 *x = modes[i].hdisplay; 3367 *y = modes[i].vdisplay; 3368 } 3369 } 3370 } 3371 3372 if ((*x == 0) || (*y == 0)) { 3373 /* fallback to safe mode */ 3374 *x = 640; 3375 *y = 480; 3376 } 3377 } 3378 3379 /* 3380 * backlight levels are linear on: 3381 * - RV200, RV250, RV280, RV350 3382 * - but NOT on PowerBook4,3 6,3 6,5 3383 * according to Linux' radeonfb 3384 */ 3385 3386 /* Get the current backlight level for the display. */ 3387 3388 static int 3389 radeonfb_get_backlight(struct radeonfb_display *dp) 3390 { 3391 int s; 3392 uint32_t level; 3393 3394 s = spltty(); 3395 3396 level = radeonfb_get32(dp->rd_softc, RADEON_LVDS_GEN_CNTL); 3397 level &= RADEON_LVDS_BL_MOD_LEV_MASK; 3398 level >>= RADEON_LVDS_BL_MOD_LEV_SHIFT; 3399 3400 /* 3401 * On some chips, we should negate the backlight level. 3402 * XXX Find out on which chips. 3403 */ 3404 if (dp->rd_softc->sc_flags & RFB_INV_BLIGHT) 3405 level = RADEONFB_BACKLIGHT_MAX - level; 3406 3407 splx(s); 3408 3409 return level; 3410 } 3411 3412 /* Set the backlight to the given level for the display. */ 3413 3414 static int 3415 radeonfb_set_backlight(struct radeonfb_display *dp, int level) 3416 { 3417 struct radeonfb_softc *sc; 3418 int rlevel, s; 3419 uint32_t lvds; 3420 3421 s = spltty(); 3422 3423 if (level < 0) 3424 level = 0; 3425 else if (level >= RADEONFB_BACKLIGHT_MAX) 3426 level = RADEONFB_BACKLIGHT_MAX; 3427 3428 sc = dp->rd_softc; 3429 3430 /* On some chips, we should negate the backlight level. */ 3431 if (dp->rd_softc->sc_flags & RFB_INV_BLIGHT) { 3432 rlevel = RADEONFB_BACKLIGHT_MAX - level; 3433 } else 3434 rlevel = level; 3435 3436 callout_stop(&dp->rd_bl_lvds_co); 3437 radeonfb_engine_idle(sc); 3438 3439 /* 3440 * Turn off the display if the backlight is set to 0, since the 3441 * display is useless without backlight anyway. 3442 */ 3443 if (level == 0) 3444 radeonfb_blank(dp, 1); 3445 else if (radeonfb_get_backlight(dp) == 0) 3446 radeonfb_blank(dp, 0); 3447 3448 lvds = radeonfb_get32(sc, RADEON_LVDS_GEN_CNTL); 3449 lvds &= ~RADEON_LVDS_DISPLAY_DIS; 3450 if (!(lvds & RADEON_LVDS_BLON) || !(lvds & RADEON_LVDS_ON)) { 3451 lvds |= dp->rd_bl_lvds_val & RADEON_LVDS_DIGON; 3452 lvds |= RADEON_LVDS_BLON | RADEON_LVDS_EN; 3453 radeonfb_put32(sc, RADEON_LVDS_GEN_CNTL, lvds); 3454 lvds &= ~RADEON_LVDS_BL_MOD_LEV_MASK; 3455 lvds |= rlevel << RADEON_LVDS_BL_MOD_LEV_SHIFT; 3456 lvds |= RADEON_LVDS_ON; 3457 lvds |= dp->rd_bl_lvds_val & RADEON_LVDS_BL_MOD_EN; 3458 } else { 3459 lvds &= ~RADEON_LVDS_BL_MOD_LEV_MASK; 3460 lvds |= rlevel << RADEON_LVDS_BL_MOD_LEV_SHIFT; 3461 radeonfb_put32(sc, RADEON_LVDS_GEN_CNTL, lvds); 3462 } 3463 3464 dp->rd_bl_lvds_val &= ~RADEON_LVDS_STATE_MASK; 3465 dp->rd_bl_lvds_val |= lvds & RADEON_LVDS_STATE_MASK; 3466 /* XXX What is the correct delay? */ 3467 callout_schedule(&dp->rd_bl_lvds_co, 200 * hz); 3468 3469 splx(s); 3470 3471 return 0; 3472 } 3473 3474 /* 3475 * Callout function for delayed operations on the LVDS_GEN_CNTL register. 3476 * Set the delayed bits in the register, and clear the stored delayed 3477 * value. 3478 */ 3479 3480 static void radeonfb_lvds_callout(void *arg) 3481 { 3482 struct radeonfb_display *dp = arg; 3483 int s; 3484 3485 s = splhigh(); 3486 3487 radeonfb_mask32(dp->rd_softc, RADEON_LVDS_GEN_CNTL, ~0, 3488 dp->rd_bl_lvds_val); 3489 dp->rd_bl_lvds_val = 0; 3490 3491 splx(s); 3492 } 3493
Indexes created Sun Sep 28 16:09:52 GMT 2025