radeonfb.c revision 1.34.2.3
1 /* $NetBSD: radeonfb.c,v 1.34.2.3 2010/11/06 08:08:31 uebayasi Exp $ */ 2 3 /*- 4 * Copyright (c) 2006 Itronix Inc. 5 * All rights reserved. 6 * 7 * Written by Garrett D'Amore for Itronix Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. The name of Itronix Inc. may not be used to endorse 18 * or promote products derived from this software without specific 19 * prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY ITRONIX INC. ``AS IS'' AND ANY EXPRESS 22 * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 23 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL ITRONIX INC. BE LIABLE FOR ANY 25 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE 27 * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 29 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 30 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 31 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * ATI Technologies Inc. ("ATI") has not assisted in the creation of, and 36 * does not endorse, this software. ATI will not be responsible or liable 37 * for any actual or alleged damage or loss caused by or in connection with 38 * the use of or reliance on this software. 39 */ 40 41 /* 42 * Portions of this code were taken from XFree86's Radeon driver, which bears 43 * this notice: 44 * 45 * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and 46 * VA Linux Systems Inc., Fremont, California. 47 * 48 * All Rights Reserved. 49 * 50 * Permission is hereby granted, free of charge, to any person obtaining 51 * a copy of this software and associated documentation files (the 52 * "Software"), to deal in the Software without restriction, including 53 * without limitation on the rights to use, copy, modify, merge, 54 * publish, distribute, sublicense, and/or sell copies of the Software, 55 * and to permit persons to whom the Software is furnished to do so, 56 * subject to the following conditions: 57 * 58 * The above copyright notice and this permission notice (including the 59 * next paragraph) shall be included in all copies or substantial 60 * portions of the Software. 61 * 62 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 63 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 64 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 65 * NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR 66 * THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 67 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 68 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 69 * DEALINGS IN THE SOFTWARE. 70 */ 71 72 #include <sys/cdefs.h> 73 __KERNEL_RCSID(0, "$NetBSD: radeonfb.c,v 1.34.2.3 2010/11/06 08:08:31 uebayasi Exp $"); 74 75 #define RADEONFB_DEFAULT_DEPTH 8 76 77 #include <sys/param.h> 78 #include <sys/systm.h> 79 #include <sys/device.h> 80 #include <sys/malloc.h> 81 #include <sys/bus.h> 82 #include <sys/kernel.h> 83 #include <sys/lwp.h> 84 #include <sys/kauth.h> 85 86 #include <dev/wscons/wsdisplayvar.h> 87 #include <dev/wscons/wsconsio.h> 88 #include <dev/wsfont/wsfont.h> 89 #include <dev/rasops/rasops.h> 90 #include <dev/videomode/videomode.h> 91 #include <dev/videomode/edidvar.h> 92 #include <dev/wscons/wsdisplay_vconsvar.h> 93 94 #include <dev/pci/pcidevs.h> 95 #include <dev/pci/pcireg.h> 96 #include <dev/pci/pcivar.h> 97 #include <dev/pci/pciio.h> 98 #include <dev/pci/radeonfbreg.h> 99 #include <dev/pci/radeonfbvar.h> 100 #include "opt_radeonfb.h" 101 102 static int radeonfb_match(device_t, cfdata_t, void *); 103 static void radeonfb_attach(device_t, device_t, void *); 104 static int radeonfb_ioctl(void *, void *, unsigned long, void *, int, 105 struct lwp *); 106 static paddr_t radeonfb_mmap(void *, void *, off_t, int); 107 static int radeonfb_scratch_test(struct radeonfb_softc *, int, uint32_t); 108 static void radeonfb_loadbios(struct radeonfb_softc *, 109 struct pci_attach_args *); 110 111 static uintmax_t radeonfb_getprop_num(struct radeonfb_softc *, const char *, 112 uintmax_t); 113 static int radeonfb_getclocks(struct radeonfb_softc *); 114 static int radeonfb_gettmds(struct radeonfb_softc *); 115 static int radeonfb_calc_dividers(struct radeonfb_softc *, uint32_t, 116 uint32_t *, uint32_t *); 117 static int radeonfb_getconnectors(struct radeonfb_softc *); 118 static const struct videomode *radeonfb_modelookup(const char *); 119 static void radeonfb_init_screen(void *, struct vcons_screen *, int, long *); 120 static void radeonfb_pllwriteupdate(struct radeonfb_softc *, int); 121 static void radeonfb_pllwaitatomicread(struct radeonfb_softc *, int); 122 static void radeonfb_program_vclk(struct radeonfb_softc *, int, int); 123 static void radeonfb_modeswitch(struct radeonfb_display *); 124 static void radeonfb_setcrtc(struct radeonfb_display *, int); 125 static void radeonfb_init_misc(struct radeonfb_softc *); 126 static void radeonfb_set_fbloc(struct radeonfb_softc *); 127 static void radeonfb_init_palette(struct radeonfb_softc *, int); 128 static void radeonfb_r300cg_workaround(struct radeonfb_softc *); 129 130 static int radeonfb_isblank(struct radeonfb_display *); 131 static void radeonfb_blank(struct radeonfb_display *, int); 132 static int radeonfb_set_cursor(struct radeonfb_display *, 133 struct wsdisplay_cursor *); 134 static int radeonfb_set_curpos(struct radeonfb_display *, 135 struct wsdisplay_curpos *); 136 137 /* acceleration support */ 138 static void radeonfb_rectfill(struct radeonfb_display *, int dstx, int dsty, 139 int width, int height, uint32_t color); 140 static void radeonfb_bitblt(struct radeonfb_display *, int srcx, int srcy, 141 int dstx, int dsty, int width, int height, int rop, uint32_t mask); 142 static void radeonfb_feed_bytes(struct radeonfb_display *, int, uint8_t *); 143 static void radeonfb_setup_mono(struct radeonfb_display *, int, int, int, 144 int, uint32_t, uint32_t); 145 146 /* hw cursor support */ 147 static void radeonfb_cursor_cmap(struct radeonfb_display *); 148 static void radeonfb_cursor_shape(struct radeonfb_display *); 149 static void radeonfb_cursor_position(struct radeonfb_display *); 150 static void radeonfb_cursor_visible(struct radeonfb_display *); 151 static void radeonfb_cursor_update(struct radeonfb_display *, unsigned); 152 153 static void radeonfb_wait_fifo(struct radeonfb_softc *, int); 154 static void radeonfb_engine_idle(struct radeonfb_softc *); 155 static void radeonfb_engine_flush(struct radeonfb_softc *); 156 static void radeonfb_engine_reset(struct radeonfb_softc *); 157 static void radeonfb_engine_init(struct radeonfb_display *); 158 static inline void radeonfb_unclip(struct radeonfb_softc *); 159 160 static void radeonfb_eraserows(void *, int, int, long); 161 static void radeonfb_erasecols(void *, int, int, int, long); 162 static void radeonfb_copyrows(void *, int, int, int); 163 static void radeonfb_copycols(void *, int, int, int, int); 164 static void radeonfb_cursor(void *, int, int, int); 165 static void radeonfb_putchar(void *, int, int, unsigned, long); 166 static void radeonfb_putchar_wrapper(void *, int, int, unsigned, long); 167 static int radeonfb_allocattr(void *, int, int, int, long *); 168 169 static int radeonfb_get_backlight(struct radeonfb_display *); 170 static int radeonfb_set_backlight(struct radeonfb_display *, int); 171 static void radeonfb_lvds_callout(void *); 172 173 static void radeonfb_brightness_up(device_t); 174 static void radeonfb_brightness_down(device_t); 175 176 static struct videomode *radeonfb_best_refresh(struct videomode *, 177 struct videomode *); 178 static void radeonfb_pickres(struct radeonfb_display *, uint16_t *, 179 uint16_t *, int); 180 static const struct videomode *radeonfb_port_mode(struct radeonfb_softc *, 181 struct radeonfb_port *, int, int); 182 183 static int radeonfb_drm_print(void *, const char *); 184 185 #ifdef RADEONFB_DEBUG 186 int radeon_debug = 1; 187 #define DPRINTF(x) \ 188 if (radeon_debug) printf x 189 #define PRINTREG(r) DPRINTF((#r " = %08x\n", GET32(sc, r))) 190 #define PRINTPLL(r) DPRINTF((#r " = %08x\n", GETPLL(sc, r))) 191 #else 192 #define DPRINTF(x) 193 #define PRINTREG(r) 194 #define PRINTPLL(r) 195 #endif 196 197 #define ROUNDUP(x,y) (((x) + ((y) - 1)) & ~((y) - 1)) 198 199 #ifndef RADEON_DEFAULT_MODE 200 /* any reasonably modern display should handle this */ 201 #define RADEON_DEFAULT_MODE "1024x768x60" 202 #endif 203 204 extern const u_char rasops_cmap[768]; 205 206 const char *radeonfb_default_mode = RADEON_DEFAULT_MODE; 207 208 static struct { 209 int size; /* minimum memory size (MB) */ 210 int maxx; /* maximum x dimension */ 211 int maxy; /* maximum y dimension */ 212 int maxbpp; /* maximum bpp */ 213 int maxdisp; /* maximum logical display count */ 214 } radeonfb_limits[] = { 215 { 32, 2048, 1536, 32, 2 }, 216 { 16, 1600, 1200, 32, 2 }, 217 { 8, 1600, 1200, 32, 1 }, 218 { 0, 0, 0, 0, 0 }, 219 }; 220 221 static struct wsscreen_descr radeonfb_stdscreen = { 222 "fb", /* name */ 223 0, 0, /* ncols, nrows */ 224 NULL, /* textops */ 225 8, 16, /* fontwidth, fontheight */ 226 WSSCREEN_WSCOLORS | WSSCREEN_REVERSE, /* capabilities */ 227 0, /* modecookie */ 228 }; 229 230 struct wsdisplay_accessops radeonfb_accessops = { 231 radeonfb_ioctl, 232 radeonfb_mmap, 233 NULL, /* vcons_alloc_screen */ 234 NULL, /* vcons_free_screen */ 235 NULL, /* vcons_show_screen */ 236 NULL, /* load_font */ 237 NULL, /* pollc */ 238 NULL, /* scroll */ 239 }; 240 241 static struct { 242 uint16_t devid; 243 uint16_t family; 244 uint16_t flags; 245 } radeonfb_devices[] = 246 { 247 /* R100 family */ 248 { PCI_PRODUCT_ATI_RADEON_R100_QD, RADEON_R100, 0 }, 249 { PCI_PRODUCT_ATI_RADEON_R100_QE, RADEON_R100, 0 }, 250 { PCI_PRODUCT_ATI_RADEON_R100_QF, RADEON_R100, 0 }, 251 { PCI_PRODUCT_ATI_RADEON_R100_QG, RADEON_R100, 0 }, 252 253 /* RV100 family */ 254 { PCI_PRODUCT_ATI_RADEON_RV100_LY, RADEON_RV100, RFB_MOB }, 255 { PCI_PRODUCT_ATI_RADEON_RV100_LZ, RADEON_RV100, RFB_MOB }, 256 { PCI_PRODUCT_ATI_RADEON_RV100_QY, RADEON_RV100, 0 }, 257 { PCI_PRODUCT_ATI_RADEON_RV100_QZ, RADEON_RV100, 0 }, 258 259 /* RS100 family */ 260 { PCI_PRODUCT_ATI_RADEON_RS100_4136, RADEON_RS100, 0 }, 261 { PCI_PRODUCT_ATI_RADEON_RS100_4336, RADEON_RS100, RFB_MOB }, 262 263 /* RS200/RS250 family */ 264 { PCI_PRODUCT_ATI_RADEON_RS200_4337, RADEON_RS200, RFB_MOB }, 265 { PCI_PRODUCT_ATI_RADEON_RS200_A7, RADEON_RS200, 0 }, 266 { PCI_PRODUCT_ATI_RADEON_RS250_B7, RADEON_RS200, RFB_MOB }, 267 { PCI_PRODUCT_ATI_RADEON_RS250_D7, RADEON_RS200, 0 }, 268 269 /* R200 family */ 270 /* add more R200 products? , 5148 */ 271 { PCI_PRODUCT_ATI_RADEON_R200_BB, RADEON_R200, 0 }, 272 { PCI_PRODUCT_ATI_RADEON_R200_BC, RADEON_R200, 0 }, 273 { PCI_PRODUCT_ATI_RADEON_R200_QH, RADEON_R200, 0 }, 274 { PCI_PRODUCT_ATI_RADEON_R200_QL, RADEON_R200, 0 }, 275 { PCI_PRODUCT_ATI_RADEON_R200_QM, RADEON_R200, 0 }, 276 277 /* RV200 family */ 278 { PCI_PRODUCT_ATI_RADEON_RV200_LW, RADEON_RV200, RFB_MOB }, 279 { PCI_PRODUCT_ATI_RADEON_RV200_LX, RADEON_RV200, RFB_MOB }, 280 { PCI_PRODUCT_ATI_RADEON_RV200_QW, RADEON_RV200, 0 }, 281 { PCI_PRODUCT_ATI_RADEON_RV200_QX, RADEON_RV200, 0 }, 282 283 /* RV250 family */ 284 { PCI_PRODUCT_ATI_RADEON_RV250_4966, RADEON_RV250, 0 }, 285 { PCI_PRODUCT_ATI_RADEON_RV250_4967, RADEON_RV250, 0 }, 286 { PCI_PRODUCT_ATI_RADEON_RV250_4C64, RADEON_RV250, RFB_MOB }, 287 { PCI_PRODUCT_ATI_RADEON_RV250_4C66, RADEON_RV250, RFB_MOB }, 288 { PCI_PRODUCT_ATI_RADEON_RV250_4C67, RADEON_RV250, RFB_MOB }, 289 290 /* RS300 family */ 291 { PCI_PRODUCT_ATI_RADEON_RS300_X5, RADEON_RS300, 0 }, 292 { PCI_PRODUCT_ATI_RADEON_RS300_X4, RADEON_RS300, 0 }, 293 { PCI_PRODUCT_ATI_RADEON_RS300_7834, RADEON_RS300, 0 }, 294 { PCI_PRODUCT_ATI_RADEON_RS300_7835, RADEON_RS300, RFB_MOB }, 295 296 /* RV280 family */ 297 { PCI_PRODUCT_ATI_RADEON_RV280_5960, RADEON_RV280, 0 }, 298 { PCI_PRODUCT_ATI_RADEON_RV280_5961, RADEON_RV280, 0 }, 299 { PCI_PRODUCT_ATI_RADEON_RV280_5962, RADEON_RV280, 0 }, 300 { PCI_PRODUCT_ATI_RADEON_RV280_5963, RADEON_RV280, 0 }, 301 { PCI_PRODUCT_ATI_RADEON_RV280_5964, RADEON_RV280, 0 }, 302 { PCI_PRODUCT_ATI_RADEON_RV280_5C61, RADEON_RV280, RFB_MOB }, 303 { PCI_PRODUCT_ATI_RADEON_RV280_5C63, RADEON_RV280, RFB_MOB }, 304 305 /* R300 family */ 306 { PCI_PRODUCT_ATI_RADEON_R300_AD, RADEON_R300, 0 }, 307 { PCI_PRODUCT_ATI_RADEON_R300_AE, RADEON_R300, 0 }, 308 { PCI_PRODUCT_ATI_RADEON_R300_AF, RADEON_R300, 0 }, 309 { PCI_PRODUCT_ATI_RADEON_R300_AG, RADEON_R300, 0 }, 310 { PCI_PRODUCT_ATI_RADEON_R300_ND, RADEON_R300, 0 }, 311 { PCI_PRODUCT_ATI_RADEON_R300_NE, RADEON_R300, 0 }, 312 { PCI_PRODUCT_ATI_RADEON_R300_NF, RADEON_R300, 0 }, 313 { PCI_PRODUCT_ATI_RADEON_R300_NG, RADEON_R300, 0 }, 314 315 /* RV350/RV360 family */ 316 { PCI_PRODUCT_ATI_RADEON_RV350_AP, RADEON_RV350, 0 }, 317 { PCI_PRODUCT_ATI_RADEON_RV350_AQ, RADEON_RV350, 0 }, 318 { PCI_PRODUCT_ATI_RADEON_RV360_AR, RADEON_RV350, 0 }, 319 { PCI_PRODUCT_ATI_RADEON_RV350_AS, RADEON_RV350, 0 }, 320 { PCI_PRODUCT_ATI_RADEON_RV350_AT, RADEON_RV350, 0 }, 321 { PCI_PRODUCT_ATI_RADEON_RV350_AV, RADEON_RV350, 0 }, 322 { PCI_PRODUCT_ATI_RADEON_RV350_NP, RADEON_RV350, RFB_MOB }, 323 { PCI_PRODUCT_ATI_RADEON_RV350_NQ, RADEON_RV350, RFB_MOB }, 324 { PCI_PRODUCT_ATI_RADEON_RV350_NR, RADEON_RV350, RFB_MOB }, 325 { PCI_PRODUCT_ATI_RADEON_RV350_NS, RADEON_RV350, RFB_MOB }, 326 { PCI_PRODUCT_ATI_RADEON_RV350_NT, RADEON_RV350, RFB_MOB }, 327 { PCI_PRODUCT_ATI_RADEON_RV350_NV, RADEON_RV350, RFB_MOB }, 328 329 /* R350/R360 family */ 330 { PCI_PRODUCT_ATI_RADEON_R350_AH, RADEON_R350, 0 }, 331 { PCI_PRODUCT_ATI_RADEON_R350_AI, RADEON_R350, 0 }, 332 { PCI_PRODUCT_ATI_RADEON_R350_AJ, RADEON_R350, 0 }, 333 { PCI_PRODUCT_ATI_RADEON_R350_AK, RADEON_R350, 0 }, 334 { PCI_PRODUCT_ATI_RADEON_R350_NH, RADEON_R350, 0 }, 335 { PCI_PRODUCT_ATI_RADEON_R350_NI, RADEON_R350, 0 }, 336 { PCI_PRODUCT_ATI_RADEON_R350_NK, RADEON_R350, 0 }, 337 { PCI_PRODUCT_ATI_RADEON_R360_NJ, RADEON_R350, 0 }, 338 339 /* RV380/RV370 family */ 340 { PCI_PRODUCT_ATI_RADEON_RV380_3150, RADEON_RV380, RFB_MOB }, 341 { PCI_PRODUCT_ATI_RADEON_RV380_3154, RADEON_RV380, RFB_MOB }, 342 { PCI_PRODUCT_ATI_RADEON_RV380_3E50, RADEON_RV380, 0 }, 343 { PCI_PRODUCT_ATI_RADEON_RV380_3E54, RADEON_RV380, 0 }, 344 { PCI_PRODUCT_ATI_RADEON_RV370_5460, RADEON_RV380, RFB_MOB }, 345 { PCI_PRODUCT_ATI_RADEON_RV370_5464, RADEON_RV380, RFB_MOB }, 346 { PCI_PRODUCT_ATI_RADEON_RV370_5B60, RADEON_RV380, 0 }, 347 { PCI_PRODUCT_ATI_RADEON_RV370_5B64, RADEON_RV380, 0 }, 348 { PCI_PRODUCT_ATI_RADEON_RV370_5B65, RADEON_RV380, 0 }, 349 350 /* R420/R423 family */ 351 { PCI_PRODUCT_ATI_RADEON_R420_JH, RADEON_R420, 0 }, 352 { PCI_PRODUCT_ATI_RADEON_R420_JI, RADEON_R420, 0 }, 353 { PCI_PRODUCT_ATI_RADEON_R420_JJ, RADEON_R420, 0 }, 354 { PCI_PRODUCT_ATI_RADEON_R420_JK, RADEON_R420, 0 }, 355 { PCI_PRODUCT_ATI_RADEON_R420_JL, RADEON_R420, 0 }, 356 { PCI_PRODUCT_ATI_RADEON_R420_JM, RADEON_R420, 0 }, 357 { PCI_PRODUCT_ATI_RADEON_R420_JN, RADEON_R420, RFB_MOB }, 358 { PCI_PRODUCT_ATI_RADEON_R420_JP, RADEON_R420, 0 }, 359 { PCI_PRODUCT_ATI_RADEON_R423_UH, RADEON_R420, 0 }, 360 { PCI_PRODUCT_ATI_RADEON_R423_UI, RADEON_R420, 0 }, 361 { PCI_PRODUCT_ATI_RADEON_R423_UJ, RADEON_R420, 0 }, 362 { PCI_PRODUCT_ATI_RADEON_R423_UK, RADEON_R420, 0 }, 363 { PCI_PRODUCT_ATI_RADEON_R423_UQ, RADEON_R420, 0 }, 364 { PCI_PRODUCT_ATI_RADEON_R423_UR, RADEON_R420, 0 }, 365 { PCI_PRODUCT_ATI_RADEON_R423_UT, RADEON_R420, 0 }, 366 { PCI_PRODUCT_ATI_RADEON_R423_5D57, RADEON_R420, 0 }, 367 { PCI_PRODUCT_ATI_RADEON_R430_554F, RADEON_R420, 0 }, 368 369 { 0, 0, 0 } 370 }; 371 372 static struct { 373 int divider; 374 int mask; 375 } radeonfb_dividers[] = { 376 { 1, 0 }, 377 { 2, 1 }, 378 { 3, 4 }, 379 { 4, 2 }, 380 { 6, 6 }, 381 { 8, 3 }, 382 { 12, 7 }, 383 { 0, 0 } 384 }; 385 386 /* 387 * This table taken from X11. 388 */ 389 static const struct { 390 int family; 391 struct radeon_tmds_pll plls[4]; 392 } radeonfb_tmds_pll[] = { 393 { RADEON_R100, {{12000, 0xa1b}, {-1, 0xa3f}}}, 394 { RADEON_RV100, {{12000, 0xa1b}, {-1, 0xa3f}}}, 395 { RADEON_RS100, {{0, 0}}}, 396 { RADEON_RV200, {{15000, 0xa1b}, {-1, 0xa3f}}}, 397 { RADEON_RS200, {{15000, 0xa1b}, {-1, 0xa3f}}}, 398 { RADEON_R200, {{15000, 0xa1b}, {-1, 0xa3f}}}, 399 { RADEON_RV250, {{15500, 0x81b}, {-1, 0x83f}}}, 400 { RADEON_RS300, {{0, 0}}}, 401 { RADEON_RV280, {{13000, 0x400f4}, {15000, 0x400f7}}}, 402 { RADEON_R300, {{-1, 0xb01cb}}}, 403 { RADEON_R350, {{-1, 0xb01cb}}}, 404 { RADEON_RV350, {{15000, 0xb0155}, {-1, 0xb01cb}}}, 405 { RADEON_RV380, {{15000, 0xb0155}, {-1, 0xb01cb}}}, 406 { RADEON_R420, {{-1, 0xb01cb}}}, 407 }; 408 409 #define RADEONFB_BACKLIGHT_MAX 255 /* Maximum backlight level. */ 410 411 412 CFATTACH_DECL(radeonfb, sizeof (struct radeonfb_softc), 413 radeonfb_match, radeonfb_attach, NULL, NULL); 414 415 static int 416 radeonfb_match(device_t parent, cfdata_t match, void *aux) 417 { 418 struct pci_attach_args *pa = aux; 419 int i; 420 421 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_ATI) 422 return 0; 423 424 for (i = 0; radeonfb_devices[i].devid; i++) { 425 if (PCI_PRODUCT(pa->pa_id) == radeonfb_devices[i].devid) 426 return 100; /* high to defeat VGA/VESA */ 427 } 428 429 return 0; 430 } 431 432 static void 433 radeonfb_attach(device_t parent, device_t dev, void *aux) 434 { 435 struct radeonfb_softc *sc = device_private(dev); 436 struct pci_attach_args *pa = aux; 437 const char *mptr; 438 bus_size_t bsz; 439 pcireg_t screg; 440 int i, j, fg, bg, ul, flags; 441 uint32_t v; 442 443 sc->sc_id = pa->pa_id; 444 for (i = 0; radeonfb_devices[i].devid; i++) { 445 if (PCI_PRODUCT(sc->sc_id) == radeonfb_devices[i].devid) 446 break; 447 } 448 449 pci_devinfo(sc->sc_id, pa->pa_class, 0, sc->sc_devinfo, 450 sizeof(sc->sc_devinfo)); 451 452 aprint_naive("\n"); 453 aprint_normal(": %s\n", sc->sc_devinfo); 454 455 DPRINTF((prop_dictionary_externalize(device_properties(dev)))); 456 457 KASSERT(radeonfb_devices[i].devid != 0); 458 sc->sc_pt = pa->pa_tag; 459 sc->sc_iot = pa->pa_iot; 460 sc->sc_pc = pa->pa_pc; 461 sc->sc_family = radeonfb_devices[i].family; 462 sc->sc_flags = radeonfb_devices[i].flags; 463 464 /* enable memory and IO access */ 465 screg = pci_conf_read(sc->sc_pc, sc->sc_pt, PCI_COMMAND_STATUS_REG); 466 screg |= PCI_FLAGS_IO_ENABLED | PCI_FLAGS_MEM_ENABLED; 467 pci_conf_write(sc->sc_pc, sc->sc_pt, PCI_COMMAND_STATUS_REG, screg); 468 469 /* 470 * Some flags are general to entire chip families, and rather 471 * than clutter up the table with them, we go ahead and set 472 * them here. 473 */ 474 switch (sc->sc_family) { 475 case RADEON_RS100: 476 case RADEON_RS200: 477 sc->sc_flags |= RFB_IGP | RFB_RV100; 478 break; 479 480 case RADEON_RV100: 481 case RADEON_RV200: 482 case RADEON_RV250: 483 case RADEON_RV280: 484 sc->sc_flags |= RFB_RV100; 485 break; 486 487 case RADEON_RS300: 488 sc->sc_flags |= RFB_SDAC | RFB_IGP | RFB_RV100; 489 break; 490 491 case RADEON_R300: 492 case RADEON_RV350: 493 case RADEON_R350: 494 case RADEON_RV380: 495 case RADEON_R420: 496 /* newer chips */ 497 sc->sc_flags |= RFB_R300; 498 break; 499 500 case RADEON_R100: 501 sc->sc_flags |= RFB_NCRTC2; 502 break; 503 } 504 505 if ((sc->sc_family == RADEON_RV200) || 506 (sc->sc_family == RADEON_RV250) || 507 (sc->sc_family == RADEON_RV280) || 508 (sc->sc_family == RADEON_RV350)) { 509 bool inverted = 0; 510 /* backlight level is linear */ 511 DPRINTF(("found RV* chip, backlight is supposedly linear\n")); 512 prop_dictionary_get_bool(device_properties(&sc->sc_dev), 513 "backlight_level_reverted", &inverted); 514 if (inverted) { 515 DPRINTF(("nope, it's inverted\n")); 516 sc->sc_flags |= RFB_INV_BLIGHT; 517 } 518 } else 519 sc->sc_flags |= RFB_INV_BLIGHT; 520 521 /* 522 * XXX: to support true multihead, this must change. 523 */ 524 sc->sc_ndisplays = 1; 525 526 /* XXX: */ 527 if (!HAS_CRTC2(sc)) { 528 sc->sc_ndisplays = 1; 529 } 530 531 if (pci_mapreg_map(pa, RADEON_MAPREG_MMIO, PCI_MAPREG_TYPE_MEM, 0, 532 &sc->sc_regt, &sc->sc_regh, &sc->sc_regaddr, 533 &sc->sc_regsz) != 0) { 534 aprint_error("%s: unable to map registers!\n", XNAME(sc)); 535 goto error; 536 } 537 538 if (pci_mapreg_info(sc->sc_pc, sc->sc_pt, PCI_MAPREG_ROM, 539 PCI_MAPREG_TYPE_ROM, &sc->sc_romaddr, &sc->sc_romsz, &flags) != 0) 540 { 541 aprint_error("%s: unable to find ROM!\n", XNAME(sc)); 542 goto error; 543 } 544 sc->sc_romt = sc->sc_memt; 545 546 /* scratch register test... */ 547 if (radeonfb_scratch_test(sc, RADEON_BIOS_0_SCRATCH, 0x55555555) || 548 radeonfb_scratch_test(sc, RADEON_BIOS_0_SCRATCH, 0xaaaaaaaa)) { 549 aprint_error("%s: scratch register test failed!\n", XNAME(sc)); 550 goto error; 551 } 552 553 PRINTREG(RADEON_BIOS_4_SCRATCH); 554 PRINTREG(RADEON_FP_GEN_CNTL); 555 sc->sc_fp_gen_cntl = GET32(sc, RADEON_FP_GEN_CNTL); 556 PRINTREG(RADEON_FP2_GEN_CNTL); 557 PRINTREG(RADEON_TMDS_CNTL); 558 PRINTREG(RADEON_TMDS_TRANSMITTER_CNTL); 559 PRINTREG(RADEON_TMDS_PLL_CNTL); 560 PRINTREG(RADEON_LVDS_GEN_CNTL); 561 PRINTREG(RADEON_FP_HORZ_STRETCH); 562 PRINTREG(RADEON_FP_VERT_STRETCH); 563 564 /* XXX: RV100 specific */ 565 PUT32(sc, RADEON_TMDS_PLL_CNTL, 0xa27); 566 567 PATCH32(sc, RADEON_TMDS_TRANSMITTER_CNTL, 568 RADEON_TMDS_TRANSMITTER_PLLEN, 569 RADEON_TMDS_TRANSMITTER_PLLEN | RADEON_TMDS_TRANSMITTER_PLLRST); 570 571 radeonfb_i2c_init(sc); 572 573 radeonfb_loadbios(sc, pa); 574 575 #ifdef RADEONFB_BIOS_INIT 576 if (radeonfb_bios_init(sc)) { 577 aprint_error("%s: BIOS inititialization failed\n", XNAME(sc)); 578 } 579 #endif 580 581 if (radeonfb_getclocks(sc)) { 582 aprint_error("%s: Unable to get reference clocks from BIOS\n", 583 XNAME(sc)); 584 goto error; 585 } 586 587 if (radeonfb_gettmds(sc)) { 588 aprint_error("%s: Unable to identify TMDS PLL settings\n", 589 XNAME(sc)); 590 goto error; 591 } 592 593 aprint_verbose("%s: refclk = %d.%03d MHz, refdiv = %d " 594 "minpll = %d, maxpll = %d\n", XNAME(sc), 595 (int)sc->sc_refclk / 1000, (int)sc->sc_refclk % 1000, 596 (int)sc->sc_refdiv, (int)sc->sc_minpll, (int)sc->sc_maxpll); 597 598 radeonfb_getconnectors(sc); 599 600 radeonfb_set_fbloc(sc); 601 602 for (i = 0; radeonfb_limits[i].size; i++) { 603 if (sc->sc_memsz >= radeonfb_limits[i].size) { 604 sc->sc_maxx = radeonfb_limits[i].maxx; 605 sc->sc_maxy = radeonfb_limits[i].maxy; 606 sc->sc_maxbpp = radeonfb_limits[i].maxbpp; 607 /* framebuffer offset, start at a 4K page */ 608 sc->sc_fboffset = sc->sc_memsz / 609 radeonfb_limits[i].maxdisp; 610 /* 611 * we use the fbsize to figure out where we can store 612 * things like cursor data. 613 */ 614 sc->sc_fbsize = 615 ROUNDUP(ROUNDUP(sc->sc_maxx * sc->sc_maxbpp / 8 , 616 RADEON_STRIDEALIGN) * sc->sc_maxy, 617 4096); 618 break; 619 } 620 } 621 622 623 radeonfb_init_misc(sc); 624 radeonfb_init_palette(sc, 0); 625 if (HAS_CRTC2(sc)) 626 radeonfb_init_palette(sc, 1); 627 628 /* program the DAC wirings */ 629 for (i = 0; i < (HAS_CRTC2(sc) ? 2 : 1); i++) { 630 switch (sc->sc_ports[i].rp_dac_type) { 631 case RADEON_DAC_PRIMARY: 632 PATCH32(sc, RADEON_DAC_CNTL2, 633 i ? RADEON_DAC2_DAC_CLK_SEL : 0, 634 ~RADEON_DAC2_DAC_CLK_SEL); 635 break; 636 case RADEON_DAC_TVDAC: 637 /* we always use the TVDAC to drive a secondary analog 638 * CRT for now. if we ever support TV-out this will 639 * have to change. 640 */ 641 SET32(sc, RADEON_DAC_CNTL2, 642 RADEON_DAC2_DAC2_CLK_SEL); 643 PATCH32(sc, RADEON_DISP_HW_DEBUG, 644 i ? 0 : RADEON_CRT2_DISP1_SEL, 645 ~RADEON_CRT2_DISP1_SEL); 646 break; 647 } 648 } 649 PRINTREG(RADEON_DAC_CNTL2); 650 PRINTREG(RADEON_DISP_HW_DEBUG); 651 652 /* other DAC programming */ 653 v = GET32(sc, RADEON_DAC_CNTL); 654 v &= (RADEON_DAC_RANGE_CNTL_MASK | RADEON_DAC_BLANKING); 655 v |= RADEON_DAC_MASK_ALL | RADEON_DAC_8BIT_EN; 656 PUT32(sc, RADEON_DAC_CNTL, v); 657 PRINTREG(RADEON_DAC_CNTL); 658 659 /* XXX: this may need more investigation */ 660 PUT32(sc, RADEON_TV_DAC_CNTL, 0x00280203); 661 PRINTREG(RADEON_TV_DAC_CNTL); 662 663 /* enable TMDS */ 664 SET32(sc, RADEON_FP_GEN_CNTL, 665 RADEON_FP_TMDS_EN | 666 RADEON_FP_CRTC_DONT_SHADOW_VPAR | 667 RADEON_FP_CRTC_DONT_SHADOW_HEND); 668 /* 669 * XXX 670 * no idea why this is necessary - if I do not clear this bit on my 671 * iBook G4 the screen remains black, even though it's already clear. 672 * It needs to be set on my Sun XVR-100 for the DVI port to work 673 */ 674 675 if (sc->sc_fp_gen_cntl & RADEON_FP_SEL_CRTC2) { 676 SET32(sc, RADEON_FP_GEN_CNTL, RADEON_FP_SEL_CRTC2); 677 } else 678 CLR32(sc, RADEON_FP_GEN_CNTL, RADEON_FP_SEL_CRTC2); 679 680 if (HAS_CRTC2(sc)) 681 SET32(sc, RADEON_FP2_GEN_CNTL, RADEON_FP2_SRC_SEL_CRTC2); 682 683 /* 684 * we use bus_space_map instead of pci_mapreg, because we don't 685 * need the full aperature space. no point in wasting virtual 686 * address space we don't intend to use, right? 687 */ 688 if ((sc->sc_memsz < (4096 * 1024)) || 689 (pci_mapreg_info(sc->sc_pc, sc->sc_pt, RADEON_MAPREG_VRAM, 690 PCI_MAPREG_TYPE_MEM, &sc->sc_memaddr, &bsz, NULL) != 0) || 691 (bsz < sc->sc_memsz)) { 692 sc->sc_memsz = 0; 693 aprint_error("%s: Bad frame buffer configuration\n", 694 XNAME(sc)); 695 goto error; 696 } 697 698 /* 64 MB should be enough -- more just wastes map entries */ 699 if (sc->sc_memsz > (64 << 20)) 700 sc->sc_memsz = (64 << 20); 701 702 sc->sc_memt = pa->pa_memt; 703 if (bus_space_map(sc->sc_memt, sc->sc_memaddr, sc->sc_memsz, 704 BUS_SPACE_MAP_LINEAR, &sc->sc_memh) != 0) { 705 sc->sc_memsz = 0; 706 aprint_error("%s: Unable to map frame buffer\n", XNAME(sc)); 707 goto error; 708 } 709 710 aprint_normal("%s: %d MB aperture at 0x%08x, " 711 "%d KB registers at 0x%08x\n", XNAME(sc), 712 (int)sc->sc_memsz >> 20, (unsigned)sc->sc_memaddr, 713 (int)sc->sc_regsz >> 10, (unsigned)sc->sc_regaddr); 714 715 /* setup default video mode from devprop (allows PROM override) */ 716 sc->sc_defaultmode = radeonfb_default_mode; 717 if (prop_dictionary_get_cstring_nocopy(device_properties(&sc->sc_dev), 718 "videomode", &mptr)) { 719 720 strncpy(sc->sc_modebuf, mptr, sizeof(sc->sc_modebuf)); 721 sc->sc_defaultmode = sc->sc_modebuf; 722 } 723 724 /* initialize some basic display parameters */ 725 for (i = 0; i < sc->sc_ndisplays; i++) { 726 struct radeonfb_display *dp = &sc->sc_displays[i]; 727 struct rasops_info *ri; 728 long defattr; 729 struct wsemuldisplaydev_attach_args aa; 730 731 /* 732 * Figure out how many "displays" (desktops) we are going to 733 * support. If more than one, then each CRTC gets its own 734 * programming. 735 * 736 * XXX: this code needs to change to support mergedfb. 737 * XXX: would be nice to allow this to be overridden 738 */ 739 if (HAS_CRTC2(sc) && (sc->sc_ndisplays == 1)) { 740 DPRINTF(("dual crtcs!\n")); 741 dp->rd_ncrtcs = 2; 742 dp->rd_crtcs[0].rc_number = 0; 743 dp->rd_crtcs[1].rc_number = 1; 744 } else { 745 dp->rd_ncrtcs = 1; 746 dp->rd_crtcs[0].rc_number = i; 747 } 748 749 /* set up port pointer */ 750 for (j = 0; j < dp->rd_ncrtcs; j++) { 751 dp->rd_crtcs[j].rc_port = 752 &sc->sc_ports[dp->rd_crtcs[j].rc_number]; 753 } 754 755 dp->rd_softc = sc; 756 dp->rd_wsmode = WSDISPLAYIO_MODE_EMUL; 757 dp->rd_bg = WS_DEFAULT_BG; 758 #if 0 759 dp->rd_bpp = sc->sc_maxbpp; /* XXX: for now */ 760 #else 761 dp->rd_bpp = RADEONFB_DEFAULT_DEPTH; /* XXX */ 762 #endif 763 /* for text mode, we pick a resolution that won't 764 * require panning */ 765 radeonfb_pickres(dp, &dp->rd_virtx, &dp->rd_virty, 0); 766 767 aprint_normal("%s: display %d: " 768 "initial virtual resolution %dx%d at %d bpp\n", 769 XNAME(sc), i, dp->rd_virtx, dp->rd_virty, dp->rd_bpp); 770 771 /* now select the *video mode* that we will use */ 772 for (j = 0; j < dp->rd_ncrtcs; j++) { 773 const struct videomode *vmp; 774 vmp = radeonfb_port_mode(sc, dp->rd_crtcs[j].rc_port, 775 dp->rd_virtx, dp->rd_virty); 776 777 /* 778 * virtual resolution should be at least as high as 779 * physical 780 */ 781 if (dp->rd_virtx < vmp->hdisplay || 782 dp->rd_virty < vmp->vdisplay) { 783 dp->rd_virtx = vmp->hdisplay; 784 dp->rd_virty = vmp->vdisplay; 785 } 786 787 dp->rd_crtcs[j].rc_videomode = *vmp; 788 printf("%s: port %d: physical %dx%d %dHz\n", 789 XNAME(sc), j, vmp->hdisplay, vmp->vdisplay, 790 DIVIDE(DIVIDE(vmp->dot_clock * 1000, 791 vmp->htotal), vmp->vtotal)); 792 } 793 794 /* N.B.: radeon wants 64-byte aligned stride */ 795 dp->rd_stride = dp->rd_virtx * dp->rd_bpp / 8; 796 dp->rd_stride = ROUNDUP(dp->rd_stride, RADEON_STRIDEALIGN); 797 798 dp->rd_offset = sc->sc_fboffset * i; 799 dp->rd_fbptr = (vaddr_t)bus_space_vaddr(sc->sc_memt, 800 sc->sc_memh) + dp->rd_offset; 801 dp->rd_curoff = sc->sc_fbsize; 802 dp->rd_curptr = dp->rd_fbptr + dp->rd_curoff; 803 804 DPRINTF(("fpbtr = %p\n", (void *)dp->rd_fbptr)); 805 806 switch (dp->rd_bpp) { 807 case 8: 808 dp->rd_format = 2; 809 break; 810 case 32: 811 dp->rd_format = 6; 812 break; 813 default: 814 aprint_error("%s: bad depth %d\n", XNAME(sc), 815 dp->rd_bpp); 816 goto error; 817 } 818 819 DPRINTF("init engine\n"); 820 /* XXX: this seems suspicious - per display engine 821 initialization? */ 822 radeonfb_engine_init(dp); 823 824 /* copy the template into place */ 825 dp->rd_wsscreens_storage[0] = radeonfb_stdscreen; 826 dp->rd_wsscreens = dp->rd_wsscreens_storage; 827 828 /* and make up the list */ 829 dp->rd_wsscreenlist.nscreens = 1; 830 dp->rd_wsscreenlist.screens = 831 (const struct wsscreen_descr **)&dp->rd_wsscreens; 832 833 vcons_init(&dp->rd_vd, dp, dp->rd_wsscreens, 834 &radeonfb_accessops); 835 836 dp->rd_vd.init_screen = radeonfb_init_screen; 837 838 dp->rd_console = 0; 839 prop_dictionary_get_bool(device_properties(&sc->sc_dev), 840 "is_console", &dp->rd_console); 841 842 dp->rd_vscreen.scr_flags |= VCONS_SCREEN_IS_STATIC; 843 844 845 vcons_init_screen(&dp->rd_vd, &dp->rd_vscreen, 846 dp->rd_console, &defattr); 847 848 ri = &dp->rd_vscreen.scr_ri; 849 850 /* clear the screen */ 851 rasops_unpack_attr(defattr, &fg, &bg, &ul); 852 radeonfb_rectfill(dp, 0, 0, ri->ri_width, ri->ri_height, 853 ri->ri_devcmap[bg & 0xf]); 854 855 dp->rd_wsscreens->textops = &ri->ri_ops; 856 dp->rd_wsscreens->capabilities = ri->ri_caps; 857 dp->rd_wsscreens->nrows = ri->ri_rows; 858 dp->rd_wsscreens->ncols = ri->ri_cols; 859 860 #ifdef SPLASHSCREEN 861 dp->rd_splash.si_depth = ri->ri_depth; 862 dp->rd_splash.si_bits = ri->ri_bits; 863 dp->rd_splash.si_hwbits = ri->ri_hwbits; 864 dp->rd_splash.si_width = ri->ri_width; 865 dp->rd_splash.si_height = ri->ri_height; 866 dp->rd_splash.si_stride = ri->ri_stride; 867 dp->rd_splash.si_fillrect = NULL; 868 #endif 869 if (dp->rd_console) { 870 871 radeonfb_modeswitch(dp); 872 wsdisplay_cnattach(dp->rd_wsscreens, ri, 0, 0, 873 defattr); 874 #ifdef SPLASHSCREEN 875 splash_render(&dp->rd_splash, 876 SPLASH_F_CENTER|SPLASH_F_FILL); 877 #else 878 vcons_replay_msgbuf(&dp->rd_vscreen); 879 #endif 880 881 #ifdef SPLASHSCREEN_PROGRESS 882 dp->rd_progress.sp_top = (dp->rd_virty / 8) * 7; 883 dp->rd_progress.sp_width = (dp->rd_virtx / 4) * 3; 884 dp->rd_progress.sp_left = (dp->rd_virtx - 885 dp->rd_progress.sp_width) / 2; 886 dp->rd_progress.sp_height = 20; 887 dp->rd_progress.sp_state = -1; 888 dp->rd_progress.sp_si = &dp->rd_splash; 889 splash_progress_init(&dp->rd_progress); 890 SCREEN_DISABLE_DRAWING(&dp->rd_vscreen); 891 #endif 892 893 } else { 894 895 /* 896 * since we're not the console we can postpone 897 * the rest until someone actually allocates a 898 * screen for us. but we do clear the screen 899 * at least. 900 */ 901 memset(ri->ri_bits, 0, 1024); 902 903 radeonfb_modeswitch(dp); 904 #ifdef SPLASHSCREEN 905 splash_render(&dp->rd_splash, 906 SPLASH_F_CENTER|SPLASH_F_FILL); 907 SCREEN_DISABLE_DRAWING(&dp->rd_vscreen); 908 #endif 909 } 910 911 aa.console = dp->rd_console; 912 aa.scrdata = &dp->rd_wsscreenlist; 913 aa.accessops = &radeonfb_accessops; 914 aa.accesscookie = &dp->rd_vd; 915 916 config_found(&sc->sc_dev, &aa, wsemuldisplaydevprint); 917 918 radeonfb_blank(dp, 0); 919 920 /* Initialise delayed lvds operations for backlight. */ 921 callout_init(&dp->rd_bl_lvds_co, 0); 922 callout_setfunc(&dp->rd_bl_lvds_co, 923 radeonfb_lvds_callout, dp); 924 } 925 926 /* 927 * if we have console output via firmware like on sparc64 it may 928 * interfere with DAC programming so program the palette again 929 * here after we took over 930 */ 931 radeonfb_init_palette(sc, 0); 932 if (HAS_CRTC2(sc)) 933 radeonfb_init_palette(sc, 1); 934 935 pmf_event_register(dev, PMFE_DISPLAY_BRIGHTNESS_UP, 936 radeonfb_brightness_up, TRUE); 937 pmf_event_register(dev, PMFE_DISPLAY_BRIGHTNESS_DOWN, 938 radeonfb_brightness_down, TRUE); 939 940 config_found_ia(dev, "drm", aux, radeonfb_drm_print); 941 942 return; 943 944 error: 945 if (sc->sc_biossz) 946 free(sc->sc_bios, M_DEVBUF); 947 948 if (sc->sc_regsz) 949 bus_space_unmap(sc->sc_regt, sc->sc_regh, sc->sc_regsz); 950 951 if (sc->sc_memsz) 952 bus_space_unmap(sc->sc_memt, sc->sc_memh, sc->sc_memsz); 953 } 954 955 static int 956 radeonfb_drm_print(void *aux, const char *pnp) 957 { 958 if (pnp) 959 aprint_normal("drm at %s", pnp); 960 return (UNCONF); 961 } 962 963 int 964 radeonfb_ioctl(void *v, void *vs, 965 unsigned long cmd, void *d, int flag, struct lwp *l) 966 { 967 struct vcons_data *vd; 968 struct radeonfb_display *dp; 969 struct radeonfb_softc *sc; 970 struct wsdisplay_param *param; 971 972 vd = (struct vcons_data *)v; 973 dp = (struct radeonfb_display *)vd->cookie; 974 sc = dp->rd_softc; 975 976 switch (cmd) { 977 case WSDISPLAYIO_GTYPE: 978 *(unsigned *)d = WSDISPLAY_TYPE_PCIMISC; 979 return 0; 980 981 case WSDISPLAYIO_GINFO: 982 if (vd->active != NULL) { 983 struct wsdisplay_fbinfo *fb; 984 fb = (struct wsdisplay_fbinfo *)d; 985 fb->width = dp->rd_virtx; 986 fb->height = dp->rd_virty; 987 fb->depth = dp->rd_bpp; 988 fb->cmsize = 256; 989 return 0; 990 } else 991 return ENODEV; 992 case WSDISPLAYIO_GVIDEO: 993 if (radeonfb_isblank(dp)) 994 *(unsigned *)d = WSDISPLAYIO_VIDEO_OFF; 995 else 996 *(unsigned *)d = WSDISPLAYIO_VIDEO_ON; 997 return 0; 998 999 case WSDISPLAYIO_SVIDEO: 1000 radeonfb_blank(dp, 1001 (*(unsigned int *)d == WSDISPLAYIO_VIDEO_OFF)); 1002 return 0; 1003 1004 case WSDISPLAYIO_GETCMAP: 1005 #if 0 1006 if (dp->rd_bpp == 8) 1007 return radeonfb_getcmap(sc, 1008 (struct wsdisplay_cmap *)d); 1009 #endif 1010 return EINVAL; 1011 1012 case WSDISPLAYIO_PUTCMAP: 1013 #if 0 1014 if (dp->rd_bpp == 8) 1015 return radeonfb_putcmap(sc, 1016 (struct wsdisplay_cmap *)d); 1017 #endif 1018 return EINVAL; 1019 1020 case WSDISPLAYIO_LINEBYTES: 1021 *(unsigned *)d = dp->rd_stride; 1022 return 0; 1023 1024 case WSDISPLAYIO_SMODE: 1025 if (*(int *)d != dp->rd_wsmode) { 1026 dp->rd_wsmode = *(int *)d; 1027 if ((dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) && 1028 (dp->rd_vd.active)) { 1029 radeonfb_engine_init(dp); 1030 radeonfb_init_palette(sc, dp == &sc->sc_displays[0] ? 0 : 1); 1031 radeonfb_modeswitch(dp); 1032 vcons_redraw_screen(dp->rd_vd.active); 1033 } 1034 } 1035 return 0; 1036 1037 case WSDISPLAYIO_GCURMAX: 1038 ((struct wsdisplay_curpos *)d)->x = RADEON_CURSORMAXX; 1039 ((struct wsdisplay_curpos *)d)->y = RADEON_CURSORMAXY; 1040 return 0; 1041 1042 case WSDISPLAYIO_SCURSOR: 1043 return radeonfb_set_cursor(dp, (struct wsdisplay_cursor *)d); 1044 1045 case WSDISPLAYIO_GCURSOR: 1046 return EPASSTHROUGH; 1047 1048 case WSDISPLAYIO_GCURPOS: 1049 ((struct wsdisplay_curpos *)d)->x = dp->rd_cursor.rc_pos.x; 1050 ((struct wsdisplay_curpos *)d)->y = dp->rd_cursor.rc_pos.y; 1051 return 0; 1052 1053 case WSDISPLAYIO_SCURPOS: 1054 return radeonfb_set_curpos(dp, (struct wsdisplay_curpos *)d); 1055 1056 case WSDISPLAYIO_SSPLASH: 1057 #if defined(SPLASHSCREEN) 1058 if (*(int *)d == 1) { 1059 SCREEN_DISABLE_DRAWING(&dp->rd_vscreen); 1060 splash_render(&dp->rd_splash, 1061 SPLASH_F_CENTER|SPLASH_F_FILL); 1062 } else 1063 SCREEN_ENABLE_DRAWING(&dp->rd_vscreen); 1064 return 0; 1065 #else 1066 return ENODEV; 1067 #endif 1068 case WSDISPLAYIO_SPROGRESS: 1069 #if defined(SPLASHSCREEN) && defined(SPLASHSCREEN_PROGRESS) 1070 dp->rd_progress.sp_force = 1; 1071 splash_progress_update(&dp->rd_progress); 1072 dp->rd_progress.sp_force = 0; 1073 return 0; 1074 #else 1075 return ENODEV; 1076 #endif 1077 case WSDISPLAYIO_GETPARAM: 1078 param = (struct wsdisplay_param *)d; 1079 if (param->param == WSDISPLAYIO_PARAM_BACKLIGHT) { 1080 param->min = 0; 1081 param->max = RADEONFB_BACKLIGHT_MAX; 1082 param->curval = radeonfb_get_backlight(dp); 1083 return 0; 1084 } 1085 return EPASSTHROUGH; 1086 1087 case WSDISPLAYIO_SETPARAM: 1088 param = (struct wsdisplay_param *)d; 1089 if (param->param == WSDISPLAYIO_PARAM_BACKLIGHT) { 1090 return radeonfb_set_backlight(dp, param->curval); 1091 } 1092 return EPASSTHROUGH; 1093 1094 /* PCI config read/write passthrough. */ 1095 case PCI_IOC_CFGREAD: 1096 case PCI_IOC_CFGWRITE: 1097 return (pci_devioctl(sc->sc_pc, sc->sc_pt, cmd, d, flag, l)); 1098 1099 default: 1100 return EPASSTHROUGH; 1101 } 1102 } 1103 1104 paddr_t 1105 radeonfb_mmap(void *v, void *vs, off_t offset, int prot) 1106 { 1107 struct vcons_data *vd; 1108 struct radeonfb_display *dp; 1109 struct radeonfb_softc *sc; 1110 paddr_t pa; 1111 1112 vd = (struct vcons_data *)v; 1113 dp = (struct radeonfb_display *)vd->cookie; 1114 sc = dp->rd_softc; 1115 1116 /* XXX: note that we don't allow mapping of registers right now */ 1117 /* XXX: this means that the XFree86 radeon driver won't work */ 1118 if ((offset >= 0) && (offset < (dp->rd_virty * dp->rd_stride))) { 1119 pa = bus_space_mmap(sc->sc_memt, 1120 sc->sc_memaddr + dp->rd_offset + offset, 0, 1121 prot, BUS_SPACE_MAP_LINEAR); 1122 return pa; 1123 } 1124 1125 #ifdef RADEONFB_MMAP_BARS 1126 /* 1127 * restrict all other mappings to processes with superuser privileges 1128 * or the kernel itself 1129 */ 1130 if (kauth_authorize_generic(kauth_cred_get(), KAUTH_GENERIC_ISSUSER, 1131 NULL) != 0) { 1132 aprint_error_dev(&sc->sc_dev, "mmap() rejected.\n"); 1133 return -1; 1134 } 1135 1136 if ((offset >= sc->sc_regaddr) && 1137 (offset < sc->sc_regaddr + sc->sc_regsz)) { 1138 return bus_space_mmap(sc->sc_regt, offset, 0, prot, 1139 BUS_SPACE_MAP_LINEAR); 1140 } 1141 1142 if ((offset >= sc->sc_memaddr) && 1143 (offset < sc->sc_memaddr + sc->sc_memsz)) { 1144 return bus_space_mmap(sc->sc_memt, offset, 0, prot, 1145 BUS_SPACE_MAP_LINEAR); 1146 } 1147 1148 if ((offset >= sc->sc_romaddr) && 1149 (offset < sc->sc_romaddr + sc->sc_romsz)) { 1150 return bus_space_mmap(sc->sc_memt, offset, 0, prot, 1151 BUS_SPACE_MAP_LINEAR); 1152 } 1153 1154 #ifdef PCI_MAGIC_IO_RANGE 1155 /* allow mapping of IO space */ 1156 if ((offset >= PCI_MAGIC_IO_RANGE) && 1157 (offset < PCI_MAGIC_IO_RANGE + 0x10000)) { 1158 pa = bus_space_mmap(sc->sc_iot, offset - PCI_MAGIC_IO_RANGE, 1159 0, prot, 0); 1160 return pa; 1161 } 1162 #endif /* macppc */ 1163 1164 #endif /* RADEONFB_MMAP_BARS */ 1165 1166 return -1; 1167 } 1168 1169 static void 1170 radeonfb_loadbios(struct radeonfb_softc *sc, struct pci_attach_args *pa) 1171 { 1172 bus_space_tag_t romt; 1173 bus_space_handle_t romh, biosh; 1174 bus_size_t romsz; 1175 bus_addr_t ptr; 1176 1177 if (pci_mapreg_map(pa, PCI_MAPREG_ROM, PCI_MAPREG_TYPE_ROM, 1178 BUS_SPACE_MAP_PREFETCHABLE, &romt, &romh, NULL, &romsz) != 0) { 1179 aprint_verbose("%s: unable to map BIOS!\n", XNAME(sc)); 1180 return; 1181 } 1182 1183 pci_find_rom(pa, romt, romh, PCI_ROM_CODE_TYPE_X86, &biosh, 1184 &sc->sc_biossz); 1185 if (sc->sc_biossz == 0) { 1186 aprint_verbose("%s: Video BIOS not present\n", XNAME(sc)); 1187 return; 1188 } 1189 1190 sc->sc_bios = malloc(sc->sc_biossz, M_DEVBUF, M_WAITOK); 1191 bus_space_read_region_1(romt, biosh, 0, sc->sc_bios, sc->sc_biossz); 1192 1193 /* unmap the PCI expansion rom */ 1194 bus_space_unmap(romt, romh, romsz); 1195 1196 /* turn off rom decoder now */ 1197 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM, 1198 pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM) & 1199 ~PCI_MAPREG_ROM_ENABLE); 1200 1201 ptr = GETBIOS16(sc, 0x48); 1202 if ((GETBIOS32(sc, ptr + 4) == 0x41544f4d /* "ATOM" */) || 1203 (GETBIOS32(sc, ptr + 4) == 0x4d4f5441 /* "MOTA" */)) { 1204 sc->sc_flags |= RFB_ATOM; 1205 } 1206 1207 aprint_verbose("%s: Found %d KB %s BIOS\n", XNAME(sc), 1208 (unsigned)sc->sc_biossz >> 10, IS_ATOM(sc) ? "ATOM" : "Legacy"); 1209 } 1210 1211 1212 uint32_t 1213 radeonfb_get32(struct radeonfb_softc *sc, uint32_t reg) 1214 { 1215 1216 return bus_space_read_4(sc->sc_regt, sc->sc_regh, reg); 1217 } 1218 1219 void 1220 radeonfb_put32(struct radeonfb_softc *sc, uint32_t reg, uint32_t val) 1221 { 1222 1223 bus_space_write_4(sc->sc_regt, sc->sc_regh, reg, val); 1224 } 1225 1226 void 1227 radeonfb_mask32(struct radeonfb_softc *sc, uint32_t reg, 1228 uint32_t andmask, uint32_t ormask) 1229 { 1230 int s; 1231 uint32_t val; 1232 1233 s = splhigh(); 1234 val = radeonfb_get32(sc, reg); 1235 val = (val & andmask) | ormask; 1236 radeonfb_put32(sc, reg, val); 1237 splx(s); 1238 } 1239 1240 uint32_t 1241 radeonfb_getindex(struct radeonfb_softc *sc, uint32_t idx) 1242 { 1243 int s; 1244 uint32_t val; 1245 1246 s = splhigh(); 1247 radeonfb_put32(sc, RADEON_MM_INDEX, idx); 1248 val = radeonfb_get32(sc, RADEON_MM_DATA); 1249 splx(s); 1250 1251 return (val); 1252 } 1253 1254 void 1255 radeonfb_putindex(struct radeonfb_softc *sc, uint32_t idx, uint32_t val) 1256 { 1257 int s; 1258 1259 s = splhigh(); 1260 radeonfb_put32(sc, RADEON_MM_INDEX, idx); 1261 radeonfb_put32(sc, RADEON_MM_DATA, val); 1262 splx(s); 1263 } 1264 1265 void 1266 radeonfb_maskindex(struct radeonfb_softc *sc, uint32_t idx, 1267 uint32_t andmask, uint32_t ormask) 1268 { 1269 int s; 1270 uint32_t val; 1271 1272 s = splhigh(); 1273 radeonfb_put32(sc, RADEON_MM_INDEX, idx); 1274 val = radeonfb_get32(sc, RADEON_MM_DATA); 1275 val = (val & andmask) | ormask; 1276 radeonfb_put32(sc, RADEON_MM_DATA, val); 1277 splx(s); 1278 } 1279 1280 uint32_t 1281 radeonfb_getpll(struct radeonfb_softc *sc, uint32_t idx) 1282 { 1283 int s; 1284 uint32_t val; 1285 1286 s = splhigh(); 1287 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, idx & 0x3f); 1288 val = radeonfb_get32(sc, RADEON_CLOCK_CNTL_DATA); 1289 if (HAS_R300CG(sc)) 1290 radeonfb_r300cg_workaround(sc); 1291 splx(s); 1292 1293 return (val); 1294 } 1295 1296 void 1297 radeonfb_putpll(struct radeonfb_softc *sc, uint32_t idx, uint32_t val) 1298 { 1299 int s; 1300 1301 s = splhigh(); 1302 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, (idx & 0x3f) | 1303 RADEON_PLL_WR_EN); 1304 radeonfb_put32(sc, RADEON_CLOCK_CNTL_DATA, val); 1305 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, 0); 1306 splx(s); 1307 } 1308 1309 void 1310 radeonfb_maskpll(struct radeonfb_softc *sc, uint32_t idx, 1311 uint32_t andmask, uint32_t ormask) 1312 { 1313 int s; 1314 uint32_t val; 1315 1316 s = splhigh(); 1317 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, (idx & 0x3f) | 1318 RADEON_PLL_WR_EN); 1319 val = radeonfb_get32(sc, RADEON_CLOCK_CNTL_DATA); 1320 val = (val & andmask) | ormask; 1321 radeonfb_put32(sc, RADEON_CLOCK_CNTL_DATA, val); 1322 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, 0); 1323 splx(s); 1324 } 1325 1326 int 1327 radeonfb_scratch_test(struct radeonfb_softc *sc, int reg, uint32_t v) 1328 { 1329 uint32_t saved; 1330 1331 saved = GET32(sc, reg); 1332 PUT32(sc, reg, v); 1333 if (GET32(sc, reg) != v) { 1334 return -1; 1335 } 1336 PUT32(sc, reg, saved); 1337 return 0; 1338 } 1339 1340 uintmax_t 1341 radeonfb_getprop_num(struct radeonfb_softc *sc, const char *name, 1342 uintmax_t defval) 1343 { 1344 prop_number_t pn; 1345 pn = prop_dictionary_get(device_properties(&sc->sc_dev), name); 1346 if (pn == NULL) { 1347 return defval; 1348 } 1349 KASSERT(prop_object_type(pn) == PROP_TYPE_NUMBER); 1350 return (prop_number_integer_value(pn)); 1351 } 1352 1353 int 1354 radeonfb_getclocks(struct radeonfb_softc *sc) 1355 { 1356 bus_addr_t ptr; 1357 int refclk = 0; 1358 int refdiv = 0; 1359 int minpll = 0; 1360 int maxpll = 0; 1361 1362 /* load initial property values if port/board provides them */ 1363 refclk = radeonfb_getprop_num(sc, "refclk", 0) & 0xffff; 1364 refdiv = radeonfb_getprop_num(sc, "refdiv", 0) & 0xffff; 1365 minpll = radeonfb_getprop_num(sc, "minpll", 0) & 0xffffffffU; 1366 maxpll = radeonfb_getprop_num(sc, "maxpll", 0) & 0xffffffffU; 1367 1368 if (refclk && refdiv && minpll && maxpll) 1369 goto dontprobe; 1370 1371 if (!sc->sc_biossz) { 1372 /* no BIOS */ 1373 aprint_verbose("%s: No video BIOS, using default clocks\n", 1374 XNAME(sc)); 1375 if (IS_IGP(sc)) 1376 refclk = refclk ? refclk : 1432; 1377 else 1378 refclk = refclk ? refclk : 2700; 1379 refdiv = refdiv ? refdiv : 12; 1380 minpll = minpll ? minpll : 12500; 1381 maxpll = maxpll ? maxpll : 35000; 1382 } else if (IS_ATOM(sc)) { 1383 /* ATOM BIOS */ 1384 ptr = GETBIOS16(sc, 0x48); 1385 ptr = GETBIOS16(sc, ptr + 32); /* aka MasterDataStart */ 1386 ptr = GETBIOS16(sc, ptr + 12); /* pll info block */ 1387 refclk = refclk ? refclk : GETBIOS16(sc, ptr + 82); 1388 minpll = minpll ? minpll : GETBIOS16(sc, ptr + 78); 1389 maxpll = maxpll ? maxpll : GETBIOS16(sc, ptr + 32); 1390 /* 1391 * ATOM BIOS doesn't supply a reference divider, so we 1392 * have to probe for it. 1393 */ 1394 if (refdiv < 2) 1395 refdiv = GETPLL(sc, RADEON_PPLL_REF_DIV) & 1396 RADEON_PPLL_REF_DIV_MASK; 1397 /* 1398 * if probe is zero, just assume one that should work 1399 * for most parts 1400 */ 1401 if (refdiv < 2) 1402 refdiv = 12; 1403 1404 } else { 1405 /* Legacy BIOS */ 1406 ptr = GETBIOS16(sc, 0x48); 1407 ptr = GETBIOS16(sc, ptr + 0x30); 1408 refclk = refclk ? refclk : GETBIOS16(sc, ptr + 0x0E); 1409 refdiv = refdiv ? refdiv : GETBIOS16(sc, ptr + 0x10); 1410 minpll = minpll ? minpll : GETBIOS32(sc, ptr + 0x12); 1411 maxpll = maxpll ? maxpll : GETBIOS32(sc, ptr + 0x16); 1412 } 1413 1414 1415 dontprobe: 1416 sc->sc_refclk = refclk * 10; 1417 sc->sc_refdiv = refdiv; 1418 sc->sc_minpll = minpll * 10; 1419 sc->sc_maxpll = maxpll * 10; 1420 return 0; 1421 } 1422 1423 int 1424 radeonfb_calc_dividers(struct radeonfb_softc *sc, uint32_t dotclock, 1425 uint32_t *postdivbit, uint32_t *feedbackdiv) 1426 { 1427 int i; 1428 uint32_t outfreq; 1429 int div; 1430 1431 DPRINTF(("dot clock: %u\n", dotclock)); 1432 for (i = 0; (div = radeonfb_dividers[i].divider) != 0; i++) { 1433 outfreq = div * dotclock; 1434 if ((outfreq >= sc->sc_minpll) && 1435 (outfreq <= sc->sc_maxpll)) { 1436 DPRINTF(("outfreq: %u\n", outfreq)); 1437 *postdivbit = 1438 ((uint32_t)radeonfb_dividers[i].mask << 16); 1439 DPRINTF(("post divider: %d (mask %x)\n", div, 1440 *postdivbit)); 1441 break; 1442 } 1443 } 1444 1445 if (div == 0) 1446 return 1; 1447 1448 *feedbackdiv = DIVIDE(sc->sc_refdiv * outfreq, sc->sc_refclk); 1449 DPRINTF(("feedback divider: %d\n", *feedbackdiv)); 1450 return 0; 1451 } 1452 1453 #if 0 1454 #ifdef RADEONFB_DEBUG 1455 static void 1456 dump_buffer(const char *pfx, void *buffer, unsigned int size) 1457 { 1458 char asc[17]; 1459 unsigned ptr = (unsigned)buffer; 1460 char *start = (char *)(ptr & ~0xf); 1461 char *end = (char *)(ptr + size); 1462 1463 end = (char *)(((unsigned)end + 0xf) & ~0xf); 1464 1465 if (pfx == NULL) { 1466 pfx = ""; 1467 } 1468 1469 while (start < end) { 1470 unsigned offset = (unsigned)start & 0xf; 1471 if (offset == 0) { 1472 printf("%s%x: ", pfx, (unsigned)start); 1473 } 1474 if (((unsigned)start < ptr) || 1475 ((unsigned)start >= (ptr + size))) { 1476 printf(" "); 1477 asc[offset] = ' '; 1478 } else { 1479 printf("%02x", *(unsigned char *)start); 1480 if ((*start >= ' ') && (*start <= '~')) { 1481 asc[offset] = *start; 1482 } else { 1483 asc[offset] = '.'; 1484 } 1485 } 1486 asc[offset + 1] = 0; 1487 if (offset % 2) { 1488 printf(" "); 1489 } 1490 if (offset == 15) { 1491 printf(" %s\n", asc); 1492 } 1493 start++; 1494 } 1495 } 1496 #endif 1497 #endif 1498 1499 int 1500 radeonfb_getconnectors(struct radeonfb_softc *sc) 1501 { 1502 int i; 1503 int found = 0; 1504 1505 for (i = 0; i < 2; i++) { 1506 sc->sc_ports[i].rp_mon_type = RADEON_MT_UNKNOWN; 1507 sc->sc_ports[i].rp_ddc_type = RADEON_DDC_NONE; 1508 sc->sc_ports[i].rp_dac_type = RADEON_DAC_UNKNOWN; 1509 sc->sc_ports[i].rp_conn_type = RADEON_CONN_NONE; 1510 sc->sc_ports[i].rp_tmds_type = RADEON_TMDS_UNKNOWN; 1511 } 1512 1513 /* 1514 * This logic is borrowed from Xorg's radeon driver. 1515 */ 1516 if (!sc->sc_biossz) 1517 goto nobios; 1518 1519 if (IS_ATOM(sc)) { 1520 /* not done yet */ 1521 } else { 1522 uint16_t ptr; 1523 int port = 0; 1524 1525 ptr = GETBIOS16(sc, 0x48); 1526 ptr = GETBIOS16(sc, ptr + 0x50); 1527 for (i = 1; i < 4; i++) { 1528 uint16_t entry; 1529 uint8_t conn, ddc, dac, tmds; 1530 1531 /* 1532 * Parse the connector table. From reading the code, 1533 * it appears to made up of 16-bit entries for each 1534 * connector. The 16-bits are defined as: 1535 * 1536 * bits 12-15 - connector type (0 == end of table) 1537 * bits 8-11 - DDC type 1538 * bits 5-7 - ??? 1539 * bit 4 - TMDS type (1 = EXT, 0 = INT) 1540 * bits 1-3 - ??? 1541 * bit 0 - DAC, 1 = TVDAC, 0 = primary 1542 */ 1543 if (!GETBIOS8(sc, ptr + i * 2) && i > 1) 1544 break; 1545 entry = GETBIOS16(sc, ptr + i * 2); 1546 1547 conn = (entry >> 12) & 0xf; 1548 ddc = (entry >> 8) & 0xf; 1549 dac = (entry & 0x1) ? RADEON_DAC_TVDAC : 1550 RADEON_DAC_PRIMARY; 1551 tmds = ((entry >> 4) & 0x1) ? RADEON_TMDS_EXT : 1552 RADEON_TMDS_INT; 1553 1554 if (conn == RADEON_CONN_NONE) 1555 continue; /* no connector */ 1556 1557 if ((found > 0) && 1558 (sc->sc_ports[port].rp_ddc_type == ddc)) { 1559 /* duplicate entry for same connector */ 1560 continue; 1561 } 1562 1563 /* internal DDC_DVI port gets priority */ 1564 if ((ddc == RADEON_DDC_DVI) || (port == 1)) 1565 port = 0; 1566 else 1567 port = 1; 1568 1569 sc->sc_ports[port].rp_ddc_type = 1570 ddc > RADEON_DDC_CRT2 ? RADEON_DDC_NONE : ddc; 1571 sc->sc_ports[port].rp_dac_type = dac; 1572 sc->sc_ports[port].rp_conn_type = 1573 min(conn, RADEON_CONN_UNSUPPORTED) ; 1574 1575 sc->sc_ports[port].rp_tmds_type = tmds; 1576 1577 if ((conn != RADEON_CONN_DVI_I) && 1578 (conn != RADEON_CONN_DVI_D) && 1579 (tmds == RADEON_TMDS_INT)) 1580 sc->sc_ports[port].rp_tmds_type = 1581 RADEON_TMDS_UNKNOWN; 1582 1583 found += (port + 1); 1584 } 1585 } 1586 1587 nobios: 1588 if (!found) { 1589 DPRINTF(("No connector info in BIOS!\n")); 1590 /* default, port 0 = internal TMDS, port 1 = CRT */ 1591 sc->sc_ports[0].rp_mon_type = RADEON_MT_UNKNOWN; 1592 sc->sc_ports[0].rp_ddc_type = RADEON_DDC_DVI; 1593 sc->sc_ports[0].rp_dac_type = RADEON_DAC_TVDAC; 1594 sc->sc_ports[0].rp_conn_type = RADEON_CONN_DVI_D; 1595 sc->sc_ports[0].rp_tmds_type = RADEON_TMDS_INT; 1596 1597 sc->sc_ports[1].rp_mon_type = RADEON_MT_UNKNOWN; 1598 sc->sc_ports[1].rp_ddc_type = RADEON_DDC_VGA; 1599 sc->sc_ports[1].rp_dac_type = RADEON_DAC_PRIMARY; 1600 sc->sc_ports[1].rp_conn_type = RADEON_CONN_CRT; 1601 sc->sc_ports[1].rp_tmds_type = RADEON_TMDS_EXT; 1602 } 1603 1604 /* 1605 * Fixup for RS300/RS350/RS400 chips, that lack a primary DAC. 1606 * these chips should use TVDAC for the VGA port. 1607 */ 1608 if (HAS_SDAC(sc)) { 1609 if (sc->sc_ports[0].rp_conn_type == RADEON_CONN_CRT) { 1610 sc->sc_ports[0].rp_dac_type = RADEON_DAC_TVDAC; 1611 sc->sc_ports[1].rp_dac_type = RADEON_DAC_PRIMARY; 1612 } else { 1613 sc->sc_ports[1].rp_dac_type = RADEON_DAC_TVDAC; 1614 sc->sc_ports[0].rp_dac_type = RADEON_DAC_PRIMARY; 1615 } 1616 } else if (!HAS_CRTC2(sc)) { 1617 sc->sc_ports[0].rp_dac_type = RADEON_DAC_PRIMARY; 1618 } 1619 1620 for (i = 0; i < 2; i++) { 1621 char edid[128]; 1622 uint8_t ddc; 1623 struct edid_info *eip = &sc->sc_ports[i].rp_edid; 1624 prop_data_t edid_data; 1625 1626 DPRINTF(("Port #%d:\n", i)); 1627 DPRINTF((" conn = %d\n", sc->sc_ports[i].rp_conn_type)); 1628 DPRINTF((" ddc = %d\n", sc->sc_ports[i].rp_ddc_type)); 1629 DPRINTF((" dac = %d\n", sc->sc_ports[i].rp_dac_type)); 1630 DPRINTF((" tmds = %d\n", sc->sc_ports[i].rp_tmds_type)); 1631 1632 sc->sc_ports[i].rp_edid_valid = 0; 1633 /* first look for static EDID data */ 1634 if ((edid_data = prop_dictionary_get(device_properties( 1635 &sc->sc_dev), "EDID")) != NULL) { 1636 1637 aprint_normal_dev(&sc->sc_dev, "using static EDID\n"); 1638 memcpy(edid, prop_data_data_nocopy(edid_data), 128); 1639 if (edid_parse(edid, eip) == 0) { 1640 1641 sc->sc_ports[i].rp_edid_valid = 1; 1642 } 1643 } 1644 /* if we didn't find any we'll try to talk to the monitor */ 1645 if (sc->sc_ports[i].rp_edid_valid != 1) { 1646 1647 ddc = sc->sc_ports[i].rp_ddc_type; 1648 if (ddc != RADEON_DDC_NONE) { 1649 if ((radeonfb_i2c_read_edid(sc, ddc, edid) 1650 == 0) && (edid_parse(edid, eip) == 0)) { 1651 1652 sc->sc_ports[i].rp_edid_valid = 1; 1653 edid_print(eip); 1654 } 1655 } 1656 } 1657 } 1658 1659 return found; 1660 } 1661 1662 int 1663 radeonfb_gettmds(struct radeonfb_softc *sc) 1664 { 1665 int i; 1666 1667 if (!sc->sc_biossz) { 1668 goto nobios; 1669 } 1670 1671 if (IS_ATOM(sc)) { 1672 /* XXX: not done yet */ 1673 } else { 1674 uint16_t ptr; 1675 int n; 1676 1677 ptr = GETBIOS16(sc, 0x48); 1678 ptr = GETBIOS16(sc, ptr + 0x34); 1679 DPRINTF(("DFP table revision %d\n", GETBIOS8(sc, ptr))); 1680 if (GETBIOS8(sc, ptr) == 3) { 1681 /* revision three table */ 1682 n = GETBIOS8(sc, ptr + 5) + 1; 1683 n = min(n, 4); 1684 1685 memset(sc->sc_tmds_pll, 0, sizeof (sc->sc_tmds_pll)); 1686 for (i = 0; i < n; i++) { 1687 sc->sc_tmds_pll[i].rtp_pll = GETBIOS32(sc, 1688 ptr + i * 10 + 8); 1689 sc->sc_tmds_pll[i].rtp_freq = GETBIOS16(sc, 1690 ptr + i * 10 + 0x10); 1691 DPRINTF(("TMDS_PLL dot clock %d pll %x\n", 1692 sc->sc_tmds_pll[i].rtp_freq, 1693 sc->sc_tmds_pll[i].rtp_pll)); 1694 } 1695 return 0; 1696 } 1697 } 1698 1699 nobios: 1700 DPRINTF(("no suitable DFP table present\n")); 1701 for (i = 0; 1702 i < sizeof (radeonfb_tmds_pll) / sizeof (radeonfb_tmds_pll[0]); 1703 i++) { 1704 int j; 1705 1706 if (radeonfb_tmds_pll[i].family != sc->sc_family) 1707 continue; 1708 1709 for (j = 0; j < 4; j++) { 1710 sc->sc_tmds_pll[j] = radeonfb_tmds_pll[i].plls[j]; 1711 DPRINTF(("TMDS_PLL dot clock %d pll %x\n", 1712 sc->sc_tmds_pll[j].rtp_freq, 1713 sc->sc_tmds_pll[j].rtp_pll)); 1714 } 1715 return 0; 1716 } 1717 1718 return -1; 1719 } 1720 1721 const struct videomode * 1722 radeonfb_modelookup(const char *name) 1723 { 1724 int i; 1725 1726 for (i = 0; i < videomode_count; i++) 1727 if (!strcmp(name, videomode_list[i].name)) 1728 return &videomode_list[i]; 1729 1730 return NULL; 1731 } 1732 1733 void 1734 radeonfb_pllwriteupdate(struct radeonfb_softc *sc, int crtc) 1735 { 1736 if (crtc) { 1737 while (GETPLL(sc, RADEON_P2PLL_REF_DIV) & 1738 RADEON_P2PLL_ATOMIC_UPDATE_R); 1739 SETPLL(sc, RADEON_P2PLL_REF_DIV, RADEON_P2PLL_ATOMIC_UPDATE_W); 1740 } else { 1741 while (GETPLL(sc, RADEON_PPLL_REF_DIV) & 1742 RADEON_PPLL_ATOMIC_UPDATE_R); 1743 SETPLL(sc, RADEON_PPLL_REF_DIV, RADEON_PPLL_ATOMIC_UPDATE_W); 1744 } 1745 } 1746 1747 void 1748 radeonfb_pllwaitatomicread(struct radeonfb_softc *sc, int crtc) 1749 { 1750 int i; 1751 1752 for (i = 10000; i; i--) { 1753 if (crtc) { 1754 if (GETPLL(sc, RADEON_P2PLL_REF_DIV) & 1755 RADEON_P2PLL_ATOMIC_UPDATE_R) 1756 break; 1757 } else { 1758 if (GETPLL(sc, RADEON_PPLL_REF_DIV) & 1759 RADEON_PPLL_ATOMIC_UPDATE_R) 1760 break; 1761 } 1762 } 1763 } 1764 1765 void 1766 radeonfb_program_vclk(struct radeonfb_softc *sc, int dotclock, int crtc) 1767 { 1768 uint32_t pbit = 0; 1769 uint32_t feed = 0; 1770 uint32_t data; 1771 #if 1 1772 int i; 1773 #endif 1774 1775 radeonfb_calc_dividers(sc, dotclock, &pbit, &feed); 1776 1777 if (crtc == 0) { 1778 1779 /* XXXX: mobility workaround missing */ 1780 /* XXXX: R300 stuff missing */ 1781 1782 PATCHPLL(sc, RADEON_VCLK_ECP_CNTL, 1783 RADEON_VCLK_SRC_SEL_CPUCLK, 1784 ~RADEON_VCLK_SRC_SEL_MASK); 1785 1786 /* put vclk into reset, use atomic updates */ 1787 SETPLL(sc, RADEON_PPLL_CNTL, 1788 RADEON_PPLL_REFCLK_SEL | 1789 RADEON_PPLL_FBCLK_SEL | 1790 RADEON_PPLL_RESET | 1791 RADEON_PPLL_ATOMIC_UPDATE_EN | 1792 RADEON_PPLL_VGA_ATOMIC_UPDATE_EN); 1793 1794 /* select clock 3 */ 1795 #if 0 1796 PATCH32(sc, RADEON_CLOCK_CNTL_INDEX, RADEON_PLL_DIV_SEL, 1797 ~RADEON_PLL_DIV_SEL); 1798 #else 1799 PATCH32(sc, RADEON_CLOCK_CNTL_INDEX, 0, 1800 ~RADEON_PLL_DIV_SEL); 1801 #endif 1802 1803 /* XXX: R300 family -- program divider differently? */ 1804 1805 /* program reference divider */ 1806 PATCHPLL(sc, RADEON_PPLL_REF_DIV, sc->sc_refdiv, 1807 ~RADEON_PPLL_REF_DIV_MASK); 1808 PRINTPLL(RADEON_PPLL_REF_DIV); 1809 1810 #if 0 1811 data = GETPLL(sc, RADEON_PPLL_DIV_3); 1812 data &= ~(RADEON_PPLL_FB3_DIV_MASK | 1813 RADEON_PPLL_POST3_DIV_MASK); 1814 data |= pbit; 1815 data |= (feed & RADEON_PPLL_FB3_DIV_MASK); 1816 PUTPLL(sc, RADEON_PPLL_DIV_3, data); 1817 #else 1818 for (i = 0; i < 4; i++) { 1819 } 1820 #endif 1821 1822 /* use the atomic update */ 1823 radeonfb_pllwriteupdate(sc, crtc); 1824 1825 /* and wait for it to complete */ 1826 radeonfb_pllwaitatomicread(sc, crtc); 1827 1828 /* program HTOTAL (why?) */ 1829 PUTPLL(sc, RADEON_HTOTAL_CNTL, 0); 1830 1831 /* drop reset */ 1832 CLRPLL(sc, RADEON_PPLL_CNTL, 1833 RADEON_PPLL_RESET | RADEON_PPLL_SLEEP | 1834 RADEON_PPLL_ATOMIC_UPDATE_EN | 1835 RADEON_PPLL_VGA_ATOMIC_UPDATE_EN); 1836 1837 PRINTPLL(RADEON_PPLL_CNTL); 1838 1839 /* give clock time to lock */ 1840 delay(50000); 1841 1842 PATCHPLL(sc, RADEON_VCLK_ECP_CNTL, 1843 RADEON_VCLK_SRC_SEL_PPLLCLK, 1844 ~RADEON_VCLK_SRC_SEL_MASK); 1845 1846 } else { 1847 1848 PATCHPLL(sc, RADEON_PIXCLKS_CNTL, 1849 RADEON_PIX2CLK_SRC_SEL_CPUCLK, 1850 ~RADEON_PIX2CLK_SRC_SEL_MASK); 1851 1852 /* put vclk into reset, use atomic updates */ 1853 SETPLL(sc, RADEON_P2PLL_CNTL, 1854 RADEON_P2PLL_RESET | 1855 RADEON_P2PLL_ATOMIC_UPDATE_EN | 1856 RADEON_P2PLL_VGA_ATOMIC_UPDATE_EN); 1857 1858 /* XXX: R300 family -- program divider differently? */ 1859 1860 /* program reference divider */ 1861 PATCHPLL(sc, RADEON_P2PLL_REF_DIV, sc->sc_refdiv, 1862 ~RADEON_P2PLL_REF_DIV_MASK); 1863 1864 /* program feedback and post dividers */ 1865 data = GETPLL(sc, RADEON_P2PLL_DIV_0); 1866 data &= ~(RADEON_P2PLL_FB0_DIV_MASK | 1867 RADEON_P2PLL_POST0_DIV_MASK); 1868 data |= pbit; 1869 data |= (feed & RADEON_P2PLL_FB0_DIV_MASK); 1870 PUTPLL(sc, RADEON_P2PLL_DIV_0, data); 1871 1872 /* use the atomic update */ 1873 radeonfb_pllwriteupdate(sc, crtc); 1874 1875 /* and wait for it to complete */ 1876 radeonfb_pllwaitatomicread(sc, crtc); 1877 1878 /* program HTOTAL (why?) */ 1879 PUTPLL(sc, RADEON_HTOTAL2_CNTL, 0); 1880 1881 /* drop reset */ 1882 CLRPLL(sc, RADEON_P2PLL_CNTL, 1883 RADEON_P2PLL_RESET | RADEON_P2PLL_SLEEP | 1884 RADEON_P2PLL_ATOMIC_UPDATE_EN | 1885 RADEON_P2PLL_VGA_ATOMIC_UPDATE_EN); 1886 1887 /* allow time for clock to lock */ 1888 delay(50000); 1889 1890 PATCHPLL(sc, RADEON_PIXCLKS_CNTL, 1891 RADEON_PIX2CLK_SRC_SEL_P2PLLCLK, 1892 ~RADEON_PIX2CLK_SRC_SEL_MASK); 1893 } 1894 PRINTREG(RADEON_CRTC_MORE_CNTL); 1895 } 1896 1897 void 1898 radeonfb_modeswitch(struct radeonfb_display *dp) 1899 { 1900 struct radeonfb_softc *sc = dp->rd_softc; 1901 int i; 1902 1903 /* blank the display while we switch modes */ 1904 radeonfb_blank(dp, 1); 1905 1906 #if 0 1907 SET32(sc, RADEON_CRTC_EXT_CNTL, 1908 RADEON_CRTC_VSYNC_DIS | RADEON_CRTC_HSYNC_DIS | 1909 RADEON_CRTC_DISPLAY_DIS /* | RADEON_CRTC_DISP_REQ_EN_B */); 1910 #endif 1911 1912 /* these registers might get in the way... */ 1913 PUT32(sc, RADEON_OVR_CLR, 0); 1914 PUT32(sc, RADEON_OVR_WID_LEFT_RIGHT, 0); 1915 PUT32(sc, RADEON_OVR_WID_TOP_BOTTOM, 0); 1916 PUT32(sc, RADEON_OV0_SCALE_CNTL, 0); 1917 PUT32(sc, RADEON_SUBPIC_CNTL, 0); 1918 PUT32(sc, RADEON_VIPH_CONTROL, 0); 1919 PUT32(sc, RADEON_I2C_CNTL_1, 0); 1920 PUT32(sc, RADEON_GEN_INT_CNTL, 0); 1921 PUT32(sc, RADEON_CAP0_TRIG_CNTL, 0); 1922 PUT32(sc, RADEON_CAP1_TRIG_CNTL, 0); 1923 PUT32(sc, RADEON_SURFACE_CNTL, 0); 1924 1925 for (i = 0; i < dp->rd_ncrtcs; i++) 1926 radeonfb_setcrtc(dp, i); 1927 1928 /* activate the display */ 1929 radeonfb_blank(dp, 0); 1930 } 1931 1932 void 1933 radeonfb_setcrtc(struct radeonfb_display *dp, int index) 1934 { 1935 int crtc; 1936 struct videomode *mode; 1937 struct radeonfb_softc *sc; 1938 struct radeonfb_crtc *cp; 1939 uint32_t v; 1940 uint32_t gencntl; 1941 uint32_t htotaldisp; 1942 uint32_t hsyncstrt; 1943 uint32_t vtotaldisp; 1944 uint32_t vsyncstrt; 1945 uint32_t fphsyncstrt; 1946 uint32_t fpvsyncstrt; 1947 uint32_t fphtotaldisp; 1948 uint32_t fpvtotaldisp; 1949 uint32_t pitch; 1950 1951 sc = dp->rd_softc; 1952 cp = &dp->rd_crtcs[index]; 1953 crtc = cp->rc_number; 1954 mode = &cp->rc_videomode; 1955 1956 #if 1 1957 pitch = (((dp->rd_virtx * dp->rd_bpp) + ((dp->rd_bpp * 8) - 1)) / 1958 (dp->rd_bpp * 8)); 1959 #else 1960 pitch = (((sc->sc_maxx * sc->sc_maxbpp) + ((sc->sc_maxbpp * 8) - 1)) / 1961 (sc->sc_maxbpp * 8)); 1962 #endif 1963 //pitch = pitch | (pitch << 16); 1964 1965 switch (crtc) { 1966 case 0: 1967 gencntl = RADEON_CRTC_GEN_CNTL; 1968 htotaldisp = RADEON_CRTC_H_TOTAL_DISP; 1969 hsyncstrt = RADEON_CRTC_H_SYNC_STRT_WID; 1970 vtotaldisp = RADEON_CRTC_V_TOTAL_DISP; 1971 vsyncstrt = RADEON_CRTC_V_SYNC_STRT_WID; 1972 fpvsyncstrt = RADEON_FP_V_SYNC_STRT_WID; 1973 fphsyncstrt = RADEON_FP_H_SYNC_STRT_WID; 1974 fpvtotaldisp = RADEON_FP_CRTC_V_TOTAL_DISP; 1975 fphtotaldisp = RADEON_FP_CRTC_H_TOTAL_DISP; 1976 break; 1977 case 1: 1978 gencntl = RADEON_CRTC2_GEN_CNTL; 1979 htotaldisp = RADEON_CRTC2_H_TOTAL_DISP; 1980 hsyncstrt = RADEON_CRTC2_H_SYNC_STRT_WID; 1981 vtotaldisp = RADEON_CRTC2_V_TOTAL_DISP; 1982 vsyncstrt = RADEON_CRTC2_V_SYNC_STRT_WID; 1983 fpvsyncstrt = RADEON_FP_V2_SYNC_STRT_WID; 1984 fphsyncstrt = RADEON_FP_H2_SYNC_STRT_WID; 1985 fpvtotaldisp = RADEON_FP_CRTC2_V_TOTAL_DISP; 1986 fphtotaldisp = RADEON_FP_CRTC2_H_TOTAL_DISP; 1987 break; 1988 default: 1989 panic("Bad CRTC!"); 1990 break; 1991 } 1992 1993 /* 1994 * CRTC_GEN_CNTL - depth, accelerator mode, etc. 1995 */ 1996 /* only bother with 32bpp and 8bpp */ 1997 v = dp->rd_format << RADEON_CRTC_PIX_WIDTH_SHIFT; 1998 1999 if (crtc == 1) { 2000 v |= RADEON_CRTC2_CRT2_ON | RADEON_CRTC2_EN; 2001 } else { 2002 v |= RADEON_CRTC_EXT_DISP_EN | RADEON_CRTC_EN; 2003 } 2004 2005 if (mode->flags & VID_DBLSCAN) 2006 v |= RADEON_CRTC2_DBL_SCAN_EN; 2007 2008 if (mode->flags & VID_INTERLACE) 2009 v |= RADEON_CRTC2_INTERLACE_EN; 2010 2011 if (mode->flags & VID_CSYNC) { 2012 v |= RADEON_CRTC2_CSYNC_EN; 2013 if (crtc == 1) 2014 v |= RADEON_CRTC2_VSYNC_TRISTAT; 2015 } 2016 2017 PUT32(sc, gencntl, v); 2018 DPRINTF(("CRTC%s_GEN_CNTL = %08x\n", crtc ? "2" : "", v)); 2019 2020 /* 2021 * CRTC_EXT_CNTL - preserve disable flags, set ATI linear and EXT_CNT 2022 */ 2023 v = GET32(sc, RADEON_CRTC_EXT_CNTL); 2024 if (crtc == 0) { 2025 v &= (RADEON_CRTC_VSYNC_DIS | RADEON_CRTC_HSYNC_DIS | 2026 RADEON_CRTC_DISPLAY_DIS); 2027 v |= RADEON_XCRT_CNT_EN | RADEON_VGA_ATI_LINEAR; 2028 if (mode->flags & VID_CSYNC) 2029 v |= RADEON_CRTC_VSYNC_TRISTAT; 2030 } 2031 /* unconditional turn on CRT, in case first CRTC is DFP */ 2032 v |= RADEON_CRTC_CRT_ON; 2033 PUT32(sc, RADEON_CRTC_EXT_CNTL, v); 2034 PRINTREG(RADEON_CRTC_EXT_CNTL); 2035 2036 /* 2037 * H_TOTAL_DISP 2038 */ 2039 v = ((mode->hdisplay / 8) - 1) << 16; 2040 v |= (mode->htotal / 8) - 1; 2041 PUT32(sc, htotaldisp, v); 2042 DPRINTF(("CRTC%s_H_TOTAL_DISP = %08x\n", crtc ? "2" : "", v)); 2043 PUT32(sc, fphtotaldisp, v); 2044 DPRINTF(("FP_H%s_TOTAL_DISP = %08x\n", crtc ? "2" : "", v)); 2045 2046 /* 2047 * H_SYNC_STRT_WID 2048 */ 2049 v = (((mode->hsync_end - mode->hsync_start) / 8) << 16); 2050 v |= mode->hsync_start; 2051 if (mode->flags & VID_NHSYNC) 2052 v |= RADEON_CRTC_H_SYNC_POL; 2053 PUT32(sc, hsyncstrt, v); 2054 DPRINTF(("CRTC%s_H_SYNC_STRT_WID = %08x\n", crtc ? "2" : "", v)); 2055 PUT32(sc, fphsyncstrt, v); 2056 DPRINTF(("FP_H%s_SYNC_STRT_WID = %08x\n", crtc ? "2" : "", v)); 2057 2058 /* 2059 * V_TOTAL_DISP 2060 */ 2061 v = ((mode->vdisplay - 1) << 16); 2062 v |= (mode->vtotal - 1); 2063 PUT32(sc, vtotaldisp, v); 2064 DPRINTF(("CRTC%s_V_TOTAL_DISP = %08x\n", crtc ? "2" : "", v)); 2065 PUT32(sc, fpvtotaldisp, v); 2066 DPRINTF(("FP_V%s_TOTAL_DISP = %08x\n", crtc ? "2" : "", v)); 2067 2068 /* 2069 * V_SYNC_STRT_WID 2070 */ 2071 v = ((mode->vsync_end - mode->vsync_start) << 16); 2072 v |= (mode->vsync_start - 1); 2073 if (mode->flags & VID_NVSYNC) 2074 v |= RADEON_CRTC_V_SYNC_POL; 2075 PUT32(sc, vsyncstrt, v); 2076 DPRINTF(("CRTC%s_V_SYNC_STRT_WID = %08x\n", crtc ? "2" : "", v)); 2077 PUT32(sc, fpvsyncstrt, v); 2078 DPRINTF(("FP_V%s_SYNC_STRT_WID = %08x\n", crtc ? "2" : "", v)); 2079 2080 radeonfb_program_vclk(sc, mode->dot_clock, crtc); 2081 2082 switch (crtc) { 2083 case 0: 2084 PUT32(sc, RADEON_CRTC_OFFSET, 0); 2085 PUT32(sc, RADEON_CRTC_OFFSET_CNTL, 0); 2086 PUT32(sc, RADEON_CRTC_PITCH, pitch); 2087 CLR32(sc, RADEON_DISP_MERGE_CNTL, RADEON_DISP_RGB_OFFSET_EN); 2088 2089 CLR32(sc, RADEON_CRTC_EXT_CNTL, 2090 RADEON_CRTC_VSYNC_DIS | RADEON_CRTC_HSYNC_DIS | 2091 RADEON_CRTC_DISPLAY_DIS /* | RADEON_CRTC_DISP_REQ_EN_B */); 2092 CLR32(sc, RADEON_CRTC_GEN_CNTL, RADEON_CRTC_DISP_REQ_EN_B); 2093 PRINTREG(RADEON_CRTC_EXT_CNTL); 2094 PRINTREG(RADEON_CRTC_GEN_CNTL); 2095 PRINTREG(RADEON_CLOCK_CNTL_INDEX); 2096 break; 2097 2098 case 1: 2099 PUT32(sc, RADEON_CRTC2_OFFSET, 0); 2100 PUT32(sc, RADEON_CRTC2_OFFSET_CNTL, 0); 2101 PUT32(sc, RADEON_CRTC2_PITCH, pitch); 2102 CLR32(sc, RADEON_DISP2_MERGE_CNTL, RADEON_DISP2_RGB_OFFSET_EN); 2103 CLR32(sc, RADEON_CRTC2_GEN_CNTL, 2104 RADEON_CRTC2_VSYNC_DIS | 2105 RADEON_CRTC2_HSYNC_DIS | 2106 RADEON_CRTC2_DISP_DIS | RADEON_CRTC2_DISP_REQ_EN_B); 2107 PRINTREG(RADEON_CRTC2_GEN_CNTL); 2108 break; 2109 } 2110 } 2111 2112 int 2113 radeonfb_isblank(struct radeonfb_display *dp) 2114 { 2115 uint32_t reg, mask; 2116 2117 if (dp->rd_crtcs[0].rc_number) { 2118 reg = RADEON_CRTC2_GEN_CNTL; 2119 mask = RADEON_CRTC2_DISP_DIS; 2120 } else { 2121 reg = RADEON_CRTC_EXT_CNTL; 2122 mask = RADEON_CRTC_DISPLAY_DIS; 2123 } 2124 return ((GET32(dp->rd_softc, reg) & mask) ? 1 : 0); 2125 } 2126 2127 void 2128 radeonfb_blank(struct radeonfb_display *dp, int blank) 2129 { 2130 struct radeonfb_softc *sc = dp->rd_softc; 2131 uint32_t reg, mask; 2132 uint32_t fpreg, fpval; 2133 int i; 2134 2135 for (i = 0; i < dp->rd_ncrtcs; i++) { 2136 2137 if (dp->rd_crtcs[i].rc_number) { 2138 reg = RADEON_CRTC2_GEN_CNTL; 2139 mask = RADEON_CRTC2_DISP_DIS; 2140 fpreg = RADEON_FP2_GEN_CNTL; 2141 fpval = RADEON_FP2_ON; 2142 } else { 2143 reg = RADEON_CRTC_EXT_CNTL; 2144 mask = RADEON_CRTC_DISPLAY_DIS; 2145 fpreg = RADEON_FP_GEN_CNTL; 2146 fpval = RADEON_FP_FPON; 2147 } 2148 2149 if (blank) { 2150 SET32(sc, reg, mask); 2151 CLR32(sc, fpreg, fpval); 2152 } else { 2153 CLR32(sc, reg, mask); 2154 SET32(sc, fpreg, fpval); 2155 } 2156 } 2157 PRINTREG(RADEON_FP_GEN_CNTL); 2158 PRINTREG(RADEON_FP2_GEN_CNTL); 2159 } 2160 2161 void 2162 radeonfb_init_screen(void *cookie, struct vcons_screen *scr, int existing, 2163 long *defattr) 2164 { 2165 struct radeonfb_display *dp = cookie; 2166 struct rasops_info *ri = &scr->scr_ri; 2167 2168 /* initialize font subsystem */ 2169 wsfont_init(); 2170 2171 DPRINTF(("init screen called, existing %d\n", existing)); 2172 2173 ri->ri_depth = dp->rd_bpp; 2174 ri->ri_width = dp->rd_virtx; 2175 ri->ri_height = dp->rd_virty; 2176 ri->ri_stride = dp->rd_stride; 2177 ri->ri_flg = RI_CENTER; 2178 ri->ri_bits = (void *)dp->rd_fbptr; 2179 2180 /* XXX: 32 bpp only */ 2181 /* this is rgb in "big-endian order..." */ 2182 ri->ri_rnum = 8; 2183 ri->ri_gnum = 8; 2184 ri->ri_bnum = 8; 2185 ri->ri_rpos = 16; 2186 ri->ri_gpos = 8; 2187 ri->ri_bpos = 0; 2188 2189 if (existing) { 2190 ri->ri_flg |= RI_CLEAR; 2191 2192 /* start a modeswitch now */ 2193 radeonfb_modeswitch(dp); 2194 } 2195 2196 /* 2197 * XXX: font selection should be based on properties, with some 2198 * normal/reasonable default. 2199 */ 2200 ri->ri_caps = WSSCREEN_WSCOLORS | WSSCREEN_REVERSE; 2201 2202 /* initialize and look for an initial font */ 2203 rasops_init(ri, dp->rd_virty/8, dp->rd_virtx/8); 2204 2205 rasops_reconfig(ri, dp->rd_virty / ri->ri_font->fontheight, 2206 dp->rd_virtx / ri->ri_font->fontwidth); 2207 2208 /* enable acceleration */ 2209 dp->rd_putchar = ri->ri_ops.putchar; 2210 ri->ri_ops.copyrows = radeonfb_copyrows; 2211 ri->ri_ops.copycols = radeonfb_copycols; 2212 ri->ri_ops.eraserows = radeonfb_eraserows; 2213 ri->ri_ops.erasecols = radeonfb_erasecols; 2214 ri->ri_ops.allocattr = radeonfb_allocattr; 2215 if (!IS_R300(dp->rd_softc)) { 2216 ri->ri_ops.putchar = radeonfb_putchar; 2217 } else { 2218 ri->ri_ops.putchar = radeonfb_putchar_wrapper; 2219 } 2220 ri->ri_ops.cursor = radeonfb_cursor; 2221 } 2222 2223 void 2224 radeonfb_set_fbloc(struct radeonfb_softc *sc) 2225 { 2226 uint32_t gen, ext, gen2 = 0; 2227 uint32_t agploc, aperbase, apersize, mcfbloc; 2228 2229 gen = GET32(sc, RADEON_CRTC_GEN_CNTL); 2230 ext = GET32(sc, RADEON_CRTC_EXT_CNTL); 2231 agploc = GET32(sc, RADEON_MC_AGP_LOCATION); 2232 aperbase = GET32(sc, RADEON_CONFIG_APER_0_BASE); 2233 apersize = GET32(sc, RADEON_CONFIG_APER_SIZE); 2234 2235 PUT32(sc, RADEON_CRTC_GEN_CNTL, gen | RADEON_CRTC_DISP_REQ_EN_B); 2236 PUT32(sc, RADEON_CRTC_EXT_CNTL, ext | RADEON_CRTC_DISPLAY_DIS); 2237 //PUT32(sc, RADEON_CRTC_GEN_CNTL, gen | RADEON_CRTC_DISPLAY_DIS); 2238 //PUT32(sc, RADEON_CRTC_EXT_CNTL, ext | RADEON_CRTC_DISP_REQ_EN_B); 2239 2240 if (HAS_CRTC2(sc)) { 2241 gen2 = GET32(sc, RADEON_CRTC2_GEN_CNTL); 2242 PUT32(sc, RADEON_CRTC2_GEN_CNTL, 2243 gen2 | RADEON_CRTC2_DISP_REQ_EN_B); 2244 } 2245 2246 delay(100000); 2247 2248 mcfbloc = (aperbase >> 16) | 2249 ((aperbase + (apersize - 1)) & 0xffff0000); 2250 2251 sc->sc_aperbase = (mcfbloc & 0xffff) << 16; 2252 sc->sc_memsz = apersize; 2253 2254 if (((agploc & 0xffff) << 16) != 2255 ((mcfbloc & 0xffff0000U) + 0x10000)) { 2256 agploc = mcfbloc & 0xffff0000U; 2257 agploc |= ((agploc + 0x10000) >> 16); 2258 } 2259 2260 PUT32(sc, RADEON_HOST_PATH_CNTL, 0); 2261 2262 PUT32(sc, RADEON_MC_FB_LOCATION, mcfbloc); 2263 PUT32(sc, RADEON_MC_AGP_LOCATION, agploc); 2264 2265 DPRINTF(("aperbase = %u\n", aperbase)); 2266 PRINTREG(RADEON_MC_FB_LOCATION); 2267 PRINTREG(RADEON_MC_AGP_LOCATION); 2268 2269 PUT32(sc, RADEON_DISPLAY_BASE_ADDR, sc->sc_aperbase); 2270 2271 if (HAS_CRTC2(sc)) 2272 PUT32(sc, RADEON_DISPLAY2_BASE_ADDR, sc->sc_aperbase); 2273 2274 PUT32(sc, RADEON_OV0_BASE_ADDR, sc->sc_aperbase); 2275 2276 #if 0 2277 /* XXX: what is this AGP garbage? :-) */ 2278 PUT32(sc, RADEON_AGP_CNTL, 0x00100000); 2279 #endif 2280 2281 delay(100000); 2282 2283 PUT32(sc, RADEON_CRTC_GEN_CNTL, gen); 2284 PUT32(sc, RADEON_CRTC_EXT_CNTL, ext); 2285 2286 if (HAS_CRTC2(sc)) 2287 PUT32(sc, RADEON_CRTC2_GEN_CNTL, gen2); 2288 } 2289 2290 void 2291 radeonfb_init_misc(struct radeonfb_softc *sc) 2292 { 2293 PUT32(sc, RADEON_BUS_CNTL, 2294 RADEON_BUS_MASTER_DIS | 2295 RADEON_BUS_PREFETCH_MODE_ACT | 2296 RADEON_BUS_PCI_READ_RETRY_EN | 2297 RADEON_BUS_PCI_WRT_RETRY_EN | 2298 (3 << RADEON_BUS_RETRY_WS_SHIFT) | 2299 RADEON_BUS_MSTR_RD_MULT | 2300 RADEON_BUS_MSTR_RD_LINE | 2301 RADEON_BUS_RD_DISCARD_EN | 2302 RADEON_BUS_MSTR_DISCONNECT_EN | 2303 RADEON_BUS_READ_BURST); 2304 2305 PUT32(sc, RADEON_BUS_CNTL1, 0xf0); 2306 /* PUT32(sc, RADEON_SEPROM_CNTL1, 0x09ff0000); */ 2307 PUT32(sc, RADEON_FCP_CNTL, RADEON_FCP0_SRC_GND); 2308 PUT32(sc, RADEON_RBBM_CNTL, 2309 (3 << RADEON_RB_SETTLE_SHIFT) | 2310 (4 << RADEON_ABORTCLKS_HI_SHIFT) | 2311 (4 << RADEON_ABORTCLKS_CP_SHIFT) | 2312 (4 << RADEON_ABORTCLKS_CFIFO_SHIFT)); 2313 2314 /* XXX: figure out what these mean! */ 2315 PUT32(sc, RADEON_AGP_CNTL, 0x00100000); 2316 PUT32(sc, RADEON_HOST_PATH_CNTL, 0); 2317 //PUT32(sc, RADEON_DISP_MISC_CNTL, 0x5bb00400); 2318 2319 PUT32(sc, RADEON_GEN_INT_CNTL, 0); 2320 PUT32(sc, RADEON_GEN_INT_STATUS, GET32(sc, RADEON_GEN_INT_STATUS)); 2321 } 2322 2323 /* 2324 * This loads a linear color map for true color. 2325 */ 2326 void 2327 radeonfb_init_palette(struct radeonfb_softc *sc, int crtc) 2328 { 2329 int i; 2330 uint32_t vclk; 2331 2332 #define DAC_WIDTH ((1 << 10) - 1) 2333 #define CLUT_WIDTH ((1 << 8) - 1) 2334 #define CLUT_COLOR(i) ((i * DAC_WIDTH * 2 / CLUT_WIDTH + 1) / 2) 2335 2336 vclk = GETPLL(sc, RADEON_VCLK_ECP_CNTL); 2337 PUTPLL(sc, RADEON_VCLK_ECP_CNTL, vclk & ~RADEON_PIXCLK_DAC_ALWAYS_ONb); 2338 2339 if (crtc) 2340 SET32(sc, RADEON_DAC_CNTL2, RADEON_DAC2_PALETTE_ACC_CTL); 2341 else 2342 CLR32(sc, RADEON_DAC_CNTL2, RADEON_DAC2_PALETTE_ACC_CTL); 2343 2344 PUT32(sc, RADEON_PALETTE_INDEX, 0); 2345 if (sc->sc_displays[crtc].rd_bpp == 0) 2346 sc->sc_displays[crtc].rd_bpp = RADEONFB_DEFAULT_DEPTH; 2347 2348 if (sc->sc_displays[crtc].rd_bpp == 8) { 2349 /* ANSI palette */ 2350 int j = 0; 2351 2352 for (i = 0; i <= CLUT_WIDTH; ++i) { 2353 PUT32(sc, RADEON_PALETTE_30_DATA, 2354 (rasops_cmap[j] << 22) | 2355 (rasops_cmap[j + 1] << 12) | 2356 (rasops_cmap[j + 2] << 2)); 2357 j += 3; 2358 } 2359 } else { 2360 /* linear ramp */ 2361 for (i = 0; i <= CLUT_WIDTH; ++i) { 2362 PUT32(sc, RADEON_PALETTE_30_DATA, 2363 (CLUT_COLOR(i) << 10) | 2364 (CLUT_COLOR(i) << 20) | 2365 (CLUT_COLOR(i))); 2366 } 2367 } 2368 2369 CLR32(sc, RADEON_DAC_CNTL2, RADEON_DAC2_PALETTE_ACC_CTL); 2370 PRINTREG(RADEON_DAC_CNTL2); 2371 2372 PUTPLL(sc, RADEON_VCLK_ECP_CNTL, vclk); 2373 } 2374 2375 /* 2376 * Bugs in some R300 hardware requires this when accessing CLOCK_CNTL_INDEX. 2377 */ 2378 void 2379 radeonfb_r300cg_workaround(struct radeonfb_softc *sc) 2380 { 2381 uint32_t tmp, save; 2382 2383 save = GET32(sc, RADEON_CLOCK_CNTL_INDEX); 2384 tmp = save & ~(0x3f | RADEON_PLL_WR_EN); 2385 PUT32(sc, RADEON_CLOCK_CNTL_INDEX, tmp); 2386 tmp = GET32(sc, RADEON_CLOCK_CNTL_DATA); 2387 PUT32(sc, RADEON_CLOCK_CNTL_INDEX, save); 2388 } 2389 2390 /* 2391 * Acceleration entry points. 2392 */ 2393 static void 2394 radeonfb_putchar(void *cookie, int row, int col, u_int c, long attr) 2395 { 2396 struct rasops_info *ri = cookie; 2397 struct vcons_screen *scr = ri->ri_hw; 2398 struct radeonfb_display *dp = scr->scr_cookie; 2399 struct wsdisplay_font *font = PICK_FONT(ri, c); 2400 uint32_t x, y, w, h; 2401 uint32_t bg, fg, flg; 2402 uint8_t *data; 2403 2404 if (dp->rd_wsmode != WSDISPLAYIO_MODE_EMUL) 2405 return; 2406 2407 if (!CHAR_IN_FONT(c, font)) 2408 return; 2409 2410 w = font->fontwidth; 2411 h = font->fontheight; 2412 2413 flg = attr & 0xff; 2414 if (flg & WSATTR_REVERSE) { 2415 fg = ri->ri_devcmap[(attr >> 16) & 0xf]; 2416 bg = ri->ri_devcmap[(attr >> 24) & 0xf]; 2417 } else { 2418 bg = ri->ri_devcmap[(attr >> 16) & 0xf]; 2419 fg = ri->ri_devcmap[(attr >> 24) & 0xf]; 2420 } 2421 2422 x = ri->ri_xorigin + col * w; 2423 y = ri->ri_yorigin + row * h; 2424 2425 if (c == 0x20) { 2426 radeonfb_rectfill(dp, x, y, w, h, bg); 2427 } else { 2428 data = (uint8_t *)font->data + 2429 (c - font->firstchar) * ri->ri_fontscale; 2430 2431 radeonfb_setup_mono(dp, x, y, w, h, fg, bg); 2432 radeonfb_feed_bytes(dp, ri->ri_fontscale, data); 2433 } 2434 } 2435 2436 /* 2437 * wrapper for software character drawing 2438 * just sync the engine and call rasops*_putchar() 2439 */ 2440 2441 static void 2442 radeonfb_putchar_wrapper(void *cookie, int row, int col, u_int c, long attr) 2443 { 2444 struct rasops_info *ri = cookie; 2445 struct vcons_screen *scr = ri->ri_hw; 2446 struct radeonfb_display *dp = scr->scr_cookie; 2447 2448 radeonfb_engine_idle(dp->rd_softc); 2449 dp->rd_putchar(ri, row, col, c, attr); 2450 } 2451 2452 static void 2453 radeonfb_eraserows(void *cookie, int row, int nrows, long fillattr) 2454 { 2455 struct rasops_info *ri = cookie; 2456 struct vcons_screen *scr = ri->ri_hw; 2457 struct radeonfb_display *dp = scr->scr_cookie; 2458 uint32_t x, y, w, h, fg, bg, ul; 2459 2460 /* XXX: check for full emulation mode? */ 2461 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 2462 x = ri->ri_xorigin; 2463 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 2464 w = ri->ri_emuwidth; 2465 h = ri->ri_font->fontheight * nrows; 2466 2467 rasops_unpack_attr(fillattr, &fg, &bg, &ul); 2468 radeonfb_rectfill(dp, x, y, w, h, ri->ri_devcmap[bg & 0xf]); 2469 } 2470 } 2471 2472 static void 2473 radeonfb_copyrows(void *cookie, int srcrow, int dstrow, int nrows) 2474 { 2475 struct rasops_info *ri = cookie; 2476 struct vcons_screen *scr = ri->ri_hw; 2477 struct radeonfb_display *dp = scr->scr_cookie; 2478 uint32_t x, ys, yd, w, h; 2479 2480 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 2481 x = ri->ri_xorigin; 2482 ys = ri->ri_yorigin + ri->ri_font->fontheight * srcrow; 2483 yd = ri->ri_yorigin + ri->ri_font->fontheight * dstrow; 2484 w = ri->ri_emuwidth; 2485 h = ri->ri_font->fontheight * nrows; 2486 radeonfb_bitblt(dp, x, ys, x, yd, w, h, 2487 RADEON_ROP3_S, 0xffffffff); 2488 } 2489 } 2490 2491 static void 2492 radeonfb_copycols(void *cookie, int row, int srccol, int dstcol, int ncols) 2493 { 2494 struct rasops_info *ri = cookie; 2495 struct vcons_screen *scr = ri->ri_hw; 2496 struct radeonfb_display *dp = scr->scr_cookie; 2497 uint32_t xs, xd, y, w, h; 2498 2499 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 2500 xs = ri->ri_xorigin + ri->ri_font->fontwidth * srccol; 2501 xd = ri->ri_xorigin + ri->ri_font->fontwidth * dstcol; 2502 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 2503 w = ri->ri_font->fontwidth * ncols; 2504 h = ri->ri_font->fontheight; 2505 radeonfb_bitblt(dp, xs, y, xd, y, w, h, 2506 RADEON_ROP3_S, 0xffffffff); 2507 } 2508 } 2509 2510 static void 2511 radeonfb_erasecols(void *cookie, int row, int startcol, int ncols, 2512 long fillattr) 2513 { 2514 struct rasops_info *ri = cookie; 2515 struct vcons_screen *scr = ri->ri_hw; 2516 struct radeonfb_display *dp = scr->scr_cookie; 2517 uint32_t x, y, w, h, fg, bg, ul; 2518 2519 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 2520 x = ri->ri_xorigin + ri->ri_font->fontwidth * startcol; 2521 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 2522 w = ri->ri_font->fontwidth * ncols; 2523 h = ri->ri_font->fontheight; 2524 2525 rasops_unpack_attr(fillattr, &fg, &bg, &ul); 2526 radeonfb_rectfill(dp, x, y, w, h, ri->ri_devcmap[bg & 0xf]); 2527 } 2528 } 2529 2530 static void 2531 radeonfb_cursor(void *cookie, int on, int row, int col) 2532 { 2533 struct rasops_info *ri = cookie; 2534 struct vcons_screen *scr = ri->ri_hw; 2535 struct radeonfb_display *dp = scr->scr_cookie; 2536 int x, y, wi, he; 2537 2538 wi = ri->ri_font->fontwidth; 2539 he = ri->ri_font->fontheight; 2540 2541 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 2542 x = ri->ri_ccol * wi + ri->ri_xorigin; 2543 y = ri->ri_crow * he + ri->ri_yorigin; 2544 /* first turn off the old cursor */ 2545 if (ri->ri_flg & RI_CURSOR) { 2546 radeonfb_bitblt(dp, x, y, x, y, wi, he, 2547 RADEON_ROP3_Dn, 0xffffffff); 2548 ri->ri_flg &= ~RI_CURSOR; 2549 } 2550 ri->ri_crow = row; 2551 ri->ri_ccol = col; 2552 /* then (possibly) turn on the new one */ 2553 if (on) { 2554 x = ri->ri_ccol * wi + ri->ri_xorigin; 2555 y = ri->ri_crow * he + ri->ri_yorigin; 2556 radeonfb_bitblt(dp, x, y, x, y, wi, he, 2557 RADEON_ROP3_Dn, 0xffffffff); 2558 ri->ri_flg |= RI_CURSOR; 2559 } 2560 } else { 2561 scr->scr_ri.ri_crow = row; 2562 scr->scr_ri.ri_ccol = col; 2563 scr->scr_ri.ri_flg &= ~RI_CURSOR; 2564 } 2565 } 2566 2567 static int 2568 radeonfb_allocattr(void *cookie, int fg, int bg, int flags, long *attrp) 2569 { 2570 if ((fg == 0) && (bg == 0)) { 2571 fg = WS_DEFAULT_FG; 2572 bg = WS_DEFAULT_BG; 2573 } 2574 *attrp = ((fg & 0xf) << 24) | ((bg & 0xf) << 16) | (flags & 0xff) << 8; 2575 return 0; 2576 } 2577 2578 /* 2579 * Underlying acceleration support. 2580 */ 2581 static void 2582 radeonfb_setup_mono(struct radeonfb_display *dp, int xd, int yd, int width, 2583 int height, uint32_t fg, uint32_t bg) 2584 { 2585 struct radeonfb_softc *sc = dp->rd_softc; 2586 uint32_t gmc; 2587 uint32_t padded_width = (width+7) & 0xfff8; 2588 uint32_t topleft, bottomright; 2589 2590 gmc = dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT; 2591 2592 if (width != padded_width) { 2593 2594 radeonfb_wait_fifo(sc, 2); 2595 topleft = ((yd << 16) & 0x1fff0000) | (xd & 0x1fff); 2596 bottomright = (((yd + height) << 16) & 0x1fff0000) | 2597 ((xd + width) & 0x1fff); 2598 PUT32(sc, RADEON_SC_TOP_LEFT, topleft); 2599 PUT32(sc, RADEON_SC_BOTTOM_RIGHT, bottomright); 2600 } 2601 2602 radeonfb_wait_fifo(sc, 5); 2603 2604 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 2605 RADEON_GMC_BRUSH_NONE | 2606 RADEON_GMC_SRC_DATATYPE_MONO_FG_BG | 2607 //RADEON_GMC_BYTE_LSB_TO_MSB | 2608 RADEON_GMC_DST_CLIPPING | 2609 RADEON_ROP3_S | 2610 RADEON_DP_SRC_SOURCE_HOST_DATA | 2611 RADEON_GMC_CLR_CMP_CNTL_DIS | 2612 RADEON_GMC_WR_MSK_DIS | 2613 gmc); 2614 2615 PUT32(sc, RADEON_DP_SRC_FRGD_CLR, fg); 2616 PUT32(sc, RADEON_DP_SRC_BKGD_CLR, bg); 2617 2618 PUT32(sc, RADEON_DST_X_Y, (xd << 16) | yd); 2619 PUT32(sc, RADEON_DST_WIDTH_HEIGHT, (padded_width << 16) | height); 2620 2621 } 2622 2623 static void 2624 radeonfb_feed_bytes(struct radeonfb_display *dp, int count, uint8_t *data) 2625 { 2626 struct radeonfb_softc *sc = dp->rd_softc; 2627 int i; 2628 uint32_t latch = 0; 2629 int shift = 0; 2630 2631 for (i = 0; i < count; i++) { 2632 latch |= (data[i] << shift); 2633 if (shift == 24) { 2634 radeonfb_wait_fifo(sc, 1); 2635 PUT32(sc, RADEON_HOST_DATA0, latch); 2636 latch = 0; 2637 shift = 0; 2638 } else 2639 shift += 8; 2640 } 2641 if (shift != 0) { 2642 radeonfb_wait_fifo(sc, 1); 2643 PUT32(sc, RADEON_HOST_DATA0, latch); 2644 } 2645 radeonfb_unclip(sc); 2646 } 2647 2648 static void 2649 radeonfb_rectfill(struct radeonfb_display *dp, int dstx, int dsty, 2650 int width, int height, uint32_t color) 2651 { 2652 struct radeonfb_softc *sc = dp->rd_softc; 2653 uint32_t gmc; 2654 2655 gmc = dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT; 2656 2657 radeonfb_wait_fifo(sc, 6); 2658 2659 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 2660 RADEON_GMC_BRUSH_SOLID_COLOR | 2661 RADEON_GMC_SRC_DATATYPE_COLOR | 2662 RADEON_GMC_CLR_CMP_CNTL_DIS | 2663 RADEON_ROP3_P | gmc); 2664 2665 PUT32(sc, RADEON_DP_BRUSH_FRGD_CLR, color); 2666 PUT32(sc, RADEON_DP_WRITE_MASK, 0xffffffff); 2667 PUT32(sc, RADEON_DP_CNTL, 2668 RADEON_DST_X_LEFT_TO_RIGHT | 2669 RADEON_DST_Y_TOP_TO_BOTTOM); 2670 PUT32(sc, RADEON_DST_Y_X, (dsty << 16) | dstx); 2671 PUT32(sc, RADEON_DST_WIDTH_HEIGHT, (width << 16) | (height)); 2672 2673 /* 2674 * XXX: we don't wait for the fifo to empty -- that would slow 2675 * things down! The linux radeonfb driver waits, but xfree doesn't 2676 */ 2677 /* XXX: for now we do, to make it safe for direct drawing */ 2678 radeonfb_engine_idle(sc); 2679 } 2680 2681 static void 2682 radeonfb_bitblt(struct radeonfb_display *dp, int srcx, int srcy, 2683 int dstx, int dsty, int width, int height, int rop, uint32_t mask) 2684 { 2685 struct radeonfb_softc *sc = dp->rd_softc; 2686 uint32_t gmc; 2687 uint32_t dir; 2688 2689 if (dsty < srcy) { 2690 dir = RADEON_DST_Y_TOP_TO_BOTTOM; 2691 } else { 2692 srcy += height - 1; 2693 dsty += height - 1; 2694 dir = 0; 2695 } 2696 if (dstx < srcx) { 2697 dir |= RADEON_DST_X_LEFT_TO_RIGHT; 2698 } else { 2699 srcx += width - 1; 2700 dstx += width - 1; 2701 } 2702 2703 gmc = dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT; 2704 2705 radeonfb_wait_fifo(sc, 6); 2706 2707 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 2708 //RADEON_GMC_SRC_CLIPPING | 2709 RADEON_GMC_BRUSH_SOLID_COLOR | 2710 RADEON_GMC_SRC_DATATYPE_COLOR | 2711 RADEON_GMC_CLR_CMP_CNTL_DIS | 2712 RADEON_DP_SRC_SOURCE_MEMORY | 2713 rop | gmc); 2714 2715 PUT32(sc, RADEON_DP_WRITE_MASK, mask); 2716 PUT32(sc, RADEON_DP_CNTL, dir); 2717 PUT32(sc, RADEON_SRC_Y_X, (srcy << 16) | srcx); 2718 PUT32(sc, RADEON_DST_Y_X, (dsty << 16) | dstx); 2719 PUT32(sc, RADEON_DST_WIDTH_HEIGHT, (width << 16) | (height)); 2720 2721 /* 2722 * XXX: we don't wait for the fifo to empty -- that would slow 2723 * things down! The linux radeonfb driver waits, but xfree doesn't 2724 */ 2725 /* XXX: for now we do, to make it safe for direct drawing */ 2726 radeonfb_engine_idle(sc); 2727 } 2728 2729 static void 2730 radeonfb_engine_idle(struct radeonfb_softc *sc) 2731 { 2732 int i; 2733 2734 radeonfb_wait_fifo(sc, 64); 2735 for (i = RADEON_TIMEOUT; i; i--) { 2736 if ((GET32(sc, RADEON_RBBM_STATUS) & 2737 RADEON_RBBM_ACTIVE) == 0) { 2738 radeonfb_engine_flush(sc); 2739 break; 2740 } 2741 } 2742 } 2743 2744 static void 2745 radeonfb_wait_fifo(struct radeonfb_softc *sc, int n) 2746 { 2747 int i; 2748 2749 for (i = RADEON_TIMEOUT; i; i--) { 2750 if ((GET32(sc, RADEON_RBBM_STATUS) & 2751 RADEON_RBBM_FIFOCNT_MASK) >= n) 2752 return; 2753 } 2754 #ifdef DIAGNOSTIC 2755 if (!i) 2756 printf("%s: timed out waiting for fifo (%x)\n", 2757 XNAME(sc), GET32(sc, RADEON_RBBM_STATUS)); 2758 #endif 2759 } 2760 2761 static void 2762 radeonfb_engine_flush(struct radeonfb_softc *sc) 2763 { 2764 int i; 2765 SET32(sc, RADEON_RB2D_DSTCACHE_CTLSTAT, RADEON_RB2D_DC_FLUSH_ALL); 2766 for (i = RADEON_TIMEOUT; i; i--) { 2767 if ((GET32(sc, RADEON_RB2D_DSTCACHE_CTLSTAT) & 2768 RADEON_RB2D_DC_BUSY) == 0) 2769 break; 2770 } 2771 #ifdef DIAGNOSTIC 2772 if (!i) 2773 printf("%s: engine flush timed out!\n", XNAME(sc)); 2774 #endif 2775 } 2776 2777 static inline void 2778 radeonfb_unclip(struct radeonfb_softc *sc) 2779 { 2780 2781 radeonfb_wait_fifo(sc, 2); 2782 PUT32(sc, RADEON_SC_TOP_LEFT, 0); 2783 PUT32(sc, RADEON_SC_BOTTOM_RIGHT, 0x1fff1fff); 2784 } 2785 2786 static void 2787 radeonfb_engine_init(struct radeonfb_display *dp) 2788 { 2789 struct radeonfb_softc *sc = dp->rd_softc; 2790 uint32_t pitch; 2791 volatile uint32_t junk; 2792 2793 /* no 3D */ 2794 PUT32(sc, RADEON_RB3D_CNTL, 0); 2795 2796 radeonfb_engine_reset(sc); 2797 pitch = ((dp->rd_virtx * (dp->rd_bpp / 8) + 0x3f)) >> 6; 2798 //pitch = ((sc->sc_maxx * (sc->sc_maxbpp / 8) + 0x3f)) >> 6; 2799 2800 radeonfb_wait_fifo(sc, 1); 2801 if (!IS_R300(sc)) 2802 PUT32(sc, RADEON_RB2D_DSTCACHE_MODE, 0); 2803 2804 radeonfb_wait_fifo(sc, 3); 2805 PUT32(sc, RADEON_DEFAULT_PITCH_OFFSET, 2806 (pitch << 22) | (sc->sc_aperbase >> 10)); 2807 2808 2809 PUT32(sc, RADEON_DST_PITCH_OFFSET, 2810 (pitch << 22) | (sc->sc_aperbase >> 10)); 2811 PUT32(sc, RADEON_SRC_PITCH_OFFSET, 2812 (pitch << 22) | (sc->sc_aperbase >> 10)); 2813 2814 radeonfb_wait_fifo(sc, 1); 2815 #if _BYTE_ORDER == _BIG_ENDIAN 2816 SET32(sc, RADEON_DP_DATATYPE, RADEON_HOST_BIG_ENDIAN_EN); 2817 #else 2818 CLR32(sc, RADEON_DP_DATATYPE, RADEON_HOST_BIG_ENDIAN_EN); 2819 #endif 2820 junk = GET32(sc, RADEON_DP_DATATYPE); 2821 2822 /* default scissors -- no clipping */ 2823 radeonfb_wait_fifo(sc, 1); 2824 PUT32(sc, RADEON_DEFAULT_SC_BOTTOM_RIGHT, 2825 RADEON_DEFAULT_SC_RIGHT_MAX | RADEON_DEFAULT_SC_BOTTOM_MAX); 2826 2827 radeonfb_wait_fifo(sc, 1); 2828 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 2829 (dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT) | 2830 RADEON_GMC_CLR_CMP_CNTL_DIS | 2831 RADEON_GMC_BRUSH_SOLID_COLOR | 2832 RADEON_GMC_SRC_DATATYPE_COLOR); 2833 2834 radeonfb_wait_fifo(sc, 7); 2835 PUT32(sc, RADEON_DST_LINE_START, 0); 2836 PUT32(sc, RADEON_DST_LINE_END, 0); 2837 PUT32(sc, RADEON_DP_BRUSH_FRGD_CLR, 0xffffffff); 2838 PUT32(sc, RADEON_DP_BRUSH_BKGD_CLR, 0); 2839 PUT32(sc, RADEON_DP_SRC_FRGD_CLR, 0xffffffff); 2840 PUT32(sc, RADEON_DP_SRC_BKGD_CLR, 0); 2841 PUT32(sc, RADEON_DP_WRITE_MASK, 0xffffffff); 2842 2843 radeonfb_engine_idle(sc); 2844 } 2845 2846 static void 2847 radeonfb_engine_reset(struct radeonfb_softc *sc) 2848 { 2849 uint32_t hpc, rbbm, mclkcntl, clkindex; 2850 2851 radeonfb_engine_flush(sc); 2852 2853 clkindex = GET32(sc, RADEON_CLOCK_CNTL_INDEX); 2854 if (HAS_R300CG(sc)) 2855 radeonfb_r300cg_workaround(sc); 2856 mclkcntl = GETPLL(sc, RADEON_MCLK_CNTL); 2857 2858 /* 2859 * According to comments in XFree code, resetting the HDP via 2860 * the RBBM_SOFT_RESET can cause bad behavior on some systems. 2861 * So we use HOST_PATH_CNTL instead. 2862 */ 2863 2864 hpc = GET32(sc, RADEON_HOST_PATH_CNTL); 2865 rbbm = GET32(sc, RADEON_RBBM_SOFT_RESET); 2866 if (IS_R300(sc)) { 2867 PUT32(sc, RADEON_RBBM_SOFT_RESET, rbbm | 2868 RADEON_SOFT_RESET_CP | 2869 RADEON_SOFT_RESET_HI | 2870 RADEON_SOFT_RESET_E2); 2871 GET32(sc, RADEON_RBBM_SOFT_RESET); 2872 PUT32(sc, RADEON_RBBM_SOFT_RESET, 0); 2873 /* 2874 * XXX: this bit is not defined in any ATI docs I have, 2875 * nor in the XFree code, but XFree does it. Why? 2876 */ 2877 SET32(sc, RADEON_RB2D_DSTCACHE_MODE, (1<<17)); 2878 } else { 2879 PUT32(sc, RADEON_RBBM_SOFT_RESET, rbbm | 2880 RADEON_SOFT_RESET_CP | 2881 RADEON_SOFT_RESET_SE | 2882 RADEON_SOFT_RESET_RE | 2883 RADEON_SOFT_RESET_PP | 2884 RADEON_SOFT_RESET_E2 | 2885 RADEON_SOFT_RESET_RB); 2886 GET32(sc, RADEON_RBBM_SOFT_RESET); 2887 PUT32(sc, RADEON_RBBM_SOFT_RESET, rbbm & 2888 ~(RADEON_SOFT_RESET_CP | 2889 RADEON_SOFT_RESET_SE | 2890 RADEON_SOFT_RESET_RE | 2891 RADEON_SOFT_RESET_PP | 2892 RADEON_SOFT_RESET_E2 | 2893 RADEON_SOFT_RESET_RB)); 2894 GET32(sc, RADEON_RBBM_SOFT_RESET); 2895 } 2896 2897 PUT32(sc, RADEON_HOST_PATH_CNTL, hpc | RADEON_HDP_SOFT_RESET); 2898 GET32(sc, RADEON_HOST_PATH_CNTL); 2899 PUT32(sc, RADEON_HOST_PATH_CNTL, hpc); 2900 2901 if (IS_R300(sc)) 2902 PUT32(sc, RADEON_RBBM_SOFT_RESET, rbbm); 2903 2904 PUT32(sc, RADEON_CLOCK_CNTL_INDEX, clkindex); 2905 PUTPLL(sc, RADEON_MCLK_CNTL, mclkcntl); 2906 2907 if (HAS_R300CG(sc)) 2908 radeonfb_r300cg_workaround(sc); 2909 } 2910 2911 static int 2912 radeonfb_set_curpos(struct radeonfb_display *dp, struct wsdisplay_curpos *pos) 2913 { 2914 int x, y; 2915 2916 x = pos->x; 2917 y = pos->y; 2918 2919 /* 2920 * This doesn't let a cursor move off the screen. I'm not 2921 * sure if this will have negative effects for e.g. Xinerama. 2922 * I'd guess Xinerama handles it by changing the cursor shape, 2923 * but that needs verification. 2924 */ 2925 if (x >= dp->rd_virtx) 2926 x = dp->rd_virtx - 1; 2927 if (x < 0) 2928 x = 0; 2929 if (y >= dp->rd_virty) 2930 y = dp->rd_virty - 1; 2931 if (y < 0) 2932 y = 0; 2933 2934 dp->rd_cursor.rc_pos.x = x; 2935 dp->rd_cursor.rc_pos.y = y; 2936 2937 radeonfb_cursor_position(dp); 2938 return 0; 2939 } 2940 2941 static int 2942 radeonfb_set_cursor(struct radeonfb_display *dp, struct wsdisplay_cursor *wc) 2943 { 2944 unsigned flags; 2945 2946 uint8_t r[2], g[2], b[2]; 2947 unsigned index, count; 2948 int i, err; 2949 int pitch, size; 2950 struct radeonfb_cursor nc; 2951 2952 flags = wc->which; 2953 2954 /* copy old values */ 2955 nc = dp->rd_cursor; 2956 2957 if (flags & WSDISPLAY_CURSOR_DOCMAP) { 2958 index = wc->cmap.index; 2959 count = wc->cmap.count; 2960 2961 if (index >= 2 || (index + count) > 2) 2962 return EINVAL; 2963 2964 err = copyin(wc->cmap.red, &r[index], count); 2965 if (err) 2966 return err; 2967 err = copyin(wc->cmap.green, &g[index], count); 2968 if (err) 2969 return err; 2970 err = copyin(wc->cmap.blue, &b[index], count); 2971 if (err) 2972 return err; 2973 2974 for (i = index; i < index + count; i++) { 2975 nc.rc_cmap[i] = 2976 (r[i] << 16) + (g[i] << 8) + (b[i] << 0); 2977 } 2978 } 2979 2980 if (flags & WSDISPLAY_CURSOR_DOSHAPE) { 2981 if ((wc->size.x > RADEON_CURSORMAXX) || 2982 (wc->size.y > RADEON_CURSORMAXY)) 2983 return EINVAL; 2984 2985 /* figure bytes per line */ 2986 pitch = (wc->size.x + 7) / 8; 2987 size = pitch * wc->size.y; 2988 2989 /* clear the old cursor and mask */ 2990 memset(nc.rc_image, 0, 512); 2991 memset(nc.rc_mask, 0, 512); 2992 2993 nc.rc_size = wc->size; 2994 2995 if ((err = copyin(wc->image, nc.rc_image, size)) != 0) 2996 return err; 2997 2998 if ((err = copyin(wc->mask, nc.rc_mask, size)) != 0) 2999 return err; 3000 } 3001 3002 if (flags & WSDISPLAY_CURSOR_DOHOT) { 3003 nc.rc_hot = wc->hot; 3004 if (nc.rc_hot.x >= nc.rc_size.x) 3005 nc.rc_hot.x = nc.rc_size.x - 1; 3006 if (nc.rc_hot.y >= nc.rc_size.y) 3007 nc.rc_hot.y = nc.rc_size.y - 1; 3008 } 3009 3010 if (flags & WSDISPLAY_CURSOR_DOPOS) { 3011 nc.rc_pos = wc->pos; 3012 if (nc.rc_pos.x >= dp->rd_virtx) 3013 nc.rc_pos.x = dp->rd_virtx - 1; 3014 #if 0 3015 if (nc.rc_pos.x < 0) 3016 nc.rc_pos.x = 0; 3017 #endif 3018 if (nc.rc_pos.y >= dp->rd_virty) 3019 nc.rc_pos.y = dp->rd_virty - 1; 3020 #if 0 3021 if (nc.rc_pos.y < 0) 3022 nc.rc_pos.y = 0; 3023 #endif 3024 } 3025 if (flags & WSDISPLAY_CURSOR_DOCUR) { 3026 nc.rc_visible = wc->enable; 3027 } 3028 3029 dp->rd_cursor = nc; 3030 radeonfb_cursor_update(dp, wc->which); 3031 3032 return 0; 3033 } 3034 3035 /* 3036 * Change the cursor shape. Call this with the cursor locked to avoid 3037 * flickering/tearing. 3038 */ 3039 static void 3040 radeonfb_cursor_shape(struct radeonfb_display *dp) 3041 { 3042 uint8_t and[512], xor[512]; 3043 int i, j, src, dst, pitch; 3044 const uint8_t *msk = dp->rd_cursor.rc_mask; 3045 const uint8_t *img = dp->rd_cursor.rc_image; 3046 3047 /* 3048 * Radeon cursor data interleaves one line of AND data followed 3049 * by a line of XOR data. (Each line corresponds to a whole hardware 3050 * pitch - i.e. 64 pixels or 8 bytes.) 3051 * 3052 * The cursor is displayed using the following table: 3053 * 3054 * AND XOR Result 3055 * ---------------------- 3056 * 0 0 Cursor color 0 3057 * 0 1 Cursor color 1 3058 * 1 0 Transparent 3059 * 1 1 Complement of background 3060 * 3061 * Our masks are therefore different from what we were passed. 3062 * Passed in, I'm assuming the data represents either color 0 or 1, 3063 * and a mask, so the passed in table looks like: 3064 * 3065 * IMG Mask Result 3066 * ----------------------- 3067 * 0 0 Transparent 3068 * 0 1 Cursor color 0 3069 * 1 0 Transparent 3070 * 1 1 Cursor color 1 3071 * 3072 * IF mask bit == 1, AND = 0, XOR = color. 3073 * IF mask bit == 0, AND = 1, XOR = 0. 3074 * 3075 * hence: AND = ~(mask); XOR = color & ~(mask); 3076 */ 3077 3078 pitch = ((dp->rd_cursor.rc_size.x + 7) / 8); 3079 3080 /* start by assuming all bits are transparent */ 3081 memset(and, 0xff, 512); 3082 memset(xor, 0x00, 512); 3083 3084 src = 0; 3085 dst = 0; 3086 for (i = 0; i < 64; i++) { 3087 for (j = 0; j < 64; j += 8) { 3088 if ((i < dp->rd_cursor.rc_size.y) && 3089 (j < dp->rd_cursor.rc_size.x)) { 3090 3091 /* take care to leave odd bits alone */ 3092 and[dst] &= ~(msk[src]); 3093 xor[dst] = img[src] & msk[src]; 3094 src++; 3095 } 3096 dst++; 3097 } 3098 } 3099 3100 /* copy the image into place */ 3101 for (i = 0; i < 64; i++) { 3102 memcpy((uint8_t *)dp->rd_curptr + (i * 16), 3103 &and[i * 8], 8); 3104 memcpy((uint8_t *)dp->rd_curptr + (i * 16) + 8, 3105 &xor[i * 8], 8); 3106 } 3107 } 3108 3109 static void 3110 radeonfb_cursor_position(struct radeonfb_display *dp) 3111 { 3112 struct radeonfb_softc *sc = dp->rd_softc; 3113 uint32_t offset, hvoff, hvpos; /* registers */ 3114 uint32_t coff; /* cursor offset */ 3115 int i, x, y, xoff, yoff, crtcoff; 3116 3117 /* 3118 * XXX: this also needs to handle pan/scan 3119 */ 3120 for (i = 0; i < dp->rd_ncrtcs; i++) { 3121 3122 struct radeonfb_crtc *rcp = &dp->rd_crtcs[i]; 3123 3124 if (rcp->rc_number) { 3125 offset = RADEON_CUR2_OFFSET; 3126 hvoff = RADEON_CUR2_HORZ_VERT_OFF; 3127 hvpos = RADEON_CUR2_HORZ_VERT_POSN; 3128 crtcoff = RADEON_CRTC2_OFFSET; 3129 } else { 3130 offset = RADEON_CUR_OFFSET; 3131 hvoff = RADEON_CUR_HORZ_VERT_OFF; 3132 hvpos = RADEON_CUR_HORZ_VERT_POSN; 3133 crtcoff = RADEON_CRTC_OFFSET; 3134 } 3135 3136 x = dp->rd_cursor.rc_pos.x; 3137 y = dp->rd_cursor.rc_pos.y; 3138 3139 while (y < rcp->rc_yoffset) { 3140 rcp->rc_yoffset -= RADEON_PANINCREMENT; 3141 } 3142 while (y >= (rcp->rc_yoffset + rcp->rc_videomode.vdisplay)) { 3143 rcp->rc_yoffset += RADEON_PANINCREMENT; 3144 } 3145 while (x < rcp->rc_xoffset) { 3146 rcp->rc_xoffset -= RADEON_PANINCREMENT; 3147 } 3148 while (x >= (rcp->rc_xoffset + rcp->rc_videomode.hdisplay)) { 3149 rcp->rc_xoffset += RADEON_PANINCREMENT; 3150 } 3151 3152 /* adjust for the cursor's hotspot */ 3153 x -= dp->rd_cursor.rc_hot.x; 3154 y -= dp->rd_cursor.rc_hot.y; 3155 xoff = yoff = 0; 3156 3157 if (x >= dp->rd_virtx) 3158 x = dp->rd_virtx - 1; 3159 if (y >= dp->rd_virty) 3160 y = dp->rd_virty - 1; 3161 3162 /* now adjust cursor so it is relative to viewport */ 3163 x -= rcp->rc_xoffset; 3164 y -= rcp->rc_yoffset; 3165 3166 /* 3167 * no need to check for fall off, because we should 3168 * never move off the screen entirely! 3169 */ 3170 coff = 0; 3171 if (x < 0) { 3172 xoff = -x; 3173 x = 0; 3174 } 3175 if (y < 0) { 3176 yoff = -y; 3177 y = 0; 3178 coff = (yoff * 2) * 8; 3179 } 3180 3181 /* pan the display */ 3182 PUT32(sc, crtcoff, (rcp->rc_yoffset * dp->rd_stride) + 3183 rcp->rc_xoffset); 3184 3185 PUT32(sc, offset, (dp->rd_curoff + coff) | RADEON_CUR_LOCK); 3186 PUT32(sc, hvoff, (xoff << 16) | (yoff) | RADEON_CUR_LOCK); 3187 /* NB: this unlocks the cursor */ 3188 PUT32(sc, hvpos, (x << 16) | y); 3189 } 3190 } 3191 3192 static void 3193 radeonfb_cursor_visible(struct radeonfb_display *dp) 3194 { 3195 int i; 3196 uint32_t gencntl, bit; 3197 3198 for (i = 0; i < dp->rd_ncrtcs; i++) { 3199 if (dp->rd_crtcs[i].rc_number) { 3200 gencntl = RADEON_CRTC2_GEN_CNTL; 3201 bit = RADEON_CRTC2_CUR_EN; 3202 } else { 3203 gencntl = RADEON_CRTC_GEN_CNTL; 3204 bit = RADEON_CRTC_CUR_EN; 3205 } 3206 3207 if (dp->rd_cursor.rc_visible) 3208 SET32(dp->rd_softc, gencntl, bit); 3209 else 3210 CLR32(dp->rd_softc, gencntl, bit); 3211 } 3212 } 3213 3214 static void 3215 radeonfb_cursor_cmap(struct radeonfb_display *dp) 3216 { 3217 int i; 3218 uint32_t c0reg, c1reg; 3219 struct radeonfb_softc *sc = dp->rd_softc; 3220 3221 for (i = 0; i < dp->rd_ncrtcs; i++) { 3222 if (dp->rd_crtcs[i].rc_number) { 3223 c0reg = RADEON_CUR2_CLR0; 3224 c1reg = RADEON_CUR2_CLR1; 3225 } else { 3226 c0reg = RADEON_CUR_CLR0; 3227 c1reg = RADEON_CUR_CLR1; 3228 } 3229 3230 PUT32(sc, c0reg, dp->rd_cursor.rc_cmap[0]); 3231 PUT32(sc, c1reg, dp->rd_cursor.rc_cmap[1]); 3232 } 3233 } 3234 3235 static void 3236 radeonfb_cursor_update(struct radeonfb_display *dp, unsigned which) 3237 { 3238 struct radeonfb_softc *sc; 3239 int i; 3240 3241 sc = dp->rd_softc; 3242 for (i = 0; i < dp->rd_ncrtcs; i++) { 3243 if (dp->rd_crtcs[i].rc_number) { 3244 SET32(sc, RADEON_CUR2_OFFSET, RADEON_CUR_LOCK); 3245 } else { 3246 SET32(sc, RADEON_CUR_OFFSET,RADEON_CUR_LOCK); 3247 } 3248 } 3249 3250 if (which & WSDISPLAY_CURSOR_DOCMAP) 3251 radeonfb_cursor_cmap(dp); 3252 3253 if (which & WSDISPLAY_CURSOR_DOSHAPE) 3254 radeonfb_cursor_shape(dp); 3255 3256 if (which & WSDISPLAY_CURSOR_DOCUR) 3257 radeonfb_cursor_visible(dp); 3258 3259 /* this one is unconditional, because it updates other stuff */ 3260 radeonfb_cursor_position(dp); 3261 } 3262 3263 static struct videomode * 3264 radeonfb_best_refresh(struct videomode *m1, struct videomode *m2) 3265 { 3266 int r1, r2; 3267 3268 /* otherwise pick the higher refresh rate */ 3269 r1 = DIVIDE(DIVIDE(m1->dot_clock, m1->htotal), m1->vtotal); 3270 r2 = DIVIDE(DIVIDE(m2->dot_clock, m2->htotal), m2->vtotal); 3271 3272 return (r1 < r2 ? m2 : m1); 3273 } 3274 3275 static const struct videomode * 3276 radeonfb_port_mode(struct radeonfb_softc *sc, struct radeonfb_port *rp, 3277 int x, int y) 3278 { 3279 struct edid_info *ep = &rp->rp_edid; 3280 struct videomode *vmp = NULL; 3281 int i; 3282 3283 if (!rp->rp_edid_valid) { 3284 /* fallback to safe mode */ 3285 return radeonfb_modelookup(sc->sc_defaultmode); 3286 } 3287 3288 /* always choose the preferred mode first! */ 3289 if (ep->edid_preferred_mode) { 3290 3291 /* XXX: add auto-stretching support for native mode */ 3292 3293 /* this may want panning to occur, btw */ 3294 if ((ep->edid_preferred_mode->hdisplay <= x) && 3295 (ep->edid_preferred_mode->vdisplay <= y)) 3296 return ep->edid_preferred_mode; 3297 } 3298 3299 for (i = 0; i < ep->edid_nmodes; i++) { 3300 /* 3301 * We elect to pick a resolution that is too large for 3302 * the monitor than one that is too small. This means 3303 * that we will prefer to pan rather than to try to 3304 * center a smaller display on a larger screen. In 3305 * practice, this shouldn't matter because if a 3306 * monitor can support a larger resolution, it can 3307 * probably also support the smaller. A specific 3308 * exception is fixed format panels, but hopefully 3309 * they are properly dealt with by the "autostretch" 3310 * logic above. 3311 */ 3312 if ((ep->edid_modes[i].hdisplay > x) || 3313 (ep->edid_modes[i].vdisplay > y)) { 3314 continue; 3315 } 3316 3317 /* 3318 * at this point, the display mode is no larger than 3319 * what we've requested. 3320 */ 3321 if (vmp == NULL) 3322 vmp = &ep->edid_modes[i]; 3323 3324 /* eliminate smaller modes */ 3325 if ((vmp->hdisplay >= ep->edid_modes[i].hdisplay) || 3326 (vmp->vdisplay >= ep->edid_modes[i].vdisplay)) 3327 continue; 3328 3329 if ((vmp->hdisplay < ep->edid_modes[i].hdisplay) || 3330 (vmp->vdisplay < ep->edid_modes[i].vdisplay)) { 3331 vmp = &ep->edid_modes[i]; 3332 continue; 3333 } 3334 3335 KASSERT(vmp->hdisplay == ep->edid_modes[i].hdisplay); 3336 KASSERT(vmp->vdisplay == ep->edid_modes[i].vdisplay); 3337 3338 vmp = radeonfb_best_refresh(vmp, &ep->edid_modes[i]); 3339 } 3340 3341 return (vmp ? vmp : radeonfb_modelookup(sc->sc_defaultmode)); 3342 } 3343 3344 static int 3345 radeonfb_hasres(struct videomode *list, int nlist, int x, int y) 3346 { 3347 int i; 3348 3349 for (i = 0; i < nlist; i++) { 3350 if ((x == list[i].hdisplay) && 3351 (y == list[i].vdisplay)) { 3352 return 1; 3353 } 3354 } 3355 return 0; 3356 } 3357 3358 static void 3359 radeonfb_pickres(struct radeonfb_display *dp, uint16_t *x, uint16_t *y, 3360 int pan) 3361 { 3362 struct radeonfb_port *rp; 3363 struct edid_info *ep; 3364 int i, j; 3365 3366 *x = 0; 3367 *y = 0; 3368 3369 if (pan) { 3370 for (i = 0; i < dp->rd_ncrtcs; i++) { 3371 rp = dp->rd_crtcs[i].rc_port; 3372 ep = &rp->rp_edid; 3373 if (!rp->rp_edid_valid) { 3374 /* monitor not present */ 3375 continue; 3376 } 3377 3378 /* 3379 * For now we are ignoring "conflict" that 3380 * could occur when mixing some modes like 3381 * 1280x1024 and 1400x800. It isn't clear 3382 * which is better, so the first one wins. 3383 */ 3384 for (j = 0; j < ep->edid_nmodes; j++) { 3385 /* 3386 * ignore resolutions that are too big for 3387 * the radeon 3388 */ 3389 if (ep->edid_modes[j].hdisplay > 3390 dp->rd_softc->sc_maxx) 3391 continue; 3392 if (ep->edid_modes[j].vdisplay > 3393 dp->rd_softc->sc_maxy) 3394 continue; 3395 3396 /* 3397 * pick largest resolution, the 3398 * smaller monitor will pan 3399 */ 3400 if ((ep->edid_modes[j].hdisplay >= *x) && 3401 (ep->edid_modes[j].vdisplay >= *y)) { 3402 *x = ep->edid_modes[j].hdisplay; 3403 *y = ep->edid_modes[j].vdisplay; 3404 } 3405 } 3406 } 3407 3408 } else { 3409 struct videomode modes[64]; 3410 int nmodes = 0; 3411 int valid = 0; 3412 3413 for (i = 0; i < dp->rd_ncrtcs; i++) { 3414 /* 3415 * pick the largest resolution in common. 3416 */ 3417 rp = dp->rd_crtcs[i].rc_port; 3418 ep = &rp->rp_edid; 3419 3420 if (!rp->rp_edid_valid) 3421 continue; 3422 3423 if (!valid) { 3424 /* 3425 * Pick the preferred mode for this port 3426 * if available. 3427 */ 3428 if (ep->edid_preferred_mode) { 3429 struct videomode *vmp = 3430 ep->edid_preferred_mode; 3431 3432 if ((vmp->hdisplay <= 3433 dp->rd_softc->sc_maxx) && 3434 (vmp->vdisplay <= 3435 dp->rd_softc->sc_maxy)) 3436 modes[nmodes++] = *vmp; 3437 } else { 3438 3439 /* initialize starting list */ 3440 for (j = 0; j < ep->edid_nmodes; j++) { 3441 /* 3442 * ignore resolutions that are 3443 * too big for the radeon 3444 */ 3445 if (ep->edid_modes[j].hdisplay > 3446 dp->rd_softc->sc_maxx) 3447 continue; 3448 if (ep->edid_modes[j].vdisplay > 3449 dp->rd_softc->sc_maxy) 3450 continue; 3451 3452 modes[nmodes] = 3453 ep->edid_modes[j]; 3454 nmodes++; 3455 } 3456 } 3457 valid = 1; 3458 } else { 3459 /* merge into preexisting list */ 3460 for (j = 0; j < nmodes; j++) { 3461 if (!radeonfb_hasres(ep->edid_modes, 3462 ep->edid_nmodes, 3463 modes[j].hdisplay, 3464 modes[j].vdisplay)) { 3465 modes[j] = modes[nmodes]; 3466 j--; 3467 nmodes--; 3468 } 3469 } 3470 } 3471 } 3472 3473 /* now we have to pick from the merged list */ 3474 for (i = 0; i < nmodes; i++) { 3475 if ((modes[i].hdisplay >= *x) && 3476 (modes[i].vdisplay >= *y)) { 3477 *x = modes[i].hdisplay; 3478 *y = modes[i].vdisplay; 3479 } 3480 } 3481 } 3482 3483 if ((*x == 0) || (*y == 0)) { 3484 /* fallback to safe mode */ 3485 *x = 640; 3486 *y = 480; 3487 } 3488 } 3489 3490 /* 3491 * backlight levels are linear on: 3492 * - RV200, RV250, RV280, RV350 3493 * - but NOT on PowerBook4,3 6,3 6,5 3494 * according to Linux' radeonfb 3495 */ 3496 3497 /* Get the current backlight level for the display. */ 3498 3499 static int 3500 radeonfb_get_backlight(struct radeonfb_display *dp) 3501 { 3502 int s; 3503 uint32_t level; 3504 3505 s = spltty(); 3506 3507 level = radeonfb_get32(dp->rd_softc, RADEON_LVDS_GEN_CNTL); 3508 level &= RADEON_LVDS_BL_MOD_LEV_MASK; 3509 level >>= RADEON_LVDS_BL_MOD_LEV_SHIFT; 3510 3511 /* 3512 * On some chips, we should negate the backlight level. 3513 * XXX Find out on which chips. 3514 */ 3515 if (dp->rd_softc->sc_flags & RFB_INV_BLIGHT) 3516 level = RADEONFB_BACKLIGHT_MAX - level; 3517 3518 splx(s); 3519 3520 return level; 3521 } 3522 3523 /* Set the backlight to the given level for the display. */ 3524 3525 static int 3526 radeonfb_set_backlight(struct radeonfb_display *dp, int level) 3527 { 3528 struct radeonfb_softc *sc; 3529 int rlevel, s; 3530 uint32_t lvds; 3531 3532 s = spltty(); 3533 3534 if (level < 0) 3535 level = 0; 3536 else if (level >= RADEONFB_BACKLIGHT_MAX) 3537 level = RADEONFB_BACKLIGHT_MAX; 3538 3539 sc = dp->rd_softc; 3540 3541 /* On some chips, we should negate the backlight level. */ 3542 if (dp->rd_softc->sc_flags & RFB_INV_BLIGHT) { 3543 rlevel = RADEONFB_BACKLIGHT_MAX - level; 3544 } else 3545 rlevel = level; 3546 3547 callout_stop(&dp->rd_bl_lvds_co); 3548 radeonfb_engine_idle(sc); 3549 3550 /* 3551 * Turn off the display if the backlight is set to 0, since the 3552 * display is useless without backlight anyway. 3553 */ 3554 if (level == 0) 3555 radeonfb_blank(dp, 1); 3556 else if (radeonfb_get_backlight(dp) == 0) 3557 radeonfb_blank(dp, 0); 3558 3559 lvds = radeonfb_get32(sc, RADEON_LVDS_GEN_CNTL); 3560 lvds &= ~RADEON_LVDS_DISPLAY_DIS; 3561 if (!(lvds & RADEON_LVDS_BLON) || !(lvds & RADEON_LVDS_ON)) { 3562 lvds |= dp->rd_bl_lvds_val & RADEON_LVDS_DIGON; 3563 lvds |= RADEON_LVDS_BLON | RADEON_LVDS_EN; 3564 radeonfb_put32(sc, RADEON_LVDS_GEN_CNTL, lvds); 3565 lvds &= ~RADEON_LVDS_BL_MOD_LEV_MASK; 3566 lvds |= rlevel << RADEON_LVDS_BL_MOD_LEV_SHIFT; 3567 lvds |= RADEON_LVDS_ON; 3568 lvds |= dp->rd_bl_lvds_val & RADEON_LVDS_BL_MOD_EN; 3569 } else { 3570 lvds &= ~RADEON_LVDS_BL_MOD_LEV_MASK; 3571 lvds |= rlevel << RADEON_LVDS_BL_MOD_LEV_SHIFT; 3572 radeonfb_put32(sc, RADEON_LVDS_GEN_CNTL, lvds); 3573 } 3574 3575 dp->rd_bl_lvds_val &= ~RADEON_LVDS_STATE_MASK; 3576 dp->rd_bl_lvds_val |= lvds & RADEON_LVDS_STATE_MASK; 3577 /* XXX What is the correct delay? */ 3578 callout_schedule(&dp->rd_bl_lvds_co, 200 * hz); 3579 3580 splx(s); 3581 3582 return 0; 3583 } 3584 3585 /* 3586 * Callout function for delayed operations on the LVDS_GEN_CNTL register. 3587 * Set the delayed bits in the register, and clear the stored delayed 3588 * value. 3589 */ 3590 3591 static void radeonfb_lvds_callout(void *arg) 3592 { 3593 struct radeonfb_display *dp = arg; 3594 int s; 3595 3596 s = splhigh(); 3597 3598 radeonfb_mask32(dp->rd_softc, RADEON_LVDS_GEN_CNTL, ~0, 3599 dp->rd_bl_lvds_val); 3600 dp->rd_bl_lvds_val = 0; 3601 3602 splx(s); 3603 } 3604 3605 static void 3606 radeonfb_brightness_up(device_t dev) 3607 { 3608 struct radeonfb_softc *sc = device_private(dev); 3609 int level; 3610 3611 /* we assume the main display is the first one - need a better way */ 3612 if (sc->sc_ndisplays < 1) return; 3613 level = radeonfb_get_backlight(&sc->sc_displays[0]); 3614 level = min(RADEONFB_BACKLIGHT_MAX, level + 5); 3615 radeonfb_set_backlight(&sc->sc_displays[0], level); 3616 } 3617 3618 static void 3619 radeonfb_brightness_down(device_t dev) 3620 { 3621 struct radeonfb_softc *sc = device_private(dev); 3622 int level; 3623 3624 /* we assume the main display is the first one - need a better way */ 3625 if (sc->sc_ndisplays < 1) return; 3626 level = radeonfb_get_backlight(&sc->sc_displays[0]); 3627 level = max(0, level - 5); 3628 radeonfb_set_backlight(&sc->sc_displays[0], level); 3629 } 3630
Indexes created Tue Oct 21 08:09:48 GMT 2025