radeonfb.c revision 1.36
1 /* $NetBSD: radeonfb.c,v 1.36 2010/08/17 18:53:16 macallan Exp $ */ 2 3 /*- 4 * Copyright (c) 2006 Itronix Inc. 5 * All rights reserved. 6 * 7 * Written by Garrett D'Amore for Itronix Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. The name of Itronix Inc. may not be used to endorse 18 * or promote products derived from this software without specific 19 * prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY ITRONIX INC. ``AS IS'' AND ANY EXPRESS 22 * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 23 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL ITRONIX INC. BE LIABLE FOR ANY 25 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE 27 * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 29 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 30 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 31 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * ATI Technologies Inc. ("ATI") has not assisted in the creation of, and 36 * does not endorse, this software. ATI will not be responsible or liable 37 * for any actual or alleged damage or loss caused by or in connection with 38 * the use of or reliance on this software. 39 */ 40 41 /* 42 * Portions of this code were taken from XFree86's Radeon driver, which bears 43 * this notice: 44 * 45 * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and 46 * VA Linux Systems Inc., Fremont, California. 47 * 48 * All Rights Reserved. 49 * 50 * Permission is hereby granted, free of charge, to any person obtaining 51 * a copy of this software and associated documentation files (the 52 * "Software"), to deal in the Software without restriction, including 53 * without limitation on the rights to use, copy, modify, merge, 54 * publish, distribute, sublicense, and/or sell copies of the Software, 55 * and to permit persons to whom the Software is furnished to do so, 56 * subject to the following conditions: 57 * 58 * The above copyright notice and this permission notice (including the 59 * next paragraph) shall be included in all copies or substantial 60 * portions of the Software. 61 * 62 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 63 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 64 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 65 * NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR 66 * THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 67 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 68 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 69 * DEALINGS IN THE SOFTWARE. 70 */ 71 72 #include <sys/cdefs.h> 73 __KERNEL_RCSID(0, "$NetBSD: radeonfb.c,v 1.36 2010/08/17 18:53:16 macallan Exp $"); 74 75 #define RADEONFB_DEFAULT_DEPTH 8 76 77 #include <sys/param.h> 78 #include <sys/systm.h> 79 #include <sys/device.h> 80 #include <sys/malloc.h> 81 #include <sys/bus.h> 82 #include <sys/kernel.h> 83 #include <sys/lwp.h> 84 #include <sys/kauth.h> 85 86 #include <dev/wscons/wsdisplayvar.h> 87 #include <dev/wscons/wsconsio.h> 88 #include <dev/wsfont/wsfont.h> 89 #include <dev/rasops/rasops.h> 90 #include <dev/videomode/videomode.h> 91 #include <dev/videomode/edidvar.h> 92 #include <dev/wscons/wsdisplay_vconsvar.h> 93 94 #include <dev/pci/pcidevs.h> 95 #include <dev/pci/pcireg.h> 96 #include <dev/pci/pcivar.h> 97 #include <dev/pci/pciio.h> 98 #include <dev/pci/radeonfbreg.h> 99 #include <dev/pci/radeonfbvar.h> 100 #include "opt_radeonfb.h" 101 102 static int radeonfb_match(device_t, cfdata_t, void *); 103 static void radeonfb_attach(device_t, device_t, void *); 104 static int radeonfb_ioctl(void *, void *, unsigned long, void *, int, 105 struct lwp *); 106 static paddr_t radeonfb_mmap(void *, void *, off_t, int); 107 static int radeonfb_scratch_test(struct radeonfb_softc *, int, uint32_t); 108 static void radeonfb_loadbios(struct radeonfb_softc *, 109 struct pci_attach_args *); 110 111 static uintmax_t radeonfb_getprop_num(struct radeonfb_softc *, const char *, 112 uintmax_t); 113 static int radeonfb_getclocks(struct radeonfb_softc *); 114 static int radeonfb_gettmds(struct radeonfb_softc *); 115 static int radeonfb_calc_dividers(struct radeonfb_softc *, uint32_t, 116 uint32_t *, uint32_t *); 117 static int radeonfb_getconnectors(struct radeonfb_softc *); 118 static const struct videomode *radeonfb_modelookup(const char *); 119 static void radeonfb_init_screen(void *, struct vcons_screen *, int, long *); 120 static void radeonfb_pllwriteupdate(struct radeonfb_softc *, int); 121 static void radeonfb_pllwaitatomicread(struct radeonfb_softc *, int); 122 static void radeonfb_program_vclk(struct radeonfb_softc *, int, int); 123 static void radeonfb_modeswitch(struct radeonfb_display *); 124 static void radeonfb_setcrtc(struct radeonfb_display *, int); 125 static void radeonfb_init_misc(struct radeonfb_softc *); 126 static void radeonfb_set_fbloc(struct radeonfb_softc *); 127 static void radeonfb_init_palette(struct radeonfb_softc *, int); 128 static void radeonfb_r300cg_workaround(struct radeonfb_softc *); 129 130 static int radeonfb_isblank(struct radeonfb_display *); 131 static void radeonfb_blank(struct radeonfb_display *, int); 132 static int radeonfb_set_cursor(struct radeonfb_display *, 133 struct wsdisplay_cursor *); 134 static int radeonfb_set_curpos(struct radeonfb_display *, 135 struct wsdisplay_curpos *); 136 137 /* acceleration support */ 138 static void radeonfb_rectfill(struct radeonfb_display *, int dstx, int dsty, 139 int width, int height, uint32_t color); 140 static void radeonfb_bitblt(struct radeonfb_display *, int srcx, int srcy, 141 int dstx, int dsty, int width, int height, int rop, uint32_t mask); 142 static void radeonfb_feed_bytes(struct radeonfb_display *, int, uint8_t *); 143 static void radeonfb_setup_mono(struct radeonfb_display *, int, int, int, 144 int, uint32_t, uint32_t); 145 146 /* hw cursor support */ 147 static void radeonfb_cursor_cmap(struct radeonfb_display *); 148 static void radeonfb_cursor_shape(struct radeonfb_display *); 149 static void radeonfb_cursor_position(struct radeonfb_display *); 150 static void radeonfb_cursor_visible(struct radeonfb_display *); 151 static void radeonfb_cursor_update(struct radeonfb_display *, unsigned); 152 153 static void radeonfb_wait_fifo(struct radeonfb_softc *, int); 154 static void radeonfb_engine_idle(struct radeonfb_softc *); 155 static void radeonfb_engine_flush(struct radeonfb_softc *); 156 static void radeonfb_engine_reset(struct radeonfb_softc *); 157 static void radeonfb_engine_init(struct radeonfb_display *); 158 static inline void radeonfb_unclip(struct radeonfb_softc *); 159 160 static void radeonfb_eraserows(void *, int, int, long); 161 static void radeonfb_erasecols(void *, int, int, int, long); 162 static void radeonfb_copyrows(void *, int, int, int); 163 static void radeonfb_copycols(void *, int, int, int, int); 164 static void radeonfb_cursor(void *, int, int, int); 165 static void radeonfb_putchar(void *, int, int, unsigned, long); 166 static int radeonfb_allocattr(void *, int, int, int, long *); 167 168 static int radeonfb_get_backlight(struct radeonfb_display *); 169 static int radeonfb_set_backlight(struct radeonfb_display *, int); 170 static void radeonfb_lvds_callout(void *); 171 172 static void radeonfb_brightness_up(device_t); 173 static void radeonfb_brightness_down(device_t); 174 175 static struct videomode *radeonfb_best_refresh(struct videomode *, 176 struct videomode *); 177 static void radeonfb_pickres(struct radeonfb_display *, uint16_t *, 178 uint16_t *, int); 179 static const struct videomode *radeonfb_port_mode(struct radeonfb_softc *, 180 struct radeonfb_port *, int, int); 181 182 static int radeonfb_drm_print(void *, const char *); 183 184 #ifdef RADEONFB_DEBUG 185 int radeon_debug = 1; 186 #define DPRINTF(x) \ 187 if (radeon_debug) printf x 188 #define PRINTREG(r) DPRINTF((#r " = %08x\n", GET32(sc, r))) 189 #define PRINTPLL(r) DPRINTF((#r " = %08x\n", GETPLL(sc, r))) 190 #else 191 #define DPRINTF(x) 192 #define PRINTREG(r) 193 #define PRINTPLL(r) 194 #endif 195 196 #define ROUNDUP(x,y) (((x) + ((y) - 1)) & ~((y) - 1)) 197 198 #ifndef RADEON_DEFAULT_MODE 199 /* any reasonably modern display should handle this */ 200 #define RADEON_DEFAULT_MODE "1024x768x60" 201 #endif 202 203 extern const u_char rasops_cmap[768]; 204 205 const char *radeonfb_default_mode = RADEON_DEFAULT_MODE; 206 207 static struct { 208 int size; /* minimum memory size (MB) */ 209 int maxx; /* maximum x dimension */ 210 int maxy; /* maximum y dimension */ 211 int maxbpp; /* maximum bpp */ 212 int maxdisp; /* maximum logical display count */ 213 } radeonfb_limits[] = { 214 { 32, 2048, 1536, 32, 2 }, 215 { 16, 1600, 1200, 32, 2 }, 216 { 8, 1600, 1200, 32, 1 }, 217 { 0, 0, 0, 0, 0 }, 218 }; 219 220 static struct wsscreen_descr radeonfb_stdscreen = { 221 "fb", /* name */ 222 0, 0, /* ncols, nrows */ 223 NULL, /* textops */ 224 8, 16, /* fontwidth, fontheight */ 225 WSSCREEN_WSCOLORS | WSSCREEN_REVERSE, /* capabilities */ 226 0, /* modecookie */ 227 }; 228 229 struct wsdisplay_accessops radeonfb_accessops = { 230 radeonfb_ioctl, 231 radeonfb_mmap, 232 NULL, /* vcons_alloc_screen */ 233 NULL, /* vcons_free_screen */ 234 NULL, /* vcons_show_screen */ 235 NULL, /* load_font */ 236 NULL, /* pollc */ 237 NULL, /* scroll */ 238 }; 239 240 static struct { 241 uint16_t devid; 242 uint16_t family; 243 uint16_t flags; 244 } radeonfb_devices[] = 245 { 246 /* R100 family */ 247 { PCI_PRODUCT_ATI_RADEON_R100_QD, RADEON_R100, 0 }, 248 { PCI_PRODUCT_ATI_RADEON_R100_QE, RADEON_R100, 0 }, 249 { PCI_PRODUCT_ATI_RADEON_R100_QF, RADEON_R100, 0 }, 250 { PCI_PRODUCT_ATI_RADEON_R100_QG, RADEON_R100, 0 }, 251 252 /* RV100 family */ 253 { PCI_PRODUCT_ATI_RADEON_RV100_LY, RADEON_RV100, RFB_MOB }, 254 { PCI_PRODUCT_ATI_RADEON_RV100_LZ, RADEON_RV100, RFB_MOB }, 255 { PCI_PRODUCT_ATI_RADEON_RV100_QY, RADEON_RV100, 0 }, 256 { PCI_PRODUCT_ATI_RADEON_RV100_QZ, RADEON_RV100, 0 }, 257 258 /* RS100 family */ 259 { PCI_PRODUCT_ATI_RADEON_RS100_4136, RADEON_RS100, 0 }, 260 { PCI_PRODUCT_ATI_RADEON_RS100_4336, RADEON_RS100, RFB_MOB }, 261 262 /* RS200/RS250 family */ 263 { PCI_PRODUCT_ATI_RADEON_RS200_4337, RADEON_RS200, RFB_MOB }, 264 { PCI_PRODUCT_ATI_RADEON_RS200_A7, RADEON_RS200, 0 }, 265 { PCI_PRODUCT_ATI_RADEON_RS250_B7, RADEON_RS200, RFB_MOB }, 266 { PCI_PRODUCT_ATI_RADEON_RS250_D7, RADEON_RS200, 0 }, 267 268 /* R200 family */ 269 /* add more R200 products? , 5148 */ 270 { PCI_PRODUCT_ATI_RADEON_R200_BB, RADEON_R200, 0 }, 271 { PCI_PRODUCT_ATI_RADEON_R200_BC, RADEON_R200, 0 }, 272 { PCI_PRODUCT_ATI_RADEON_R200_QH, RADEON_R200, 0 }, 273 { PCI_PRODUCT_ATI_RADEON_R200_QL, RADEON_R200, 0 }, 274 { PCI_PRODUCT_ATI_RADEON_R200_QM, RADEON_R200, 0 }, 275 276 /* RV200 family */ 277 { PCI_PRODUCT_ATI_RADEON_RV200_LW, RADEON_RV200, RFB_MOB }, 278 { PCI_PRODUCT_ATI_RADEON_RV200_LX, RADEON_RV200, RFB_MOB }, 279 { PCI_PRODUCT_ATI_RADEON_RV200_QW, RADEON_RV200, 0 }, 280 { PCI_PRODUCT_ATI_RADEON_RV200_QX, RADEON_RV200, 0 }, 281 282 /* RV250 family */ 283 { PCI_PRODUCT_ATI_RADEON_RV250_4966, RADEON_RV250, 0 }, 284 { PCI_PRODUCT_ATI_RADEON_RV250_4967, RADEON_RV250, 0 }, 285 { PCI_PRODUCT_ATI_RADEON_RV250_4C64, RADEON_RV250, RFB_MOB }, 286 { PCI_PRODUCT_ATI_RADEON_RV250_4C66, RADEON_RV250, RFB_MOB }, 287 { PCI_PRODUCT_ATI_RADEON_RV250_4C67, RADEON_RV250, RFB_MOB }, 288 289 /* RS300 family */ 290 { PCI_PRODUCT_ATI_RADEON_RS300_X5, RADEON_RS300, 0 }, 291 { PCI_PRODUCT_ATI_RADEON_RS300_X4, RADEON_RS300, 0 }, 292 { PCI_PRODUCT_ATI_RADEON_RS300_7834, RADEON_RS300, 0 }, 293 { PCI_PRODUCT_ATI_RADEON_RS300_7835, RADEON_RS300, RFB_MOB }, 294 295 /* RV280 family */ 296 { PCI_PRODUCT_ATI_RADEON_RV280_5960, RADEON_RV280, 0 }, 297 { PCI_PRODUCT_ATI_RADEON_RV280_5961, RADEON_RV280, 0 }, 298 { PCI_PRODUCT_ATI_RADEON_RV280_5962, RADEON_RV280, 0 }, 299 { PCI_PRODUCT_ATI_RADEON_RV280_5963, RADEON_RV280, 0 }, 300 { PCI_PRODUCT_ATI_RADEON_RV280_5964, RADEON_RV280, 0 }, 301 { PCI_PRODUCT_ATI_RADEON_RV280_5C61, RADEON_RV280, RFB_MOB }, 302 { PCI_PRODUCT_ATI_RADEON_RV280_5C63, RADEON_RV280, RFB_MOB }, 303 304 /* R300 family */ 305 { PCI_PRODUCT_ATI_RADEON_R300_AD, RADEON_R300, 0 }, 306 { PCI_PRODUCT_ATI_RADEON_R300_AE, RADEON_R300, 0 }, 307 { PCI_PRODUCT_ATI_RADEON_R300_AF, RADEON_R300, 0 }, 308 { PCI_PRODUCT_ATI_RADEON_R300_AG, RADEON_R300, 0 }, 309 { PCI_PRODUCT_ATI_RADEON_R300_ND, RADEON_R300, 0 }, 310 { PCI_PRODUCT_ATI_RADEON_R300_NE, RADEON_R300, 0 }, 311 { PCI_PRODUCT_ATI_RADEON_R300_NF, RADEON_R300, 0 }, 312 { PCI_PRODUCT_ATI_RADEON_R300_NG, RADEON_R300, 0 }, 313 314 /* RV350/RV360 family */ 315 { PCI_PRODUCT_ATI_RADEON_RV350_AP, RADEON_RV350, 0 }, 316 { PCI_PRODUCT_ATI_RADEON_RV350_AQ, RADEON_RV350, 0 }, 317 { PCI_PRODUCT_ATI_RADEON_RV360_AR, RADEON_RV350, 0 }, 318 { PCI_PRODUCT_ATI_RADEON_RV350_AS, RADEON_RV350, 0 }, 319 { PCI_PRODUCT_ATI_RADEON_RV350_AT, RADEON_RV350, 0 }, 320 { PCI_PRODUCT_ATI_RADEON_RV350_AV, RADEON_RV350, 0 }, 321 { PCI_PRODUCT_ATI_RADEON_RV350_NP, RADEON_RV350, RFB_MOB }, 322 { PCI_PRODUCT_ATI_RADEON_RV350_NQ, RADEON_RV350, RFB_MOB }, 323 { PCI_PRODUCT_ATI_RADEON_RV350_NR, RADEON_RV350, RFB_MOB }, 324 { PCI_PRODUCT_ATI_RADEON_RV350_NS, RADEON_RV350, RFB_MOB }, 325 { PCI_PRODUCT_ATI_RADEON_RV350_NT, RADEON_RV350, RFB_MOB }, 326 { PCI_PRODUCT_ATI_RADEON_RV350_NV, RADEON_RV350, RFB_MOB }, 327 328 /* R350/R360 family */ 329 { PCI_PRODUCT_ATI_RADEON_R350_AH, RADEON_R350, 0 }, 330 { PCI_PRODUCT_ATI_RADEON_R350_AI, RADEON_R350, 0 }, 331 { PCI_PRODUCT_ATI_RADEON_R350_AJ, RADEON_R350, 0 }, 332 { PCI_PRODUCT_ATI_RADEON_R350_AK, RADEON_R350, 0 }, 333 { PCI_PRODUCT_ATI_RADEON_R350_NH, RADEON_R350, 0 }, 334 { PCI_PRODUCT_ATI_RADEON_R350_NI, RADEON_R350, 0 }, 335 { PCI_PRODUCT_ATI_RADEON_R350_NK, RADEON_R350, 0 }, 336 { PCI_PRODUCT_ATI_RADEON_R360_NJ, RADEON_R350, 0 }, 337 338 /* RV380/RV370 family */ 339 { PCI_PRODUCT_ATI_RADEON_RV380_3150, RADEON_RV380, RFB_MOB }, 340 { PCI_PRODUCT_ATI_RADEON_RV380_3154, RADEON_RV380, RFB_MOB }, 341 { PCI_PRODUCT_ATI_RADEON_RV380_3E50, RADEON_RV380, 0 }, 342 { PCI_PRODUCT_ATI_RADEON_RV380_3E54, RADEON_RV380, 0 }, 343 { PCI_PRODUCT_ATI_RADEON_RV370_5460, RADEON_RV380, RFB_MOB }, 344 { PCI_PRODUCT_ATI_RADEON_RV370_5464, RADEON_RV380, RFB_MOB }, 345 { PCI_PRODUCT_ATI_RADEON_RV370_5B60, RADEON_RV380, 0 }, 346 { PCI_PRODUCT_ATI_RADEON_RV370_5B64, RADEON_RV380, 0 }, 347 { PCI_PRODUCT_ATI_RADEON_RV370_5B65, RADEON_RV380, 0 }, 348 349 /* R420/R423 family */ 350 { PCI_PRODUCT_ATI_RADEON_R420_JH, RADEON_R420, 0 }, 351 { PCI_PRODUCT_ATI_RADEON_R420_JI, RADEON_R420, 0 }, 352 { PCI_PRODUCT_ATI_RADEON_R420_JJ, RADEON_R420, 0 }, 353 { PCI_PRODUCT_ATI_RADEON_R420_JK, RADEON_R420, 0 }, 354 { PCI_PRODUCT_ATI_RADEON_R420_JL, RADEON_R420, 0 }, 355 { PCI_PRODUCT_ATI_RADEON_R420_JM, RADEON_R420, 0 }, 356 { PCI_PRODUCT_ATI_RADEON_R420_JN, RADEON_R420, RFB_MOB }, 357 { PCI_PRODUCT_ATI_RADEON_R420_JP, RADEON_R420, 0 }, 358 { PCI_PRODUCT_ATI_RADEON_R423_UH, RADEON_R420, 0 }, 359 { PCI_PRODUCT_ATI_RADEON_R423_UI, RADEON_R420, 0 }, 360 { PCI_PRODUCT_ATI_RADEON_R423_UJ, RADEON_R420, 0 }, 361 { PCI_PRODUCT_ATI_RADEON_R423_UK, RADEON_R420, 0 }, 362 { PCI_PRODUCT_ATI_RADEON_R423_UQ, RADEON_R420, 0 }, 363 { PCI_PRODUCT_ATI_RADEON_R423_UR, RADEON_R420, 0 }, 364 { PCI_PRODUCT_ATI_RADEON_R423_UT, RADEON_R420, 0 }, 365 { PCI_PRODUCT_ATI_RADEON_R423_5D57, RADEON_R420, 0 }, 366 { PCI_PRODUCT_ATI_RADEON_R430_554F, RADEON_R420, 0 }, 367 368 { 0, 0, 0 } 369 }; 370 371 static struct { 372 int divider; 373 int mask; 374 } radeonfb_dividers[] = { 375 { 1, 0 }, 376 { 2, 1 }, 377 { 3, 4 }, 378 { 4, 2 }, 379 { 6, 6 }, 380 { 8, 3 }, 381 { 12, 7 }, 382 { 0, 0 } 383 }; 384 385 /* 386 * This table taken from X11. 387 */ 388 static const struct { 389 int family; 390 struct radeon_tmds_pll plls[4]; 391 } radeonfb_tmds_pll[] = { 392 { RADEON_R100, {{12000, 0xa1b}, {-1, 0xa3f}}}, 393 { RADEON_RV100, {{12000, 0xa1b}, {-1, 0xa3f}}}, 394 { RADEON_RS100, {{0, 0}}}, 395 { RADEON_RV200, {{15000, 0xa1b}, {-1, 0xa3f}}}, 396 { RADEON_RS200, {{15000, 0xa1b}, {-1, 0xa3f}}}, 397 { RADEON_R200, {{15000, 0xa1b}, {-1, 0xa3f}}}, 398 { RADEON_RV250, {{15500, 0x81b}, {-1, 0x83f}}}, 399 { RADEON_RS300, {{0, 0}}}, 400 { RADEON_RV280, {{13000, 0x400f4}, {15000, 0x400f7}}}, 401 { RADEON_R300, {{-1, 0xb01cb}}}, 402 { RADEON_R350, {{-1, 0xb01cb}}}, 403 { RADEON_RV350, {{15000, 0xb0155}, {-1, 0xb01cb}}}, 404 { RADEON_RV380, {{15000, 0xb0155}, {-1, 0xb01cb}}}, 405 { RADEON_R420, {{-1, 0xb01cb}}}, 406 }; 407 408 #define RADEONFB_BACKLIGHT_MAX 255 /* Maximum backlight level. */ 409 410 411 CFATTACH_DECL(radeonfb, sizeof (struct radeonfb_softc), 412 radeonfb_match, radeonfb_attach, NULL, NULL); 413 414 static int 415 radeonfb_match(device_t parent, cfdata_t match, void *aux) 416 { 417 struct pci_attach_args *pa = aux; 418 int i; 419 420 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_ATI) 421 return 0; 422 423 for (i = 0; radeonfb_devices[i].devid; i++) { 424 if (PCI_PRODUCT(pa->pa_id) == radeonfb_devices[i].devid) 425 return 100; /* high to defeat VGA/VESA */ 426 } 427 428 return 0; 429 } 430 431 static void 432 radeonfb_attach(device_t parent, device_t dev, void *aux) 433 { 434 struct radeonfb_softc *sc = device_private(dev); 435 struct pci_attach_args *pa = aux; 436 const char *mptr; 437 bus_size_t bsz; 438 pcireg_t screg; 439 int i, j, fg, bg, ul, flags; 440 uint32_t v; 441 442 sc->sc_id = pa->pa_id; 443 for (i = 0; radeonfb_devices[i].devid; i++) { 444 if (PCI_PRODUCT(sc->sc_id) == radeonfb_devices[i].devid) 445 break; 446 } 447 448 pci_devinfo(sc->sc_id, pa->pa_class, 0, sc->sc_devinfo, 449 sizeof(sc->sc_devinfo)); 450 451 aprint_naive("\n"); 452 aprint_normal(": %s\n", sc->sc_devinfo); 453 454 DPRINTF((prop_dictionary_externalize(device_properties(dev)))); 455 456 KASSERT(radeonfb_devices[i].devid != 0); 457 sc->sc_pt = pa->pa_tag; 458 sc->sc_iot = pa->pa_iot; 459 sc->sc_pc = pa->pa_pc; 460 sc->sc_family = radeonfb_devices[i].family; 461 sc->sc_flags = radeonfb_devices[i].flags; 462 463 /* enable memory and IO access */ 464 screg = pci_conf_read(sc->sc_pc, sc->sc_pt, PCI_COMMAND_STATUS_REG); 465 screg |= PCI_FLAGS_IO_ENABLED | PCI_FLAGS_MEM_ENABLED; 466 pci_conf_write(sc->sc_pc, sc->sc_pt, PCI_COMMAND_STATUS_REG, screg); 467 468 /* 469 * Some flags are general to entire chip families, and rather 470 * than clutter up the table with them, we go ahead and set 471 * them here. 472 */ 473 switch (sc->sc_family) { 474 case RADEON_RS100: 475 case RADEON_RS200: 476 sc->sc_flags |= RFB_IGP | RFB_RV100; 477 break; 478 479 case RADEON_RV100: 480 case RADEON_RV200: 481 case RADEON_RV250: 482 case RADEON_RV280: 483 sc->sc_flags |= RFB_RV100; 484 break; 485 486 case RADEON_RS300: 487 sc->sc_flags |= RFB_SDAC | RFB_IGP | RFB_RV100; 488 break; 489 490 case RADEON_R300: 491 case RADEON_RV350: 492 case RADEON_R350: 493 case RADEON_RV380: 494 case RADEON_R420: 495 /* newer chips */ 496 sc->sc_flags |= RFB_R300; 497 break; 498 499 case RADEON_R100: 500 sc->sc_flags |= RFB_NCRTC2; 501 break; 502 } 503 504 if ((sc->sc_family == RADEON_RV200) || 505 (sc->sc_family == RADEON_RV250) || 506 (sc->sc_family == RADEON_RV280) || 507 (sc->sc_family == RADEON_RV350)) { 508 bool inverted = 0; 509 /* backlight level is linear */ 510 DPRINTF(("found RV* chip, backlight is supposedly linear\n")); 511 prop_dictionary_get_bool(device_properties(&sc->sc_dev), 512 "backlight_level_reverted", &inverted); 513 if (inverted) { 514 DPRINTF(("nope, it's inverted\n")); 515 sc->sc_flags |= RFB_INV_BLIGHT; 516 } 517 } else 518 sc->sc_flags |= RFB_INV_BLIGHT; 519 520 /* 521 * XXX: to support true multihead, this must change. 522 */ 523 sc->sc_ndisplays = 1; 524 525 /* XXX: */ 526 if (!HAS_CRTC2(sc)) { 527 sc->sc_ndisplays = 1; 528 } 529 530 if (pci_mapreg_map(pa, RADEON_MAPREG_MMIO, PCI_MAPREG_TYPE_MEM, 0, 531 &sc->sc_regt, &sc->sc_regh, &sc->sc_regaddr, 532 &sc->sc_regsz) != 0) { 533 aprint_error("%s: unable to map registers!\n", XNAME(sc)); 534 goto error; 535 } 536 537 if (pci_mapreg_info(sc->sc_pc, sc->sc_pt, PCI_MAPREG_ROM, 538 PCI_MAPREG_TYPE_ROM, &sc->sc_romaddr, &sc->sc_romsz, &flags) != 0) 539 { 540 aprint_error("%s: unable to find ROM!\n", XNAME(sc)); 541 goto error; 542 } 543 sc->sc_romt = sc->sc_memt; 544 545 /* scratch register test... */ 546 if (radeonfb_scratch_test(sc, RADEON_BIOS_0_SCRATCH, 0x55555555) || 547 radeonfb_scratch_test(sc, RADEON_BIOS_0_SCRATCH, 0xaaaaaaaa)) { 548 aprint_error("%s: scratch register test failed!\n", XNAME(sc)); 549 goto error; 550 } 551 552 PRINTREG(RADEON_BIOS_4_SCRATCH); 553 PRINTREG(RADEON_FP_GEN_CNTL); 554 sc->sc_fp_gen_cntl = GET32(sc, RADEON_FP_GEN_CNTL); 555 PRINTREG(RADEON_FP2_GEN_CNTL); 556 PRINTREG(RADEON_TMDS_CNTL); 557 PRINTREG(RADEON_TMDS_TRANSMITTER_CNTL); 558 PRINTREG(RADEON_TMDS_PLL_CNTL); 559 PRINTREG(RADEON_LVDS_GEN_CNTL); 560 PRINTREG(RADEON_FP_HORZ_STRETCH); 561 PRINTREG(RADEON_FP_VERT_STRETCH); 562 563 /* XXX: RV100 specific */ 564 PUT32(sc, RADEON_TMDS_PLL_CNTL, 0xa27); 565 566 PATCH32(sc, RADEON_TMDS_TRANSMITTER_CNTL, 567 RADEON_TMDS_TRANSMITTER_PLLEN, 568 RADEON_TMDS_TRANSMITTER_PLLEN | RADEON_TMDS_TRANSMITTER_PLLRST); 569 570 radeonfb_i2c_init(sc); 571 572 radeonfb_loadbios(sc, pa); 573 574 #ifdef RADEON_BIOS_INIT 575 if (radeonfb_bios_init(sc)) { 576 aprint_error("%s: BIOS inititialization failed\n", XNAME(sc)); 577 goto error; 578 } 579 #endif 580 581 if (radeonfb_getclocks(sc)) { 582 aprint_error("%s: Unable to get reference clocks from BIOS\n", 583 XNAME(sc)); 584 goto error; 585 } 586 587 if (radeonfb_gettmds(sc)) { 588 aprint_error("%s: Unable to identify TMDS PLL settings\n", 589 XNAME(sc)); 590 goto error; 591 } 592 593 aprint_verbose("%s: refclk = %d.%03d MHz, refdiv = %d " 594 "minpll = %d, maxpll = %d\n", XNAME(sc), 595 (int)sc->sc_refclk / 1000, (int)sc->sc_refclk % 1000, 596 (int)sc->sc_refdiv, (int)sc->sc_minpll, (int)sc->sc_maxpll); 597 598 radeonfb_getconnectors(sc); 599 600 radeonfb_set_fbloc(sc); 601 602 for (i = 0; radeonfb_limits[i].size; i++) { 603 if (sc->sc_memsz >= radeonfb_limits[i].size) { 604 sc->sc_maxx = radeonfb_limits[i].maxx; 605 sc->sc_maxy = radeonfb_limits[i].maxy; 606 sc->sc_maxbpp = radeonfb_limits[i].maxbpp; 607 /* framebuffer offset, start at a 4K page */ 608 sc->sc_fboffset = sc->sc_memsz / 609 radeonfb_limits[i].maxdisp; 610 /* 611 * we use the fbsize to figure out where we can store 612 * things like cursor data. 613 */ 614 sc->sc_fbsize = 615 ROUNDUP(ROUNDUP(sc->sc_maxx * sc->sc_maxbpp / 8 , 616 RADEON_STRIDEALIGN) * sc->sc_maxy, 617 4096); 618 break; 619 } 620 } 621 622 623 radeonfb_init_misc(sc); 624 radeonfb_init_palette(sc, 0); 625 if (HAS_CRTC2(sc)) 626 radeonfb_init_palette(sc, 1); 627 628 /* program the DAC wirings */ 629 for (i = 0; i < (HAS_CRTC2(sc) ? 2 : 1); i++) { 630 switch (sc->sc_ports[i].rp_dac_type) { 631 case RADEON_DAC_PRIMARY: 632 PATCH32(sc, RADEON_DAC_CNTL2, 633 i ? RADEON_DAC2_DAC_CLK_SEL : 0, 634 ~RADEON_DAC2_DAC_CLK_SEL); 635 break; 636 case RADEON_DAC_TVDAC: 637 /* we always use the TVDAC to drive a secondary analog 638 * CRT for now. if we ever support TV-out this will 639 * have to change. 640 */ 641 SET32(sc, RADEON_DAC_CNTL2, 642 RADEON_DAC2_DAC2_CLK_SEL); 643 PATCH32(sc, RADEON_DISP_HW_DEBUG, 644 i ? 0 : RADEON_CRT2_DISP1_SEL, 645 ~RADEON_CRT2_DISP1_SEL); 646 break; 647 } 648 } 649 PRINTREG(RADEON_DAC_CNTL2); 650 PRINTREG(RADEON_DISP_HW_DEBUG); 651 652 /* other DAC programming */ 653 v = GET32(sc, RADEON_DAC_CNTL); 654 v &= (RADEON_DAC_RANGE_CNTL_MASK | RADEON_DAC_BLANKING); 655 v |= RADEON_DAC_MASK_ALL | RADEON_DAC_8BIT_EN; 656 PUT32(sc, RADEON_DAC_CNTL, v); 657 PRINTREG(RADEON_DAC_CNTL); 658 659 /* XXX: this may need more investigation */ 660 PUT32(sc, RADEON_TV_DAC_CNTL, 0x00280203); 661 PRINTREG(RADEON_TV_DAC_CNTL); 662 663 /* enable TMDS */ 664 SET32(sc, RADEON_FP_GEN_CNTL, 665 RADEON_FP_TMDS_EN | 666 RADEON_FP_CRTC_DONT_SHADOW_VPAR | 667 RADEON_FP_CRTC_DONT_SHADOW_HEND); 668 /* 669 * XXX 670 * no idea why this is necessary - if I do not clear this bit on my 671 * iBook G4 the screen remains black, even though it's already clear. 672 * It needs to be set on my Sun XVR-100 for the DVI port to work 673 */ 674 675 if (sc->sc_fp_gen_cntl & RADEON_FP_SEL_CRTC2) { 676 SET32(sc, RADEON_FP_GEN_CNTL, RADEON_FP_SEL_CRTC2); 677 } else 678 CLR32(sc, RADEON_FP_GEN_CNTL, RADEON_FP_SEL_CRTC2); 679 680 if (HAS_CRTC2(sc)) 681 SET32(sc, RADEON_FP2_GEN_CNTL, RADEON_FP2_SRC_SEL_CRTC2); 682 683 /* 684 * we use bus_space_map instead of pci_mapreg, because we don't 685 * need the full aperature space. no point in wasting virtual 686 * address space we don't intend to use, right? 687 */ 688 if ((sc->sc_memsz < (4096 * 1024)) || 689 (pci_mapreg_info(sc->sc_pc, sc->sc_pt, RADEON_MAPREG_VRAM, 690 PCI_MAPREG_TYPE_MEM, &sc->sc_memaddr, &bsz, NULL) != 0) || 691 (bsz < sc->sc_memsz)) { 692 sc->sc_memsz = 0; 693 aprint_error("%s: Bad frame buffer configuration\n", 694 XNAME(sc)); 695 goto error; 696 } 697 698 /* 64 MB should be enough -- more just wastes map entries */ 699 if (sc->sc_memsz > (64 << 20)) 700 sc->sc_memsz = (64 << 20); 701 702 sc->sc_memt = pa->pa_memt; 703 if (bus_space_map(sc->sc_memt, sc->sc_memaddr, sc->sc_memsz, 704 BUS_SPACE_MAP_LINEAR, &sc->sc_memh) != 0) { 705 sc->sc_memsz = 0; 706 aprint_error("%s: Unable to map frame buffer\n", XNAME(sc)); 707 goto error; 708 } 709 710 aprint_normal("%s: %d MB aperture at 0x%08x, " 711 "%d KB registers at 0x%08x\n", XNAME(sc), 712 (int)sc->sc_memsz >> 20, (unsigned)sc->sc_memaddr, 713 (int)sc->sc_regsz >> 10, (unsigned)sc->sc_regaddr); 714 715 /* setup default video mode from devprop (allows PROM override) */ 716 sc->sc_defaultmode = radeonfb_default_mode; 717 if (prop_dictionary_get_cstring_nocopy(device_properties(&sc->sc_dev), 718 "videomode", &mptr)) { 719 720 strncpy(sc->sc_modebuf, mptr, sizeof(sc->sc_modebuf)); 721 sc->sc_defaultmode = sc->sc_modebuf; 722 } 723 724 /* initialize some basic display parameters */ 725 for (i = 0; i < sc->sc_ndisplays; i++) { 726 struct radeonfb_display *dp = &sc->sc_displays[i]; 727 struct rasops_info *ri; 728 long defattr; 729 struct wsemuldisplaydev_attach_args aa; 730 731 /* 732 * Figure out how many "displays" (desktops) we are going to 733 * support. If more than one, then each CRTC gets its own 734 * programming. 735 * 736 * XXX: this code needs to change to support mergedfb. 737 * XXX: would be nice to allow this to be overridden 738 */ 739 if (HAS_CRTC2(sc) && (sc->sc_ndisplays == 1)) { 740 DPRINTF(("dual crtcs!\n")); 741 dp->rd_ncrtcs = 2; 742 dp->rd_crtcs[0].rc_number = 0; 743 dp->rd_crtcs[1].rc_number = 1; 744 } else { 745 dp->rd_ncrtcs = 1; 746 dp->rd_crtcs[0].rc_number = i; 747 } 748 749 /* set up port pointer */ 750 for (j = 0; j < dp->rd_ncrtcs; j++) { 751 dp->rd_crtcs[j].rc_port = 752 &sc->sc_ports[dp->rd_crtcs[j].rc_number]; 753 } 754 755 dp->rd_softc = sc; 756 dp->rd_wsmode = WSDISPLAYIO_MODE_EMUL; 757 dp->rd_bg = WS_DEFAULT_BG; 758 #if 0 759 dp->rd_bpp = sc->sc_maxbpp; /* XXX: for now */ 760 #else 761 dp->rd_bpp = RADEONFB_DEFAULT_DEPTH; /* XXX */ 762 #endif 763 /* for text mode, we pick a resolution that won't 764 * require panning */ 765 radeonfb_pickres(dp, &dp->rd_virtx, &dp->rd_virty, 0); 766 767 aprint_normal("%s: display %d: " 768 "initial virtual resolution %dx%d at %d bpp\n", 769 XNAME(sc), i, dp->rd_virtx, dp->rd_virty, dp->rd_bpp); 770 771 /* now select the *video mode* that we will use */ 772 for (j = 0; j < dp->rd_ncrtcs; j++) { 773 const struct videomode *vmp; 774 vmp = radeonfb_port_mode(sc, dp->rd_crtcs[j].rc_port, 775 dp->rd_virtx, dp->rd_virty); 776 777 /* 778 * virtual resolution should be at least as high as 779 * physical 780 */ 781 if (dp->rd_virtx < vmp->hdisplay || 782 dp->rd_virty < vmp->vdisplay) { 783 dp->rd_virtx = vmp->hdisplay; 784 dp->rd_virty = vmp->vdisplay; 785 } 786 787 dp->rd_crtcs[j].rc_videomode = *vmp; 788 printf("%s: port %d: physical %dx%d %dHz\n", 789 XNAME(sc), j, vmp->hdisplay, vmp->vdisplay, 790 DIVIDE(DIVIDE(vmp->dot_clock * 1000, 791 vmp->htotal), vmp->vtotal)); 792 } 793 794 /* N.B.: radeon wants 64-byte aligned stride */ 795 dp->rd_stride = dp->rd_virtx * dp->rd_bpp / 8; 796 dp->rd_stride = ROUNDUP(dp->rd_stride, RADEON_STRIDEALIGN); 797 798 dp->rd_offset = sc->sc_fboffset * i; 799 dp->rd_fbptr = (vaddr_t)bus_space_vaddr(sc->sc_memt, 800 sc->sc_memh) + dp->rd_offset; 801 dp->rd_curoff = sc->sc_fbsize; 802 dp->rd_curptr = dp->rd_fbptr + dp->rd_curoff; 803 804 DPRINTF(("fpbtr = %p\n", (void *)dp->rd_fbptr)); 805 806 switch (dp->rd_bpp) { 807 case 8: 808 dp->rd_format = 2; 809 break; 810 case 32: 811 dp->rd_format = 6; 812 break; 813 default: 814 aprint_error("%s: bad depth %d\n", XNAME(sc), 815 dp->rd_bpp); 816 goto error; 817 } 818 819 DPRINTF("init engine\n"); 820 /* XXX: this seems suspicious - per display engine 821 initialization? */ 822 radeonfb_engine_init(dp); 823 824 /* copy the template into place */ 825 dp->rd_wsscreens_storage[0] = radeonfb_stdscreen; 826 dp->rd_wsscreens = dp->rd_wsscreens_storage; 827 828 /* and make up the list */ 829 dp->rd_wsscreenlist.nscreens = 1; 830 dp->rd_wsscreenlist.screens = 831 (const struct wsscreen_descr **)&dp->rd_wsscreens; 832 833 vcons_init(&dp->rd_vd, dp, dp->rd_wsscreens, 834 &radeonfb_accessops); 835 836 dp->rd_vd.init_screen = radeonfb_init_screen; 837 838 dp->rd_console = 0; 839 prop_dictionary_get_bool(device_properties(&sc->sc_dev), 840 "is_console", &dp->rd_console); 841 842 dp->rd_vscreen.scr_flags |= VCONS_SCREEN_IS_STATIC; 843 844 845 vcons_init_screen(&dp->rd_vd, &dp->rd_vscreen, 846 dp->rd_console, &defattr); 847 848 ri = &dp->rd_vscreen.scr_ri; 849 850 /* clear the screen */ 851 rasops_unpack_attr(defattr, &fg, &bg, &ul); 852 radeonfb_rectfill(dp, 0, 0, ri->ri_width, ri->ri_height, 853 ri->ri_devcmap[bg & 0xf]); 854 855 dp->rd_wsscreens->textops = &ri->ri_ops; 856 dp->rd_wsscreens->capabilities = ri->ri_caps; 857 dp->rd_wsscreens->nrows = ri->ri_rows; 858 dp->rd_wsscreens->ncols = ri->ri_cols; 859 860 #ifdef SPLASHSCREEN 861 dp->rd_splash.si_depth = ri->ri_depth; 862 dp->rd_splash.si_bits = ri->ri_bits; 863 dp->rd_splash.si_hwbits = ri->ri_hwbits; 864 dp->rd_splash.si_width = ri->ri_width; 865 dp->rd_splash.si_height = ri->ri_height; 866 dp->rd_splash.si_stride = ri->ri_stride; 867 dp->rd_splash.si_fillrect = NULL; 868 #endif 869 if (dp->rd_console) { 870 871 radeonfb_modeswitch(dp); 872 wsdisplay_cnattach(dp->rd_wsscreens, ri, 0, 0, 873 defattr); 874 #ifdef SPLASHSCREEN 875 splash_render(&dp->rd_splash, 876 SPLASH_F_CENTER|SPLASH_F_FILL); 877 #else 878 vcons_replay_msgbuf(&dp->rd_vscreen); 879 #endif 880 881 #ifdef SPLASHSCREEN_PROGRESS 882 dp->rd_progress.sp_top = (dp->rd_virty / 8) * 7; 883 dp->rd_progress.sp_width = (dp->rd_virtx / 4) * 3; 884 dp->rd_progress.sp_left = (dp->rd_virtx - 885 dp->rd_progress.sp_width) / 2; 886 dp->rd_progress.sp_height = 20; 887 dp->rd_progress.sp_state = -1; 888 dp->rd_progress.sp_si = &dp->rd_splash; 889 splash_progress_init(&dp->rd_progress); 890 SCREEN_DISABLE_DRAWING(&dp->rd_vscreen); 891 #endif 892 893 } else { 894 895 /* 896 * since we're not the console we can postpone 897 * the rest until someone actually allocates a 898 * screen for us. but we do clear the screen 899 * at least. 900 */ 901 memset(ri->ri_bits, 0, 1024); 902 903 radeonfb_modeswitch(dp); 904 #ifdef SPLASHSCREEN 905 splash_render(&dp->rd_splash, 906 SPLASH_F_CENTER|SPLASH_F_FILL); 907 SCREEN_DISABLE_DRAWING(&dp->rd_vscreen); 908 #endif 909 } 910 911 aa.console = dp->rd_console; 912 aa.scrdata = &dp->rd_wsscreenlist; 913 aa.accessops = &radeonfb_accessops; 914 aa.accesscookie = &dp->rd_vd; 915 916 config_found(&sc->sc_dev, &aa, wsemuldisplaydevprint); 917 918 radeonfb_blank(dp, 0); 919 920 /* Initialise delayed lvds operations for backlight. */ 921 callout_init(&dp->rd_bl_lvds_co, 0); 922 callout_setfunc(&dp->rd_bl_lvds_co, 923 radeonfb_lvds_callout, dp); 924 } 925 926 /* 927 * if we have console output via firmware like on sparc64 it may 928 * interfere with DAC programming so program the palette again 929 * here after we took over 930 */ 931 radeonfb_init_palette(sc, 0); 932 if (HAS_CRTC2(sc)) 933 radeonfb_init_palette(sc, 1); 934 935 pmf_event_register(dev, PMFE_DISPLAY_BRIGHTNESS_UP, 936 radeonfb_brightness_up, TRUE); 937 pmf_event_register(dev, PMFE_DISPLAY_BRIGHTNESS_DOWN, 938 radeonfb_brightness_down, TRUE); 939 940 config_found_ia(dev, "drm", aux, radeonfb_drm_print); 941 942 return; 943 944 error: 945 if (sc->sc_biossz) 946 free(sc->sc_bios, M_DEVBUF); 947 948 if (sc->sc_regsz) 949 bus_space_unmap(sc->sc_regt, sc->sc_regh, sc->sc_regsz); 950 951 if (sc->sc_memsz) 952 bus_space_unmap(sc->sc_memt, sc->sc_memh, sc->sc_memsz); 953 } 954 955 static int 956 radeonfb_drm_print(void *aux, const char *pnp) 957 { 958 if (pnp) 959 aprint_normal("drm at %s", pnp); 960 return (UNCONF); 961 } 962 963 int 964 radeonfb_ioctl(void *v, void *vs, 965 unsigned long cmd, void *d, int flag, struct lwp *l) 966 { 967 struct vcons_data *vd; 968 struct radeonfb_display *dp; 969 struct radeonfb_softc *sc; 970 struct wsdisplay_param *param; 971 972 vd = (struct vcons_data *)v; 973 dp = (struct radeonfb_display *)vd->cookie; 974 sc = dp->rd_softc; 975 976 switch (cmd) { 977 case WSDISPLAYIO_GTYPE: 978 *(unsigned *)d = WSDISPLAY_TYPE_PCIMISC; 979 return 0; 980 981 case WSDISPLAYIO_GINFO: 982 if (vd->active != NULL) { 983 struct wsdisplay_fbinfo *fb; 984 fb = (struct wsdisplay_fbinfo *)d; 985 fb->width = dp->rd_virtx; 986 fb->height = dp->rd_virty; 987 fb->depth = dp->rd_bpp; 988 fb->cmsize = 256; 989 return 0; 990 } else 991 return ENODEV; 992 case WSDISPLAYIO_GVIDEO: 993 if (radeonfb_isblank(dp)) 994 *(unsigned *)d = WSDISPLAYIO_VIDEO_OFF; 995 else 996 *(unsigned *)d = WSDISPLAYIO_VIDEO_ON; 997 return 0; 998 999 case WSDISPLAYIO_SVIDEO: 1000 radeonfb_blank(dp, 1001 (*(unsigned int *)d == WSDISPLAYIO_VIDEO_OFF)); 1002 return 0; 1003 1004 case WSDISPLAYIO_GETCMAP: 1005 #if 0 1006 if (dp->rd_bpp == 8) 1007 return radeonfb_getcmap(sc, 1008 (struct wsdisplay_cmap *)d); 1009 #endif 1010 return EINVAL; 1011 1012 case WSDISPLAYIO_PUTCMAP: 1013 #if 0 1014 if (dp->rd_bpp == 8) 1015 return radeonfb_putcmap(sc, 1016 (struct wsdisplay_cmap *)d); 1017 #endif 1018 return EINVAL; 1019 1020 case WSDISPLAYIO_LINEBYTES: 1021 *(unsigned *)d = dp->rd_stride; 1022 return 0; 1023 1024 case WSDISPLAYIO_SMODE: 1025 if (*(int *)d != dp->rd_wsmode) { 1026 dp->rd_wsmode = *(int *)d; 1027 if ((dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) && 1028 (dp->rd_vd.active)) { 1029 radeonfb_engine_init(dp); 1030 radeonfb_modeswitch(dp); 1031 vcons_redraw_screen(dp->rd_vd.active); 1032 } 1033 } 1034 return 0; 1035 1036 case WSDISPLAYIO_GCURMAX: 1037 ((struct wsdisplay_curpos *)d)->x = RADEON_CURSORMAXX; 1038 ((struct wsdisplay_curpos *)d)->y = RADEON_CURSORMAXY; 1039 return 0; 1040 1041 case WSDISPLAYIO_SCURSOR: 1042 return radeonfb_set_cursor(dp, (struct wsdisplay_cursor *)d); 1043 1044 case WSDISPLAYIO_GCURSOR: 1045 return EPASSTHROUGH; 1046 1047 case WSDISPLAYIO_GCURPOS: 1048 ((struct wsdisplay_curpos *)d)->x = dp->rd_cursor.rc_pos.x; 1049 ((struct wsdisplay_curpos *)d)->y = dp->rd_cursor.rc_pos.y; 1050 return 0; 1051 1052 case WSDISPLAYIO_SCURPOS: 1053 return radeonfb_set_curpos(dp, (struct wsdisplay_curpos *)d); 1054 1055 case WSDISPLAYIO_SSPLASH: 1056 #if defined(SPLASHSCREEN) 1057 if (*(int *)d == 1) { 1058 SCREEN_DISABLE_DRAWING(&dp->rd_vscreen); 1059 splash_render(&dp->rd_splash, 1060 SPLASH_F_CENTER|SPLASH_F_FILL); 1061 } else 1062 SCREEN_ENABLE_DRAWING(&dp->rd_vscreen); 1063 return 0; 1064 #else 1065 return ENODEV; 1066 #endif 1067 case WSDISPLAYIO_SPROGRESS: 1068 #if defined(SPLASHSCREEN) && defined(SPLASHSCREEN_PROGRESS) 1069 dp->rd_progress.sp_force = 1; 1070 splash_progress_update(&dp->rd_progress); 1071 dp->rd_progress.sp_force = 0; 1072 return 0; 1073 #else 1074 return ENODEV; 1075 #endif 1076 case WSDISPLAYIO_GETPARAM: 1077 param = (struct wsdisplay_param *)d; 1078 if (param->param == WSDISPLAYIO_PARAM_BACKLIGHT) { 1079 param->min = 0; 1080 param->max = RADEONFB_BACKLIGHT_MAX; 1081 param->curval = radeonfb_get_backlight(dp); 1082 return 0; 1083 } 1084 return EPASSTHROUGH; 1085 1086 case WSDISPLAYIO_SETPARAM: 1087 param = (struct wsdisplay_param *)d; 1088 if (param->param == WSDISPLAYIO_PARAM_BACKLIGHT) { 1089 return radeonfb_set_backlight(dp, param->curval); 1090 } 1091 return EPASSTHROUGH; 1092 1093 /* PCI config read/write passthrough. */ 1094 case PCI_IOC_CFGREAD: 1095 case PCI_IOC_CFGWRITE: 1096 return (pci_devioctl(sc->sc_pc, sc->sc_pt, cmd, d, flag, l)); 1097 1098 default: 1099 return EPASSTHROUGH; 1100 } 1101 } 1102 1103 paddr_t 1104 radeonfb_mmap(void *v, void *vs, off_t offset, int prot) 1105 { 1106 struct vcons_data *vd; 1107 struct radeonfb_display *dp; 1108 struct radeonfb_softc *sc; 1109 paddr_t pa; 1110 1111 vd = (struct vcons_data *)v; 1112 dp = (struct radeonfb_display *)vd->cookie; 1113 sc = dp->rd_softc; 1114 1115 /* XXX: note that we don't allow mapping of registers right now */ 1116 /* XXX: this means that the XFree86 radeon driver won't work */ 1117 if ((offset >= 0) && (offset < (dp->rd_virty * dp->rd_stride))) { 1118 pa = bus_space_mmap(sc->sc_memt, 1119 sc->sc_memaddr + dp->rd_offset + offset, 0, 1120 prot, BUS_SPACE_MAP_LINEAR); 1121 return pa; 1122 } 1123 1124 #ifdef RADEONFB_MMAP_BARS 1125 /* 1126 * restrict all other mappings to processes with superuser privileges 1127 * or the kernel itself 1128 */ 1129 if (kauth_authorize_generic(kauth_cred_get(), KAUTH_GENERIC_ISSUSER, 1130 NULL) != 0) { 1131 aprint_error_dev(&sc->sc_dev, "mmap() rejected.\n"); 1132 return -1; 1133 } 1134 1135 if ((offset >= sc->sc_regaddr) && 1136 (offset < sc->sc_regaddr + sc->sc_regsz)) { 1137 return bus_space_mmap(sc->sc_regt, offset, 0, prot, 1138 BUS_SPACE_MAP_LINEAR); 1139 } 1140 1141 if ((offset >= sc->sc_memaddr) && 1142 (offset < sc->sc_memaddr + sc->sc_memsz)) { 1143 return bus_space_mmap(sc->sc_memt, offset, 0, prot, 1144 BUS_SPACE_MAP_LINEAR); 1145 } 1146 1147 if ((offset >= sc->sc_romaddr) && 1148 (offset < sc->sc_romaddr + sc->sc_romsz)) { 1149 return bus_space_mmap(sc->sc_memt, offset, 0, prot, 1150 BUS_SPACE_MAP_LINEAR); 1151 } 1152 1153 #ifdef PCI_MAGIC_IO_RANGE 1154 /* allow mapping of IO space */ 1155 if ((offset >= PCI_MAGIC_IO_RANGE) && 1156 (offset < PCI_MAGIC_IO_RANGE + 0x10000)) { 1157 pa = bus_space_mmap(sc->sc_iot, offset - PCI_MAGIC_IO_RANGE, 1158 0, prot, 0); 1159 return pa; 1160 } 1161 #endif /* macppc */ 1162 1163 #endif /* RADEONFB_MMAP_BARS */ 1164 1165 return -1; 1166 } 1167 1168 static void 1169 radeonfb_loadbios(struct radeonfb_softc *sc, struct pci_attach_args *pa) 1170 { 1171 bus_space_tag_t romt; 1172 bus_space_handle_t romh, biosh; 1173 bus_size_t romsz; 1174 bus_addr_t ptr; 1175 1176 if (pci_mapreg_map(pa, PCI_MAPREG_ROM, PCI_MAPREG_TYPE_ROM, 1177 BUS_SPACE_MAP_PREFETCHABLE, &romt, &romh, NULL, &romsz) != 0) { 1178 aprint_verbose("%s: unable to map BIOS!\n", XNAME(sc)); 1179 return; 1180 } 1181 1182 pci_find_rom(pa, romt, romh, PCI_ROM_CODE_TYPE_X86, &biosh, 1183 &sc->sc_biossz); 1184 if (sc->sc_biossz == 0) { 1185 aprint_verbose("%s: Video BIOS not present\n", XNAME(sc)); 1186 return; 1187 } 1188 1189 sc->sc_bios = malloc(sc->sc_biossz, M_DEVBUF, M_WAITOK); 1190 bus_space_read_region_1(romt, biosh, 0, sc->sc_bios, sc->sc_biossz); 1191 1192 /* unmap the PCI expansion rom */ 1193 bus_space_unmap(romt, romh, romsz); 1194 1195 /* turn off rom decoder now */ 1196 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM, 1197 pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM) & 1198 ~PCI_MAPREG_ROM_ENABLE); 1199 1200 ptr = GETBIOS16(sc, 0x48); 1201 if ((GETBIOS32(sc, ptr + 4) == 0x41544f4d /* "ATOM" */) || 1202 (GETBIOS32(sc, ptr + 4) == 0x4d4f5441 /* "MOTA" */)) { 1203 sc->sc_flags |= RFB_ATOM; 1204 } 1205 1206 aprint_verbose("%s: Found %d KB %s BIOS\n", XNAME(sc), 1207 (unsigned)sc->sc_biossz >> 10, IS_ATOM(sc) ? "ATOM" : "Legacy"); 1208 } 1209 1210 1211 uint32_t 1212 radeonfb_get32(struct radeonfb_softc *sc, uint32_t reg) 1213 { 1214 1215 return bus_space_read_4(sc->sc_regt, sc->sc_regh, reg); 1216 } 1217 1218 void 1219 radeonfb_put32(struct radeonfb_softc *sc, uint32_t reg, uint32_t val) 1220 { 1221 1222 bus_space_write_4(sc->sc_regt, sc->sc_regh, reg, val); 1223 } 1224 1225 void 1226 radeonfb_mask32(struct radeonfb_softc *sc, uint32_t reg, 1227 uint32_t andmask, uint32_t ormask) 1228 { 1229 int s; 1230 uint32_t val; 1231 1232 s = splhigh(); 1233 val = radeonfb_get32(sc, reg); 1234 val = (val & andmask) | ormask; 1235 radeonfb_put32(sc, reg, val); 1236 splx(s); 1237 } 1238 1239 uint32_t 1240 radeonfb_getindex(struct radeonfb_softc *sc, uint32_t idx) 1241 { 1242 int s; 1243 uint32_t val; 1244 1245 s = splhigh(); 1246 radeonfb_put32(sc, RADEON_MM_INDEX, idx); 1247 val = radeonfb_get32(sc, RADEON_MM_DATA); 1248 splx(s); 1249 1250 return (val); 1251 } 1252 1253 void 1254 radeonfb_putindex(struct radeonfb_softc *sc, uint32_t idx, uint32_t val) 1255 { 1256 int s; 1257 1258 s = splhigh(); 1259 radeonfb_put32(sc, RADEON_MM_INDEX, idx); 1260 radeonfb_put32(sc, RADEON_MM_DATA, val); 1261 splx(s); 1262 } 1263 1264 void 1265 radeonfb_maskindex(struct radeonfb_softc *sc, uint32_t idx, 1266 uint32_t andmask, uint32_t ormask) 1267 { 1268 int s; 1269 uint32_t val; 1270 1271 s = splhigh(); 1272 radeonfb_put32(sc, RADEON_MM_INDEX, idx); 1273 val = radeonfb_get32(sc, RADEON_MM_DATA); 1274 val = (val & andmask) | ormask; 1275 radeonfb_put32(sc, RADEON_MM_DATA, val); 1276 splx(s); 1277 } 1278 1279 uint32_t 1280 radeonfb_getpll(struct radeonfb_softc *sc, uint32_t idx) 1281 { 1282 int s; 1283 uint32_t val; 1284 1285 s = splhigh(); 1286 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, idx & 0x3f); 1287 val = radeonfb_get32(sc, RADEON_CLOCK_CNTL_DATA); 1288 if (HAS_R300CG(sc)) 1289 radeonfb_r300cg_workaround(sc); 1290 splx(s); 1291 1292 return (val); 1293 } 1294 1295 void 1296 radeonfb_putpll(struct radeonfb_softc *sc, uint32_t idx, uint32_t val) 1297 { 1298 int s; 1299 1300 s = splhigh(); 1301 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, (idx & 0x3f) | 1302 RADEON_PLL_WR_EN); 1303 radeonfb_put32(sc, RADEON_CLOCK_CNTL_DATA, val); 1304 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, 0); 1305 splx(s); 1306 } 1307 1308 void 1309 radeonfb_maskpll(struct radeonfb_softc *sc, uint32_t idx, 1310 uint32_t andmask, uint32_t ormask) 1311 { 1312 int s; 1313 uint32_t val; 1314 1315 s = splhigh(); 1316 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, (idx & 0x3f) | 1317 RADEON_PLL_WR_EN); 1318 val = radeonfb_get32(sc, RADEON_CLOCK_CNTL_DATA); 1319 val = (val & andmask) | ormask; 1320 radeonfb_put32(sc, RADEON_CLOCK_CNTL_DATA, val); 1321 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, 0); 1322 splx(s); 1323 } 1324 1325 int 1326 radeonfb_scratch_test(struct radeonfb_softc *sc, int reg, uint32_t v) 1327 { 1328 uint32_t saved; 1329 1330 saved = GET32(sc, reg); 1331 PUT32(sc, reg, v); 1332 if (GET32(sc, reg) != v) { 1333 return -1; 1334 } 1335 PUT32(sc, reg, saved); 1336 return 0; 1337 } 1338 1339 uintmax_t 1340 radeonfb_getprop_num(struct radeonfb_softc *sc, const char *name, 1341 uintmax_t defval) 1342 { 1343 prop_number_t pn; 1344 pn = prop_dictionary_get(device_properties(&sc->sc_dev), name); 1345 if (pn == NULL) { 1346 return defval; 1347 } 1348 KASSERT(prop_object_type(pn) == PROP_TYPE_NUMBER); 1349 return (prop_number_integer_value(pn)); 1350 } 1351 1352 int 1353 radeonfb_getclocks(struct radeonfb_softc *sc) 1354 { 1355 bus_addr_t ptr; 1356 int refclk = 0; 1357 int refdiv = 0; 1358 int minpll = 0; 1359 int maxpll = 0; 1360 1361 /* load initial property values if port/board provides them */ 1362 refclk = radeonfb_getprop_num(sc, "refclk", 0) & 0xffff; 1363 refdiv = radeonfb_getprop_num(sc, "refdiv", 0) & 0xffff; 1364 minpll = radeonfb_getprop_num(sc, "minpll", 0) & 0xffffffffU; 1365 maxpll = radeonfb_getprop_num(sc, "maxpll", 0) & 0xffffffffU; 1366 1367 if (refclk && refdiv && minpll && maxpll) 1368 goto dontprobe; 1369 1370 if (!sc->sc_biossz) { 1371 /* no BIOS */ 1372 aprint_verbose("%s: No video BIOS, using default clocks\n", 1373 XNAME(sc)); 1374 if (IS_IGP(sc)) 1375 refclk = refclk ? refclk : 1432; 1376 else 1377 refclk = refclk ? refclk : 2700; 1378 refdiv = refdiv ? refdiv : 12; 1379 minpll = minpll ? minpll : 12500; 1380 maxpll = maxpll ? maxpll : 35000; 1381 } else if (IS_ATOM(sc)) { 1382 /* ATOM BIOS */ 1383 ptr = GETBIOS16(sc, 0x48); 1384 ptr = GETBIOS16(sc, ptr + 32); /* aka MasterDataStart */ 1385 ptr = GETBIOS16(sc, ptr + 12); /* pll info block */ 1386 refclk = refclk ? refclk : GETBIOS16(sc, ptr + 82); 1387 minpll = minpll ? minpll : GETBIOS16(sc, ptr + 78); 1388 maxpll = maxpll ? maxpll : GETBIOS16(sc, ptr + 32); 1389 /* 1390 * ATOM BIOS doesn't supply a reference divider, so we 1391 * have to probe for it. 1392 */ 1393 if (refdiv < 2) 1394 refdiv = GETPLL(sc, RADEON_PPLL_REF_DIV) & 1395 RADEON_PPLL_REF_DIV_MASK; 1396 /* 1397 * if probe is zero, just assume one that should work 1398 * for most parts 1399 */ 1400 if (refdiv < 2) 1401 refdiv = 12; 1402 1403 } else { 1404 /* Legacy BIOS */ 1405 ptr = GETBIOS16(sc, 0x48); 1406 ptr = GETBIOS16(sc, ptr + 0x30); 1407 refclk = refclk ? refclk : GETBIOS16(sc, ptr + 0x0E); 1408 refdiv = refdiv ? refdiv : GETBIOS16(sc, ptr + 0x10); 1409 minpll = minpll ? minpll : GETBIOS32(sc, ptr + 0x12); 1410 maxpll = maxpll ? maxpll : GETBIOS32(sc, ptr + 0x16); 1411 } 1412 1413 1414 dontprobe: 1415 sc->sc_refclk = refclk * 10; 1416 sc->sc_refdiv = refdiv; 1417 sc->sc_minpll = minpll * 10; 1418 sc->sc_maxpll = maxpll * 10; 1419 return 0; 1420 } 1421 1422 int 1423 radeonfb_calc_dividers(struct radeonfb_softc *sc, uint32_t dotclock, 1424 uint32_t *postdivbit, uint32_t *feedbackdiv) 1425 { 1426 int i; 1427 uint32_t outfreq; 1428 int div; 1429 1430 DPRINTF(("dot clock: %u\n", dotclock)); 1431 for (i = 0; (div = radeonfb_dividers[i].divider) != 0; i++) { 1432 outfreq = div * dotclock; 1433 if ((outfreq >= sc->sc_minpll) && 1434 (outfreq <= sc->sc_maxpll)) { 1435 DPRINTF(("outfreq: %u\n", outfreq)); 1436 *postdivbit = 1437 ((uint32_t)radeonfb_dividers[i].mask << 16); 1438 DPRINTF(("post divider: %d (mask %x)\n", div, 1439 *postdivbit)); 1440 break; 1441 } 1442 } 1443 1444 if (div == 0) 1445 return 1; 1446 1447 *feedbackdiv = DIVIDE(sc->sc_refdiv * outfreq, sc->sc_refclk); 1448 DPRINTF(("feedback divider: %d\n", *feedbackdiv)); 1449 return 0; 1450 } 1451 1452 #if 0 1453 #ifdef RADEONFB_DEBUG 1454 static void 1455 dump_buffer(const char *pfx, void *buffer, unsigned int size) 1456 { 1457 char asc[17]; 1458 unsigned ptr = (unsigned)buffer; 1459 char *start = (char *)(ptr & ~0xf); 1460 char *end = (char *)(ptr + size); 1461 1462 end = (char *)(((unsigned)end + 0xf) & ~0xf); 1463 1464 if (pfx == NULL) { 1465 pfx = ""; 1466 } 1467 1468 while (start < end) { 1469 unsigned offset = (unsigned)start & 0xf; 1470 if (offset == 0) { 1471 printf("%s%x: ", pfx, (unsigned)start); 1472 } 1473 if (((unsigned)start < ptr) || 1474 ((unsigned)start >= (ptr + size))) { 1475 printf(" "); 1476 asc[offset] = ' '; 1477 } else { 1478 printf("%02x", *(unsigned char *)start); 1479 if ((*start >= ' ') && (*start <= '~')) { 1480 asc[offset] = *start; 1481 } else { 1482 asc[offset] = '.'; 1483 } 1484 } 1485 asc[offset + 1] = 0; 1486 if (offset % 2) { 1487 printf(" "); 1488 } 1489 if (offset == 15) { 1490 printf(" %s\n", asc); 1491 } 1492 start++; 1493 } 1494 } 1495 #endif 1496 #endif 1497 1498 int 1499 radeonfb_getconnectors(struct radeonfb_softc *sc) 1500 { 1501 int i; 1502 int found = 0; 1503 1504 for (i = 0; i < 2; i++) { 1505 sc->sc_ports[i].rp_mon_type = RADEON_MT_UNKNOWN; 1506 sc->sc_ports[i].rp_ddc_type = RADEON_DDC_NONE; 1507 sc->sc_ports[i].rp_dac_type = RADEON_DAC_UNKNOWN; 1508 sc->sc_ports[i].rp_conn_type = RADEON_CONN_NONE; 1509 sc->sc_ports[i].rp_tmds_type = RADEON_TMDS_UNKNOWN; 1510 } 1511 1512 /* 1513 * This logic is borrowed from Xorg's radeon driver. 1514 */ 1515 if (!sc->sc_biossz) 1516 goto nobios; 1517 1518 if (IS_ATOM(sc)) { 1519 /* not done yet */ 1520 } else { 1521 uint16_t ptr; 1522 int port = 0; 1523 1524 ptr = GETBIOS16(sc, 0x48); 1525 ptr = GETBIOS16(sc, ptr + 0x50); 1526 for (i = 1; i < 4; i++) { 1527 uint16_t entry; 1528 uint8_t conn, ddc, dac, tmds; 1529 1530 /* 1531 * Parse the connector table. From reading the code, 1532 * it appears to made up of 16-bit entries for each 1533 * connector. The 16-bits are defined as: 1534 * 1535 * bits 12-15 - connector type (0 == end of table) 1536 * bits 8-11 - DDC type 1537 * bits 5-7 - ??? 1538 * bit 4 - TMDS type (1 = EXT, 0 = INT) 1539 * bits 1-3 - ??? 1540 * bit 0 - DAC, 1 = TVDAC, 0 = primary 1541 */ 1542 if (!GETBIOS8(sc, ptr + i * 2) && i > 1) 1543 break; 1544 entry = GETBIOS16(sc, ptr + i * 2); 1545 1546 conn = (entry >> 12) & 0xf; 1547 ddc = (entry >> 8) & 0xf; 1548 dac = (entry & 0x1) ? RADEON_DAC_TVDAC : 1549 RADEON_DAC_PRIMARY; 1550 tmds = ((entry >> 4) & 0x1) ? RADEON_TMDS_EXT : 1551 RADEON_TMDS_INT; 1552 1553 if (conn == RADEON_CONN_NONE) 1554 continue; /* no connector */ 1555 1556 if ((found > 0) && 1557 (sc->sc_ports[port].rp_ddc_type == ddc)) { 1558 /* duplicate entry for same connector */ 1559 continue; 1560 } 1561 1562 /* internal DDC_DVI port gets priority */ 1563 if ((ddc == RADEON_DDC_DVI) || (port == 1)) 1564 port = 0; 1565 else 1566 port = 1; 1567 1568 sc->sc_ports[port].rp_ddc_type = 1569 ddc > RADEON_DDC_CRT2 ? RADEON_DDC_NONE : ddc; 1570 sc->sc_ports[port].rp_dac_type = dac; 1571 sc->sc_ports[port].rp_conn_type = 1572 min(conn, RADEON_CONN_UNSUPPORTED) ; 1573 1574 sc->sc_ports[port].rp_tmds_type = tmds; 1575 1576 if ((conn != RADEON_CONN_DVI_I) && 1577 (conn != RADEON_CONN_DVI_D) && 1578 (tmds == RADEON_TMDS_INT)) 1579 sc->sc_ports[port].rp_tmds_type = 1580 RADEON_TMDS_UNKNOWN; 1581 1582 found += (port + 1); 1583 } 1584 } 1585 1586 nobios: 1587 if (!found) { 1588 DPRINTF(("No connector info in BIOS!\n")); 1589 /* default, port 0 = internal TMDS, port 1 = CRT */ 1590 sc->sc_ports[0].rp_mon_type = RADEON_MT_UNKNOWN; 1591 sc->sc_ports[0].rp_ddc_type = RADEON_DDC_DVI; 1592 sc->sc_ports[0].rp_dac_type = RADEON_DAC_TVDAC; 1593 sc->sc_ports[0].rp_conn_type = RADEON_CONN_DVI_D; 1594 sc->sc_ports[0].rp_tmds_type = RADEON_TMDS_INT; 1595 1596 sc->sc_ports[1].rp_mon_type = RADEON_MT_UNKNOWN; 1597 sc->sc_ports[1].rp_ddc_type = RADEON_DDC_VGA; 1598 sc->sc_ports[1].rp_dac_type = RADEON_DAC_PRIMARY; 1599 sc->sc_ports[1].rp_conn_type = RADEON_CONN_CRT; 1600 sc->sc_ports[1].rp_tmds_type = RADEON_TMDS_EXT; 1601 } 1602 1603 /* 1604 * Fixup for RS300/RS350/RS400 chips, that lack a primary DAC. 1605 * these chips should use TVDAC for the VGA port. 1606 */ 1607 if (HAS_SDAC(sc)) { 1608 if (sc->sc_ports[0].rp_conn_type == RADEON_CONN_CRT) { 1609 sc->sc_ports[0].rp_dac_type = RADEON_DAC_TVDAC; 1610 sc->sc_ports[1].rp_dac_type = RADEON_DAC_PRIMARY; 1611 } else { 1612 sc->sc_ports[1].rp_dac_type = RADEON_DAC_TVDAC; 1613 sc->sc_ports[0].rp_dac_type = RADEON_DAC_PRIMARY; 1614 } 1615 } else if (!HAS_CRTC2(sc)) { 1616 sc->sc_ports[0].rp_dac_type = RADEON_DAC_PRIMARY; 1617 } 1618 1619 for (i = 0; i < 2; i++) { 1620 char edid[128]; 1621 uint8_t ddc; 1622 struct edid_info *eip = &sc->sc_ports[i].rp_edid; 1623 prop_data_t edid_data; 1624 1625 DPRINTF(("Port #%d:\n", i)); 1626 DPRINTF((" conn = %d\n", sc->sc_ports[i].rp_conn_type)); 1627 DPRINTF((" ddc = %d\n", sc->sc_ports[i].rp_ddc_type)); 1628 DPRINTF((" dac = %d\n", sc->sc_ports[i].rp_dac_type)); 1629 DPRINTF((" tmds = %d\n", sc->sc_ports[i].rp_tmds_type)); 1630 1631 sc->sc_ports[i].rp_edid_valid = 0; 1632 /* first look for static EDID data */ 1633 if ((edid_data = prop_dictionary_get(device_properties( 1634 &sc->sc_dev), "EDID")) != NULL) { 1635 1636 aprint_normal_dev(&sc->sc_dev, "using static EDID\n"); 1637 memcpy(edid, prop_data_data_nocopy(edid_data), 128); 1638 if (edid_parse(edid, eip) == 0) { 1639 1640 sc->sc_ports[i].rp_edid_valid = 1; 1641 } 1642 } 1643 /* if we didn't find any we'll try to talk to the monitor */ 1644 if (sc->sc_ports[i].rp_edid_valid != 1) { 1645 1646 ddc = sc->sc_ports[i].rp_ddc_type; 1647 if (ddc != RADEON_DDC_NONE) { 1648 if ((radeonfb_i2c_read_edid(sc, ddc, edid) 1649 == 0) && (edid_parse(edid, eip) == 0)) { 1650 1651 sc->sc_ports[i].rp_edid_valid = 1; 1652 edid_print(eip); 1653 } 1654 } 1655 } 1656 } 1657 1658 return found; 1659 } 1660 1661 int 1662 radeonfb_gettmds(struct radeonfb_softc *sc) 1663 { 1664 int i; 1665 1666 if (!sc->sc_biossz) { 1667 goto nobios; 1668 } 1669 1670 if (IS_ATOM(sc)) { 1671 /* XXX: not done yet */ 1672 } else { 1673 uint16_t ptr; 1674 int n; 1675 1676 ptr = GETBIOS16(sc, 0x48); 1677 ptr = GETBIOS16(sc, ptr + 0x34); 1678 DPRINTF(("DFP table revision %d\n", GETBIOS8(sc, ptr))); 1679 if (GETBIOS8(sc, ptr) == 3) { 1680 /* revision three table */ 1681 n = GETBIOS8(sc, ptr + 5) + 1; 1682 n = min(n, 4); 1683 1684 memset(sc->sc_tmds_pll, 0, sizeof (sc->sc_tmds_pll)); 1685 for (i = 0; i < n; i++) { 1686 sc->sc_tmds_pll[i].rtp_pll = GETBIOS32(sc, 1687 ptr + i * 10 + 8); 1688 sc->sc_tmds_pll[i].rtp_freq = GETBIOS16(sc, 1689 ptr + i * 10 + 0x10); 1690 DPRINTF(("TMDS_PLL dot clock %d pll %x\n", 1691 sc->sc_tmds_pll[i].rtp_freq, 1692 sc->sc_tmds_pll[i].rtp_pll)); 1693 } 1694 return 0; 1695 } 1696 } 1697 1698 nobios: 1699 DPRINTF(("no suitable DFP table present\n")); 1700 for (i = 0; 1701 i < sizeof (radeonfb_tmds_pll) / sizeof (radeonfb_tmds_pll[0]); 1702 i++) { 1703 int j; 1704 1705 if (radeonfb_tmds_pll[i].family != sc->sc_family) 1706 continue; 1707 1708 for (j = 0; j < 4; j++) { 1709 sc->sc_tmds_pll[j] = radeonfb_tmds_pll[i].plls[j]; 1710 DPRINTF(("TMDS_PLL dot clock %d pll %x\n", 1711 sc->sc_tmds_pll[j].rtp_freq, 1712 sc->sc_tmds_pll[j].rtp_pll)); 1713 } 1714 return 0; 1715 } 1716 1717 return -1; 1718 } 1719 1720 const struct videomode * 1721 radeonfb_modelookup(const char *name) 1722 { 1723 int i; 1724 1725 for (i = 0; i < videomode_count; i++) 1726 if (!strcmp(name, videomode_list[i].name)) 1727 return &videomode_list[i]; 1728 1729 return NULL; 1730 } 1731 1732 void 1733 radeonfb_pllwriteupdate(struct radeonfb_softc *sc, int crtc) 1734 { 1735 if (crtc) { 1736 while (GETPLL(sc, RADEON_P2PLL_REF_DIV) & 1737 RADEON_P2PLL_ATOMIC_UPDATE_R); 1738 SETPLL(sc, RADEON_P2PLL_REF_DIV, RADEON_P2PLL_ATOMIC_UPDATE_W); 1739 } else { 1740 while (GETPLL(sc, RADEON_PPLL_REF_DIV) & 1741 RADEON_PPLL_ATOMIC_UPDATE_R); 1742 SETPLL(sc, RADEON_PPLL_REF_DIV, RADEON_PPLL_ATOMIC_UPDATE_W); 1743 } 1744 } 1745 1746 void 1747 radeonfb_pllwaitatomicread(struct radeonfb_softc *sc, int crtc) 1748 { 1749 int i; 1750 1751 for (i = 10000; i; i--) { 1752 if (crtc) { 1753 if (GETPLL(sc, RADEON_P2PLL_REF_DIV) & 1754 RADEON_P2PLL_ATOMIC_UPDATE_R) 1755 break; 1756 } else { 1757 if (GETPLL(sc, RADEON_PPLL_REF_DIV) & 1758 RADEON_PPLL_ATOMIC_UPDATE_R) 1759 break; 1760 } 1761 } 1762 } 1763 1764 void 1765 radeonfb_program_vclk(struct radeonfb_softc *sc, int dotclock, int crtc) 1766 { 1767 uint32_t pbit = 0; 1768 uint32_t feed = 0; 1769 uint32_t data; 1770 #if 1 1771 int i; 1772 #endif 1773 1774 radeonfb_calc_dividers(sc, dotclock, &pbit, &feed); 1775 1776 if (crtc == 0) { 1777 1778 /* XXXX: mobility workaround missing */ 1779 /* XXXX: R300 stuff missing */ 1780 1781 PATCHPLL(sc, RADEON_VCLK_ECP_CNTL, 1782 RADEON_VCLK_SRC_SEL_CPUCLK, 1783 ~RADEON_VCLK_SRC_SEL_MASK); 1784 1785 /* put vclk into reset, use atomic updates */ 1786 SETPLL(sc, RADEON_PPLL_CNTL, 1787 RADEON_PPLL_REFCLK_SEL | 1788 RADEON_PPLL_FBCLK_SEL | 1789 RADEON_PPLL_RESET | 1790 RADEON_PPLL_ATOMIC_UPDATE_EN | 1791 RADEON_PPLL_VGA_ATOMIC_UPDATE_EN); 1792 1793 /* select clock 3 */ 1794 #if 0 1795 PATCH32(sc, RADEON_CLOCK_CNTL_INDEX, RADEON_PLL_DIV_SEL, 1796 ~RADEON_PLL_DIV_SEL); 1797 #else 1798 PATCH32(sc, RADEON_CLOCK_CNTL_INDEX, 0, 1799 ~RADEON_PLL_DIV_SEL); 1800 #endif 1801 1802 /* XXX: R300 family -- program divider differently? */ 1803 1804 /* program reference divider */ 1805 PATCHPLL(sc, RADEON_PPLL_REF_DIV, sc->sc_refdiv, 1806 ~RADEON_PPLL_REF_DIV_MASK); 1807 PRINTPLL(RADEON_PPLL_REF_DIV); 1808 1809 #if 0 1810 data = GETPLL(sc, RADEON_PPLL_DIV_3); 1811 data &= ~(RADEON_PPLL_FB3_DIV_MASK | 1812 RADEON_PPLL_POST3_DIV_MASK); 1813 data |= pbit; 1814 data |= (feed & RADEON_PPLL_FB3_DIV_MASK); 1815 PUTPLL(sc, RADEON_PPLL_DIV_3, data); 1816 #else 1817 for (i = 0; i < 4; i++) { 1818 } 1819 #endif 1820 1821 /* use the atomic update */ 1822 radeonfb_pllwriteupdate(sc, crtc); 1823 1824 /* and wait for it to complete */ 1825 radeonfb_pllwaitatomicread(sc, crtc); 1826 1827 /* program HTOTAL (why?) */ 1828 PUTPLL(sc, RADEON_HTOTAL_CNTL, 0); 1829 1830 /* drop reset */ 1831 CLRPLL(sc, RADEON_PPLL_CNTL, 1832 RADEON_PPLL_RESET | RADEON_PPLL_SLEEP | 1833 RADEON_PPLL_ATOMIC_UPDATE_EN | 1834 RADEON_PPLL_VGA_ATOMIC_UPDATE_EN); 1835 1836 PRINTPLL(RADEON_PPLL_CNTL); 1837 1838 /* give clock time to lock */ 1839 delay(50000); 1840 1841 PATCHPLL(sc, RADEON_VCLK_ECP_CNTL, 1842 RADEON_VCLK_SRC_SEL_PPLLCLK, 1843 ~RADEON_VCLK_SRC_SEL_MASK); 1844 1845 } else { 1846 1847 PATCHPLL(sc, RADEON_PIXCLKS_CNTL, 1848 RADEON_PIX2CLK_SRC_SEL_CPUCLK, 1849 ~RADEON_PIX2CLK_SRC_SEL_MASK); 1850 1851 /* put vclk into reset, use atomic updates */ 1852 SETPLL(sc, RADEON_P2PLL_CNTL, 1853 RADEON_P2PLL_RESET | 1854 RADEON_P2PLL_ATOMIC_UPDATE_EN | 1855 RADEON_P2PLL_VGA_ATOMIC_UPDATE_EN); 1856 1857 /* XXX: R300 family -- program divider differently? */ 1858 1859 /* program reference divider */ 1860 PATCHPLL(sc, RADEON_P2PLL_REF_DIV, sc->sc_refdiv, 1861 ~RADEON_P2PLL_REF_DIV_MASK); 1862 1863 /* program feedback and post dividers */ 1864 data = GETPLL(sc, RADEON_P2PLL_DIV_0); 1865 data &= ~(RADEON_P2PLL_FB0_DIV_MASK | 1866 RADEON_P2PLL_POST0_DIV_MASK); 1867 data |= pbit; 1868 data |= (feed & RADEON_P2PLL_FB0_DIV_MASK); 1869 PUTPLL(sc, RADEON_P2PLL_DIV_0, data); 1870 1871 /* use the atomic update */ 1872 radeonfb_pllwriteupdate(sc, crtc); 1873 1874 /* and wait for it to complete */ 1875 radeonfb_pllwaitatomicread(sc, crtc); 1876 1877 /* program HTOTAL (why?) */ 1878 PUTPLL(sc, RADEON_HTOTAL2_CNTL, 0); 1879 1880 /* drop reset */ 1881 CLRPLL(sc, RADEON_P2PLL_CNTL, 1882 RADEON_P2PLL_RESET | RADEON_P2PLL_SLEEP | 1883 RADEON_P2PLL_ATOMIC_UPDATE_EN | 1884 RADEON_P2PLL_VGA_ATOMIC_UPDATE_EN); 1885 1886 /* allow time for clock to lock */ 1887 delay(50000); 1888 1889 PATCHPLL(sc, RADEON_PIXCLKS_CNTL, 1890 RADEON_PIX2CLK_SRC_SEL_P2PLLCLK, 1891 ~RADEON_PIX2CLK_SRC_SEL_MASK); 1892 } 1893 PRINTREG(RADEON_CRTC_MORE_CNTL); 1894 } 1895 1896 void 1897 radeonfb_modeswitch(struct radeonfb_display *dp) 1898 { 1899 struct radeonfb_softc *sc = dp->rd_softc; 1900 int i; 1901 1902 /* blank the display while we switch modes */ 1903 radeonfb_blank(dp, 1); 1904 1905 #if 0 1906 SET32(sc, RADEON_CRTC_EXT_CNTL, 1907 RADEON_CRTC_VSYNC_DIS | RADEON_CRTC_HSYNC_DIS | 1908 RADEON_CRTC_DISPLAY_DIS /* | RADEON_CRTC_DISP_REQ_EN_B */); 1909 #endif 1910 1911 /* these registers might get in the way... */ 1912 PUT32(sc, RADEON_OVR_CLR, 0); 1913 PUT32(sc, RADEON_OVR_WID_LEFT_RIGHT, 0); 1914 PUT32(sc, RADEON_OVR_WID_TOP_BOTTOM, 0); 1915 PUT32(sc, RADEON_OV0_SCALE_CNTL, 0); 1916 PUT32(sc, RADEON_SUBPIC_CNTL, 0); 1917 PUT32(sc, RADEON_VIPH_CONTROL, 0); 1918 PUT32(sc, RADEON_I2C_CNTL_1, 0); 1919 PUT32(sc, RADEON_GEN_INT_CNTL, 0); 1920 PUT32(sc, RADEON_CAP0_TRIG_CNTL, 0); 1921 PUT32(sc, RADEON_CAP1_TRIG_CNTL, 0); 1922 PUT32(sc, RADEON_SURFACE_CNTL, 0); 1923 1924 for (i = 0; i < dp->rd_ncrtcs; i++) 1925 radeonfb_setcrtc(dp, i); 1926 1927 /* activate the display */ 1928 radeonfb_blank(dp, 0); 1929 } 1930 1931 void 1932 radeonfb_setcrtc(struct radeonfb_display *dp, int index) 1933 { 1934 int crtc; 1935 struct videomode *mode; 1936 struct radeonfb_softc *sc; 1937 struct radeonfb_crtc *cp; 1938 uint32_t v; 1939 uint32_t gencntl; 1940 uint32_t htotaldisp; 1941 uint32_t hsyncstrt; 1942 uint32_t vtotaldisp; 1943 uint32_t vsyncstrt; 1944 uint32_t fphsyncstrt; 1945 uint32_t fpvsyncstrt; 1946 uint32_t fphtotaldisp; 1947 uint32_t fpvtotaldisp; 1948 uint32_t pitch; 1949 1950 sc = dp->rd_softc; 1951 cp = &dp->rd_crtcs[index]; 1952 crtc = cp->rc_number; 1953 mode = &cp->rc_videomode; 1954 1955 #if 1 1956 pitch = (((dp->rd_virtx * dp->rd_bpp) + ((dp->rd_bpp * 8) - 1)) / 1957 (dp->rd_bpp * 8)); 1958 #else 1959 pitch = (((sc->sc_maxx * sc->sc_maxbpp) + ((sc->sc_maxbpp * 8) - 1)) / 1960 (sc->sc_maxbpp * 8)); 1961 #endif 1962 //pitch = pitch | (pitch << 16); 1963 1964 switch (crtc) { 1965 case 0: 1966 gencntl = RADEON_CRTC_GEN_CNTL; 1967 htotaldisp = RADEON_CRTC_H_TOTAL_DISP; 1968 hsyncstrt = RADEON_CRTC_H_SYNC_STRT_WID; 1969 vtotaldisp = RADEON_CRTC_V_TOTAL_DISP; 1970 vsyncstrt = RADEON_CRTC_V_SYNC_STRT_WID; 1971 fpvsyncstrt = RADEON_FP_V_SYNC_STRT_WID; 1972 fphsyncstrt = RADEON_FP_H_SYNC_STRT_WID; 1973 fpvtotaldisp = RADEON_FP_CRTC_V_TOTAL_DISP; 1974 fphtotaldisp = RADEON_FP_CRTC_H_TOTAL_DISP; 1975 break; 1976 case 1: 1977 gencntl = RADEON_CRTC2_GEN_CNTL; 1978 htotaldisp = RADEON_CRTC2_H_TOTAL_DISP; 1979 hsyncstrt = RADEON_CRTC2_H_SYNC_STRT_WID; 1980 vtotaldisp = RADEON_CRTC2_V_TOTAL_DISP; 1981 vsyncstrt = RADEON_CRTC2_V_SYNC_STRT_WID; 1982 fpvsyncstrt = RADEON_FP_V2_SYNC_STRT_WID; 1983 fphsyncstrt = RADEON_FP_H2_SYNC_STRT_WID; 1984 fpvtotaldisp = RADEON_FP_CRTC2_V_TOTAL_DISP; 1985 fphtotaldisp = RADEON_FP_CRTC2_H_TOTAL_DISP; 1986 break; 1987 default: 1988 panic("Bad CRTC!"); 1989 break; 1990 } 1991 1992 /* 1993 * CRTC_GEN_CNTL - depth, accelerator mode, etc. 1994 */ 1995 /* only bother with 32bpp and 8bpp */ 1996 v = dp->rd_format << RADEON_CRTC_PIX_WIDTH_SHIFT; 1997 1998 if (crtc == 1) { 1999 v |= RADEON_CRTC2_CRT2_ON | RADEON_CRTC2_EN; 2000 } else { 2001 v |= RADEON_CRTC_EXT_DISP_EN | RADEON_CRTC_EN; 2002 } 2003 2004 if (mode->flags & VID_DBLSCAN) 2005 v |= RADEON_CRTC2_DBL_SCAN_EN; 2006 2007 if (mode->flags & VID_INTERLACE) 2008 v |= RADEON_CRTC2_INTERLACE_EN; 2009 2010 if (mode->flags & VID_CSYNC) { 2011 v |= RADEON_CRTC2_CSYNC_EN; 2012 if (crtc == 1) 2013 v |= RADEON_CRTC2_VSYNC_TRISTAT; 2014 } 2015 2016 PUT32(sc, gencntl, v); 2017 DPRINTF(("CRTC%s_GEN_CNTL = %08x\n", crtc ? "2" : "", v)); 2018 2019 /* 2020 * CRTC_EXT_CNTL - preserve disable flags, set ATI linear and EXT_CNT 2021 */ 2022 v = GET32(sc, RADEON_CRTC_EXT_CNTL); 2023 if (crtc == 0) { 2024 v &= (RADEON_CRTC_VSYNC_DIS | RADEON_CRTC_HSYNC_DIS | 2025 RADEON_CRTC_DISPLAY_DIS); 2026 v |= RADEON_XCRT_CNT_EN | RADEON_VGA_ATI_LINEAR; 2027 if (mode->flags & VID_CSYNC) 2028 v |= RADEON_CRTC_VSYNC_TRISTAT; 2029 } 2030 /* unconditional turn on CRT, in case first CRTC is DFP */ 2031 v |= RADEON_CRTC_CRT_ON; 2032 PUT32(sc, RADEON_CRTC_EXT_CNTL, v); 2033 PRINTREG(RADEON_CRTC_EXT_CNTL); 2034 2035 /* 2036 * H_TOTAL_DISP 2037 */ 2038 v = ((mode->hdisplay / 8) - 1) << 16; 2039 v |= (mode->htotal / 8) - 1; 2040 PUT32(sc, htotaldisp, v); 2041 DPRINTF(("CRTC%s_H_TOTAL_DISP = %08x\n", crtc ? "2" : "", v)); 2042 PUT32(sc, fphtotaldisp, v); 2043 DPRINTF(("FP_H%s_TOTAL_DISP = %08x\n", crtc ? "2" : "", v)); 2044 2045 /* 2046 * H_SYNC_STRT_WID 2047 */ 2048 v = (((mode->hsync_end - mode->hsync_start) / 8) << 16); 2049 v |= mode->hsync_start; 2050 if (mode->flags & VID_NHSYNC) 2051 v |= RADEON_CRTC_H_SYNC_POL; 2052 PUT32(sc, hsyncstrt, v); 2053 DPRINTF(("CRTC%s_H_SYNC_STRT_WID = %08x\n", crtc ? "2" : "", v)); 2054 PUT32(sc, fphsyncstrt, v); 2055 DPRINTF(("FP_H%s_SYNC_STRT_WID = %08x\n", crtc ? "2" : "", v)); 2056 2057 /* 2058 * V_TOTAL_DISP 2059 */ 2060 v = ((mode->vdisplay - 1) << 16); 2061 v |= (mode->vtotal - 1); 2062 PUT32(sc, vtotaldisp, v); 2063 DPRINTF(("CRTC%s_V_TOTAL_DISP = %08x\n", crtc ? "2" : "", v)); 2064 PUT32(sc, fpvtotaldisp, v); 2065 DPRINTF(("FP_V%s_TOTAL_DISP = %08x\n", crtc ? "2" : "", v)); 2066 2067 /* 2068 * V_SYNC_STRT_WID 2069 */ 2070 v = ((mode->vsync_end - mode->vsync_start) << 16); 2071 v |= (mode->vsync_start - 1); 2072 if (mode->flags & VID_NVSYNC) 2073 v |= RADEON_CRTC_V_SYNC_POL; 2074 PUT32(sc, vsyncstrt, v); 2075 DPRINTF(("CRTC%s_V_SYNC_STRT_WID = %08x\n", crtc ? "2" : "", v)); 2076 PUT32(sc, fpvsyncstrt, v); 2077 DPRINTF(("FP_V%s_SYNC_STRT_WID = %08x\n", crtc ? "2" : "", v)); 2078 2079 radeonfb_program_vclk(sc, mode->dot_clock, crtc); 2080 2081 switch (crtc) { 2082 case 0: 2083 PUT32(sc, RADEON_CRTC_OFFSET, 0); 2084 PUT32(sc, RADEON_CRTC_OFFSET_CNTL, 0); 2085 PUT32(sc, RADEON_CRTC_PITCH, pitch); 2086 CLR32(sc, RADEON_DISP_MERGE_CNTL, RADEON_DISP_RGB_OFFSET_EN); 2087 2088 CLR32(sc, RADEON_CRTC_EXT_CNTL, 2089 RADEON_CRTC_VSYNC_DIS | RADEON_CRTC_HSYNC_DIS | 2090 RADEON_CRTC_DISPLAY_DIS /* | RADEON_CRTC_DISP_REQ_EN_B */); 2091 CLR32(sc, RADEON_CRTC_GEN_CNTL, RADEON_CRTC_DISP_REQ_EN_B); 2092 PRINTREG(RADEON_CRTC_EXT_CNTL); 2093 PRINTREG(RADEON_CRTC_GEN_CNTL); 2094 PRINTREG(RADEON_CLOCK_CNTL_INDEX); 2095 break; 2096 2097 case 1: 2098 PUT32(sc, RADEON_CRTC2_OFFSET, 0); 2099 PUT32(sc, RADEON_CRTC2_OFFSET_CNTL, 0); 2100 PUT32(sc, RADEON_CRTC2_PITCH, pitch); 2101 CLR32(sc, RADEON_DISP2_MERGE_CNTL, RADEON_DISP2_RGB_OFFSET_EN); 2102 CLR32(sc, RADEON_CRTC2_GEN_CNTL, 2103 RADEON_CRTC2_VSYNC_DIS | 2104 RADEON_CRTC2_HSYNC_DIS | 2105 RADEON_CRTC2_DISP_DIS | RADEON_CRTC2_DISP_REQ_EN_B); 2106 PRINTREG(RADEON_CRTC2_GEN_CNTL); 2107 break; 2108 } 2109 } 2110 2111 int 2112 radeonfb_isblank(struct radeonfb_display *dp) 2113 { 2114 uint32_t reg, mask; 2115 2116 if (dp->rd_crtcs[0].rc_number) { 2117 reg = RADEON_CRTC2_GEN_CNTL; 2118 mask = RADEON_CRTC2_DISP_DIS; 2119 } else { 2120 reg = RADEON_CRTC_EXT_CNTL; 2121 mask = RADEON_CRTC_DISPLAY_DIS; 2122 } 2123 return ((GET32(dp->rd_softc, reg) & mask) ? 1 : 0); 2124 } 2125 2126 void 2127 radeonfb_blank(struct radeonfb_display *dp, int blank) 2128 { 2129 struct radeonfb_softc *sc = dp->rd_softc; 2130 uint32_t reg, mask; 2131 uint32_t fpreg, fpval; 2132 int i; 2133 2134 for (i = 0; i < dp->rd_ncrtcs; i++) { 2135 2136 if (dp->rd_crtcs[i].rc_number) { 2137 reg = RADEON_CRTC2_GEN_CNTL; 2138 mask = RADEON_CRTC2_DISP_DIS; 2139 fpreg = RADEON_FP2_GEN_CNTL; 2140 fpval = RADEON_FP2_ON; 2141 } else { 2142 reg = RADEON_CRTC_EXT_CNTL; 2143 mask = RADEON_CRTC_DISPLAY_DIS; 2144 fpreg = RADEON_FP_GEN_CNTL; 2145 fpval = RADEON_FP_FPON; 2146 } 2147 2148 if (blank) { 2149 SET32(sc, reg, mask); 2150 CLR32(sc, fpreg, fpval); 2151 } else { 2152 CLR32(sc, reg, mask); 2153 SET32(sc, fpreg, fpval); 2154 } 2155 } 2156 PRINTREG(RADEON_FP_GEN_CNTL); 2157 PRINTREG(RADEON_FP2_GEN_CNTL); 2158 } 2159 2160 void 2161 radeonfb_init_screen(void *cookie, struct vcons_screen *scr, int existing, 2162 long *defattr) 2163 { 2164 struct radeonfb_display *dp = cookie; 2165 struct rasops_info *ri = &scr->scr_ri; 2166 2167 /* initialize font subsystem */ 2168 wsfont_init(); 2169 2170 DPRINTF(("init screen called, existing %d\n", existing)); 2171 2172 ri->ri_depth = dp->rd_bpp; 2173 ri->ri_width = dp->rd_virtx; 2174 ri->ri_height = dp->rd_virty; 2175 ri->ri_stride = dp->rd_stride; 2176 ri->ri_flg = RI_CENTER; 2177 ri->ri_bits = (void *)dp->rd_fbptr; 2178 2179 /* XXX: 32 bpp only */ 2180 /* this is rgb in "big-endian order..." */ 2181 ri->ri_rnum = 8; 2182 ri->ri_gnum = 8; 2183 ri->ri_bnum = 8; 2184 ri->ri_rpos = 16; 2185 ri->ri_gpos = 8; 2186 ri->ri_bpos = 0; 2187 2188 if (existing) { 2189 ri->ri_flg |= RI_CLEAR; 2190 2191 /* start a modeswitch now */ 2192 radeonfb_modeswitch(dp); 2193 } 2194 2195 /* 2196 * XXX: font selection should be based on properties, with some 2197 * normal/reasonable default. 2198 */ 2199 ri->ri_caps = WSSCREEN_WSCOLORS | WSSCREEN_REVERSE; 2200 2201 /* initialize and look for an initial font */ 2202 rasops_init(ri, dp->rd_virty/8, dp->rd_virtx/8); 2203 2204 rasops_reconfig(ri, dp->rd_virty / ri->ri_font->fontheight, 2205 dp->rd_virtx / ri->ri_font->fontwidth); 2206 2207 /* enable acceleration */ 2208 ri->ri_ops.copyrows = radeonfb_copyrows; 2209 ri->ri_ops.copycols = radeonfb_copycols; 2210 ri->ri_ops.eraserows = radeonfb_eraserows; 2211 ri->ri_ops.erasecols = radeonfb_erasecols; 2212 ri->ri_ops.allocattr = radeonfb_allocattr; 2213 if (!IS_R300(dp->rd_softc)) { 2214 ri->ri_ops.putchar = radeonfb_putchar; 2215 } 2216 ri->ri_ops.cursor = radeonfb_cursor; 2217 } 2218 2219 void 2220 radeonfb_set_fbloc(struct radeonfb_softc *sc) 2221 { 2222 uint32_t gen, ext, gen2 = 0; 2223 uint32_t agploc, aperbase, apersize, mcfbloc; 2224 2225 gen = GET32(sc, RADEON_CRTC_GEN_CNTL); 2226 ext = GET32(sc, RADEON_CRTC_EXT_CNTL); 2227 agploc = GET32(sc, RADEON_MC_AGP_LOCATION); 2228 aperbase = GET32(sc, RADEON_CONFIG_APER_0_BASE); 2229 apersize = GET32(sc, RADEON_CONFIG_APER_SIZE); 2230 2231 PUT32(sc, RADEON_CRTC_GEN_CNTL, gen | RADEON_CRTC_DISP_REQ_EN_B); 2232 PUT32(sc, RADEON_CRTC_EXT_CNTL, ext | RADEON_CRTC_DISPLAY_DIS); 2233 //PUT32(sc, RADEON_CRTC_GEN_CNTL, gen | RADEON_CRTC_DISPLAY_DIS); 2234 //PUT32(sc, RADEON_CRTC_EXT_CNTL, ext | RADEON_CRTC_DISP_REQ_EN_B); 2235 2236 if (HAS_CRTC2(sc)) { 2237 gen2 = GET32(sc, RADEON_CRTC2_GEN_CNTL); 2238 PUT32(sc, RADEON_CRTC2_GEN_CNTL, 2239 gen2 | RADEON_CRTC2_DISP_REQ_EN_B); 2240 } 2241 2242 delay(100000); 2243 2244 mcfbloc = (aperbase >> 16) | 2245 ((aperbase + (apersize - 1)) & 0xffff0000); 2246 2247 sc->sc_aperbase = (mcfbloc & 0xffff) << 16; 2248 sc->sc_memsz = apersize; 2249 2250 if (((agploc & 0xffff) << 16) != 2251 ((mcfbloc & 0xffff0000U) + 0x10000)) { 2252 agploc = mcfbloc & 0xffff0000U; 2253 agploc |= ((agploc + 0x10000) >> 16); 2254 } 2255 2256 PUT32(sc, RADEON_HOST_PATH_CNTL, 0); 2257 2258 PUT32(sc, RADEON_MC_FB_LOCATION, mcfbloc); 2259 PUT32(sc, RADEON_MC_AGP_LOCATION, agploc); 2260 2261 DPRINTF(("aperbase = %u\n", aperbase)); 2262 PRINTREG(RADEON_MC_FB_LOCATION); 2263 PRINTREG(RADEON_MC_AGP_LOCATION); 2264 2265 PUT32(sc, RADEON_DISPLAY_BASE_ADDR, sc->sc_aperbase); 2266 2267 if (HAS_CRTC2(sc)) 2268 PUT32(sc, RADEON_DISPLAY2_BASE_ADDR, sc->sc_aperbase); 2269 2270 PUT32(sc, RADEON_OV0_BASE_ADDR, sc->sc_aperbase); 2271 2272 #if 0 2273 /* XXX: what is this AGP garbage? :-) */ 2274 PUT32(sc, RADEON_AGP_CNTL, 0x00100000); 2275 #endif 2276 2277 delay(100000); 2278 2279 PUT32(sc, RADEON_CRTC_GEN_CNTL, gen); 2280 PUT32(sc, RADEON_CRTC_EXT_CNTL, ext); 2281 2282 if (HAS_CRTC2(sc)) 2283 PUT32(sc, RADEON_CRTC2_GEN_CNTL, gen2); 2284 } 2285 2286 void 2287 radeonfb_init_misc(struct radeonfb_softc *sc) 2288 { 2289 PUT32(sc, RADEON_BUS_CNTL, 2290 RADEON_BUS_MASTER_DIS | 2291 RADEON_BUS_PREFETCH_MODE_ACT | 2292 RADEON_BUS_PCI_READ_RETRY_EN | 2293 RADEON_BUS_PCI_WRT_RETRY_EN | 2294 (3 << RADEON_BUS_RETRY_WS_SHIFT) | 2295 RADEON_BUS_MSTR_RD_MULT | 2296 RADEON_BUS_MSTR_RD_LINE | 2297 RADEON_BUS_RD_DISCARD_EN | 2298 RADEON_BUS_MSTR_DISCONNECT_EN | 2299 RADEON_BUS_READ_BURST); 2300 2301 PUT32(sc, RADEON_BUS_CNTL1, 0xf0); 2302 /* PUT32(sc, RADEON_SEPROM_CNTL1, 0x09ff0000); */ 2303 PUT32(sc, RADEON_FCP_CNTL, RADEON_FCP0_SRC_GND); 2304 PUT32(sc, RADEON_RBBM_CNTL, 2305 (3 << RADEON_RB_SETTLE_SHIFT) | 2306 (4 << RADEON_ABORTCLKS_HI_SHIFT) | 2307 (4 << RADEON_ABORTCLKS_CP_SHIFT) | 2308 (4 << RADEON_ABORTCLKS_CFIFO_SHIFT)); 2309 2310 /* XXX: figure out what these mean! */ 2311 PUT32(sc, RADEON_AGP_CNTL, 0x00100000); 2312 PUT32(sc, RADEON_HOST_PATH_CNTL, 0); 2313 //PUT32(sc, RADEON_DISP_MISC_CNTL, 0x5bb00400); 2314 2315 PUT32(sc, RADEON_GEN_INT_CNTL, 0); 2316 PUT32(sc, RADEON_GEN_INT_STATUS, GET32(sc, RADEON_GEN_INT_STATUS)); 2317 } 2318 2319 /* 2320 * This loads a linear color map for true color. 2321 */ 2322 void 2323 radeonfb_init_palette(struct radeonfb_softc *sc, int crtc) 2324 { 2325 int i; 2326 uint32_t vclk; 2327 2328 #define DAC_WIDTH ((1 << 10) - 1) 2329 #define CLUT_WIDTH ((1 << 8) - 1) 2330 #define CLUT_COLOR(i) ((i * DAC_WIDTH * 2 / CLUT_WIDTH + 1) / 2) 2331 2332 vclk = GETPLL(sc, RADEON_VCLK_ECP_CNTL); 2333 PUTPLL(sc, RADEON_VCLK_ECP_CNTL, vclk & ~RADEON_PIXCLK_DAC_ALWAYS_ONb); 2334 2335 if (crtc) 2336 SET32(sc, RADEON_DAC_CNTL2, RADEON_DAC2_PALETTE_ACC_CTL); 2337 else 2338 CLR32(sc, RADEON_DAC_CNTL2, RADEON_DAC2_PALETTE_ACC_CTL); 2339 2340 PUT32(sc, RADEON_PALETTE_INDEX, 0); 2341 if (sc->sc_displays[crtc].rd_bpp == 0) 2342 sc->sc_displays[crtc].rd_bpp = RADEONFB_DEFAULT_DEPTH; 2343 2344 if (sc->sc_displays[crtc].rd_bpp == 8) { 2345 /* ANSI palette */ 2346 int j = 0; 2347 2348 for (i = 0; i <= CLUT_WIDTH; ++i) { 2349 PUT32(sc, RADEON_PALETTE_30_DATA, 2350 (rasops_cmap[j] << 22) | 2351 (rasops_cmap[j + 1] << 12) | 2352 (rasops_cmap[j + 2] << 2)); 2353 j += 3; 2354 } 2355 } else { 2356 /* linear ramp */ 2357 for (i = 0; i <= CLUT_WIDTH; ++i) { 2358 PUT32(sc, RADEON_PALETTE_30_DATA, 2359 (CLUT_COLOR(i) << 10) | 2360 (CLUT_COLOR(i) << 20) | 2361 (CLUT_COLOR(i))); 2362 } 2363 } 2364 2365 CLR32(sc, RADEON_DAC_CNTL2, RADEON_DAC2_PALETTE_ACC_CTL); 2366 PRINTREG(RADEON_DAC_CNTL2); 2367 2368 PUTPLL(sc, RADEON_VCLK_ECP_CNTL, vclk); 2369 } 2370 2371 /* 2372 * Bugs in some R300 hardware requires this when accessing CLOCK_CNTL_INDEX. 2373 */ 2374 void 2375 radeonfb_r300cg_workaround(struct radeonfb_softc *sc) 2376 { 2377 uint32_t tmp, save; 2378 2379 save = GET32(sc, RADEON_CLOCK_CNTL_INDEX); 2380 tmp = save & ~(0x3f | RADEON_PLL_WR_EN); 2381 PUT32(sc, RADEON_CLOCK_CNTL_INDEX, tmp); 2382 tmp = GET32(sc, RADEON_CLOCK_CNTL_DATA); 2383 PUT32(sc, RADEON_CLOCK_CNTL_INDEX, save); 2384 } 2385 2386 /* 2387 * Acceleration entry points. 2388 */ 2389 static void 2390 radeonfb_putchar(void *cookie, int row, int col, u_int c, long attr) 2391 { 2392 struct rasops_info *ri = cookie; 2393 struct vcons_screen *scr = ri->ri_hw; 2394 struct radeonfb_display *dp = scr->scr_cookie; 2395 struct wsdisplay_font *font = PICK_FONT(ri, c); 2396 uint32_t x, y, w, h; 2397 uint32_t bg, fg, flg; 2398 uint8_t *data; 2399 2400 if (dp->rd_wsmode != WSDISPLAYIO_MODE_EMUL) 2401 return; 2402 2403 if (!CHAR_IN_FONT(c, font)) 2404 return; 2405 2406 w = font->fontwidth; 2407 h = font->fontheight; 2408 2409 flg = attr & 0xff; 2410 if (flg & WSATTR_REVERSE) { 2411 fg = ri->ri_devcmap[(attr >> 16) & 0xf]; 2412 bg = ri->ri_devcmap[(attr >> 24) & 0xf]; 2413 } else { 2414 bg = ri->ri_devcmap[(attr >> 16) & 0xf]; 2415 fg = ri->ri_devcmap[(attr >> 24) & 0xf]; 2416 } 2417 2418 x = ri->ri_xorigin + col * w; 2419 y = ri->ri_yorigin + row * h; 2420 2421 if (c == 0x20) { 2422 radeonfb_rectfill(dp, x, y, w, h, bg); 2423 } else { 2424 data = (uint8_t *)font->data + 2425 (c - font->firstchar) * ri->ri_fontscale; 2426 2427 radeonfb_setup_mono(dp, x, y, w, h, fg, bg); 2428 radeonfb_feed_bytes(dp, ri->ri_fontscale, data); 2429 } 2430 } 2431 2432 static void 2433 radeonfb_eraserows(void *cookie, int row, int nrows, long fillattr) 2434 { 2435 struct rasops_info *ri = cookie; 2436 struct vcons_screen *scr = ri->ri_hw; 2437 struct radeonfb_display *dp = scr->scr_cookie; 2438 uint32_t x, y, w, h, fg, bg, ul; 2439 2440 /* XXX: check for full emulation mode? */ 2441 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 2442 x = ri->ri_xorigin; 2443 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 2444 w = ri->ri_emuwidth; 2445 h = ri->ri_font->fontheight * nrows; 2446 2447 rasops_unpack_attr(fillattr, &fg, &bg, &ul); 2448 radeonfb_rectfill(dp, x, y, w, h, ri->ri_devcmap[bg & 0xf]); 2449 } 2450 } 2451 2452 static void 2453 radeonfb_copyrows(void *cookie, int srcrow, int dstrow, int nrows) 2454 { 2455 struct rasops_info *ri = cookie; 2456 struct vcons_screen *scr = ri->ri_hw; 2457 struct radeonfb_display *dp = scr->scr_cookie; 2458 uint32_t x, ys, yd, w, h; 2459 2460 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 2461 x = ri->ri_xorigin; 2462 ys = ri->ri_yorigin + ri->ri_font->fontheight * srcrow; 2463 yd = ri->ri_yorigin + ri->ri_font->fontheight * dstrow; 2464 w = ri->ri_emuwidth; 2465 h = ri->ri_font->fontheight * nrows; 2466 radeonfb_bitblt(dp, x, ys, x, yd, w, h, 2467 RADEON_ROP3_S, 0xffffffff); 2468 } 2469 } 2470 2471 static void 2472 radeonfb_copycols(void *cookie, int row, int srccol, int dstcol, int ncols) 2473 { 2474 struct rasops_info *ri = cookie; 2475 struct vcons_screen *scr = ri->ri_hw; 2476 struct radeonfb_display *dp = scr->scr_cookie; 2477 uint32_t xs, xd, y, w, h; 2478 2479 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 2480 xs = ri->ri_xorigin + ri->ri_font->fontwidth * srccol; 2481 xd = ri->ri_xorigin + ri->ri_font->fontwidth * dstcol; 2482 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 2483 w = ri->ri_font->fontwidth * ncols; 2484 h = ri->ri_font->fontheight; 2485 radeonfb_bitblt(dp, xs, y, xd, y, w, h, 2486 RADEON_ROP3_S, 0xffffffff); 2487 } 2488 } 2489 2490 static void 2491 radeonfb_erasecols(void *cookie, int row, int startcol, int ncols, 2492 long fillattr) 2493 { 2494 struct rasops_info *ri = cookie; 2495 struct vcons_screen *scr = ri->ri_hw; 2496 struct radeonfb_display *dp = scr->scr_cookie; 2497 uint32_t x, y, w, h, fg, bg, ul; 2498 2499 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 2500 x = ri->ri_xorigin + ri->ri_font->fontwidth * startcol; 2501 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 2502 w = ri->ri_font->fontwidth * ncols; 2503 h = ri->ri_font->fontheight; 2504 2505 rasops_unpack_attr(fillattr, &fg, &bg, &ul); 2506 radeonfb_rectfill(dp, x, y, w, h, ri->ri_devcmap[bg & 0xf]); 2507 } 2508 } 2509 2510 static void 2511 radeonfb_cursor(void *cookie, int on, int row, int col) 2512 { 2513 struct rasops_info *ri = cookie; 2514 struct vcons_screen *scr = ri->ri_hw; 2515 struct radeonfb_display *dp = scr->scr_cookie; 2516 int x, y, wi, he; 2517 2518 wi = ri->ri_font->fontwidth; 2519 he = ri->ri_font->fontheight; 2520 2521 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 2522 x = ri->ri_ccol * wi + ri->ri_xorigin; 2523 y = ri->ri_crow * he + ri->ri_yorigin; 2524 /* first turn off the old cursor */ 2525 if (ri->ri_flg & RI_CURSOR) { 2526 radeonfb_bitblt(dp, x, y, x, y, wi, he, 2527 RADEON_ROP3_Dn, 0xffffffff); 2528 ri->ri_flg &= ~RI_CURSOR; 2529 } 2530 ri->ri_crow = row; 2531 ri->ri_ccol = col; 2532 /* then (possibly) turn on the new one */ 2533 if (on) { 2534 x = ri->ri_ccol * wi + ri->ri_xorigin; 2535 y = ri->ri_crow * he + ri->ri_yorigin; 2536 radeonfb_bitblt(dp, x, y, x, y, wi, he, 2537 RADEON_ROP3_Dn, 0xffffffff); 2538 ri->ri_flg |= RI_CURSOR; 2539 } 2540 } else { 2541 scr->scr_ri.ri_crow = row; 2542 scr->scr_ri.ri_ccol = col; 2543 scr->scr_ri.ri_flg &= ~RI_CURSOR; 2544 } 2545 } 2546 2547 static int 2548 radeonfb_allocattr(void *cookie, int fg, int bg, int flags, long *attrp) 2549 { 2550 if ((fg == 0) && (bg == 0)) { 2551 fg = WS_DEFAULT_FG; 2552 bg = WS_DEFAULT_BG; 2553 } 2554 *attrp = ((fg & 0xf) << 24) | ((bg & 0xf) << 16) | (flags & 0xff) << 8; 2555 return 0; 2556 } 2557 2558 /* 2559 * Underlying acceleration support. 2560 */ 2561 static void 2562 radeonfb_setup_mono(struct radeonfb_display *dp, int xd, int yd, int width, 2563 int height, uint32_t fg, uint32_t bg) 2564 { 2565 struct radeonfb_softc *sc = dp->rd_softc; 2566 uint32_t gmc; 2567 uint32_t padded_width = (width+7) & 0xfff8; 2568 uint32_t topleft, bottomright; 2569 2570 gmc = dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT; 2571 2572 if (width != padded_width) { 2573 2574 radeonfb_wait_fifo(sc, 2); 2575 topleft = ((yd << 16) & 0x1fff0000) | (xd & 0x1fff); 2576 bottomright = (((yd + height) << 16) & 0x1fff0000) | 2577 ((xd + width) & 0x1fff); 2578 PUT32(sc, RADEON_SC_TOP_LEFT, topleft); 2579 PUT32(sc, RADEON_SC_BOTTOM_RIGHT, bottomright); 2580 } 2581 2582 radeonfb_wait_fifo(sc, 5); 2583 2584 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 2585 RADEON_GMC_BRUSH_NONE | 2586 RADEON_GMC_SRC_DATATYPE_MONO_FG_BG | 2587 //RADEON_GMC_BYTE_LSB_TO_MSB | 2588 RADEON_GMC_DST_CLIPPING | 2589 RADEON_ROP3_S | 2590 RADEON_DP_SRC_SOURCE_HOST_DATA | 2591 RADEON_GMC_CLR_CMP_CNTL_DIS | 2592 RADEON_GMC_WR_MSK_DIS | 2593 gmc); 2594 2595 PUT32(sc, RADEON_DP_SRC_FRGD_CLR, fg); 2596 PUT32(sc, RADEON_DP_SRC_BKGD_CLR, bg); 2597 2598 PUT32(sc, RADEON_DST_X_Y, (xd << 16) | yd); 2599 PUT32(sc, RADEON_DST_WIDTH_HEIGHT, (padded_width << 16) | height); 2600 2601 } 2602 2603 static void 2604 radeonfb_feed_bytes(struct radeonfb_display *dp, int count, uint8_t *data) 2605 { 2606 struct radeonfb_softc *sc = dp->rd_softc; 2607 int i; 2608 uint32_t latch = 0; 2609 int shift = 0; 2610 2611 for (i = 0; i < count; i++) { 2612 latch |= (data[i] << shift); 2613 if (shift == 24) { 2614 radeonfb_wait_fifo(sc, 1); 2615 PUT32(sc, RADEON_HOST_DATA0, latch); 2616 latch = 0; 2617 shift = 0; 2618 } else 2619 shift += 8; 2620 } 2621 if (shift != 0) { 2622 radeonfb_wait_fifo(sc, 1); 2623 PUT32(sc, RADEON_HOST_DATA0, latch); 2624 } 2625 radeonfb_unclip(sc); 2626 } 2627 2628 static void 2629 radeonfb_rectfill(struct radeonfb_display *dp, int dstx, int dsty, 2630 int width, int height, uint32_t color) 2631 { 2632 struct radeonfb_softc *sc = dp->rd_softc; 2633 uint32_t gmc; 2634 2635 gmc = dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT; 2636 2637 radeonfb_wait_fifo(sc, 6); 2638 2639 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 2640 RADEON_GMC_BRUSH_SOLID_COLOR | 2641 RADEON_GMC_SRC_DATATYPE_COLOR | 2642 RADEON_GMC_CLR_CMP_CNTL_DIS | 2643 RADEON_ROP3_P | gmc); 2644 2645 PUT32(sc, RADEON_DP_BRUSH_FRGD_CLR, color); 2646 PUT32(sc, RADEON_DP_WRITE_MASK, 0xffffffff); 2647 PUT32(sc, RADEON_DP_CNTL, 2648 RADEON_DST_X_LEFT_TO_RIGHT | 2649 RADEON_DST_Y_TOP_TO_BOTTOM); 2650 PUT32(sc, RADEON_DST_Y_X, (dsty << 16) | dstx); 2651 PUT32(sc, RADEON_DST_WIDTH_HEIGHT, (width << 16) | (height)); 2652 2653 /* 2654 * XXX: we don't wait for the fifo to empty -- that would slow 2655 * things down! The linux radeonfb driver waits, but xfree doesn't 2656 */ 2657 /* XXX: for now we do, to make it safe for direct drawing */ 2658 radeonfb_engine_idle(sc); 2659 } 2660 2661 static void 2662 radeonfb_bitblt(struct radeonfb_display *dp, int srcx, int srcy, 2663 int dstx, int dsty, int width, int height, int rop, uint32_t mask) 2664 { 2665 struct radeonfb_softc *sc = dp->rd_softc; 2666 uint32_t gmc; 2667 uint32_t dir; 2668 2669 if (dsty < srcy) { 2670 dir = RADEON_DST_Y_TOP_TO_BOTTOM; 2671 } else { 2672 srcy += height - 1; 2673 dsty += height - 1; 2674 dir = 0; 2675 } 2676 if (dstx < srcx) { 2677 dir |= RADEON_DST_X_LEFT_TO_RIGHT; 2678 } else { 2679 srcx += width - 1; 2680 dstx += width - 1; 2681 } 2682 2683 gmc = dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT; 2684 2685 radeonfb_wait_fifo(sc, 6); 2686 2687 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 2688 //RADEON_GMC_SRC_CLIPPING | 2689 RADEON_GMC_BRUSH_SOLID_COLOR | 2690 RADEON_GMC_SRC_DATATYPE_COLOR | 2691 RADEON_GMC_CLR_CMP_CNTL_DIS | 2692 RADEON_DP_SRC_SOURCE_MEMORY | 2693 rop | gmc); 2694 2695 PUT32(sc, RADEON_DP_WRITE_MASK, mask); 2696 PUT32(sc, RADEON_DP_CNTL, dir); 2697 PUT32(sc, RADEON_SRC_Y_X, (srcy << 16) | srcx); 2698 PUT32(sc, RADEON_DST_Y_X, (dsty << 16) | dstx); 2699 PUT32(sc, RADEON_DST_WIDTH_HEIGHT, (width << 16) | (height)); 2700 2701 /* 2702 * XXX: we don't wait for the fifo to empty -- that would slow 2703 * things down! The linux radeonfb driver waits, but xfree doesn't 2704 */ 2705 /* XXX: for now we do, to make it safe for direct drawing */ 2706 radeonfb_engine_idle(sc); 2707 } 2708 2709 static void 2710 radeonfb_engine_idle(struct radeonfb_softc *sc) 2711 { 2712 int i; 2713 2714 radeonfb_wait_fifo(sc, 64); 2715 for (i = RADEON_TIMEOUT; i; i--) { 2716 if ((GET32(sc, RADEON_RBBM_STATUS) & 2717 RADEON_RBBM_ACTIVE) == 0) { 2718 radeonfb_engine_flush(sc); 2719 break; 2720 } 2721 } 2722 } 2723 2724 static void 2725 radeonfb_wait_fifo(struct radeonfb_softc *sc, int n) 2726 { 2727 int i; 2728 2729 for (i = RADEON_TIMEOUT; i; i--) { 2730 if ((GET32(sc, RADEON_RBBM_STATUS) & 2731 RADEON_RBBM_FIFOCNT_MASK) >= n) 2732 return; 2733 } 2734 #ifdef DIAGNOSTIC 2735 if (!i) 2736 printf("%s: timed out waiting for fifo (%x)\n", 2737 XNAME(sc), GET32(sc, RADEON_RBBM_STATUS)); 2738 #endif 2739 } 2740 2741 static void 2742 radeonfb_engine_flush(struct radeonfb_softc *sc) 2743 { 2744 int i; 2745 SET32(sc, RADEON_RB2D_DSTCACHE_CTLSTAT, RADEON_RB2D_DC_FLUSH_ALL); 2746 for (i = RADEON_TIMEOUT; i; i--) { 2747 if ((GET32(sc, RADEON_RB2D_DSTCACHE_CTLSTAT) & 2748 RADEON_RB2D_DC_BUSY) == 0) 2749 break; 2750 } 2751 #ifdef DIAGNOSTIC 2752 if (!i) 2753 printf("%s: engine flush timed out!\n", XNAME(sc)); 2754 #endif 2755 } 2756 2757 static inline void 2758 radeonfb_unclip(struct radeonfb_softc *sc) 2759 { 2760 2761 radeonfb_wait_fifo(sc, 2); 2762 PUT32(sc, RADEON_SC_TOP_LEFT, 0); 2763 PUT32(sc, RADEON_SC_BOTTOM_RIGHT, 0x1fff1fff); 2764 } 2765 2766 static void 2767 radeonfb_engine_init(struct radeonfb_display *dp) 2768 { 2769 struct radeonfb_softc *sc = dp->rd_softc; 2770 uint32_t pitch; 2771 volatile uint32_t junk; 2772 2773 /* no 3D */ 2774 PUT32(sc, RADEON_RB3D_CNTL, 0); 2775 2776 radeonfb_engine_reset(sc); 2777 pitch = ((dp->rd_virtx * (dp->rd_bpp / 8) + 0x3f)) >> 6; 2778 //pitch = ((sc->sc_maxx * (sc->sc_maxbpp / 8) + 0x3f)) >> 6; 2779 2780 radeonfb_wait_fifo(sc, 1); 2781 if (!IS_R300(sc)) 2782 PUT32(sc, RADEON_RB2D_DSTCACHE_MODE, 0); 2783 2784 radeonfb_wait_fifo(sc, 3); 2785 PUT32(sc, RADEON_DEFAULT_PITCH_OFFSET, 2786 (pitch << 22) | (sc->sc_aperbase >> 10)); 2787 2788 2789 PUT32(sc, RADEON_DST_PITCH_OFFSET, 2790 (pitch << 22) | (sc->sc_aperbase >> 10)); 2791 PUT32(sc, RADEON_SRC_PITCH_OFFSET, 2792 (pitch << 22) | (sc->sc_aperbase >> 10)); 2793 2794 radeonfb_wait_fifo(sc, 1); 2795 #if _BYTE_ORDER == _BIG_ENDIAN 2796 SET32(sc, RADEON_DP_DATATYPE, RADEON_HOST_BIG_ENDIAN_EN); 2797 #else 2798 CLR32(sc, RADEON_DP_DATATYPE, RADEON_HOST_BIG_ENDIAN_EN); 2799 #endif 2800 junk = GET32(sc, RADEON_DP_DATATYPE); 2801 2802 /* default scissors -- no clipping */ 2803 radeonfb_wait_fifo(sc, 1); 2804 PUT32(sc, RADEON_DEFAULT_SC_BOTTOM_RIGHT, 2805 RADEON_DEFAULT_SC_RIGHT_MAX | RADEON_DEFAULT_SC_BOTTOM_MAX); 2806 2807 radeonfb_wait_fifo(sc, 1); 2808 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 2809 (dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT) | 2810 RADEON_GMC_CLR_CMP_CNTL_DIS | 2811 RADEON_GMC_BRUSH_SOLID_COLOR | 2812 RADEON_GMC_SRC_DATATYPE_COLOR); 2813 2814 radeonfb_wait_fifo(sc, 7); 2815 PUT32(sc, RADEON_DST_LINE_START, 0); 2816 PUT32(sc, RADEON_DST_LINE_END, 0); 2817 PUT32(sc, RADEON_DP_BRUSH_FRGD_CLR, 0xffffffff); 2818 PUT32(sc, RADEON_DP_BRUSH_BKGD_CLR, 0); 2819 PUT32(sc, RADEON_DP_SRC_FRGD_CLR, 0xffffffff); 2820 PUT32(sc, RADEON_DP_SRC_BKGD_CLR, 0); 2821 PUT32(sc, RADEON_DP_WRITE_MASK, 0xffffffff); 2822 2823 radeonfb_engine_idle(sc); 2824 } 2825 2826 static void 2827 radeonfb_engine_reset(struct radeonfb_softc *sc) 2828 { 2829 uint32_t hpc, rbbm, mclkcntl, clkindex; 2830 2831 radeonfb_engine_flush(sc); 2832 2833 clkindex = GET32(sc, RADEON_CLOCK_CNTL_INDEX); 2834 if (HAS_R300CG(sc)) 2835 radeonfb_r300cg_workaround(sc); 2836 mclkcntl = GETPLL(sc, RADEON_MCLK_CNTL); 2837 2838 /* 2839 * According to comments in XFree code, resetting the HDP via 2840 * the RBBM_SOFT_RESET can cause bad behavior on some systems. 2841 * So we use HOST_PATH_CNTL instead. 2842 */ 2843 2844 hpc = GET32(sc, RADEON_HOST_PATH_CNTL); 2845 rbbm = GET32(sc, RADEON_RBBM_SOFT_RESET); 2846 if (IS_R300(sc)) { 2847 PUT32(sc, RADEON_RBBM_SOFT_RESET, rbbm | 2848 RADEON_SOFT_RESET_CP | 2849 RADEON_SOFT_RESET_HI | 2850 RADEON_SOFT_RESET_E2); 2851 GET32(sc, RADEON_RBBM_SOFT_RESET); 2852 PUT32(sc, RADEON_RBBM_SOFT_RESET, 0); 2853 /* 2854 * XXX: this bit is not defined in any ATI docs I have, 2855 * nor in the XFree code, but XFree does it. Why? 2856 */ 2857 SET32(sc, RADEON_RB2D_DSTCACHE_MODE, (1<<17)); 2858 } else { 2859 PUT32(sc, RADEON_RBBM_SOFT_RESET, rbbm | 2860 RADEON_SOFT_RESET_CP | 2861 RADEON_SOFT_RESET_SE | 2862 RADEON_SOFT_RESET_RE | 2863 RADEON_SOFT_RESET_PP | 2864 RADEON_SOFT_RESET_E2 | 2865 RADEON_SOFT_RESET_RB); 2866 GET32(sc, RADEON_RBBM_SOFT_RESET); 2867 PUT32(sc, RADEON_RBBM_SOFT_RESET, rbbm & 2868 ~(RADEON_SOFT_RESET_CP | 2869 RADEON_SOFT_RESET_SE | 2870 RADEON_SOFT_RESET_RE | 2871 RADEON_SOFT_RESET_PP | 2872 RADEON_SOFT_RESET_E2 | 2873 RADEON_SOFT_RESET_RB)); 2874 GET32(sc, RADEON_RBBM_SOFT_RESET); 2875 } 2876 2877 PUT32(sc, RADEON_HOST_PATH_CNTL, hpc | RADEON_HDP_SOFT_RESET); 2878 GET32(sc, RADEON_HOST_PATH_CNTL); 2879 PUT32(sc, RADEON_HOST_PATH_CNTL, hpc); 2880 2881 if (IS_R300(sc)) 2882 PUT32(sc, RADEON_RBBM_SOFT_RESET, rbbm); 2883 2884 PUT32(sc, RADEON_CLOCK_CNTL_INDEX, clkindex); 2885 PUTPLL(sc, RADEON_MCLK_CNTL, mclkcntl); 2886 2887 if (HAS_R300CG(sc)) 2888 radeonfb_r300cg_workaround(sc); 2889 } 2890 2891 static int 2892 radeonfb_set_curpos(struct radeonfb_display *dp, struct wsdisplay_curpos *pos) 2893 { 2894 int x, y; 2895 2896 x = pos->x; 2897 y = pos->y; 2898 2899 /* 2900 * This doesn't let a cursor move off the screen. I'm not 2901 * sure if this will have negative effects for e.g. Xinerama. 2902 * I'd guess Xinerama handles it by changing the cursor shape, 2903 * but that needs verification. 2904 */ 2905 if (x >= dp->rd_virtx) 2906 x = dp->rd_virtx - 1; 2907 if (x < 0) 2908 x = 0; 2909 if (y >= dp->rd_virty) 2910 y = dp->rd_virty - 1; 2911 if (y < 0) 2912 y = 0; 2913 2914 dp->rd_cursor.rc_pos.x = x; 2915 dp->rd_cursor.rc_pos.y = y; 2916 2917 radeonfb_cursor_position(dp); 2918 return 0; 2919 } 2920 2921 static int 2922 radeonfb_set_cursor(struct radeonfb_display *dp, struct wsdisplay_cursor *wc) 2923 { 2924 unsigned flags; 2925 2926 uint8_t r[2], g[2], b[2]; 2927 unsigned index, count; 2928 int i, err; 2929 int pitch, size; 2930 struct radeonfb_cursor nc; 2931 2932 flags = wc->which; 2933 2934 /* copy old values */ 2935 nc = dp->rd_cursor; 2936 2937 if (flags & WSDISPLAY_CURSOR_DOCMAP) { 2938 index = wc->cmap.index; 2939 count = wc->cmap.count; 2940 2941 if (index >= 2 || (index + count) > 2) 2942 return EINVAL; 2943 2944 err = copyin(wc->cmap.red, &r[index], count); 2945 if (err) 2946 return err; 2947 err = copyin(wc->cmap.green, &g[index], count); 2948 if (err) 2949 return err; 2950 err = copyin(wc->cmap.blue, &b[index], count); 2951 if (err) 2952 return err; 2953 2954 for (i = index; i < index + count; i++) { 2955 nc.rc_cmap[i] = 2956 (r[i] << 16) + (g[i] << 8) + (b[i] << 0); 2957 } 2958 } 2959 2960 if (flags & WSDISPLAY_CURSOR_DOSHAPE) { 2961 if ((wc->size.x > RADEON_CURSORMAXX) || 2962 (wc->size.y > RADEON_CURSORMAXY)) 2963 return EINVAL; 2964 2965 /* figure bytes per line */ 2966 pitch = (wc->size.x + 7) / 8; 2967 size = pitch * wc->size.y; 2968 2969 /* clear the old cursor and mask */ 2970 memset(nc.rc_image, 0, 512); 2971 memset(nc.rc_mask, 0, 512); 2972 2973 nc.rc_size = wc->size; 2974 2975 if ((err = copyin(wc->image, nc.rc_image, size)) != 0) 2976 return err; 2977 2978 if ((err = copyin(wc->mask, nc.rc_mask, size)) != 0) 2979 return err; 2980 } 2981 2982 if (flags & WSDISPLAY_CURSOR_DOHOT) { 2983 nc.rc_hot = wc->hot; 2984 if (nc.rc_hot.x >= nc.rc_size.x) 2985 nc.rc_hot.x = nc.rc_size.x - 1; 2986 if (nc.rc_hot.y >= nc.rc_size.y) 2987 nc.rc_hot.y = nc.rc_size.y - 1; 2988 } 2989 2990 if (flags & WSDISPLAY_CURSOR_DOPOS) { 2991 nc.rc_pos = wc->pos; 2992 if (nc.rc_pos.x >= dp->rd_virtx) 2993 nc.rc_pos.x = dp->rd_virtx - 1; 2994 #if 0 2995 if (nc.rc_pos.x < 0) 2996 nc.rc_pos.x = 0; 2997 #endif 2998 if (nc.rc_pos.y >= dp->rd_virty) 2999 nc.rc_pos.y = dp->rd_virty - 1; 3000 #if 0 3001 if (nc.rc_pos.y < 0) 3002 nc.rc_pos.y = 0; 3003 #endif 3004 } 3005 if (flags & WSDISPLAY_CURSOR_DOCUR) { 3006 nc.rc_visible = wc->enable; 3007 } 3008 3009 dp->rd_cursor = nc; 3010 radeonfb_cursor_update(dp, wc->which); 3011 3012 return 0; 3013 } 3014 3015 /* 3016 * Change the cursor shape. Call this with the cursor locked to avoid 3017 * flickering/tearing. 3018 */ 3019 static void 3020 radeonfb_cursor_shape(struct radeonfb_display *dp) 3021 { 3022 uint8_t and[512], xor[512]; 3023 int i, j, src, dst, pitch; 3024 const uint8_t *msk = dp->rd_cursor.rc_mask; 3025 const uint8_t *img = dp->rd_cursor.rc_image; 3026 3027 /* 3028 * Radeon cursor data interleaves one line of AND data followed 3029 * by a line of XOR data. (Each line corresponds to a whole hardware 3030 * pitch - i.e. 64 pixels or 8 bytes.) 3031 * 3032 * The cursor is displayed using the following table: 3033 * 3034 * AND XOR Result 3035 * ---------------------- 3036 * 0 0 Cursor color 0 3037 * 0 1 Cursor color 1 3038 * 1 0 Transparent 3039 * 1 1 Complement of background 3040 * 3041 * Our masks are therefore different from what we were passed. 3042 * Passed in, I'm assuming the data represents either color 0 or 1, 3043 * and a mask, so the passed in table looks like: 3044 * 3045 * IMG Mask Result 3046 * ----------------------- 3047 * 0 0 Transparent 3048 * 0 1 Cursor color 0 3049 * 1 0 Transparent 3050 * 1 1 Cursor color 1 3051 * 3052 * IF mask bit == 1, AND = 0, XOR = color. 3053 * IF mask bit == 0, AND = 1, XOR = 0. 3054 * 3055 * hence: AND = ~(mask); XOR = color & ~(mask); 3056 */ 3057 3058 pitch = ((dp->rd_cursor.rc_size.x + 7) / 8); 3059 3060 /* start by assuming all bits are transparent */ 3061 memset(and, 0xff, 512); 3062 memset(xor, 0x00, 512); 3063 3064 src = 0; 3065 dst = 0; 3066 for (i = 0; i < 64; i++) { 3067 for (j = 0; j < 64; j += 8) { 3068 if ((i < dp->rd_cursor.rc_size.y) && 3069 (j < dp->rd_cursor.rc_size.x)) { 3070 3071 /* take care to leave odd bits alone */ 3072 and[dst] &= ~(msk[src]); 3073 xor[dst] = img[src] & msk[src]; 3074 src++; 3075 } 3076 dst++; 3077 } 3078 } 3079 3080 /* copy the image into place */ 3081 for (i = 0; i < 64; i++) { 3082 memcpy((uint8_t *)dp->rd_curptr + (i * 16), 3083 &and[i * 8], 8); 3084 memcpy((uint8_t *)dp->rd_curptr + (i * 16) + 8, 3085 &xor[i * 8], 8); 3086 } 3087 } 3088 3089 static void 3090 radeonfb_cursor_position(struct radeonfb_display *dp) 3091 { 3092 struct radeonfb_softc *sc = dp->rd_softc; 3093 uint32_t offset, hvoff, hvpos; /* registers */ 3094 uint32_t coff; /* cursor offset */ 3095 int i, x, y, xoff, yoff, crtcoff; 3096 3097 /* 3098 * XXX: this also needs to handle pan/scan 3099 */ 3100 for (i = 0; i < dp->rd_ncrtcs; i++) { 3101 3102 struct radeonfb_crtc *rcp = &dp->rd_crtcs[i]; 3103 3104 if (rcp->rc_number) { 3105 offset = RADEON_CUR2_OFFSET; 3106 hvoff = RADEON_CUR2_HORZ_VERT_OFF; 3107 hvpos = RADEON_CUR2_HORZ_VERT_POSN; 3108 crtcoff = RADEON_CRTC2_OFFSET; 3109 } else { 3110 offset = RADEON_CUR_OFFSET; 3111 hvoff = RADEON_CUR_HORZ_VERT_OFF; 3112 hvpos = RADEON_CUR_HORZ_VERT_POSN; 3113 crtcoff = RADEON_CRTC_OFFSET; 3114 } 3115 3116 x = dp->rd_cursor.rc_pos.x; 3117 y = dp->rd_cursor.rc_pos.y; 3118 3119 while (y < rcp->rc_yoffset) { 3120 rcp->rc_yoffset -= RADEON_PANINCREMENT; 3121 } 3122 while (y >= (rcp->rc_yoffset + rcp->rc_videomode.vdisplay)) { 3123 rcp->rc_yoffset += RADEON_PANINCREMENT; 3124 } 3125 while (x < rcp->rc_xoffset) { 3126 rcp->rc_xoffset -= RADEON_PANINCREMENT; 3127 } 3128 while (x >= (rcp->rc_xoffset + rcp->rc_videomode.hdisplay)) { 3129 rcp->rc_xoffset += RADEON_PANINCREMENT; 3130 } 3131 3132 /* adjust for the cursor's hotspot */ 3133 x -= dp->rd_cursor.rc_hot.x; 3134 y -= dp->rd_cursor.rc_hot.y; 3135 xoff = yoff = 0; 3136 3137 if (x >= dp->rd_virtx) 3138 x = dp->rd_virtx - 1; 3139 if (y >= dp->rd_virty) 3140 y = dp->rd_virty - 1; 3141 3142 /* now adjust cursor so it is relative to viewport */ 3143 x -= rcp->rc_xoffset; 3144 y -= rcp->rc_yoffset; 3145 3146 /* 3147 * no need to check for fall off, because we should 3148 * never move off the screen entirely! 3149 */ 3150 coff = 0; 3151 if (x < 0) { 3152 xoff = -x; 3153 x = 0; 3154 } 3155 if (y < 0) { 3156 yoff = -y; 3157 y = 0; 3158 coff = (yoff * 2) * 8; 3159 } 3160 3161 /* pan the display */ 3162 PUT32(sc, crtcoff, (rcp->rc_yoffset * dp->rd_stride) + 3163 rcp->rc_xoffset); 3164 3165 PUT32(sc, offset, (dp->rd_curoff + coff) | RADEON_CUR_LOCK); 3166 PUT32(sc, hvoff, (xoff << 16) | (yoff) | RADEON_CUR_LOCK); 3167 /* NB: this unlocks the cursor */ 3168 PUT32(sc, hvpos, (x << 16) | y); 3169 } 3170 } 3171 3172 static void 3173 radeonfb_cursor_visible(struct radeonfb_display *dp) 3174 { 3175 int i; 3176 uint32_t gencntl, bit; 3177 3178 for (i = 0; i < dp->rd_ncrtcs; i++) { 3179 if (dp->rd_crtcs[i].rc_number) { 3180 gencntl = RADEON_CRTC2_GEN_CNTL; 3181 bit = RADEON_CRTC2_CUR_EN; 3182 } else { 3183 gencntl = RADEON_CRTC_GEN_CNTL; 3184 bit = RADEON_CRTC_CUR_EN; 3185 } 3186 3187 if (dp->rd_cursor.rc_visible) 3188 SET32(dp->rd_softc, gencntl, bit); 3189 else 3190 CLR32(dp->rd_softc, gencntl, bit); 3191 } 3192 } 3193 3194 static void 3195 radeonfb_cursor_cmap(struct radeonfb_display *dp) 3196 { 3197 int i; 3198 uint32_t c0reg, c1reg; 3199 struct radeonfb_softc *sc = dp->rd_softc; 3200 3201 for (i = 0; i < dp->rd_ncrtcs; i++) { 3202 if (dp->rd_crtcs[i].rc_number) { 3203 c0reg = RADEON_CUR2_CLR0; 3204 c1reg = RADEON_CUR2_CLR1; 3205 } else { 3206 c0reg = RADEON_CUR_CLR0; 3207 c1reg = RADEON_CUR_CLR1; 3208 } 3209 3210 PUT32(sc, c0reg, dp->rd_cursor.rc_cmap[0]); 3211 PUT32(sc, c1reg, dp->rd_cursor.rc_cmap[1]); 3212 } 3213 } 3214 3215 static void 3216 radeonfb_cursor_update(struct radeonfb_display *dp, unsigned which) 3217 { 3218 struct radeonfb_softc *sc; 3219 int i; 3220 3221 sc = dp->rd_softc; 3222 for (i = 0; i < dp->rd_ncrtcs; i++) { 3223 if (dp->rd_crtcs[i].rc_number) { 3224 SET32(sc, RADEON_CUR2_OFFSET, RADEON_CUR_LOCK); 3225 } else { 3226 SET32(sc, RADEON_CUR_OFFSET,RADEON_CUR_LOCK); 3227 } 3228 } 3229 3230 if (which & WSDISPLAY_CURSOR_DOCMAP) 3231 radeonfb_cursor_cmap(dp); 3232 3233 if (which & WSDISPLAY_CURSOR_DOSHAPE) 3234 radeonfb_cursor_shape(dp); 3235 3236 if (which & WSDISPLAY_CURSOR_DOCUR) 3237 radeonfb_cursor_visible(dp); 3238 3239 /* this one is unconditional, because it updates other stuff */ 3240 radeonfb_cursor_position(dp); 3241 } 3242 3243 static struct videomode * 3244 radeonfb_best_refresh(struct videomode *m1, struct videomode *m2) 3245 { 3246 int r1, r2; 3247 3248 /* otherwise pick the higher refresh rate */ 3249 r1 = DIVIDE(DIVIDE(m1->dot_clock, m1->htotal), m1->vtotal); 3250 r2 = DIVIDE(DIVIDE(m2->dot_clock, m2->htotal), m2->vtotal); 3251 3252 return (r1 < r2 ? m2 : m1); 3253 } 3254 3255 static const struct videomode * 3256 radeonfb_port_mode(struct radeonfb_softc *sc, struct radeonfb_port *rp, 3257 int x, int y) 3258 { 3259 struct edid_info *ep = &rp->rp_edid; 3260 struct videomode *vmp = NULL; 3261 int i; 3262 3263 if (!rp->rp_edid_valid) { 3264 /* fallback to safe mode */ 3265 return radeonfb_modelookup(sc->sc_defaultmode); 3266 } 3267 3268 /* always choose the preferred mode first! */ 3269 if (ep->edid_preferred_mode) { 3270 3271 /* XXX: add auto-stretching support for native mode */ 3272 3273 /* this may want panning to occur, btw */ 3274 if ((ep->edid_preferred_mode->hdisplay <= x) && 3275 (ep->edid_preferred_mode->vdisplay <= y)) 3276 return ep->edid_preferred_mode; 3277 } 3278 3279 for (i = 0; i < ep->edid_nmodes; i++) { 3280 /* 3281 * We elect to pick a resolution that is too large for 3282 * the monitor than one that is too small. This means 3283 * that we will prefer to pan rather than to try to 3284 * center a smaller display on a larger screen. In 3285 * practice, this shouldn't matter because if a 3286 * monitor can support a larger resolution, it can 3287 * probably also support the smaller. A specific 3288 * exception is fixed format panels, but hopefully 3289 * they are properly dealt with by the "autostretch" 3290 * logic above. 3291 */ 3292 if ((ep->edid_modes[i].hdisplay > x) || 3293 (ep->edid_modes[i].vdisplay > y)) { 3294 continue; 3295 } 3296 3297 /* 3298 * at this point, the display mode is no larger than 3299 * what we've requested. 3300 */ 3301 if (vmp == NULL) 3302 vmp = &ep->edid_modes[i]; 3303 3304 /* eliminate smaller modes */ 3305 if ((vmp->hdisplay >= ep->edid_modes[i].hdisplay) || 3306 (vmp->vdisplay >= ep->edid_modes[i].vdisplay)) 3307 continue; 3308 3309 if ((vmp->hdisplay < ep->edid_modes[i].hdisplay) || 3310 (vmp->vdisplay < ep->edid_modes[i].vdisplay)) { 3311 vmp = &ep->edid_modes[i]; 3312 continue; 3313 } 3314 3315 KASSERT(vmp->hdisplay == ep->edid_modes[i].hdisplay); 3316 KASSERT(vmp->vdisplay == ep->edid_modes[i].vdisplay); 3317 3318 vmp = radeonfb_best_refresh(vmp, &ep->edid_modes[i]); 3319 } 3320 3321 return (vmp ? vmp : radeonfb_modelookup(sc->sc_defaultmode)); 3322 } 3323 3324 static int 3325 radeonfb_hasres(struct videomode *list, int nlist, int x, int y) 3326 { 3327 int i; 3328 3329 for (i = 0; i < nlist; i++) { 3330 if ((x == list[i].hdisplay) && 3331 (y == list[i].vdisplay)) { 3332 return 1; 3333 } 3334 } 3335 return 0; 3336 } 3337 3338 static void 3339 radeonfb_pickres(struct radeonfb_display *dp, uint16_t *x, uint16_t *y, 3340 int pan) 3341 { 3342 struct radeonfb_port *rp; 3343 struct edid_info *ep; 3344 int i, j; 3345 3346 *x = 0; 3347 *y = 0; 3348 3349 if (pan) { 3350 for (i = 0; i < dp->rd_ncrtcs; i++) { 3351 rp = dp->rd_crtcs[i].rc_port; 3352 ep = &rp->rp_edid; 3353 if (!rp->rp_edid_valid) { 3354 /* monitor not present */ 3355 continue; 3356 } 3357 3358 /* 3359 * For now we are ignoring "conflict" that 3360 * could occur when mixing some modes like 3361 * 1280x1024 and 1400x800. It isn't clear 3362 * which is better, so the first one wins. 3363 */ 3364 for (j = 0; j < ep->edid_nmodes; j++) { 3365 /* 3366 * ignore resolutions that are too big for 3367 * the radeon 3368 */ 3369 if (ep->edid_modes[j].hdisplay > 3370 dp->rd_softc->sc_maxx) 3371 continue; 3372 if (ep->edid_modes[j].vdisplay > 3373 dp->rd_softc->sc_maxy) 3374 continue; 3375 3376 /* 3377 * pick largest resolution, the 3378 * smaller monitor will pan 3379 */ 3380 if ((ep->edid_modes[j].hdisplay >= *x) && 3381 (ep->edid_modes[j].vdisplay >= *y)) { 3382 *x = ep->edid_modes[j].hdisplay; 3383 *y = ep->edid_modes[j].vdisplay; 3384 } 3385 } 3386 } 3387 3388 } else { 3389 struct videomode modes[64]; 3390 int nmodes = 0; 3391 int valid = 0; 3392 3393 for (i = 0; i < dp->rd_ncrtcs; i++) { 3394 /* 3395 * pick the largest resolution in common. 3396 */ 3397 rp = dp->rd_crtcs[i].rc_port; 3398 ep = &rp->rp_edid; 3399 3400 if (!rp->rp_edid_valid) 3401 continue; 3402 3403 if (!valid) { 3404 /* 3405 * Pick the preferred mode for this port 3406 * if available. 3407 */ 3408 if (ep->edid_preferred_mode) { 3409 struct videomode *vmp = 3410 ep->edid_preferred_mode; 3411 3412 if ((vmp->hdisplay <= 3413 dp->rd_softc->sc_maxx) && 3414 (vmp->vdisplay <= 3415 dp->rd_softc->sc_maxy)) 3416 modes[nmodes++] = *vmp; 3417 } else { 3418 3419 /* initialize starting list */ 3420 for (j = 0; j < ep->edid_nmodes; j++) { 3421 /* 3422 * ignore resolutions that are 3423 * too big for the radeon 3424 */ 3425 if (ep->edid_modes[j].hdisplay > 3426 dp->rd_softc->sc_maxx) 3427 continue; 3428 if (ep->edid_modes[j].vdisplay > 3429 dp->rd_softc->sc_maxy) 3430 continue; 3431 3432 modes[nmodes] = 3433 ep->edid_modes[j]; 3434 nmodes++; 3435 } 3436 } 3437 valid = 1; 3438 } else { 3439 /* merge into preexisting list */ 3440 for (j = 0; j < nmodes; j++) { 3441 if (!radeonfb_hasres(ep->edid_modes, 3442 ep->edid_nmodes, 3443 modes[j].hdisplay, 3444 modes[j].vdisplay)) { 3445 modes[j] = modes[nmodes]; 3446 j--; 3447 nmodes--; 3448 } 3449 } 3450 } 3451 } 3452 3453 /* now we have to pick from the merged list */ 3454 for (i = 0; i < nmodes; i++) { 3455 if ((modes[i].hdisplay >= *x) && 3456 (modes[i].vdisplay >= *y)) { 3457 *x = modes[i].hdisplay; 3458 *y = modes[i].vdisplay; 3459 } 3460 } 3461 } 3462 3463 if ((*x == 0) || (*y == 0)) { 3464 /* fallback to safe mode */ 3465 *x = 640; 3466 *y = 480; 3467 } 3468 } 3469 3470 /* 3471 * backlight levels are linear on: 3472 * - RV200, RV250, RV280, RV350 3473 * - but NOT on PowerBook4,3 6,3 6,5 3474 * according to Linux' radeonfb 3475 */ 3476 3477 /* Get the current backlight level for the display. */ 3478 3479 static int 3480 radeonfb_get_backlight(struct radeonfb_display *dp) 3481 { 3482 int s; 3483 uint32_t level; 3484 3485 s = spltty(); 3486 3487 level = radeonfb_get32(dp->rd_softc, RADEON_LVDS_GEN_CNTL); 3488 level &= RADEON_LVDS_BL_MOD_LEV_MASK; 3489 level >>= RADEON_LVDS_BL_MOD_LEV_SHIFT; 3490 3491 /* 3492 * On some chips, we should negate the backlight level. 3493 * XXX Find out on which chips. 3494 */ 3495 if (dp->rd_softc->sc_flags & RFB_INV_BLIGHT) 3496 level = RADEONFB_BACKLIGHT_MAX - level; 3497 3498 splx(s); 3499 3500 return level; 3501 } 3502 3503 /* Set the backlight to the given level for the display. */ 3504 3505 static int 3506 radeonfb_set_backlight(struct radeonfb_display *dp, int level) 3507 { 3508 struct radeonfb_softc *sc; 3509 int rlevel, s; 3510 uint32_t lvds; 3511 3512 s = spltty(); 3513 3514 if (level < 0) 3515 level = 0; 3516 else if (level >= RADEONFB_BACKLIGHT_MAX) 3517 level = RADEONFB_BACKLIGHT_MAX; 3518 3519 sc = dp->rd_softc; 3520 3521 /* On some chips, we should negate the backlight level. */ 3522 if (dp->rd_softc->sc_flags & RFB_INV_BLIGHT) { 3523 rlevel = RADEONFB_BACKLIGHT_MAX - level; 3524 } else 3525 rlevel = level; 3526 3527 callout_stop(&dp->rd_bl_lvds_co); 3528 radeonfb_engine_idle(sc); 3529 3530 /* 3531 * Turn off the display if the backlight is set to 0, since the 3532 * display is useless without backlight anyway. 3533 */ 3534 if (level == 0) 3535 radeonfb_blank(dp, 1); 3536 else if (radeonfb_get_backlight(dp) == 0) 3537 radeonfb_blank(dp, 0); 3538 3539 lvds = radeonfb_get32(sc, RADEON_LVDS_GEN_CNTL); 3540 lvds &= ~RADEON_LVDS_DISPLAY_DIS; 3541 if (!(lvds & RADEON_LVDS_BLON) || !(lvds & RADEON_LVDS_ON)) { 3542 lvds |= dp->rd_bl_lvds_val & RADEON_LVDS_DIGON; 3543 lvds |= RADEON_LVDS_BLON | RADEON_LVDS_EN; 3544 radeonfb_put32(sc, RADEON_LVDS_GEN_CNTL, lvds); 3545 lvds &= ~RADEON_LVDS_BL_MOD_LEV_MASK; 3546 lvds |= rlevel << RADEON_LVDS_BL_MOD_LEV_SHIFT; 3547 lvds |= RADEON_LVDS_ON; 3548 lvds |= dp->rd_bl_lvds_val & RADEON_LVDS_BL_MOD_EN; 3549 } else { 3550 lvds &= ~RADEON_LVDS_BL_MOD_LEV_MASK; 3551 lvds |= rlevel << RADEON_LVDS_BL_MOD_LEV_SHIFT; 3552 radeonfb_put32(sc, RADEON_LVDS_GEN_CNTL, lvds); 3553 } 3554 3555 dp->rd_bl_lvds_val &= ~RADEON_LVDS_STATE_MASK; 3556 dp->rd_bl_lvds_val |= lvds & RADEON_LVDS_STATE_MASK; 3557 /* XXX What is the correct delay? */ 3558 callout_schedule(&dp->rd_bl_lvds_co, 200 * hz); 3559 3560 splx(s); 3561 3562 return 0; 3563 } 3564 3565 /* 3566 * Callout function for delayed operations on the LVDS_GEN_CNTL register. 3567 * Set the delayed bits in the register, and clear the stored delayed 3568 * value. 3569 */ 3570 3571 static void radeonfb_lvds_callout(void *arg) 3572 { 3573 struct radeonfb_display *dp = arg; 3574 int s; 3575 3576 s = splhigh(); 3577 3578 radeonfb_mask32(dp->rd_softc, RADEON_LVDS_GEN_CNTL, ~0, 3579 dp->rd_bl_lvds_val); 3580 dp->rd_bl_lvds_val = 0; 3581 3582 splx(s); 3583 } 3584 3585 static void 3586 radeonfb_brightness_up(device_t dev) 3587 { 3588 struct radeonfb_softc *sc = device_private(dev); 3589 int level; 3590 3591 /* we assume the main display is the first one - need a better way */ 3592 if (sc->sc_ndisplays < 1) return; 3593 level = radeonfb_get_backlight(&sc->sc_displays[0]); 3594 level = min(RADEONFB_BACKLIGHT_MAX, level + 5); 3595 radeonfb_set_backlight(&sc->sc_displays[0], level); 3596 } 3597 3598 static void 3599 radeonfb_brightness_down(device_t dev) 3600 { 3601 struct radeonfb_softc *sc = device_private(dev); 3602 int level; 3603 3604 /* we assume the main display is the first one - need a better way */ 3605 if (sc->sc_ndisplays < 1) return; 3606 level = radeonfb_get_backlight(&sc->sc_displays[0]); 3607 level = max(0, level - 5); 3608 radeonfb_set_backlight(&sc->sc_displays[0], level); 3609 } 3610
Indexes created Tue Sep 23 07:09:52 GMT 2025