radeonfb.c revision 1.43
1 /* $NetBSD: radeonfb.c,v 1.43 2011/04/15 21:47:39 dyoung Exp $ */ 2 3 /*- 4 * Copyright (c) 2006 Itronix Inc. 5 * All rights reserved. 6 * 7 * Written by Garrett D'Amore for Itronix Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. The name of Itronix Inc. may not be used to endorse 18 * or promote products derived from this software without specific 19 * prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY ITRONIX INC. ``AS IS'' AND ANY EXPRESS 22 * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 23 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL ITRONIX INC. BE LIABLE FOR ANY 25 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE 27 * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 29 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 30 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 31 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * ATI Technologies Inc. ("ATI") has not assisted in the creation of, and 36 * does not endorse, this software. ATI will not be responsible or liable 37 * for any actual or alleged damage or loss caused by or in connection with 38 * the use of or reliance on this software. 39 */ 40 41 /* 42 * Portions of this code were taken from XFree86's Radeon driver, which bears 43 * this notice: 44 * 45 * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and 46 * VA Linux Systems Inc., Fremont, California. 47 * 48 * All Rights Reserved. 49 * 50 * Permission is hereby granted, free of charge, to any person obtaining 51 * a copy of this software and associated documentation files (the 52 * "Software"), to deal in the Software without restriction, including 53 * without limitation on the rights to use, copy, modify, merge, 54 * publish, distribute, sublicense, and/or sell copies of the Software, 55 * and to permit persons to whom the Software is furnished to do so, 56 * subject to the following conditions: 57 * 58 * The above copyright notice and this permission notice (including the 59 * next paragraph) shall be included in all copies or substantial 60 * portions of the Software. 61 * 62 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 63 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 64 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 65 * NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR 66 * THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 67 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 68 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 69 * DEALINGS IN THE SOFTWARE. 70 */ 71 72 #include <sys/cdefs.h> 73 __KERNEL_RCSID(0, "$NetBSD: radeonfb.c,v 1.43 2011/04/15 21:47:39 dyoung Exp $"); 74 75 #define RADEONFB_DEFAULT_DEPTH 8 76 77 #include <sys/param.h> 78 #include <sys/systm.h> 79 #include <sys/device.h> 80 #include <sys/malloc.h> 81 #include <sys/bus.h> 82 #include <sys/kernel.h> 83 #include <sys/lwp.h> 84 #include <sys/kauth.h> 85 86 #include <dev/wscons/wsdisplayvar.h> 87 #include <dev/wscons/wsconsio.h> 88 #include <dev/wsfont/wsfont.h> 89 #include <dev/rasops/rasops.h> 90 #include <dev/videomode/videomode.h> 91 #include <dev/videomode/edidvar.h> 92 #include <dev/wscons/wsdisplay_vconsvar.h> 93 #include <dev/pci/wsdisplay_pci.h> 94 95 #include <dev/pci/pcidevs.h> 96 #include <dev/pci/pcireg.h> 97 #include <dev/pci/pcivar.h> 98 #include <dev/pci/pciio.h> 99 #include <dev/pci/radeonfbreg.h> 100 #include <dev/pci/radeonfbvar.h> 101 #include "opt_radeonfb.h" 102 103 static int radeonfb_match(device_t, cfdata_t, void *); 104 static void radeonfb_attach(device_t, device_t, void *); 105 static int radeonfb_ioctl(void *, void *, unsigned long, void *, int, 106 struct lwp *); 107 static paddr_t radeonfb_mmap(void *, void *, off_t, int); 108 static int radeonfb_scratch_test(struct radeonfb_softc *, int, uint32_t); 109 static void radeonfb_loadbios(struct radeonfb_softc *, 110 struct pci_attach_args *); 111 112 static uintmax_t radeonfb_getprop_num(struct radeonfb_softc *, const char *, 113 uintmax_t); 114 static int radeonfb_getclocks(struct radeonfb_softc *); 115 static int radeonfb_gettmds(struct radeonfb_softc *); 116 static int radeonfb_calc_dividers(struct radeonfb_softc *, uint32_t, 117 uint32_t *, uint32_t *); 118 static int radeonfb_getconnectors(struct radeonfb_softc *); 119 static const struct videomode *radeonfb_modelookup(const char *); 120 static void radeonfb_init_screen(void *, struct vcons_screen *, int, long *); 121 static void radeonfb_pllwriteupdate(struct radeonfb_softc *, int); 122 static void radeonfb_pllwaitatomicread(struct radeonfb_softc *, int); 123 static void radeonfb_program_vclk(struct radeonfb_softc *, int, int); 124 static void radeonfb_modeswitch(struct radeonfb_display *); 125 static void radeonfb_setcrtc(struct radeonfb_display *, int); 126 static void radeonfb_init_misc(struct radeonfb_softc *); 127 static void radeonfb_set_fbloc(struct radeonfb_softc *); 128 static void radeonfb_init_palette(struct radeonfb_softc *, int); 129 static void radeonfb_r300cg_workaround(struct radeonfb_softc *); 130 131 static int radeonfb_isblank(struct radeonfb_display *); 132 static void radeonfb_blank(struct radeonfb_display *, int); 133 static int radeonfb_set_cursor(struct radeonfb_display *, 134 struct wsdisplay_cursor *); 135 static int radeonfb_set_curpos(struct radeonfb_display *, 136 struct wsdisplay_curpos *); 137 138 /* acceleration support */ 139 static void radeonfb_rectfill(struct radeonfb_display *, int dstx, int dsty, 140 int width, int height, uint32_t color); 141 static void radeonfb_bitblt(struct radeonfb_display *, int srcx, int srcy, 142 int dstx, int dsty, int width, int height, int rop, uint32_t mask); 143 static void radeonfb_feed_bytes(struct radeonfb_display *, int, uint8_t *); 144 static void radeonfb_setup_mono(struct radeonfb_display *, int, int, int, 145 int, uint32_t, uint32_t); 146 147 /* hw cursor support */ 148 static void radeonfb_cursor_cmap(struct radeonfb_display *); 149 static void radeonfb_cursor_shape(struct radeonfb_display *); 150 static void radeonfb_cursor_position(struct radeonfb_display *); 151 static void radeonfb_cursor_visible(struct radeonfb_display *); 152 static void radeonfb_cursor_update(struct radeonfb_display *, unsigned); 153 154 static void radeonfb_wait_fifo(struct radeonfb_softc *, int); 155 static void radeonfb_engine_idle(struct radeonfb_softc *); 156 static void radeonfb_engine_flush(struct radeonfb_softc *); 157 static void radeonfb_engine_reset(struct radeonfb_softc *); 158 static void radeonfb_engine_init(struct radeonfb_display *); 159 static inline void radeonfb_unclip(struct radeonfb_softc *); 160 161 static void radeonfb_eraserows(void *, int, int, long); 162 static void radeonfb_erasecols(void *, int, int, int, long); 163 static void radeonfb_copyrows(void *, int, int, int); 164 static void radeonfb_copycols(void *, int, int, int, int); 165 static void radeonfb_cursor(void *, int, int, int); 166 static void radeonfb_putchar(void *, int, int, unsigned, long); 167 static void radeonfb_putchar_wrapper(void *, int, int, unsigned, long); 168 static int radeonfb_allocattr(void *, int, int, int, long *); 169 170 static int radeonfb_get_backlight(struct radeonfb_display *); 171 static int radeonfb_set_backlight(struct radeonfb_display *, int); 172 static void radeonfb_lvds_callout(void *); 173 174 static void radeonfb_brightness_up(device_t); 175 static void radeonfb_brightness_down(device_t); 176 177 static struct videomode *radeonfb_best_refresh(struct videomode *, 178 struct videomode *); 179 static void radeonfb_pickres(struct radeonfb_display *, uint16_t *, 180 uint16_t *, int); 181 static const struct videomode *radeonfb_port_mode(struct radeonfb_softc *, 182 struct radeonfb_port *, int, int); 183 184 static int radeonfb_drm_print(void *, const char *); 185 186 #ifdef RADEONFB_DEBUG 187 int radeon_debug = 1; 188 #define DPRINTF(x) \ 189 if (radeon_debug) printf x 190 #define PRINTREG(r) DPRINTF((#r " = %08x\n", GET32(sc, r))) 191 #define PRINTPLL(r) DPRINTF((#r " = %08x\n", GETPLL(sc, r))) 192 #else 193 #define DPRINTF(x) 194 #define PRINTREG(r) 195 #define PRINTPLL(r) 196 #endif 197 198 #define ROUNDUP(x,y) (((x) + ((y) - 1)) & ~((y) - 1)) 199 200 #ifndef RADEON_DEFAULT_MODE 201 /* any reasonably modern display should handle this */ 202 #define RADEON_DEFAULT_MODE "1024x768x60" 203 #endif 204 205 extern const u_char rasops_cmap[768]; 206 207 const char *radeonfb_default_mode = RADEON_DEFAULT_MODE; 208 209 static struct { 210 int size; /* minimum memory size (MB) */ 211 int maxx; /* maximum x dimension */ 212 int maxy; /* maximum y dimension */ 213 int maxbpp; /* maximum bpp */ 214 int maxdisp; /* maximum logical display count */ 215 } radeonfb_limits[] = { 216 { 32, 2048, 1536, 32, 2 }, 217 { 16, 1600, 1200, 32, 2 }, 218 { 8, 1600, 1200, 32, 1 }, 219 { 0, 0, 0, 0, 0 }, 220 }; 221 222 static struct wsscreen_descr radeonfb_stdscreen = { 223 "fb", /* name */ 224 0, 0, /* ncols, nrows */ 225 NULL, /* textops */ 226 8, 16, /* fontwidth, fontheight */ 227 WSSCREEN_WSCOLORS | WSSCREEN_REVERSE, /* capabilities */ 228 0, /* modecookie */ 229 }; 230 231 struct wsdisplay_accessops radeonfb_accessops = { 232 radeonfb_ioctl, 233 radeonfb_mmap, 234 NULL, /* vcons_alloc_screen */ 235 NULL, /* vcons_free_screen */ 236 NULL, /* vcons_show_screen */ 237 NULL, /* load_font */ 238 NULL, /* pollc */ 239 NULL, /* scroll */ 240 }; 241 242 static struct { 243 uint16_t devid; 244 uint16_t family; 245 uint16_t flags; 246 } radeonfb_devices[] = 247 { 248 /* R100 family */ 249 { PCI_PRODUCT_ATI_RADEON_R100_QD, RADEON_R100, 0 }, 250 { PCI_PRODUCT_ATI_RADEON_R100_QE, RADEON_R100, 0 }, 251 { PCI_PRODUCT_ATI_RADEON_R100_QF, RADEON_R100, 0 }, 252 { PCI_PRODUCT_ATI_RADEON_R100_QG, RADEON_R100, 0 }, 253 254 /* RV100 family */ 255 { PCI_PRODUCT_ATI_RADEON_RV100_LY, RADEON_RV100, RFB_MOB }, 256 { PCI_PRODUCT_ATI_RADEON_RV100_LZ, RADEON_RV100, RFB_MOB }, 257 { PCI_PRODUCT_ATI_RADEON_RV100_QY, RADEON_RV100, 0 }, 258 { PCI_PRODUCT_ATI_RADEON_RV100_QZ, RADEON_RV100, 0 }, 259 260 /* RS100 family */ 261 { PCI_PRODUCT_ATI_RADEON_RS100_4136, RADEON_RS100, 0 }, 262 { PCI_PRODUCT_ATI_RADEON_RS100_4336, RADEON_RS100, RFB_MOB }, 263 264 /* RS200/RS250 family */ 265 { PCI_PRODUCT_ATI_RADEON_RS200_4337, RADEON_RS200, RFB_MOB }, 266 { PCI_PRODUCT_ATI_RADEON_RS200_A7, RADEON_RS200, 0 }, 267 { PCI_PRODUCT_ATI_RADEON_RS250_B7, RADEON_RS200, RFB_MOB }, 268 { PCI_PRODUCT_ATI_RADEON_RS250_D7, RADEON_RS200, 0 }, 269 270 /* R200 family */ 271 /* add more R200 products? , 5148 */ 272 { PCI_PRODUCT_ATI_RADEON_R200_BB, RADEON_R200, 0 }, 273 { PCI_PRODUCT_ATI_RADEON_R200_BC, RADEON_R200, 0 }, 274 { PCI_PRODUCT_ATI_RADEON_R200_QH, RADEON_R200, 0 }, 275 { PCI_PRODUCT_ATI_RADEON_R200_QL, RADEON_R200, 0 }, 276 { PCI_PRODUCT_ATI_RADEON_R200_QM, RADEON_R200, 0 }, 277 278 /* RV200 family */ 279 { PCI_PRODUCT_ATI_RADEON_RV200_LW, RADEON_RV200, RFB_MOB }, 280 { PCI_PRODUCT_ATI_RADEON_RV200_LX, RADEON_RV200, RFB_MOB }, 281 { PCI_PRODUCT_ATI_RADEON_RV200_QW, RADEON_RV200, 0 }, 282 { PCI_PRODUCT_ATI_RADEON_RV200_QX, RADEON_RV200, 0 }, 283 284 /* RV250 family */ 285 { PCI_PRODUCT_ATI_RADEON_RV250_4966, RADEON_RV250, 0 }, 286 { PCI_PRODUCT_ATI_RADEON_RV250_4967, RADEON_RV250, 0 }, 287 { PCI_PRODUCT_ATI_RADEON_RV250_4C64, RADEON_RV250, RFB_MOB }, 288 { PCI_PRODUCT_ATI_RADEON_RV250_4C66, RADEON_RV250, RFB_MOB }, 289 { PCI_PRODUCT_ATI_RADEON_RV250_4C67, RADEON_RV250, RFB_MOB }, 290 291 /* RS300 family */ 292 { PCI_PRODUCT_ATI_RADEON_RS300_X5, RADEON_RS300, 0 }, 293 { PCI_PRODUCT_ATI_RADEON_RS300_X4, RADEON_RS300, 0 }, 294 { PCI_PRODUCT_ATI_RADEON_RS300_7834, RADEON_RS300, 0 }, 295 { PCI_PRODUCT_ATI_RADEON_RS300_7835, RADEON_RS300, RFB_MOB }, 296 297 /* RV280 family */ 298 { PCI_PRODUCT_ATI_RADEON_RV280_5960, RADEON_RV280, 0 }, 299 { PCI_PRODUCT_ATI_RADEON_RV280_5961, RADEON_RV280, 0 }, 300 { PCI_PRODUCT_ATI_RADEON_RV280_5962, RADEON_RV280, 0 }, 301 { PCI_PRODUCT_ATI_RADEON_RV280_5963, RADEON_RV280, 0 }, 302 { PCI_PRODUCT_ATI_RADEON_RV280_5964, RADEON_RV280, 0 }, 303 { PCI_PRODUCT_ATI_RADEON_RV280_5C61, RADEON_RV280, RFB_MOB }, 304 { PCI_PRODUCT_ATI_RADEON_RV280_5C63, RADEON_RV280, RFB_MOB }, 305 306 /* R300 family */ 307 { PCI_PRODUCT_ATI_RADEON_R300_AD, RADEON_R300, 0 }, 308 { PCI_PRODUCT_ATI_RADEON_R300_AE, RADEON_R300, 0 }, 309 { PCI_PRODUCT_ATI_RADEON_R300_AF, RADEON_R300, 0 }, 310 { PCI_PRODUCT_ATI_RADEON_R300_AG, RADEON_R300, 0 }, 311 { PCI_PRODUCT_ATI_RADEON_R300_ND, RADEON_R300, 0 }, 312 { PCI_PRODUCT_ATI_RADEON_R300_NE, RADEON_R300, 0 }, 313 { PCI_PRODUCT_ATI_RADEON_R300_NF, RADEON_R300, 0 }, 314 { PCI_PRODUCT_ATI_RADEON_R300_NG, RADEON_R300, 0 }, 315 316 /* RV350/RV360 family */ 317 { PCI_PRODUCT_ATI_RADEON_RV350_AP, RADEON_RV350, 0 }, 318 { PCI_PRODUCT_ATI_RADEON_RV350_AQ, RADEON_RV350, 0 }, 319 { PCI_PRODUCT_ATI_RADEON_RV360_AR, RADEON_RV350, 0 }, 320 { PCI_PRODUCT_ATI_RADEON_RV350_AS, RADEON_RV350, 0 }, 321 { PCI_PRODUCT_ATI_RADEON_RV350_AT, RADEON_RV350, 0 }, 322 { PCI_PRODUCT_ATI_RADEON_RV350_AV, RADEON_RV350, 0 }, 323 { PCI_PRODUCT_ATI_RADEON_RV350_NP, RADEON_RV350, RFB_MOB }, 324 { PCI_PRODUCT_ATI_RADEON_RV350_NQ, RADEON_RV350, RFB_MOB }, 325 { PCI_PRODUCT_ATI_RADEON_RV350_NR, RADEON_RV350, RFB_MOB }, 326 { PCI_PRODUCT_ATI_RADEON_RV350_NS, RADEON_RV350, RFB_MOB }, 327 { PCI_PRODUCT_ATI_RADEON_RV350_NT, RADEON_RV350, RFB_MOB }, 328 { PCI_PRODUCT_ATI_RADEON_RV350_NV, RADEON_RV350, RFB_MOB }, 329 330 /* R350/R360 family */ 331 { PCI_PRODUCT_ATI_RADEON_R350_AH, RADEON_R350, 0 }, 332 { PCI_PRODUCT_ATI_RADEON_R350_AI, RADEON_R350, 0 }, 333 { PCI_PRODUCT_ATI_RADEON_R350_AJ, RADEON_R350, 0 }, 334 { PCI_PRODUCT_ATI_RADEON_R350_AK, RADEON_R350, 0 }, 335 { PCI_PRODUCT_ATI_RADEON_R350_NH, RADEON_R350, 0 }, 336 { PCI_PRODUCT_ATI_RADEON_R350_NI, RADEON_R350, 0 }, 337 { PCI_PRODUCT_ATI_RADEON_R350_NK, RADEON_R350, 0 }, 338 { PCI_PRODUCT_ATI_RADEON_R360_NJ, RADEON_R350, 0 }, 339 340 /* RV380/RV370 family */ 341 { PCI_PRODUCT_ATI_RADEON_RV380_3150, RADEON_RV380, RFB_MOB }, 342 { PCI_PRODUCT_ATI_RADEON_RV380_3154, RADEON_RV380, RFB_MOB }, 343 { PCI_PRODUCT_ATI_RADEON_RV380_3E50, RADEON_RV380, 0 }, 344 { PCI_PRODUCT_ATI_RADEON_RV380_3E54, RADEON_RV380, 0 }, 345 { PCI_PRODUCT_ATI_RADEON_RV370_5460, RADEON_RV380, RFB_MOB }, 346 { PCI_PRODUCT_ATI_RADEON_RV370_5464, RADEON_RV380, RFB_MOB }, 347 { PCI_PRODUCT_ATI_RADEON_RV370_5B60, RADEON_RV380, 0 }, 348 { PCI_PRODUCT_ATI_RADEON_RV370_5B64, RADEON_RV380, 0 }, 349 { PCI_PRODUCT_ATI_RADEON_RV370_5B65, RADEON_RV380, 0 }, 350 351 /* R420/R423 family */ 352 { PCI_PRODUCT_ATI_RADEON_R420_JH, RADEON_R420, 0 }, 353 { PCI_PRODUCT_ATI_RADEON_R420_JI, RADEON_R420, 0 }, 354 { PCI_PRODUCT_ATI_RADEON_R420_JJ, RADEON_R420, 0 }, 355 { PCI_PRODUCT_ATI_RADEON_R420_JK, RADEON_R420, 0 }, 356 { PCI_PRODUCT_ATI_RADEON_R420_JL, RADEON_R420, 0 }, 357 { PCI_PRODUCT_ATI_RADEON_R420_JM, RADEON_R420, 0 }, 358 { PCI_PRODUCT_ATI_RADEON_R420_JN, RADEON_R420, RFB_MOB }, 359 { PCI_PRODUCT_ATI_RADEON_R420_JP, RADEON_R420, 0 }, 360 { PCI_PRODUCT_ATI_RADEON_R423_UH, RADEON_R420, 0 }, 361 { PCI_PRODUCT_ATI_RADEON_R423_UI, RADEON_R420, 0 }, 362 { PCI_PRODUCT_ATI_RADEON_R423_UJ, RADEON_R420, 0 }, 363 { PCI_PRODUCT_ATI_RADEON_R423_UK, RADEON_R420, 0 }, 364 { PCI_PRODUCT_ATI_RADEON_R423_UQ, RADEON_R420, 0 }, 365 { PCI_PRODUCT_ATI_RADEON_R423_UR, RADEON_R420, 0 }, 366 { PCI_PRODUCT_ATI_RADEON_R423_UT, RADEON_R420, 0 }, 367 { PCI_PRODUCT_ATI_RADEON_R423_5D57, RADEON_R420, 0 }, 368 { PCI_PRODUCT_ATI_RADEON_R430_554F, RADEON_R420, 0 }, 369 370 { 0, 0, 0 } 371 }; 372 373 static struct { 374 int divider; 375 int mask; 376 } radeonfb_dividers[] = { 377 { 1, 0 }, 378 { 2, 1 }, 379 { 3, 4 }, 380 { 4, 2 }, 381 { 6, 6 }, 382 { 8, 3 }, 383 { 12, 7 }, 384 { 0, 0 } 385 }; 386 387 /* 388 * This table taken from X11. 389 */ 390 static const struct { 391 int family; 392 struct radeon_tmds_pll plls[4]; 393 } radeonfb_tmds_pll[] = { 394 { RADEON_R100, {{12000, 0xa1b}, {-1, 0xa3f}}}, 395 { RADEON_RV100, {{12000, 0xa1b}, {-1, 0xa3f}}}, 396 { RADEON_RS100, {{0, 0}}}, 397 { RADEON_RV200, {{15000, 0xa1b}, {-1, 0xa3f}}}, 398 { RADEON_RS200, {{15000, 0xa1b}, {-1, 0xa3f}}}, 399 { RADEON_R200, {{15000, 0xa1b}, {-1, 0xa3f}}}, 400 { RADEON_RV250, {{15500, 0x81b}, {-1, 0x83f}}}, 401 { RADEON_RS300, {{0, 0}}}, 402 { RADEON_RV280, {{13000, 0x400f4}, {15000, 0x400f7}}}, 403 { RADEON_R300, {{-1, 0xb01cb}}}, 404 { RADEON_R350, {{-1, 0xb01cb}}}, 405 { RADEON_RV350, {{15000, 0xb0155}, {-1, 0xb01cb}}}, 406 { RADEON_RV380, {{15000, 0xb0155}, {-1, 0xb01cb}}}, 407 { RADEON_R420, {{-1, 0xb01cb}}}, 408 }; 409 410 #define RADEONFB_BACKLIGHT_MAX 255 /* Maximum backlight level. */ 411 412 413 CFATTACH_DECL(radeonfb, sizeof (struct radeonfb_softc), 414 radeonfb_match, radeonfb_attach, NULL, NULL); 415 416 static int 417 radeonfb_match(device_t parent, cfdata_t match, void *aux) 418 { 419 struct pci_attach_args *pa = aux; 420 int i; 421 422 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_ATI) 423 return 0; 424 425 for (i = 0; radeonfb_devices[i].devid; i++) { 426 if (PCI_PRODUCT(pa->pa_id) == radeonfb_devices[i].devid) 427 return 100; /* high to defeat VGA/VESA */ 428 } 429 430 return 0; 431 } 432 433 static void 434 radeonfb_attach(device_t parent, device_t dev, void *aux) 435 { 436 struct radeonfb_softc *sc = device_private(dev); 437 struct pci_attach_args *pa = aux; 438 const char *mptr; 439 bus_size_t bsz; 440 pcireg_t screg; 441 int i, j, fg, bg, ul, flags; 442 uint32_t v; 443 444 sc->sc_id = pa->pa_id; 445 for (i = 0; radeonfb_devices[i].devid; i++) { 446 if (PCI_PRODUCT(sc->sc_id) == radeonfb_devices[i].devid) 447 break; 448 } 449 450 pci_devinfo(sc->sc_id, pa->pa_class, 0, sc->sc_devinfo, 451 sizeof(sc->sc_devinfo)); 452 453 aprint_naive("\n"); 454 aprint_normal(": %s\n", sc->sc_devinfo); 455 456 DPRINTF((prop_dictionary_externalize(device_properties(dev)))); 457 458 KASSERT(radeonfb_devices[i].devid != 0); 459 sc->sc_pt = pa->pa_tag; 460 sc->sc_iot = pa->pa_iot; 461 sc->sc_pc = pa->pa_pc; 462 sc->sc_family = radeonfb_devices[i].family; 463 sc->sc_flags = radeonfb_devices[i].flags; 464 465 /* enable memory and IO access */ 466 screg = pci_conf_read(sc->sc_pc, sc->sc_pt, PCI_COMMAND_STATUS_REG); 467 screg |= PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE; 468 pci_conf_write(sc->sc_pc, sc->sc_pt, PCI_COMMAND_STATUS_REG, screg); 469 470 /* 471 * Some flags are general to entire chip families, and rather 472 * than clutter up the table with them, we go ahead and set 473 * them here. 474 */ 475 switch (sc->sc_family) { 476 case RADEON_RS100: 477 case RADEON_RS200: 478 sc->sc_flags |= RFB_IGP | RFB_RV100; 479 break; 480 481 case RADEON_RV100: 482 case RADEON_RV200: 483 case RADEON_RV250: 484 case RADEON_RV280: 485 sc->sc_flags |= RFB_RV100; 486 break; 487 488 case RADEON_RS300: 489 sc->sc_flags |= RFB_SDAC | RFB_IGP | RFB_RV100; 490 break; 491 492 case RADEON_R300: 493 case RADEON_RV350: 494 case RADEON_R350: 495 case RADEON_RV380: 496 case RADEON_R420: 497 /* newer chips */ 498 sc->sc_flags |= RFB_R300; 499 break; 500 501 case RADEON_R100: 502 sc->sc_flags |= RFB_NCRTC2; 503 break; 504 } 505 506 if ((sc->sc_family == RADEON_RV200) || 507 (sc->sc_family == RADEON_RV250) || 508 (sc->sc_family == RADEON_RV280) || 509 (sc->sc_family == RADEON_RV350)) { 510 bool inverted = 0; 511 /* backlight level is linear */ 512 DPRINTF(("found RV* chip, backlight is supposedly linear\n")); 513 prop_dictionary_get_bool(device_properties(&sc->sc_dev), 514 "backlight_level_reverted", &inverted); 515 if (inverted) { 516 DPRINTF(("nope, it's inverted\n")); 517 sc->sc_flags |= RFB_INV_BLIGHT; 518 } 519 } else 520 sc->sc_flags |= RFB_INV_BLIGHT; 521 522 /* 523 * XXX: to support true multihead, this must change. 524 */ 525 sc->sc_ndisplays = 1; 526 527 /* XXX: */ 528 if (!HAS_CRTC2(sc)) { 529 sc->sc_ndisplays = 1; 530 } 531 532 if (pci_mapreg_map(pa, RADEON_MAPREG_MMIO, PCI_MAPREG_TYPE_MEM, 0, 533 &sc->sc_regt, &sc->sc_regh, &sc->sc_regaddr, 534 &sc->sc_regsz) != 0) { 535 aprint_error("%s: unable to map registers!\n", XNAME(sc)); 536 goto error; 537 } 538 539 if (pci_mapreg_info(sc->sc_pc, sc->sc_pt, PCI_MAPREG_ROM, 540 PCI_MAPREG_TYPE_ROM, &sc->sc_romaddr, &sc->sc_romsz, &flags) != 0) 541 { 542 aprint_error("%s: unable to find ROM!\n", XNAME(sc)); 543 goto error; 544 } 545 sc->sc_romt = sc->sc_memt; 546 547 /* scratch register test... */ 548 if (radeonfb_scratch_test(sc, RADEON_BIOS_0_SCRATCH, 0x55555555) || 549 radeonfb_scratch_test(sc, RADEON_BIOS_0_SCRATCH, 0xaaaaaaaa)) { 550 aprint_error("%s: scratch register test failed!\n", XNAME(sc)); 551 goto error; 552 } 553 554 PRINTREG(RADEON_BIOS_4_SCRATCH); 555 PRINTREG(RADEON_FP_GEN_CNTL); 556 sc->sc_fp_gen_cntl = GET32(sc, RADEON_FP_GEN_CNTL); 557 PRINTREG(RADEON_FP2_GEN_CNTL); 558 PRINTREG(RADEON_TMDS_CNTL); 559 PRINTREG(RADEON_TMDS_TRANSMITTER_CNTL); 560 PRINTREG(RADEON_TMDS_PLL_CNTL); 561 PRINTREG(RADEON_LVDS_GEN_CNTL); 562 PRINTREG(RADEON_FP_HORZ_STRETCH); 563 PRINTREG(RADEON_FP_VERT_STRETCH); 564 565 /* XXX: RV100 specific */ 566 PUT32(sc, RADEON_TMDS_PLL_CNTL, 0xa27); 567 568 PATCH32(sc, RADEON_TMDS_TRANSMITTER_CNTL, 569 RADEON_TMDS_TRANSMITTER_PLLEN, 570 RADEON_TMDS_TRANSMITTER_PLLEN | RADEON_TMDS_TRANSMITTER_PLLRST); 571 572 radeonfb_i2c_init(sc); 573 574 radeonfb_loadbios(sc, pa); 575 576 #ifdef RADEONFB_BIOS_INIT 577 if (radeonfb_bios_init(sc)) { 578 aprint_error("%s: BIOS inititialization failed\n", XNAME(sc)); 579 } 580 #endif 581 582 if (radeonfb_getclocks(sc)) { 583 aprint_error("%s: Unable to get reference clocks from BIOS\n", 584 XNAME(sc)); 585 goto error; 586 } 587 588 if (radeonfb_gettmds(sc)) { 589 aprint_error("%s: Unable to identify TMDS PLL settings\n", 590 XNAME(sc)); 591 goto error; 592 } 593 594 aprint_verbose("%s: refclk = %d.%03d MHz, refdiv = %d " 595 "minpll = %d, maxpll = %d\n", XNAME(sc), 596 (int)sc->sc_refclk / 1000, (int)sc->sc_refclk % 1000, 597 (int)sc->sc_refdiv, (int)sc->sc_minpll, (int)sc->sc_maxpll); 598 599 radeonfb_getconnectors(sc); 600 601 radeonfb_set_fbloc(sc); 602 603 for (i = 0; radeonfb_limits[i].size; i++) { 604 if (sc->sc_memsz >= radeonfb_limits[i].size) { 605 sc->sc_maxx = radeonfb_limits[i].maxx; 606 sc->sc_maxy = radeonfb_limits[i].maxy; 607 sc->sc_maxbpp = radeonfb_limits[i].maxbpp; 608 /* framebuffer offset, start at a 4K page */ 609 sc->sc_fboffset = sc->sc_memsz / 610 radeonfb_limits[i].maxdisp; 611 /* 612 * we use the fbsize to figure out where we can store 613 * things like cursor data. 614 */ 615 sc->sc_fbsize = 616 ROUNDUP(ROUNDUP(sc->sc_maxx * sc->sc_maxbpp / 8 , 617 RADEON_STRIDEALIGN) * sc->sc_maxy, 618 4096); 619 break; 620 } 621 } 622 623 624 radeonfb_init_misc(sc); 625 radeonfb_init_palette(sc, 0); 626 if (HAS_CRTC2(sc)) 627 radeonfb_init_palette(sc, 1); 628 629 /* program the DAC wirings */ 630 for (i = 0; i < (HAS_CRTC2(sc) ? 2 : 1); i++) { 631 switch (sc->sc_ports[i].rp_dac_type) { 632 case RADEON_DAC_PRIMARY: 633 PATCH32(sc, RADEON_DAC_CNTL2, 634 i ? RADEON_DAC2_DAC_CLK_SEL : 0, 635 ~RADEON_DAC2_DAC_CLK_SEL); 636 break; 637 case RADEON_DAC_TVDAC: 638 /* we always use the TVDAC to drive a secondary analog 639 * CRT for now. if we ever support TV-out this will 640 * have to change. 641 */ 642 SET32(sc, RADEON_DAC_CNTL2, 643 RADEON_DAC2_DAC2_CLK_SEL); 644 PATCH32(sc, RADEON_DISP_HW_DEBUG, 645 i ? 0 : RADEON_CRT2_DISP1_SEL, 646 ~RADEON_CRT2_DISP1_SEL); 647 break; 648 } 649 } 650 PRINTREG(RADEON_DAC_CNTL2); 651 PRINTREG(RADEON_DISP_HW_DEBUG); 652 653 /* other DAC programming */ 654 v = GET32(sc, RADEON_DAC_CNTL); 655 v &= (RADEON_DAC_RANGE_CNTL_MASK | RADEON_DAC_BLANKING); 656 v |= RADEON_DAC_MASK_ALL | RADEON_DAC_8BIT_EN; 657 PUT32(sc, RADEON_DAC_CNTL, v); 658 PRINTREG(RADEON_DAC_CNTL); 659 660 /* XXX: this may need more investigation */ 661 PUT32(sc, RADEON_TV_DAC_CNTL, 0x00280203); 662 PRINTREG(RADEON_TV_DAC_CNTL); 663 664 /* enable TMDS */ 665 SET32(sc, RADEON_FP_GEN_CNTL, 666 RADEON_FP_TMDS_EN | 667 RADEON_FP_CRTC_DONT_SHADOW_VPAR | 668 RADEON_FP_CRTC_DONT_SHADOW_HEND); 669 /* 670 * XXX 671 * no idea why this is necessary - if I do not clear this bit on my 672 * iBook G4 the screen remains black, even though it's already clear. 673 * It needs to be set on my Sun XVR-100 for the DVI port to work 674 */ 675 676 if (sc->sc_fp_gen_cntl & RADEON_FP_SEL_CRTC2) { 677 SET32(sc, RADEON_FP_GEN_CNTL, RADEON_FP_SEL_CRTC2); 678 } else 679 CLR32(sc, RADEON_FP_GEN_CNTL, RADEON_FP_SEL_CRTC2); 680 681 if (HAS_CRTC2(sc)) 682 SET32(sc, RADEON_FP2_GEN_CNTL, RADEON_FP2_SRC_SEL_CRTC2); 683 684 /* 685 * we use bus_space_map instead of pci_mapreg, because we don't 686 * need the full aperature space. no point in wasting virtual 687 * address space we don't intend to use, right? 688 */ 689 if ((sc->sc_memsz < (4096 * 1024)) || 690 (pci_mapreg_info(sc->sc_pc, sc->sc_pt, RADEON_MAPREG_VRAM, 691 PCI_MAPREG_TYPE_MEM, &sc->sc_memaddr, &bsz, NULL) != 0) || 692 (bsz < sc->sc_memsz)) { 693 sc->sc_memsz = 0; 694 aprint_error("%s: Bad frame buffer configuration\n", 695 XNAME(sc)); 696 goto error; 697 } 698 699 /* 64 MB should be enough -- more just wastes map entries */ 700 if (sc->sc_memsz > (64 << 20)) 701 sc->sc_memsz = (64 << 20); 702 703 sc->sc_memt = pa->pa_memt; 704 if (bus_space_map(sc->sc_memt, sc->sc_memaddr, sc->sc_memsz, 705 BUS_SPACE_MAP_LINEAR, &sc->sc_memh) != 0) { 706 sc->sc_memsz = 0; 707 aprint_error("%s: Unable to map frame buffer\n", XNAME(sc)); 708 goto error; 709 } 710 711 aprint_normal("%s: %d MB aperture at 0x%08x, " 712 "%d KB registers at 0x%08x\n", XNAME(sc), 713 (int)sc->sc_memsz >> 20, (unsigned)sc->sc_memaddr, 714 (int)sc->sc_regsz >> 10, (unsigned)sc->sc_regaddr); 715 716 /* setup default video mode from devprop (allows PROM override) */ 717 sc->sc_defaultmode = radeonfb_default_mode; 718 if (prop_dictionary_get_cstring_nocopy(device_properties(&sc->sc_dev), 719 "videomode", &mptr)) { 720 721 strncpy(sc->sc_modebuf, mptr, sizeof(sc->sc_modebuf)); 722 sc->sc_defaultmode = sc->sc_modebuf; 723 } 724 725 /* initialize some basic display parameters */ 726 for (i = 0; i < sc->sc_ndisplays; i++) { 727 struct radeonfb_display *dp = &sc->sc_displays[i]; 728 struct rasops_info *ri; 729 long defattr; 730 struct wsemuldisplaydev_attach_args aa; 731 732 /* 733 * Figure out how many "displays" (desktops) we are going to 734 * support. If more than one, then each CRTC gets its own 735 * programming. 736 * 737 * XXX: this code needs to change to support mergedfb. 738 * XXX: would be nice to allow this to be overridden 739 */ 740 if (HAS_CRTC2(sc) && (sc->sc_ndisplays == 1)) { 741 DPRINTF(("dual crtcs!\n")); 742 dp->rd_ncrtcs = 2; 743 dp->rd_crtcs[0].rc_number = 0; 744 dp->rd_crtcs[1].rc_number = 1; 745 } else { 746 dp->rd_ncrtcs = 1; 747 dp->rd_crtcs[0].rc_number = i; 748 } 749 750 /* set up port pointer */ 751 for (j = 0; j < dp->rd_ncrtcs; j++) { 752 dp->rd_crtcs[j].rc_port = 753 &sc->sc_ports[dp->rd_crtcs[j].rc_number]; 754 } 755 756 dp->rd_softc = sc; 757 dp->rd_wsmode = WSDISPLAYIO_MODE_EMUL; 758 dp->rd_bg = WS_DEFAULT_BG; 759 #if 0 760 dp->rd_bpp = sc->sc_maxbpp; /* XXX: for now */ 761 #else 762 dp->rd_bpp = RADEONFB_DEFAULT_DEPTH; /* XXX */ 763 #endif 764 /* for text mode, we pick a resolution that won't 765 * require panning */ 766 radeonfb_pickres(dp, &dp->rd_virtx, &dp->rd_virty, 0); 767 768 aprint_normal("%s: display %d: " 769 "initial virtual resolution %dx%d at %d bpp\n", 770 XNAME(sc), i, dp->rd_virtx, dp->rd_virty, dp->rd_bpp); 771 772 /* now select the *video mode* that we will use */ 773 for (j = 0; j < dp->rd_ncrtcs; j++) { 774 const struct videomode *vmp; 775 vmp = radeonfb_port_mode(sc, dp->rd_crtcs[j].rc_port, 776 dp->rd_virtx, dp->rd_virty); 777 778 /* 779 * virtual resolution should be at least as high as 780 * physical 781 */ 782 if (dp->rd_virtx < vmp->hdisplay || 783 dp->rd_virty < vmp->vdisplay) { 784 dp->rd_virtx = vmp->hdisplay; 785 dp->rd_virty = vmp->vdisplay; 786 } 787 788 dp->rd_crtcs[j].rc_videomode = *vmp; 789 printf("%s: port %d: physical %dx%d %dHz\n", 790 XNAME(sc), j, vmp->hdisplay, vmp->vdisplay, 791 DIVIDE(DIVIDE(vmp->dot_clock * 1000, 792 vmp->htotal), vmp->vtotal)); 793 } 794 795 /* N.B.: radeon wants 64-byte aligned stride */ 796 dp->rd_stride = dp->rd_virtx * dp->rd_bpp / 8; 797 dp->rd_stride = ROUNDUP(dp->rd_stride, RADEON_STRIDEALIGN); 798 799 dp->rd_offset = sc->sc_fboffset * i; 800 dp->rd_fbptr = (vaddr_t)bus_space_vaddr(sc->sc_memt, 801 sc->sc_memh) + dp->rd_offset; 802 dp->rd_curoff = sc->sc_fbsize; 803 dp->rd_curptr = dp->rd_fbptr + dp->rd_curoff; 804 805 DPRINTF(("fpbtr = %p\n", (void *)dp->rd_fbptr)); 806 807 switch (dp->rd_bpp) { 808 case 8: 809 dp->rd_format = 2; 810 break; 811 case 32: 812 dp->rd_format = 6; 813 break; 814 default: 815 aprint_error("%s: bad depth %d\n", XNAME(sc), 816 dp->rd_bpp); 817 goto error; 818 } 819 820 DPRINTF("init engine\n"); 821 /* XXX: this seems suspicious - per display engine 822 initialization? */ 823 radeonfb_engine_init(dp); 824 825 /* copy the template into place */ 826 dp->rd_wsscreens_storage[0] = radeonfb_stdscreen; 827 dp->rd_wsscreens = dp->rd_wsscreens_storage; 828 829 /* and make up the list */ 830 dp->rd_wsscreenlist.nscreens = 1; 831 dp->rd_wsscreenlist.screens = 832 (const struct wsscreen_descr **)&dp->rd_wsscreens; 833 834 vcons_init(&dp->rd_vd, dp, dp->rd_wsscreens, 835 &radeonfb_accessops); 836 837 dp->rd_vd.init_screen = radeonfb_init_screen; 838 839 dp->rd_console = 0; 840 prop_dictionary_get_bool(device_properties(&sc->sc_dev), 841 "is_console", &dp->rd_console); 842 843 dp->rd_vscreen.scr_flags |= VCONS_SCREEN_IS_STATIC; 844 845 846 vcons_init_screen(&dp->rd_vd, &dp->rd_vscreen, 847 dp->rd_console, &defattr); 848 849 ri = &dp->rd_vscreen.scr_ri; 850 851 /* clear the screen */ 852 rasops_unpack_attr(defattr, &fg, &bg, &ul); 853 radeonfb_rectfill(dp, 0, 0, ri->ri_width, ri->ri_height, 854 ri->ri_devcmap[bg & 0xf]); 855 856 dp->rd_wsscreens->textops = &ri->ri_ops; 857 dp->rd_wsscreens->capabilities = ri->ri_caps; 858 dp->rd_wsscreens->nrows = ri->ri_rows; 859 dp->rd_wsscreens->ncols = ri->ri_cols; 860 861 #ifdef SPLASHSCREEN 862 dp->rd_splash.si_depth = ri->ri_depth; 863 dp->rd_splash.si_bits = ri->ri_bits; 864 dp->rd_splash.si_hwbits = ri->ri_hwbits; 865 dp->rd_splash.si_width = ri->ri_width; 866 dp->rd_splash.si_height = ri->ri_height; 867 dp->rd_splash.si_stride = ri->ri_stride; 868 dp->rd_splash.si_fillrect = NULL; 869 #endif 870 if (dp->rd_console) { 871 872 radeonfb_modeswitch(dp); 873 wsdisplay_cnattach(dp->rd_wsscreens, ri, 0, 0, 874 defattr); 875 #ifdef SPLASHSCREEN 876 if (splash_render(&dp->rd_splash, 877 SPLASH_F_CENTER|SPLASH_F_FILL) == 0) 878 SCREEN_DISABLE_DRAWING(&dp->rd_vscreen); 879 else 880 #endif 881 vcons_replay_msgbuf(&dp->rd_vscreen); 882 } else { 883 884 /* 885 * since we're not the console we can postpone 886 * the rest until someone actually allocates a 887 * screen for us. but we do clear the screen 888 * at least. 889 */ 890 memset(ri->ri_bits, 0, 1024); 891 892 radeonfb_modeswitch(dp); 893 #ifdef SPLASHSCREEN 894 if (splash_render(&dp->rd_splash, 895 SPLASH_F_CENTER|SPLASH_F_FILL) == 0) 896 SCREEN_DISABLE_DRAWING(&dp->rd_vscreen); 897 #endif 898 } 899 900 aa.console = dp->rd_console; 901 aa.scrdata = &dp->rd_wsscreenlist; 902 aa.accessops = &radeonfb_accessops; 903 aa.accesscookie = &dp->rd_vd; 904 905 config_found(&sc->sc_dev, &aa, wsemuldisplaydevprint); 906 907 radeonfb_blank(dp, 0); 908 909 /* Initialise delayed lvds operations for backlight. */ 910 callout_init(&dp->rd_bl_lvds_co, 0); 911 callout_setfunc(&dp->rd_bl_lvds_co, 912 radeonfb_lvds_callout, dp); 913 } 914 915 /* 916 * if we have console output via firmware like on sparc64 it may 917 * interfere with DAC programming so program the palette again 918 * here after we took over 919 */ 920 radeonfb_init_palette(sc, 0); 921 if (HAS_CRTC2(sc)) 922 radeonfb_init_palette(sc, 1); 923 924 pmf_event_register(dev, PMFE_DISPLAY_BRIGHTNESS_UP, 925 radeonfb_brightness_up, TRUE); 926 pmf_event_register(dev, PMFE_DISPLAY_BRIGHTNESS_DOWN, 927 radeonfb_brightness_down, TRUE); 928 929 config_found_ia(dev, "drm", aux, radeonfb_drm_print); 930 931 return; 932 933 error: 934 if (sc->sc_biossz) 935 free(sc->sc_bios, M_DEVBUF); 936 937 if (sc->sc_regsz) 938 bus_space_unmap(sc->sc_regt, sc->sc_regh, sc->sc_regsz); 939 940 if (sc->sc_memsz) 941 bus_space_unmap(sc->sc_memt, sc->sc_memh, sc->sc_memsz); 942 } 943 944 static int 945 radeonfb_drm_print(void *aux, const char *pnp) 946 { 947 if (pnp) 948 aprint_normal("drm at %s", pnp); 949 return (UNCONF); 950 } 951 952 int 953 radeonfb_ioctl(void *v, void *vs, 954 unsigned long cmd, void *d, int flag, struct lwp *l) 955 { 956 struct vcons_data *vd; 957 struct radeonfb_display *dp; 958 struct radeonfb_softc *sc; 959 struct wsdisplay_param *param; 960 961 vd = (struct vcons_data *)v; 962 dp = (struct radeonfb_display *)vd->cookie; 963 sc = dp->rd_softc; 964 965 switch (cmd) { 966 case WSDISPLAYIO_GTYPE: 967 *(unsigned *)d = WSDISPLAY_TYPE_PCIMISC; 968 return 0; 969 970 case WSDISPLAYIO_GINFO: 971 if (vd->active != NULL) { 972 struct wsdisplay_fbinfo *fb; 973 fb = (struct wsdisplay_fbinfo *)d; 974 fb->width = dp->rd_virtx; 975 fb->height = dp->rd_virty; 976 fb->depth = dp->rd_bpp; 977 fb->cmsize = 256; 978 return 0; 979 } else 980 return ENODEV; 981 case WSDISPLAYIO_GVIDEO: 982 if (radeonfb_isblank(dp)) 983 *(unsigned *)d = WSDISPLAYIO_VIDEO_OFF; 984 else 985 *(unsigned *)d = WSDISPLAYIO_VIDEO_ON; 986 return 0; 987 988 case WSDISPLAYIO_SVIDEO: 989 radeonfb_blank(dp, 990 (*(unsigned int *)d == WSDISPLAYIO_VIDEO_OFF)); 991 return 0; 992 993 case WSDISPLAYIO_GETCMAP: 994 #if 0 995 if (dp->rd_bpp == 8) 996 return radeonfb_getcmap(sc, 997 (struct wsdisplay_cmap *)d); 998 #endif 999 return EINVAL; 1000 1001 case WSDISPLAYIO_PUTCMAP: 1002 #if 0 1003 if (dp->rd_bpp == 8) 1004 return radeonfb_putcmap(sc, 1005 (struct wsdisplay_cmap *)d); 1006 #endif 1007 return EINVAL; 1008 1009 case WSDISPLAYIO_LINEBYTES: 1010 *(unsigned *)d = dp->rd_stride; 1011 return 0; 1012 1013 case WSDISPLAYIO_SMODE: 1014 if (*(int *)d != dp->rd_wsmode) { 1015 dp->rd_wsmode = *(int *)d; 1016 if ((dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) && 1017 (dp->rd_vd.active)) { 1018 radeonfb_engine_init(dp); 1019 radeonfb_init_palette(sc, dp == &sc->sc_displays[0] ? 0 : 1); 1020 radeonfb_modeswitch(dp); 1021 vcons_redraw_screen(dp->rd_vd.active); 1022 } 1023 } 1024 return 0; 1025 1026 case WSDISPLAYIO_GCURMAX: 1027 ((struct wsdisplay_curpos *)d)->x = RADEON_CURSORMAXX; 1028 ((struct wsdisplay_curpos *)d)->y = RADEON_CURSORMAXY; 1029 return 0; 1030 1031 case WSDISPLAYIO_SCURSOR: 1032 return radeonfb_set_cursor(dp, (struct wsdisplay_cursor *)d); 1033 1034 case WSDISPLAYIO_GCURSOR: 1035 return EPASSTHROUGH; 1036 1037 case WSDISPLAYIO_GCURPOS: 1038 ((struct wsdisplay_curpos *)d)->x = dp->rd_cursor.rc_pos.x; 1039 ((struct wsdisplay_curpos *)d)->y = dp->rd_cursor.rc_pos.y; 1040 return 0; 1041 1042 case WSDISPLAYIO_SCURPOS: 1043 return radeonfb_set_curpos(dp, (struct wsdisplay_curpos *)d); 1044 1045 case WSDISPLAYIO_SSPLASH: 1046 #if defined(SPLASHSCREEN) 1047 if (*(int *)d == 1) { 1048 SCREEN_DISABLE_DRAWING(&dp->rd_vscreen); 1049 splash_render(&dp->rd_splash, 1050 SPLASH_F_CENTER|SPLASH_F_FILL); 1051 } else 1052 SCREEN_ENABLE_DRAWING(&dp->rd_vscreen); 1053 return 0; 1054 #else 1055 return ENODEV; 1056 #endif 1057 case WSDISPLAYIO_GETPARAM: 1058 param = (struct wsdisplay_param *)d; 1059 if (param->param == WSDISPLAYIO_PARAM_BACKLIGHT) { 1060 param->min = 0; 1061 param->max = RADEONFB_BACKLIGHT_MAX; 1062 param->curval = radeonfb_get_backlight(dp); 1063 return 0; 1064 } 1065 return EPASSTHROUGH; 1066 1067 case WSDISPLAYIO_SETPARAM: 1068 param = (struct wsdisplay_param *)d; 1069 if (param->param == WSDISPLAYIO_PARAM_BACKLIGHT) { 1070 return radeonfb_set_backlight(dp, param->curval); 1071 } 1072 return EPASSTHROUGH; 1073 1074 /* PCI config read/write passthrough. */ 1075 case PCI_IOC_CFGREAD: 1076 case PCI_IOC_CFGWRITE: 1077 return pci_devioctl(sc->sc_pc, sc->sc_pt, cmd, d, flag, l); 1078 1079 case WSDISPLAYIO_GET_BUSID: 1080 return wsdisplayio_busid_pci(&sc->sc_dev, sc->sc_pc, 1081 sc->sc_pt, d); 1082 1083 default: 1084 return EPASSTHROUGH; 1085 } 1086 } 1087 1088 paddr_t 1089 radeonfb_mmap(void *v, void *vs, off_t offset, int prot) 1090 { 1091 struct vcons_data *vd; 1092 struct radeonfb_display *dp; 1093 struct radeonfb_softc *sc; 1094 paddr_t pa; 1095 1096 vd = (struct vcons_data *)v; 1097 dp = (struct radeonfb_display *)vd->cookie; 1098 sc = dp->rd_softc; 1099 1100 /* XXX: note that we don't allow mapping of registers right now */ 1101 /* XXX: this means that the XFree86 radeon driver won't work */ 1102 if ((offset >= 0) && (offset < (dp->rd_virty * dp->rd_stride))) { 1103 pa = bus_space_mmap(sc->sc_memt, 1104 sc->sc_memaddr + dp->rd_offset + offset, 0, 1105 prot, BUS_SPACE_MAP_LINEAR); 1106 return pa; 1107 } 1108 1109 #ifdef RADEONFB_MMAP_BARS 1110 /* 1111 * restrict all other mappings to processes with superuser privileges 1112 * or the kernel itself 1113 */ 1114 if (kauth_authorize_generic(kauth_cred_get(), KAUTH_GENERIC_ISSUSER, 1115 NULL) != 0) { 1116 aprint_error_dev(&sc->sc_dev, "mmap() rejected.\n"); 1117 return -1; 1118 } 1119 1120 if ((offset >= sc->sc_regaddr) && 1121 (offset < sc->sc_regaddr + sc->sc_regsz)) { 1122 return bus_space_mmap(sc->sc_regt, offset, 0, prot, 1123 BUS_SPACE_MAP_LINEAR); 1124 } 1125 1126 if ((offset >= sc->sc_memaddr) && 1127 (offset < sc->sc_memaddr + sc->sc_memsz)) { 1128 return bus_space_mmap(sc->sc_memt, offset, 0, prot, 1129 BUS_SPACE_MAP_LINEAR); 1130 } 1131 1132 if ((offset >= sc->sc_romaddr) && 1133 (offset < sc->sc_romaddr + sc->sc_romsz)) { 1134 return bus_space_mmap(sc->sc_memt, offset, 0, prot, 1135 BUS_SPACE_MAP_LINEAR); 1136 } 1137 1138 #ifdef PCI_MAGIC_IO_RANGE 1139 /* allow mapping of IO space */ 1140 if ((offset >= PCI_MAGIC_IO_RANGE) && 1141 (offset < PCI_MAGIC_IO_RANGE + 0x10000)) { 1142 pa = bus_space_mmap(sc->sc_iot, offset - PCI_MAGIC_IO_RANGE, 1143 0, prot, 0); 1144 return pa; 1145 } 1146 #endif /* macppc */ 1147 1148 #endif /* RADEONFB_MMAP_BARS */ 1149 1150 return -1; 1151 } 1152 1153 static void 1154 radeonfb_loadbios(struct radeonfb_softc *sc, struct pci_attach_args *pa) 1155 { 1156 bus_space_tag_t romt; 1157 bus_space_handle_t romh, biosh; 1158 bus_size_t romsz; 1159 bus_addr_t ptr; 1160 1161 if (pci_mapreg_map(pa, PCI_MAPREG_ROM, PCI_MAPREG_TYPE_ROM, 1162 BUS_SPACE_MAP_PREFETCHABLE, &romt, &romh, NULL, &romsz) != 0) { 1163 aprint_verbose("%s: unable to map BIOS!\n", XNAME(sc)); 1164 return; 1165 } 1166 1167 pci_find_rom(pa, romt, romh, PCI_ROM_CODE_TYPE_X86, &biosh, 1168 &sc->sc_biossz); 1169 if (sc->sc_biossz == 0) { 1170 aprint_verbose("%s: Video BIOS not present\n", XNAME(sc)); 1171 return; 1172 } 1173 1174 sc->sc_bios = malloc(sc->sc_biossz, M_DEVBUF, M_WAITOK); 1175 bus_space_read_region_1(romt, biosh, 0, sc->sc_bios, sc->sc_biossz); 1176 1177 /* unmap the PCI expansion rom */ 1178 bus_space_unmap(romt, romh, romsz); 1179 1180 /* turn off rom decoder now */ 1181 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM, 1182 pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM) & 1183 ~PCI_MAPREG_ROM_ENABLE); 1184 1185 ptr = GETBIOS16(sc, 0x48); 1186 if ((GETBIOS32(sc, ptr + 4) == 0x41544f4d /* "ATOM" */) || 1187 (GETBIOS32(sc, ptr + 4) == 0x4d4f5441 /* "MOTA" */)) { 1188 sc->sc_flags |= RFB_ATOM; 1189 } 1190 1191 aprint_verbose("%s: Found %d KB %s BIOS\n", XNAME(sc), 1192 (unsigned)sc->sc_biossz >> 10, IS_ATOM(sc) ? "ATOM" : "Legacy"); 1193 } 1194 1195 1196 uint32_t 1197 radeonfb_get32(struct radeonfb_softc *sc, uint32_t reg) 1198 { 1199 1200 return bus_space_read_4(sc->sc_regt, sc->sc_regh, reg); 1201 } 1202 1203 void 1204 radeonfb_put32(struct radeonfb_softc *sc, uint32_t reg, uint32_t val) 1205 { 1206 1207 bus_space_write_4(sc->sc_regt, sc->sc_regh, reg, val); 1208 } 1209 1210 void 1211 radeonfb_mask32(struct radeonfb_softc *sc, uint32_t reg, 1212 uint32_t andmask, uint32_t ormask) 1213 { 1214 int s; 1215 uint32_t val; 1216 1217 s = splhigh(); 1218 val = radeonfb_get32(sc, reg); 1219 val = (val & andmask) | ormask; 1220 radeonfb_put32(sc, reg, val); 1221 splx(s); 1222 } 1223 1224 uint32_t 1225 radeonfb_getindex(struct radeonfb_softc *sc, uint32_t idx) 1226 { 1227 int s; 1228 uint32_t val; 1229 1230 s = splhigh(); 1231 radeonfb_put32(sc, RADEON_MM_INDEX, idx); 1232 val = radeonfb_get32(sc, RADEON_MM_DATA); 1233 splx(s); 1234 1235 return (val); 1236 } 1237 1238 void 1239 radeonfb_putindex(struct radeonfb_softc *sc, uint32_t idx, uint32_t val) 1240 { 1241 int s; 1242 1243 s = splhigh(); 1244 radeonfb_put32(sc, RADEON_MM_INDEX, idx); 1245 radeonfb_put32(sc, RADEON_MM_DATA, val); 1246 splx(s); 1247 } 1248 1249 void 1250 radeonfb_maskindex(struct radeonfb_softc *sc, uint32_t idx, 1251 uint32_t andmask, uint32_t ormask) 1252 { 1253 int s; 1254 uint32_t val; 1255 1256 s = splhigh(); 1257 radeonfb_put32(sc, RADEON_MM_INDEX, idx); 1258 val = radeonfb_get32(sc, RADEON_MM_DATA); 1259 val = (val & andmask) | ormask; 1260 radeonfb_put32(sc, RADEON_MM_DATA, val); 1261 splx(s); 1262 } 1263 1264 uint32_t 1265 radeonfb_getpll(struct radeonfb_softc *sc, uint32_t idx) 1266 { 1267 int s; 1268 uint32_t val; 1269 1270 s = splhigh(); 1271 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, idx & 0x3f); 1272 val = radeonfb_get32(sc, RADEON_CLOCK_CNTL_DATA); 1273 if (HAS_R300CG(sc)) 1274 radeonfb_r300cg_workaround(sc); 1275 splx(s); 1276 1277 return (val); 1278 } 1279 1280 void 1281 radeonfb_putpll(struct radeonfb_softc *sc, uint32_t idx, uint32_t val) 1282 { 1283 int s; 1284 1285 s = splhigh(); 1286 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, (idx & 0x3f) | 1287 RADEON_PLL_WR_EN); 1288 radeonfb_put32(sc, RADEON_CLOCK_CNTL_DATA, val); 1289 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, 0); 1290 splx(s); 1291 } 1292 1293 void 1294 radeonfb_maskpll(struct radeonfb_softc *sc, uint32_t idx, 1295 uint32_t andmask, uint32_t ormask) 1296 { 1297 int s; 1298 uint32_t val; 1299 1300 s = splhigh(); 1301 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, (idx & 0x3f) | 1302 RADEON_PLL_WR_EN); 1303 val = radeonfb_get32(sc, RADEON_CLOCK_CNTL_DATA); 1304 val = (val & andmask) | ormask; 1305 radeonfb_put32(sc, RADEON_CLOCK_CNTL_DATA, val); 1306 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, 0); 1307 splx(s); 1308 } 1309 1310 int 1311 radeonfb_scratch_test(struct radeonfb_softc *sc, int reg, uint32_t v) 1312 { 1313 uint32_t saved; 1314 1315 saved = GET32(sc, reg); 1316 PUT32(sc, reg, v); 1317 if (GET32(sc, reg) != v) { 1318 return -1; 1319 } 1320 PUT32(sc, reg, saved); 1321 return 0; 1322 } 1323 1324 uintmax_t 1325 radeonfb_getprop_num(struct radeonfb_softc *sc, const char *name, 1326 uintmax_t defval) 1327 { 1328 prop_number_t pn; 1329 pn = prop_dictionary_get(device_properties(&sc->sc_dev), name); 1330 if (pn == NULL) { 1331 return defval; 1332 } 1333 KASSERT(prop_object_type(pn) == PROP_TYPE_NUMBER); 1334 return (prop_number_integer_value(pn)); 1335 } 1336 1337 int 1338 radeonfb_getclocks(struct radeonfb_softc *sc) 1339 { 1340 bus_addr_t ptr; 1341 int refclk = 0; 1342 int refdiv = 0; 1343 int minpll = 0; 1344 int maxpll = 0; 1345 1346 /* load initial property values if port/board provides them */ 1347 refclk = radeonfb_getprop_num(sc, "refclk", 0) & 0xffff; 1348 refdiv = radeonfb_getprop_num(sc, "refdiv", 0) & 0xffff; 1349 minpll = radeonfb_getprop_num(sc, "minpll", 0) & 0xffffffffU; 1350 maxpll = radeonfb_getprop_num(sc, "maxpll", 0) & 0xffffffffU; 1351 1352 if (refclk && refdiv && minpll && maxpll) 1353 goto dontprobe; 1354 1355 if (!sc->sc_biossz) { 1356 /* no BIOS */ 1357 aprint_verbose("%s: No video BIOS, using default clocks\n", 1358 XNAME(sc)); 1359 if (IS_IGP(sc)) 1360 refclk = refclk ? refclk : 1432; 1361 else 1362 refclk = refclk ? refclk : 2700; 1363 refdiv = refdiv ? refdiv : 12; 1364 minpll = minpll ? minpll : 12500; 1365 maxpll = maxpll ? maxpll : 35000; 1366 } else if (IS_ATOM(sc)) { 1367 /* ATOM BIOS */ 1368 ptr = GETBIOS16(sc, 0x48); 1369 ptr = GETBIOS16(sc, ptr + 32); /* aka MasterDataStart */ 1370 ptr = GETBIOS16(sc, ptr + 12); /* pll info block */ 1371 refclk = refclk ? refclk : GETBIOS16(sc, ptr + 82); 1372 minpll = minpll ? minpll : GETBIOS16(sc, ptr + 78); 1373 maxpll = maxpll ? maxpll : GETBIOS16(sc, ptr + 32); 1374 /* 1375 * ATOM BIOS doesn't supply a reference divider, so we 1376 * have to probe for it. 1377 */ 1378 if (refdiv < 2) 1379 refdiv = GETPLL(sc, RADEON_PPLL_REF_DIV) & 1380 RADEON_PPLL_REF_DIV_MASK; 1381 /* 1382 * if probe is zero, just assume one that should work 1383 * for most parts 1384 */ 1385 if (refdiv < 2) 1386 refdiv = 12; 1387 1388 } else { 1389 /* Legacy BIOS */ 1390 ptr = GETBIOS16(sc, 0x48); 1391 ptr = GETBIOS16(sc, ptr + 0x30); 1392 refclk = refclk ? refclk : GETBIOS16(sc, ptr + 0x0E); 1393 refdiv = refdiv ? refdiv : GETBIOS16(sc, ptr + 0x10); 1394 minpll = minpll ? minpll : GETBIOS32(sc, ptr + 0x12); 1395 maxpll = maxpll ? maxpll : GETBIOS32(sc, ptr + 0x16); 1396 } 1397 1398 1399 dontprobe: 1400 sc->sc_refclk = refclk * 10; 1401 sc->sc_refdiv = refdiv; 1402 sc->sc_minpll = minpll * 10; 1403 sc->sc_maxpll = maxpll * 10; 1404 return 0; 1405 } 1406 1407 int 1408 radeonfb_calc_dividers(struct radeonfb_softc *sc, uint32_t dotclock, 1409 uint32_t *postdivbit, uint32_t *feedbackdiv) 1410 { 1411 int i; 1412 uint32_t outfreq; 1413 int div; 1414 1415 DPRINTF(("dot clock: %u\n", dotclock)); 1416 for (i = 0; (div = radeonfb_dividers[i].divider) != 0; i++) { 1417 outfreq = div * dotclock; 1418 if ((outfreq >= sc->sc_minpll) && 1419 (outfreq <= sc->sc_maxpll)) { 1420 DPRINTF(("outfreq: %u\n", outfreq)); 1421 *postdivbit = 1422 ((uint32_t)radeonfb_dividers[i].mask << 16); 1423 DPRINTF(("post divider: %d (mask %x)\n", div, 1424 *postdivbit)); 1425 break; 1426 } 1427 } 1428 1429 if (div == 0) 1430 return 1; 1431 1432 *feedbackdiv = DIVIDE(sc->sc_refdiv * outfreq, sc->sc_refclk); 1433 DPRINTF(("feedback divider: %d\n", *feedbackdiv)); 1434 return 0; 1435 } 1436 1437 #if 0 1438 #ifdef RADEONFB_DEBUG 1439 static void 1440 dump_buffer(const char *pfx, void *buffer, unsigned int size) 1441 { 1442 char asc[17]; 1443 unsigned ptr = (unsigned)buffer; 1444 char *start = (char *)(ptr & ~0xf); 1445 char *end = (char *)(ptr + size); 1446 1447 end = (char *)(((unsigned)end + 0xf) & ~0xf); 1448 1449 if (pfx == NULL) { 1450 pfx = ""; 1451 } 1452 1453 while (start < end) { 1454 unsigned offset = (unsigned)start & 0xf; 1455 if (offset == 0) { 1456 printf("%s%x: ", pfx, (unsigned)start); 1457 } 1458 if (((unsigned)start < ptr) || 1459 ((unsigned)start >= (ptr + size))) { 1460 printf(" "); 1461 asc[offset] = ' '; 1462 } else { 1463 printf("%02x", *(unsigned char *)start); 1464 if ((*start >= ' ') && (*start <= '~')) { 1465 asc[offset] = *start; 1466 } else { 1467 asc[offset] = '.'; 1468 } 1469 } 1470 asc[offset + 1] = 0; 1471 if (offset % 2) { 1472 printf(" "); 1473 } 1474 if (offset == 15) { 1475 printf(" %s\n", asc); 1476 } 1477 start++; 1478 } 1479 } 1480 #endif 1481 #endif 1482 1483 int 1484 radeonfb_getconnectors(struct radeonfb_softc *sc) 1485 { 1486 int i; 1487 int found = 0; 1488 1489 for (i = 0; i < 2; i++) { 1490 sc->sc_ports[i].rp_mon_type = RADEON_MT_UNKNOWN; 1491 sc->sc_ports[i].rp_ddc_type = RADEON_DDC_NONE; 1492 sc->sc_ports[i].rp_dac_type = RADEON_DAC_UNKNOWN; 1493 sc->sc_ports[i].rp_conn_type = RADEON_CONN_NONE; 1494 sc->sc_ports[i].rp_tmds_type = RADEON_TMDS_UNKNOWN; 1495 } 1496 1497 /* 1498 * This logic is borrowed from Xorg's radeon driver. 1499 */ 1500 if (!sc->sc_biossz) 1501 goto nobios; 1502 1503 if (IS_ATOM(sc)) { 1504 /* not done yet */ 1505 } else { 1506 uint16_t ptr; 1507 int port = 0; 1508 1509 ptr = GETBIOS16(sc, 0x48); 1510 ptr = GETBIOS16(sc, ptr + 0x50); 1511 for (i = 1; i < 4; i++) { 1512 uint16_t entry; 1513 uint8_t conn, ddc, dac, tmds; 1514 1515 /* 1516 * Parse the connector table. From reading the code, 1517 * it appears to made up of 16-bit entries for each 1518 * connector. The 16-bits are defined as: 1519 * 1520 * bits 12-15 - connector type (0 == end of table) 1521 * bits 8-11 - DDC type 1522 * bits 5-7 - ??? 1523 * bit 4 - TMDS type (1 = EXT, 0 = INT) 1524 * bits 1-3 - ??? 1525 * bit 0 - DAC, 1 = TVDAC, 0 = primary 1526 */ 1527 if (!GETBIOS8(sc, ptr + i * 2) && i > 1) 1528 break; 1529 entry = GETBIOS16(sc, ptr + i * 2); 1530 1531 conn = (entry >> 12) & 0xf; 1532 ddc = (entry >> 8) & 0xf; 1533 dac = (entry & 0x1) ? RADEON_DAC_TVDAC : 1534 RADEON_DAC_PRIMARY; 1535 tmds = ((entry >> 4) & 0x1) ? RADEON_TMDS_EXT : 1536 RADEON_TMDS_INT; 1537 1538 if (conn == RADEON_CONN_NONE) 1539 continue; /* no connector */ 1540 1541 if ((found > 0) && 1542 (sc->sc_ports[port].rp_ddc_type == ddc)) { 1543 /* duplicate entry for same connector */ 1544 continue; 1545 } 1546 1547 /* internal DDC_DVI port gets priority */ 1548 if ((ddc == RADEON_DDC_DVI) || (port == 1)) 1549 port = 0; 1550 else 1551 port = 1; 1552 1553 sc->sc_ports[port].rp_ddc_type = 1554 ddc > RADEON_DDC_CRT2 ? RADEON_DDC_NONE : ddc; 1555 sc->sc_ports[port].rp_dac_type = dac; 1556 sc->sc_ports[port].rp_conn_type = 1557 min(conn, RADEON_CONN_UNSUPPORTED) ; 1558 1559 sc->sc_ports[port].rp_tmds_type = tmds; 1560 1561 if ((conn != RADEON_CONN_DVI_I) && 1562 (conn != RADEON_CONN_DVI_D) && 1563 (tmds == RADEON_TMDS_INT)) 1564 sc->sc_ports[port].rp_tmds_type = 1565 RADEON_TMDS_UNKNOWN; 1566 1567 found += (port + 1); 1568 } 1569 } 1570 1571 nobios: 1572 if (!found) { 1573 DPRINTF(("No connector info in BIOS!\n")); 1574 /* default, port 0 = internal TMDS, port 1 = CRT */ 1575 sc->sc_ports[0].rp_mon_type = RADEON_MT_UNKNOWN; 1576 sc->sc_ports[0].rp_ddc_type = RADEON_DDC_DVI; 1577 sc->sc_ports[0].rp_dac_type = RADEON_DAC_TVDAC; 1578 sc->sc_ports[0].rp_conn_type = RADEON_CONN_DVI_D; 1579 sc->sc_ports[0].rp_tmds_type = RADEON_TMDS_INT; 1580 1581 sc->sc_ports[1].rp_mon_type = RADEON_MT_UNKNOWN; 1582 sc->sc_ports[1].rp_ddc_type = RADEON_DDC_VGA; 1583 sc->sc_ports[1].rp_dac_type = RADEON_DAC_PRIMARY; 1584 sc->sc_ports[1].rp_conn_type = RADEON_CONN_CRT; 1585 sc->sc_ports[1].rp_tmds_type = RADEON_TMDS_EXT; 1586 } 1587 1588 /* 1589 * Fixup for RS300/RS350/RS400 chips, that lack a primary DAC. 1590 * these chips should use TVDAC for the VGA port. 1591 */ 1592 if (HAS_SDAC(sc)) { 1593 if (sc->sc_ports[0].rp_conn_type == RADEON_CONN_CRT) { 1594 sc->sc_ports[0].rp_dac_type = RADEON_DAC_TVDAC; 1595 sc->sc_ports[1].rp_dac_type = RADEON_DAC_PRIMARY; 1596 } else { 1597 sc->sc_ports[1].rp_dac_type = RADEON_DAC_TVDAC; 1598 sc->sc_ports[0].rp_dac_type = RADEON_DAC_PRIMARY; 1599 } 1600 } else if (!HAS_CRTC2(sc)) { 1601 sc->sc_ports[0].rp_dac_type = RADEON_DAC_PRIMARY; 1602 } 1603 1604 for (i = 0; i < 2; i++) { 1605 char edid[128]; 1606 uint8_t ddc; 1607 struct edid_info *eip = &sc->sc_ports[i].rp_edid; 1608 prop_data_t edid_data; 1609 1610 DPRINTF(("Port #%d:\n", i)); 1611 DPRINTF((" conn = %d\n", sc->sc_ports[i].rp_conn_type)); 1612 DPRINTF((" ddc = %d\n", sc->sc_ports[i].rp_ddc_type)); 1613 DPRINTF((" dac = %d\n", sc->sc_ports[i].rp_dac_type)); 1614 DPRINTF((" tmds = %d\n", sc->sc_ports[i].rp_tmds_type)); 1615 1616 sc->sc_ports[i].rp_edid_valid = 0; 1617 /* first look for static EDID data */ 1618 if ((edid_data = prop_dictionary_get(device_properties( 1619 &sc->sc_dev), "EDID")) != NULL) { 1620 1621 aprint_normal_dev(&sc->sc_dev, "using static EDID\n"); 1622 memcpy(edid, prop_data_data_nocopy(edid_data), 128); 1623 if (edid_parse(edid, eip) == 0) { 1624 1625 sc->sc_ports[i].rp_edid_valid = 1; 1626 } 1627 } 1628 /* if we didn't find any we'll try to talk to the monitor */ 1629 if (sc->sc_ports[i].rp_edid_valid != 1) { 1630 1631 ddc = sc->sc_ports[i].rp_ddc_type; 1632 if (ddc != RADEON_DDC_NONE) { 1633 if ((radeonfb_i2c_read_edid(sc, ddc, edid) 1634 == 0) && (edid_parse(edid, eip) == 0)) { 1635 1636 sc->sc_ports[i].rp_edid_valid = 1; 1637 edid_print(eip); 1638 } 1639 } 1640 } 1641 } 1642 1643 return found; 1644 } 1645 1646 int 1647 radeonfb_gettmds(struct radeonfb_softc *sc) 1648 { 1649 int i; 1650 1651 if (!sc->sc_biossz) { 1652 goto nobios; 1653 } 1654 1655 if (IS_ATOM(sc)) { 1656 /* XXX: not done yet */ 1657 } else { 1658 uint16_t ptr; 1659 int n; 1660 1661 ptr = GETBIOS16(sc, 0x48); 1662 ptr = GETBIOS16(sc, ptr + 0x34); 1663 DPRINTF(("DFP table revision %d\n", GETBIOS8(sc, ptr))); 1664 if (GETBIOS8(sc, ptr) == 3) { 1665 /* revision three table */ 1666 n = GETBIOS8(sc, ptr + 5) + 1; 1667 n = min(n, 4); 1668 1669 memset(sc->sc_tmds_pll, 0, sizeof (sc->sc_tmds_pll)); 1670 for (i = 0; i < n; i++) { 1671 sc->sc_tmds_pll[i].rtp_pll = GETBIOS32(sc, 1672 ptr + i * 10 + 8); 1673 sc->sc_tmds_pll[i].rtp_freq = GETBIOS16(sc, 1674 ptr + i * 10 + 0x10); 1675 DPRINTF(("TMDS_PLL dot clock %d pll %x\n", 1676 sc->sc_tmds_pll[i].rtp_freq, 1677 sc->sc_tmds_pll[i].rtp_pll)); 1678 } 1679 return 0; 1680 } 1681 } 1682 1683 nobios: 1684 DPRINTF(("no suitable DFP table present\n")); 1685 for (i = 0; 1686 i < sizeof (radeonfb_tmds_pll) / sizeof (radeonfb_tmds_pll[0]); 1687 i++) { 1688 int j; 1689 1690 if (radeonfb_tmds_pll[i].family != sc->sc_family) 1691 continue; 1692 1693 for (j = 0; j < 4; j++) { 1694 sc->sc_tmds_pll[j] = radeonfb_tmds_pll[i].plls[j]; 1695 DPRINTF(("TMDS_PLL dot clock %d pll %x\n", 1696 sc->sc_tmds_pll[j].rtp_freq, 1697 sc->sc_tmds_pll[j].rtp_pll)); 1698 } 1699 return 0; 1700 } 1701 1702 return -1; 1703 } 1704 1705 const struct videomode * 1706 radeonfb_modelookup(const char *name) 1707 { 1708 int i; 1709 1710 for (i = 0; i < videomode_count; i++) 1711 if (!strcmp(name, videomode_list[i].name)) 1712 return &videomode_list[i]; 1713 1714 return NULL; 1715 } 1716 1717 void 1718 radeonfb_pllwriteupdate(struct radeonfb_softc *sc, int crtc) 1719 { 1720 if (crtc) { 1721 while (GETPLL(sc, RADEON_P2PLL_REF_DIV) & 1722 RADEON_P2PLL_ATOMIC_UPDATE_R); 1723 SETPLL(sc, RADEON_P2PLL_REF_DIV, RADEON_P2PLL_ATOMIC_UPDATE_W); 1724 } else { 1725 while (GETPLL(sc, RADEON_PPLL_REF_DIV) & 1726 RADEON_PPLL_ATOMIC_UPDATE_R); 1727 SETPLL(sc, RADEON_PPLL_REF_DIV, RADEON_PPLL_ATOMIC_UPDATE_W); 1728 } 1729 } 1730 1731 void 1732 radeonfb_pllwaitatomicread(struct radeonfb_softc *sc, int crtc) 1733 { 1734 int i; 1735 1736 for (i = 10000; i; i--) { 1737 if (crtc) { 1738 if (GETPLL(sc, RADEON_P2PLL_REF_DIV) & 1739 RADEON_P2PLL_ATOMIC_UPDATE_R) 1740 break; 1741 } else { 1742 if (GETPLL(sc, RADEON_PPLL_REF_DIV) & 1743 RADEON_PPLL_ATOMIC_UPDATE_R) 1744 break; 1745 } 1746 } 1747 } 1748 1749 void 1750 radeonfb_program_vclk(struct radeonfb_softc *sc, int dotclock, int crtc) 1751 { 1752 uint32_t pbit = 0; 1753 uint32_t feed = 0; 1754 uint32_t data; 1755 #if 1 1756 int i; 1757 #endif 1758 1759 radeonfb_calc_dividers(sc, dotclock, &pbit, &feed); 1760 1761 if (crtc == 0) { 1762 1763 /* XXXX: mobility workaround missing */ 1764 /* XXXX: R300 stuff missing */ 1765 1766 PATCHPLL(sc, RADEON_VCLK_ECP_CNTL, 1767 RADEON_VCLK_SRC_SEL_CPUCLK, 1768 ~RADEON_VCLK_SRC_SEL_MASK); 1769 1770 /* put vclk into reset, use atomic updates */ 1771 SETPLL(sc, RADEON_PPLL_CNTL, 1772 RADEON_PPLL_REFCLK_SEL | 1773 RADEON_PPLL_FBCLK_SEL | 1774 RADEON_PPLL_RESET | 1775 RADEON_PPLL_ATOMIC_UPDATE_EN | 1776 RADEON_PPLL_VGA_ATOMIC_UPDATE_EN); 1777 1778 /* select clock 3 */ 1779 #if 0 1780 PATCH32(sc, RADEON_CLOCK_CNTL_INDEX, RADEON_PLL_DIV_SEL, 1781 ~RADEON_PLL_DIV_SEL); 1782 #else 1783 PATCH32(sc, RADEON_CLOCK_CNTL_INDEX, 0, 1784 ~RADEON_PLL_DIV_SEL); 1785 #endif 1786 1787 /* XXX: R300 family -- program divider differently? */ 1788 1789 /* program reference divider */ 1790 PATCHPLL(sc, RADEON_PPLL_REF_DIV, sc->sc_refdiv, 1791 ~RADEON_PPLL_REF_DIV_MASK); 1792 PRINTPLL(RADEON_PPLL_REF_DIV); 1793 1794 #if 0 1795 data = GETPLL(sc, RADEON_PPLL_DIV_3); 1796 data &= ~(RADEON_PPLL_FB3_DIV_MASK | 1797 RADEON_PPLL_POST3_DIV_MASK); 1798 data |= pbit; 1799 data |= (feed & RADEON_PPLL_FB3_DIV_MASK); 1800 PUTPLL(sc, RADEON_PPLL_DIV_3, data); 1801 #else 1802 for (i = 0; i < 4; i++) { 1803 } 1804 #endif 1805 1806 /* use the atomic update */ 1807 radeonfb_pllwriteupdate(sc, crtc); 1808 1809 /* and wait for it to complete */ 1810 radeonfb_pllwaitatomicread(sc, crtc); 1811 1812 /* program HTOTAL (why?) */ 1813 PUTPLL(sc, RADEON_HTOTAL_CNTL, 0); 1814 1815 /* drop reset */ 1816 CLRPLL(sc, RADEON_PPLL_CNTL, 1817 RADEON_PPLL_RESET | RADEON_PPLL_SLEEP | 1818 RADEON_PPLL_ATOMIC_UPDATE_EN | 1819 RADEON_PPLL_VGA_ATOMIC_UPDATE_EN); 1820 1821 PRINTPLL(RADEON_PPLL_CNTL); 1822 1823 /* give clock time to lock */ 1824 delay(50000); 1825 1826 PATCHPLL(sc, RADEON_VCLK_ECP_CNTL, 1827 RADEON_VCLK_SRC_SEL_PPLLCLK, 1828 ~RADEON_VCLK_SRC_SEL_MASK); 1829 1830 } else { 1831 1832 PATCHPLL(sc, RADEON_PIXCLKS_CNTL, 1833 RADEON_PIX2CLK_SRC_SEL_CPUCLK, 1834 ~RADEON_PIX2CLK_SRC_SEL_MASK); 1835 1836 /* put vclk into reset, use atomic updates */ 1837 SETPLL(sc, RADEON_P2PLL_CNTL, 1838 RADEON_P2PLL_RESET | 1839 RADEON_P2PLL_ATOMIC_UPDATE_EN | 1840 RADEON_P2PLL_VGA_ATOMIC_UPDATE_EN); 1841 1842 /* XXX: R300 family -- program divider differently? */ 1843 1844 /* program reference divider */ 1845 PATCHPLL(sc, RADEON_P2PLL_REF_DIV, sc->sc_refdiv, 1846 ~RADEON_P2PLL_REF_DIV_MASK); 1847 1848 /* program feedback and post dividers */ 1849 data = GETPLL(sc, RADEON_P2PLL_DIV_0); 1850 data &= ~(RADEON_P2PLL_FB0_DIV_MASK | 1851 RADEON_P2PLL_POST0_DIV_MASK); 1852 data |= pbit; 1853 data |= (feed & RADEON_P2PLL_FB0_DIV_MASK); 1854 PUTPLL(sc, RADEON_P2PLL_DIV_0, data); 1855 1856 /* use the atomic update */ 1857 radeonfb_pllwriteupdate(sc, crtc); 1858 1859 /* and wait for it to complete */ 1860 radeonfb_pllwaitatomicread(sc, crtc); 1861 1862 /* program HTOTAL (why?) */ 1863 PUTPLL(sc, RADEON_HTOTAL2_CNTL, 0); 1864 1865 /* drop reset */ 1866 CLRPLL(sc, RADEON_P2PLL_CNTL, 1867 RADEON_P2PLL_RESET | RADEON_P2PLL_SLEEP | 1868 RADEON_P2PLL_ATOMIC_UPDATE_EN | 1869 RADEON_P2PLL_VGA_ATOMIC_UPDATE_EN); 1870 1871 /* allow time for clock to lock */ 1872 delay(50000); 1873 1874 PATCHPLL(sc, RADEON_PIXCLKS_CNTL, 1875 RADEON_PIX2CLK_SRC_SEL_P2PLLCLK, 1876 ~RADEON_PIX2CLK_SRC_SEL_MASK); 1877 } 1878 PRINTREG(RADEON_CRTC_MORE_CNTL); 1879 } 1880 1881 void 1882 radeonfb_modeswitch(struct radeonfb_display *dp) 1883 { 1884 struct radeonfb_softc *sc = dp->rd_softc; 1885 int i; 1886 1887 /* blank the display while we switch modes */ 1888 radeonfb_blank(dp, 1); 1889 1890 #if 0 1891 SET32(sc, RADEON_CRTC_EXT_CNTL, 1892 RADEON_CRTC_VSYNC_DIS | RADEON_CRTC_HSYNC_DIS | 1893 RADEON_CRTC_DISPLAY_DIS /* | RADEON_CRTC_DISP_REQ_EN_B */); 1894 #endif 1895 1896 /* these registers might get in the way... */ 1897 PUT32(sc, RADEON_OVR_CLR, 0); 1898 PUT32(sc, RADEON_OVR_WID_LEFT_RIGHT, 0); 1899 PUT32(sc, RADEON_OVR_WID_TOP_BOTTOM, 0); 1900 PUT32(sc, RADEON_OV0_SCALE_CNTL, 0); 1901 PUT32(sc, RADEON_SUBPIC_CNTL, 0); 1902 PUT32(sc, RADEON_VIPH_CONTROL, 0); 1903 PUT32(sc, RADEON_I2C_CNTL_1, 0); 1904 PUT32(sc, RADEON_GEN_INT_CNTL, 0); 1905 PUT32(sc, RADEON_CAP0_TRIG_CNTL, 0); 1906 PUT32(sc, RADEON_CAP1_TRIG_CNTL, 0); 1907 PUT32(sc, RADEON_SURFACE_CNTL, 0); 1908 1909 for (i = 0; i < dp->rd_ncrtcs; i++) 1910 radeonfb_setcrtc(dp, i); 1911 1912 /* activate the display */ 1913 radeonfb_blank(dp, 0); 1914 } 1915 1916 void 1917 radeonfb_setcrtc(struct radeonfb_display *dp, int index) 1918 { 1919 int crtc; 1920 struct videomode *mode; 1921 struct radeonfb_softc *sc; 1922 struct radeonfb_crtc *cp; 1923 uint32_t v; 1924 uint32_t gencntl; 1925 uint32_t htotaldisp; 1926 uint32_t hsyncstrt; 1927 uint32_t vtotaldisp; 1928 uint32_t vsyncstrt; 1929 uint32_t fphsyncstrt; 1930 uint32_t fpvsyncstrt; 1931 uint32_t fphtotaldisp; 1932 uint32_t fpvtotaldisp; 1933 uint32_t pitch; 1934 1935 sc = dp->rd_softc; 1936 cp = &dp->rd_crtcs[index]; 1937 crtc = cp->rc_number; 1938 mode = &cp->rc_videomode; 1939 1940 #if 1 1941 pitch = (((dp->rd_virtx * dp->rd_bpp) + ((dp->rd_bpp * 8) - 1)) / 1942 (dp->rd_bpp * 8)); 1943 #else 1944 pitch = (((sc->sc_maxx * sc->sc_maxbpp) + ((sc->sc_maxbpp * 8) - 1)) / 1945 (sc->sc_maxbpp * 8)); 1946 #endif 1947 //pitch = pitch | (pitch << 16); 1948 1949 switch (crtc) { 1950 case 0: 1951 gencntl = RADEON_CRTC_GEN_CNTL; 1952 htotaldisp = RADEON_CRTC_H_TOTAL_DISP; 1953 hsyncstrt = RADEON_CRTC_H_SYNC_STRT_WID; 1954 vtotaldisp = RADEON_CRTC_V_TOTAL_DISP; 1955 vsyncstrt = RADEON_CRTC_V_SYNC_STRT_WID; 1956 fpvsyncstrt = RADEON_FP_V_SYNC_STRT_WID; 1957 fphsyncstrt = RADEON_FP_H_SYNC_STRT_WID; 1958 fpvtotaldisp = RADEON_FP_CRTC_V_TOTAL_DISP; 1959 fphtotaldisp = RADEON_FP_CRTC_H_TOTAL_DISP; 1960 break; 1961 case 1: 1962 gencntl = RADEON_CRTC2_GEN_CNTL; 1963 htotaldisp = RADEON_CRTC2_H_TOTAL_DISP; 1964 hsyncstrt = RADEON_CRTC2_H_SYNC_STRT_WID; 1965 vtotaldisp = RADEON_CRTC2_V_TOTAL_DISP; 1966 vsyncstrt = RADEON_CRTC2_V_SYNC_STRT_WID; 1967 fpvsyncstrt = RADEON_FP_V2_SYNC_STRT_WID; 1968 fphsyncstrt = RADEON_FP_H2_SYNC_STRT_WID; 1969 fpvtotaldisp = RADEON_FP_CRTC2_V_TOTAL_DISP; 1970 fphtotaldisp = RADEON_FP_CRTC2_H_TOTAL_DISP; 1971 break; 1972 default: 1973 panic("Bad CRTC!"); 1974 break; 1975 } 1976 1977 /* 1978 * CRTC_GEN_CNTL - depth, accelerator mode, etc. 1979 */ 1980 /* only bother with 32bpp and 8bpp */ 1981 v = dp->rd_format << RADEON_CRTC_PIX_WIDTH_SHIFT; 1982 1983 if (crtc == 1) { 1984 v |= RADEON_CRTC2_CRT2_ON | RADEON_CRTC2_EN; 1985 } else { 1986 v |= RADEON_CRTC_EXT_DISP_EN | RADEON_CRTC_EN; 1987 } 1988 1989 if (mode->flags & VID_DBLSCAN) 1990 v |= RADEON_CRTC2_DBL_SCAN_EN; 1991 1992 if (mode->flags & VID_INTERLACE) 1993 v |= RADEON_CRTC2_INTERLACE_EN; 1994 1995 if (mode->flags & VID_CSYNC) { 1996 v |= RADEON_CRTC2_CSYNC_EN; 1997 if (crtc == 1) 1998 v |= RADEON_CRTC2_VSYNC_TRISTAT; 1999 } 2000 2001 PUT32(sc, gencntl, v); 2002 DPRINTF(("CRTC%s_GEN_CNTL = %08x\n", crtc ? "2" : "", v)); 2003 2004 /* 2005 * CRTC_EXT_CNTL - preserve disable flags, set ATI linear and EXT_CNT 2006 */ 2007 v = GET32(sc, RADEON_CRTC_EXT_CNTL); 2008 if (crtc == 0) { 2009 v &= (RADEON_CRTC_VSYNC_DIS | RADEON_CRTC_HSYNC_DIS | 2010 RADEON_CRTC_DISPLAY_DIS); 2011 v |= RADEON_XCRT_CNT_EN | RADEON_VGA_ATI_LINEAR; 2012 if (mode->flags & VID_CSYNC) 2013 v |= RADEON_CRTC_VSYNC_TRISTAT; 2014 } 2015 /* unconditional turn on CRT, in case first CRTC is DFP */ 2016 v |= RADEON_CRTC_CRT_ON; 2017 PUT32(sc, RADEON_CRTC_EXT_CNTL, v); 2018 PRINTREG(RADEON_CRTC_EXT_CNTL); 2019 2020 /* 2021 * H_TOTAL_DISP 2022 */ 2023 v = ((mode->hdisplay / 8) - 1) << 16; 2024 v |= (mode->htotal / 8) - 1; 2025 PUT32(sc, htotaldisp, v); 2026 DPRINTF(("CRTC%s_H_TOTAL_DISP = %08x\n", crtc ? "2" : "", v)); 2027 PUT32(sc, fphtotaldisp, v); 2028 DPRINTF(("FP_H%s_TOTAL_DISP = %08x\n", crtc ? "2" : "", v)); 2029 2030 /* 2031 * H_SYNC_STRT_WID 2032 */ 2033 v = (((mode->hsync_end - mode->hsync_start) / 8) << 16); 2034 v |= mode->hsync_start; 2035 if (mode->flags & VID_NHSYNC) 2036 v |= RADEON_CRTC_H_SYNC_POL; 2037 PUT32(sc, hsyncstrt, v); 2038 DPRINTF(("CRTC%s_H_SYNC_STRT_WID = %08x\n", crtc ? "2" : "", v)); 2039 PUT32(sc, fphsyncstrt, v); 2040 DPRINTF(("FP_H%s_SYNC_STRT_WID = %08x\n", crtc ? "2" : "", v)); 2041 2042 /* 2043 * V_TOTAL_DISP 2044 */ 2045 v = ((mode->vdisplay - 1) << 16); 2046 v |= (mode->vtotal - 1); 2047 PUT32(sc, vtotaldisp, v); 2048 DPRINTF(("CRTC%s_V_TOTAL_DISP = %08x\n", crtc ? "2" : "", v)); 2049 PUT32(sc, fpvtotaldisp, v); 2050 DPRINTF(("FP_V%s_TOTAL_DISP = %08x\n", crtc ? "2" : "", v)); 2051 2052 /* 2053 * V_SYNC_STRT_WID 2054 */ 2055 v = ((mode->vsync_end - mode->vsync_start) << 16); 2056 v |= (mode->vsync_start - 1); 2057 if (mode->flags & VID_NVSYNC) 2058 v |= RADEON_CRTC_V_SYNC_POL; 2059 PUT32(sc, vsyncstrt, v); 2060 DPRINTF(("CRTC%s_V_SYNC_STRT_WID = %08x\n", crtc ? "2" : "", v)); 2061 PUT32(sc, fpvsyncstrt, v); 2062 DPRINTF(("FP_V%s_SYNC_STRT_WID = %08x\n", crtc ? "2" : "", v)); 2063 2064 radeonfb_program_vclk(sc, mode->dot_clock, crtc); 2065 2066 switch (crtc) { 2067 case 0: 2068 PUT32(sc, RADEON_CRTC_OFFSET, 0); 2069 PUT32(sc, RADEON_CRTC_OFFSET_CNTL, 0); 2070 PUT32(sc, RADEON_CRTC_PITCH, pitch); 2071 CLR32(sc, RADEON_DISP_MERGE_CNTL, RADEON_DISP_RGB_OFFSET_EN); 2072 2073 CLR32(sc, RADEON_CRTC_EXT_CNTL, 2074 RADEON_CRTC_VSYNC_DIS | RADEON_CRTC_HSYNC_DIS | 2075 RADEON_CRTC_DISPLAY_DIS /* | RADEON_CRTC_DISP_REQ_EN_B */); 2076 CLR32(sc, RADEON_CRTC_GEN_CNTL, RADEON_CRTC_DISP_REQ_EN_B); 2077 PRINTREG(RADEON_CRTC_EXT_CNTL); 2078 PRINTREG(RADEON_CRTC_GEN_CNTL); 2079 PRINTREG(RADEON_CLOCK_CNTL_INDEX); 2080 break; 2081 2082 case 1: 2083 PUT32(sc, RADEON_CRTC2_OFFSET, 0); 2084 PUT32(sc, RADEON_CRTC2_OFFSET_CNTL, 0); 2085 PUT32(sc, RADEON_CRTC2_PITCH, pitch); 2086 CLR32(sc, RADEON_DISP2_MERGE_CNTL, RADEON_DISP2_RGB_OFFSET_EN); 2087 CLR32(sc, RADEON_CRTC2_GEN_CNTL, 2088 RADEON_CRTC2_VSYNC_DIS | 2089 RADEON_CRTC2_HSYNC_DIS | 2090 RADEON_CRTC2_DISP_DIS | RADEON_CRTC2_DISP_REQ_EN_B); 2091 PRINTREG(RADEON_CRTC2_GEN_CNTL); 2092 break; 2093 } 2094 } 2095 2096 int 2097 radeonfb_isblank(struct radeonfb_display *dp) 2098 { 2099 uint32_t reg, mask; 2100 2101 if (dp->rd_crtcs[0].rc_number) { 2102 reg = RADEON_CRTC2_GEN_CNTL; 2103 mask = RADEON_CRTC2_DISP_DIS; 2104 } else { 2105 reg = RADEON_CRTC_EXT_CNTL; 2106 mask = RADEON_CRTC_DISPLAY_DIS; 2107 } 2108 return ((GET32(dp->rd_softc, reg) & mask) ? 1 : 0); 2109 } 2110 2111 void 2112 radeonfb_blank(struct radeonfb_display *dp, int blank) 2113 { 2114 struct radeonfb_softc *sc = dp->rd_softc; 2115 uint32_t reg, mask; 2116 uint32_t fpreg, fpval; 2117 int i; 2118 2119 for (i = 0; i < dp->rd_ncrtcs; i++) { 2120 2121 if (dp->rd_crtcs[i].rc_number) { 2122 reg = RADEON_CRTC2_GEN_CNTL; 2123 mask = RADEON_CRTC2_DISP_DIS; 2124 fpreg = RADEON_FP2_GEN_CNTL; 2125 fpval = RADEON_FP2_ON; 2126 } else { 2127 reg = RADEON_CRTC_EXT_CNTL; 2128 mask = RADEON_CRTC_DISPLAY_DIS; 2129 fpreg = RADEON_FP_GEN_CNTL; 2130 fpval = RADEON_FP_FPON; 2131 } 2132 2133 if (blank) { 2134 SET32(sc, reg, mask); 2135 CLR32(sc, fpreg, fpval); 2136 } else { 2137 CLR32(sc, reg, mask); 2138 SET32(sc, fpreg, fpval); 2139 } 2140 } 2141 PRINTREG(RADEON_FP_GEN_CNTL); 2142 PRINTREG(RADEON_FP2_GEN_CNTL); 2143 } 2144 2145 void 2146 radeonfb_init_screen(void *cookie, struct vcons_screen *scr, int existing, 2147 long *defattr) 2148 { 2149 struct radeonfb_display *dp = cookie; 2150 struct rasops_info *ri = &scr->scr_ri; 2151 2152 /* initialize font subsystem */ 2153 wsfont_init(); 2154 2155 DPRINTF(("init screen called, existing %d\n", existing)); 2156 2157 ri->ri_depth = dp->rd_bpp; 2158 ri->ri_width = dp->rd_virtx; 2159 ri->ri_height = dp->rd_virty; 2160 ri->ri_stride = dp->rd_stride; 2161 ri->ri_flg = RI_CENTER; 2162 ri->ri_bits = (void *)dp->rd_fbptr; 2163 2164 /* XXX: 32 bpp only */ 2165 /* this is rgb in "big-endian order..." */ 2166 ri->ri_rnum = 8; 2167 ri->ri_gnum = 8; 2168 ri->ri_bnum = 8; 2169 ri->ri_rpos = 16; 2170 ri->ri_gpos = 8; 2171 ri->ri_bpos = 0; 2172 2173 if (existing) { 2174 ri->ri_flg |= RI_CLEAR; 2175 2176 /* start a modeswitch now */ 2177 radeonfb_modeswitch(dp); 2178 } 2179 2180 /* 2181 * XXX: font selection should be based on properties, with some 2182 * normal/reasonable default. 2183 */ 2184 ri->ri_caps = WSSCREEN_WSCOLORS | WSSCREEN_REVERSE; 2185 2186 /* initialize and look for an initial font */ 2187 rasops_init(ri, dp->rd_virty/8, dp->rd_virtx/8); 2188 2189 rasops_reconfig(ri, dp->rd_virty / ri->ri_font->fontheight, 2190 dp->rd_virtx / ri->ri_font->fontwidth); 2191 2192 /* enable acceleration */ 2193 dp->rd_putchar = ri->ri_ops.putchar; 2194 ri->ri_ops.copyrows = radeonfb_copyrows; 2195 ri->ri_ops.copycols = radeonfb_copycols; 2196 ri->ri_ops.eraserows = radeonfb_eraserows; 2197 ri->ri_ops.erasecols = radeonfb_erasecols; 2198 ri->ri_ops.allocattr = radeonfb_allocattr; 2199 if (!IS_R300(dp->rd_softc)) { 2200 ri->ri_ops.putchar = radeonfb_putchar; 2201 } else { 2202 ri->ri_ops.putchar = radeonfb_putchar_wrapper; 2203 } 2204 ri->ri_ops.cursor = radeonfb_cursor; 2205 } 2206 2207 void 2208 radeonfb_set_fbloc(struct radeonfb_softc *sc) 2209 { 2210 uint32_t gen, ext, gen2 = 0; 2211 uint32_t agploc, aperbase, apersize, mcfbloc; 2212 2213 gen = GET32(sc, RADEON_CRTC_GEN_CNTL); 2214 ext = GET32(sc, RADEON_CRTC_EXT_CNTL); 2215 agploc = GET32(sc, RADEON_MC_AGP_LOCATION); 2216 aperbase = GET32(sc, RADEON_CONFIG_APER_0_BASE); 2217 apersize = GET32(sc, RADEON_CONFIG_APER_SIZE); 2218 2219 PUT32(sc, RADEON_CRTC_GEN_CNTL, gen | RADEON_CRTC_DISP_REQ_EN_B); 2220 PUT32(sc, RADEON_CRTC_EXT_CNTL, ext | RADEON_CRTC_DISPLAY_DIS); 2221 //PUT32(sc, RADEON_CRTC_GEN_CNTL, gen | RADEON_CRTC_DISPLAY_DIS); 2222 //PUT32(sc, RADEON_CRTC_EXT_CNTL, ext | RADEON_CRTC_DISP_REQ_EN_B); 2223 2224 if (HAS_CRTC2(sc)) { 2225 gen2 = GET32(sc, RADEON_CRTC2_GEN_CNTL); 2226 PUT32(sc, RADEON_CRTC2_GEN_CNTL, 2227 gen2 | RADEON_CRTC2_DISP_REQ_EN_B); 2228 } 2229 2230 delay(100000); 2231 2232 mcfbloc = (aperbase >> 16) | 2233 ((aperbase + (apersize - 1)) & 0xffff0000); 2234 2235 sc->sc_aperbase = (mcfbloc & 0xffff) << 16; 2236 sc->sc_memsz = apersize; 2237 2238 if (((agploc & 0xffff) << 16) != 2239 ((mcfbloc & 0xffff0000U) + 0x10000)) { 2240 agploc = mcfbloc & 0xffff0000U; 2241 agploc |= ((agploc + 0x10000) >> 16); 2242 } 2243 2244 PUT32(sc, RADEON_HOST_PATH_CNTL, 0); 2245 2246 PUT32(sc, RADEON_MC_FB_LOCATION, mcfbloc); 2247 PUT32(sc, RADEON_MC_AGP_LOCATION, agploc); 2248 2249 DPRINTF(("aperbase = %u\n", aperbase)); 2250 PRINTREG(RADEON_MC_FB_LOCATION); 2251 PRINTREG(RADEON_MC_AGP_LOCATION); 2252 2253 PUT32(sc, RADEON_DISPLAY_BASE_ADDR, sc->sc_aperbase); 2254 2255 if (HAS_CRTC2(sc)) 2256 PUT32(sc, RADEON_DISPLAY2_BASE_ADDR, sc->sc_aperbase); 2257 2258 PUT32(sc, RADEON_OV0_BASE_ADDR, sc->sc_aperbase); 2259 2260 #if 0 2261 /* XXX: what is this AGP garbage? :-) */ 2262 PUT32(sc, RADEON_AGP_CNTL, 0x00100000); 2263 #endif 2264 2265 delay(100000); 2266 2267 PUT32(sc, RADEON_CRTC_GEN_CNTL, gen); 2268 PUT32(sc, RADEON_CRTC_EXT_CNTL, ext); 2269 2270 if (HAS_CRTC2(sc)) 2271 PUT32(sc, RADEON_CRTC2_GEN_CNTL, gen2); 2272 } 2273 2274 void 2275 radeonfb_init_misc(struct radeonfb_softc *sc) 2276 { 2277 PUT32(sc, RADEON_BUS_CNTL, 2278 RADEON_BUS_MASTER_DIS | 2279 RADEON_BUS_PREFETCH_MODE_ACT | 2280 RADEON_BUS_PCI_READ_RETRY_EN | 2281 RADEON_BUS_PCI_WRT_RETRY_EN | 2282 (3 << RADEON_BUS_RETRY_WS_SHIFT) | 2283 RADEON_BUS_MSTR_RD_MULT | 2284 RADEON_BUS_MSTR_RD_LINE | 2285 RADEON_BUS_RD_DISCARD_EN | 2286 RADEON_BUS_MSTR_DISCONNECT_EN | 2287 RADEON_BUS_READ_BURST); 2288 2289 PUT32(sc, RADEON_BUS_CNTL1, 0xf0); 2290 /* PUT32(sc, RADEON_SEPROM_CNTL1, 0x09ff0000); */ 2291 PUT32(sc, RADEON_FCP_CNTL, RADEON_FCP0_SRC_GND); 2292 PUT32(sc, RADEON_RBBM_CNTL, 2293 (3 << RADEON_RB_SETTLE_SHIFT) | 2294 (4 << RADEON_ABORTCLKS_HI_SHIFT) | 2295 (4 << RADEON_ABORTCLKS_CP_SHIFT) | 2296 (4 << RADEON_ABORTCLKS_CFIFO_SHIFT)); 2297 2298 /* XXX: figure out what these mean! */ 2299 PUT32(sc, RADEON_AGP_CNTL, 0x00100000); 2300 PUT32(sc, RADEON_HOST_PATH_CNTL, 0); 2301 //PUT32(sc, RADEON_DISP_MISC_CNTL, 0x5bb00400); 2302 2303 PUT32(sc, RADEON_GEN_INT_CNTL, 0); 2304 PUT32(sc, RADEON_GEN_INT_STATUS, GET32(sc, RADEON_GEN_INT_STATUS)); 2305 } 2306 2307 /* 2308 * This loads a linear color map for true color. 2309 */ 2310 void 2311 radeonfb_init_palette(struct radeonfb_softc *sc, int crtc) 2312 { 2313 int i; 2314 uint32_t vclk; 2315 2316 #define DAC_WIDTH ((1 << 10) - 1) 2317 #define CLUT_WIDTH ((1 << 8) - 1) 2318 #define CLUT_COLOR(i) ((i * DAC_WIDTH * 2 / CLUT_WIDTH + 1) / 2) 2319 2320 vclk = GETPLL(sc, RADEON_VCLK_ECP_CNTL); 2321 PUTPLL(sc, RADEON_VCLK_ECP_CNTL, vclk & ~RADEON_PIXCLK_DAC_ALWAYS_ONb); 2322 2323 if (crtc) 2324 SET32(sc, RADEON_DAC_CNTL2, RADEON_DAC2_PALETTE_ACC_CTL); 2325 else 2326 CLR32(sc, RADEON_DAC_CNTL2, RADEON_DAC2_PALETTE_ACC_CTL); 2327 2328 PUT32(sc, RADEON_PALETTE_INDEX, 0); 2329 if (sc->sc_displays[crtc].rd_bpp == 0) 2330 sc->sc_displays[crtc].rd_bpp = RADEONFB_DEFAULT_DEPTH; 2331 2332 if (sc->sc_displays[crtc].rd_bpp == 8) { 2333 /* ANSI palette */ 2334 int j = 0; 2335 2336 for (i = 0; i <= CLUT_WIDTH; ++i) { 2337 PUT32(sc, RADEON_PALETTE_30_DATA, 2338 (rasops_cmap[j] << 22) | 2339 (rasops_cmap[j + 1] << 12) | 2340 (rasops_cmap[j + 2] << 2)); 2341 j += 3; 2342 } 2343 } else { 2344 /* linear ramp */ 2345 for (i = 0; i <= CLUT_WIDTH; ++i) { 2346 PUT32(sc, RADEON_PALETTE_30_DATA, 2347 (CLUT_COLOR(i) << 10) | 2348 (CLUT_COLOR(i) << 20) | 2349 (CLUT_COLOR(i))); 2350 } 2351 } 2352 2353 CLR32(sc, RADEON_DAC_CNTL2, RADEON_DAC2_PALETTE_ACC_CTL); 2354 PRINTREG(RADEON_DAC_CNTL2); 2355 2356 PUTPLL(sc, RADEON_VCLK_ECP_CNTL, vclk); 2357 } 2358 2359 /* 2360 * Bugs in some R300 hardware requires this when accessing CLOCK_CNTL_INDEX. 2361 */ 2362 void 2363 radeonfb_r300cg_workaround(struct radeonfb_softc *sc) 2364 { 2365 uint32_t tmp, save; 2366 2367 save = GET32(sc, RADEON_CLOCK_CNTL_INDEX); 2368 tmp = save & ~(0x3f | RADEON_PLL_WR_EN); 2369 PUT32(sc, RADEON_CLOCK_CNTL_INDEX, tmp); 2370 tmp = GET32(sc, RADEON_CLOCK_CNTL_DATA); 2371 PUT32(sc, RADEON_CLOCK_CNTL_INDEX, save); 2372 } 2373 2374 /* 2375 * Acceleration entry points. 2376 */ 2377 static void 2378 radeonfb_putchar(void *cookie, int row, int col, u_int c, long attr) 2379 { 2380 struct rasops_info *ri = cookie; 2381 struct vcons_screen *scr = ri->ri_hw; 2382 struct radeonfb_display *dp = scr->scr_cookie; 2383 struct wsdisplay_font *font = PICK_FONT(ri, c); 2384 uint32_t x, y, w, h; 2385 uint32_t bg, fg, flg; 2386 uint8_t *data; 2387 2388 if (dp->rd_wsmode != WSDISPLAYIO_MODE_EMUL) 2389 return; 2390 2391 if (!CHAR_IN_FONT(c, font)) 2392 return; 2393 2394 w = font->fontwidth; 2395 h = font->fontheight; 2396 2397 flg = attr & 0xff; 2398 if (flg & WSATTR_REVERSE) { 2399 fg = ri->ri_devcmap[(attr >> 16) & 0xf]; 2400 bg = ri->ri_devcmap[(attr >> 24) & 0xf]; 2401 } else { 2402 bg = ri->ri_devcmap[(attr >> 16) & 0xf]; 2403 fg = ri->ri_devcmap[(attr >> 24) & 0xf]; 2404 } 2405 2406 x = ri->ri_xorigin + col * w; 2407 y = ri->ri_yorigin + row * h; 2408 2409 if (c == 0x20) { 2410 radeonfb_rectfill(dp, x, y, w, h, bg); 2411 } else { 2412 data = (uint8_t *)font->data + 2413 (c - font->firstchar) * ri->ri_fontscale; 2414 2415 radeonfb_setup_mono(dp, x, y, w, h, fg, bg); 2416 radeonfb_feed_bytes(dp, ri->ri_fontscale, data); 2417 } 2418 } 2419 2420 /* 2421 * wrapper for software character drawing 2422 * just sync the engine and call rasops*_putchar() 2423 */ 2424 2425 static void 2426 radeonfb_putchar_wrapper(void *cookie, int row, int col, u_int c, long attr) 2427 { 2428 struct rasops_info *ri = cookie; 2429 struct vcons_screen *scr = ri->ri_hw; 2430 struct radeonfb_display *dp = scr->scr_cookie; 2431 2432 radeonfb_engine_idle(dp->rd_softc); 2433 dp->rd_putchar(ri, row, col, c, attr); 2434 } 2435 2436 static void 2437 radeonfb_eraserows(void *cookie, int row, int nrows, long fillattr) 2438 { 2439 struct rasops_info *ri = cookie; 2440 struct vcons_screen *scr = ri->ri_hw; 2441 struct radeonfb_display *dp = scr->scr_cookie; 2442 uint32_t x, y, w, h, fg, bg, ul; 2443 2444 /* XXX: check for full emulation mode? */ 2445 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 2446 x = ri->ri_xorigin; 2447 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 2448 w = ri->ri_emuwidth; 2449 h = ri->ri_font->fontheight * nrows; 2450 2451 rasops_unpack_attr(fillattr, &fg, &bg, &ul); 2452 radeonfb_rectfill(dp, x, y, w, h, ri->ri_devcmap[bg & 0xf]); 2453 } 2454 } 2455 2456 static void 2457 radeonfb_copyrows(void *cookie, int srcrow, int dstrow, int nrows) 2458 { 2459 struct rasops_info *ri = cookie; 2460 struct vcons_screen *scr = ri->ri_hw; 2461 struct radeonfb_display *dp = scr->scr_cookie; 2462 uint32_t x, ys, yd, w, h; 2463 2464 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 2465 x = ri->ri_xorigin; 2466 ys = ri->ri_yorigin + ri->ri_font->fontheight * srcrow; 2467 yd = ri->ri_yorigin + ri->ri_font->fontheight * dstrow; 2468 w = ri->ri_emuwidth; 2469 h = ri->ri_font->fontheight * nrows; 2470 radeonfb_bitblt(dp, x, ys, x, yd, w, h, 2471 RADEON_ROP3_S, 0xffffffff); 2472 } 2473 } 2474 2475 static void 2476 radeonfb_copycols(void *cookie, int row, int srccol, int dstcol, int ncols) 2477 { 2478 struct rasops_info *ri = cookie; 2479 struct vcons_screen *scr = ri->ri_hw; 2480 struct radeonfb_display *dp = scr->scr_cookie; 2481 uint32_t xs, xd, y, w, h; 2482 2483 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 2484 xs = ri->ri_xorigin + ri->ri_font->fontwidth * srccol; 2485 xd = ri->ri_xorigin + ri->ri_font->fontwidth * dstcol; 2486 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 2487 w = ri->ri_font->fontwidth * ncols; 2488 h = ri->ri_font->fontheight; 2489 radeonfb_bitblt(dp, xs, y, xd, y, w, h, 2490 RADEON_ROP3_S, 0xffffffff); 2491 } 2492 } 2493 2494 static void 2495 radeonfb_erasecols(void *cookie, int row, int startcol, int ncols, 2496 long fillattr) 2497 { 2498 struct rasops_info *ri = cookie; 2499 struct vcons_screen *scr = ri->ri_hw; 2500 struct radeonfb_display *dp = scr->scr_cookie; 2501 uint32_t x, y, w, h, fg, bg, ul; 2502 2503 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 2504 x = ri->ri_xorigin + ri->ri_font->fontwidth * startcol; 2505 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 2506 w = ri->ri_font->fontwidth * ncols; 2507 h = ri->ri_font->fontheight; 2508 2509 rasops_unpack_attr(fillattr, &fg, &bg, &ul); 2510 radeonfb_rectfill(dp, x, y, w, h, ri->ri_devcmap[bg & 0xf]); 2511 } 2512 } 2513 2514 static void 2515 radeonfb_cursor(void *cookie, int on, int row, int col) 2516 { 2517 struct rasops_info *ri = cookie; 2518 struct vcons_screen *scr = ri->ri_hw; 2519 struct radeonfb_display *dp = scr->scr_cookie; 2520 int x, y, wi, he; 2521 2522 wi = ri->ri_font->fontwidth; 2523 he = ri->ri_font->fontheight; 2524 2525 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 2526 x = ri->ri_ccol * wi + ri->ri_xorigin; 2527 y = ri->ri_crow * he + ri->ri_yorigin; 2528 /* first turn off the old cursor */ 2529 if (ri->ri_flg & RI_CURSOR) { 2530 radeonfb_bitblt(dp, x, y, x, y, wi, he, 2531 RADEON_ROP3_Dn, 0xffffffff); 2532 ri->ri_flg &= ~RI_CURSOR; 2533 } 2534 ri->ri_crow = row; 2535 ri->ri_ccol = col; 2536 /* then (possibly) turn on the new one */ 2537 if (on) { 2538 x = ri->ri_ccol * wi + ri->ri_xorigin; 2539 y = ri->ri_crow * he + ri->ri_yorigin; 2540 radeonfb_bitblt(dp, x, y, x, y, wi, he, 2541 RADEON_ROP3_Dn, 0xffffffff); 2542 ri->ri_flg |= RI_CURSOR; 2543 } 2544 } else { 2545 scr->scr_ri.ri_crow = row; 2546 scr->scr_ri.ri_ccol = col; 2547 scr->scr_ri.ri_flg &= ~RI_CURSOR; 2548 } 2549 } 2550 2551 static int 2552 radeonfb_allocattr(void *cookie, int fg, int bg, int flags, long *attrp) 2553 { 2554 if ((fg == 0) && (bg == 0)) { 2555 fg = WS_DEFAULT_FG; 2556 bg = WS_DEFAULT_BG; 2557 } 2558 *attrp = ((fg & 0xf) << 24) | ((bg & 0xf) << 16) | (flags & 0xff) << 8; 2559 return 0; 2560 } 2561 2562 /* 2563 * Underlying acceleration support. 2564 */ 2565 static void 2566 radeonfb_setup_mono(struct radeonfb_display *dp, int xd, int yd, int width, 2567 int height, uint32_t fg, uint32_t bg) 2568 { 2569 struct radeonfb_softc *sc = dp->rd_softc; 2570 uint32_t gmc; 2571 uint32_t padded_width = (width+7) & 0xfff8; 2572 uint32_t topleft, bottomright; 2573 2574 gmc = dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT; 2575 2576 if (width != padded_width) { 2577 2578 radeonfb_wait_fifo(sc, 2); 2579 topleft = ((yd << 16) & 0x1fff0000) | (xd & 0x1fff); 2580 bottomright = (((yd + height) << 16) & 0x1fff0000) | 2581 ((xd + width) & 0x1fff); 2582 PUT32(sc, RADEON_SC_TOP_LEFT, topleft); 2583 PUT32(sc, RADEON_SC_BOTTOM_RIGHT, bottomright); 2584 } 2585 2586 radeonfb_wait_fifo(sc, 5); 2587 2588 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 2589 RADEON_GMC_BRUSH_NONE | 2590 RADEON_GMC_SRC_DATATYPE_MONO_FG_BG | 2591 //RADEON_GMC_BYTE_LSB_TO_MSB | 2592 RADEON_GMC_DST_CLIPPING | 2593 RADEON_ROP3_S | 2594 RADEON_DP_SRC_SOURCE_HOST_DATA | 2595 RADEON_GMC_CLR_CMP_CNTL_DIS | 2596 RADEON_GMC_WR_MSK_DIS | 2597 gmc); 2598 2599 PUT32(sc, RADEON_DP_SRC_FRGD_CLR, fg); 2600 PUT32(sc, RADEON_DP_SRC_BKGD_CLR, bg); 2601 2602 PUT32(sc, RADEON_DST_X_Y, (xd << 16) | yd); 2603 PUT32(sc, RADEON_DST_WIDTH_HEIGHT, (padded_width << 16) | height); 2604 2605 } 2606 2607 static void 2608 radeonfb_feed_bytes(struct radeonfb_display *dp, int count, uint8_t *data) 2609 { 2610 struct radeonfb_softc *sc = dp->rd_softc; 2611 int i; 2612 uint32_t latch = 0; 2613 int shift = 0; 2614 2615 for (i = 0; i < count; i++) { 2616 latch |= (data[i] << shift); 2617 if (shift == 24) { 2618 radeonfb_wait_fifo(sc, 1); 2619 PUT32(sc, RADEON_HOST_DATA0, latch); 2620 latch = 0; 2621 shift = 0; 2622 } else 2623 shift += 8; 2624 } 2625 if (shift != 0) { 2626 radeonfb_wait_fifo(sc, 1); 2627 PUT32(sc, RADEON_HOST_DATA0, latch); 2628 } 2629 radeonfb_unclip(sc); 2630 } 2631 2632 static void 2633 radeonfb_rectfill(struct radeonfb_display *dp, int dstx, int dsty, 2634 int width, int height, uint32_t color) 2635 { 2636 struct radeonfb_softc *sc = dp->rd_softc; 2637 uint32_t gmc; 2638 2639 gmc = dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT; 2640 2641 radeonfb_wait_fifo(sc, 6); 2642 2643 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 2644 RADEON_GMC_BRUSH_SOLID_COLOR | 2645 RADEON_GMC_SRC_DATATYPE_COLOR | 2646 RADEON_GMC_CLR_CMP_CNTL_DIS | 2647 RADEON_ROP3_P | gmc); 2648 2649 PUT32(sc, RADEON_DP_BRUSH_FRGD_CLR, color); 2650 PUT32(sc, RADEON_DP_WRITE_MASK, 0xffffffff); 2651 PUT32(sc, RADEON_DP_CNTL, 2652 RADEON_DST_X_LEFT_TO_RIGHT | 2653 RADEON_DST_Y_TOP_TO_BOTTOM); 2654 PUT32(sc, RADEON_DST_Y_X, (dsty << 16) | dstx); 2655 PUT32(sc, RADEON_DST_WIDTH_HEIGHT, (width << 16) | (height)); 2656 2657 /* 2658 * XXX: we don't wait for the fifo to empty -- that would slow 2659 * things down! The linux radeonfb driver waits, but xfree doesn't 2660 */ 2661 /* XXX: for now we do, to make it safe for direct drawing */ 2662 radeonfb_engine_idle(sc); 2663 } 2664 2665 static void 2666 radeonfb_bitblt(struct radeonfb_display *dp, int srcx, int srcy, 2667 int dstx, int dsty, int width, int height, int rop, uint32_t mask) 2668 { 2669 struct radeonfb_softc *sc = dp->rd_softc; 2670 uint32_t gmc; 2671 uint32_t dir; 2672 2673 if (dsty < srcy) { 2674 dir = RADEON_DST_Y_TOP_TO_BOTTOM; 2675 } else { 2676 srcy += height - 1; 2677 dsty += height - 1; 2678 dir = 0; 2679 } 2680 if (dstx < srcx) { 2681 dir |= RADEON_DST_X_LEFT_TO_RIGHT; 2682 } else { 2683 srcx += width - 1; 2684 dstx += width - 1; 2685 } 2686 2687 gmc = dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT; 2688 2689 radeonfb_wait_fifo(sc, 6); 2690 2691 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 2692 //RADEON_GMC_SRC_CLIPPING | 2693 RADEON_GMC_BRUSH_SOLID_COLOR | 2694 RADEON_GMC_SRC_DATATYPE_COLOR | 2695 RADEON_GMC_CLR_CMP_CNTL_DIS | 2696 RADEON_DP_SRC_SOURCE_MEMORY | 2697 rop | gmc); 2698 2699 PUT32(sc, RADEON_DP_WRITE_MASK, mask); 2700 PUT32(sc, RADEON_DP_CNTL, dir); 2701 PUT32(sc, RADEON_SRC_Y_X, (srcy << 16) | srcx); 2702 PUT32(sc, RADEON_DST_Y_X, (dsty << 16) | dstx); 2703 PUT32(sc, RADEON_DST_WIDTH_HEIGHT, (width << 16) | (height)); 2704 2705 /* 2706 * XXX: we don't wait for the fifo to empty -- that would slow 2707 * things down! The linux radeonfb driver waits, but xfree doesn't 2708 */ 2709 /* XXX: for now we do, to make it safe for direct drawing */ 2710 radeonfb_engine_idle(sc); 2711 } 2712 2713 static void 2714 radeonfb_engine_idle(struct radeonfb_softc *sc) 2715 { 2716 int i; 2717 2718 radeonfb_wait_fifo(sc, 64); 2719 for (i = RADEON_TIMEOUT; i; i--) { 2720 if ((GET32(sc, RADEON_RBBM_STATUS) & 2721 RADEON_RBBM_ACTIVE) == 0) { 2722 radeonfb_engine_flush(sc); 2723 break; 2724 } 2725 } 2726 } 2727 2728 static void 2729 radeonfb_wait_fifo(struct radeonfb_softc *sc, int n) 2730 { 2731 int i; 2732 2733 for (i = RADEON_TIMEOUT; i; i--) { 2734 if ((GET32(sc, RADEON_RBBM_STATUS) & 2735 RADEON_RBBM_FIFOCNT_MASK) >= n) 2736 return; 2737 } 2738 #ifdef DIAGNOSTIC 2739 if (!i) 2740 printf("%s: timed out waiting for fifo (%x)\n", 2741 XNAME(sc), GET32(sc, RADEON_RBBM_STATUS)); 2742 #endif 2743 } 2744 2745 static void 2746 radeonfb_engine_flush(struct radeonfb_softc *sc) 2747 { 2748 int i; 2749 SET32(sc, RADEON_RB2D_DSTCACHE_CTLSTAT, RADEON_RB2D_DC_FLUSH_ALL); 2750 for (i = RADEON_TIMEOUT; i; i--) { 2751 if ((GET32(sc, RADEON_RB2D_DSTCACHE_CTLSTAT) & 2752 RADEON_RB2D_DC_BUSY) == 0) 2753 break; 2754 } 2755 #ifdef DIAGNOSTIC 2756 if (!i) 2757 printf("%s: engine flush timed out!\n", XNAME(sc)); 2758 #endif 2759 } 2760 2761 static inline void 2762 radeonfb_unclip(struct radeonfb_softc *sc) 2763 { 2764 2765 radeonfb_wait_fifo(sc, 2); 2766 PUT32(sc, RADEON_SC_TOP_LEFT, 0); 2767 PUT32(sc, RADEON_SC_BOTTOM_RIGHT, 0x1fff1fff); 2768 } 2769 2770 static void 2771 radeonfb_engine_init(struct radeonfb_display *dp) 2772 { 2773 struct radeonfb_softc *sc = dp->rd_softc; 2774 uint32_t pitch; 2775 volatile uint32_t junk; 2776 2777 /* no 3D */ 2778 PUT32(sc, RADEON_RB3D_CNTL, 0); 2779 2780 radeonfb_engine_reset(sc); 2781 pitch = ((dp->rd_virtx * (dp->rd_bpp / 8) + 0x3f)) >> 6; 2782 //pitch = ((sc->sc_maxx * (sc->sc_maxbpp / 8) + 0x3f)) >> 6; 2783 2784 radeonfb_wait_fifo(sc, 1); 2785 if (!IS_R300(sc)) 2786 PUT32(sc, RADEON_RB2D_DSTCACHE_MODE, 0); 2787 2788 radeonfb_wait_fifo(sc, 3); 2789 PUT32(sc, RADEON_DEFAULT_PITCH_OFFSET, 2790 (pitch << 22) | (sc->sc_aperbase >> 10)); 2791 2792 2793 PUT32(sc, RADEON_DST_PITCH_OFFSET, 2794 (pitch << 22) | (sc->sc_aperbase >> 10)); 2795 PUT32(sc, RADEON_SRC_PITCH_OFFSET, 2796 (pitch << 22) | (sc->sc_aperbase >> 10)); 2797 2798 radeonfb_wait_fifo(sc, 1); 2799 #if _BYTE_ORDER == _BIG_ENDIAN 2800 SET32(sc, RADEON_DP_DATATYPE, RADEON_HOST_BIG_ENDIAN_EN); 2801 #else 2802 CLR32(sc, RADEON_DP_DATATYPE, RADEON_HOST_BIG_ENDIAN_EN); 2803 #endif 2804 junk = GET32(sc, RADEON_DP_DATATYPE); 2805 2806 /* default scissors -- no clipping */ 2807 radeonfb_wait_fifo(sc, 1); 2808 PUT32(sc, RADEON_DEFAULT_SC_BOTTOM_RIGHT, 2809 RADEON_DEFAULT_SC_RIGHT_MAX | RADEON_DEFAULT_SC_BOTTOM_MAX); 2810 2811 radeonfb_wait_fifo(sc, 1); 2812 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 2813 (dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT) | 2814 RADEON_GMC_CLR_CMP_CNTL_DIS | 2815 RADEON_GMC_BRUSH_SOLID_COLOR | 2816 RADEON_GMC_SRC_DATATYPE_COLOR); 2817 2818 radeonfb_wait_fifo(sc, 7); 2819 PUT32(sc, RADEON_DST_LINE_START, 0); 2820 PUT32(sc, RADEON_DST_LINE_END, 0); 2821 PUT32(sc, RADEON_DP_BRUSH_FRGD_CLR, 0xffffffff); 2822 PUT32(sc, RADEON_DP_BRUSH_BKGD_CLR, 0); 2823 PUT32(sc, RADEON_DP_SRC_FRGD_CLR, 0xffffffff); 2824 PUT32(sc, RADEON_DP_SRC_BKGD_CLR, 0); 2825 PUT32(sc, RADEON_DP_WRITE_MASK, 0xffffffff); 2826 2827 radeonfb_engine_idle(sc); 2828 } 2829 2830 static void 2831 radeonfb_engine_reset(struct radeonfb_softc *sc) 2832 { 2833 uint32_t hpc, rbbm, mclkcntl, clkindex; 2834 2835 radeonfb_engine_flush(sc); 2836 2837 clkindex = GET32(sc, RADEON_CLOCK_CNTL_INDEX); 2838 if (HAS_R300CG(sc)) 2839 radeonfb_r300cg_workaround(sc); 2840 mclkcntl = GETPLL(sc, RADEON_MCLK_CNTL); 2841 2842 /* 2843 * According to comments in XFree code, resetting the HDP via 2844 * the RBBM_SOFT_RESET can cause bad behavior on some systems. 2845 * So we use HOST_PATH_CNTL instead. 2846 */ 2847 2848 hpc = GET32(sc, RADEON_HOST_PATH_CNTL); 2849 rbbm = GET32(sc, RADEON_RBBM_SOFT_RESET); 2850 if (IS_R300(sc)) { 2851 PUT32(sc, RADEON_RBBM_SOFT_RESET, rbbm | 2852 RADEON_SOFT_RESET_CP | 2853 RADEON_SOFT_RESET_HI | 2854 RADEON_SOFT_RESET_E2); 2855 GET32(sc, RADEON_RBBM_SOFT_RESET); 2856 PUT32(sc, RADEON_RBBM_SOFT_RESET, 0); 2857 /* 2858 * XXX: this bit is not defined in any ATI docs I have, 2859 * nor in the XFree code, but XFree does it. Why? 2860 */ 2861 SET32(sc, RADEON_RB2D_DSTCACHE_MODE, (1<<17)); 2862 } else { 2863 PUT32(sc, RADEON_RBBM_SOFT_RESET, rbbm | 2864 RADEON_SOFT_RESET_CP | 2865 RADEON_SOFT_RESET_SE | 2866 RADEON_SOFT_RESET_RE | 2867 RADEON_SOFT_RESET_PP | 2868 RADEON_SOFT_RESET_E2 | 2869 RADEON_SOFT_RESET_RB); 2870 GET32(sc, RADEON_RBBM_SOFT_RESET); 2871 PUT32(sc, RADEON_RBBM_SOFT_RESET, rbbm & 2872 ~(RADEON_SOFT_RESET_CP | 2873 RADEON_SOFT_RESET_SE | 2874 RADEON_SOFT_RESET_RE | 2875 RADEON_SOFT_RESET_PP | 2876 RADEON_SOFT_RESET_E2 | 2877 RADEON_SOFT_RESET_RB)); 2878 GET32(sc, RADEON_RBBM_SOFT_RESET); 2879 } 2880 2881 PUT32(sc, RADEON_HOST_PATH_CNTL, hpc | RADEON_HDP_SOFT_RESET); 2882 GET32(sc, RADEON_HOST_PATH_CNTL); 2883 PUT32(sc, RADEON_HOST_PATH_CNTL, hpc); 2884 2885 if (IS_R300(sc)) 2886 PUT32(sc, RADEON_RBBM_SOFT_RESET, rbbm); 2887 2888 PUT32(sc, RADEON_CLOCK_CNTL_INDEX, clkindex); 2889 PUTPLL(sc, RADEON_MCLK_CNTL, mclkcntl); 2890 2891 if (HAS_R300CG(sc)) 2892 radeonfb_r300cg_workaround(sc); 2893 } 2894 2895 static int 2896 radeonfb_set_curpos(struct radeonfb_display *dp, struct wsdisplay_curpos *pos) 2897 { 2898 int x, y; 2899 2900 x = pos->x; 2901 y = pos->y; 2902 2903 /* 2904 * This doesn't let a cursor move off the screen. I'm not 2905 * sure if this will have negative effects for e.g. Xinerama. 2906 * I'd guess Xinerama handles it by changing the cursor shape, 2907 * but that needs verification. 2908 */ 2909 if (x >= dp->rd_virtx) 2910 x = dp->rd_virtx - 1; 2911 if (x < 0) 2912 x = 0; 2913 if (y >= dp->rd_virty) 2914 y = dp->rd_virty - 1; 2915 if (y < 0) 2916 y = 0; 2917 2918 dp->rd_cursor.rc_pos.x = x; 2919 dp->rd_cursor.rc_pos.y = y; 2920 2921 radeonfb_cursor_position(dp); 2922 return 0; 2923 } 2924 2925 static int 2926 radeonfb_set_cursor(struct radeonfb_display *dp, struct wsdisplay_cursor *wc) 2927 { 2928 unsigned flags; 2929 2930 uint8_t r[2], g[2], b[2]; 2931 unsigned index, count; 2932 int i, err; 2933 int pitch, size; 2934 struct radeonfb_cursor nc; 2935 2936 flags = wc->which; 2937 2938 /* copy old values */ 2939 nc = dp->rd_cursor; 2940 2941 if (flags & WSDISPLAY_CURSOR_DOCMAP) { 2942 index = wc->cmap.index; 2943 count = wc->cmap.count; 2944 2945 if (index >= 2 || (index + count) > 2) 2946 return EINVAL; 2947 2948 err = copyin(wc->cmap.red, &r[index], count); 2949 if (err) 2950 return err; 2951 err = copyin(wc->cmap.green, &g[index], count); 2952 if (err) 2953 return err; 2954 err = copyin(wc->cmap.blue, &b[index], count); 2955 if (err) 2956 return err; 2957 2958 for (i = index; i < index + count; i++) { 2959 nc.rc_cmap[i] = 2960 (r[i] << 16) + (g[i] << 8) + (b[i] << 0); 2961 } 2962 } 2963 2964 if (flags & WSDISPLAY_CURSOR_DOSHAPE) { 2965 if ((wc->size.x > RADEON_CURSORMAXX) || 2966 (wc->size.y > RADEON_CURSORMAXY)) 2967 return EINVAL; 2968 2969 /* figure bytes per line */ 2970 pitch = (wc->size.x + 7) / 8; 2971 size = pitch * wc->size.y; 2972 2973 /* clear the old cursor and mask */ 2974 memset(nc.rc_image, 0, 512); 2975 memset(nc.rc_mask, 0, 512); 2976 2977 nc.rc_size = wc->size; 2978 2979 if ((err = copyin(wc->image, nc.rc_image, size)) != 0) 2980 return err; 2981 2982 if ((err = copyin(wc->mask, nc.rc_mask, size)) != 0) 2983 return err; 2984 } 2985 2986 if (flags & WSDISPLAY_CURSOR_DOHOT) { 2987 nc.rc_hot = wc->hot; 2988 if (nc.rc_hot.x >= nc.rc_size.x) 2989 nc.rc_hot.x = nc.rc_size.x - 1; 2990 if (nc.rc_hot.y >= nc.rc_size.y) 2991 nc.rc_hot.y = nc.rc_size.y - 1; 2992 } 2993 2994 if (flags & WSDISPLAY_CURSOR_DOPOS) { 2995 nc.rc_pos = wc->pos; 2996 if (nc.rc_pos.x >= dp->rd_virtx) 2997 nc.rc_pos.x = dp->rd_virtx - 1; 2998 #if 0 2999 if (nc.rc_pos.x < 0) 3000 nc.rc_pos.x = 0; 3001 #endif 3002 if (nc.rc_pos.y >= dp->rd_virty) 3003 nc.rc_pos.y = dp->rd_virty - 1; 3004 #if 0 3005 if (nc.rc_pos.y < 0) 3006 nc.rc_pos.y = 0; 3007 #endif 3008 } 3009 if (flags & WSDISPLAY_CURSOR_DOCUR) { 3010 nc.rc_visible = wc->enable; 3011 } 3012 3013 dp->rd_cursor = nc; 3014 radeonfb_cursor_update(dp, wc->which); 3015 3016 return 0; 3017 } 3018 3019 /* 3020 * Change the cursor shape. Call this with the cursor locked to avoid 3021 * flickering/tearing. 3022 */ 3023 static void 3024 radeonfb_cursor_shape(struct radeonfb_display *dp) 3025 { 3026 uint8_t and[512], xor[512]; 3027 int i, j, src, dst, pitch; 3028 const uint8_t *msk = dp->rd_cursor.rc_mask; 3029 const uint8_t *img = dp->rd_cursor.rc_image; 3030 3031 /* 3032 * Radeon cursor data interleaves one line of AND data followed 3033 * by a line of XOR data. (Each line corresponds to a whole hardware 3034 * pitch - i.e. 64 pixels or 8 bytes.) 3035 * 3036 * The cursor is displayed using the following table: 3037 * 3038 * AND XOR Result 3039 * ---------------------- 3040 * 0 0 Cursor color 0 3041 * 0 1 Cursor color 1 3042 * 1 0 Transparent 3043 * 1 1 Complement of background 3044 * 3045 * Our masks are therefore different from what we were passed. 3046 * Passed in, I'm assuming the data represents either color 0 or 1, 3047 * and a mask, so the passed in table looks like: 3048 * 3049 * IMG Mask Result 3050 * ----------------------- 3051 * 0 0 Transparent 3052 * 0 1 Cursor color 0 3053 * 1 0 Transparent 3054 * 1 1 Cursor color 1 3055 * 3056 * IF mask bit == 1, AND = 0, XOR = color. 3057 * IF mask bit == 0, AND = 1, XOR = 0. 3058 * 3059 * hence: AND = ~(mask); XOR = color & ~(mask); 3060 */ 3061 3062 pitch = ((dp->rd_cursor.rc_size.x + 7) / 8); 3063 3064 /* start by assuming all bits are transparent */ 3065 memset(and, 0xff, 512); 3066 memset(xor, 0x00, 512); 3067 3068 src = 0; 3069 dst = 0; 3070 for (i = 0; i < 64; i++) { 3071 for (j = 0; j < 64; j += 8) { 3072 if ((i < dp->rd_cursor.rc_size.y) && 3073 (j < dp->rd_cursor.rc_size.x)) { 3074 3075 /* take care to leave odd bits alone */ 3076 and[dst] &= ~(msk[src]); 3077 xor[dst] = img[src] & msk[src]; 3078 src++; 3079 } 3080 dst++; 3081 } 3082 } 3083 3084 /* copy the image into place */ 3085 for (i = 0; i < 64; i++) { 3086 memcpy((uint8_t *)dp->rd_curptr + (i * 16), 3087 &and[i * 8], 8); 3088 memcpy((uint8_t *)dp->rd_curptr + (i * 16) + 8, 3089 &xor[i * 8], 8); 3090 } 3091 } 3092 3093 static void 3094 radeonfb_cursor_position(struct radeonfb_display *dp) 3095 { 3096 struct radeonfb_softc *sc = dp->rd_softc; 3097 uint32_t offset, hvoff, hvpos; /* registers */ 3098 uint32_t coff; /* cursor offset */ 3099 int i, x, y, xoff, yoff, crtcoff; 3100 3101 /* 3102 * XXX: this also needs to handle pan/scan 3103 */ 3104 for (i = 0; i < dp->rd_ncrtcs; i++) { 3105 3106 struct radeonfb_crtc *rcp = &dp->rd_crtcs[i]; 3107 3108 if (rcp->rc_number) { 3109 offset = RADEON_CUR2_OFFSET; 3110 hvoff = RADEON_CUR2_HORZ_VERT_OFF; 3111 hvpos = RADEON_CUR2_HORZ_VERT_POSN; 3112 crtcoff = RADEON_CRTC2_OFFSET; 3113 } else { 3114 offset = RADEON_CUR_OFFSET; 3115 hvoff = RADEON_CUR_HORZ_VERT_OFF; 3116 hvpos = RADEON_CUR_HORZ_VERT_POSN; 3117 crtcoff = RADEON_CRTC_OFFSET; 3118 } 3119 3120 x = dp->rd_cursor.rc_pos.x; 3121 y = dp->rd_cursor.rc_pos.y; 3122 3123 while (y < rcp->rc_yoffset) { 3124 rcp->rc_yoffset -= RADEON_PANINCREMENT; 3125 } 3126 while (y >= (rcp->rc_yoffset + rcp->rc_videomode.vdisplay)) { 3127 rcp->rc_yoffset += RADEON_PANINCREMENT; 3128 } 3129 while (x < rcp->rc_xoffset) { 3130 rcp->rc_xoffset -= RADEON_PANINCREMENT; 3131 } 3132 while (x >= (rcp->rc_xoffset + rcp->rc_videomode.hdisplay)) { 3133 rcp->rc_xoffset += RADEON_PANINCREMENT; 3134 } 3135 3136 /* adjust for the cursor's hotspot */ 3137 x -= dp->rd_cursor.rc_hot.x; 3138 y -= dp->rd_cursor.rc_hot.y; 3139 xoff = yoff = 0; 3140 3141 if (x >= dp->rd_virtx) 3142 x = dp->rd_virtx - 1; 3143 if (y >= dp->rd_virty) 3144 y = dp->rd_virty - 1; 3145 3146 /* now adjust cursor so it is relative to viewport */ 3147 x -= rcp->rc_xoffset; 3148 y -= rcp->rc_yoffset; 3149 3150 /* 3151 * no need to check for fall off, because we should 3152 * never move off the screen entirely! 3153 */ 3154 coff = 0; 3155 if (x < 0) { 3156 xoff = -x; 3157 x = 0; 3158 } 3159 if (y < 0) { 3160 yoff = -y; 3161 y = 0; 3162 coff = (yoff * 2) * 8; 3163 } 3164 3165 /* pan the display */ 3166 PUT32(sc, crtcoff, (rcp->rc_yoffset * dp->rd_stride) + 3167 rcp->rc_xoffset); 3168 3169 PUT32(sc, offset, (dp->rd_curoff + coff) | RADEON_CUR_LOCK); 3170 PUT32(sc, hvoff, (xoff << 16) | (yoff) | RADEON_CUR_LOCK); 3171 /* NB: this unlocks the cursor */ 3172 PUT32(sc, hvpos, (x << 16) | y); 3173 } 3174 } 3175 3176 static void 3177 radeonfb_cursor_visible(struct radeonfb_display *dp) 3178 { 3179 int i; 3180 uint32_t gencntl, bit; 3181 3182 for (i = 0; i < dp->rd_ncrtcs; i++) { 3183 if (dp->rd_crtcs[i].rc_number) { 3184 gencntl = RADEON_CRTC2_GEN_CNTL; 3185 bit = RADEON_CRTC2_CUR_EN; 3186 } else { 3187 gencntl = RADEON_CRTC_GEN_CNTL; 3188 bit = RADEON_CRTC_CUR_EN; 3189 } 3190 3191 if (dp->rd_cursor.rc_visible) 3192 SET32(dp->rd_softc, gencntl, bit); 3193 else 3194 CLR32(dp->rd_softc, gencntl, bit); 3195 } 3196 } 3197 3198 static void 3199 radeonfb_cursor_cmap(struct radeonfb_display *dp) 3200 { 3201 int i; 3202 uint32_t c0reg, c1reg; 3203 struct radeonfb_softc *sc = dp->rd_softc; 3204 3205 for (i = 0; i < dp->rd_ncrtcs; i++) { 3206 if (dp->rd_crtcs[i].rc_number) { 3207 c0reg = RADEON_CUR2_CLR0; 3208 c1reg = RADEON_CUR2_CLR1; 3209 } else { 3210 c0reg = RADEON_CUR_CLR0; 3211 c1reg = RADEON_CUR_CLR1; 3212 } 3213 3214 PUT32(sc, c0reg, dp->rd_cursor.rc_cmap[0]); 3215 PUT32(sc, c1reg, dp->rd_cursor.rc_cmap[1]); 3216 } 3217 } 3218 3219 static void 3220 radeonfb_cursor_update(struct radeonfb_display *dp, unsigned which) 3221 { 3222 struct radeonfb_softc *sc; 3223 int i; 3224 3225 sc = dp->rd_softc; 3226 for (i = 0; i < dp->rd_ncrtcs; i++) { 3227 if (dp->rd_crtcs[i].rc_number) { 3228 SET32(sc, RADEON_CUR2_OFFSET, RADEON_CUR_LOCK); 3229 } else { 3230 SET32(sc, RADEON_CUR_OFFSET,RADEON_CUR_LOCK); 3231 } 3232 } 3233 3234 if (which & WSDISPLAY_CURSOR_DOCMAP) 3235 radeonfb_cursor_cmap(dp); 3236 3237 if (which & WSDISPLAY_CURSOR_DOSHAPE) 3238 radeonfb_cursor_shape(dp); 3239 3240 if (which & WSDISPLAY_CURSOR_DOCUR) 3241 radeonfb_cursor_visible(dp); 3242 3243 /* this one is unconditional, because it updates other stuff */ 3244 radeonfb_cursor_position(dp); 3245 } 3246 3247 static struct videomode * 3248 radeonfb_best_refresh(struct videomode *m1, struct videomode *m2) 3249 { 3250 int r1, r2; 3251 3252 /* otherwise pick the higher refresh rate */ 3253 r1 = DIVIDE(DIVIDE(m1->dot_clock, m1->htotal), m1->vtotal); 3254 r2 = DIVIDE(DIVIDE(m2->dot_clock, m2->htotal), m2->vtotal); 3255 3256 return (r1 < r2 ? m2 : m1); 3257 } 3258 3259 static const struct videomode * 3260 radeonfb_port_mode(struct radeonfb_softc *sc, struct radeonfb_port *rp, 3261 int x, int y) 3262 { 3263 struct edid_info *ep = &rp->rp_edid; 3264 struct videomode *vmp = NULL; 3265 int i; 3266 3267 if (!rp->rp_edid_valid) { 3268 /* fallback to safe mode */ 3269 return radeonfb_modelookup(sc->sc_defaultmode); 3270 } 3271 3272 /* always choose the preferred mode first! */ 3273 if (ep->edid_preferred_mode) { 3274 3275 /* XXX: add auto-stretching support for native mode */ 3276 3277 /* this may want panning to occur, btw */ 3278 if ((ep->edid_preferred_mode->hdisplay <= x) && 3279 (ep->edid_preferred_mode->vdisplay <= y)) 3280 return ep->edid_preferred_mode; 3281 } 3282 3283 for (i = 0; i < ep->edid_nmodes; i++) { 3284 /* 3285 * We elect to pick a resolution that is too large for 3286 * the monitor than one that is too small. This means 3287 * that we will prefer to pan rather than to try to 3288 * center a smaller display on a larger screen. In 3289 * practice, this shouldn't matter because if a 3290 * monitor can support a larger resolution, it can 3291 * probably also support the smaller. A specific 3292 * exception is fixed format panels, but hopefully 3293 * they are properly dealt with by the "autostretch" 3294 * logic above. 3295 */ 3296 if ((ep->edid_modes[i].hdisplay > x) || 3297 (ep->edid_modes[i].vdisplay > y)) { 3298 continue; 3299 } 3300 3301 /* 3302 * at this point, the display mode is no larger than 3303 * what we've requested. 3304 */ 3305 if (vmp == NULL) 3306 vmp = &ep->edid_modes[i]; 3307 3308 /* eliminate smaller modes */ 3309 if ((vmp->hdisplay >= ep->edid_modes[i].hdisplay) || 3310 (vmp->vdisplay >= ep->edid_modes[i].vdisplay)) 3311 continue; 3312 3313 if ((vmp->hdisplay < ep->edid_modes[i].hdisplay) || 3314 (vmp->vdisplay < ep->edid_modes[i].vdisplay)) { 3315 vmp = &ep->edid_modes[i]; 3316 continue; 3317 } 3318 3319 KASSERT(vmp->hdisplay == ep->edid_modes[i].hdisplay); 3320 KASSERT(vmp->vdisplay == ep->edid_modes[i].vdisplay); 3321 3322 vmp = radeonfb_best_refresh(vmp, &ep->edid_modes[i]); 3323 } 3324 3325 return (vmp ? vmp : radeonfb_modelookup(sc->sc_defaultmode)); 3326 } 3327 3328 static int 3329 radeonfb_hasres(struct videomode *list, int nlist, int x, int y) 3330 { 3331 int i; 3332 3333 for (i = 0; i < nlist; i++) { 3334 if ((x == list[i].hdisplay) && 3335 (y == list[i].vdisplay)) { 3336 return 1; 3337 } 3338 } 3339 return 0; 3340 } 3341 3342 static void 3343 radeonfb_pickres(struct radeonfb_display *dp, uint16_t *x, uint16_t *y, 3344 int pan) 3345 { 3346 struct radeonfb_port *rp; 3347 struct edid_info *ep; 3348 int i, j; 3349 3350 *x = 0; 3351 *y = 0; 3352 3353 if (pan) { 3354 for (i = 0; i < dp->rd_ncrtcs; i++) { 3355 rp = dp->rd_crtcs[i].rc_port; 3356 ep = &rp->rp_edid; 3357 if (!rp->rp_edid_valid) { 3358 /* monitor not present */ 3359 continue; 3360 } 3361 3362 /* 3363 * For now we are ignoring "conflict" that 3364 * could occur when mixing some modes like 3365 * 1280x1024 and 1400x800. It isn't clear 3366 * which is better, so the first one wins. 3367 */ 3368 for (j = 0; j < ep->edid_nmodes; j++) { 3369 /* 3370 * ignore resolutions that are too big for 3371 * the radeon 3372 */ 3373 if (ep->edid_modes[j].hdisplay > 3374 dp->rd_softc->sc_maxx) 3375 continue; 3376 if (ep->edid_modes[j].vdisplay > 3377 dp->rd_softc->sc_maxy) 3378 continue; 3379 3380 /* 3381 * pick largest resolution, the 3382 * smaller monitor will pan 3383 */ 3384 if ((ep->edid_modes[j].hdisplay >= *x) && 3385 (ep->edid_modes[j].vdisplay >= *y)) { 3386 *x = ep->edid_modes[j].hdisplay; 3387 *y = ep->edid_modes[j].vdisplay; 3388 } 3389 } 3390 } 3391 3392 } else { 3393 struct videomode modes[64]; 3394 int nmodes = 0; 3395 int valid = 0; 3396 3397 for (i = 0; i < dp->rd_ncrtcs; i++) { 3398 /* 3399 * pick the largest resolution in common. 3400 */ 3401 rp = dp->rd_crtcs[i].rc_port; 3402 ep = &rp->rp_edid; 3403 3404 if (!rp->rp_edid_valid) 3405 continue; 3406 3407 if (!valid) { 3408 /* 3409 * Pick the preferred mode for this port 3410 * if available. 3411 */ 3412 if (ep->edid_preferred_mode) { 3413 struct videomode *vmp = 3414 ep->edid_preferred_mode; 3415 3416 if ((vmp->hdisplay <= 3417 dp->rd_softc->sc_maxx) && 3418 (vmp->vdisplay <= 3419 dp->rd_softc->sc_maxy)) 3420 modes[nmodes++] = *vmp; 3421 } else { 3422 3423 /* initialize starting list */ 3424 for (j = 0; j < ep->edid_nmodes; j++) { 3425 /* 3426 * ignore resolutions that are 3427 * too big for the radeon 3428 */ 3429 if (ep->edid_modes[j].hdisplay > 3430 dp->rd_softc->sc_maxx) 3431 continue; 3432 if (ep->edid_modes[j].vdisplay > 3433 dp->rd_softc->sc_maxy) 3434 continue; 3435 3436 modes[nmodes] = 3437 ep->edid_modes[j]; 3438 nmodes++; 3439 } 3440 } 3441 valid = 1; 3442 } else { 3443 /* merge into preexisting list */ 3444 for (j = 0; j < nmodes; j++) { 3445 if (!radeonfb_hasres(ep->edid_modes, 3446 ep->edid_nmodes, 3447 modes[j].hdisplay, 3448 modes[j].vdisplay)) { 3449 modes[j] = modes[nmodes]; 3450 j--; 3451 nmodes--; 3452 } 3453 } 3454 } 3455 } 3456 3457 /* now we have to pick from the merged list */ 3458 for (i = 0; i < nmodes; i++) { 3459 if ((modes[i].hdisplay >= *x) && 3460 (modes[i].vdisplay >= *y)) { 3461 *x = modes[i].hdisplay; 3462 *y = modes[i].vdisplay; 3463 } 3464 } 3465 } 3466 3467 if ((*x == 0) || (*y == 0)) { 3468 /* fallback to safe mode */ 3469 *x = 640; 3470 *y = 480; 3471 } 3472 } 3473 3474 /* 3475 * backlight levels are linear on: 3476 * - RV200, RV250, RV280, RV350 3477 * - but NOT on PowerBook4,3 6,3 6,5 3478 * according to Linux' radeonfb 3479 */ 3480 3481 /* Get the current backlight level for the display. */ 3482 3483 static int 3484 radeonfb_get_backlight(struct radeonfb_display *dp) 3485 { 3486 int s; 3487 uint32_t level; 3488 3489 s = spltty(); 3490 3491 level = radeonfb_get32(dp->rd_softc, RADEON_LVDS_GEN_CNTL); 3492 level &= RADEON_LVDS_BL_MOD_LEV_MASK; 3493 level >>= RADEON_LVDS_BL_MOD_LEV_SHIFT; 3494 3495 /* 3496 * On some chips, we should negate the backlight level. 3497 * XXX Find out on which chips. 3498 */ 3499 if (dp->rd_softc->sc_flags & RFB_INV_BLIGHT) 3500 level = RADEONFB_BACKLIGHT_MAX - level; 3501 3502 splx(s); 3503 3504 return level; 3505 } 3506 3507 /* Set the backlight to the given level for the display. */ 3508 3509 static int 3510 radeonfb_set_backlight(struct radeonfb_display *dp, int level) 3511 { 3512 struct radeonfb_softc *sc; 3513 int rlevel, s; 3514 uint32_t lvds; 3515 3516 s = spltty(); 3517 3518 if (level < 0) 3519 level = 0; 3520 else if (level >= RADEONFB_BACKLIGHT_MAX) 3521 level = RADEONFB_BACKLIGHT_MAX; 3522 3523 sc = dp->rd_softc; 3524 3525 /* On some chips, we should negate the backlight level. */ 3526 if (dp->rd_softc->sc_flags & RFB_INV_BLIGHT) { 3527 rlevel = RADEONFB_BACKLIGHT_MAX - level; 3528 } else 3529 rlevel = level; 3530 3531 callout_stop(&dp->rd_bl_lvds_co); 3532 radeonfb_engine_idle(sc); 3533 3534 /* 3535 * Turn off the display if the backlight is set to 0, since the 3536 * display is useless without backlight anyway. 3537 */ 3538 if (level == 0) 3539 radeonfb_blank(dp, 1); 3540 else if (radeonfb_get_backlight(dp) == 0) 3541 radeonfb_blank(dp, 0); 3542 3543 lvds = radeonfb_get32(sc, RADEON_LVDS_GEN_CNTL); 3544 lvds &= ~RADEON_LVDS_DISPLAY_DIS; 3545 if (!(lvds & RADEON_LVDS_BLON) || !(lvds & RADEON_LVDS_ON)) { 3546 lvds |= dp->rd_bl_lvds_val & RADEON_LVDS_DIGON; 3547 lvds |= RADEON_LVDS_BLON | RADEON_LVDS_EN; 3548 radeonfb_put32(sc, RADEON_LVDS_GEN_CNTL, lvds); 3549 lvds &= ~RADEON_LVDS_BL_MOD_LEV_MASK; 3550 lvds |= rlevel << RADEON_LVDS_BL_MOD_LEV_SHIFT; 3551 lvds |= RADEON_LVDS_ON; 3552 lvds |= dp->rd_bl_lvds_val & RADEON_LVDS_BL_MOD_EN; 3553 } else { 3554 lvds &= ~RADEON_LVDS_BL_MOD_LEV_MASK; 3555 lvds |= rlevel << RADEON_LVDS_BL_MOD_LEV_SHIFT; 3556 radeonfb_put32(sc, RADEON_LVDS_GEN_CNTL, lvds); 3557 } 3558 3559 dp->rd_bl_lvds_val &= ~RADEON_LVDS_STATE_MASK; 3560 dp->rd_bl_lvds_val |= lvds & RADEON_LVDS_STATE_MASK; 3561 /* XXX What is the correct delay? */ 3562 callout_schedule(&dp->rd_bl_lvds_co, 200 * hz); 3563 3564 splx(s); 3565 3566 return 0; 3567 } 3568 3569 /* 3570 * Callout function for delayed operations on the LVDS_GEN_CNTL register. 3571 * Set the delayed bits in the register, and clear the stored delayed 3572 * value. 3573 */ 3574 3575 static void radeonfb_lvds_callout(void *arg) 3576 { 3577 struct radeonfb_display *dp = arg; 3578 int s; 3579 3580 s = splhigh(); 3581 3582 radeonfb_mask32(dp->rd_softc, RADEON_LVDS_GEN_CNTL, ~0, 3583 dp->rd_bl_lvds_val); 3584 dp->rd_bl_lvds_val = 0; 3585 3586 splx(s); 3587 } 3588 3589 static void 3590 radeonfb_brightness_up(device_t dev) 3591 { 3592 struct radeonfb_softc *sc = device_private(dev); 3593 int level; 3594 3595 /* we assume the main display is the first one - need a better way */ 3596 if (sc->sc_ndisplays < 1) return; 3597 level = radeonfb_get_backlight(&sc->sc_displays[0]); 3598 level = min(RADEONFB_BACKLIGHT_MAX, level + 5); 3599 radeonfb_set_backlight(&sc->sc_displays[0], level); 3600 } 3601 3602 static void 3603 radeonfb_brightness_down(device_t dev) 3604 { 3605 struct radeonfb_softc *sc = device_private(dev); 3606 int level; 3607 3608 /* we assume the main display is the first one - need a better way */ 3609 if (sc->sc_ndisplays < 1) return; 3610 level = radeonfb_get_backlight(&sc->sc_displays[0]); 3611 level = max(0, level - 5); 3612 radeonfb_set_backlight(&sc->sc_displays[0], level); 3613 } 3614
Indexes created Wed Sep 24 05:09:52 GMT 2025