radeonfb.c revision 1.46.2.4
1 /* $NetBSD: radeonfb.c,v 1.46.2.4 2013/01/16 05:33:31 yamt Exp $ */ 2 3 /*- 4 * Copyright (c) 2006 Itronix Inc. 5 * All rights reserved. 6 * 7 * Written by Garrett D'Amore for Itronix Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. The name of Itronix Inc. may not be used to endorse 18 * or promote products derived from this software without specific 19 * prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY ITRONIX INC. ``AS IS'' AND ANY EXPRESS 22 * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 23 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL ITRONIX INC. BE LIABLE FOR ANY 25 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE 27 * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 29 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 30 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 31 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * ATI Technologies Inc. ("ATI") has not assisted in the creation of, and 36 * does not endorse, this software. ATI will not be responsible or liable 37 * for any actual or alleged damage or loss caused by or in connection with 38 * the use of or reliance on this software. 39 */ 40 41 /* 42 * Portions of this code were taken from XFree86's Radeon driver, which bears 43 * this notice: 44 * 45 * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and 46 * VA Linux Systems Inc., Fremont, California. 47 * 48 * All Rights Reserved. 49 * 50 * Permission is hereby granted, free of charge, to any person obtaining 51 * a copy of this software and associated documentation files (the 52 * "Software"), to deal in the Software without restriction, including 53 * without limitation on the rights to use, copy, modify, merge, 54 * publish, distribute, sublicense, and/or sell copies of the Software, 55 * and to permit persons to whom the Software is furnished to do so, 56 * subject to the following conditions: 57 * 58 * The above copyright notice and this permission notice (including the 59 * next paragraph) shall be included in all copies or substantial 60 * portions of the Software. 61 * 62 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 63 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 64 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 65 * NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR 66 * THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 67 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 68 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 69 * DEALINGS IN THE SOFTWARE. 70 */ 71 72 #include <sys/cdefs.h> 73 __KERNEL_RCSID(0, "$NetBSD: radeonfb.c,v 1.46.2.4 2013/01/16 05:33:31 yamt Exp $"); 74 75 #include <sys/param.h> 76 #include <sys/systm.h> 77 #include <sys/device.h> 78 #include <sys/malloc.h> 79 #include <sys/bus.h> 80 #include <sys/kernel.h> 81 #include <sys/lwp.h> 82 #include <sys/kauth.h> 83 84 #include <dev/wscons/wsdisplayvar.h> 85 #include <dev/wscons/wsconsio.h> 86 #include <dev/wsfont/wsfont.h> 87 #include <dev/rasops/rasops.h> 88 #include <dev/videomode/videomode.h> 89 #include <dev/videomode/edidvar.h> 90 #include <dev/wscons/wsdisplay_vconsvar.h> 91 #include <dev/pci/wsdisplay_pci.h> 92 #include <dev/wscons/wsdisplay_glyphcachevar.h> 93 94 #include <dev/pci/pcidevs.h> 95 #include <dev/pci/pcireg.h> 96 #include <dev/pci/pcivar.h> 97 #include <dev/pci/pciio.h> 98 #include <dev/pci/radeonfbreg.h> 99 #include <dev/pci/radeonfbvar.h> 100 #include "opt_radeonfb.h" 101 #include "opt_vcons.h" 102 103 #ifdef RADEONFB_DEPTH_32 104 #define RADEONFB_DEFAULT_DEPTH 32 105 #else 106 #define RADEONFB_DEFAULT_DEPTH 8 107 #endif 108 109 static int radeonfb_match(device_t, cfdata_t, void *); 110 static void radeonfb_attach(device_t, device_t, void *); 111 static int radeonfb_ioctl(void *, void *, unsigned long, void *, int, 112 struct lwp *); 113 static paddr_t radeonfb_mmap(void *, void *, off_t, int); 114 static int radeonfb_scratch_test(struct radeonfb_softc *, int, uint32_t); 115 static void radeonfb_loadbios(struct radeonfb_softc *, 116 const struct pci_attach_args *); 117 118 static uintmax_t radeonfb_getprop_num(struct radeonfb_softc *, const char *, 119 uintmax_t); 120 static int radeonfb_getclocks(struct radeonfb_softc *); 121 static int radeonfb_gettmds(struct radeonfb_softc *); 122 static int radeonfb_calc_dividers(struct radeonfb_softc *, uint32_t, 123 uint32_t *, uint32_t *); 124 static int radeonfb_getconnectors(struct radeonfb_softc *); 125 static const struct videomode *radeonfb_modelookup(const char *); 126 static void radeonfb_init_screen(void *, struct vcons_screen *, int, long *); 127 static void radeonfb_pllwriteupdate(struct radeonfb_softc *, int); 128 static void radeonfb_pllwaitatomicread(struct radeonfb_softc *, int); 129 static void radeonfb_program_vclk(struct radeonfb_softc *, int, int); 130 static void radeonfb_modeswitch(struct radeonfb_display *); 131 static void radeonfb_setcrtc(struct radeonfb_display *, int); 132 static void radeonfb_init_misc(struct radeonfb_softc *); 133 static void radeonfb_set_fbloc(struct radeonfb_softc *); 134 static void radeonfb_init_palette(struct radeonfb_softc *, int); 135 static void radeonfb_r300cg_workaround(struct radeonfb_softc *); 136 137 static int radeonfb_isblank(struct radeonfb_display *); 138 static void radeonfb_blank(struct radeonfb_display *, int); 139 static int radeonfb_set_cursor(struct radeonfb_display *, 140 struct wsdisplay_cursor *); 141 static int radeonfb_set_curpos(struct radeonfb_display *, 142 struct wsdisplay_curpos *); 143 144 /* acceleration support */ 145 static void radeonfb_rectfill(struct radeonfb_display *, int dstx, int dsty, 146 int width, int height, uint32_t color); 147 static void radeonfb_rectfill_a(void *, int, int, int, int, long); 148 static void radeonfb_bitblt(void *, int srcx, int srcy, 149 int dstx, int dsty, int width, int height, int rop); 150 151 /* hw cursor support */ 152 static void radeonfb_cursor_cmap(struct radeonfb_display *); 153 static void radeonfb_cursor_shape(struct radeonfb_display *); 154 static void radeonfb_cursor_position(struct radeonfb_display *); 155 static void radeonfb_cursor_visible(struct radeonfb_display *); 156 static void radeonfb_cursor_update(struct radeonfb_display *, unsigned); 157 158 static inline void radeonfb_wait_fifo(struct radeonfb_softc *, int); 159 static void radeonfb_engine_idle(struct radeonfb_softc *); 160 static void radeonfb_engine_flush(struct radeonfb_softc *); 161 static void radeonfb_engine_reset(struct radeonfb_softc *); 162 static void radeonfb_engine_init(struct radeonfb_display *); 163 static inline void radeonfb_unclip(struct radeonfb_softc *); 164 165 static void radeonfb_eraserows(void *, int, int, long); 166 static void radeonfb_erasecols(void *, int, int, int, long); 167 static void radeonfb_copyrows(void *, int, int, int); 168 static void radeonfb_copycols(void *, int, int, int, int); 169 static void radeonfb_cursor(void *, int, int, int); 170 static void radeonfb_putchar(void *, int, int, unsigned, long); 171 static void radeonfb_putchar_aa32(void *, int, int, unsigned, long); 172 static void radeonfb_putchar_aa8(void *, int, int, unsigned, long); 173 static void radeonfb_putchar_wrapper(void *, int, int, unsigned, long); 174 175 static int radeonfb_set_backlight(struct radeonfb_display *, int); 176 static int radeonfb_get_backlight(struct radeonfb_display *); 177 static void radeonfb_switch_backlight(struct radeonfb_display *, int); 178 static void radeonfb_lvds_callout(void *); 179 180 static void radeonfb_brightness_up(device_t); 181 static void radeonfb_brightness_down(device_t); 182 183 static struct videomode *radeonfb_best_refresh(struct videomode *, 184 struct videomode *); 185 static void radeonfb_pickres(struct radeonfb_display *, uint16_t *, 186 uint16_t *, int); 187 static const struct videomode *radeonfb_port_mode(struct radeonfb_softc *, 188 struct radeonfb_port *, int, int); 189 190 static int radeonfb_drm_print(void *, const char *); 191 192 #ifdef RADEONFB_DEBUG 193 int radeon_debug = 1; 194 #define DPRINTF(x) \ 195 if (radeon_debug) printf x 196 #define PRINTREG(r) DPRINTF((#r " = %08x\n", GET32(sc, r))) 197 #define PRINTPLL(r) DPRINTF((#r " = %08x\n", GETPLL(sc, r))) 198 #else 199 #define DPRINTF(x) 200 #define PRINTREG(r) 201 #define PRINTPLL(r) 202 #endif 203 204 #define ROUNDUP(x,y) (((x) + ((y) - 1)) & ~((y) - 1)) 205 206 #ifndef RADEON_DEFAULT_MODE 207 /* any reasonably modern display should handle this */ 208 #define RADEON_DEFAULT_MODE "1024x768x60" 209 #endif 210 211 extern const u_char rasops_cmap[768]; 212 213 const char *radeonfb_default_mode = RADEON_DEFAULT_MODE; 214 215 static struct { 216 int size; /* minimum memory size (MB) */ 217 int maxx; /* maximum x dimension */ 218 int maxy; /* maximum y dimension */ 219 int maxbpp; /* maximum bpp */ 220 int maxdisp; /* maximum logical display count */ 221 } radeonfb_limits[] = { 222 { 32, 2048, 1536, 32, 2 }, 223 { 16, 1600, 1200, 32, 2 }, 224 { 8, 1600, 1200, 32, 1 }, 225 { 0, 0, 0, 0, 0 }, 226 }; 227 228 static struct wsscreen_descr radeonfb_stdscreen = { 229 "fb", /* name */ 230 0, 0, /* ncols, nrows */ 231 NULL, /* textops */ 232 8, 16, /* fontwidth, fontheight */ 233 WSSCREEN_WSCOLORS | WSSCREEN_UNDERLINE, /* capabilities */ 234 0, /* modecookie */ 235 }; 236 237 struct wsdisplay_accessops radeonfb_accessops = { 238 radeonfb_ioctl, 239 radeonfb_mmap, 240 NULL, /* vcons_alloc_screen */ 241 NULL, /* vcons_free_screen */ 242 NULL, /* vcons_show_screen */ 243 NULL, /* load_font */ 244 NULL, /* pollc */ 245 NULL, /* scroll */ 246 }; 247 248 static struct { 249 uint16_t devid; 250 uint16_t family; 251 uint16_t flags; 252 } radeonfb_devices[] = 253 { 254 /* R100 family */ 255 { PCI_PRODUCT_ATI_RADEON_R100_QD, RADEON_R100, 0 }, 256 { PCI_PRODUCT_ATI_RADEON_R100_QE, RADEON_R100, 0 }, 257 { PCI_PRODUCT_ATI_RADEON_R100_QF, RADEON_R100, 0 }, 258 { PCI_PRODUCT_ATI_RADEON_R100_QG, RADEON_R100, 0 }, 259 260 /* RV100 family */ 261 { PCI_PRODUCT_ATI_RADEON_RV100_LY, RADEON_RV100, RFB_MOB }, 262 { PCI_PRODUCT_ATI_RADEON_RV100_LZ, RADEON_RV100, RFB_MOB }, 263 { PCI_PRODUCT_ATI_RADEON_RV100_QY, RADEON_RV100, 0 }, 264 { PCI_PRODUCT_ATI_RADEON_RV100_QZ, RADEON_RV100, 0 }, 265 266 /* RS100 family */ 267 { PCI_PRODUCT_ATI_RADEON_RS100_4136, RADEON_RS100, 0 }, 268 { PCI_PRODUCT_ATI_RADEON_RS100_4336, RADEON_RS100, RFB_MOB }, 269 270 /* RS200/RS250 family */ 271 { PCI_PRODUCT_ATI_RADEON_RS200_4337, RADEON_RS200, RFB_MOB }, 272 { PCI_PRODUCT_ATI_RADEON_RS200_A7, RADEON_RS200, 0 }, 273 { PCI_PRODUCT_ATI_RADEON_RS250_B7, RADEON_RS200, RFB_MOB }, 274 { PCI_PRODUCT_ATI_RADEON_RS250_D7, RADEON_RS200, 0 }, 275 276 /* R200 family */ 277 /* add more R200 products? , 5148 */ 278 { PCI_PRODUCT_ATI_RADEON_R200_BB, RADEON_R200, 0 }, 279 { PCI_PRODUCT_ATI_RADEON_R200_BC, RADEON_R200, 0 }, 280 { PCI_PRODUCT_ATI_RADEON_R200_QH, RADEON_R200, 0 }, 281 { PCI_PRODUCT_ATI_RADEON_R200_QL, RADEON_R200, 0 }, 282 { PCI_PRODUCT_ATI_RADEON_R200_QM, RADEON_R200, 0 }, 283 284 /* RV200 family */ 285 { PCI_PRODUCT_ATI_RADEON_RV200_LW, RADEON_RV200, RFB_MOB }, 286 { PCI_PRODUCT_ATI_RADEON_RV200_LX, RADEON_RV200, RFB_MOB }, 287 { PCI_PRODUCT_ATI_RADEON_RV200_QW, RADEON_RV200, 0 }, 288 { PCI_PRODUCT_ATI_RADEON_RV200_QX, RADEON_RV200, 0 }, 289 290 /* RV250 family */ 291 { PCI_PRODUCT_ATI_RADEON_RV250_4966, RADEON_RV250, 0 }, 292 { PCI_PRODUCT_ATI_RADEON_RV250_4967, RADEON_RV250, 0 }, 293 { PCI_PRODUCT_ATI_RADEON_RV250_4C64, RADEON_RV250, RFB_MOB }, 294 { PCI_PRODUCT_ATI_RADEON_RV250_4C66, RADEON_RV250, RFB_MOB }, 295 { PCI_PRODUCT_ATI_RADEON_RV250_4C67, RADEON_RV250, RFB_MOB }, 296 297 /* RS300 family */ 298 { PCI_PRODUCT_ATI_RADEON_RS300_X5, RADEON_RS300, 0 }, 299 { PCI_PRODUCT_ATI_RADEON_RS300_X4, RADEON_RS300, 0 }, 300 { PCI_PRODUCT_ATI_RADEON_RS300_7834, RADEON_RS300, 0 }, 301 { PCI_PRODUCT_ATI_RADEON_RS300_7835, RADEON_RS300, RFB_MOB }, 302 303 /* RV280 family */ 304 { PCI_PRODUCT_ATI_RADEON_RV280_5960, RADEON_RV280, 0 }, 305 { PCI_PRODUCT_ATI_RADEON_RV280_5961, RADEON_RV280, 0 }, 306 { PCI_PRODUCT_ATI_RADEON_RV280_5962, RADEON_RV280, 0 }, 307 { PCI_PRODUCT_ATI_RADEON_RV280_5963, RADEON_RV280, 0 }, 308 { PCI_PRODUCT_ATI_RADEON_RV280_5964, RADEON_RV280, 0 }, 309 { PCI_PRODUCT_ATI_RADEON_RV280_5C61, RADEON_RV280, RFB_MOB }, 310 { PCI_PRODUCT_ATI_RADEON_RV280_5C63, RADEON_RV280, RFB_MOB }, 311 312 /* R300 family */ 313 { PCI_PRODUCT_ATI_RADEON_R300_AD, RADEON_R300, 0 }, 314 { PCI_PRODUCT_ATI_RADEON_R300_AE, RADEON_R300, 0 }, 315 { PCI_PRODUCT_ATI_RADEON_R300_AF, RADEON_R300, 0 }, 316 { PCI_PRODUCT_ATI_RADEON_R300_AG, RADEON_R300, 0 }, 317 { PCI_PRODUCT_ATI_RADEON_R300_ND, RADEON_R300, 0 }, 318 { PCI_PRODUCT_ATI_RADEON_R300_NE, RADEON_R300, 0 }, 319 { PCI_PRODUCT_ATI_RADEON_R300_NF, RADEON_R300, 0 }, 320 { PCI_PRODUCT_ATI_RADEON_R300_NG, RADEON_R300, 0 }, 321 322 /* RV350/RV360 family */ 323 { PCI_PRODUCT_ATI_RADEON_RV350_AP, RADEON_RV350, 0 }, 324 { PCI_PRODUCT_ATI_RADEON_RV350_AQ, RADEON_RV350, 0 }, 325 { PCI_PRODUCT_ATI_RADEON_RV360_AR, RADEON_RV350, 0 }, 326 { PCI_PRODUCT_ATI_RADEON_RV350_AS, RADEON_RV350, 0 }, 327 { PCI_PRODUCT_ATI_RADEON_RV350_AT, RADEON_RV350, 0 }, 328 { PCI_PRODUCT_ATI_RADEON_RV350_AV, RADEON_RV350, 0 }, 329 { PCI_PRODUCT_ATI_RADEON_RV350_NP, RADEON_RV350, RFB_MOB }, 330 { PCI_PRODUCT_ATI_RADEON_RV350_NQ, RADEON_RV350, RFB_MOB }, 331 { PCI_PRODUCT_ATI_RADEON_RV350_NR, RADEON_RV350, RFB_MOB }, 332 { PCI_PRODUCT_ATI_RADEON_RV350_NS, RADEON_RV350, RFB_MOB }, 333 { PCI_PRODUCT_ATI_RADEON_RV350_NT, RADEON_RV350, RFB_MOB }, 334 { PCI_PRODUCT_ATI_RADEON_RV350_NV, RADEON_RV350, RFB_MOB }, 335 336 /* R350/R360 family */ 337 { PCI_PRODUCT_ATI_RADEON_R350_AH, RADEON_R350, 0 }, 338 { PCI_PRODUCT_ATI_RADEON_R350_AI, RADEON_R350, 0 }, 339 { PCI_PRODUCT_ATI_RADEON_R350_AJ, RADEON_R350, 0 }, 340 { PCI_PRODUCT_ATI_RADEON_R350_AK, RADEON_R350, 0 }, 341 { PCI_PRODUCT_ATI_RADEON_R350_NH, RADEON_R350, 0 }, 342 { PCI_PRODUCT_ATI_RADEON_R350_NI, RADEON_R350, 0 }, 343 { PCI_PRODUCT_ATI_RADEON_R350_NK, RADEON_R350, 0 }, 344 { PCI_PRODUCT_ATI_RADEON_R360_NJ, RADEON_R350, 0 }, 345 346 /* RV380/RV370 family */ 347 { PCI_PRODUCT_ATI_RADEON_RV380_3150, RADEON_RV380, RFB_MOB }, 348 { PCI_PRODUCT_ATI_RADEON_RV380_3154, RADEON_RV380, RFB_MOB }, 349 { PCI_PRODUCT_ATI_RADEON_RV380_3E50, RADEON_RV380, 0 }, 350 { PCI_PRODUCT_ATI_RADEON_RV380_3E54, RADEON_RV380, 0 }, 351 { PCI_PRODUCT_ATI_RADEON_RV370_5460, RADEON_RV380, RFB_MOB }, 352 { PCI_PRODUCT_ATI_RADEON_RV370_5464, RADEON_RV380, RFB_MOB }, 353 { PCI_PRODUCT_ATI_RADEON_RV370_5B60, RADEON_RV380, 0 }, 354 { PCI_PRODUCT_ATI_RADEON_RV370_5B64, RADEON_RV380, 0 }, 355 { PCI_PRODUCT_ATI_RADEON_RV370_5B65, RADEON_RV380, 0 }, 356 357 /* R420/R423 family */ 358 { PCI_PRODUCT_ATI_RADEON_R420_JH, RADEON_R420, 0 }, 359 { PCI_PRODUCT_ATI_RADEON_R420_JI, RADEON_R420, 0 }, 360 { PCI_PRODUCT_ATI_RADEON_R420_JJ, RADEON_R420, 0 }, 361 { PCI_PRODUCT_ATI_RADEON_R420_JK, RADEON_R420, 0 }, 362 { PCI_PRODUCT_ATI_RADEON_R420_JL, RADEON_R420, 0 }, 363 { PCI_PRODUCT_ATI_RADEON_R420_JM, RADEON_R420, 0 }, 364 { PCI_PRODUCT_ATI_RADEON_R420_JN, RADEON_R420, RFB_MOB }, 365 { PCI_PRODUCT_ATI_RADEON_R420_JP, RADEON_R420, 0 }, 366 { PCI_PRODUCT_ATI_RADEON_R423_UH, RADEON_R420, 0 }, 367 { PCI_PRODUCT_ATI_RADEON_R423_UI, RADEON_R420, 0 }, 368 { PCI_PRODUCT_ATI_RADEON_R423_UJ, RADEON_R420, 0 }, 369 { PCI_PRODUCT_ATI_RADEON_R423_UK, RADEON_R420, 0 }, 370 { PCI_PRODUCT_ATI_RADEON_R423_UQ, RADEON_R420, 0 }, 371 { PCI_PRODUCT_ATI_RADEON_R423_UR, RADEON_R420, 0 }, 372 { PCI_PRODUCT_ATI_RADEON_R423_UT, RADEON_R420, 0 }, 373 { PCI_PRODUCT_ATI_RADEON_R423_5D57, RADEON_R420, 0 }, 374 { PCI_PRODUCT_ATI_RADEON_R430_554F, RADEON_R420, 0 }, 375 376 { 0, 0, 0 } 377 }; 378 379 static struct { 380 int divider; 381 int mask; 382 } radeonfb_dividers[] = { 383 { 1, 0 }, 384 { 2, 1 }, 385 { 3, 4 }, 386 { 4, 2 }, 387 { 6, 6 }, 388 { 8, 3 }, 389 { 12, 7 }, 390 { 0, 0 } 391 }; 392 393 /* 394 * This table taken from X11. 395 */ 396 static const struct { 397 int family; 398 struct radeon_tmds_pll plls[4]; 399 } radeonfb_tmds_pll[] = { 400 { RADEON_R100, {{12000, 0xa1b}, {-1, 0xa3f}}}, 401 { RADEON_RV100, {{12000, 0xa1b}, {-1, 0xa3f}}}, 402 { RADEON_RS100, {{0, 0}}}, 403 { RADEON_RV200, {{15000, 0xa1b}, {-1, 0xa3f}}}, 404 { RADEON_RS200, {{15000, 0xa1b}, {-1, 0xa3f}}}, 405 { RADEON_R200, {{15000, 0xa1b}, {-1, 0xa3f}}}, 406 { RADEON_RV250, {{15500, 0x81b}, {-1, 0x83f}}}, 407 { RADEON_RS300, {{0, 0}}}, 408 { RADEON_RV280, {{13000, 0x400f4}, {15000, 0x400f7}}}, 409 { RADEON_R300, {{-1, 0xb01cb}}}, 410 { RADEON_R350, {{-1, 0xb01cb}}}, 411 { RADEON_RV350, {{15000, 0xb0155}, {-1, 0xb01cb}}}, 412 { RADEON_RV380, {{15000, 0xb0155}, {-1, 0xb01cb}}}, 413 { RADEON_R420, {{-1, 0xb01cb}}}, 414 }; 415 416 #define RADEONFB_BACKLIGHT_MAX 255 /* Maximum backlight level. */ 417 418 419 CFATTACH_DECL_NEW(radeonfb, sizeof (struct radeonfb_softc), 420 radeonfb_match, radeonfb_attach, NULL, NULL); 421 422 static int 423 radeonfb_match(device_t parent, cfdata_t match, void *aux) 424 { 425 const struct pci_attach_args *pa = aux; 426 int i; 427 428 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_ATI) 429 return 0; 430 431 for (i = 0; radeonfb_devices[i].devid; i++) { 432 if (PCI_PRODUCT(pa->pa_id) == radeonfb_devices[i].devid) 433 return 100; /* high to defeat VGA/VESA */ 434 } 435 436 return 0; 437 } 438 439 static void 440 radeonfb_attach(device_t parent, device_t dev, void *aux) 441 { 442 struct radeonfb_softc *sc = device_private(dev); 443 const struct pci_attach_args *pa = aux; 444 const char *mptr; 445 bus_size_t bsz; 446 pcireg_t screg; 447 int i, j, fg, bg, ul, flags; 448 uint32_t v; 449 450 sc->sc_dev = dev; 451 sc->sc_id = pa->pa_id; 452 for (i = 0; radeonfb_devices[i].devid; i++) { 453 if (PCI_PRODUCT(sc->sc_id) == radeonfb_devices[i].devid) 454 break; 455 } 456 457 pci_aprint_devinfo(pa, NULL); 458 459 DPRINTF((prop_dictionary_externalize(device_properties(dev)))); 460 461 KASSERT(radeonfb_devices[i].devid != 0); 462 sc->sc_pt = pa->pa_tag; 463 sc->sc_iot = pa->pa_iot; 464 sc->sc_pc = pa->pa_pc; 465 sc->sc_family = radeonfb_devices[i].family; 466 sc->sc_flags = radeonfb_devices[i].flags; 467 468 /* enable memory and IO access */ 469 screg = pci_conf_read(sc->sc_pc, sc->sc_pt, PCI_COMMAND_STATUS_REG); 470 screg |= PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE; 471 pci_conf_write(sc->sc_pc, sc->sc_pt, PCI_COMMAND_STATUS_REG, screg); 472 473 /* 474 * Some flags are general to entire chip families, and rather 475 * than clutter up the table with them, we go ahead and set 476 * them here. 477 */ 478 switch (sc->sc_family) { 479 case RADEON_RS100: 480 case RADEON_RS200: 481 sc->sc_flags |= RFB_IGP | RFB_RV100; 482 break; 483 484 case RADEON_RV100: 485 case RADEON_RV200: 486 case RADEON_RV250: 487 case RADEON_RV280: 488 sc->sc_flags |= RFB_RV100; 489 break; 490 491 case RADEON_RS300: 492 sc->sc_flags |= RFB_SDAC | RFB_IGP | RFB_RV100; 493 break; 494 495 case RADEON_R300: 496 case RADEON_RV350: 497 case RADEON_R350: 498 case RADEON_RV380: 499 case RADEON_R420: 500 /* newer chips */ 501 sc->sc_flags |= RFB_R300; 502 break; 503 504 case RADEON_R100: 505 sc->sc_flags |= RFB_NCRTC2; 506 break; 507 } 508 509 if ((sc->sc_family == RADEON_RV200) || 510 (sc->sc_family == RADEON_RV250) || 511 (sc->sc_family == RADEON_RV280) || 512 (sc->sc_family == RADEON_RV350)) { 513 bool inverted = 0; 514 /* backlight level is linear */ 515 DPRINTF(("found RV* chip, backlight is supposedly linear\n")); 516 prop_dictionary_get_bool(device_properties(sc->sc_dev), 517 "backlight_level_reverted", &inverted); 518 if (inverted) { 519 DPRINTF(("nope, it's inverted\n")); 520 sc->sc_flags |= RFB_INV_BLIGHT; 521 } 522 } else 523 sc->sc_flags |= RFB_INV_BLIGHT; 524 525 /* 526 * XXX: to support true multihead, this must change. 527 */ 528 sc->sc_ndisplays = 1; 529 530 /* XXX: */ 531 if (!HAS_CRTC2(sc)) { 532 sc->sc_ndisplays = 1; 533 } 534 535 if (pci_mapreg_map(pa, RADEON_MAPREG_MMIO, PCI_MAPREG_TYPE_MEM, 0, 536 &sc->sc_regt, &sc->sc_regh, &sc->sc_regaddr, 537 &sc->sc_regsz) != 0) { 538 aprint_error("%s: unable to map registers!\n", XNAME(sc)); 539 goto error; 540 } 541 542 if (pci_mapreg_info(sc->sc_pc, sc->sc_pt, PCI_MAPREG_ROM, 543 PCI_MAPREG_TYPE_ROM, &sc->sc_romaddr, &sc->sc_romsz, &flags) != 0) 544 { 545 aprint_error("%s: unable to find ROM!\n", XNAME(sc)); 546 goto error; 547 } 548 sc->sc_romt = sc->sc_memt; 549 550 /* scratch register test... */ 551 if (radeonfb_scratch_test(sc, RADEON_BIOS_0_SCRATCH, 0x55555555) || 552 radeonfb_scratch_test(sc, RADEON_BIOS_0_SCRATCH, 0xaaaaaaaa)) { 553 aprint_error("%s: scratch register test failed!\n", XNAME(sc)); 554 goto error; 555 } 556 557 PRINTREG(RADEON_BIOS_4_SCRATCH); 558 PRINTREG(RADEON_FP_GEN_CNTL); 559 sc->sc_fp_gen_cntl = GET32(sc, RADEON_FP_GEN_CNTL); 560 PRINTREG(RADEON_FP2_GEN_CNTL); 561 PRINTREG(RADEON_TMDS_CNTL); 562 PRINTREG(RADEON_TMDS_TRANSMITTER_CNTL); 563 PRINTREG(RADEON_TMDS_PLL_CNTL); 564 PRINTREG(RADEON_LVDS_GEN_CNTL); 565 PRINTREG(RADEON_FP_HORZ_STRETCH); 566 PRINTREG(RADEON_FP_VERT_STRETCH); 567 568 /* XXX: RV100 specific */ 569 PUT32(sc, RADEON_TMDS_PLL_CNTL, 0xa27); 570 571 PATCH32(sc, RADEON_TMDS_TRANSMITTER_CNTL, 572 RADEON_TMDS_TRANSMITTER_PLLEN, 573 RADEON_TMDS_TRANSMITTER_PLLEN | RADEON_TMDS_TRANSMITTER_PLLRST); 574 575 radeonfb_i2c_init(sc); 576 577 radeonfb_loadbios(sc, pa); 578 579 #ifdef RADEONFB_BIOS_INIT 580 if (radeonfb_bios_init(sc)) { 581 aprint_error("%s: BIOS inititialization failed\n", XNAME(sc)); 582 } 583 #endif 584 585 if (radeonfb_getclocks(sc)) { 586 aprint_error("%s: Unable to get reference clocks from BIOS\n", 587 XNAME(sc)); 588 goto error; 589 } 590 591 if (radeonfb_gettmds(sc)) { 592 aprint_error("%s: Unable to identify TMDS PLL settings\n", 593 XNAME(sc)); 594 goto error; 595 } 596 597 aprint_verbose("%s: refclk = %d.%03d MHz, refdiv = %d " 598 "minpll = %d, maxpll = %d\n", XNAME(sc), 599 (int)sc->sc_refclk / 1000, (int)sc->sc_refclk % 1000, 600 (int)sc->sc_refdiv, (int)sc->sc_minpll, (int)sc->sc_maxpll); 601 602 radeonfb_getconnectors(sc); 603 604 radeonfb_set_fbloc(sc); 605 606 for (i = 0; radeonfb_limits[i].size; i++) { 607 if (sc->sc_memsz >= radeonfb_limits[i].size) { 608 sc->sc_maxx = radeonfb_limits[i].maxx; 609 sc->sc_maxy = radeonfb_limits[i].maxy; 610 sc->sc_maxbpp = radeonfb_limits[i].maxbpp; 611 /* framebuffer offset, start at a 4K page */ 612 sc->sc_fboffset = sc->sc_memsz / 613 radeonfb_limits[i].maxdisp; 614 /* 615 * we use the fbsize to figure out where we can store 616 * things like cursor data. 617 */ 618 sc->sc_fbsize = 619 ROUNDUP(ROUNDUP(sc->sc_maxx * sc->sc_maxbpp / 8 , 620 RADEON_STRIDEALIGN) * sc->sc_maxy, 621 4096); 622 break; 623 } 624 } 625 626 627 radeonfb_init_misc(sc); 628 radeonfb_init_palette(sc, 0); 629 if (HAS_CRTC2(sc)) 630 radeonfb_init_palette(sc, 1); 631 632 /* program the DAC wirings */ 633 for (i = 0; i < (HAS_CRTC2(sc) ? 2 : 1); i++) { 634 switch (sc->sc_ports[i].rp_dac_type) { 635 case RADEON_DAC_PRIMARY: 636 PATCH32(sc, RADEON_DAC_CNTL2, 637 i ? RADEON_DAC2_DAC_CLK_SEL : 0, 638 ~RADEON_DAC2_DAC_CLK_SEL); 639 break; 640 case RADEON_DAC_TVDAC: 641 /* we always use the TVDAC to drive a secondary analog 642 * CRT for now. if we ever support TV-out this will 643 * have to change. 644 */ 645 SET32(sc, RADEON_DAC_CNTL2, 646 RADEON_DAC2_DAC2_CLK_SEL); 647 PATCH32(sc, RADEON_DISP_HW_DEBUG, 648 i ? 0 : RADEON_CRT2_DISP1_SEL, 649 ~RADEON_CRT2_DISP1_SEL); 650 break; 651 } 652 } 653 PRINTREG(RADEON_DAC_CNTL2); 654 PRINTREG(RADEON_DISP_HW_DEBUG); 655 656 /* other DAC programming */ 657 v = GET32(sc, RADEON_DAC_CNTL); 658 v &= (RADEON_DAC_RANGE_CNTL_MASK | RADEON_DAC_BLANKING); 659 v |= RADEON_DAC_MASK_ALL | RADEON_DAC_8BIT_EN; 660 PUT32(sc, RADEON_DAC_CNTL, v); 661 PRINTREG(RADEON_DAC_CNTL); 662 663 /* XXX: this may need more investigation */ 664 PUT32(sc, RADEON_TV_DAC_CNTL, 0x00280203); 665 PRINTREG(RADEON_TV_DAC_CNTL); 666 667 /* enable TMDS */ 668 SET32(sc, RADEON_FP_GEN_CNTL, 669 RADEON_FP_TMDS_EN | 670 RADEON_FP_CRTC_DONT_SHADOW_VPAR | 671 RADEON_FP_CRTC_DONT_SHADOW_HEND); 672 /* 673 * XXX 674 * no idea why this is necessary - if I do not clear this bit on my 675 * iBook G4 the screen remains black, even though it's already clear. 676 * It needs to be set on my Sun XVR-100 for the DVI port to work 677 */ 678 if (sc->sc_fp_gen_cntl & RADEON_FP_SEL_CRTC2) { 679 SET32(sc, RADEON_FP_GEN_CNTL, RADEON_FP_SEL_CRTC2); 680 } else 681 CLR32(sc, RADEON_FP_GEN_CNTL, RADEON_FP_SEL_CRTC2); 682 683 if (HAS_CRTC2(sc)) 684 SET32(sc, RADEON_FP2_GEN_CNTL, RADEON_FP2_SRC_SEL_CRTC2); 685 686 /* 687 * we use bus_space_map instead of pci_mapreg, because we don't 688 * need the full aperature space. no point in wasting virtual 689 * address space we don't intend to use, right? 690 */ 691 if ((sc->sc_memsz < (4096 * 1024)) || 692 (pci_mapreg_info(sc->sc_pc, sc->sc_pt, RADEON_MAPREG_VRAM, 693 PCI_MAPREG_TYPE_MEM, &sc->sc_memaddr, &bsz, NULL) != 0) || 694 (bsz < sc->sc_memsz)) { 695 sc->sc_memsz = 0; 696 aprint_error("%s: Bad frame buffer configuration\n", 697 XNAME(sc)); 698 goto error; 699 } 700 701 /* 64 MB should be enough -- more just wastes map entries */ 702 if (sc->sc_memsz > (64 << 20)) 703 sc->sc_memsz = (64 << 20); 704 705 sc->sc_memt = pa->pa_memt; 706 if (bus_space_map(sc->sc_memt, sc->sc_memaddr, sc->sc_memsz, 707 BUS_SPACE_MAP_LINEAR, &sc->sc_memh) != 0) { 708 sc->sc_memsz = 0; 709 aprint_error("%s: Unable to map frame buffer\n", XNAME(sc)); 710 goto error; 711 } 712 713 aprint_normal("%s: %d MB aperture at 0x%08x, " 714 "%d KB registers at 0x%08x\n", XNAME(sc), 715 (int)sc->sc_memsz >> 20, (unsigned)sc->sc_memaddr, 716 (int)sc->sc_regsz >> 10, (unsigned)sc->sc_regaddr); 717 718 /* setup default video mode from devprop (allows PROM override) */ 719 sc->sc_defaultmode = radeonfb_default_mode; 720 if (prop_dictionary_get_cstring_nocopy(device_properties(sc->sc_dev), 721 "videomode", &mptr)) { 722 723 strncpy(sc->sc_modebuf, mptr, sizeof(sc->sc_modebuf)); 724 sc->sc_defaultmode = sc->sc_modebuf; 725 } 726 727 /* initialize some basic display parameters */ 728 for (i = 0; i < sc->sc_ndisplays; i++) { 729 struct radeonfb_display *dp = &sc->sc_displays[i]; 730 struct rasops_info *ri; 731 long defattr; 732 struct wsemuldisplaydev_attach_args aa; 733 734 /* 735 * Figure out how many "displays" (desktops) we are going to 736 * support. If more than one, then each CRTC gets its own 737 * programming. 738 * 739 * XXX: this code needs to change to support mergedfb. 740 * XXX: would be nice to allow this to be overridden 741 */ 742 if (HAS_CRTC2(sc) && (sc->sc_ndisplays == 1)) { 743 DPRINTF(("dual crtcs!\n")); 744 dp->rd_ncrtcs = 2; 745 dp->rd_crtcs[0].rc_number = 0; 746 dp->rd_crtcs[1].rc_number = 1; 747 } else { 748 dp->rd_ncrtcs = 1; 749 dp->rd_crtcs[0].rc_number = i; 750 } 751 752 /* set up port pointer */ 753 for (j = 0; j < dp->rd_ncrtcs; j++) { 754 dp->rd_crtcs[j].rc_port = 755 &sc->sc_ports[dp->rd_crtcs[j].rc_number]; 756 } 757 758 dp->rd_softc = sc; 759 dp->rd_wsmode = WSDISPLAYIO_MODE_EMUL; 760 dp->rd_bg = WS_DEFAULT_BG; 761 dp->rd_bpp = RADEONFB_DEFAULT_DEPTH; /* XXX */ 762 763 /* for text mode, we pick a resolution that won't 764 * require panning */ 765 radeonfb_pickres(dp, &dp->rd_virtx, &dp->rd_virty, 0); 766 767 aprint_normal("%s: display %d: " 768 "initial virtual resolution %dx%d at %d bpp\n", 769 XNAME(sc), i, dp->rd_virtx, dp->rd_virty, dp->rd_bpp); 770 771 /* now select the *video mode* that we will use */ 772 for (j = 0; j < dp->rd_ncrtcs; j++) { 773 const struct videomode *vmp; 774 vmp = radeonfb_port_mode(sc, dp->rd_crtcs[j].rc_port, 775 dp->rd_virtx, dp->rd_virty); 776 777 /* 778 * virtual resolution should be at least as high as 779 * physical 780 */ 781 if (dp->rd_virtx < vmp->hdisplay || 782 dp->rd_virty < vmp->vdisplay) { 783 dp->rd_virtx = vmp->hdisplay; 784 dp->rd_virty = vmp->vdisplay; 785 } 786 787 dp->rd_crtcs[j].rc_videomode = *vmp; 788 printf("%s: port %d: physical %dx%d %dHz\n", 789 XNAME(sc), j, vmp->hdisplay, vmp->vdisplay, 790 DIVIDE(DIVIDE(vmp->dot_clock * 1000, 791 vmp->htotal), vmp->vtotal)); 792 } 793 794 /* N.B.: radeon wants 64-byte aligned stride */ 795 dp->rd_stride = dp->rd_virtx * dp->rd_bpp / 8; 796 dp->rd_stride = ROUNDUP(dp->rd_stride, RADEON_STRIDEALIGN); 797 DPRINTF(("stride: %d\n", dp->rd_stride)); 798 799 dp->rd_offset = sc->sc_fboffset * i; 800 dp->rd_fbptr = (vaddr_t)bus_space_vaddr(sc->sc_memt, 801 sc->sc_memh) + dp->rd_offset; 802 dp->rd_curoff = sc->sc_fbsize; 803 dp->rd_curptr = dp->rd_fbptr + dp->rd_curoff; 804 805 DPRINTF(("fpbtr = %p\n", (void *)dp->rd_fbptr)); 806 807 switch (dp->rd_bpp) { 808 case 8: 809 dp->rd_format = 2; 810 break; 811 case 32: 812 dp->rd_format = 6; 813 break; 814 default: 815 aprint_error("%s: bad depth %d\n", XNAME(sc), 816 dp->rd_bpp); 817 goto error; 818 } 819 820 DPRINTF(("init engine\n")); 821 /* XXX: this seems suspicious - per display engine 822 initialization? */ 823 radeonfb_engine_init(dp); 824 825 /* copy the template into place */ 826 dp->rd_wsscreens_storage[0] = radeonfb_stdscreen; 827 dp->rd_wsscreens = dp->rd_wsscreens_storage; 828 829 /* and make up the list */ 830 dp->rd_wsscreenlist.nscreens = 1; 831 dp->rd_wsscreenlist.screens = (void *)&dp->rd_wsscreens; 832 833 vcons_init(&dp->rd_vd, dp, dp->rd_wsscreens, 834 &radeonfb_accessops); 835 836 dp->rd_vd.init_screen = radeonfb_init_screen; 837 838 #ifdef RADEONFB_DEBUG 839 dp->rd_virty -= 200; 840 #endif 841 842 dp->rd_console = 0; 843 prop_dictionary_get_bool(device_properties(sc->sc_dev), 844 "is_console", &dp->rd_console); 845 846 dp->rd_vscreen.scr_flags |= VCONS_SCREEN_IS_STATIC; 847 848 849 vcons_init_screen(&dp->rd_vd, &dp->rd_vscreen, 850 dp->rd_console, &defattr); 851 852 ri = &dp->rd_vscreen.scr_ri; 853 854 /* clear the screen */ 855 rasops_unpack_attr(defattr, &fg, &bg, &ul); 856 radeonfb_rectfill(dp, 0, 0, ri->ri_width, ri->ri_height, 857 ri->ri_devcmap[bg & 0xf]); 858 859 dp->rd_wsscreens->textops = &ri->ri_ops; 860 dp->rd_wsscreens->capabilities = ri->ri_caps; 861 dp->rd_wsscreens->nrows = ri->ri_rows; 862 dp->rd_wsscreens->ncols = ri->ri_cols; 863 864 #ifdef SPLASHSCREEN 865 dp->rd_splash.si_depth = ri->ri_depth; 866 dp->rd_splash.si_bits = ri->ri_bits; 867 dp->rd_splash.si_hwbits = ri->ri_hwbits; 868 dp->rd_splash.si_width = ri->ri_width; 869 dp->rd_splash.si_height = ri->ri_height; 870 dp->rd_splash.si_stride = ri->ri_stride; 871 dp->rd_splash.si_fillrect = NULL; 872 #endif 873 dp->rd_gc.gc_bitblt = radeonfb_bitblt; 874 dp->rd_gc.gc_rectfill = radeonfb_rectfill_a; 875 dp->rd_gc.gc_rop = RADEON_ROP3_S; 876 dp->rd_gc.gc_blitcookie = dp; 877 glyphcache_init(&dp->rd_gc, dp->rd_virty + 4, 878 (0x800000 / dp->rd_stride) - (dp->rd_virty + 4), 879 dp->rd_virtx, 880 ri->ri_font->fontwidth, 881 ri->ri_font->fontheight, 882 defattr); 883 if (dp->rd_console) { 884 885 radeonfb_modeswitch(dp); 886 wsdisplay_cnattach(dp->rd_wsscreens, ri, 0, 0, 887 defattr); 888 #ifdef SPLASHSCREEN 889 if (splash_render(&dp->rd_splash, 890 SPLASH_F_CENTER|SPLASH_F_FILL) == 0) 891 SCREEN_DISABLE_DRAWING(&dp->rd_vscreen); 892 else 893 #endif 894 vcons_replay_msgbuf(&dp->rd_vscreen); 895 } else { 896 897 /* 898 * since we're not the console we can postpone 899 * the rest until someone actually allocates a 900 * screen for us. but we do clear the screen 901 * at least. 902 */ 903 memset(ri->ri_bits, 0, 1024); 904 905 radeonfb_modeswitch(dp); 906 #ifdef SPLASHSCREEN 907 if (splash_render(&dp->rd_splash, 908 SPLASH_F_CENTER|SPLASH_F_FILL) == 0) 909 SCREEN_DISABLE_DRAWING(&dp->rd_vscreen); 910 #endif 911 } 912 913 aa.console = dp->rd_console; 914 aa.scrdata = &dp->rd_wsscreenlist; 915 aa.accessops = &radeonfb_accessops; 916 aa.accesscookie = &dp->rd_vd; 917 918 config_found(sc->sc_dev, &aa, wsemuldisplaydevprint); 919 920 radeonfb_blank(dp, 0); 921 922 /* Initialise delayed lvds operations for backlight. */ 923 callout_init(&dp->rd_bl_lvds_co, 0); 924 callout_setfunc(&dp->rd_bl_lvds_co, 925 radeonfb_lvds_callout, dp); 926 dp->rd_bl_on = 1; 927 dp->rd_bl_level = radeonfb_get_backlight(dp); 928 radeonfb_set_backlight(dp, dp->rd_bl_level); 929 } 930 931 /* 932 * if we have console output via firmware like on sparc64 it may 933 * interfere with DAC programming so program the palette again 934 * here after we took over 935 */ 936 radeonfb_init_palette(sc, 0); 937 if (HAS_CRTC2(sc)) 938 radeonfb_init_palette(sc, 1); 939 940 pmf_event_register(dev, PMFE_DISPLAY_BRIGHTNESS_UP, 941 radeonfb_brightness_up, TRUE); 942 pmf_event_register(dev, PMFE_DISPLAY_BRIGHTNESS_DOWN, 943 radeonfb_brightness_down, TRUE); 944 945 config_found_ia(dev, "drm", aux, radeonfb_drm_print); 946 947 return; 948 949 error: 950 if (sc->sc_biossz) 951 free(sc->sc_bios, M_DEVBUF); 952 953 if (sc->sc_regsz) 954 bus_space_unmap(sc->sc_regt, sc->sc_regh, sc->sc_regsz); 955 956 if (sc->sc_memsz) 957 bus_space_unmap(sc->sc_memt, sc->sc_memh, sc->sc_memsz); 958 } 959 960 static void 961 radeonfb_map(struct radeonfb_softc *sc) 962 { 963 if (bus_space_map(sc->sc_regt, sc->sc_regaddr, sc->sc_regsz, 0, 964 &sc->sc_regh) != 0) { 965 aprint_error("%s: unable to map registers!\n", XNAME(sc)); 966 return; 967 } 968 if (bus_space_map(sc->sc_memt, sc->sc_memaddr, sc->sc_memsz, 969 BUS_SPACE_MAP_LINEAR, &sc->sc_memh) != 0) { 970 sc->sc_memsz = 0; 971 aprint_error("%s: Unable to map frame buffer\n", XNAME(sc)); 972 return; 973 } 974 } 975 976 static void 977 radeonfb_unmap(struct radeonfb_softc *sc) 978 { 979 bus_space_unmap(sc->sc_regt, sc->sc_regh, sc->sc_regsz); 980 bus_space_unmap(sc->sc_memt, sc->sc_memh, sc->sc_memsz); 981 } 982 983 static int 984 radeonfb_drm_print(void *aux, const char *pnp) 985 { 986 if (pnp) 987 aprint_normal("drm at %s", pnp); 988 return (UNCONF); 989 } 990 991 int 992 radeonfb_ioctl(void *v, void *vs, 993 unsigned long cmd, void *d, int flag, struct lwp *l) 994 { 995 struct vcons_data *vd; 996 struct radeonfb_display *dp; 997 struct radeonfb_softc *sc; 998 struct wsdisplay_param *param; 999 1000 vd = (struct vcons_data *)v; 1001 dp = (struct radeonfb_display *)vd->cookie; 1002 sc = dp->rd_softc; 1003 1004 switch (cmd) { 1005 case WSDISPLAYIO_GTYPE: 1006 *(unsigned *)d = WSDISPLAY_TYPE_PCIMISC; 1007 return 0; 1008 1009 case WSDISPLAYIO_GINFO: 1010 if (vd->active != NULL) { 1011 struct wsdisplay_fbinfo *fb; 1012 fb = (struct wsdisplay_fbinfo *)d; 1013 fb->width = dp->rd_virtx; 1014 fb->height = dp->rd_virty; 1015 fb->depth = dp->rd_bpp; 1016 fb->cmsize = 256; 1017 return 0; 1018 } else 1019 return ENODEV; 1020 case WSDISPLAYIO_GVIDEO: 1021 if (radeonfb_isblank(dp)) 1022 *(unsigned *)d = WSDISPLAYIO_VIDEO_OFF; 1023 else 1024 *(unsigned *)d = WSDISPLAYIO_VIDEO_ON; 1025 return 0; 1026 1027 case WSDISPLAYIO_SVIDEO: 1028 radeonfb_blank(dp, 1029 (*(unsigned int *)d == WSDISPLAYIO_VIDEO_OFF)); 1030 return 0; 1031 1032 case WSDISPLAYIO_GETCMAP: 1033 #if 0 1034 if (dp->rd_bpp == 8) 1035 return radeonfb_getcmap(sc, 1036 (struct wsdisplay_cmap *)d); 1037 #endif 1038 return EINVAL; 1039 1040 case WSDISPLAYIO_PUTCMAP: 1041 #if 0 1042 if (dp->rd_bpp == 8) 1043 return radeonfb_putcmap(sc, 1044 (struct wsdisplay_cmap *)d); 1045 #endif 1046 return EINVAL; 1047 1048 case WSDISPLAYIO_LINEBYTES: 1049 *(unsigned *)d = dp->rd_stride; 1050 return 0; 1051 1052 case WSDISPLAYIO_SMODE: 1053 if (*(int *)d != dp->rd_wsmode) { 1054 dp->rd_wsmode = *(int *)d; 1055 if ((dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) && 1056 (dp->rd_vd.active)) { 1057 radeonfb_map(sc); 1058 radeonfb_engine_init(dp); 1059 glyphcache_wipe(&dp->rd_gc); 1060 radeonfb_init_palette(sc, dp == &sc->sc_displays[0] ? 0 : 1); 1061 radeonfb_modeswitch(dp); 1062 vcons_redraw_screen(dp->rd_vd.active); 1063 } else { 1064 radeonfb_unmap(sc); 1065 } 1066 } 1067 return 0; 1068 1069 case WSDISPLAYIO_GCURMAX: 1070 ((struct wsdisplay_curpos *)d)->x = RADEON_CURSORMAXX; 1071 ((struct wsdisplay_curpos *)d)->y = RADEON_CURSORMAXY; 1072 return 0; 1073 1074 case WSDISPLAYIO_SCURSOR: 1075 return radeonfb_set_cursor(dp, (struct wsdisplay_cursor *)d); 1076 1077 case WSDISPLAYIO_GCURSOR: 1078 return EPASSTHROUGH; 1079 1080 case WSDISPLAYIO_GCURPOS: 1081 ((struct wsdisplay_curpos *)d)->x = dp->rd_cursor.rc_pos.x; 1082 ((struct wsdisplay_curpos *)d)->y = dp->rd_cursor.rc_pos.y; 1083 return 0; 1084 1085 case WSDISPLAYIO_SCURPOS: 1086 return radeonfb_set_curpos(dp, (struct wsdisplay_curpos *)d); 1087 1088 case WSDISPLAYIO_SSPLASH: 1089 #if defined(SPLASHSCREEN) 1090 if (*(int *)d == 1) { 1091 SCREEN_DISABLE_DRAWING(&dp->rd_vscreen); 1092 splash_render(&dp->rd_splash, 1093 SPLASH_F_CENTER|SPLASH_F_FILL); 1094 } else 1095 SCREEN_ENABLE_DRAWING(&dp->rd_vscreen); 1096 return 0; 1097 #else 1098 return ENODEV; 1099 #endif 1100 case WSDISPLAYIO_GETPARAM: 1101 param = (struct wsdisplay_param *)d; 1102 switch (param->param) { 1103 case WSDISPLAYIO_PARAM_BRIGHTNESS: 1104 param->min = 0; 1105 param->max = 255; 1106 param->curval = dp->rd_bl_level; 1107 return 0; 1108 case WSDISPLAYIO_PARAM_BACKLIGHT: 1109 param->min = 0; 1110 param->max = RADEONFB_BACKLIGHT_MAX; 1111 param->curval = dp->rd_bl_on; 1112 return 0; 1113 } 1114 return EPASSTHROUGH; 1115 1116 case WSDISPLAYIO_SETPARAM: 1117 param = (struct wsdisplay_param *)d; 1118 switch (param->param) { 1119 case WSDISPLAYIO_PARAM_BRIGHTNESS: 1120 radeonfb_set_backlight(dp, param->curval); 1121 return 0; 1122 case WSDISPLAYIO_PARAM_BACKLIGHT: 1123 radeonfb_switch_backlight(dp, param->curval); 1124 return 0; 1125 } 1126 return EPASSTHROUGH; 1127 1128 /* PCI config read/write passthrough. */ 1129 case PCI_IOC_CFGREAD: 1130 case PCI_IOC_CFGWRITE: 1131 return pci_devioctl(sc->sc_pc, sc->sc_pt, cmd, d, flag, l); 1132 1133 case WSDISPLAYIO_GET_BUSID: 1134 return wsdisplayio_busid_pci(sc->sc_dev, sc->sc_pc, 1135 sc->sc_pt, d); 1136 1137 case WSDISPLAYIO_GET_EDID: { 1138 struct wsdisplayio_edid_info *ei = d; 1139 return wsdisplayio_get_edid(sc->sc_dev, ei); 1140 } 1141 1142 default: 1143 return EPASSTHROUGH; 1144 } 1145 } 1146 1147 paddr_t 1148 radeonfb_mmap(void *v, void *vs, off_t offset, int prot) 1149 { 1150 struct vcons_data *vd; 1151 struct radeonfb_display *dp; 1152 struct radeonfb_softc *sc; 1153 paddr_t pa; 1154 1155 vd = (struct vcons_data *)v; 1156 dp = (struct radeonfb_display *)vd->cookie; 1157 sc = dp->rd_softc; 1158 1159 /* XXX: note that we don't allow mapping of registers right now */ 1160 /* XXX: this means that the XFree86 radeon driver won't work */ 1161 if ((offset >= 0) && (offset < (dp->rd_virty * dp->rd_stride))) { 1162 pa = bus_space_mmap(sc->sc_memt, 1163 sc->sc_memaddr + dp->rd_offset + offset, 0, 1164 prot, BUS_SPACE_MAP_LINEAR); 1165 return pa; 1166 } 1167 1168 #ifdef RADEONFB_MMAP_BARS 1169 /* 1170 * restrict all other mappings to processes with superuser privileges 1171 * or the kernel itself 1172 */ 1173 if (kauth_authorize_machdep(kauth_cred_get(), KAUTH_MACHDEP_UNMANAGEDMEM, 1174 NULL, NULL, NULL, NULL) != 0) { 1175 aprint_error_dev(sc->sc_dev, "mmap() rejected.\n"); 1176 return -1; 1177 } 1178 1179 if ((offset >= sc->sc_regaddr) && 1180 (offset < sc->sc_regaddr + sc->sc_regsz)) { 1181 return bus_space_mmap(sc->sc_regt, offset, 0, prot, 1182 BUS_SPACE_MAP_LINEAR); 1183 } 1184 1185 if ((offset >= sc->sc_memaddr) && 1186 (offset < sc->sc_memaddr + sc->sc_memsz)) { 1187 return bus_space_mmap(sc->sc_memt, offset, 0, prot, 1188 BUS_SPACE_MAP_LINEAR); 1189 } 1190 1191 if ((offset >= sc->sc_romaddr) && 1192 (offset < sc->sc_romaddr + sc->sc_romsz)) { 1193 return bus_space_mmap(sc->sc_memt, offset, 0, prot, 1194 BUS_SPACE_MAP_LINEAR); 1195 } 1196 1197 #ifdef PCI_MAGIC_IO_RANGE 1198 /* allow mapping of IO space */ 1199 if ((offset >= PCI_MAGIC_IO_RANGE) && 1200 (offset < PCI_MAGIC_IO_RANGE + 0x10000)) { 1201 pa = bus_space_mmap(sc->sc_iot, offset - PCI_MAGIC_IO_RANGE, 1202 0, prot, 0); 1203 return pa; 1204 } 1205 #endif /* PCI_MAGIC_IO_RANGE */ 1206 1207 #endif /* RADEONFB_MMAP_BARS */ 1208 1209 return -1; 1210 } 1211 1212 static void 1213 radeonfb_loadbios(struct radeonfb_softc *sc, const struct pci_attach_args *pa) 1214 { 1215 bus_space_tag_t romt; 1216 bus_space_handle_t romh, biosh; 1217 bus_size_t romsz; 1218 bus_addr_t ptr; 1219 1220 if (pci_mapreg_map(pa, PCI_MAPREG_ROM, PCI_MAPREG_TYPE_ROM, 1221 BUS_SPACE_MAP_PREFETCHABLE, &romt, &romh, NULL, &romsz) != 0) { 1222 aprint_verbose("%s: unable to map BIOS!\n", XNAME(sc)); 1223 return; 1224 } 1225 1226 pci_find_rom(pa, romt, romh, PCI_ROM_CODE_TYPE_X86, &biosh, 1227 &sc->sc_biossz); 1228 if (sc->sc_biossz == 0) { 1229 aprint_verbose("%s: Video BIOS not present\n", XNAME(sc)); 1230 return; 1231 } 1232 1233 sc->sc_bios = malloc(sc->sc_biossz, M_DEVBUF, M_WAITOK); 1234 bus_space_read_region_1(romt, biosh, 0, sc->sc_bios, sc->sc_biossz); 1235 1236 /* unmap the PCI expansion rom */ 1237 bus_space_unmap(romt, romh, romsz); 1238 1239 /* turn off rom decoder now */ 1240 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM, 1241 pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM) & 1242 ~PCI_MAPREG_ROM_ENABLE); 1243 1244 ptr = GETBIOS16(sc, 0x48); 1245 if ((GETBIOS32(sc, ptr + 4) == 0x41544f4d /* "ATOM" */) || 1246 (GETBIOS32(sc, ptr + 4) == 0x4d4f5441 /* "MOTA" */)) { 1247 sc->sc_flags |= RFB_ATOM; 1248 } 1249 1250 aprint_verbose("%s: Found %d KB %s BIOS\n", XNAME(sc), 1251 (unsigned)sc->sc_biossz >> 10, IS_ATOM(sc) ? "ATOM" : "Legacy"); 1252 } 1253 1254 1255 uint32_t 1256 radeonfb_get32(struct radeonfb_softc *sc, uint32_t reg) 1257 { 1258 1259 return bus_space_read_4(sc->sc_regt, sc->sc_regh, reg); 1260 } 1261 1262 void 1263 radeonfb_put32(struct radeonfb_softc *sc, uint32_t reg, uint32_t val) 1264 { 1265 1266 bus_space_write_4(sc->sc_regt, sc->sc_regh, reg, val); 1267 } 1268 1269 void 1270 radeonfb_put32s(struct radeonfb_softc *sc, uint32_t reg, uint32_t val) 1271 { 1272 1273 bus_space_write_stream_4(sc->sc_regt, sc->sc_regh, reg, val); 1274 } 1275 1276 void 1277 radeonfb_mask32(struct radeonfb_softc *sc, uint32_t reg, 1278 uint32_t andmask, uint32_t ormask) 1279 { 1280 int s; 1281 uint32_t val; 1282 1283 s = splhigh(); 1284 val = radeonfb_get32(sc, reg); 1285 val = (val & andmask) | ormask; 1286 radeonfb_put32(sc, reg, val); 1287 splx(s); 1288 } 1289 1290 uint32_t 1291 radeonfb_getindex(struct radeonfb_softc *sc, uint32_t idx) 1292 { 1293 int s; 1294 uint32_t val; 1295 1296 s = splhigh(); 1297 radeonfb_put32(sc, RADEON_MM_INDEX, idx); 1298 val = radeonfb_get32(sc, RADEON_MM_DATA); 1299 splx(s); 1300 1301 return (val); 1302 } 1303 1304 void 1305 radeonfb_putindex(struct radeonfb_softc *sc, uint32_t idx, uint32_t val) 1306 { 1307 int s; 1308 1309 s = splhigh(); 1310 radeonfb_put32(sc, RADEON_MM_INDEX, idx); 1311 radeonfb_put32(sc, RADEON_MM_DATA, val); 1312 splx(s); 1313 } 1314 1315 void 1316 radeonfb_maskindex(struct radeonfb_softc *sc, uint32_t idx, 1317 uint32_t andmask, uint32_t ormask) 1318 { 1319 int s; 1320 uint32_t val; 1321 1322 s = splhigh(); 1323 radeonfb_put32(sc, RADEON_MM_INDEX, idx); 1324 val = radeonfb_get32(sc, RADEON_MM_DATA); 1325 val = (val & andmask) | ormask; 1326 radeonfb_put32(sc, RADEON_MM_DATA, val); 1327 splx(s); 1328 } 1329 1330 uint32_t 1331 radeonfb_getpll(struct radeonfb_softc *sc, uint32_t idx) 1332 { 1333 int s; 1334 uint32_t val; 1335 1336 s = splhigh(); 1337 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, idx & 0x3f); 1338 val = radeonfb_get32(sc, RADEON_CLOCK_CNTL_DATA); 1339 if (HAS_R300CG(sc)) 1340 radeonfb_r300cg_workaround(sc); 1341 splx(s); 1342 1343 return (val); 1344 } 1345 1346 void 1347 radeonfb_putpll(struct radeonfb_softc *sc, uint32_t idx, uint32_t val) 1348 { 1349 int s; 1350 1351 s = splhigh(); 1352 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, (idx & 0x3f) | 1353 RADEON_PLL_WR_EN); 1354 radeonfb_put32(sc, RADEON_CLOCK_CNTL_DATA, val); 1355 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, 0); 1356 splx(s); 1357 } 1358 1359 void 1360 radeonfb_maskpll(struct radeonfb_softc *sc, uint32_t idx, 1361 uint32_t andmask, uint32_t ormask) 1362 { 1363 int s; 1364 uint32_t val; 1365 1366 s = splhigh(); 1367 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, (idx & 0x3f) | 1368 RADEON_PLL_WR_EN); 1369 val = radeonfb_get32(sc, RADEON_CLOCK_CNTL_DATA); 1370 val = (val & andmask) | ormask; 1371 radeonfb_put32(sc, RADEON_CLOCK_CNTL_DATA, val); 1372 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, 0); 1373 splx(s); 1374 } 1375 1376 int 1377 radeonfb_scratch_test(struct radeonfb_softc *sc, int reg, uint32_t v) 1378 { 1379 uint32_t saved; 1380 1381 saved = GET32(sc, reg); 1382 PUT32(sc, reg, v); 1383 if (GET32(sc, reg) != v) { 1384 return -1; 1385 } 1386 PUT32(sc, reg, saved); 1387 return 0; 1388 } 1389 1390 uintmax_t 1391 radeonfb_getprop_num(struct radeonfb_softc *sc, const char *name, 1392 uintmax_t defval) 1393 { 1394 prop_number_t pn; 1395 pn = prop_dictionary_get(device_properties(sc->sc_dev), name); 1396 if (pn == NULL) { 1397 return defval; 1398 } 1399 KASSERT(prop_object_type(pn) == PROP_TYPE_NUMBER); 1400 return (prop_number_integer_value(pn)); 1401 } 1402 1403 int 1404 radeonfb_getclocks(struct radeonfb_softc *sc) 1405 { 1406 bus_addr_t ptr; 1407 int refclk = 0; 1408 int refdiv = 0; 1409 int minpll = 0; 1410 int maxpll = 0; 1411 1412 /* load initial property values if port/board provides them */ 1413 refclk = radeonfb_getprop_num(sc, "refclk", 0) & 0xffff; 1414 refdiv = radeonfb_getprop_num(sc, "refdiv", 0) & 0xffff; 1415 minpll = radeonfb_getprop_num(sc, "minpll", 0) & 0xffffffffU; 1416 maxpll = radeonfb_getprop_num(sc, "maxpll", 0) & 0xffffffffU; 1417 1418 if (refclk && refdiv && minpll && maxpll) 1419 goto dontprobe; 1420 1421 if (!sc->sc_biossz) { 1422 /* no BIOS */ 1423 aprint_verbose("%s: No video BIOS, using default clocks\n", 1424 XNAME(sc)); 1425 if (IS_IGP(sc)) 1426 refclk = refclk ? refclk : 1432; 1427 else 1428 refclk = refclk ? refclk : 2700; 1429 refdiv = refdiv ? refdiv : 12; 1430 minpll = minpll ? minpll : 12500; 1431 maxpll = maxpll ? maxpll : 35000; 1432 } else if (IS_ATOM(sc)) { 1433 /* ATOM BIOS */ 1434 ptr = GETBIOS16(sc, 0x48); 1435 ptr = GETBIOS16(sc, ptr + 32); /* aka MasterDataStart */ 1436 ptr = GETBIOS16(sc, ptr + 12); /* pll info block */ 1437 refclk = refclk ? refclk : GETBIOS16(sc, ptr + 82); 1438 minpll = minpll ? minpll : GETBIOS16(sc, ptr + 78); 1439 maxpll = maxpll ? maxpll : GETBIOS16(sc, ptr + 32); 1440 /* 1441 * ATOM BIOS doesn't supply a reference divider, so we 1442 * have to probe for it. 1443 */ 1444 if (refdiv < 2) 1445 refdiv = GETPLL(sc, RADEON_PPLL_REF_DIV) & 1446 RADEON_PPLL_REF_DIV_MASK; 1447 /* 1448 * if probe is zero, just assume one that should work 1449 * for most parts 1450 */ 1451 if (refdiv < 2) 1452 refdiv = 12; 1453 1454 } else { 1455 /* Legacy BIOS */ 1456 ptr = GETBIOS16(sc, 0x48); 1457 ptr = GETBIOS16(sc, ptr + 0x30); 1458 refclk = refclk ? refclk : GETBIOS16(sc, ptr + 0x0E); 1459 refdiv = refdiv ? refdiv : GETBIOS16(sc, ptr + 0x10); 1460 minpll = minpll ? minpll : GETBIOS32(sc, ptr + 0x12); 1461 maxpll = maxpll ? maxpll : GETBIOS32(sc, ptr + 0x16); 1462 } 1463 1464 1465 dontprobe: 1466 sc->sc_refclk = refclk * 10; 1467 sc->sc_refdiv = refdiv; 1468 sc->sc_minpll = minpll * 10; 1469 sc->sc_maxpll = maxpll * 10; 1470 return 0; 1471 } 1472 1473 int 1474 radeonfb_calc_dividers(struct radeonfb_softc *sc, uint32_t dotclock, 1475 uint32_t *postdivbit, uint32_t *feedbackdiv) 1476 { 1477 int i; 1478 uint32_t outfreq; 1479 int div; 1480 1481 DPRINTF(("dot clock: %u\n", dotclock)); 1482 for (i = 0; (div = radeonfb_dividers[i].divider) != 0; i++) { 1483 outfreq = div * dotclock; 1484 if ((outfreq >= sc->sc_minpll) && 1485 (outfreq <= sc->sc_maxpll)) { 1486 DPRINTF(("outfreq: %u\n", outfreq)); 1487 *postdivbit = 1488 ((uint32_t)radeonfb_dividers[i].mask << 16); 1489 DPRINTF(("post divider: %d (mask %x)\n", div, 1490 *postdivbit)); 1491 break; 1492 } 1493 } 1494 1495 if (div == 0) 1496 return 1; 1497 1498 *feedbackdiv = DIVIDE(sc->sc_refdiv * outfreq, sc->sc_refclk); 1499 DPRINTF(("feedback divider: %d\n", *feedbackdiv)); 1500 return 0; 1501 } 1502 1503 #if 0 1504 #ifdef RADEONFB_DEBUG 1505 static void 1506 dump_buffer(const char *pfx, void *buffer, unsigned int size) 1507 { 1508 char asc[17]; 1509 unsigned ptr = (unsigned)buffer; 1510 char *start = (char *)(ptr & ~0xf); 1511 char *end = (char *)(ptr + size); 1512 1513 end = (char *)(((unsigned)end + 0xf) & ~0xf); 1514 1515 if (pfx == NULL) { 1516 pfx = ""; 1517 } 1518 1519 while (start < end) { 1520 unsigned offset = (unsigned)start & 0xf; 1521 if (offset == 0) { 1522 printf("%s%x: ", pfx, (unsigned)start); 1523 } 1524 if (((unsigned)start < ptr) || 1525 ((unsigned)start >= (ptr + size))) { 1526 printf(" "); 1527 asc[offset] = ' '; 1528 } else { 1529 printf("%02x", *(unsigned char *)start); 1530 if ((*start >= ' ') && (*start <= '~')) { 1531 asc[offset] = *start; 1532 } else { 1533 asc[offset] = '.'; 1534 } 1535 } 1536 asc[offset + 1] = 0; 1537 if (offset % 2) { 1538 printf(" "); 1539 } 1540 if (offset == 15) { 1541 printf(" %s\n", asc); 1542 } 1543 start++; 1544 } 1545 } 1546 #endif 1547 #endif 1548 1549 int 1550 radeonfb_getconnectors(struct radeonfb_softc *sc) 1551 { 1552 int i; 1553 int found = 0; 1554 1555 for (i = 0; i < 2; i++) { 1556 sc->sc_ports[i].rp_mon_type = RADEON_MT_UNKNOWN; 1557 sc->sc_ports[i].rp_ddc_type = RADEON_DDC_NONE; 1558 sc->sc_ports[i].rp_dac_type = RADEON_DAC_UNKNOWN; 1559 sc->sc_ports[i].rp_conn_type = RADEON_CONN_NONE; 1560 sc->sc_ports[i].rp_tmds_type = RADEON_TMDS_UNKNOWN; 1561 } 1562 1563 /* 1564 * This logic is borrowed from Xorg's radeon driver. 1565 */ 1566 if (!sc->sc_biossz) 1567 goto nobios; 1568 1569 if (IS_ATOM(sc)) { 1570 /* not done yet */ 1571 } else { 1572 uint16_t ptr; 1573 int port = 0; 1574 1575 ptr = GETBIOS16(sc, 0x48); 1576 ptr = GETBIOS16(sc, ptr + 0x50); 1577 for (i = 1; i < 4; i++) { 1578 uint16_t entry; 1579 uint8_t conn, ddc, dac, tmds; 1580 1581 /* 1582 * Parse the connector table. From reading the code, 1583 * it appears to made up of 16-bit entries for each 1584 * connector. The 16-bits are defined as: 1585 * 1586 * bits 12-15 - connector type (0 == end of table) 1587 * bits 8-11 - DDC type 1588 * bits 5-7 - ??? 1589 * bit 4 - TMDS type (1 = EXT, 0 = INT) 1590 * bits 1-3 - ??? 1591 * bit 0 - DAC, 1 = TVDAC, 0 = primary 1592 */ 1593 if (!GETBIOS8(sc, ptr + i * 2) && i > 1) 1594 break; 1595 entry = GETBIOS16(sc, ptr + i * 2); 1596 1597 conn = (entry >> 12) & 0xf; 1598 ddc = (entry >> 8) & 0xf; 1599 dac = (entry & 0x1) ? RADEON_DAC_TVDAC : 1600 RADEON_DAC_PRIMARY; 1601 tmds = ((entry >> 4) & 0x1) ? RADEON_TMDS_EXT : 1602 RADEON_TMDS_INT; 1603 1604 if (conn == RADEON_CONN_NONE) 1605 continue; /* no connector */ 1606 1607 if ((found > 0) && 1608 (sc->sc_ports[port].rp_ddc_type == ddc)) { 1609 /* duplicate entry for same connector */ 1610 continue; 1611 } 1612 1613 /* internal DDC_DVI port gets priority */ 1614 if ((ddc == RADEON_DDC_DVI) || (port == 1)) 1615 port = 0; 1616 else 1617 port = 1; 1618 1619 sc->sc_ports[port].rp_ddc_type = 1620 ddc > RADEON_DDC_CRT2 ? RADEON_DDC_NONE : ddc; 1621 sc->sc_ports[port].rp_dac_type = dac; 1622 sc->sc_ports[port].rp_conn_type = 1623 min(conn, RADEON_CONN_UNSUPPORTED) ; 1624 1625 sc->sc_ports[port].rp_tmds_type = tmds; 1626 1627 if ((conn != RADEON_CONN_DVI_I) && 1628 (conn != RADEON_CONN_DVI_D) && 1629 (tmds == RADEON_TMDS_INT)) 1630 sc->sc_ports[port].rp_tmds_type = 1631 RADEON_TMDS_UNKNOWN; 1632 1633 found += (port + 1); 1634 } 1635 } 1636 1637 nobios: 1638 if (!found) { 1639 DPRINTF(("No connector info in BIOS!\n")); 1640 /* default, port 0 = internal TMDS, port 1 = CRT */ 1641 sc->sc_ports[0].rp_mon_type = RADEON_MT_UNKNOWN; 1642 sc->sc_ports[0].rp_ddc_type = RADEON_DDC_DVI; 1643 sc->sc_ports[0].rp_dac_type = RADEON_DAC_TVDAC; 1644 sc->sc_ports[0].rp_conn_type = RADEON_CONN_DVI_D; 1645 sc->sc_ports[0].rp_tmds_type = RADEON_TMDS_INT; 1646 1647 sc->sc_ports[1].rp_mon_type = RADEON_MT_UNKNOWN; 1648 sc->sc_ports[1].rp_ddc_type = RADEON_DDC_VGA; 1649 sc->sc_ports[1].rp_dac_type = RADEON_DAC_PRIMARY; 1650 sc->sc_ports[1].rp_conn_type = RADEON_CONN_CRT; 1651 sc->sc_ports[1].rp_tmds_type = RADEON_TMDS_EXT; 1652 } 1653 1654 /* 1655 * Fixup for RS300/RS350/RS400 chips, that lack a primary DAC. 1656 * these chips should use TVDAC for the VGA port. 1657 */ 1658 if (HAS_SDAC(sc)) { 1659 if (sc->sc_ports[0].rp_conn_type == RADEON_CONN_CRT) { 1660 sc->sc_ports[0].rp_dac_type = RADEON_DAC_TVDAC; 1661 sc->sc_ports[1].rp_dac_type = RADEON_DAC_PRIMARY; 1662 } else { 1663 sc->sc_ports[1].rp_dac_type = RADEON_DAC_TVDAC; 1664 sc->sc_ports[0].rp_dac_type = RADEON_DAC_PRIMARY; 1665 } 1666 } else if (!HAS_CRTC2(sc)) { 1667 sc->sc_ports[0].rp_dac_type = RADEON_DAC_PRIMARY; 1668 } 1669 1670 for (i = 0; i < 2; i++) { 1671 char edid[128]; 1672 uint8_t ddc; 1673 struct edid_info *eip = &sc->sc_ports[i].rp_edid; 1674 prop_data_t edid_data; 1675 1676 DPRINTF(("Port #%d:\n", i)); 1677 DPRINTF((" conn = %d\n", sc->sc_ports[i].rp_conn_type)); 1678 DPRINTF((" ddc = %d\n", sc->sc_ports[i].rp_ddc_type)); 1679 DPRINTF((" dac = %d\n", sc->sc_ports[i].rp_dac_type)); 1680 DPRINTF((" tmds = %d\n", sc->sc_ports[i].rp_tmds_type)); 1681 1682 sc->sc_ports[i].rp_edid_valid = 0; 1683 /* first look for static EDID data */ 1684 if ((edid_data = prop_dictionary_get(device_properties( 1685 sc->sc_dev), "EDID")) != NULL) { 1686 1687 aprint_normal_dev(sc->sc_dev, "using static EDID\n"); 1688 memcpy(edid, prop_data_data_nocopy(edid_data), 128); 1689 if (edid_parse(edid, eip) == 0) { 1690 1691 sc->sc_ports[i].rp_edid_valid = 1; 1692 } 1693 } 1694 /* if we didn't find any we'll try to talk to the monitor */ 1695 if (sc->sc_ports[i].rp_edid_valid != 1) { 1696 1697 ddc = sc->sc_ports[i].rp_ddc_type; 1698 if (ddc != RADEON_DDC_NONE) { 1699 if ((radeonfb_i2c_read_edid(sc, ddc, edid) 1700 == 0) && (edid_parse(edid, eip) == 0)) { 1701 1702 sc->sc_ports[i].rp_edid_valid = 1; 1703 #ifdef RADEONFB_DEBUG 1704 edid_print(eip); 1705 #endif 1706 } 1707 } 1708 } 1709 } 1710 1711 return found; 1712 } 1713 1714 int 1715 radeonfb_gettmds(struct radeonfb_softc *sc) 1716 { 1717 int i; 1718 1719 if (!sc->sc_biossz) { 1720 goto nobios; 1721 } 1722 1723 if (IS_ATOM(sc)) { 1724 /* XXX: not done yet */ 1725 } else { 1726 uint16_t ptr; 1727 int n; 1728 1729 ptr = GETBIOS16(sc, 0x48); 1730 ptr = GETBIOS16(sc, ptr + 0x34); 1731 DPRINTF(("DFP table revision %d\n", GETBIOS8(sc, ptr))); 1732 if (GETBIOS8(sc, ptr) == 3) { 1733 /* revision three table */ 1734 n = GETBIOS8(sc, ptr + 5) + 1; 1735 n = min(n, 4); 1736 1737 memset(sc->sc_tmds_pll, 0, sizeof (sc->sc_tmds_pll)); 1738 for (i = 0; i < n; i++) { 1739 sc->sc_tmds_pll[i].rtp_pll = GETBIOS32(sc, 1740 ptr + i * 10 + 8); 1741 sc->sc_tmds_pll[i].rtp_freq = GETBIOS16(sc, 1742 ptr + i * 10 + 0x10); 1743 DPRINTF(("TMDS_PLL dot clock %d pll %x\n", 1744 sc->sc_tmds_pll[i].rtp_freq, 1745 sc->sc_tmds_pll[i].rtp_pll)); 1746 } 1747 return 0; 1748 } 1749 } 1750 1751 nobios: 1752 DPRINTF(("no suitable DFP table present\n")); 1753 for (i = 0; 1754 i < sizeof (radeonfb_tmds_pll) / sizeof (radeonfb_tmds_pll[0]); 1755 i++) { 1756 int j; 1757 1758 if (radeonfb_tmds_pll[i].family != sc->sc_family) 1759 continue; 1760 1761 for (j = 0; j < 4; j++) { 1762 sc->sc_tmds_pll[j] = radeonfb_tmds_pll[i].plls[j]; 1763 DPRINTF(("TMDS_PLL dot clock %d pll %x\n", 1764 sc->sc_tmds_pll[j].rtp_freq, 1765 sc->sc_tmds_pll[j].rtp_pll)); 1766 } 1767 return 0; 1768 } 1769 1770 return -1; 1771 } 1772 1773 const struct videomode * 1774 radeonfb_modelookup(const char *name) 1775 { 1776 int i; 1777 1778 for (i = 0; i < videomode_count; i++) 1779 if (!strcmp(name, videomode_list[i].name)) 1780 return &videomode_list[i]; 1781 1782 return NULL; 1783 } 1784 1785 void 1786 radeonfb_pllwriteupdate(struct radeonfb_softc *sc, int crtc) 1787 { 1788 if (crtc) { 1789 while (GETPLL(sc, RADEON_P2PLL_REF_DIV) & 1790 RADEON_P2PLL_ATOMIC_UPDATE_R); 1791 SETPLL(sc, RADEON_P2PLL_REF_DIV, RADEON_P2PLL_ATOMIC_UPDATE_W); 1792 } else { 1793 while (GETPLL(sc, RADEON_PPLL_REF_DIV) & 1794 RADEON_PPLL_ATOMIC_UPDATE_R); 1795 SETPLL(sc, RADEON_PPLL_REF_DIV, RADEON_PPLL_ATOMIC_UPDATE_W); 1796 } 1797 } 1798 1799 void 1800 radeonfb_pllwaitatomicread(struct radeonfb_softc *sc, int crtc) 1801 { 1802 int i; 1803 1804 for (i = 10000; i; i--) { 1805 if (crtc) { 1806 if (GETPLL(sc, RADEON_P2PLL_REF_DIV) & 1807 RADEON_P2PLL_ATOMIC_UPDATE_R) 1808 break; 1809 } else { 1810 if (GETPLL(sc, RADEON_PPLL_REF_DIV) & 1811 RADEON_PPLL_ATOMIC_UPDATE_R) 1812 break; 1813 } 1814 } 1815 } 1816 1817 void 1818 radeonfb_program_vclk(struct radeonfb_softc *sc, int dotclock, int crtc) 1819 { 1820 uint32_t pbit = 0; 1821 uint32_t feed = 0; 1822 uint32_t data; 1823 #if 1 1824 int i; 1825 #endif 1826 1827 radeonfb_calc_dividers(sc, dotclock, &pbit, &feed); 1828 1829 if (crtc == 0) { 1830 1831 /* XXXX: mobility workaround missing */ 1832 /* XXXX: R300 stuff missing */ 1833 1834 PATCHPLL(sc, RADEON_VCLK_ECP_CNTL, 1835 RADEON_VCLK_SRC_SEL_CPUCLK, 1836 ~RADEON_VCLK_SRC_SEL_MASK); 1837 1838 /* put vclk into reset, use atomic updates */ 1839 SETPLL(sc, RADEON_PPLL_CNTL, 1840 RADEON_PPLL_REFCLK_SEL | 1841 RADEON_PPLL_FBCLK_SEL | 1842 RADEON_PPLL_RESET | 1843 RADEON_PPLL_ATOMIC_UPDATE_EN | 1844 RADEON_PPLL_VGA_ATOMIC_UPDATE_EN); 1845 1846 /* select clock 3 */ 1847 #if 0 1848 PATCH32(sc, RADEON_CLOCK_CNTL_INDEX, RADEON_PLL_DIV_SEL, 1849 ~RADEON_PLL_DIV_SEL); 1850 #else 1851 PATCH32(sc, RADEON_CLOCK_CNTL_INDEX, 0, 1852 ~RADEON_PLL_DIV_SEL); 1853 #endif 1854 1855 /* XXX: R300 family -- program divider differently? */ 1856 1857 /* program reference divider */ 1858 PATCHPLL(sc, RADEON_PPLL_REF_DIV, sc->sc_refdiv, 1859 ~RADEON_PPLL_REF_DIV_MASK); 1860 PRINTPLL(RADEON_PPLL_REF_DIV); 1861 1862 #if 0 1863 data = GETPLL(sc, RADEON_PPLL_DIV_3); 1864 data &= ~(RADEON_PPLL_FB3_DIV_MASK | 1865 RADEON_PPLL_POST3_DIV_MASK); 1866 data |= pbit; 1867 data |= (feed & RADEON_PPLL_FB3_DIV_MASK); 1868 PUTPLL(sc, RADEON_PPLL_DIV_3, data); 1869 #else 1870 for (i = 0; i < 4; i++) { 1871 } 1872 #endif 1873 1874 /* use the atomic update */ 1875 radeonfb_pllwriteupdate(sc, crtc); 1876 1877 /* and wait for it to complete */ 1878 radeonfb_pllwaitatomicread(sc, crtc); 1879 1880 /* program HTOTAL (why?) */ 1881 PUTPLL(sc, RADEON_HTOTAL_CNTL, 0); 1882 1883 /* drop reset */ 1884 CLRPLL(sc, RADEON_PPLL_CNTL, 1885 RADEON_PPLL_RESET | RADEON_PPLL_SLEEP | 1886 RADEON_PPLL_ATOMIC_UPDATE_EN | 1887 RADEON_PPLL_VGA_ATOMIC_UPDATE_EN); 1888 1889 PRINTPLL(RADEON_PPLL_CNTL); 1890 1891 /* give clock time to lock */ 1892 delay(50000); 1893 1894 PATCHPLL(sc, RADEON_VCLK_ECP_CNTL, 1895 RADEON_VCLK_SRC_SEL_PPLLCLK, 1896 ~RADEON_VCLK_SRC_SEL_MASK); 1897 1898 } else { 1899 1900 PATCHPLL(sc, RADEON_PIXCLKS_CNTL, 1901 RADEON_PIX2CLK_SRC_SEL_CPUCLK, 1902 ~RADEON_PIX2CLK_SRC_SEL_MASK); 1903 1904 /* put vclk into reset, use atomic updates */ 1905 SETPLL(sc, RADEON_P2PLL_CNTL, 1906 RADEON_P2PLL_RESET | 1907 RADEON_P2PLL_ATOMIC_UPDATE_EN | 1908 RADEON_P2PLL_VGA_ATOMIC_UPDATE_EN); 1909 1910 /* XXX: R300 family -- program divider differently? */ 1911 1912 /* program reference divider */ 1913 PATCHPLL(sc, RADEON_P2PLL_REF_DIV, sc->sc_refdiv, 1914 ~RADEON_P2PLL_REF_DIV_MASK); 1915 1916 /* program feedback and post dividers */ 1917 data = GETPLL(sc, RADEON_P2PLL_DIV_0); 1918 data &= ~(RADEON_P2PLL_FB0_DIV_MASK | 1919 RADEON_P2PLL_POST0_DIV_MASK); 1920 data |= pbit; 1921 data |= (feed & RADEON_P2PLL_FB0_DIV_MASK); 1922 PUTPLL(sc, RADEON_P2PLL_DIV_0, data); 1923 1924 /* use the atomic update */ 1925 radeonfb_pllwriteupdate(sc, crtc); 1926 1927 /* and wait for it to complete */ 1928 radeonfb_pllwaitatomicread(sc, crtc); 1929 1930 /* program HTOTAL (why?) */ 1931 PUTPLL(sc, RADEON_HTOTAL2_CNTL, 0); 1932 1933 /* drop reset */ 1934 CLRPLL(sc, RADEON_P2PLL_CNTL, 1935 RADEON_P2PLL_RESET | RADEON_P2PLL_SLEEP | 1936 RADEON_P2PLL_ATOMIC_UPDATE_EN | 1937 RADEON_P2PLL_VGA_ATOMIC_UPDATE_EN); 1938 1939 /* allow time for clock to lock */ 1940 delay(50000); 1941 1942 PATCHPLL(sc, RADEON_PIXCLKS_CNTL, 1943 RADEON_PIX2CLK_SRC_SEL_P2PLLCLK, 1944 ~RADEON_PIX2CLK_SRC_SEL_MASK); 1945 } 1946 PRINTREG(RADEON_CRTC_MORE_CNTL); 1947 } 1948 1949 void 1950 radeonfb_modeswitch(struct radeonfb_display *dp) 1951 { 1952 struct radeonfb_softc *sc = dp->rd_softc; 1953 int i; 1954 1955 /* blank the display while we switch modes */ 1956 radeonfb_blank(dp, 1); 1957 1958 #if 0 1959 SET32(sc, RADEON_CRTC_EXT_CNTL, 1960 RADEON_CRTC_VSYNC_DIS | RADEON_CRTC_HSYNC_DIS | 1961 RADEON_CRTC_DISPLAY_DIS /* | RADEON_CRTC_DISP_REQ_EN_B */); 1962 #endif 1963 1964 /* these registers might get in the way... */ 1965 PUT32(sc, RADEON_OVR_CLR, 0); 1966 PUT32(sc, RADEON_OVR_WID_LEFT_RIGHT, 0); 1967 PUT32(sc, RADEON_OVR_WID_TOP_BOTTOM, 0); 1968 PUT32(sc, RADEON_OV0_SCALE_CNTL, 0); 1969 PUT32(sc, RADEON_SUBPIC_CNTL, 0); 1970 PUT32(sc, RADEON_VIPH_CONTROL, 0); 1971 PUT32(sc, RADEON_I2C_CNTL_1, 0); 1972 PUT32(sc, RADEON_GEN_INT_CNTL, 0); 1973 PUT32(sc, RADEON_CAP0_TRIG_CNTL, 0); 1974 PUT32(sc, RADEON_CAP1_TRIG_CNTL, 0); 1975 PUT32(sc, RADEON_SURFACE_CNTL, 0); 1976 1977 for (i = 0; i < dp->rd_ncrtcs; i++) 1978 radeonfb_setcrtc(dp, i); 1979 1980 /* activate the display */ 1981 radeonfb_blank(dp, 0); 1982 } 1983 1984 void 1985 radeonfb_setcrtc(struct radeonfb_display *dp, int index) 1986 { 1987 int crtc; 1988 struct videomode *mode; 1989 struct radeonfb_softc *sc; 1990 struct radeonfb_crtc *cp; 1991 uint32_t v; 1992 uint32_t gencntl; 1993 uint32_t htotaldisp; 1994 uint32_t hsyncstrt; 1995 uint32_t vtotaldisp; 1996 uint32_t vsyncstrt; 1997 uint32_t fphsyncstrt; 1998 uint32_t fpvsyncstrt; 1999 uint32_t fphtotaldisp; 2000 uint32_t fpvtotaldisp; 2001 uint32_t pitch; 2002 2003 sc = dp->rd_softc; 2004 cp = &dp->rd_crtcs[index]; 2005 crtc = cp->rc_number; 2006 mode = &cp->rc_videomode; 2007 2008 #if 1 2009 pitch = dp->rd_stride / dp->rd_bpp; 2010 #else 2011 pitch = (((sc->sc_maxx * sc->sc_maxbpp) + ((sc->sc_maxbpp * 8) - 1)) / 2012 (sc->sc_maxbpp * 8)); 2013 #endif 2014 switch (crtc) { 2015 case 0: 2016 gencntl = RADEON_CRTC_GEN_CNTL; 2017 htotaldisp = RADEON_CRTC_H_TOTAL_DISP; 2018 hsyncstrt = RADEON_CRTC_H_SYNC_STRT_WID; 2019 vtotaldisp = RADEON_CRTC_V_TOTAL_DISP; 2020 vsyncstrt = RADEON_CRTC_V_SYNC_STRT_WID; 2021 fpvsyncstrt = RADEON_FP_V_SYNC_STRT_WID; 2022 fphsyncstrt = RADEON_FP_H_SYNC_STRT_WID; 2023 fpvtotaldisp = RADEON_FP_CRTC_V_TOTAL_DISP; 2024 fphtotaldisp = RADEON_FP_CRTC_H_TOTAL_DISP; 2025 break; 2026 case 1: 2027 gencntl = RADEON_CRTC2_GEN_CNTL; 2028 htotaldisp = RADEON_CRTC2_H_TOTAL_DISP; 2029 hsyncstrt = RADEON_CRTC2_H_SYNC_STRT_WID; 2030 vtotaldisp = RADEON_CRTC2_V_TOTAL_DISP; 2031 vsyncstrt = RADEON_CRTC2_V_SYNC_STRT_WID; 2032 fpvsyncstrt = RADEON_FP_V2_SYNC_STRT_WID; 2033 fphsyncstrt = RADEON_FP_H2_SYNC_STRT_WID; 2034 fpvtotaldisp = RADEON_FP_CRTC2_V_TOTAL_DISP; 2035 fphtotaldisp = RADEON_FP_CRTC2_H_TOTAL_DISP; 2036 break; 2037 default: 2038 panic("Bad CRTC!"); 2039 break; 2040 } 2041 2042 /* 2043 * CRTC_GEN_CNTL - depth, accelerator mode, etc. 2044 */ 2045 /* only bother with 32bpp and 8bpp */ 2046 v = dp->rd_format << RADEON_CRTC_PIX_WIDTH_SHIFT; 2047 2048 if (crtc == 1) { 2049 v |= RADEON_CRTC2_CRT2_ON | RADEON_CRTC2_EN; 2050 } else { 2051 v |= RADEON_CRTC_EXT_DISP_EN | RADEON_CRTC_EN; 2052 } 2053 2054 if (mode->flags & VID_DBLSCAN) 2055 v |= RADEON_CRTC2_DBL_SCAN_EN; 2056 2057 if (mode->flags & VID_INTERLACE) 2058 v |= RADEON_CRTC2_INTERLACE_EN; 2059 2060 if (mode->flags & VID_CSYNC) { 2061 v |= RADEON_CRTC2_CSYNC_EN; 2062 if (crtc == 1) 2063 v |= RADEON_CRTC2_VSYNC_TRISTAT; 2064 } 2065 2066 PUT32(sc, gencntl, v); 2067 DPRINTF(("CRTC%s_GEN_CNTL = %08x\n", crtc ? "2" : "", v)); 2068 2069 /* 2070 * CRTC_EXT_CNTL - preserve disable flags, set ATI linear and EXT_CNT 2071 */ 2072 v = GET32(sc, RADEON_CRTC_EXT_CNTL); 2073 if (crtc == 0) { 2074 v &= (RADEON_CRTC_VSYNC_DIS | RADEON_CRTC_HSYNC_DIS | 2075 RADEON_CRTC_DISPLAY_DIS); 2076 v |= RADEON_XCRT_CNT_EN | RADEON_VGA_ATI_LINEAR; 2077 if (mode->flags & VID_CSYNC) 2078 v |= RADEON_CRTC_VSYNC_TRISTAT; 2079 } 2080 /* unconditional turn on CRT, in case first CRTC is DFP */ 2081 v |= RADEON_CRTC_CRT_ON; 2082 PUT32(sc, RADEON_CRTC_EXT_CNTL, v); 2083 PRINTREG(RADEON_CRTC_EXT_CNTL); 2084 2085 /* 2086 * H_TOTAL_DISP 2087 */ 2088 v = ((mode->hdisplay / 8) - 1) << 16; 2089 v |= (mode->htotal / 8) - 1; 2090 PUT32(sc, htotaldisp, v); 2091 DPRINTF(("CRTC%s_H_TOTAL_DISP = %08x\n", crtc ? "2" : "", v)); 2092 PUT32(sc, fphtotaldisp, v); 2093 DPRINTF(("FP_H%s_TOTAL_DISP = %08x\n", crtc ? "2" : "", v)); 2094 2095 /* 2096 * H_SYNC_STRT_WID 2097 */ 2098 v = (((mode->hsync_end - mode->hsync_start) / 8) << 16); 2099 v |= mode->hsync_start; 2100 if (mode->flags & VID_NHSYNC) 2101 v |= RADEON_CRTC_H_SYNC_POL; 2102 PUT32(sc, hsyncstrt, v); 2103 DPRINTF(("CRTC%s_H_SYNC_STRT_WID = %08x\n", crtc ? "2" : "", v)); 2104 PUT32(sc, fphsyncstrt, v); 2105 DPRINTF(("FP_H%s_SYNC_STRT_WID = %08x\n", crtc ? "2" : "", v)); 2106 2107 /* 2108 * V_TOTAL_DISP 2109 */ 2110 v = ((mode->vdisplay - 1) << 16); 2111 v |= (mode->vtotal - 1); 2112 PUT32(sc, vtotaldisp, v); 2113 DPRINTF(("CRTC%s_V_TOTAL_DISP = %08x\n", crtc ? "2" : "", v)); 2114 PUT32(sc, fpvtotaldisp, v); 2115 DPRINTF(("FP_V%s_TOTAL_DISP = %08x\n", crtc ? "2" : "", v)); 2116 2117 /* 2118 * V_SYNC_STRT_WID 2119 */ 2120 v = ((mode->vsync_end - mode->vsync_start) << 16); 2121 v |= (mode->vsync_start - 1); 2122 if (mode->flags & VID_NVSYNC) 2123 v |= RADEON_CRTC_V_SYNC_POL; 2124 PUT32(sc, vsyncstrt, v); 2125 DPRINTF(("CRTC%s_V_SYNC_STRT_WID = %08x\n", crtc ? "2" : "", v)); 2126 PUT32(sc, fpvsyncstrt, v); 2127 DPRINTF(("FP_V%s_SYNC_STRT_WID = %08x\n", crtc ? "2" : "", v)); 2128 2129 radeonfb_program_vclk(sc, mode->dot_clock, crtc); 2130 2131 switch (crtc) { 2132 case 0: 2133 PUT32(sc, RADEON_CRTC_OFFSET, 0); 2134 PUT32(sc, RADEON_CRTC_OFFSET_CNTL, 0); 2135 PUT32(sc, RADEON_CRTC_PITCH, pitch); 2136 CLR32(sc, RADEON_DISP_MERGE_CNTL, RADEON_DISP_RGB_OFFSET_EN); 2137 2138 CLR32(sc, RADEON_CRTC_EXT_CNTL, 2139 RADEON_CRTC_VSYNC_DIS | RADEON_CRTC_HSYNC_DIS | 2140 RADEON_CRTC_DISPLAY_DIS /* | RADEON_CRTC_DISP_REQ_EN_B */); 2141 CLR32(sc, RADEON_CRTC_GEN_CNTL, RADEON_CRTC_DISP_REQ_EN_B); 2142 PRINTREG(RADEON_CRTC_EXT_CNTL); 2143 PRINTREG(RADEON_CRTC_GEN_CNTL); 2144 PRINTREG(RADEON_CLOCK_CNTL_INDEX); 2145 break; 2146 2147 case 1: 2148 PUT32(sc, RADEON_CRTC2_OFFSET, 0); 2149 PUT32(sc, RADEON_CRTC2_OFFSET_CNTL, 0); 2150 PUT32(sc, RADEON_CRTC2_PITCH, pitch); 2151 CLR32(sc, RADEON_DISP2_MERGE_CNTL, RADEON_DISP2_RGB_OFFSET_EN); 2152 CLR32(sc, RADEON_CRTC2_GEN_CNTL, 2153 RADEON_CRTC2_VSYNC_DIS | 2154 RADEON_CRTC2_HSYNC_DIS | 2155 RADEON_CRTC2_DISP_DIS | RADEON_CRTC2_DISP_REQ_EN_B); 2156 PRINTREG(RADEON_CRTC2_GEN_CNTL); 2157 break; 2158 } 2159 } 2160 2161 int 2162 radeonfb_isblank(struct radeonfb_display *dp) 2163 { 2164 uint32_t reg, mask; 2165 2166 if (dp->rd_crtcs[0].rc_number) { 2167 reg = RADEON_CRTC2_GEN_CNTL; 2168 mask = RADEON_CRTC2_DISP_DIS; 2169 } else { 2170 reg = RADEON_CRTC_EXT_CNTL; 2171 mask = RADEON_CRTC_DISPLAY_DIS; 2172 } 2173 return ((GET32(dp->rd_softc, reg) & mask) ? 1 : 0); 2174 } 2175 2176 void 2177 radeonfb_blank(struct radeonfb_display *dp, int blank) 2178 { 2179 struct radeonfb_softc *sc = dp->rd_softc; 2180 uint32_t reg, mask; 2181 uint32_t fpreg, fpval; 2182 int i; 2183 2184 for (i = 0; i < dp->rd_ncrtcs; i++) { 2185 2186 if (dp->rd_crtcs[i].rc_number) { 2187 reg = RADEON_CRTC2_GEN_CNTL; 2188 mask = RADEON_CRTC2_DISP_DIS; 2189 fpreg = RADEON_FP2_GEN_CNTL; 2190 fpval = RADEON_FP2_ON; 2191 } else { 2192 reg = RADEON_CRTC_EXT_CNTL; 2193 mask = RADEON_CRTC_DISPLAY_DIS; 2194 fpreg = RADEON_FP_GEN_CNTL; 2195 fpval = RADEON_FP_FPON; 2196 } 2197 2198 if (blank) { 2199 SET32(sc, reg, mask); 2200 CLR32(sc, fpreg, fpval); 2201 } else { 2202 CLR32(sc, reg, mask); 2203 SET32(sc, fpreg, fpval); 2204 } 2205 } 2206 PRINTREG(RADEON_FP_GEN_CNTL); 2207 PRINTREG(RADEON_FP2_GEN_CNTL); 2208 } 2209 2210 void 2211 radeonfb_init_screen(void *cookie, struct vcons_screen *scr, int existing, 2212 long *defattr) 2213 { 2214 struct radeonfb_display *dp = cookie; 2215 struct rasops_info *ri = &scr->scr_ri; 2216 2217 /* initialize font subsystem */ 2218 wsfont_init(); 2219 2220 DPRINTF(("init screen called, existing %d\n", existing)); 2221 2222 ri->ri_depth = dp->rd_bpp; 2223 ri->ri_width = dp->rd_virtx; 2224 ri->ri_height = dp->rd_virty; 2225 ri->ri_stride = dp->rd_stride; 2226 ri->ri_flg = RI_CENTER; 2227 switch (ri->ri_depth) { 2228 case 8: 2229 ri->ri_flg |= RI_ENABLE_ALPHA | RI_8BIT_IS_RGB; 2230 break; 2231 case 32: 2232 ri->ri_flg |= RI_ENABLE_ALPHA; 2233 /* we run radeons in RGB even on SPARC hardware */ 2234 ri->ri_rnum = 8; 2235 ri->ri_gnum = 8; 2236 ri->ri_bnum = 8; 2237 ri->ri_rpos = 16; 2238 ri->ri_gpos = 8; 2239 ri->ri_bpos = 0; 2240 break; 2241 } 2242 2243 ri->ri_bits = (void *)dp->rd_fbptr; 2244 2245 #ifdef VCONS_DRAW_INTR 2246 scr->scr_flags |= VCONS_DONT_READ; 2247 #endif 2248 2249 if (existing) { 2250 ri->ri_flg |= RI_CLEAR; 2251 2252 /* start a modeswitch now */ 2253 radeonfb_modeswitch(dp); 2254 } 2255 2256 /* 2257 * XXX: font selection should be based on properties, with some 2258 * normal/reasonable default. 2259 */ 2260 2261 /* initialize and look for an initial font */ 2262 rasops_init(ri, 0, 0); 2263 ri->ri_caps = WSSCREEN_UNDERLINE | WSSCREEN_HILIT | 2264 WSSCREEN_WSCOLORS | WSSCREEN_REVERSE; 2265 2266 rasops_reconfig(ri, dp->rd_virty / ri->ri_font->fontheight, 2267 dp->rd_virtx / ri->ri_font->fontwidth); 2268 2269 /* enable acceleration */ 2270 dp->rd_putchar = ri->ri_ops.putchar; 2271 ri->ri_ops.copyrows = radeonfb_copyrows; 2272 ri->ri_ops.copycols = radeonfb_copycols; 2273 ri->ri_ops.eraserows = radeonfb_eraserows; 2274 ri->ri_ops.erasecols = radeonfb_erasecols; 2275 /* pick a putchar method based on font and Radeon model */ 2276 if (ri->ri_font->stride < ri->ri_font->fontwidth) { 2277 /* got a bitmap font */ 2278 if (IS_R300(dp->rd_softc)) { 2279 /* 2280 * radeonfb_putchar() doesn't work right on some R3xx 2281 * so we use software drawing here, the wrapper just 2282 * makes sure the engine is idle before scribbling 2283 * into vram 2284 */ 2285 ri->ri_ops.putchar = radeonfb_putchar_wrapper; 2286 } else { 2287 ri->ri_ops.putchar = radeonfb_putchar; 2288 } 2289 } else { 2290 /* got an alpha font */ 2291 switch(ri->ri_depth) { 2292 case 32: 2293 ri->ri_ops.putchar = radeonfb_putchar_aa32; 2294 break; 2295 case 8: 2296 ri->ri_ops.putchar = radeonfb_putchar_aa8; 2297 break; 2298 default: 2299 /* XXX this should never happen */ 2300 panic("%s: depth is not 8 or 32 but we got an" \ 2301 " alpha font?!", __func__); 2302 } 2303 } 2304 ri->ri_ops.cursor = radeonfb_cursor; 2305 } 2306 2307 void 2308 radeonfb_set_fbloc(struct radeonfb_softc *sc) 2309 { 2310 uint32_t gen, ext, gen2 = 0; 2311 uint32_t agploc, aperbase, apersize, mcfbloc; 2312 2313 gen = GET32(sc, RADEON_CRTC_GEN_CNTL); 2314 ext = GET32(sc, RADEON_CRTC_EXT_CNTL); 2315 agploc = GET32(sc, RADEON_MC_AGP_LOCATION); 2316 aperbase = GET32(sc, RADEON_CONFIG_APER_0_BASE); 2317 apersize = GET32(sc, RADEON_CONFIG_APER_SIZE); 2318 2319 PUT32(sc, RADEON_CRTC_GEN_CNTL, gen | RADEON_CRTC_DISP_REQ_EN_B); 2320 PUT32(sc, RADEON_CRTC_EXT_CNTL, ext | RADEON_CRTC_DISPLAY_DIS); 2321 #if 0 2322 PUT32(sc, RADEON_CRTC_GEN_CNTL, gen | RADEON_CRTC_DISPLAY_DIS); 2323 PUT32(sc, RADEON_CRTC_EXT_CNTL, ext | RADEON_CRTC_DISP_REQ_EN_B); 2324 #endif 2325 2326 if (HAS_CRTC2(sc)) { 2327 gen2 = GET32(sc, RADEON_CRTC2_GEN_CNTL); 2328 PUT32(sc, RADEON_CRTC2_GEN_CNTL, 2329 gen2 | RADEON_CRTC2_DISP_REQ_EN_B); 2330 } 2331 2332 delay(100000); 2333 2334 mcfbloc = (aperbase >> 16) | 2335 ((aperbase + (apersize - 1)) & 0xffff0000); 2336 2337 sc->sc_aperbase = (mcfbloc & 0xffff) << 16; 2338 sc->sc_memsz = apersize; 2339 2340 if (((agploc & 0xffff) << 16) != 2341 ((mcfbloc & 0xffff0000U) + 0x10000)) { 2342 agploc = mcfbloc & 0xffff0000U; 2343 agploc |= ((agploc + 0x10000) >> 16); 2344 } 2345 2346 PUT32(sc, RADEON_HOST_PATH_CNTL, 0); 2347 2348 PUT32(sc, RADEON_MC_FB_LOCATION, mcfbloc); 2349 PUT32(sc, RADEON_MC_AGP_LOCATION, agploc); 2350 2351 DPRINTF(("aperbase = %u\n", aperbase)); 2352 PRINTREG(RADEON_MC_FB_LOCATION); 2353 PRINTREG(RADEON_MC_AGP_LOCATION); 2354 2355 PUT32(sc, RADEON_DISPLAY_BASE_ADDR, sc->sc_aperbase); 2356 2357 if (HAS_CRTC2(sc)) 2358 PUT32(sc, RADEON_DISPLAY2_BASE_ADDR, sc->sc_aperbase); 2359 2360 PUT32(sc, RADEON_OV0_BASE_ADDR, sc->sc_aperbase); 2361 2362 #if 0 2363 /* XXX: what is this AGP garbage? :-) */ 2364 PUT32(sc, RADEON_AGP_CNTL, 0x00100000); 2365 #endif 2366 2367 delay(100000); 2368 2369 PUT32(sc, RADEON_CRTC_GEN_CNTL, gen); 2370 PUT32(sc, RADEON_CRTC_EXT_CNTL, ext); 2371 2372 if (HAS_CRTC2(sc)) 2373 PUT32(sc, RADEON_CRTC2_GEN_CNTL, gen2); 2374 } 2375 2376 void 2377 radeonfb_init_misc(struct radeonfb_softc *sc) 2378 { 2379 PUT32(sc, RADEON_BUS_CNTL, 2380 RADEON_BUS_MASTER_DIS | 2381 RADEON_BUS_PREFETCH_MODE_ACT | 2382 RADEON_BUS_PCI_READ_RETRY_EN | 2383 RADEON_BUS_PCI_WRT_RETRY_EN | 2384 (3 << RADEON_BUS_RETRY_WS_SHIFT) | 2385 RADEON_BUS_MSTR_RD_MULT | 2386 RADEON_BUS_MSTR_RD_LINE | 2387 RADEON_BUS_RD_DISCARD_EN | 2388 RADEON_BUS_MSTR_DISCONNECT_EN | 2389 RADEON_BUS_READ_BURST); 2390 2391 PUT32(sc, RADEON_BUS_CNTL1, 0xf0); 2392 /* PUT32(sc, RADEON_SEPROM_CNTL1, 0x09ff0000); */ 2393 PUT32(sc, RADEON_FCP_CNTL, RADEON_FCP0_SRC_GND); 2394 PUT32(sc, RADEON_RBBM_CNTL, 2395 (3 << RADEON_RB_SETTLE_SHIFT) | 2396 (4 << RADEON_ABORTCLKS_HI_SHIFT) | 2397 (4 << RADEON_ABORTCLKS_CP_SHIFT) | 2398 (4 << RADEON_ABORTCLKS_CFIFO_SHIFT)); 2399 2400 /* XXX: figure out what these mean! */ 2401 PUT32(sc, RADEON_AGP_CNTL, 0x00100000); 2402 PUT32(sc, RADEON_HOST_PATH_CNTL, 0); 2403 #if 0 2404 PUT32(sc, RADEON_DISP_MISC_CNTL, 0x5bb00400); 2405 #endif 2406 2407 PUT32(sc, RADEON_GEN_INT_CNTL, 0); 2408 PUT32(sc, RADEON_GEN_INT_STATUS, GET32(sc, RADEON_GEN_INT_STATUS)); 2409 } 2410 2411 /* 2412 * This loads a linear color map for true color. 2413 */ 2414 void 2415 radeonfb_init_palette(struct radeonfb_softc *sc, int crtc) 2416 { 2417 int i; 2418 uint32_t vclk; 2419 2420 #define DAC_WIDTH ((1 << 10) - 1) 2421 #define CLUT_WIDTH ((1 << 8) - 1) 2422 #define CLUT_COLOR(i) ((i * DAC_WIDTH * 2 / CLUT_WIDTH + 1) / 2) 2423 2424 vclk = GETPLL(sc, RADEON_VCLK_ECP_CNTL); 2425 PUTPLL(sc, RADEON_VCLK_ECP_CNTL, vclk & ~RADEON_PIXCLK_DAC_ALWAYS_ONb); 2426 2427 if (crtc) 2428 SET32(sc, RADEON_DAC_CNTL2, RADEON_DAC2_PALETTE_ACC_CTL); 2429 else 2430 CLR32(sc, RADEON_DAC_CNTL2, RADEON_DAC2_PALETTE_ACC_CTL); 2431 2432 PUT32(sc, RADEON_PALETTE_INDEX, 0); 2433 if (sc->sc_displays[crtc].rd_bpp == 0) 2434 sc->sc_displays[crtc].rd_bpp = RADEONFB_DEFAULT_DEPTH; 2435 2436 if (sc->sc_displays[crtc].rd_bpp == 8) { 2437 /* ANSI palette */ 2438 int j = 0; 2439 uint32_t tmp, r, g, b; 2440 2441 for (i = 0; i <= CLUT_WIDTH; ++i) { 2442 tmp = i & 0xe0; 2443 /* 2444 * replicate bits so 0xe0 maps to a red value of 0xff 2445 * in order to make white look actually white 2446 */ 2447 tmp |= (tmp >> 3) | (tmp >> 6); 2448 r = tmp; 2449 2450 tmp = (i & 0x1c) << 3; 2451 tmp |= (tmp >> 3) | (tmp >> 6); 2452 g = tmp; 2453 2454 tmp = (i & 0x03) << 6; 2455 tmp |= tmp >> 2; 2456 tmp |= tmp >> 4; 2457 b = tmp; 2458 PUT32(sc, RADEON_PALETTE_30_DATA, 2459 (r << 22) | 2460 (g << 12) | 2461 (b << 2)); 2462 j += 3; 2463 } 2464 } else { 2465 /* linear ramp */ 2466 for (i = 0; i <= CLUT_WIDTH; ++i) { 2467 PUT32(sc, RADEON_PALETTE_30_DATA, 2468 (CLUT_COLOR(i) << 10) | 2469 (CLUT_COLOR(i) << 20) | 2470 (CLUT_COLOR(i))); 2471 } 2472 } 2473 2474 CLR32(sc, RADEON_DAC_CNTL2, RADEON_DAC2_PALETTE_ACC_CTL); 2475 PRINTREG(RADEON_DAC_CNTL2); 2476 2477 PUTPLL(sc, RADEON_VCLK_ECP_CNTL, vclk); 2478 } 2479 2480 /* 2481 * Bugs in some R300 hardware requires this when accessing CLOCK_CNTL_INDEX. 2482 */ 2483 void 2484 radeonfb_r300cg_workaround(struct radeonfb_softc *sc) 2485 { 2486 uint32_t tmp, save; 2487 2488 save = GET32(sc, RADEON_CLOCK_CNTL_INDEX); 2489 tmp = save & ~(0x3f | RADEON_PLL_WR_EN); 2490 PUT32(sc, RADEON_CLOCK_CNTL_INDEX, tmp); 2491 tmp = GET32(sc, RADEON_CLOCK_CNTL_DATA); 2492 PUT32(sc, RADEON_CLOCK_CNTL_INDEX, save); 2493 } 2494 2495 /* 2496 * Acceleration entry points. 2497 */ 2498 2499 /* this one draws characters using bitmap fonts */ 2500 static void 2501 radeonfb_putchar(void *cookie, int row, int col, u_int c, long attr) 2502 { 2503 struct rasops_info *ri = cookie; 2504 struct vcons_screen *scr = ri->ri_hw; 2505 struct radeonfb_display *dp = scr->scr_cookie; 2506 struct radeonfb_softc *sc = dp->rd_softc; 2507 struct wsdisplay_font *font = PICK_FONT(ri, c); 2508 uint32_t w, h; 2509 int xd, yd, offset, i; 2510 uint32_t bg, fg, gmc; 2511 uint32_t reg; 2512 uint8_t *data8; 2513 uint16_t *data16; 2514 void *data; 2515 2516 if (dp->rd_wsmode != WSDISPLAYIO_MODE_EMUL) 2517 return; 2518 2519 if (!CHAR_IN_FONT(c, font)) 2520 return; 2521 2522 w = font->fontwidth; 2523 h = font->fontheight; 2524 2525 bg = ri->ri_devcmap[(attr >> 16) & 0xf]; 2526 fg = ri->ri_devcmap[(attr >> 24) & 0xf]; 2527 2528 xd = ri->ri_xorigin + col * w; 2529 yd = ri->ri_yorigin + row * h; 2530 2531 if (c == 0x20) { 2532 radeonfb_rectfill(dp, xd, yd, w, h, bg); 2533 return; 2534 } 2535 data = WSFONT_GLYPH(c, font); 2536 2537 gmc = dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT; 2538 2539 radeonfb_wait_fifo(sc, 9); 2540 2541 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 2542 RADEON_GMC_BRUSH_NONE | 2543 RADEON_GMC_SRC_DATATYPE_MONO_FG_BG | 2544 RADEON_GMC_DST_CLIPPING | 2545 RADEON_ROP3_S | 2546 RADEON_DP_SRC_SOURCE_HOST_DATA | 2547 RADEON_GMC_CLR_CMP_CNTL_DIS | 2548 RADEON_GMC_WR_MSK_DIS | 2549 gmc); 2550 2551 PUT32(sc, RADEON_SC_LEFT, xd); 2552 PUT32(sc, RADEON_SC_RIGHT, xd + w); 2553 PUT32(sc, RADEON_DP_SRC_FRGD_CLR, fg); 2554 PUT32(sc, RADEON_DP_SRC_BKGD_CLR, bg); 2555 PUT32(sc, RADEON_DP_CNTL, 2556 RADEON_DST_X_LEFT_TO_RIGHT | 2557 RADEON_DST_Y_TOP_TO_BOTTOM); 2558 2559 PUT32(sc, RADEON_SRC_X_Y, 0); 2560 offset = 32 - (font->stride << 3); 2561 PUT32(sc, RADEON_DST_X_Y, ((xd - offset) << 16) | yd); 2562 PUT32(sc, RADEON_DST_WIDTH_HEIGHT, (32 << 16) | h); 2563 2564 radeonfb_wait_fifo(sc, h); 2565 switch (font->stride) { 2566 case 1: { 2567 data8 = data; 2568 for (i = 0; i < h; i++) { 2569 reg = *data8; 2570 bus_space_write_stream_4(sc->sc_regt, 2571 sc->sc_regh, RADEON_HOST_DATA0, reg); 2572 data8++; 2573 } 2574 break; 2575 } 2576 case 2: { 2577 data16 = data; 2578 for (i = 0; i < h; i++) { 2579 reg = *data16; 2580 bus_space_write_stream_4(sc->sc_regt, 2581 sc->sc_regh, RADEON_HOST_DATA0, reg); 2582 data16++; 2583 } 2584 break; 2585 } 2586 } 2587 if (attr & 1) 2588 radeonfb_rectfill(dp, xd, yd + h - 2, w, 1, fg); 2589 } 2590 2591 /* ... while this one is for anti-aliased ones */ 2592 static void 2593 radeonfb_putchar_aa32(void *cookie, int row, int col, u_int c, long attr) 2594 { 2595 struct rasops_info *ri = cookie; 2596 struct vcons_screen *scr = ri->ri_hw; 2597 struct radeonfb_display *dp = scr->scr_cookie; 2598 struct radeonfb_softc *sc = dp->rd_softc; 2599 struct wsdisplay_font *font = PICK_FONT(ri, c); 2600 uint32_t bg, fg, gmc; 2601 uint8_t *data; 2602 int w, h, xd, yd; 2603 int i, r, g, b, aval; 2604 int rf, gf, bf, rb, gb, bb; 2605 uint32_t pixel; 2606 int rv; 2607 2608 if (dp->rd_wsmode != WSDISPLAYIO_MODE_EMUL) 2609 return; 2610 2611 if (!CHAR_IN_FONT(c, font)) 2612 return; 2613 2614 w = font->fontwidth; 2615 h = font->fontheight; 2616 2617 bg = ri->ri_devcmap[(attr >> 16) & 0xf]; 2618 fg = ri->ri_devcmap[(attr >> 24) & 0xf]; 2619 2620 xd = ri->ri_xorigin + col * w; 2621 yd = ri->ri_yorigin + row * h; 2622 2623 if (c == 0x20) { 2624 radeonfb_rectfill(dp, xd, yd, w, h, bg); 2625 if (attr & 1) 2626 radeonfb_rectfill(dp, xd, yd + h - 2, w, 1, fg); 2627 return; 2628 } 2629 rv = glyphcache_try(&dp->rd_gc, c, xd, yd, attr); 2630 if (rv == GC_OK) 2631 return; 2632 2633 data = WSFONT_GLYPH(c, font); 2634 2635 gmc = dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT; 2636 2637 radeonfb_wait_fifo(sc, 5); 2638 2639 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 2640 RADEON_GMC_BRUSH_NONE | 2641 RADEON_GMC_SRC_DATATYPE_COLOR | 2642 RADEON_ROP3_S | 2643 RADEON_DP_SRC_SOURCE_HOST_DATA | 2644 RADEON_GMC_CLR_CMP_CNTL_DIS | 2645 RADEON_GMC_WR_MSK_DIS | 2646 gmc); 2647 2648 PUT32(sc, RADEON_DP_CNTL, 2649 RADEON_DST_X_LEFT_TO_RIGHT | 2650 RADEON_DST_Y_TOP_TO_BOTTOM); 2651 2652 PUT32(sc, RADEON_SRC_X_Y, 0); 2653 PUT32(sc, RADEON_DST_X_Y, (xd << 16) | yd); 2654 PUT32(sc, RADEON_DST_WIDTH_HEIGHT, (w << 16) | h); 2655 2656 rf = (fg >> 16) & 0xff; 2657 rb = (bg >> 16) & 0xff; 2658 gf = (fg >> 8) & 0xff; 2659 gb = (bg >> 8) & 0xff; 2660 bf = fg & 0xff; 2661 bb = bg & 0xff; 2662 2663 /* 2664 * I doubt we can upload data faster than even the slowest Radeon 2665 * could process them, especially when doing the alpha blending stuff 2666 * along the way, so just make sure there's some room in the FIFO and 2667 * then hammer away 2668 * As it turns out we can, so make periodic stops to let the FIFO 2669 * drain. 2670 */ 2671 radeonfb_wait_fifo(sc, 20); 2672 for (i = 0; i < ri->ri_fontscale; i++) { 2673 aval = *data; 2674 data++; 2675 if (aval == 0) { 2676 pixel = bg; 2677 } else if (aval == 255) { 2678 pixel = fg; 2679 } else { 2680 r = aval * rf + (255 - aval) * rb; 2681 g = aval * gf + (255 - aval) * gb; 2682 b = aval * bf + (255 - aval) * bb; 2683 pixel = (r & 0xff00) << 8 | 2684 (g & 0xff00) | 2685 (b & 0xff00) >> 8; 2686 } 2687 if (i & 16) 2688 radeonfb_wait_fifo(sc, 20); 2689 PUT32(sc, RADEON_HOST_DATA0, pixel); 2690 } 2691 if (rv == GC_ADD) { 2692 glyphcache_add(&dp->rd_gc, c, xd, yd); 2693 } else 2694 if (attr & 1) 2695 radeonfb_rectfill(dp, xd, yd + h - 2, w, 1, fg); 2696 2697 } 2698 2699 static void 2700 radeonfb_putchar_aa8(void *cookie, int row, int col, u_int c, long attr) 2701 { 2702 struct rasops_info *ri = cookie; 2703 struct vcons_screen *scr = ri->ri_hw; 2704 struct radeonfb_display *dp = scr->scr_cookie; 2705 struct radeonfb_softc *sc = dp->rd_softc; 2706 struct wsdisplay_font *font = PICK_FONT(ri, c); 2707 uint32_t bg, fg, latch = 0, bg8, fg8, pixel, gmc; 2708 int i, x, y, wi, he, r, g, b, aval; 2709 int r1, g1, b1, r0, g0, b0, fgo, bgo; 2710 uint8_t *data8; 2711 int rv, cnt; 2712 2713 if (dp->rd_wsmode != WSDISPLAYIO_MODE_EMUL) 2714 return; 2715 2716 if (!CHAR_IN_FONT(c, font)) 2717 return; 2718 2719 wi = font->fontwidth; 2720 he = font->fontheight; 2721 2722 bg = ri->ri_devcmap[(attr >> 16) & 0xf]; 2723 fg = ri->ri_devcmap[(attr >> 24) & 0xf]; 2724 2725 x = ri->ri_xorigin + col * wi; 2726 y = ri->ri_yorigin + row * he; 2727 2728 if (c == 0x20) { 2729 radeonfb_rectfill(dp, x, y, wi, he, bg); 2730 if (attr & 1) 2731 radeonfb_rectfill(dp, x, y + he - 2, wi, 1, fg); 2732 return; 2733 } 2734 rv = glyphcache_try(&dp->rd_gc, c, x, y, attr); 2735 if (rv == GC_OK) 2736 return; 2737 2738 data8 = WSFONT_GLYPH(c, font); 2739 2740 gmc = dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT; 2741 2742 radeonfb_wait_fifo(sc, 5); 2743 2744 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 2745 RADEON_GMC_BRUSH_NONE | 2746 RADEON_GMC_SRC_DATATYPE_COLOR | 2747 RADEON_ROP3_S | 2748 RADEON_DP_SRC_SOURCE_HOST_DATA | 2749 RADEON_GMC_CLR_CMP_CNTL_DIS | 2750 RADEON_GMC_WR_MSK_DIS | 2751 gmc); 2752 2753 PUT32(sc, RADEON_DP_CNTL, 2754 RADEON_DST_X_LEFT_TO_RIGHT | 2755 RADEON_DST_Y_TOP_TO_BOTTOM); 2756 2757 PUT32(sc, RADEON_SRC_X_Y, 0); 2758 PUT32(sc, RADEON_DST_X_Y, (x << 16) | y); 2759 PUT32(sc, RADEON_DST_WIDTH_HEIGHT, (wi << 16) | he); 2760 2761 /* 2762 * we need the RGB colours here, so get offsets into rasops_cmap 2763 */ 2764 fgo = ((attr >> 24) & 0xf) * 3; 2765 bgo = ((attr >> 16) & 0xf) * 3; 2766 2767 r0 = rasops_cmap[bgo]; 2768 r1 = rasops_cmap[fgo]; 2769 g0 = rasops_cmap[bgo + 1]; 2770 g1 = rasops_cmap[fgo + 1]; 2771 b0 = rasops_cmap[bgo + 2]; 2772 b1 = rasops_cmap[fgo + 2]; 2773 #define R3G3B2(r, g, b) ((r & 0xe0) | ((g >> 3) & 0x1c) | (b >> 6)) 2774 bg8 = R3G3B2(r0, g0, b0); 2775 fg8 = R3G3B2(r1, g1, b1); 2776 2777 radeonfb_wait_fifo(sc, 20); 2778 cnt = 0; 2779 for (i = 0; i < ri->ri_fontscale; i++) { 2780 aval = *data8; 2781 if (aval == 0) { 2782 pixel = bg8; 2783 } else if (aval == 255) { 2784 pixel = fg8; 2785 } else { 2786 r = aval * r1 + (255 - aval) * r0; 2787 g = aval * g1 + (255 - aval) * g0; 2788 b = aval * b1 + (255 - aval) * b0; 2789 pixel = ((r & 0xe000) >> 8) | 2790 ((g & 0xe000) >> 11) | 2791 ((b & 0xc000) >> 14); 2792 } 2793 latch = (latch << 8) | pixel; 2794 /* write in 32bit chunks */ 2795 if ((i & 3) == 3) { 2796 PUT32S(sc, RADEON_HOST_DATA0, latch); 2797 /* 2798 * not strictly necessary, old data should be shifted 2799 * out 2800 */ 2801 latch = 0; 2802 cnt++; 2803 if (cnt > 16) { 2804 cnt = 0; 2805 radeonfb_wait_fifo(sc, 20); 2806 } 2807 } 2808 data8++; 2809 } 2810 /* if we have pixels left in latch write them out */ 2811 if ((i & 3) != 0) { 2812 /* 2813 * radeon is weird - apparently leftover pixels are written 2814 * from the middle, not from the left as everything else 2815 */ 2816 PUT32(sc, RADEON_HOST_DATA0, latch); 2817 } 2818 2819 if (rv == GC_ADD) { 2820 glyphcache_add(&dp->rd_gc, c, x, y); 2821 } else 2822 if (attr & 1) 2823 radeonfb_rectfill(dp, x, y + he - 2, wi, 1, fg); 2824 2825 } 2826 2827 /* 2828 * wrapper for software character drawing 2829 * just sync the engine and call rasops*_putchar() 2830 */ 2831 2832 static void 2833 radeonfb_putchar_wrapper(void *cookie, int row, int col, u_int c, long attr) 2834 { 2835 struct rasops_info *ri = cookie; 2836 struct vcons_screen *scr = ri->ri_hw; 2837 struct radeonfb_display *dp = scr->scr_cookie; 2838 2839 radeonfb_engine_idle(dp->rd_softc); 2840 dp->rd_putchar(ri, row, col, c, attr); 2841 } 2842 2843 static void 2844 radeonfb_eraserows(void *cookie, int row, int nrows, long fillattr) 2845 { 2846 struct rasops_info *ri = cookie; 2847 struct vcons_screen *scr = ri->ri_hw; 2848 struct radeonfb_display *dp = scr->scr_cookie; 2849 uint32_t x, y, w, h, fg, bg, ul; 2850 2851 /* XXX: check for full emulation mode? */ 2852 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 2853 x = ri->ri_xorigin; 2854 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 2855 w = ri->ri_emuwidth; 2856 h = ri->ri_font->fontheight * nrows; 2857 2858 rasops_unpack_attr(fillattr, &fg, &bg, &ul); 2859 radeonfb_rectfill(dp, x, y, w, h, ri->ri_devcmap[bg & 0xf]); 2860 } 2861 } 2862 2863 static void 2864 radeonfb_copyrows(void *cookie, int srcrow, int dstrow, int nrows) 2865 { 2866 struct rasops_info *ri = cookie; 2867 struct vcons_screen *scr = ri->ri_hw; 2868 struct radeonfb_display *dp = scr->scr_cookie; 2869 uint32_t x, ys, yd, w, h; 2870 2871 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 2872 x = ri->ri_xorigin; 2873 ys = ri->ri_yorigin + ri->ri_font->fontheight * srcrow; 2874 yd = ri->ri_yorigin + ri->ri_font->fontheight * dstrow; 2875 w = ri->ri_emuwidth; 2876 h = ri->ri_font->fontheight * nrows; 2877 radeonfb_bitblt(dp, x, ys, x, yd, w, h, 2878 RADEON_ROP3_S); 2879 } 2880 } 2881 2882 static void 2883 radeonfb_copycols(void *cookie, int row, int srccol, int dstcol, int ncols) 2884 { 2885 struct rasops_info *ri = cookie; 2886 struct vcons_screen *scr = ri->ri_hw; 2887 struct radeonfb_display *dp = scr->scr_cookie; 2888 uint32_t xs, xd, y, w, h; 2889 2890 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 2891 xs = ri->ri_xorigin + ri->ri_font->fontwidth * srccol; 2892 xd = ri->ri_xorigin + ri->ri_font->fontwidth * dstcol; 2893 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 2894 w = ri->ri_font->fontwidth * ncols; 2895 h = ri->ri_font->fontheight; 2896 radeonfb_bitblt(dp, xs, y, xd, y, w, h, 2897 RADEON_ROP3_S); 2898 } 2899 } 2900 2901 static void 2902 radeonfb_erasecols(void *cookie, int row, int startcol, int ncols, 2903 long fillattr) 2904 { 2905 struct rasops_info *ri = cookie; 2906 struct vcons_screen *scr = ri->ri_hw; 2907 struct radeonfb_display *dp = scr->scr_cookie; 2908 uint32_t x, y, w, h, fg, bg, ul; 2909 2910 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 2911 x = ri->ri_xorigin + ri->ri_font->fontwidth * startcol; 2912 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 2913 w = ri->ri_font->fontwidth * ncols; 2914 h = ri->ri_font->fontheight; 2915 2916 rasops_unpack_attr(fillattr, &fg, &bg, &ul); 2917 radeonfb_rectfill(dp, x, y, w, h, ri->ri_devcmap[bg & 0xf]); 2918 } 2919 } 2920 2921 static void 2922 radeonfb_cursor(void *cookie, int on, int row, int col) 2923 { 2924 struct rasops_info *ri = cookie; 2925 struct vcons_screen *scr = ri->ri_hw; 2926 struct radeonfb_display *dp = scr->scr_cookie; 2927 int x, y, wi, he; 2928 2929 wi = ri->ri_font->fontwidth; 2930 he = ri->ri_font->fontheight; 2931 2932 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 2933 x = ri->ri_ccol * wi + ri->ri_xorigin; 2934 y = ri->ri_crow * he + ri->ri_yorigin; 2935 /* first turn off the old cursor */ 2936 if (ri->ri_flg & RI_CURSOR) { 2937 radeonfb_bitblt(dp, x, y, x, y, wi, he, 2938 RADEON_ROP3_Dn); 2939 ri->ri_flg &= ~RI_CURSOR; 2940 } 2941 ri->ri_crow = row; 2942 ri->ri_ccol = col; 2943 /* then (possibly) turn on the new one */ 2944 if (on) { 2945 x = ri->ri_ccol * wi + ri->ri_xorigin; 2946 y = ri->ri_crow * he + ri->ri_yorigin; 2947 radeonfb_bitblt(dp, x, y, x, y, wi, he, 2948 RADEON_ROP3_Dn); 2949 ri->ri_flg |= RI_CURSOR; 2950 } 2951 } else { 2952 scr->scr_ri.ri_crow = row; 2953 scr->scr_ri.ri_ccol = col; 2954 scr->scr_ri.ri_flg &= ~RI_CURSOR; 2955 } 2956 } 2957 2958 /* 2959 * Underlying acceleration support. 2960 */ 2961 2962 static void 2963 radeonfb_rectfill(struct radeonfb_display *dp, int dstx, int dsty, 2964 int width, int height, uint32_t color) 2965 { 2966 struct radeonfb_softc *sc = dp->rd_softc; 2967 uint32_t gmc; 2968 2969 gmc = dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT; 2970 2971 radeonfb_wait_fifo(sc, 6); 2972 2973 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 2974 RADEON_GMC_BRUSH_SOLID_COLOR | 2975 RADEON_GMC_SRC_DATATYPE_COLOR | 2976 RADEON_GMC_CLR_CMP_CNTL_DIS | 2977 RADEON_ROP3_P | gmc); 2978 2979 PUT32(sc, RADEON_DP_BRUSH_FRGD_CLR, color); 2980 PUT32(sc, RADEON_DP_WRITE_MASK, 0xffffffff); 2981 PUT32(sc, RADEON_DP_CNTL, 2982 RADEON_DST_X_LEFT_TO_RIGHT | 2983 RADEON_DST_Y_TOP_TO_BOTTOM); 2984 PUT32(sc, RADEON_DST_Y_X, (dsty << 16) | dstx); 2985 PUT32(sc, RADEON_DST_WIDTH_HEIGHT, (width << 16) | (height)); 2986 2987 } 2988 2989 static void 2990 radeonfb_rectfill_a(void *cookie, int dstx, int dsty, 2991 int width, int height, long attr) 2992 { 2993 struct radeonfb_display *dp = cookie; 2994 2995 radeonfb_rectfill(dp, dstx, dsty, width, height, 2996 dp->rd_vscreen.scr_ri.ri_devcmap[(attr >> 24 & 0xf)]); 2997 } 2998 2999 static void 3000 radeonfb_bitblt(void *cookie, int srcx, int srcy, 3001 int dstx, int dsty, int width, int height, int rop) 3002 { 3003 struct radeonfb_display *dp = cookie; 3004 struct radeonfb_softc *sc = dp->rd_softc; 3005 uint32_t gmc; 3006 uint32_t dir; 3007 3008 if (dsty < srcy) { 3009 dir = RADEON_DST_Y_TOP_TO_BOTTOM; 3010 } else { 3011 srcy += height - 1; 3012 dsty += height - 1; 3013 dir = 0; 3014 } 3015 if (dstx < srcx) { 3016 dir |= RADEON_DST_X_LEFT_TO_RIGHT; 3017 } else { 3018 srcx += width - 1; 3019 dstx += width - 1; 3020 } 3021 3022 gmc = dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT; 3023 3024 radeonfb_wait_fifo(sc, 6); 3025 3026 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 3027 RADEON_GMC_BRUSH_SOLID_COLOR | 3028 RADEON_GMC_SRC_DATATYPE_COLOR | 3029 RADEON_GMC_CLR_CMP_CNTL_DIS | 3030 RADEON_DP_SRC_SOURCE_MEMORY | 3031 rop | gmc); 3032 3033 PUT32(sc, RADEON_DP_WRITE_MASK, 0xffffffff); 3034 PUT32(sc, RADEON_DP_CNTL, dir); 3035 PUT32(sc, RADEON_SRC_Y_X, (srcy << 16) | srcx); 3036 PUT32(sc, RADEON_DST_Y_X, (dsty << 16) | dstx); 3037 PUT32(sc, RADEON_DST_WIDTH_HEIGHT, (width << 16) | (height)); 3038 } 3039 3040 static void 3041 radeonfb_engine_idle(struct radeonfb_softc *sc) 3042 { 3043 3044 radeonfb_wait_fifo(sc, 64); 3045 while ((GET32(sc, RADEON_RBBM_STATUS) & 3046 RADEON_RBBM_ACTIVE) != 0); 3047 radeonfb_engine_flush(sc); 3048 } 3049 3050 static inline void 3051 radeonfb_wait_fifo(struct radeonfb_softc *sc, int n) 3052 { 3053 int i; 3054 3055 for (i = RADEON_TIMEOUT; i; i--) { 3056 if ((GET32(sc, RADEON_RBBM_STATUS) & 3057 RADEON_RBBM_FIFOCNT_MASK) >= n) 3058 return; 3059 } 3060 #ifdef DIAGNOSTIC 3061 if (!i) 3062 printf("%s: timed out waiting for fifo (%x)\n", 3063 XNAME(sc), GET32(sc, RADEON_RBBM_STATUS)); 3064 #endif 3065 } 3066 3067 static void 3068 radeonfb_engine_flush(struct radeonfb_softc *sc) 3069 { 3070 int i = 0; 3071 3072 if (IS_R300(sc)) { 3073 SET32(sc, R300_DSTCACHE_CTLSTAT, R300_RB2D_DC_FLUSH_ALL); 3074 while (GET32(sc, R300_DSTCACHE_CTLSTAT) & R300_RB2D_DC_BUSY) { 3075 i++; 3076 } 3077 } else { 3078 SET32(sc, RADEON_RB2D_DSTCACHE_CTLSTAT, 3079 RADEON_RB2D_DC_FLUSH_ALL); 3080 while (GET32(sc, RADEON_RB2D_DSTCACHE_CTLSTAT) & 3081 RADEON_RB2D_DC_BUSY) { 3082 i++; 3083 } 3084 } 3085 #ifdef DIAGNOSTIC 3086 if (i > RADEON_TIMEOUT) 3087 printf("%s: engine flush timed out!\n", XNAME(sc)); 3088 #endif 3089 } 3090 3091 static inline void 3092 radeonfb_unclip(struct radeonfb_softc *sc) 3093 { 3094 3095 radeonfb_wait_fifo(sc, 2); 3096 PUT32(sc, RADEON_SC_TOP_LEFT, 0); 3097 PUT32(sc, RADEON_SC_BOTTOM_RIGHT, 0x1fff1fff); 3098 } 3099 3100 static void 3101 radeonfb_engine_init(struct radeonfb_display *dp) 3102 { 3103 struct radeonfb_softc *sc = dp->rd_softc; 3104 uint32_t pitch; 3105 volatile uint32_t junk; 3106 3107 /* no 3D */ 3108 PUT32(sc, RADEON_RB3D_CNTL, 0); 3109 3110 radeonfb_engine_reset(sc); 3111 pitch = ((dp->rd_virtx * (dp->rd_bpp / 8) + 0x3f)) >> 6; 3112 3113 radeonfb_wait_fifo(sc, 1); 3114 if (!IS_R300(sc)) 3115 PUT32(sc, RADEON_RB2D_DSTCACHE_MODE, 0); 3116 3117 radeonfb_wait_fifo(sc, 3); 3118 PUT32(sc, RADEON_DEFAULT_PITCH_OFFSET, 3119 (pitch << 22) | (sc->sc_aperbase >> 10)); 3120 3121 3122 PUT32(sc, RADEON_DST_PITCH_OFFSET, 3123 (pitch << 22) | (sc->sc_aperbase >> 10)); 3124 PUT32(sc, RADEON_SRC_PITCH_OFFSET, 3125 (pitch << 22) | (sc->sc_aperbase >> 10)); 3126 3127 radeonfb_wait_fifo(sc, 1); 3128 #if _BYTE_ORDER == _BIG_ENDIAN 3129 SET32(sc, RADEON_DP_DATATYPE, RADEON_HOST_BIG_ENDIAN_EN); 3130 #else 3131 CLR32(sc, RADEON_DP_DATATYPE, RADEON_HOST_BIG_ENDIAN_EN); 3132 #endif 3133 junk = GET32(sc, RADEON_DP_DATATYPE); 3134 3135 /* default scissors -- no clipping */ 3136 radeonfb_wait_fifo(sc, 1); 3137 PUT32(sc, RADEON_DEFAULT_SC_BOTTOM_RIGHT, 3138 RADEON_DEFAULT_SC_RIGHT_MAX | RADEON_DEFAULT_SC_BOTTOM_MAX); 3139 3140 radeonfb_wait_fifo(sc, 1); 3141 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 3142 (dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT) | 3143 RADEON_GMC_CLR_CMP_CNTL_DIS | 3144 RADEON_GMC_BRUSH_SOLID_COLOR | 3145 RADEON_GMC_SRC_DATATYPE_COLOR); 3146 3147 radeonfb_wait_fifo(sc, 10); 3148 PUT32(sc, RADEON_DST_LINE_START, 0); 3149 PUT32(sc, RADEON_DST_LINE_END, 0); 3150 PUT32(sc, RADEON_DP_BRUSH_FRGD_CLR, 0xffffffff); 3151 PUT32(sc, RADEON_DP_BRUSH_BKGD_CLR, 0); 3152 PUT32(sc, RADEON_DP_SRC_FRGD_CLR, 0xffffffff); 3153 PUT32(sc, RADEON_DP_SRC_BKGD_CLR, 0); 3154 PUT32(sc, RADEON_DP_WRITE_MASK, 0xffffffff); 3155 PUT32(sc, RADEON_SC_TOP_LEFT, 0); 3156 PUT32(sc, RADEON_SC_BOTTOM_RIGHT, 0x1fff1fff); 3157 PUT32(sc, RADEON_AUX_SC_CNTL, 0); 3158 radeonfb_engine_idle(sc); 3159 } 3160 3161 static void 3162 radeonfb_engine_reset(struct radeonfb_softc *sc) 3163 { 3164 uint32_t hpc, rbbm, mclkcntl, clkindex; 3165 3166 radeonfb_engine_flush(sc); 3167 3168 clkindex = GET32(sc, RADEON_CLOCK_CNTL_INDEX); 3169 if (HAS_R300CG(sc)) 3170 radeonfb_r300cg_workaround(sc); 3171 mclkcntl = GETPLL(sc, RADEON_MCLK_CNTL); 3172 3173 /* 3174 * According to comments in XFree code, resetting the HDP via 3175 * the RBBM_SOFT_RESET can cause bad behavior on some systems. 3176 * So we use HOST_PATH_CNTL instead. 3177 */ 3178 3179 hpc = GET32(sc, RADEON_HOST_PATH_CNTL); 3180 rbbm = GET32(sc, RADEON_RBBM_SOFT_RESET); 3181 if (IS_R300(sc)) { 3182 PUT32(sc, RADEON_RBBM_SOFT_RESET, rbbm | 3183 RADEON_SOFT_RESET_CP | 3184 RADEON_SOFT_RESET_HI | 3185 RADEON_SOFT_RESET_E2); 3186 GET32(sc, RADEON_RBBM_SOFT_RESET); 3187 PUT32(sc, RADEON_RBBM_SOFT_RESET, 0); 3188 /* 3189 * XXX: this bit is not defined in any ATI docs I have, 3190 * nor in the XFree code, but XFree does it. Why? 3191 */ 3192 SET32(sc, RADEON_RB2D_DSTCACHE_MODE, (1<<17)); 3193 } else { 3194 PUT32(sc, RADEON_RBBM_SOFT_RESET, rbbm | 3195 RADEON_SOFT_RESET_CP | 3196 RADEON_SOFT_RESET_SE | 3197 RADEON_SOFT_RESET_RE | 3198 RADEON_SOFT_RESET_PP | 3199 RADEON_SOFT_RESET_E2 | 3200 RADEON_SOFT_RESET_RB); 3201 GET32(sc, RADEON_RBBM_SOFT_RESET); 3202 PUT32(sc, RADEON_RBBM_SOFT_RESET, rbbm & 3203 ~(RADEON_SOFT_RESET_CP | 3204 RADEON_SOFT_RESET_SE | 3205 RADEON_SOFT_RESET_RE | 3206 RADEON_SOFT_RESET_PP | 3207 RADEON_SOFT_RESET_E2 | 3208 RADEON_SOFT_RESET_RB)); 3209 GET32(sc, RADEON_RBBM_SOFT_RESET); 3210 } 3211 3212 PUT32(sc, RADEON_HOST_PATH_CNTL, hpc | RADEON_HDP_SOFT_RESET); 3213 GET32(sc, RADEON_HOST_PATH_CNTL); 3214 PUT32(sc, RADEON_HOST_PATH_CNTL, hpc); 3215 3216 if (IS_R300(sc)) 3217 PUT32(sc, RADEON_RBBM_SOFT_RESET, rbbm); 3218 3219 PUT32(sc, RADEON_CLOCK_CNTL_INDEX, clkindex); 3220 PUTPLL(sc, RADEON_MCLK_CNTL, mclkcntl); 3221 3222 if (HAS_R300CG(sc)) 3223 radeonfb_r300cg_workaround(sc); 3224 } 3225 3226 static int 3227 radeonfb_set_curpos(struct radeonfb_display *dp, struct wsdisplay_curpos *pos) 3228 { 3229 int x, y; 3230 3231 x = pos->x; 3232 y = pos->y; 3233 3234 /* 3235 * This doesn't let a cursor move off the screen. I'm not 3236 * sure if this will have negative effects for e.g. Xinerama. 3237 * I'd guess Xinerama handles it by changing the cursor shape, 3238 * but that needs verification. 3239 */ 3240 if (x >= dp->rd_virtx) 3241 x = dp->rd_virtx - 1; 3242 if (x < 0) 3243 x = 0; 3244 if (y >= dp->rd_virty) 3245 y = dp->rd_virty - 1; 3246 if (y < 0) 3247 y = 0; 3248 3249 dp->rd_cursor.rc_pos.x = x; 3250 dp->rd_cursor.rc_pos.y = y; 3251 3252 radeonfb_cursor_position(dp); 3253 return 0; 3254 } 3255 3256 static int 3257 radeonfb_set_cursor(struct radeonfb_display *dp, struct wsdisplay_cursor *wc) 3258 { 3259 unsigned flags; 3260 3261 uint8_t r[2], g[2], b[2]; 3262 unsigned index, count; 3263 int i, err; 3264 int pitch, size; 3265 struct radeonfb_cursor nc; 3266 3267 flags = wc->which; 3268 3269 /* copy old values */ 3270 nc = dp->rd_cursor; 3271 3272 if (flags & WSDISPLAY_CURSOR_DOCMAP) { 3273 index = wc->cmap.index; 3274 count = wc->cmap.count; 3275 3276 if (index >= 2 || (index + count) > 2) 3277 return EINVAL; 3278 3279 err = copyin(wc->cmap.red, &r[index], count); 3280 if (err) 3281 return err; 3282 err = copyin(wc->cmap.green, &g[index], count); 3283 if (err) 3284 return err; 3285 err = copyin(wc->cmap.blue, &b[index], count); 3286 if (err) 3287 return err; 3288 3289 for (i = index; i < index + count; i++) { 3290 nc.rc_cmap[i] = 3291 (r[i] << 16) + (g[i] << 8) + (b[i] << 0); 3292 } 3293 } 3294 3295 if (flags & WSDISPLAY_CURSOR_DOSHAPE) { 3296 if ((wc->size.x > RADEON_CURSORMAXX) || 3297 (wc->size.y > RADEON_CURSORMAXY)) 3298 return EINVAL; 3299 3300 /* figure bytes per line */ 3301 pitch = (wc->size.x + 7) / 8; 3302 size = pitch * wc->size.y; 3303 3304 /* clear the old cursor and mask */ 3305 memset(nc.rc_image, 0, 512); 3306 memset(nc.rc_mask, 0, 512); 3307 3308 nc.rc_size = wc->size; 3309 3310 if ((err = copyin(wc->image, nc.rc_image, size)) != 0) 3311 return err; 3312 3313 if ((err = copyin(wc->mask, nc.rc_mask, size)) != 0) 3314 return err; 3315 } 3316 3317 if (flags & WSDISPLAY_CURSOR_DOHOT) { 3318 nc.rc_hot = wc->hot; 3319 if (nc.rc_hot.x >= nc.rc_size.x) 3320 nc.rc_hot.x = nc.rc_size.x - 1; 3321 if (nc.rc_hot.y >= nc.rc_size.y) 3322 nc.rc_hot.y = nc.rc_size.y - 1; 3323 } 3324 3325 if (flags & WSDISPLAY_CURSOR_DOPOS) { 3326 nc.rc_pos = wc->pos; 3327 if (nc.rc_pos.x >= dp->rd_virtx) 3328 nc.rc_pos.x = dp->rd_virtx - 1; 3329 #if 0 3330 if (nc.rc_pos.x < 0) 3331 nc.rc_pos.x = 0; 3332 #endif 3333 if (nc.rc_pos.y >= dp->rd_virty) 3334 nc.rc_pos.y = dp->rd_virty - 1; 3335 #if 0 3336 if (nc.rc_pos.y < 0) 3337 nc.rc_pos.y = 0; 3338 #endif 3339 } 3340 if (flags & WSDISPLAY_CURSOR_DOCUR) { 3341 nc.rc_visible = wc->enable; 3342 } 3343 3344 dp->rd_cursor = nc; 3345 radeonfb_cursor_update(dp, wc->which); 3346 3347 return 0; 3348 } 3349 3350 /* 3351 * Change the cursor shape. Call this with the cursor locked to avoid 3352 * flickering/tearing. 3353 */ 3354 static void 3355 radeonfb_cursor_shape(struct radeonfb_display *dp) 3356 { 3357 uint8_t and[512], xor[512]; 3358 int i, j, src, dst, pitch; 3359 const uint8_t *msk = dp->rd_cursor.rc_mask; 3360 const uint8_t *img = dp->rd_cursor.rc_image; 3361 3362 /* 3363 * Radeon cursor data interleaves one line of AND data followed 3364 * by a line of XOR data. (Each line corresponds to a whole hardware 3365 * pitch - i.e. 64 pixels or 8 bytes.) 3366 * 3367 * The cursor is displayed using the following table: 3368 * 3369 * AND XOR Result 3370 * ---------------------- 3371 * 0 0 Cursor color 0 3372 * 0 1 Cursor color 1 3373 * 1 0 Transparent 3374 * 1 1 Complement of background 3375 * 3376 * Our masks are therefore different from what we were passed. 3377 * Passed in, I'm assuming the data represents either color 0 or 1, 3378 * and a mask, so the passed in table looks like: 3379 * 3380 * IMG Mask Result 3381 * ----------------------- 3382 * 0 0 Transparent 3383 * 0 1 Cursor color 0 3384 * 1 0 Transparent 3385 * 1 1 Cursor color 1 3386 * 3387 * IF mask bit == 1, AND = 0, XOR = color. 3388 * IF mask bit == 0, AND = 1, XOR = 0. 3389 * 3390 * hence: AND = ~(mask); XOR = color & ~(mask); 3391 */ 3392 3393 pitch = ((dp->rd_cursor.rc_size.x + 7) / 8); 3394 3395 /* start by assuming all bits are transparent */ 3396 memset(and, 0xff, 512); 3397 memset(xor, 0x00, 512); 3398 3399 src = 0; 3400 dst = 0; 3401 for (i = 0; i < 64; i++) { 3402 for (j = 0; j < 64; j += 8) { 3403 if ((i < dp->rd_cursor.rc_size.y) && 3404 (j < dp->rd_cursor.rc_size.x)) { 3405 3406 /* take care to leave odd bits alone */ 3407 and[dst] &= ~(msk[src]); 3408 xor[dst] = img[src] & msk[src]; 3409 src++; 3410 } 3411 dst++; 3412 } 3413 } 3414 3415 /* copy the image into place */ 3416 for (i = 0; i < 64; i++) { 3417 memcpy((uint8_t *)dp->rd_curptr + (i * 16), 3418 &and[i * 8], 8); 3419 memcpy((uint8_t *)dp->rd_curptr + (i * 16) + 8, 3420 &xor[i * 8], 8); 3421 } 3422 } 3423 3424 static void 3425 radeonfb_cursor_position(struct radeonfb_display *dp) 3426 { 3427 struct radeonfb_softc *sc = dp->rd_softc; 3428 uint32_t offset, hvoff, hvpos; /* registers */ 3429 uint32_t coff; /* cursor offset */ 3430 int i, x, y, xoff, yoff, crtcoff; 3431 3432 /* 3433 * XXX: this also needs to handle pan/scan 3434 */ 3435 for (i = 0; i < dp->rd_ncrtcs; i++) { 3436 3437 struct radeonfb_crtc *rcp = &dp->rd_crtcs[i]; 3438 3439 if (rcp->rc_number) { 3440 offset = RADEON_CUR2_OFFSET; 3441 hvoff = RADEON_CUR2_HORZ_VERT_OFF; 3442 hvpos = RADEON_CUR2_HORZ_VERT_POSN; 3443 crtcoff = RADEON_CRTC2_OFFSET; 3444 } else { 3445 offset = RADEON_CUR_OFFSET; 3446 hvoff = RADEON_CUR_HORZ_VERT_OFF; 3447 hvpos = RADEON_CUR_HORZ_VERT_POSN; 3448 crtcoff = RADEON_CRTC_OFFSET; 3449 } 3450 3451 x = dp->rd_cursor.rc_pos.x; 3452 y = dp->rd_cursor.rc_pos.y; 3453 3454 while (y < rcp->rc_yoffset) { 3455 rcp->rc_yoffset -= RADEON_PANINCREMENT; 3456 } 3457 while (y >= (rcp->rc_yoffset + rcp->rc_videomode.vdisplay)) { 3458 rcp->rc_yoffset += RADEON_PANINCREMENT; 3459 } 3460 while (x < rcp->rc_xoffset) { 3461 rcp->rc_xoffset -= RADEON_PANINCREMENT; 3462 } 3463 while (x >= (rcp->rc_xoffset + rcp->rc_videomode.hdisplay)) { 3464 rcp->rc_xoffset += RADEON_PANINCREMENT; 3465 } 3466 3467 /* adjust for the cursor's hotspot */ 3468 x -= dp->rd_cursor.rc_hot.x; 3469 y -= dp->rd_cursor.rc_hot.y; 3470 xoff = yoff = 0; 3471 3472 if (x >= dp->rd_virtx) 3473 x = dp->rd_virtx - 1; 3474 if (y >= dp->rd_virty) 3475 y = dp->rd_virty - 1; 3476 3477 /* now adjust cursor so it is relative to viewport */ 3478 x -= rcp->rc_xoffset; 3479 y -= rcp->rc_yoffset; 3480 3481 /* 3482 * no need to check for fall off, because we should 3483 * never move off the screen entirely! 3484 */ 3485 coff = 0; 3486 if (x < 0) { 3487 xoff = -x; 3488 x = 0; 3489 } 3490 if (y < 0) { 3491 yoff = -y; 3492 y = 0; 3493 coff = (yoff * 2) * 8; 3494 } 3495 3496 /* pan the display */ 3497 PUT32(sc, crtcoff, (rcp->rc_yoffset * dp->rd_stride) + 3498 rcp->rc_xoffset); 3499 3500 PUT32(sc, offset, (dp->rd_curoff + coff) | RADEON_CUR_LOCK); 3501 PUT32(sc, hvoff, (xoff << 16) | (yoff) | RADEON_CUR_LOCK); 3502 /* NB: this unlocks the cursor */ 3503 PUT32(sc, hvpos, (x << 16) | y); 3504 } 3505 } 3506 3507 static void 3508 radeonfb_cursor_visible(struct radeonfb_display *dp) 3509 { 3510 int i; 3511 uint32_t gencntl, bit; 3512 3513 for (i = 0; i < dp->rd_ncrtcs; i++) { 3514 if (dp->rd_crtcs[i].rc_number) { 3515 gencntl = RADEON_CRTC2_GEN_CNTL; 3516 bit = RADEON_CRTC2_CUR_EN; 3517 } else { 3518 gencntl = RADEON_CRTC_GEN_CNTL; 3519 bit = RADEON_CRTC_CUR_EN; 3520 } 3521 3522 if (dp->rd_cursor.rc_visible) 3523 SET32(dp->rd_softc, gencntl, bit); 3524 else 3525 CLR32(dp->rd_softc, gencntl, bit); 3526 } 3527 } 3528 3529 static void 3530 radeonfb_cursor_cmap(struct radeonfb_display *dp) 3531 { 3532 int i; 3533 uint32_t c0reg, c1reg; 3534 struct radeonfb_softc *sc = dp->rd_softc; 3535 3536 for (i = 0; i < dp->rd_ncrtcs; i++) { 3537 if (dp->rd_crtcs[i].rc_number) { 3538 c0reg = RADEON_CUR2_CLR0; 3539 c1reg = RADEON_CUR2_CLR1; 3540 } else { 3541 c0reg = RADEON_CUR_CLR0; 3542 c1reg = RADEON_CUR_CLR1; 3543 } 3544 3545 PUT32(sc, c0reg, dp->rd_cursor.rc_cmap[0]); 3546 PUT32(sc, c1reg, dp->rd_cursor.rc_cmap[1]); 3547 } 3548 } 3549 3550 static void 3551 radeonfb_cursor_update(struct radeonfb_display *dp, unsigned which) 3552 { 3553 struct radeonfb_softc *sc; 3554 int i; 3555 3556 sc = dp->rd_softc; 3557 for (i = 0; i < dp->rd_ncrtcs; i++) { 3558 if (dp->rd_crtcs[i].rc_number) { 3559 SET32(sc, RADEON_CUR2_OFFSET, RADEON_CUR_LOCK); 3560 } else { 3561 SET32(sc, RADEON_CUR_OFFSET,RADEON_CUR_LOCK); 3562 } 3563 } 3564 3565 if (which & WSDISPLAY_CURSOR_DOCMAP) 3566 radeonfb_cursor_cmap(dp); 3567 3568 if (which & WSDISPLAY_CURSOR_DOSHAPE) 3569 radeonfb_cursor_shape(dp); 3570 3571 if (which & WSDISPLAY_CURSOR_DOCUR) 3572 radeonfb_cursor_visible(dp); 3573 3574 /* this one is unconditional, because it updates other stuff */ 3575 radeonfb_cursor_position(dp); 3576 } 3577 3578 static struct videomode * 3579 radeonfb_best_refresh(struct videomode *m1, struct videomode *m2) 3580 { 3581 int r1, r2; 3582 3583 /* otherwise pick the higher refresh rate */ 3584 r1 = DIVIDE(DIVIDE(m1->dot_clock, m1->htotal), m1->vtotal); 3585 r2 = DIVIDE(DIVIDE(m2->dot_clock, m2->htotal), m2->vtotal); 3586 3587 return (r1 < r2 ? m2 : m1); 3588 } 3589 3590 static const struct videomode * 3591 radeonfb_port_mode(struct radeonfb_softc *sc, struct radeonfb_port *rp, 3592 int x, int y) 3593 { 3594 struct edid_info *ep = &rp->rp_edid; 3595 struct videomode *vmp = NULL; 3596 int i; 3597 3598 if (!rp->rp_edid_valid) { 3599 /* fallback to safe mode */ 3600 return radeonfb_modelookup(sc->sc_defaultmode); 3601 } 3602 3603 /* always choose the preferred mode first! */ 3604 if (ep->edid_preferred_mode) { 3605 3606 /* XXX: add auto-stretching support for native mode */ 3607 3608 /* this may want panning to occur, btw */ 3609 if ((ep->edid_preferred_mode->hdisplay <= x) && 3610 (ep->edid_preferred_mode->vdisplay <= y)) 3611 return ep->edid_preferred_mode; 3612 } 3613 3614 for (i = 0; i < ep->edid_nmodes; i++) { 3615 /* 3616 * We elect to pick a resolution that is too large for 3617 * the monitor than one that is too small. This means 3618 * that we will prefer to pan rather than to try to 3619 * center a smaller display on a larger screen. In 3620 * practice, this shouldn't matter because if a 3621 * monitor can support a larger resolution, it can 3622 * probably also support the smaller. A specific 3623 * exception is fixed format panels, but hopefully 3624 * they are properly dealt with by the "autostretch" 3625 * logic above. 3626 */ 3627 if ((ep->edid_modes[i].hdisplay > x) || 3628 (ep->edid_modes[i].vdisplay > y)) { 3629 continue; 3630 } 3631 3632 /* 3633 * at this point, the display mode is no larger than 3634 * what we've requested. 3635 */ 3636 if (vmp == NULL) 3637 vmp = &ep->edid_modes[i]; 3638 3639 /* eliminate smaller modes */ 3640 if ((vmp->hdisplay >= ep->edid_modes[i].hdisplay) || 3641 (vmp->vdisplay >= ep->edid_modes[i].vdisplay)) 3642 continue; 3643 3644 if ((vmp->hdisplay < ep->edid_modes[i].hdisplay) || 3645 (vmp->vdisplay < ep->edid_modes[i].vdisplay)) { 3646 vmp = &ep->edid_modes[i]; 3647 continue; 3648 } 3649 3650 KASSERT(vmp->hdisplay == ep->edid_modes[i].hdisplay); 3651 KASSERT(vmp->vdisplay == ep->edid_modes[i].vdisplay); 3652 3653 vmp = radeonfb_best_refresh(vmp, &ep->edid_modes[i]); 3654 } 3655 3656 return (vmp ? vmp : radeonfb_modelookup(sc->sc_defaultmode)); 3657 } 3658 3659 static int 3660 radeonfb_hasres(struct videomode *list, int nlist, int x, int y) 3661 { 3662 int i; 3663 3664 for (i = 0; i < nlist; i++) { 3665 if ((x == list[i].hdisplay) && 3666 (y == list[i].vdisplay)) { 3667 return 1; 3668 } 3669 } 3670 return 0; 3671 } 3672 3673 static void 3674 radeonfb_pickres(struct radeonfb_display *dp, uint16_t *x, uint16_t *y, 3675 int pan) 3676 { 3677 struct radeonfb_port *rp; 3678 struct edid_info *ep; 3679 int i, j; 3680 3681 *x = 0; 3682 *y = 0; 3683 3684 if (pan) { 3685 for (i = 0; i < dp->rd_ncrtcs; i++) { 3686 rp = dp->rd_crtcs[i].rc_port; 3687 ep = &rp->rp_edid; 3688 if (!rp->rp_edid_valid) { 3689 /* monitor not present */ 3690 continue; 3691 } 3692 3693 /* 3694 * For now we are ignoring "conflict" that 3695 * could occur when mixing some modes like 3696 * 1280x1024 and 1400x800. It isn't clear 3697 * which is better, so the first one wins. 3698 */ 3699 for (j = 0; j < ep->edid_nmodes; j++) { 3700 /* 3701 * ignore resolutions that are too big for 3702 * the radeon 3703 */ 3704 if (ep->edid_modes[j].hdisplay > 3705 dp->rd_softc->sc_maxx) 3706 continue; 3707 if (ep->edid_modes[j].vdisplay > 3708 dp->rd_softc->sc_maxy) 3709 continue; 3710 3711 /* 3712 * pick largest resolution, the 3713 * smaller monitor will pan 3714 */ 3715 if ((ep->edid_modes[j].hdisplay >= *x) && 3716 (ep->edid_modes[j].vdisplay >= *y)) { 3717 *x = ep->edid_modes[j].hdisplay; 3718 *y = ep->edid_modes[j].vdisplay; 3719 } 3720 } 3721 } 3722 3723 } else { 3724 struct videomode modes[64]; 3725 int nmodes = 0; 3726 int valid = 0; 3727 3728 for (i = 0; i < dp->rd_ncrtcs; i++) { 3729 /* 3730 * pick the largest resolution in common. 3731 */ 3732 rp = dp->rd_crtcs[i].rc_port; 3733 ep = &rp->rp_edid; 3734 3735 if (!rp->rp_edid_valid) 3736 continue; 3737 3738 if (!valid) { 3739 /* 3740 * Pick the preferred mode for this port 3741 * if available. 3742 */ 3743 if (ep->edid_preferred_mode) { 3744 struct videomode *vmp = 3745 ep->edid_preferred_mode; 3746 3747 if ((vmp->hdisplay <= 3748 dp->rd_softc->sc_maxx) && 3749 (vmp->vdisplay <= 3750 dp->rd_softc->sc_maxy)) 3751 modes[nmodes++] = *vmp; 3752 } else { 3753 3754 /* initialize starting list */ 3755 for (j = 0; j < ep->edid_nmodes; j++) { 3756 /* 3757 * ignore resolutions that are 3758 * too big for the radeon 3759 */ 3760 if (ep->edid_modes[j].hdisplay > 3761 dp->rd_softc->sc_maxx) 3762 continue; 3763 if (ep->edid_modes[j].vdisplay > 3764 dp->rd_softc->sc_maxy) 3765 continue; 3766 3767 modes[nmodes] = 3768 ep->edid_modes[j]; 3769 nmodes++; 3770 } 3771 } 3772 valid = 1; 3773 } else { 3774 /* merge into preexisting list */ 3775 for (j = 0; j < nmodes; j++) { 3776 if (!radeonfb_hasres(ep->edid_modes, 3777 ep->edid_nmodes, 3778 modes[j].hdisplay, 3779 modes[j].vdisplay)) { 3780 modes[j] = modes[nmodes]; 3781 j--; 3782 nmodes--; 3783 } 3784 } 3785 } 3786 } 3787 3788 /* now we have to pick from the merged list */ 3789 for (i = 0; i < nmodes; i++) { 3790 if ((modes[i].hdisplay >= *x) && 3791 (modes[i].vdisplay >= *y)) { 3792 *x = modes[i].hdisplay; 3793 *y = modes[i].vdisplay; 3794 } 3795 } 3796 } 3797 3798 if ((*x == 0) || (*y == 0)) { 3799 /* fallback to safe mode */ 3800 *x = 640; 3801 *y = 480; 3802 } 3803 } 3804 3805 /* 3806 * backlight levels are linear on: 3807 * - RV200, RV250, RV280, RV350 3808 * - but NOT on PowerBook4,3 6,3 6,5 3809 * according to Linux' radeonfb 3810 */ 3811 3812 /* Get the current backlight level for the display. */ 3813 3814 static int 3815 radeonfb_get_backlight(struct radeonfb_display *dp) 3816 { 3817 int s; 3818 uint32_t level; 3819 3820 s = spltty(); 3821 3822 level = radeonfb_get32(dp->rd_softc, RADEON_LVDS_GEN_CNTL); 3823 level &= RADEON_LVDS_BL_MOD_LEV_MASK; 3824 level >>= RADEON_LVDS_BL_MOD_LEV_SHIFT; 3825 3826 /* 3827 * On some chips, we should negate the backlight level. 3828 * XXX Find out on which chips. 3829 */ 3830 if (dp->rd_softc->sc_flags & RFB_INV_BLIGHT) 3831 level = RADEONFB_BACKLIGHT_MAX - level; 3832 3833 splx(s); 3834 3835 return level; 3836 } 3837 3838 /* Set the backlight to the given level for the display. */ 3839 static void 3840 radeonfb_switch_backlight(struct radeonfb_display *dp, int on) 3841 { 3842 if (dp->rd_bl_on == on) 3843 return; 3844 dp->rd_bl_on = on; 3845 radeonfb_set_backlight(dp, dp->rd_bl_level); 3846 } 3847 3848 static int 3849 radeonfb_set_backlight(struct radeonfb_display *dp, int level) 3850 { 3851 struct radeonfb_softc *sc; 3852 int rlevel, s; 3853 uint32_t lvds; 3854 3855 s = spltty(); 3856 3857 dp->rd_bl_level = level; 3858 if (dp->rd_bl_on == 0) 3859 level = 0; 3860 3861 if (level < 0) 3862 level = 0; 3863 else if (level >= RADEONFB_BACKLIGHT_MAX) 3864 level = RADEONFB_BACKLIGHT_MAX; 3865 3866 sc = dp->rd_softc; 3867 3868 /* On some chips, we should negate the backlight level. */ 3869 if (dp->rd_softc->sc_flags & RFB_INV_BLIGHT) { 3870 rlevel = RADEONFB_BACKLIGHT_MAX - level; 3871 } else 3872 rlevel = level; 3873 3874 callout_stop(&dp->rd_bl_lvds_co); 3875 radeonfb_engine_idle(sc); 3876 3877 /* 3878 * Turn off the display if the backlight is set to 0, since the 3879 * display is useless without backlight anyway. 3880 */ 3881 if (level == 0) 3882 radeonfb_blank(dp, 1); 3883 else if (radeonfb_get_backlight(dp) == 0) 3884 radeonfb_blank(dp, 0); 3885 3886 lvds = radeonfb_get32(sc, RADEON_LVDS_GEN_CNTL); 3887 lvds &= ~RADEON_LVDS_DISPLAY_DIS; 3888 if (!(lvds & RADEON_LVDS_BLON) || !(lvds & RADEON_LVDS_ON)) { 3889 lvds |= dp->rd_bl_lvds_val & RADEON_LVDS_DIGON; 3890 lvds |= RADEON_LVDS_BLON | RADEON_LVDS_EN; 3891 radeonfb_put32(sc, RADEON_LVDS_GEN_CNTL, lvds); 3892 lvds &= ~RADEON_LVDS_BL_MOD_LEV_MASK; 3893 lvds |= rlevel << RADEON_LVDS_BL_MOD_LEV_SHIFT; 3894 lvds |= RADEON_LVDS_ON; 3895 lvds |= dp->rd_bl_lvds_val & RADEON_LVDS_BL_MOD_EN; 3896 } else { 3897 lvds &= ~RADEON_LVDS_BL_MOD_LEV_MASK; 3898 lvds |= rlevel << RADEON_LVDS_BL_MOD_LEV_SHIFT; 3899 radeonfb_put32(sc, RADEON_LVDS_GEN_CNTL, lvds); 3900 } 3901 3902 dp->rd_bl_lvds_val &= ~RADEON_LVDS_STATE_MASK; 3903 dp->rd_bl_lvds_val |= lvds & RADEON_LVDS_STATE_MASK; 3904 /* XXX What is the correct delay? */ 3905 callout_schedule(&dp->rd_bl_lvds_co, 200 * hz); 3906 3907 splx(s); 3908 3909 return 0; 3910 } 3911 3912 /* 3913 * Callout function for delayed operations on the LVDS_GEN_CNTL register. 3914 * Set the delayed bits in the register, and clear the stored delayed 3915 * value. 3916 */ 3917 3918 static void radeonfb_lvds_callout(void *arg) 3919 { 3920 struct radeonfb_display *dp = arg; 3921 int s; 3922 3923 s = splhigh(); 3924 3925 radeonfb_mask32(dp->rd_softc, RADEON_LVDS_GEN_CNTL, ~0, 3926 dp->rd_bl_lvds_val); 3927 dp->rd_bl_lvds_val = 0; 3928 3929 splx(s); 3930 } 3931 3932 static void 3933 radeonfb_brightness_up(device_t dev) 3934 { 3935 struct radeonfb_softc *sc = device_private(dev); 3936 struct radeonfb_display *dp = &sc->sc_displays[0]; 3937 int level; 3938 3939 /* we assume the main display is the first one - need a better way */ 3940 if (sc->sc_ndisplays < 1) return; 3941 /* make sure pushing the hotkeys always has an effect */ 3942 dp->rd_bl_on = 1; 3943 level = dp->rd_bl_level; 3944 level = min(RADEONFB_BACKLIGHT_MAX, level + 5); 3945 radeonfb_set_backlight(dp, level); 3946 } 3947 3948 static void 3949 radeonfb_brightness_down(device_t dev) 3950 { 3951 struct radeonfb_softc *sc = device_private(dev); 3952 struct radeonfb_display *dp = &sc->sc_displays[0]; 3953 int level; 3954 3955 /* we assume the main display is the first one - need a better way */ 3956 if (sc->sc_ndisplays < 1) return; 3957 /* make sure pushing the hotkeys always has an effect */ 3958 dp->rd_bl_on = 1; 3959 level = dp->rd_bl_level; 3960 level = max(0, level - 5); 3961 radeonfb_set_backlight(dp, level); 3962 } 3963
Indexes created Fri Oct 17 00:09:41 GMT 2025