radeonfb.c revision 1.48
1 /* $NetBSD: radeonfb.c,v 1.48 2011/12/29 20:14:39 macallan Exp $ */ 2 3 /*- 4 * Copyright (c) 2006 Itronix Inc. 5 * All rights reserved. 6 * 7 * Written by Garrett D'Amore for Itronix Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. The name of Itronix Inc. may not be used to endorse 18 * or promote products derived from this software without specific 19 * prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY ITRONIX INC. ``AS IS'' AND ANY EXPRESS 22 * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 23 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL ITRONIX INC. BE LIABLE FOR ANY 25 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE 27 * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 29 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 30 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 31 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * ATI Technologies Inc. ("ATI") has not assisted in the creation of, and 36 * does not endorse, this software. ATI will not be responsible or liable 37 * for any actual or alleged damage or loss caused by or in connection with 38 * the use of or reliance on this software. 39 */ 40 41 /* 42 * Portions of this code were taken from XFree86's Radeon driver, which bears 43 * this notice: 44 * 45 * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and 46 * VA Linux Systems Inc., Fremont, California. 47 * 48 * All Rights Reserved. 49 * 50 * Permission is hereby granted, free of charge, to any person obtaining 51 * a copy of this software and associated documentation files (the 52 * "Software"), to deal in the Software without restriction, including 53 * without limitation on the rights to use, copy, modify, merge, 54 * publish, distribute, sublicense, and/or sell copies of the Software, 55 * and to permit persons to whom the Software is furnished to do so, 56 * subject to the following conditions: 57 * 58 * The above copyright notice and this permission notice (including the 59 * next paragraph) shall be included in all copies or substantial 60 * portions of the Software. 61 * 62 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 63 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 64 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 65 * NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR 66 * THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 67 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 68 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 69 * DEALINGS IN THE SOFTWARE. 70 */ 71 72 #include <sys/cdefs.h> 73 __KERNEL_RCSID(0, "$NetBSD: radeonfb.c,v 1.48 2011/12/29 20:14:39 macallan Exp $"); 74 75 #define RADEONFB_DEFAULT_DEPTH 8 76 77 #include <sys/param.h> 78 #include <sys/systm.h> 79 #include <sys/device.h> 80 #include <sys/malloc.h> 81 #include <sys/bus.h> 82 #include <sys/kernel.h> 83 #include <sys/lwp.h> 84 #include <sys/kauth.h> 85 86 #include <dev/wscons/wsdisplayvar.h> 87 #include <dev/wscons/wsconsio.h> 88 #include <dev/wsfont/wsfont.h> 89 #include <dev/rasops/rasops.h> 90 #include <dev/videomode/videomode.h> 91 #include <dev/videomode/edidvar.h> 92 #include <dev/wscons/wsdisplay_vconsvar.h> 93 #include <dev/pci/wsdisplay_pci.h> 94 95 #include <dev/pci/pcidevs.h> 96 #include <dev/pci/pcireg.h> 97 #include <dev/pci/pcivar.h> 98 #include <dev/pci/pciio.h> 99 #include <dev/pci/radeonfbreg.h> 100 #include <dev/pci/radeonfbvar.h> 101 #include "opt_radeonfb.h" 102 #include "opt_vcons.h" 103 104 static int radeonfb_match(device_t, cfdata_t, void *); 105 static void radeonfb_attach(device_t, device_t, void *); 106 static int radeonfb_ioctl(void *, void *, unsigned long, void *, int, 107 struct lwp *); 108 static paddr_t radeonfb_mmap(void *, void *, off_t, int); 109 static int radeonfb_scratch_test(struct radeonfb_softc *, int, uint32_t); 110 static void radeonfb_loadbios(struct radeonfb_softc *, 111 const struct pci_attach_args *); 112 113 static uintmax_t radeonfb_getprop_num(struct radeonfb_softc *, const char *, 114 uintmax_t); 115 static int radeonfb_getclocks(struct radeonfb_softc *); 116 static int radeonfb_gettmds(struct radeonfb_softc *); 117 static int radeonfb_calc_dividers(struct radeonfb_softc *, uint32_t, 118 uint32_t *, uint32_t *); 119 static int radeonfb_getconnectors(struct radeonfb_softc *); 120 static const struct videomode *radeonfb_modelookup(const char *); 121 static void radeonfb_init_screen(void *, struct vcons_screen *, int, long *); 122 static void radeonfb_pllwriteupdate(struct radeonfb_softc *, int); 123 static void radeonfb_pllwaitatomicread(struct radeonfb_softc *, int); 124 static void radeonfb_program_vclk(struct radeonfb_softc *, int, int); 125 static void radeonfb_modeswitch(struct radeonfb_display *); 126 static void radeonfb_setcrtc(struct radeonfb_display *, int); 127 static void radeonfb_init_misc(struct radeonfb_softc *); 128 static void radeonfb_set_fbloc(struct radeonfb_softc *); 129 static void radeonfb_init_palette(struct radeonfb_softc *, int); 130 static void radeonfb_r300cg_workaround(struct radeonfb_softc *); 131 132 static int radeonfb_isblank(struct radeonfb_display *); 133 static void radeonfb_blank(struct radeonfb_display *, int); 134 static int radeonfb_set_cursor(struct radeonfb_display *, 135 struct wsdisplay_cursor *); 136 static int radeonfb_set_curpos(struct radeonfb_display *, 137 struct wsdisplay_curpos *); 138 139 /* acceleration support */ 140 static void radeonfb_rectfill(struct radeonfb_display *, int dstx, int dsty, 141 int width, int height, uint32_t color); 142 static void radeonfb_bitblt(struct radeonfb_display *, int srcx, int srcy, 143 int dstx, int dsty, int width, int height, int rop, uint32_t mask); 144 145 /* hw cursor support */ 146 static void radeonfb_cursor_cmap(struct radeonfb_display *); 147 static void radeonfb_cursor_shape(struct radeonfb_display *); 148 static void radeonfb_cursor_position(struct radeonfb_display *); 149 static void radeonfb_cursor_visible(struct radeonfb_display *); 150 static void radeonfb_cursor_update(struct radeonfb_display *, unsigned); 151 152 static void radeonfb_wait_fifo(struct radeonfb_softc *, int); 153 static void radeonfb_engine_idle(struct radeonfb_softc *); 154 static void radeonfb_engine_flush(struct radeonfb_softc *); 155 static void radeonfb_engine_reset(struct radeonfb_softc *); 156 static void radeonfb_engine_init(struct radeonfb_display *); 157 static inline void radeonfb_unclip(struct radeonfb_softc *); 158 159 static void radeonfb_eraserows(void *, int, int, long); 160 static void radeonfb_erasecols(void *, int, int, int, long); 161 static void radeonfb_copyrows(void *, int, int, int); 162 static void radeonfb_copycols(void *, int, int, int, int); 163 static void radeonfb_cursor(void *, int, int, int); 164 static void radeonfb_putchar(void *, int, int, unsigned, long); 165 static void radeonfb_putchar_wrapper(void *, int, int, unsigned, long); 166 static int radeonfb_allocattr(void *, int, int, int, long *); 167 168 static int radeonfb_get_backlight(struct radeonfb_display *); 169 static int radeonfb_set_backlight(struct radeonfb_display *, int); 170 static void radeonfb_lvds_callout(void *); 171 172 static void radeonfb_brightness_up(device_t); 173 static void radeonfb_brightness_down(device_t); 174 175 static struct videomode *radeonfb_best_refresh(struct videomode *, 176 struct videomode *); 177 static void radeonfb_pickres(struct radeonfb_display *, uint16_t *, 178 uint16_t *, int); 179 static const struct videomode *radeonfb_port_mode(struct radeonfb_softc *, 180 struct radeonfb_port *, int, int); 181 182 static int radeonfb_drm_print(void *, const char *); 183 184 #ifdef RADEONFB_DEBUG 185 int radeon_debug = 1; 186 #define DPRINTF(x) \ 187 if (radeon_debug) printf x 188 #define PRINTREG(r) DPRINTF((#r " = %08x\n", GET32(sc, r))) 189 #define PRINTPLL(r) DPRINTF((#r " = %08x\n", GETPLL(sc, r))) 190 #else 191 #define DPRINTF(x) 192 #define PRINTREG(r) 193 #define PRINTPLL(r) 194 #endif 195 196 #define ROUNDUP(x,y) (((x) + ((y) - 1)) & ~((y) - 1)) 197 198 #ifndef RADEON_DEFAULT_MODE 199 /* any reasonably modern display should handle this */ 200 #define RADEON_DEFAULT_MODE "1024x768x60" 201 #endif 202 203 extern const u_char rasops_cmap[768]; 204 205 const char *radeonfb_default_mode = RADEON_DEFAULT_MODE; 206 207 static struct { 208 int size; /* minimum memory size (MB) */ 209 int maxx; /* maximum x dimension */ 210 int maxy; /* maximum y dimension */ 211 int maxbpp; /* maximum bpp */ 212 int maxdisp; /* maximum logical display count */ 213 } radeonfb_limits[] = { 214 { 32, 2048, 1536, 32, 2 }, 215 { 16, 1600, 1200, 32, 2 }, 216 { 8, 1600, 1200, 32, 1 }, 217 { 0, 0, 0, 0, 0 }, 218 }; 219 220 static struct wsscreen_descr radeonfb_stdscreen = { 221 "fb", /* name */ 222 0, 0, /* ncols, nrows */ 223 NULL, /* textops */ 224 8, 16, /* fontwidth, fontheight */ 225 WSSCREEN_WSCOLORS | WSSCREEN_REVERSE, /* capabilities */ 226 0, /* modecookie */ 227 }; 228 229 struct wsdisplay_accessops radeonfb_accessops = { 230 radeonfb_ioctl, 231 radeonfb_mmap, 232 NULL, /* vcons_alloc_screen */ 233 NULL, /* vcons_free_screen */ 234 NULL, /* vcons_show_screen */ 235 NULL, /* load_font */ 236 NULL, /* pollc */ 237 NULL, /* scroll */ 238 }; 239 240 static struct { 241 uint16_t devid; 242 uint16_t family; 243 uint16_t flags; 244 } radeonfb_devices[] = 245 { 246 /* R100 family */ 247 { PCI_PRODUCT_ATI_RADEON_R100_QD, RADEON_R100, 0 }, 248 { PCI_PRODUCT_ATI_RADEON_R100_QE, RADEON_R100, 0 }, 249 { PCI_PRODUCT_ATI_RADEON_R100_QF, RADEON_R100, 0 }, 250 { PCI_PRODUCT_ATI_RADEON_R100_QG, RADEON_R100, 0 }, 251 252 /* RV100 family */ 253 { PCI_PRODUCT_ATI_RADEON_RV100_LY, RADEON_RV100, RFB_MOB }, 254 { PCI_PRODUCT_ATI_RADEON_RV100_LZ, RADEON_RV100, RFB_MOB }, 255 { PCI_PRODUCT_ATI_RADEON_RV100_QY, RADEON_RV100, 0 }, 256 { PCI_PRODUCT_ATI_RADEON_RV100_QZ, RADEON_RV100, 0 }, 257 258 /* RS100 family */ 259 { PCI_PRODUCT_ATI_RADEON_RS100_4136, RADEON_RS100, 0 }, 260 { PCI_PRODUCT_ATI_RADEON_RS100_4336, RADEON_RS100, RFB_MOB }, 261 262 /* RS200/RS250 family */ 263 { PCI_PRODUCT_ATI_RADEON_RS200_4337, RADEON_RS200, RFB_MOB }, 264 { PCI_PRODUCT_ATI_RADEON_RS200_A7, RADEON_RS200, 0 }, 265 { PCI_PRODUCT_ATI_RADEON_RS250_B7, RADEON_RS200, RFB_MOB }, 266 { PCI_PRODUCT_ATI_RADEON_RS250_D7, RADEON_RS200, 0 }, 267 268 /* R200 family */ 269 /* add more R200 products? , 5148 */ 270 { PCI_PRODUCT_ATI_RADEON_R200_BB, RADEON_R200, 0 }, 271 { PCI_PRODUCT_ATI_RADEON_R200_BC, RADEON_R200, 0 }, 272 { PCI_PRODUCT_ATI_RADEON_R200_QH, RADEON_R200, 0 }, 273 { PCI_PRODUCT_ATI_RADEON_R200_QL, RADEON_R200, 0 }, 274 { PCI_PRODUCT_ATI_RADEON_R200_QM, RADEON_R200, 0 }, 275 276 /* RV200 family */ 277 { PCI_PRODUCT_ATI_RADEON_RV200_LW, RADEON_RV200, RFB_MOB }, 278 { PCI_PRODUCT_ATI_RADEON_RV200_LX, RADEON_RV200, RFB_MOB }, 279 { PCI_PRODUCT_ATI_RADEON_RV200_QW, RADEON_RV200, 0 }, 280 { PCI_PRODUCT_ATI_RADEON_RV200_QX, RADEON_RV200, 0 }, 281 282 /* RV250 family */ 283 { PCI_PRODUCT_ATI_RADEON_RV250_4966, RADEON_RV250, 0 }, 284 { PCI_PRODUCT_ATI_RADEON_RV250_4967, RADEON_RV250, 0 }, 285 { PCI_PRODUCT_ATI_RADEON_RV250_4C64, RADEON_RV250, RFB_MOB }, 286 { PCI_PRODUCT_ATI_RADEON_RV250_4C66, RADEON_RV250, RFB_MOB }, 287 { PCI_PRODUCT_ATI_RADEON_RV250_4C67, RADEON_RV250, RFB_MOB }, 288 289 /* RS300 family */ 290 { PCI_PRODUCT_ATI_RADEON_RS300_X5, RADEON_RS300, 0 }, 291 { PCI_PRODUCT_ATI_RADEON_RS300_X4, RADEON_RS300, 0 }, 292 { PCI_PRODUCT_ATI_RADEON_RS300_7834, RADEON_RS300, 0 }, 293 { PCI_PRODUCT_ATI_RADEON_RS300_7835, RADEON_RS300, RFB_MOB }, 294 295 /* RV280 family */ 296 { PCI_PRODUCT_ATI_RADEON_RV280_5960, RADEON_RV280, 0 }, 297 { PCI_PRODUCT_ATI_RADEON_RV280_5961, RADEON_RV280, 0 }, 298 { PCI_PRODUCT_ATI_RADEON_RV280_5962, RADEON_RV280, 0 }, 299 { PCI_PRODUCT_ATI_RADEON_RV280_5963, RADEON_RV280, 0 }, 300 { PCI_PRODUCT_ATI_RADEON_RV280_5964, RADEON_RV280, 0 }, 301 { PCI_PRODUCT_ATI_RADEON_RV280_5C61, RADEON_RV280, RFB_MOB }, 302 { PCI_PRODUCT_ATI_RADEON_RV280_5C63, RADEON_RV280, RFB_MOB }, 303 304 /* R300 family */ 305 { PCI_PRODUCT_ATI_RADEON_R300_AD, RADEON_R300, 0 }, 306 { PCI_PRODUCT_ATI_RADEON_R300_AE, RADEON_R300, 0 }, 307 { PCI_PRODUCT_ATI_RADEON_R300_AF, RADEON_R300, 0 }, 308 { PCI_PRODUCT_ATI_RADEON_R300_AG, RADEON_R300, 0 }, 309 { PCI_PRODUCT_ATI_RADEON_R300_ND, RADEON_R300, 0 }, 310 { PCI_PRODUCT_ATI_RADEON_R300_NE, RADEON_R300, 0 }, 311 { PCI_PRODUCT_ATI_RADEON_R300_NF, RADEON_R300, 0 }, 312 { PCI_PRODUCT_ATI_RADEON_R300_NG, RADEON_R300, 0 }, 313 314 /* RV350/RV360 family */ 315 { PCI_PRODUCT_ATI_RADEON_RV350_AP, RADEON_RV350, 0 }, 316 { PCI_PRODUCT_ATI_RADEON_RV350_AQ, RADEON_RV350, 0 }, 317 { PCI_PRODUCT_ATI_RADEON_RV360_AR, RADEON_RV350, 0 }, 318 { PCI_PRODUCT_ATI_RADEON_RV350_AS, RADEON_RV350, 0 }, 319 { PCI_PRODUCT_ATI_RADEON_RV350_AT, RADEON_RV350, 0 }, 320 { PCI_PRODUCT_ATI_RADEON_RV350_AV, RADEON_RV350, 0 }, 321 { PCI_PRODUCT_ATI_RADEON_RV350_NP, RADEON_RV350, RFB_MOB }, 322 { PCI_PRODUCT_ATI_RADEON_RV350_NQ, RADEON_RV350, RFB_MOB }, 323 { PCI_PRODUCT_ATI_RADEON_RV350_NR, RADEON_RV350, RFB_MOB }, 324 { PCI_PRODUCT_ATI_RADEON_RV350_NS, RADEON_RV350, RFB_MOB }, 325 { PCI_PRODUCT_ATI_RADEON_RV350_NT, RADEON_RV350, RFB_MOB }, 326 { PCI_PRODUCT_ATI_RADEON_RV350_NV, RADEON_RV350, RFB_MOB }, 327 328 /* R350/R360 family */ 329 { PCI_PRODUCT_ATI_RADEON_R350_AH, RADEON_R350, 0 }, 330 { PCI_PRODUCT_ATI_RADEON_R350_AI, RADEON_R350, 0 }, 331 { PCI_PRODUCT_ATI_RADEON_R350_AJ, RADEON_R350, 0 }, 332 { PCI_PRODUCT_ATI_RADEON_R350_AK, RADEON_R350, 0 }, 333 { PCI_PRODUCT_ATI_RADEON_R350_NH, RADEON_R350, 0 }, 334 { PCI_PRODUCT_ATI_RADEON_R350_NI, RADEON_R350, 0 }, 335 { PCI_PRODUCT_ATI_RADEON_R350_NK, RADEON_R350, 0 }, 336 { PCI_PRODUCT_ATI_RADEON_R360_NJ, RADEON_R350, 0 }, 337 338 /* RV380/RV370 family */ 339 { PCI_PRODUCT_ATI_RADEON_RV380_3150, RADEON_RV380, RFB_MOB }, 340 { PCI_PRODUCT_ATI_RADEON_RV380_3154, RADEON_RV380, RFB_MOB }, 341 { PCI_PRODUCT_ATI_RADEON_RV380_3E50, RADEON_RV380, 0 }, 342 { PCI_PRODUCT_ATI_RADEON_RV380_3E54, RADEON_RV380, 0 }, 343 { PCI_PRODUCT_ATI_RADEON_RV370_5460, RADEON_RV380, RFB_MOB }, 344 { PCI_PRODUCT_ATI_RADEON_RV370_5464, RADEON_RV380, RFB_MOB }, 345 { PCI_PRODUCT_ATI_RADEON_RV370_5B60, RADEON_RV380, 0 }, 346 { PCI_PRODUCT_ATI_RADEON_RV370_5B64, RADEON_RV380, 0 }, 347 { PCI_PRODUCT_ATI_RADEON_RV370_5B65, RADEON_RV380, 0 }, 348 349 /* R420/R423 family */ 350 { PCI_PRODUCT_ATI_RADEON_R420_JH, RADEON_R420, 0 }, 351 { PCI_PRODUCT_ATI_RADEON_R420_JI, RADEON_R420, 0 }, 352 { PCI_PRODUCT_ATI_RADEON_R420_JJ, RADEON_R420, 0 }, 353 { PCI_PRODUCT_ATI_RADEON_R420_JK, RADEON_R420, 0 }, 354 { PCI_PRODUCT_ATI_RADEON_R420_JL, RADEON_R420, 0 }, 355 { PCI_PRODUCT_ATI_RADEON_R420_JM, RADEON_R420, 0 }, 356 { PCI_PRODUCT_ATI_RADEON_R420_JN, RADEON_R420, RFB_MOB }, 357 { PCI_PRODUCT_ATI_RADEON_R420_JP, RADEON_R420, 0 }, 358 { PCI_PRODUCT_ATI_RADEON_R423_UH, RADEON_R420, 0 }, 359 { PCI_PRODUCT_ATI_RADEON_R423_UI, RADEON_R420, 0 }, 360 { PCI_PRODUCT_ATI_RADEON_R423_UJ, RADEON_R420, 0 }, 361 { PCI_PRODUCT_ATI_RADEON_R423_UK, RADEON_R420, 0 }, 362 { PCI_PRODUCT_ATI_RADEON_R423_UQ, RADEON_R420, 0 }, 363 { PCI_PRODUCT_ATI_RADEON_R423_UR, RADEON_R420, 0 }, 364 { PCI_PRODUCT_ATI_RADEON_R423_UT, RADEON_R420, 0 }, 365 { PCI_PRODUCT_ATI_RADEON_R423_5D57, RADEON_R420, 0 }, 366 { PCI_PRODUCT_ATI_RADEON_R430_554F, RADEON_R420, 0 }, 367 368 { 0, 0, 0 } 369 }; 370 371 static struct { 372 int divider; 373 int mask; 374 } radeonfb_dividers[] = { 375 { 1, 0 }, 376 { 2, 1 }, 377 { 3, 4 }, 378 { 4, 2 }, 379 { 6, 6 }, 380 { 8, 3 }, 381 { 12, 7 }, 382 { 0, 0 } 383 }; 384 385 /* 386 * This table taken from X11. 387 */ 388 static const struct { 389 int family; 390 struct radeon_tmds_pll plls[4]; 391 } radeonfb_tmds_pll[] = { 392 { RADEON_R100, {{12000, 0xa1b}, {-1, 0xa3f}}}, 393 { RADEON_RV100, {{12000, 0xa1b}, {-1, 0xa3f}}}, 394 { RADEON_RS100, {{0, 0}}}, 395 { RADEON_RV200, {{15000, 0xa1b}, {-1, 0xa3f}}}, 396 { RADEON_RS200, {{15000, 0xa1b}, {-1, 0xa3f}}}, 397 { RADEON_R200, {{15000, 0xa1b}, {-1, 0xa3f}}}, 398 { RADEON_RV250, {{15500, 0x81b}, {-1, 0x83f}}}, 399 { RADEON_RS300, {{0, 0}}}, 400 { RADEON_RV280, {{13000, 0x400f4}, {15000, 0x400f7}}}, 401 { RADEON_R300, {{-1, 0xb01cb}}}, 402 { RADEON_R350, {{-1, 0xb01cb}}}, 403 { RADEON_RV350, {{15000, 0xb0155}, {-1, 0xb01cb}}}, 404 { RADEON_RV380, {{15000, 0xb0155}, {-1, 0xb01cb}}}, 405 { RADEON_R420, {{-1, 0xb01cb}}}, 406 }; 407 408 #define RADEONFB_BACKLIGHT_MAX 255 /* Maximum backlight level. */ 409 410 411 CFATTACH_DECL_NEW(radeonfb, sizeof (struct radeonfb_softc), 412 radeonfb_match, radeonfb_attach, NULL, NULL); 413 414 static int 415 radeonfb_match(device_t parent, cfdata_t match, void *aux) 416 { 417 const struct pci_attach_args *pa = aux; 418 int i; 419 420 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_ATI) 421 return 0; 422 423 for (i = 0; radeonfb_devices[i].devid; i++) { 424 if (PCI_PRODUCT(pa->pa_id) == radeonfb_devices[i].devid) 425 return 100; /* high to defeat VGA/VESA */ 426 } 427 428 return 0; 429 } 430 431 static void 432 radeonfb_attach(device_t parent, device_t dev, void *aux) 433 { 434 struct radeonfb_softc *sc = device_private(dev); 435 const struct pci_attach_args *pa = aux; 436 const char *mptr; 437 bus_size_t bsz; 438 pcireg_t screg; 439 int i, j, fg, bg, ul, flags; 440 uint32_t v; 441 442 sc->sc_dev = dev; 443 sc->sc_id = pa->pa_id; 444 for (i = 0; radeonfb_devices[i].devid; i++) { 445 if (PCI_PRODUCT(sc->sc_id) == radeonfb_devices[i].devid) 446 break; 447 } 448 449 pci_devinfo(sc->sc_id, pa->pa_class, 0, sc->sc_devinfo, 450 sizeof(sc->sc_devinfo)); 451 452 aprint_naive("\n"); 453 aprint_normal(": %s\n", sc->sc_devinfo); 454 455 DPRINTF((prop_dictionary_externalize(device_properties(dev)))); 456 457 KASSERT(radeonfb_devices[i].devid != 0); 458 sc->sc_pt = pa->pa_tag; 459 sc->sc_iot = pa->pa_iot; 460 sc->sc_pc = pa->pa_pc; 461 sc->sc_family = radeonfb_devices[i].family; 462 sc->sc_flags = radeonfb_devices[i].flags; 463 464 /* enable memory and IO access */ 465 screg = pci_conf_read(sc->sc_pc, sc->sc_pt, PCI_COMMAND_STATUS_REG); 466 screg |= PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE; 467 pci_conf_write(sc->sc_pc, sc->sc_pt, PCI_COMMAND_STATUS_REG, screg); 468 469 /* 470 * Some flags are general to entire chip families, and rather 471 * than clutter up the table with them, we go ahead and set 472 * them here. 473 */ 474 switch (sc->sc_family) { 475 case RADEON_RS100: 476 case RADEON_RS200: 477 sc->sc_flags |= RFB_IGP | RFB_RV100; 478 break; 479 480 case RADEON_RV100: 481 case RADEON_RV200: 482 case RADEON_RV250: 483 case RADEON_RV280: 484 sc->sc_flags |= RFB_RV100; 485 break; 486 487 case RADEON_RS300: 488 sc->sc_flags |= RFB_SDAC | RFB_IGP | RFB_RV100; 489 break; 490 491 case RADEON_R300: 492 case RADEON_RV350: 493 case RADEON_R350: 494 case RADEON_RV380: 495 case RADEON_R420: 496 /* newer chips */ 497 sc->sc_flags |= RFB_R300; 498 break; 499 500 case RADEON_R100: 501 sc->sc_flags |= RFB_NCRTC2; 502 break; 503 } 504 505 if ((sc->sc_family == RADEON_RV200) || 506 (sc->sc_family == RADEON_RV250) || 507 (sc->sc_family == RADEON_RV280) || 508 (sc->sc_family == RADEON_RV350)) { 509 bool inverted = 0; 510 /* backlight level is linear */ 511 DPRINTF(("found RV* chip, backlight is supposedly linear\n")); 512 prop_dictionary_get_bool(device_properties(sc->sc_dev), 513 "backlight_level_reverted", &inverted); 514 if (inverted) { 515 DPRINTF(("nope, it's inverted\n")); 516 sc->sc_flags |= RFB_INV_BLIGHT; 517 } 518 } else 519 sc->sc_flags |= RFB_INV_BLIGHT; 520 521 /* 522 * XXX: to support true multihead, this must change. 523 */ 524 sc->sc_ndisplays = 1; 525 526 /* XXX: */ 527 if (!HAS_CRTC2(sc)) { 528 sc->sc_ndisplays = 1; 529 } 530 531 if (pci_mapreg_map(pa, RADEON_MAPREG_MMIO, PCI_MAPREG_TYPE_MEM, 0, 532 &sc->sc_regt, &sc->sc_regh, &sc->sc_regaddr, 533 &sc->sc_regsz) != 0) { 534 aprint_error("%s: unable to map registers!\n", XNAME(sc)); 535 goto error; 536 } 537 538 if (pci_mapreg_info(sc->sc_pc, sc->sc_pt, PCI_MAPREG_ROM, 539 PCI_MAPREG_TYPE_ROM, &sc->sc_romaddr, &sc->sc_romsz, &flags) != 0) 540 { 541 aprint_error("%s: unable to find ROM!\n", XNAME(sc)); 542 goto error; 543 } 544 sc->sc_romt = sc->sc_memt; 545 546 /* scratch register test... */ 547 if (radeonfb_scratch_test(sc, RADEON_BIOS_0_SCRATCH, 0x55555555) || 548 radeonfb_scratch_test(sc, RADEON_BIOS_0_SCRATCH, 0xaaaaaaaa)) { 549 aprint_error("%s: scratch register test failed!\n", XNAME(sc)); 550 goto error; 551 } 552 553 PRINTREG(RADEON_BIOS_4_SCRATCH); 554 PRINTREG(RADEON_FP_GEN_CNTL); 555 sc->sc_fp_gen_cntl = GET32(sc, RADEON_FP_GEN_CNTL); 556 PRINTREG(RADEON_FP2_GEN_CNTL); 557 PRINTREG(RADEON_TMDS_CNTL); 558 PRINTREG(RADEON_TMDS_TRANSMITTER_CNTL); 559 PRINTREG(RADEON_TMDS_PLL_CNTL); 560 PRINTREG(RADEON_LVDS_GEN_CNTL); 561 PRINTREG(RADEON_FP_HORZ_STRETCH); 562 PRINTREG(RADEON_FP_VERT_STRETCH); 563 564 /* XXX: RV100 specific */ 565 PUT32(sc, RADEON_TMDS_PLL_CNTL, 0xa27); 566 567 PATCH32(sc, RADEON_TMDS_TRANSMITTER_CNTL, 568 RADEON_TMDS_TRANSMITTER_PLLEN, 569 RADEON_TMDS_TRANSMITTER_PLLEN | RADEON_TMDS_TRANSMITTER_PLLRST); 570 571 radeonfb_i2c_init(sc); 572 573 radeonfb_loadbios(sc, pa); 574 575 #ifdef RADEONFB_BIOS_INIT 576 if (radeonfb_bios_init(sc)) { 577 aprint_error("%s: BIOS inititialization failed\n", XNAME(sc)); 578 } 579 #endif 580 581 if (radeonfb_getclocks(sc)) { 582 aprint_error("%s: Unable to get reference clocks from BIOS\n", 583 XNAME(sc)); 584 goto error; 585 } 586 587 if (radeonfb_gettmds(sc)) { 588 aprint_error("%s: Unable to identify TMDS PLL settings\n", 589 XNAME(sc)); 590 goto error; 591 } 592 593 aprint_verbose("%s: refclk = %d.%03d MHz, refdiv = %d " 594 "minpll = %d, maxpll = %d\n", XNAME(sc), 595 (int)sc->sc_refclk / 1000, (int)sc->sc_refclk % 1000, 596 (int)sc->sc_refdiv, (int)sc->sc_minpll, (int)sc->sc_maxpll); 597 598 radeonfb_getconnectors(sc); 599 600 radeonfb_set_fbloc(sc); 601 602 for (i = 0; radeonfb_limits[i].size; i++) { 603 if (sc->sc_memsz >= radeonfb_limits[i].size) { 604 sc->sc_maxx = radeonfb_limits[i].maxx; 605 sc->sc_maxy = radeonfb_limits[i].maxy; 606 sc->sc_maxbpp = radeonfb_limits[i].maxbpp; 607 /* framebuffer offset, start at a 4K page */ 608 sc->sc_fboffset = sc->sc_memsz / 609 radeonfb_limits[i].maxdisp; 610 /* 611 * we use the fbsize to figure out where we can store 612 * things like cursor data. 613 */ 614 sc->sc_fbsize = 615 ROUNDUP(ROUNDUP(sc->sc_maxx * sc->sc_maxbpp / 8 , 616 RADEON_STRIDEALIGN) * sc->sc_maxy, 617 4096); 618 break; 619 } 620 } 621 622 623 radeonfb_init_misc(sc); 624 radeonfb_init_palette(sc, 0); 625 if (HAS_CRTC2(sc)) 626 radeonfb_init_palette(sc, 1); 627 628 /* program the DAC wirings */ 629 for (i = 0; i < (HAS_CRTC2(sc) ? 2 : 1); i++) { 630 switch (sc->sc_ports[i].rp_dac_type) { 631 case RADEON_DAC_PRIMARY: 632 PATCH32(sc, RADEON_DAC_CNTL2, 633 i ? RADEON_DAC2_DAC_CLK_SEL : 0, 634 ~RADEON_DAC2_DAC_CLK_SEL); 635 break; 636 case RADEON_DAC_TVDAC: 637 /* we always use the TVDAC to drive a secondary analog 638 * CRT for now. if we ever support TV-out this will 639 * have to change. 640 */ 641 SET32(sc, RADEON_DAC_CNTL2, 642 RADEON_DAC2_DAC2_CLK_SEL); 643 PATCH32(sc, RADEON_DISP_HW_DEBUG, 644 i ? 0 : RADEON_CRT2_DISP1_SEL, 645 ~RADEON_CRT2_DISP1_SEL); 646 break; 647 } 648 } 649 PRINTREG(RADEON_DAC_CNTL2); 650 PRINTREG(RADEON_DISP_HW_DEBUG); 651 652 /* other DAC programming */ 653 v = GET32(sc, RADEON_DAC_CNTL); 654 v &= (RADEON_DAC_RANGE_CNTL_MASK | RADEON_DAC_BLANKING); 655 v |= RADEON_DAC_MASK_ALL | RADEON_DAC_8BIT_EN; 656 PUT32(sc, RADEON_DAC_CNTL, v); 657 PRINTREG(RADEON_DAC_CNTL); 658 659 /* XXX: this may need more investigation */ 660 PUT32(sc, RADEON_TV_DAC_CNTL, 0x00280203); 661 PRINTREG(RADEON_TV_DAC_CNTL); 662 663 /* enable TMDS */ 664 SET32(sc, RADEON_FP_GEN_CNTL, 665 RADEON_FP_TMDS_EN | 666 RADEON_FP_CRTC_DONT_SHADOW_VPAR | 667 RADEON_FP_CRTC_DONT_SHADOW_HEND); 668 /* 669 * XXX 670 * no idea why this is necessary - if I do not clear this bit on my 671 * iBook G4 the screen remains black, even though it's already clear. 672 * It needs to be set on my Sun XVR-100 for the DVI port to work 673 */ 674 675 if (sc->sc_fp_gen_cntl & RADEON_FP_SEL_CRTC2) { 676 SET32(sc, RADEON_FP_GEN_CNTL, RADEON_FP_SEL_CRTC2); 677 } else 678 CLR32(sc, RADEON_FP_GEN_CNTL, RADEON_FP_SEL_CRTC2); 679 680 if (HAS_CRTC2(sc)) 681 SET32(sc, RADEON_FP2_GEN_CNTL, RADEON_FP2_SRC_SEL_CRTC2); 682 683 /* 684 * we use bus_space_map instead of pci_mapreg, because we don't 685 * need the full aperature space. no point in wasting virtual 686 * address space we don't intend to use, right? 687 */ 688 if ((sc->sc_memsz < (4096 * 1024)) || 689 (pci_mapreg_info(sc->sc_pc, sc->sc_pt, RADEON_MAPREG_VRAM, 690 PCI_MAPREG_TYPE_MEM, &sc->sc_memaddr, &bsz, NULL) != 0) || 691 (bsz < sc->sc_memsz)) { 692 sc->sc_memsz = 0; 693 aprint_error("%s: Bad frame buffer configuration\n", 694 XNAME(sc)); 695 goto error; 696 } 697 698 /* 64 MB should be enough -- more just wastes map entries */ 699 if (sc->sc_memsz > (64 << 20)) 700 sc->sc_memsz = (64 << 20); 701 702 sc->sc_memt = pa->pa_memt; 703 if (bus_space_map(sc->sc_memt, sc->sc_memaddr, sc->sc_memsz, 704 BUS_SPACE_MAP_LINEAR, &sc->sc_memh) != 0) { 705 sc->sc_memsz = 0; 706 aprint_error("%s: Unable to map frame buffer\n", XNAME(sc)); 707 goto error; 708 } 709 710 aprint_normal("%s: %d MB aperture at 0x%08x, " 711 "%d KB registers at 0x%08x\n", XNAME(sc), 712 (int)sc->sc_memsz >> 20, (unsigned)sc->sc_memaddr, 713 (int)sc->sc_regsz >> 10, (unsigned)sc->sc_regaddr); 714 715 /* setup default video mode from devprop (allows PROM override) */ 716 sc->sc_defaultmode = radeonfb_default_mode; 717 if (prop_dictionary_get_cstring_nocopy(device_properties(sc->sc_dev), 718 "videomode", &mptr)) { 719 720 strncpy(sc->sc_modebuf, mptr, sizeof(sc->sc_modebuf)); 721 sc->sc_defaultmode = sc->sc_modebuf; 722 } 723 724 /* initialize some basic display parameters */ 725 for (i = 0; i < sc->sc_ndisplays; i++) { 726 struct radeonfb_display *dp = &sc->sc_displays[i]; 727 struct rasops_info *ri; 728 long defattr; 729 struct wsemuldisplaydev_attach_args aa; 730 731 /* 732 * Figure out how many "displays" (desktops) we are going to 733 * support. If more than one, then each CRTC gets its own 734 * programming. 735 * 736 * XXX: this code needs to change to support mergedfb. 737 * XXX: would be nice to allow this to be overridden 738 */ 739 if (HAS_CRTC2(sc) && (sc->sc_ndisplays == 1)) { 740 DPRINTF(("dual crtcs!\n")); 741 dp->rd_ncrtcs = 2; 742 dp->rd_crtcs[0].rc_number = 0; 743 dp->rd_crtcs[1].rc_number = 1; 744 } else { 745 dp->rd_ncrtcs = 1; 746 dp->rd_crtcs[0].rc_number = i; 747 } 748 749 /* set up port pointer */ 750 for (j = 0; j < dp->rd_ncrtcs; j++) { 751 dp->rd_crtcs[j].rc_port = 752 &sc->sc_ports[dp->rd_crtcs[j].rc_number]; 753 } 754 755 dp->rd_softc = sc; 756 dp->rd_wsmode = WSDISPLAYIO_MODE_EMUL; 757 dp->rd_bg = WS_DEFAULT_BG; 758 #if 0 759 dp->rd_bpp = sc->sc_maxbpp; /* XXX: for now */ 760 #else 761 dp->rd_bpp = RADEONFB_DEFAULT_DEPTH; /* XXX */ 762 #endif 763 /* for text mode, we pick a resolution that won't 764 * require panning */ 765 radeonfb_pickres(dp, &dp->rd_virtx, &dp->rd_virty, 0); 766 767 aprint_normal("%s: display %d: " 768 "initial virtual resolution %dx%d at %d bpp\n", 769 XNAME(sc), i, dp->rd_virtx, dp->rd_virty, dp->rd_bpp); 770 771 /* now select the *video mode* that we will use */ 772 for (j = 0; j < dp->rd_ncrtcs; j++) { 773 const struct videomode *vmp; 774 vmp = radeonfb_port_mode(sc, dp->rd_crtcs[j].rc_port, 775 dp->rd_virtx, dp->rd_virty); 776 777 /* 778 * virtual resolution should be at least as high as 779 * physical 780 */ 781 if (dp->rd_virtx < vmp->hdisplay || 782 dp->rd_virty < vmp->vdisplay) { 783 dp->rd_virtx = vmp->hdisplay; 784 dp->rd_virty = vmp->vdisplay; 785 } 786 787 dp->rd_crtcs[j].rc_videomode = *vmp; 788 printf("%s: port %d: physical %dx%d %dHz\n", 789 XNAME(sc), j, vmp->hdisplay, vmp->vdisplay, 790 DIVIDE(DIVIDE(vmp->dot_clock * 1000, 791 vmp->htotal), vmp->vtotal)); 792 } 793 794 /* N.B.: radeon wants 64-byte aligned stride */ 795 dp->rd_stride = dp->rd_virtx * dp->rd_bpp / 8; 796 dp->rd_stride = ROUNDUP(dp->rd_stride, RADEON_STRIDEALIGN); 797 798 dp->rd_offset = sc->sc_fboffset * i; 799 dp->rd_fbptr = (vaddr_t)bus_space_vaddr(sc->sc_memt, 800 sc->sc_memh) + dp->rd_offset; 801 dp->rd_curoff = sc->sc_fbsize; 802 dp->rd_curptr = dp->rd_fbptr + dp->rd_curoff; 803 804 DPRINTF(("fpbtr = %p\n", (void *)dp->rd_fbptr)); 805 806 switch (dp->rd_bpp) { 807 case 8: 808 dp->rd_format = 2; 809 break; 810 case 32: 811 dp->rd_format = 6; 812 break; 813 default: 814 aprint_error("%s: bad depth %d\n", XNAME(sc), 815 dp->rd_bpp); 816 goto error; 817 } 818 819 DPRINTF(("init engine\n")); 820 /* XXX: this seems suspicious - per display engine 821 initialization? */ 822 radeonfb_engine_init(dp); 823 824 /* copy the template into place */ 825 dp->rd_wsscreens_storage[0] = radeonfb_stdscreen; 826 dp->rd_wsscreens = dp->rd_wsscreens_storage; 827 828 /* and make up the list */ 829 dp->rd_wsscreenlist.nscreens = 1; 830 dp->rd_wsscreenlist.screens = (void *)&dp->rd_wsscreens; 831 832 vcons_init(&dp->rd_vd, dp, dp->rd_wsscreens, 833 &radeonfb_accessops); 834 835 dp->rd_vd.init_screen = radeonfb_init_screen; 836 837 dp->rd_console = 0; 838 prop_dictionary_get_bool(device_properties(sc->sc_dev), 839 "is_console", &dp->rd_console); 840 841 dp->rd_vscreen.scr_flags |= VCONS_SCREEN_IS_STATIC; 842 843 844 vcons_init_screen(&dp->rd_vd, &dp->rd_vscreen, 845 dp->rd_console, &defattr); 846 847 ri = &dp->rd_vscreen.scr_ri; 848 849 /* clear the screen */ 850 rasops_unpack_attr(defattr, &fg, &bg, &ul); 851 radeonfb_rectfill(dp, 0, 0, ri->ri_width, ri->ri_height, 852 ri->ri_devcmap[bg & 0xf]); 853 854 dp->rd_wsscreens->textops = &ri->ri_ops; 855 dp->rd_wsscreens->capabilities = ri->ri_caps; 856 dp->rd_wsscreens->nrows = ri->ri_rows; 857 dp->rd_wsscreens->ncols = ri->ri_cols; 858 859 #ifdef SPLASHSCREEN 860 dp->rd_splash.si_depth = ri->ri_depth; 861 dp->rd_splash.si_bits = ri->ri_bits; 862 dp->rd_splash.si_hwbits = ri->ri_hwbits; 863 dp->rd_splash.si_width = ri->ri_width; 864 dp->rd_splash.si_height = ri->ri_height; 865 dp->rd_splash.si_stride = ri->ri_stride; 866 dp->rd_splash.si_fillrect = NULL; 867 #endif 868 if (dp->rd_console) { 869 870 radeonfb_modeswitch(dp); 871 wsdisplay_cnattach(dp->rd_wsscreens, ri, 0, 0, 872 defattr); 873 #ifdef SPLASHSCREEN 874 if (splash_render(&dp->rd_splash, 875 SPLASH_F_CENTER|SPLASH_F_FILL) == 0) 876 SCREEN_DISABLE_DRAWING(&dp->rd_vscreen); 877 else 878 #endif 879 vcons_replay_msgbuf(&dp->rd_vscreen); 880 } else { 881 882 /* 883 * since we're not the console we can postpone 884 * the rest until someone actually allocates a 885 * screen for us. but we do clear the screen 886 * at least. 887 */ 888 memset(ri->ri_bits, 0, 1024); 889 890 radeonfb_modeswitch(dp); 891 #ifdef SPLASHSCREEN 892 if (splash_render(&dp->rd_splash, 893 SPLASH_F_CENTER|SPLASH_F_FILL) == 0) 894 SCREEN_DISABLE_DRAWING(&dp->rd_vscreen); 895 #endif 896 } 897 898 aa.console = dp->rd_console; 899 aa.scrdata = &dp->rd_wsscreenlist; 900 aa.accessops = &radeonfb_accessops; 901 aa.accesscookie = &dp->rd_vd; 902 903 config_found(sc->sc_dev, &aa, wsemuldisplaydevprint); 904 905 radeonfb_blank(dp, 0); 906 907 /* Initialise delayed lvds operations for backlight. */ 908 callout_init(&dp->rd_bl_lvds_co, 0); 909 callout_setfunc(&dp->rd_bl_lvds_co, 910 radeonfb_lvds_callout, dp); 911 } 912 913 /* 914 * if we have console output via firmware like on sparc64 it may 915 * interfere with DAC programming so program the palette again 916 * here after we took over 917 */ 918 radeonfb_init_palette(sc, 0); 919 if (HAS_CRTC2(sc)) 920 radeonfb_init_palette(sc, 1); 921 922 pmf_event_register(dev, PMFE_DISPLAY_BRIGHTNESS_UP, 923 radeonfb_brightness_up, TRUE); 924 pmf_event_register(dev, PMFE_DISPLAY_BRIGHTNESS_DOWN, 925 radeonfb_brightness_down, TRUE); 926 927 config_found_ia(dev, "drm", aux, radeonfb_drm_print); 928 929 return; 930 931 error: 932 if (sc->sc_biossz) 933 free(sc->sc_bios, M_DEVBUF); 934 935 if (sc->sc_regsz) 936 bus_space_unmap(sc->sc_regt, sc->sc_regh, sc->sc_regsz); 937 938 if (sc->sc_memsz) 939 bus_space_unmap(sc->sc_memt, sc->sc_memh, sc->sc_memsz); 940 } 941 942 static int 943 radeonfb_drm_print(void *aux, const char *pnp) 944 { 945 if (pnp) 946 aprint_normal("drm at %s", pnp); 947 return (UNCONF); 948 } 949 950 int 951 radeonfb_ioctl(void *v, void *vs, 952 unsigned long cmd, void *d, int flag, struct lwp *l) 953 { 954 struct vcons_data *vd; 955 struct radeonfb_display *dp; 956 struct radeonfb_softc *sc; 957 struct wsdisplay_param *param; 958 959 vd = (struct vcons_data *)v; 960 dp = (struct radeonfb_display *)vd->cookie; 961 sc = dp->rd_softc; 962 963 switch (cmd) { 964 case WSDISPLAYIO_GTYPE: 965 *(unsigned *)d = WSDISPLAY_TYPE_PCIMISC; 966 return 0; 967 968 case WSDISPLAYIO_GINFO: 969 if (vd->active != NULL) { 970 struct wsdisplay_fbinfo *fb; 971 fb = (struct wsdisplay_fbinfo *)d; 972 fb->width = dp->rd_virtx; 973 fb->height = dp->rd_virty; 974 fb->depth = dp->rd_bpp; 975 fb->cmsize = 256; 976 return 0; 977 } else 978 return ENODEV; 979 case WSDISPLAYIO_GVIDEO: 980 if (radeonfb_isblank(dp)) 981 *(unsigned *)d = WSDISPLAYIO_VIDEO_OFF; 982 else 983 *(unsigned *)d = WSDISPLAYIO_VIDEO_ON; 984 return 0; 985 986 case WSDISPLAYIO_SVIDEO: 987 radeonfb_blank(dp, 988 (*(unsigned int *)d == WSDISPLAYIO_VIDEO_OFF)); 989 return 0; 990 991 case WSDISPLAYIO_GETCMAP: 992 #if 0 993 if (dp->rd_bpp == 8) 994 return radeonfb_getcmap(sc, 995 (struct wsdisplay_cmap *)d); 996 #endif 997 return EINVAL; 998 999 case WSDISPLAYIO_PUTCMAP: 1000 #if 0 1001 if (dp->rd_bpp == 8) 1002 return radeonfb_putcmap(sc, 1003 (struct wsdisplay_cmap *)d); 1004 #endif 1005 return EINVAL; 1006 1007 case WSDISPLAYIO_LINEBYTES: 1008 *(unsigned *)d = dp->rd_stride; 1009 return 0; 1010 1011 case WSDISPLAYIO_SMODE: 1012 if (*(int *)d != dp->rd_wsmode) { 1013 dp->rd_wsmode = *(int *)d; 1014 if ((dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) && 1015 (dp->rd_vd.active)) { 1016 radeonfb_engine_init(dp); 1017 radeonfb_init_palette(sc, dp == &sc->sc_displays[0] ? 0 : 1); 1018 radeonfb_modeswitch(dp); 1019 vcons_redraw_screen(dp->rd_vd.active); 1020 } 1021 } 1022 return 0; 1023 1024 case WSDISPLAYIO_GCURMAX: 1025 ((struct wsdisplay_curpos *)d)->x = RADEON_CURSORMAXX; 1026 ((struct wsdisplay_curpos *)d)->y = RADEON_CURSORMAXY; 1027 return 0; 1028 1029 case WSDISPLAYIO_SCURSOR: 1030 return radeonfb_set_cursor(dp, (struct wsdisplay_cursor *)d); 1031 1032 case WSDISPLAYIO_GCURSOR: 1033 return EPASSTHROUGH; 1034 1035 case WSDISPLAYIO_GCURPOS: 1036 ((struct wsdisplay_curpos *)d)->x = dp->rd_cursor.rc_pos.x; 1037 ((struct wsdisplay_curpos *)d)->y = dp->rd_cursor.rc_pos.y; 1038 return 0; 1039 1040 case WSDISPLAYIO_SCURPOS: 1041 return radeonfb_set_curpos(dp, (struct wsdisplay_curpos *)d); 1042 1043 case WSDISPLAYIO_SSPLASH: 1044 #if defined(SPLASHSCREEN) 1045 if (*(int *)d == 1) { 1046 SCREEN_DISABLE_DRAWING(&dp->rd_vscreen); 1047 splash_render(&dp->rd_splash, 1048 SPLASH_F_CENTER|SPLASH_F_FILL); 1049 } else 1050 SCREEN_ENABLE_DRAWING(&dp->rd_vscreen); 1051 return 0; 1052 #else 1053 return ENODEV; 1054 #endif 1055 case WSDISPLAYIO_GETPARAM: 1056 param = (struct wsdisplay_param *)d; 1057 if (param->param == WSDISPLAYIO_PARAM_BACKLIGHT) { 1058 param->min = 0; 1059 param->max = RADEONFB_BACKLIGHT_MAX; 1060 param->curval = radeonfb_get_backlight(dp); 1061 return 0; 1062 } 1063 return EPASSTHROUGH; 1064 1065 case WSDISPLAYIO_SETPARAM: 1066 param = (struct wsdisplay_param *)d; 1067 if (param->param == WSDISPLAYIO_PARAM_BACKLIGHT) { 1068 return radeonfb_set_backlight(dp, param->curval); 1069 } 1070 return EPASSTHROUGH; 1071 1072 /* PCI config read/write passthrough. */ 1073 case PCI_IOC_CFGREAD: 1074 case PCI_IOC_CFGWRITE: 1075 return pci_devioctl(sc->sc_pc, sc->sc_pt, cmd, d, flag, l); 1076 1077 case WSDISPLAYIO_GET_BUSID: 1078 return wsdisplayio_busid_pci(sc->sc_dev, sc->sc_pc, 1079 sc->sc_pt, d); 1080 1081 case WSDISPLAYIO_GET_EDID: { 1082 struct wsdisplayio_edid_info *ei = d; 1083 return wsdisplayio_get_edid(sc->sc_dev, ei); 1084 } 1085 1086 default: 1087 return EPASSTHROUGH; 1088 } 1089 } 1090 1091 paddr_t 1092 radeonfb_mmap(void *v, void *vs, off_t offset, int prot) 1093 { 1094 struct vcons_data *vd; 1095 struct radeonfb_display *dp; 1096 struct radeonfb_softc *sc; 1097 paddr_t pa; 1098 1099 vd = (struct vcons_data *)v; 1100 dp = (struct radeonfb_display *)vd->cookie; 1101 sc = dp->rd_softc; 1102 1103 /* XXX: note that we don't allow mapping of registers right now */ 1104 /* XXX: this means that the XFree86 radeon driver won't work */ 1105 if ((offset >= 0) && (offset < (dp->rd_virty * dp->rd_stride))) { 1106 pa = bus_space_mmap(sc->sc_memt, 1107 sc->sc_memaddr + dp->rd_offset + offset, 0, 1108 prot, BUS_SPACE_MAP_LINEAR); 1109 return pa; 1110 } 1111 1112 #ifdef RADEONFB_MMAP_BARS 1113 /* 1114 * restrict all other mappings to processes with superuser privileges 1115 * or the kernel itself 1116 */ 1117 if (kauth_authorize_generic(kauth_cred_get(), KAUTH_GENERIC_ISSUSER, 1118 NULL) != 0) { 1119 aprint_error_dev(sc->sc_dev, "mmap() rejected.\n"); 1120 return -1; 1121 } 1122 1123 if ((offset >= sc->sc_regaddr) && 1124 (offset < sc->sc_regaddr + sc->sc_regsz)) { 1125 return bus_space_mmap(sc->sc_regt, offset, 0, prot, 1126 BUS_SPACE_MAP_LINEAR); 1127 } 1128 1129 if ((offset >= sc->sc_memaddr) && 1130 (offset < sc->sc_memaddr + sc->sc_memsz)) { 1131 return bus_space_mmap(sc->sc_memt, offset, 0, prot, 1132 BUS_SPACE_MAP_LINEAR); 1133 } 1134 1135 if ((offset >= sc->sc_romaddr) && 1136 (offset < sc->sc_romaddr + sc->sc_romsz)) { 1137 return bus_space_mmap(sc->sc_memt, offset, 0, prot, 1138 BUS_SPACE_MAP_LINEAR); 1139 } 1140 1141 #ifdef PCI_MAGIC_IO_RANGE 1142 /* allow mapping of IO space */ 1143 if ((offset >= PCI_MAGIC_IO_RANGE) && 1144 (offset < PCI_MAGIC_IO_RANGE + 0x10000)) { 1145 pa = bus_space_mmap(sc->sc_iot, offset - PCI_MAGIC_IO_RANGE, 1146 0, prot, 0); 1147 return pa; 1148 } 1149 #endif /* macppc */ 1150 1151 #endif /* RADEONFB_MMAP_BARS */ 1152 1153 return -1; 1154 } 1155 1156 static void 1157 radeonfb_loadbios(struct radeonfb_softc *sc, const struct pci_attach_args *pa) 1158 { 1159 bus_space_tag_t romt; 1160 bus_space_handle_t romh, biosh; 1161 bus_size_t romsz; 1162 bus_addr_t ptr; 1163 1164 if (pci_mapreg_map(pa, PCI_MAPREG_ROM, PCI_MAPREG_TYPE_ROM, 1165 BUS_SPACE_MAP_PREFETCHABLE, &romt, &romh, NULL, &romsz) != 0) { 1166 aprint_verbose("%s: unable to map BIOS!\n", XNAME(sc)); 1167 return; 1168 } 1169 1170 pci_find_rom(pa, romt, romh, PCI_ROM_CODE_TYPE_X86, &biosh, 1171 &sc->sc_biossz); 1172 if (sc->sc_biossz == 0) { 1173 aprint_verbose("%s: Video BIOS not present\n", XNAME(sc)); 1174 return; 1175 } 1176 1177 sc->sc_bios = malloc(sc->sc_biossz, M_DEVBUF, M_WAITOK); 1178 bus_space_read_region_1(romt, biosh, 0, sc->sc_bios, sc->sc_biossz); 1179 1180 /* unmap the PCI expansion rom */ 1181 bus_space_unmap(romt, romh, romsz); 1182 1183 /* turn off rom decoder now */ 1184 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM, 1185 pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM) & 1186 ~PCI_MAPREG_ROM_ENABLE); 1187 1188 ptr = GETBIOS16(sc, 0x48); 1189 if ((GETBIOS32(sc, ptr + 4) == 0x41544f4d /* "ATOM" */) || 1190 (GETBIOS32(sc, ptr + 4) == 0x4d4f5441 /* "MOTA" */)) { 1191 sc->sc_flags |= RFB_ATOM; 1192 } 1193 1194 aprint_verbose("%s: Found %d KB %s BIOS\n", XNAME(sc), 1195 (unsigned)sc->sc_biossz >> 10, IS_ATOM(sc) ? "ATOM" : "Legacy"); 1196 } 1197 1198 1199 uint32_t 1200 radeonfb_get32(struct radeonfb_softc *sc, uint32_t reg) 1201 { 1202 1203 return bus_space_read_4(sc->sc_regt, sc->sc_regh, reg); 1204 } 1205 1206 void 1207 radeonfb_put32(struct radeonfb_softc *sc, uint32_t reg, uint32_t val) 1208 { 1209 1210 bus_space_write_4(sc->sc_regt, sc->sc_regh, reg, val); 1211 } 1212 1213 void 1214 radeonfb_mask32(struct radeonfb_softc *sc, uint32_t reg, 1215 uint32_t andmask, uint32_t ormask) 1216 { 1217 int s; 1218 uint32_t val; 1219 1220 s = splhigh(); 1221 val = radeonfb_get32(sc, reg); 1222 val = (val & andmask) | ormask; 1223 radeonfb_put32(sc, reg, val); 1224 splx(s); 1225 } 1226 1227 uint32_t 1228 radeonfb_getindex(struct radeonfb_softc *sc, uint32_t idx) 1229 { 1230 int s; 1231 uint32_t val; 1232 1233 s = splhigh(); 1234 radeonfb_put32(sc, RADEON_MM_INDEX, idx); 1235 val = radeonfb_get32(sc, RADEON_MM_DATA); 1236 splx(s); 1237 1238 return (val); 1239 } 1240 1241 void 1242 radeonfb_putindex(struct radeonfb_softc *sc, uint32_t idx, uint32_t val) 1243 { 1244 int s; 1245 1246 s = splhigh(); 1247 radeonfb_put32(sc, RADEON_MM_INDEX, idx); 1248 radeonfb_put32(sc, RADEON_MM_DATA, val); 1249 splx(s); 1250 } 1251 1252 void 1253 radeonfb_maskindex(struct radeonfb_softc *sc, uint32_t idx, 1254 uint32_t andmask, uint32_t ormask) 1255 { 1256 int s; 1257 uint32_t val; 1258 1259 s = splhigh(); 1260 radeonfb_put32(sc, RADEON_MM_INDEX, idx); 1261 val = radeonfb_get32(sc, RADEON_MM_DATA); 1262 val = (val & andmask) | ormask; 1263 radeonfb_put32(sc, RADEON_MM_DATA, val); 1264 splx(s); 1265 } 1266 1267 uint32_t 1268 radeonfb_getpll(struct radeonfb_softc *sc, uint32_t idx) 1269 { 1270 int s; 1271 uint32_t val; 1272 1273 s = splhigh(); 1274 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, idx & 0x3f); 1275 val = radeonfb_get32(sc, RADEON_CLOCK_CNTL_DATA); 1276 if (HAS_R300CG(sc)) 1277 radeonfb_r300cg_workaround(sc); 1278 splx(s); 1279 1280 return (val); 1281 } 1282 1283 void 1284 radeonfb_putpll(struct radeonfb_softc *sc, uint32_t idx, uint32_t val) 1285 { 1286 int s; 1287 1288 s = splhigh(); 1289 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, (idx & 0x3f) | 1290 RADEON_PLL_WR_EN); 1291 radeonfb_put32(sc, RADEON_CLOCK_CNTL_DATA, val); 1292 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, 0); 1293 splx(s); 1294 } 1295 1296 void 1297 radeonfb_maskpll(struct radeonfb_softc *sc, uint32_t idx, 1298 uint32_t andmask, uint32_t ormask) 1299 { 1300 int s; 1301 uint32_t val; 1302 1303 s = splhigh(); 1304 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, (idx & 0x3f) | 1305 RADEON_PLL_WR_EN); 1306 val = radeonfb_get32(sc, RADEON_CLOCK_CNTL_DATA); 1307 val = (val & andmask) | ormask; 1308 radeonfb_put32(sc, RADEON_CLOCK_CNTL_DATA, val); 1309 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, 0); 1310 splx(s); 1311 } 1312 1313 int 1314 radeonfb_scratch_test(struct radeonfb_softc *sc, int reg, uint32_t v) 1315 { 1316 uint32_t saved; 1317 1318 saved = GET32(sc, reg); 1319 PUT32(sc, reg, v); 1320 if (GET32(sc, reg) != v) { 1321 return -1; 1322 } 1323 PUT32(sc, reg, saved); 1324 return 0; 1325 } 1326 1327 uintmax_t 1328 radeonfb_getprop_num(struct radeonfb_softc *sc, const char *name, 1329 uintmax_t defval) 1330 { 1331 prop_number_t pn; 1332 pn = prop_dictionary_get(device_properties(sc->sc_dev), name); 1333 if (pn == NULL) { 1334 return defval; 1335 } 1336 KASSERT(prop_object_type(pn) == PROP_TYPE_NUMBER); 1337 return (prop_number_integer_value(pn)); 1338 } 1339 1340 int 1341 radeonfb_getclocks(struct radeonfb_softc *sc) 1342 { 1343 bus_addr_t ptr; 1344 int refclk = 0; 1345 int refdiv = 0; 1346 int minpll = 0; 1347 int maxpll = 0; 1348 1349 /* load initial property values if port/board provides them */ 1350 refclk = radeonfb_getprop_num(sc, "refclk", 0) & 0xffff; 1351 refdiv = radeonfb_getprop_num(sc, "refdiv", 0) & 0xffff; 1352 minpll = radeonfb_getprop_num(sc, "minpll", 0) & 0xffffffffU; 1353 maxpll = radeonfb_getprop_num(sc, "maxpll", 0) & 0xffffffffU; 1354 1355 if (refclk && refdiv && minpll && maxpll) 1356 goto dontprobe; 1357 1358 if (!sc->sc_biossz) { 1359 /* no BIOS */ 1360 aprint_verbose("%s: No video BIOS, using default clocks\n", 1361 XNAME(sc)); 1362 if (IS_IGP(sc)) 1363 refclk = refclk ? refclk : 1432; 1364 else 1365 refclk = refclk ? refclk : 2700; 1366 refdiv = refdiv ? refdiv : 12; 1367 minpll = minpll ? minpll : 12500; 1368 maxpll = maxpll ? maxpll : 35000; 1369 } else if (IS_ATOM(sc)) { 1370 /* ATOM BIOS */ 1371 ptr = GETBIOS16(sc, 0x48); 1372 ptr = GETBIOS16(sc, ptr + 32); /* aka MasterDataStart */ 1373 ptr = GETBIOS16(sc, ptr + 12); /* pll info block */ 1374 refclk = refclk ? refclk : GETBIOS16(sc, ptr + 82); 1375 minpll = minpll ? minpll : GETBIOS16(sc, ptr + 78); 1376 maxpll = maxpll ? maxpll : GETBIOS16(sc, ptr + 32); 1377 /* 1378 * ATOM BIOS doesn't supply a reference divider, so we 1379 * have to probe for it. 1380 */ 1381 if (refdiv < 2) 1382 refdiv = GETPLL(sc, RADEON_PPLL_REF_DIV) & 1383 RADEON_PPLL_REF_DIV_MASK; 1384 /* 1385 * if probe is zero, just assume one that should work 1386 * for most parts 1387 */ 1388 if (refdiv < 2) 1389 refdiv = 12; 1390 1391 } else { 1392 /* Legacy BIOS */ 1393 ptr = GETBIOS16(sc, 0x48); 1394 ptr = GETBIOS16(sc, ptr + 0x30); 1395 refclk = refclk ? refclk : GETBIOS16(sc, ptr + 0x0E); 1396 refdiv = refdiv ? refdiv : GETBIOS16(sc, ptr + 0x10); 1397 minpll = minpll ? minpll : GETBIOS32(sc, ptr + 0x12); 1398 maxpll = maxpll ? maxpll : GETBIOS32(sc, ptr + 0x16); 1399 } 1400 1401 1402 dontprobe: 1403 sc->sc_refclk = refclk * 10; 1404 sc->sc_refdiv = refdiv; 1405 sc->sc_minpll = minpll * 10; 1406 sc->sc_maxpll = maxpll * 10; 1407 return 0; 1408 } 1409 1410 int 1411 radeonfb_calc_dividers(struct radeonfb_softc *sc, uint32_t dotclock, 1412 uint32_t *postdivbit, uint32_t *feedbackdiv) 1413 { 1414 int i; 1415 uint32_t outfreq; 1416 int div; 1417 1418 DPRINTF(("dot clock: %u\n", dotclock)); 1419 for (i = 0; (div = radeonfb_dividers[i].divider) != 0; i++) { 1420 outfreq = div * dotclock; 1421 if ((outfreq >= sc->sc_minpll) && 1422 (outfreq <= sc->sc_maxpll)) { 1423 DPRINTF(("outfreq: %u\n", outfreq)); 1424 *postdivbit = 1425 ((uint32_t)radeonfb_dividers[i].mask << 16); 1426 DPRINTF(("post divider: %d (mask %x)\n", div, 1427 *postdivbit)); 1428 break; 1429 } 1430 } 1431 1432 if (div == 0) 1433 return 1; 1434 1435 *feedbackdiv = DIVIDE(sc->sc_refdiv * outfreq, sc->sc_refclk); 1436 DPRINTF(("feedback divider: %d\n", *feedbackdiv)); 1437 return 0; 1438 } 1439 1440 #if 0 1441 #ifdef RADEONFB_DEBUG 1442 static void 1443 dump_buffer(const char *pfx, void *buffer, unsigned int size) 1444 { 1445 char asc[17]; 1446 unsigned ptr = (unsigned)buffer; 1447 char *start = (char *)(ptr & ~0xf); 1448 char *end = (char *)(ptr + size); 1449 1450 end = (char *)(((unsigned)end + 0xf) & ~0xf); 1451 1452 if (pfx == NULL) { 1453 pfx = ""; 1454 } 1455 1456 while (start < end) { 1457 unsigned offset = (unsigned)start & 0xf; 1458 if (offset == 0) { 1459 printf("%s%x: ", pfx, (unsigned)start); 1460 } 1461 if (((unsigned)start < ptr) || 1462 ((unsigned)start >= (ptr + size))) { 1463 printf(" "); 1464 asc[offset] = ' '; 1465 } else { 1466 printf("%02x", *(unsigned char *)start); 1467 if ((*start >= ' ') && (*start <= '~')) { 1468 asc[offset] = *start; 1469 } else { 1470 asc[offset] = '.'; 1471 } 1472 } 1473 asc[offset + 1] = 0; 1474 if (offset % 2) { 1475 printf(" "); 1476 } 1477 if (offset == 15) { 1478 printf(" %s\n", asc); 1479 } 1480 start++; 1481 } 1482 } 1483 #endif 1484 #endif 1485 1486 int 1487 radeonfb_getconnectors(struct radeonfb_softc *sc) 1488 { 1489 int i; 1490 int found = 0; 1491 1492 for (i = 0; i < 2; i++) { 1493 sc->sc_ports[i].rp_mon_type = RADEON_MT_UNKNOWN; 1494 sc->sc_ports[i].rp_ddc_type = RADEON_DDC_NONE; 1495 sc->sc_ports[i].rp_dac_type = RADEON_DAC_UNKNOWN; 1496 sc->sc_ports[i].rp_conn_type = RADEON_CONN_NONE; 1497 sc->sc_ports[i].rp_tmds_type = RADEON_TMDS_UNKNOWN; 1498 } 1499 1500 /* 1501 * This logic is borrowed from Xorg's radeon driver. 1502 */ 1503 if (!sc->sc_biossz) 1504 goto nobios; 1505 1506 if (IS_ATOM(sc)) { 1507 /* not done yet */ 1508 } else { 1509 uint16_t ptr; 1510 int port = 0; 1511 1512 ptr = GETBIOS16(sc, 0x48); 1513 ptr = GETBIOS16(sc, ptr + 0x50); 1514 for (i = 1; i < 4; i++) { 1515 uint16_t entry; 1516 uint8_t conn, ddc, dac, tmds; 1517 1518 /* 1519 * Parse the connector table. From reading the code, 1520 * it appears to made up of 16-bit entries for each 1521 * connector. The 16-bits are defined as: 1522 * 1523 * bits 12-15 - connector type (0 == end of table) 1524 * bits 8-11 - DDC type 1525 * bits 5-7 - ??? 1526 * bit 4 - TMDS type (1 = EXT, 0 = INT) 1527 * bits 1-3 - ??? 1528 * bit 0 - DAC, 1 = TVDAC, 0 = primary 1529 */ 1530 if (!GETBIOS8(sc, ptr + i * 2) && i > 1) 1531 break; 1532 entry = GETBIOS16(sc, ptr + i * 2); 1533 1534 conn = (entry >> 12) & 0xf; 1535 ddc = (entry >> 8) & 0xf; 1536 dac = (entry & 0x1) ? RADEON_DAC_TVDAC : 1537 RADEON_DAC_PRIMARY; 1538 tmds = ((entry >> 4) & 0x1) ? RADEON_TMDS_EXT : 1539 RADEON_TMDS_INT; 1540 1541 if (conn == RADEON_CONN_NONE) 1542 continue; /* no connector */ 1543 1544 if ((found > 0) && 1545 (sc->sc_ports[port].rp_ddc_type == ddc)) { 1546 /* duplicate entry for same connector */ 1547 continue; 1548 } 1549 1550 /* internal DDC_DVI port gets priority */ 1551 if ((ddc == RADEON_DDC_DVI) || (port == 1)) 1552 port = 0; 1553 else 1554 port = 1; 1555 1556 sc->sc_ports[port].rp_ddc_type = 1557 ddc > RADEON_DDC_CRT2 ? RADEON_DDC_NONE : ddc; 1558 sc->sc_ports[port].rp_dac_type = dac; 1559 sc->sc_ports[port].rp_conn_type = 1560 min(conn, RADEON_CONN_UNSUPPORTED) ; 1561 1562 sc->sc_ports[port].rp_tmds_type = tmds; 1563 1564 if ((conn != RADEON_CONN_DVI_I) && 1565 (conn != RADEON_CONN_DVI_D) && 1566 (tmds == RADEON_TMDS_INT)) 1567 sc->sc_ports[port].rp_tmds_type = 1568 RADEON_TMDS_UNKNOWN; 1569 1570 found += (port + 1); 1571 } 1572 } 1573 1574 nobios: 1575 if (!found) { 1576 DPRINTF(("No connector info in BIOS!\n")); 1577 /* default, port 0 = internal TMDS, port 1 = CRT */ 1578 sc->sc_ports[0].rp_mon_type = RADEON_MT_UNKNOWN; 1579 sc->sc_ports[0].rp_ddc_type = RADEON_DDC_DVI; 1580 sc->sc_ports[0].rp_dac_type = RADEON_DAC_TVDAC; 1581 sc->sc_ports[0].rp_conn_type = RADEON_CONN_DVI_D; 1582 sc->sc_ports[0].rp_tmds_type = RADEON_TMDS_INT; 1583 1584 sc->sc_ports[1].rp_mon_type = RADEON_MT_UNKNOWN; 1585 sc->sc_ports[1].rp_ddc_type = RADEON_DDC_VGA; 1586 sc->sc_ports[1].rp_dac_type = RADEON_DAC_PRIMARY; 1587 sc->sc_ports[1].rp_conn_type = RADEON_CONN_CRT; 1588 sc->sc_ports[1].rp_tmds_type = RADEON_TMDS_EXT; 1589 } 1590 1591 /* 1592 * Fixup for RS300/RS350/RS400 chips, that lack a primary DAC. 1593 * these chips should use TVDAC for the VGA port. 1594 */ 1595 if (HAS_SDAC(sc)) { 1596 if (sc->sc_ports[0].rp_conn_type == RADEON_CONN_CRT) { 1597 sc->sc_ports[0].rp_dac_type = RADEON_DAC_TVDAC; 1598 sc->sc_ports[1].rp_dac_type = RADEON_DAC_PRIMARY; 1599 } else { 1600 sc->sc_ports[1].rp_dac_type = RADEON_DAC_TVDAC; 1601 sc->sc_ports[0].rp_dac_type = RADEON_DAC_PRIMARY; 1602 } 1603 } else if (!HAS_CRTC2(sc)) { 1604 sc->sc_ports[0].rp_dac_type = RADEON_DAC_PRIMARY; 1605 } 1606 1607 for (i = 0; i < 2; i++) { 1608 char edid[128]; 1609 uint8_t ddc; 1610 struct edid_info *eip = &sc->sc_ports[i].rp_edid; 1611 prop_data_t edid_data; 1612 1613 DPRINTF(("Port #%d:\n", i)); 1614 DPRINTF((" conn = %d\n", sc->sc_ports[i].rp_conn_type)); 1615 DPRINTF((" ddc = %d\n", sc->sc_ports[i].rp_ddc_type)); 1616 DPRINTF((" dac = %d\n", sc->sc_ports[i].rp_dac_type)); 1617 DPRINTF((" tmds = %d\n", sc->sc_ports[i].rp_tmds_type)); 1618 1619 sc->sc_ports[i].rp_edid_valid = 0; 1620 /* first look for static EDID data */ 1621 if ((edid_data = prop_dictionary_get(device_properties( 1622 sc->sc_dev), "EDID")) != NULL) { 1623 1624 aprint_normal_dev(sc->sc_dev, "using static EDID\n"); 1625 memcpy(edid, prop_data_data_nocopy(edid_data), 128); 1626 if (edid_parse(edid, eip) == 0) { 1627 1628 sc->sc_ports[i].rp_edid_valid = 1; 1629 } 1630 } 1631 /* if we didn't find any we'll try to talk to the monitor */ 1632 if (sc->sc_ports[i].rp_edid_valid != 1) { 1633 1634 ddc = sc->sc_ports[i].rp_ddc_type; 1635 if (ddc != RADEON_DDC_NONE) { 1636 if ((radeonfb_i2c_read_edid(sc, ddc, edid) 1637 == 0) && (edid_parse(edid, eip) == 0)) { 1638 1639 sc->sc_ports[i].rp_edid_valid = 1; 1640 edid_print(eip); 1641 } 1642 } 1643 } 1644 } 1645 1646 return found; 1647 } 1648 1649 int 1650 radeonfb_gettmds(struct radeonfb_softc *sc) 1651 { 1652 int i; 1653 1654 if (!sc->sc_biossz) { 1655 goto nobios; 1656 } 1657 1658 if (IS_ATOM(sc)) { 1659 /* XXX: not done yet */ 1660 } else { 1661 uint16_t ptr; 1662 int n; 1663 1664 ptr = GETBIOS16(sc, 0x48); 1665 ptr = GETBIOS16(sc, ptr + 0x34); 1666 DPRINTF(("DFP table revision %d\n", GETBIOS8(sc, ptr))); 1667 if (GETBIOS8(sc, ptr) == 3) { 1668 /* revision three table */ 1669 n = GETBIOS8(sc, ptr + 5) + 1; 1670 n = min(n, 4); 1671 1672 memset(sc->sc_tmds_pll, 0, sizeof (sc->sc_tmds_pll)); 1673 for (i = 0; i < n; i++) { 1674 sc->sc_tmds_pll[i].rtp_pll = GETBIOS32(sc, 1675 ptr + i * 10 + 8); 1676 sc->sc_tmds_pll[i].rtp_freq = GETBIOS16(sc, 1677 ptr + i * 10 + 0x10); 1678 DPRINTF(("TMDS_PLL dot clock %d pll %x\n", 1679 sc->sc_tmds_pll[i].rtp_freq, 1680 sc->sc_tmds_pll[i].rtp_pll)); 1681 } 1682 return 0; 1683 } 1684 } 1685 1686 nobios: 1687 DPRINTF(("no suitable DFP table present\n")); 1688 for (i = 0; 1689 i < sizeof (radeonfb_tmds_pll) / sizeof (radeonfb_tmds_pll[0]); 1690 i++) { 1691 int j; 1692 1693 if (radeonfb_tmds_pll[i].family != sc->sc_family) 1694 continue; 1695 1696 for (j = 0; j < 4; j++) { 1697 sc->sc_tmds_pll[j] = radeonfb_tmds_pll[i].plls[j]; 1698 DPRINTF(("TMDS_PLL dot clock %d pll %x\n", 1699 sc->sc_tmds_pll[j].rtp_freq, 1700 sc->sc_tmds_pll[j].rtp_pll)); 1701 } 1702 return 0; 1703 } 1704 1705 return -1; 1706 } 1707 1708 const struct videomode * 1709 radeonfb_modelookup(const char *name) 1710 { 1711 int i; 1712 1713 for (i = 0; i < videomode_count; i++) 1714 if (!strcmp(name, videomode_list[i].name)) 1715 return &videomode_list[i]; 1716 1717 return NULL; 1718 } 1719 1720 void 1721 radeonfb_pllwriteupdate(struct radeonfb_softc *sc, int crtc) 1722 { 1723 if (crtc) { 1724 while (GETPLL(sc, RADEON_P2PLL_REF_DIV) & 1725 RADEON_P2PLL_ATOMIC_UPDATE_R); 1726 SETPLL(sc, RADEON_P2PLL_REF_DIV, RADEON_P2PLL_ATOMIC_UPDATE_W); 1727 } else { 1728 while (GETPLL(sc, RADEON_PPLL_REF_DIV) & 1729 RADEON_PPLL_ATOMIC_UPDATE_R); 1730 SETPLL(sc, RADEON_PPLL_REF_DIV, RADEON_PPLL_ATOMIC_UPDATE_W); 1731 } 1732 } 1733 1734 void 1735 radeonfb_pllwaitatomicread(struct radeonfb_softc *sc, int crtc) 1736 { 1737 int i; 1738 1739 for (i = 10000; i; i--) { 1740 if (crtc) { 1741 if (GETPLL(sc, RADEON_P2PLL_REF_DIV) & 1742 RADEON_P2PLL_ATOMIC_UPDATE_R) 1743 break; 1744 } else { 1745 if (GETPLL(sc, RADEON_PPLL_REF_DIV) & 1746 RADEON_PPLL_ATOMIC_UPDATE_R) 1747 break; 1748 } 1749 } 1750 } 1751 1752 void 1753 radeonfb_program_vclk(struct radeonfb_softc *sc, int dotclock, int crtc) 1754 { 1755 uint32_t pbit = 0; 1756 uint32_t feed = 0; 1757 uint32_t data; 1758 #if 1 1759 int i; 1760 #endif 1761 1762 radeonfb_calc_dividers(sc, dotclock, &pbit, &feed); 1763 1764 if (crtc == 0) { 1765 1766 /* XXXX: mobility workaround missing */ 1767 /* XXXX: R300 stuff missing */ 1768 1769 PATCHPLL(sc, RADEON_VCLK_ECP_CNTL, 1770 RADEON_VCLK_SRC_SEL_CPUCLK, 1771 ~RADEON_VCLK_SRC_SEL_MASK); 1772 1773 /* put vclk into reset, use atomic updates */ 1774 SETPLL(sc, RADEON_PPLL_CNTL, 1775 RADEON_PPLL_REFCLK_SEL | 1776 RADEON_PPLL_FBCLK_SEL | 1777 RADEON_PPLL_RESET | 1778 RADEON_PPLL_ATOMIC_UPDATE_EN | 1779 RADEON_PPLL_VGA_ATOMIC_UPDATE_EN); 1780 1781 /* select clock 3 */ 1782 #if 0 1783 PATCH32(sc, RADEON_CLOCK_CNTL_INDEX, RADEON_PLL_DIV_SEL, 1784 ~RADEON_PLL_DIV_SEL); 1785 #else 1786 PATCH32(sc, RADEON_CLOCK_CNTL_INDEX, 0, 1787 ~RADEON_PLL_DIV_SEL); 1788 #endif 1789 1790 /* XXX: R300 family -- program divider differently? */ 1791 1792 /* program reference divider */ 1793 PATCHPLL(sc, RADEON_PPLL_REF_DIV, sc->sc_refdiv, 1794 ~RADEON_PPLL_REF_DIV_MASK); 1795 PRINTPLL(RADEON_PPLL_REF_DIV); 1796 1797 #if 0 1798 data = GETPLL(sc, RADEON_PPLL_DIV_3); 1799 data &= ~(RADEON_PPLL_FB3_DIV_MASK | 1800 RADEON_PPLL_POST3_DIV_MASK); 1801 data |= pbit; 1802 data |= (feed & RADEON_PPLL_FB3_DIV_MASK); 1803 PUTPLL(sc, RADEON_PPLL_DIV_3, data); 1804 #else 1805 for (i = 0; i < 4; i++) { 1806 } 1807 #endif 1808 1809 /* use the atomic update */ 1810 radeonfb_pllwriteupdate(sc, crtc); 1811 1812 /* and wait for it to complete */ 1813 radeonfb_pllwaitatomicread(sc, crtc); 1814 1815 /* program HTOTAL (why?) */ 1816 PUTPLL(sc, RADEON_HTOTAL_CNTL, 0); 1817 1818 /* drop reset */ 1819 CLRPLL(sc, RADEON_PPLL_CNTL, 1820 RADEON_PPLL_RESET | RADEON_PPLL_SLEEP | 1821 RADEON_PPLL_ATOMIC_UPDATE_EN | 1822 RADEON_PPLL_VGA_ATOMIC_UPDATE_EN); 1823 1824 PRINTPLL(RADEON_PPLL_CNTL); 1825 1826 /* give clock time to lock */ 1827 delay(50000); 1828 1829 PATCHPLL(sc, RADEON_VCLK_ECP_CNTL, 1830 RADEON_VCLK_SRC_SEL_PPLLCLK, 1831 ~RADEON_VCLK_SRC_SEL_MASK); 1832 1833 } else { 1834 1835 PATCHPLL(sc, RADEON_PIXCLKS_CNTL, 1836 RADEON_PIX2CLK_SRC_SEL_CPUCLK, 1837 ~RADEON_PIX2CLK_SRC_SEL_MASK); 1838 1839 /* put vclk into reset, use atomic updates */ 1840 SETPLL(sc, RADEON_P2PLL_CNTL, 1841 RADEON_P2PLL_RESET | 1842 RADEON_P2PLL_ATOMIC_UPDATE_EN | 1843 RADEON_P2PLL_VGA_ATOMIC_UPDATE_EN); 1844 1845 /* XXX: R300 family -- program divider differently? */ 1846 1847 /* program reference divider */ 1848 PATCHPLL(sc, RADEON_P2PLL_REF_DIV, sc->sc_refdiv, 1849 ~RADEON_P2PLL_REF_DIV_MASK); 1850 1851 /* program feedback and post dividers */ 1852 data = GETPLL(sc, RADEON_P2PLL_DIV_0); 1853 data &= ~(RADEON_P2PLL_FB0_DIV_MASK | 1854 RADEON_P2PLL_POST0_DIV_MASK); 1855 data |= pbit; 1856 data |= (feed & RADEON_P2PLL_FB0_DIV_MASK); 1857 PUTPLL(sc, RADEON_P2PLL_DIV_0, data); 1858 1859 /* use the atomic update */ 1860 radeonfb_pllwriteupdate(sc, crtc); 1861 1862 /* and wait for it to complete */ 1863 radeonfb_pllwaitatomicread(sc, crtc); 1864 1865 /* program HTOTAL (why?) */ 1866 PUTPLL(sc, RADEON_HTOTAL2_CNTL, 0); 1867 1868 /* drop reset */ 1869 CLRPLL(sc, RADEON_P2PLL_CNTL, 1870 RADEON_P2PLL_RESET | RADEON_P2PLL_SLEEP | 1871 RADEON_P2PLL_ATOMIC_UPDATE_EN | 1872 RADEON_P2PLL_VGA_ATOMIC_UPDATE_EN); 1873 1874 /* allow time for clock to lock */ 1875 delay(50000); 1876 1877 PATCHPLL(sc, RADEON_PIXCLKS_CNTL, 1878 RADEON_PIX2CLK_SRC_SEL_P2PLLCLK, 1879 ~RADEON_PIX2CLK_SRC_SEL_MASK); 1880 } 1881 PRINTREG(RADEON_CRTC_MORE_CNTL); 1882 } 1883 1884 void 1885 radeonfb_modeswitch(struct radeonfb_display *dp) 1886 { 1887 struct radeonfb_softc *sc = dp->rd_softc; 1888 int i; 1889 1890 /* blank the display while we switch modes */ 1891 radeonfb_blank(dp, 1); 1892 1893 #if 0 1894 SET32(sc, RADEON_CRTC_EXT_CNTL, 1895 RADEON_CRTC_VSYNC_DIS | RADEON_CRTC_HSYNC_DIS | 1896 RADEON_CRTC_DISPLAY_DIS /* | RADEON_CRTC_DISP_REQ_EN_B */); 1897 #endif 1898 1899 /* these registers might get in the way... */ 1900 PUT32(sc, RADEON_OVR_CLR, 0); 1901 PUT32(sc, RADEON_OVR_WID_LEFT_RIGHT, 0); 1902 PUT32(sc, RADEON_OVR_WID_TOP_BOTTOM, 0); 1903 PUT32(sc, RADEON_OV0_SCALE_CNTL, 0); 1904 PUT32(sc, RADEON_SUBPIC_CNTL, 0); 1905 PUT32(sc, RADEON_VIPH_CONTROL, 0); 1906 PUT32(sc, RADEON_I2C_CNTL_1, 0); 1907 PUT32(sc, RADEON_GEN_INT_CNTL, 0); 1908 PUT32(sc, RADEON_CAP0_TRIG_CNTL, 0); 1909 PUT32(sc, RADEON_CAP1_TRIG_CNTL, 0); 1910 PUT32(sc, RADEON_SURFACE_CNTL, 0); 1911 1912 for (i = 0; i < dp->rd_ncrtcs; i++) 1913 radeonfb_setcrtc(dp, i); 1914 1915 /* activate the display */ 1916 radeonfb_blank(dp, 0); 1917 } 1918 1919 void 1920 radeonfb_setcrtc(struct radeonfb_display *dp, int index) 1921 { 1922 int crtc; 1923 struct videomode *mode; 1924 struct radeonfb_softc *sc; 1925 struct radeonfb_crtc *cp; 1926 uint32_t v; 1927 uint32_t gencntl; 1928 uint32_t htotaldisp; 1929 uint32_t hsyncstrt; 1930 uint32_t vtotaldisp; 1931 uint32_t vsyncstrt; 1932 uint32_t fphsyncstrt; 1933 uint32_t fpvsyncstrt; 1934 uint32_t fphtotaldisp; 1935 uint32_t fpvtotaldisp; 1936 uint32_t pitch; 1937 1938 sc = dp->rd_softc; 1939 cp = &dp->rd_crtcs[index]; 1940 crtc = cp->rc_number; 1941 mode = &cp->rc_videomode; 1942 1943 #if 1 1944 pitch = (((dp->rd_virtx * dp->rd_bpp) + ((dp->rd_bpp * 8) - 1)) / 1945 (dp->rd_bpp * 8)); 1946 #else 1947 pitch = (((sc->sc_maxx * sc->sc_maxbpp) + ((sc->sc_maxbpp * 8) - 1)) / 1948 (sc->sc_maxbpp * 8)); 1949 #endif 1950 //pitch = pitch | (pitch << 16); 1951 1952 switch (crtc) { 1953 case 0: 1954 gencntl = RADEON_CRTC_GEN_CNTL; 1955 htotaldisp = RADEON_CRTC_H_TOTAL_DISP; 1956 hsyncstrt = RADEON_CRTC_H_SYNC_STRT_WID; 1957 vtotaldisp = RADEON_CRTC_V_TOTAL_DISP; 1958 vsyncstrt = RADEON_CRTC_V_SYNC_STRT_WID; 1959 fpvsyncstrt = RADEON_FP_V_SYNC_STRT_WID; 1960 fphsyncstrt = RADEON_FP_H_SYNC_STRT_WID; 1961 fpvtotaldisp = RADEON_FP_CRTC_V_TOTAL_DISP; 1962 fphtotaldisp = RADEON_FP_CRTC_H_TOTAL_DISP; 1963 break; 1964 case 1: 1965 gencntl = RADEON_CRTC2_GEN_CNTL; 1966 htotaldisp = RADEON_CRTC2_H_TOTAL_DISP; 1967 hsyncstrt = RADEON_CRTC2_H_SYNC_STRT_WID; 1968 vtotaldisp = RADEON_CRTC2_V_TOTAL_DISP; 1969 vsyncstrt = RADEON_CRTC2_V_SYNC_STRT_WID; 1970 fpvsyncstrt = RADEON_FP_V2_SYNC_STRT_WID; 1971 fphsyncstrt = RADEON_FP_H2_SYNC_STRT_WID; 1972 fpvtotaldisp = RADEON_FP_CRTC2_V_TOTAL_DISP; 1973 fphtotaldisp = RADEON_FP_CRTC2_H_TOTAL_DISP; 1974 break; 1975 default: 1976 panic("Bad CRTC!"); 1977 break; 1978 } 1979 1980 /* 1981 * CRTC_GEN_CNTL - depth, accelerator mode, etc. 1982 */ 1983 /* only bother with 32bpp and 8bpp */ 1984 v = dp->rd_format << RADEON_CRTC_PIX_WIDTH_SHIFT; 1985 1986 if (crtc == 1) { 1987 v |= RADEON_CRTC2_CRT2_ON | RADEON_CRTC2_EN; 1988 } else { 1989 v |= RADEON_CRTC_EXT_DISP_EN | RADEON_CRTC_EN; 1990 } 1991 1992 if (mode->flags & VID_DBLSCAN) 1993 v |= RADEON_CRTC2_DBL_SCAN_EN; 1994 1995 if (mode->flags & VID_INTERLACE) 1996 v |= RADEON_CRTC2_INTERLACE_EN; 1997 1998 if (mode->flags & VID_CSYNC) { 1999 v |= RADEON_CRTC2_CSYNC_EN; 2000 if (crtc == 1) 2001 v |= RADEON_CRTC2_VSYNC_TRISTAT; 2002 } 2003 2004 PUT32(sc, gencntl, v); 2005 DPRINTF(("CRTC%s_GEN_CNTL = %08x\n", crtc ? "2" : "", v)); 2006 2007 /* 2008 * CRTC_EXT_CNTL - preserve disable flags, set ATI linear and EXT_CNT 2009 */ 2010 v = GET32(sc, RADEON_CRTC_EXT_CNTL); 2011 if (crtc == 0) { 2012 v &= (RADEON_CRTC_VSYNC_DIS | RADEON_CRTC_HSYNC_DIS | 2013 RADEON_CRTC_DISPLAY_DIS); 2014 v |= RADEON_XCRT_CNT_EN | RADEON_VGA_ATI_LINEAR; 2015 if (mode->flags & VID_CSYNC) 2016 v |= RADEON_CRTC_VSYNC_TRISTAT; 2017 } 2018 /* unconditional turn on CRT, in case first CRTC is DFP */ 2019 v |= RADEON_CRTC_CRT_ON; 2020 PUT32(sc, RADEON_CRTC_EXT_CNTL, v); 2021 PRINTREG(RADEON_CRTC_EXT_CNTL); 2022 2023 /* 2024 * H_TOTAL_DISP 2025 */ 2026 v = ((mode->hdisplay / 8) - 1) << 16; 2027 v |= (mode->htotal / 8) - 1; 2028 PUT32(sc, htotaldisp, v); 2029 DPRINTF(("CRTC%s_H_TOTAL_DISP = %08x\n", crtc ? "2" : "", v)); 2030 PUT32(sc, fphtotaldisp, v); 2031 DPRINTF(("FP_H%s_TOTAL_DISP = %08x\n", crtc ? "2" : "", v)); 2032 2033 /* 2034 * H_SYNC_STRT_WID 2035 */ 2036 v = (((mode->hsync_end - mode->hsync_start) / 8) << 16); 2037 v |= mode->hsync_start; 2038 if (mode->flags & VID_NHSYNC) 2039 v |= RADEON_CRTC_H_SYNC_POL; 2040 PUT32(sc, hsyncstrt, v); 2041 DPRINTF(("CRTC%s_H_SYNC_STRT_WID = %08x\n", crtc ? "2" : "", v)); 2042 PUT32(sc, fphsyncstrt, v); 2043 DPRINTF(("FP_H%s_SYNC_STRT_WID = %08x\n", crtc ? "2" : "", v)); 2044 2045 /* 2046 * V_TOTAL_DISP 2047 */ 2048 v = ((mode->vdisplay - 1) << 16); 2049 v |= (mode->vtotal - 1); 2050 PUT32(sc, vtotaldisp, v); 2051 DPRINTF(("CRTC%s_V_TOTAL_DISP = %08x\n", crtc ? "2" : "", v)); 2052 PUT32(sc, fpvtotaldisp, v); 2053 DPRINTF(("FP_V%s_TOTAL_DISP = %08x\n", crtc ? "2" : "", v)); 2054 2055 /* 2056 * V_SYNC_STRT_WID 2057 */ 2058 v = ((mode->vsync_end - mode->vsync_start) << 16); 2059 v |= (mode->vsync_start - 1); 2060 if (mode->flags & VID_NVSYNC) 2061 v |= RADEON_CRTC_V_SYNC_POL; 2062 PUT32(sc, vsyncstrt, v); 2063 DPRINTF(("CRTC%s_V_SYNC_STRT_WID = %08x\n", crtc ? "2" : "", v)); 2064 PUT32(sc, fpvsyncstrt, v); 2065 DPRINTF(("FP_V%s_SYNC_STRT_WID = %08x\n", crtc ? "2" : "", v)); 2066 2067 radeonfb_program_vclk(sc, mode->dot_clock, crtc); 2068 2069 switch (crtc) { 2070 case 0: 2071 PUT32(sc, RADEON_CRTC_OFFSET, 0); 2072 PUT32(sc, RADEON_CRTC_OFFSET_CNTL, 0); 2073 PUT32(sc, RADEON_CRTC_PITCH, pitch); 2074 CLR32(sc, RADEON_DISP_MERGE_CNTL, RADEON_DISP_RGB_OFFSET_EN); 2075 2076 CLR32(sc, RADEON_CRTC_EXT_CNTL, 2077 RADEON_CRTC_VSYNC_DIS | RADEON_CRTC_HSYNC_DIS | 2078 RADEON_CRTC_DISPLAY_DIS /* | RADEON_CRTC_DISP_REQ_EN_B */); 2079 CLR32(sc, RADEON_CRTC_GEN_CNTL, RADEON_CRTC_DISP_REQ_EN_B); 2080 PRINTREG(RADEON_CRTC_EXT_CNTL); 2081 PRINTREG(RADEON_CRTC_GEN_CNTL); 2082 PRINTREG(RADEON_CLOCK_CNTL_INDEX); 2083 break; 2084 2085 case 1: 2086 PUT32(sc, RADEON_CRTC2_OFFSET, 0); 2087 PUT32(sc, RADEON_CRTC2_OFFSET_CNTL, 0); 2088 PUT32(sc, RADEON_CRTC2_PITCH, pitch); 2089 CLR32(sc, RADEON_DISP2_MERGE_CNTL, RADEON_DISP2_RGB_OFFSET_EN); 2090 CLR32(sc, RADEON_CRTC2_GEN_CNTL, 2091 RADEON_CRTC2_VSYNC_DIS | 2092 RADEON_CRTC2_HSYNC_DIS | 2093 RADEON_CRTC2_DISP_DIS | RADEON_CRTC2_DISP_REQ_EN_B); 2094 PRINTREG(RADEON_CRTC2_GEN_CNTL); 2095 break; 2096 } 2097 } 2098 2099 int 2100 radeonfb_isblank(struct radeonfb_display *dp) 2101 { 2102 uint32_t reg, mask; 2103 2104 if (dp->rd_crtcs[0].rc_number) { 2105 reg = RADEON_CRTC2_GEN_CNTL; 2106 mask = RADEON_CRTC2_DISP_DIS; 2107 } else { 2108 reg = RADEON_CRTC_EXT_CNTL; 2109 mask = RADEON_CRTC_DISPLAY_DIS; 2110 } 2111 return ((GET32(dp->rd_softc, reg) & mask) ? 1 : 0); 2112 } 2113 2114 void 2115 radeonfb_blank(struct radeonfb_display *dp, int blank) 2116 { 2117 struct radeonfb_softc *sc = dp->rd_softc; 2118 uint32_t reg, mask; 2119 uint32_t fpreg, fpval; 2120 int i; 2121 2122 for (i = 0; i < dp->rd_ncrtcs; i++) { 2123 2124 if (dp->rd_crtcs[i].rc_number) { 2125 reg = RADEON_CRTC2_GEN_CNTL; 2126 mask = RADEON_CRTC2_DISP_DIS; 2127 fpreg = RADEON_FP2_GEN_CNTL; 2128 fpval = RADEON_FP2_ON; 2129 } else { 2130 reg = RADEON_CRTC_EXT_CNTL; 2131 mask = RADEON_CRTC_DISPLAY_DIS; 2132 fpreg = RADEON_FP_GEN_CNTL; 2133 fpval = RADEON_FP_FPON; 2134 } 2135 2136 if (blank) { 2137 SET32(sc, reg, mask); 2138 CLR32(sc, fpreg, fpval); 2139 } else { 2140 CLR32(sc, reg, mask); 2141 SET32(sc, fpreg, fpval); 2142 } 2143 } 2144 PRINTREG(RADEON_FP_GEN_CNTL); 2145 PRINTREG(RADEON_FP2_GEN_CNTL); 2146 } 2147 2148 void 2149 radeonfb_init_screen(void *cookie, struct vcons_screen *scr, int existing, 2150 long *defattr) 2151 { 2152 struct radeonfb_display *dp = cookie; 2153 struct rasops_info *ri = &scr->scr_ri; 2154 2155 /* initialize font subsystem */ 2156 wsfont_init(); 2157 2158 DPRINTF(("init screen called, existing %d\n", existing)); 2159 2160 ri->ri_depth = dp->rd_bpp; 2161 ri->ri_width = dp->rd_virtx; 2162 ri->ri_height = dp->rd_virty; 2163 ri->ri_stride = dp->rd_stride; 2164 ri->ri_flg = RI_CENTER; 2165 ri->ri_bits = (void *)dp->rd_fbptr; 2166 2167 #ifdef VCONS_DRAW_INTR 2168 scr->scr_flags |= VCONS_DONT_READ; 2169 #endif 2170 2171 /* XXX: 32 bpp only */ 2172 /* this is rgb in "big-endian order..." */ 2173 ri->ri_rnum = 8; 2174 ri->ri_gnum = 8; 2175 ri->ri_bnum = 8; 2176 ri->ri_rpos = 16; 2177 ri->ri_gpos = 8; 2178 ri->ri_bpos = 0; 2179 2180 if (existing) { 2181 ri->ri_flg |= RI_CLEAR; 2182 2183 /* start a modeswitch now */ 2184 radeonfb_modeswitch(dp); 2185 } 2186 2187 /* 2188 * XXX: font selection should be based on properties, with some 2189 * normal/reasonable default. 2190 */ 2191 ri->ri_caps = WSSCREEN_WSCOLORS | WSSCREEN_REVERSE; 2192 2193 /* initialize and look for an initial font */ 2194 rasops_init(ri, dp->rd_virty/8, dp->rd_virtx/8); 2195 2196 rasops_reconfig(ri, dp->rd_virty / ri->ri_font->fontheight, 2197 dp->rd_virtx / ri->ri_font->fontwidth); 2198 2199 /* enable acceleration */ 2200 dp->rd_putchar = ri->ri_ops.putchar; 2201 ri->ri_ops.copyrows = radeonfb_copyrows; 2202 ri->ri_ops.copycols = radeonfb_copycols; 2203 ri->ri_ops.eraserows = radeonfb_eraserows; 2204 ri->ri_ops.erasecols = radeonfb_erasecols; 2205 ri->ri_ops.allocattr = radeonfb_allocattr; 2206 if (IS_R300(dp->rd_softc)) { 2207 /* 2208 * radeonfb_putchar() doesn't work right on some R3xx 2209 * so we use software drawing here, the wrapper just makes 2210 * sure the engine is idle before scribbling into vram 2211 */ 2212 ri->ri_ops.putchar = radeonfb_putchar_wrapper; 2213 } else { 2214 ri->ri_ops.putchar = radeonfb_putchar; 2215 } 2216 ri->ri_ops.cursor = radeonfb_cursor; 2217 } 2218 2219 void 2220 radeonfb_set_fbloc(struct radeonfb_softc *sc) 2221 { 2222 uint32_t gen, ext, gen2 = 0; 2223 uint32_t agploc, aperbase, apersize, mcfbloc; 2224 2225 gen = GET32(sc, RADEON_CRTC_GEN_CNTL); 2226 ext = GET32(sc, RADEON_CRTC_EXT_CNTL); 2227 agploc = GET32(sc, RADEON_MC_AGP_LOCATION); 2228 aperbase = GET32(sc, RADEON_CONFIG_APER_0_BASE); 2229 apersize = GET32(sc, RADEON_CONFIG_APER_SIZE); 2230 2231 PUT32(sc, RADEON_CRTC_GEN_CNTL, gen | RADEON_CRTC_DISP_REQ_EN_B); 2232 PUT32(sc, RADEON_CRTC_EXT_CNTL, ext | RADEON_CRTC_DISPLAY_DIS); 2233 //PUT32(sc, RADEON_CRTC_GEN_CNTL, gen | RADEON_CRTC_DISPLAY_DIS); 2234 //PUT32(sc, RADEON_CRTC_EXT_CNTL, ext | RADEON_CRTC_DISP_REQ_EN_B); 2235 2236 if (HAS_CRTC2(sc)) { 2237 gen2 = GET32(sc, RADEON_CRTC2_GEN_CNTL); 2238 PUT32(sc, RADEON_CRTC2_GEN_CNTL, 2239 gen2 | RADEON_CRTC2_DISP_REQ_EN_B); 2240 } 2241 2242 delay(100000); 2243 2244 mcfbloc = (aperbase >> 16) | 2245 ((aperbase + (apersize - 1)) & 0xffff0000); 2246 2247 sc->sc_aperbase = (mcfbloc & 0xffff) << 16; 2248 sc->sc_memsz = apersize; 2249 2250 if (((agploc & 0xffff) << 16) != 2251 ((mcfbloc & 0xffff0000U) + 0x10000)) { 2252 agploc = mcfbloc & 0xffff0000U; 2253 agploc |= ((agploc + 0x10000) >> 16); 2254 } 2255 2256 PUT32(sc, RADEON_HOST_PATH_CNTL, 0); 2257 2258 PUT32(sc, RADEON_MC_FB_LOCATION, mcfbloc); 2259 PUT32(sc, RADEON_MC_AGP_LOCATION, agploc); 2260 2261 DPRINTF(("aperbase = %u\n", aperbase)); 2262 PRINTREG(RADEON_MC_FB_LOCATION); 2263 PRINTREG(RADEON_MC_AGP_LOCATION); 2264 2265 PUT32(sc, RADEON_DISPLAY_BASE_ADDR, sc->sc_aperbase); 2266 2267 if (HAS_CRTC2(sc)) 2268 PUT32(sc, RADEON_DISPLAY2_BASE_ADDR, sc->sc_aperbase); 2269 2270 PUT32(sc, RADEON_OV0_BASE_ADDR, sc->sc_aperbase); 2271 2272 #if 0 2273 /* XXX: what is this AGP garbage? :-) */ 2274 PUT32(sc, RADEON_AGP_CNTL, 0x00100000); 2275 #endif 2276 2277 delay(100000); 2278 2279 PUT32(sc, RADEON_CRTC_GEN_CNTL, gen); 2280 PUT32(sc, RADEON_CRTC_EXT_CNTL, ext); 2281 2282 if (HAS_CRTC2(sc)) 2283 PUT32(sc, RADEON_CRTC2_GEN_CNTL, gen2); 2284 } 2285 2286 void 2287 radeonfb_init_misc(struct radeonfb_softc *sc) 2288 { 2289 PUT32(sc, RADEON_BUS_CNTL, 2290 RADEON_BUS_MASTER_DIS | 2291 RADEON_BUS_PREFETCH_MODE_ACT | 2292 RADEON_BUS_PCI_READ_RETRY_EN | 2293 RADEON_BUS_PCI_WRT_RETRY_EN | 2294 (3 << RADEON_BUS_RETRY_WS_SHIFT) | 2295 RADEON_BUS_MSTR_RD_MULT | 2296 RADEON_BUS_MSTR_RD_LINE | 2297 RADEON_BUS_RD_DISCARD_EN | 2298 RADEON_BUS_MSTR_DISCONNECT_EN | 2299 RADEON_BUS_READ_BURST); 2300 2301 PUT32(sc, RADEON_BUS_CNTL1, 0xf0); 2302 /* PUT32(sc, RADEON_SEPROM_CNTL1, 0x09ff0000); */ 2303 PUT32(sc, RADEON_FCP_CNTL, RADEON_FCP0_SRC_GND); 2304 PUT32(sc, RADEON_RBBM_CNTL, 2305 (3 << RADEON_RB_SETTLE_SHIFT) | 2306 (4 << RADEON_ABORTCLKS_HI_SHIFT) | 2307 (4 << RADEON_ABORTCLKS_CP_SHIFT) | 2308 (4 << RADEON_ABORTCLKS_CFIFO_SHIFT)); 2309 2310 /* XXX: figure out what these mean! */ 2311 PUT32(sc, RADEON_AGP_CNTL, 0x00100000); 2312 PUT32(sc, RADEON_HOST_PATH_CNTL, 0); 2313 //PUT32(sc, RADEON_DISP_MISC_CNTL, 0x5bb00400); 2314 2315 PUT32(sc, RADEON_GEN_INT_CNTL, 0); 2316 PUT32(sc, RADEON_GEN_INT_STATUS, GET32(sc, RADEON_GEN_INT_STATUS)); 2317 } 2318 2319 /* 2320 * This loads a linear color map for true color. 2321 */ 2322 void 2323 radeonfb_init_palette(struct radeonfb_softc *sc, int crtc) 2324 { 2325 int i; 2326 uint32_t vclk; 2327 2328 #define DAC_WIDTH ((1 << 10) - 1) 2329 #define CLUT_WIDTH ((1 << 8) - 1) 2330 #define CLUT_COLOR(i) ((i * DAC_WIDTH * 2 / CLUT_WIDTH + 1) / 2) 2331 2332 vclk = GETPLL(sc, RADEON_VCLK_ECP_CNTL); 2333 PUTPLL(sc, RADEON_VCLK_ECP_CNTL, vclk & ~RADEON_PIXCLK_DAC_ALWAYS_ONb); 2334 2335 if (crtc) 2336 SET32(sc, RADEON_DAC_CNTL2, RADEON_DAC2_PALETTE_ACC_CTL); 2337 else 2338 CLR32(sc, RADEON_DAC_CNTL2, RADEON_DAC2_PALETTE_ACC_CTL); 2339 2340 PUT32(sc, RADEON_PALETTE_INDEX, 0); 2341 if (sc->sc_displays[crtc].rd_bpp == 0) 2342 sc->sc_displays[crtc].rd_bpp = RADEONFB_DEFAULT_DEPTH; 2343 2344 if (sc->sc_displays[crtc].rd_bpp == 8) { 2345 /* ANSI palette */ 2346 int j = 0; 2347 2348 for (i = 0; i <= CLUT_WIDTH; ++i) { 2349 PUT32(sc, RADEON_PALETTE_30_DATA, 2350 (rasops_cmap[j] << 22) | 2351 (rasops_cmap[j + 1] << 12) | 2352 (rasops_cmap[j + 2] << 2)); 2353 j += 3; 2354 } 2355 } else { 2356 /* linear ramp */ 2357 for (i = 0; i <= CLUT_WIDTH; ++i) { 2358 PUT32(sc, RADEON_PALETTE_30_DATA, 2359 (CLUT_COLOR(i) << 10) | 2360 (CLUT_COLOR(i) << 20) | 2361 (CLUT_COLOR(i))); 2362 } 2363 } 2364 2365 CLR32(sc, RADEON_DAC_CNTL2, RADEON_DAC2_PALETTE_ACC_CTL); 2366 PRINTREG(RADEON_DAC_CNTL2); 2367 2368 PUTPLL(sc, RADEON_VCLK_ECP_CNTL, vclk); 2369 } 2370 2371 /* 2372 * Bugs in some R300 hardware requires this when accessing CLOCK_CNTL_INDEX. 2373 */ 2374 void 2375 radeonfb_r300cg_workaround(struct radeonfb_softc *sc) 2376 { 2377 uint32_t tmp, save; 2378 2379 save = GET32(sc, RADEON_CLOCK_CNTL_INDEX); 2380 tmp = save & ~(0x3f | RADEON_PLL_WR_EN); 2381 PUT32(sc, RADEON_CLOCK_CNTL_INDEX, tmp); 2382 tmp = GET32(sc, RADEON_CLOCK_CNTL_DATA); 2383 PUT32(sc, RADEON_CLOCK_CNTL_INDEX, save); 2384 } 2385 2386 /* 2387 * Acceleration entry points. 2388 */ 2389 static void 2390 radeonfb_putchar(void *cookie, int row, int col, u_int c, long attr) 2391 { 2392 struct rasops_info *ri = cookie; 2393 struct vcons_screen *scr = ri->ri_hw; 2394 struct radeonfb_display *dp = scr->scr_cookie; 2395 struct radeonfb_softc *sc = dp->rd_softc; 2396 struct wsdisplay_font *font = PICK_FONT(ri, c); 2397 uint32_t w, h; 2398 int xd, yd, offset, i; 2399 uint32_t bg, fg, gmc; 2400 uint32_t reg; 2401 uint8_t *data8; 2402 uint16_t *data16; 2403 void *data; 2404 2405 if (dp->rd_wsmode != WSDISPLAYIO_MODE_EMUL) 2406 return; 2407 2408 if (!CHAR_IN_FONT(c, font)) 2409 return; 2410 2411 w = font->fontwidth; 2412 h = font->fontheight; 2413 2414 bg = ri->ri_devcmap[(attr >> 16) & 0xf]; 2415 fg = ri->ri_devcmap[(attr >> 24) & 0xf]; 2416 2417 xd = ri->ri_xorigin + col * w; 2418 yd = ri->ri_yorigin + row * h; 2419 2420 if (c == 0x20) { 2421 radeonfb_rectfill(dp, xd, yd, w, h, bg); 2422 return; 2423 } 2424 data = (uint8_t *)font->data + (c - font->firstchar) * ri->ri_fontscale; 2425 2426 gmc = dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT; 2427 2428 radeonfb_wait_fifo(sc, 9); 2429 2430 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 2431 RADEON_GMC_BRUSH_NONE | 2432 RADEON_GMC_SRC_DATATYPE_MONO_FG_BG | 2433 RADEON_GMC_DST_CLIPPING | 2434 RADEON_ROP3_S | 2435 RADEON_DP_SRC_SOURCE_HOST_DATA | 2436 RADEON_GMC_CLR_CMP_CNTL_DIS | 2437 RADEON_GMC_WR_MSK_DIS | 2438 gmc); 2439 2440 PUT32(sc, RADEON_SC_LEFT, xd); 2441 PUT32(sc, RADEON_SC_RIGHT, xd + w); 2442 PUT32(sc, RADEON_DP_SRC_FRGD_CLR, fg); 2443 PUT32(sc, RADEON_DP_SRC_BKGD_CLR, bg); 2444 PUT32(sc, RADEON_DP_CNTL, 2445 RADEON_DST_X_LEFT_TO_RIGHT | 2446 RADEON_DST_Y_TOP_TO_BOTTOM); 2447 2448 PUT32(sc, RADEON_SRC_X_Y, 0); 2449 offset = 32 - (font->stride << 3); 2450 PUT32(sc, RADEON_DST_X_Y, ((xd - offset) << 16) | yd); 2451 PUT32(sc, RADEON_DST_WIDTH_HEIGHT, (32 << 16) | h); 2452 2453 radeonfb_wait_fifo(sc, h); 2454 switch (font->stride) { 2455 case 1: { 2456 data8 = data; 2457 for (i = 0; i < h; i++) { 2458 reg = *data8; 2459 bus_space_write_stream_4(sc->sc_regt, 2460 sc->sc_regh, RADEON_HOST_DATA0, reg); 2461 data8++; 2462 } 2463 break; 2464 } 2465 case 2: { 2466 data16 = data; 2467 for (i = 0; i < h; i++) { 2468 reg = *data16; 2469 bus_space_write_stream_4(sc->sc_regt, 2470 sc->sc_regh, RADEON_HOST_DATA0, reg); 2471 data16++; 2472 } 2473 break; 2474 } 2475 } 2476 } 2477 2478 /* 2479 * wrapper for software character drawing 2480 * just sync the engine and call rasops*_putchar() 2481 */ 2482 2483 static void 2484 radeonfb_putchar_wrapper(void *cookie, int row, int col, u_int c, long attr) 2485 { 2486 struct rasops_info *ri = cookie; 2487 struct vcons_screen *scr = ri->ri_hw; 2488 struct radeonfb_display *dp = scr->scr_cookie; 2489 2490 radeonfb_engine_idle(dp->rd_softc); 2491 dp->rd_putchar(ri, row, col, c, attr); 2492 } 2493 2494 static void 2495 radeonfb_eraserows(void *cookie, int row, int nrows, long fillattr) 2496 { 2497 struct rasops_info *ri = cookie; 2498 struct vcons_screen *scr = ri->ri_hw; 2499 struct radeonfb_display *dp = scr->scr_cookie; 2500 uint32_t x, y, w, h, fg, bg, ul; 2501 2502 /* XXX: check for full emulation mode? */ 2503 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 2504 x = ri->ri_xorigin; 2505 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 2506 w = ri->ri_emuwidth; 2507 h = ri->ri_font->fontheight * nrows; 2508 2509 rasops_unpack_attr(fillattr, &fg, &bg, &ul); 2510 radeonfb_rectfill(dp, x, y, w, h, ri->ri_devcmap[bg & 0xf]); 2511 } 2512 } 2513 2514 static void 2515 radeonfb_copyrows(void *cookie, int srcrow, int dstrow, int nrows) 2516 { 2517 struct rasops_info *ri = cookie; 2518 struct vcons_screen *scr = ri->ri_hw; 2519 struct radeonfb_display *dp = scr->scr_cookie; 2520 uint32_t x, ys, yd, w, h; 2521 2522 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 2523 x = ri->ri_xorigin; 2524 ys = ri->ri_yorigin + ri->ri_font->fontheight * srcrow; 2525 yd = ri->ri_yorigin + ri->ri_font->fontheight * dstrow; 2526 w = ri->ri_emuwidth; 2527 h = ri->ri_font->fontheight * nrows; 2528 radeonfb_bitblt(dp, x, ys, x, yd, w, h, 2529 RADEON_ROP3_S, 0xffffffff); 2530 } 2531 } 2532 2533 static void 2534 radeonfb_copycols(void *cookie, int row, int srccol, int dstcol, int ncols) 2535 { 2536 struct rasops_info *ri = cookie; 2537 struct vcons_screen *scr = ri->ri_hw; 2538 struct radeonfb_display *dp = scr->scr_cookie; 2539 uint32_t xs, xd, y, w, h; 2540 2541 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 2542 xs = ri->ri_xorigin + ri->ri_font->fontwidth * srccol; 2543 xd = ri->ri_xorigin + ri->ri_font->fontwidth * dstcol; 2544 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 2545 w = ri->ri_font->fontwidth * ncols; 2546 h = ri->ri_font->fontheight; 2547 radeonfb_bitblt(dp, xs, y, xd, y, w, h, 2548 RADEON_ROP3_S, 0xffffffff); 2549 } 2550 } 2551 2552 static void 2553 radeonfb_erasecols(void *cookie, int row, int startcol, int ncols, 2554 long fillattr) 2555 { 2556 struct rasops_info *ri = cookie; 2557 struct vcons_screen *scr = ri->ri_hw; 2558 struct radeonfb_display *dp = scr->scr_cookie; 2559 uint32_t x, y, w, h, fg, bg, ul; 2560 2561 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 2562 x = ri->ri_xorigin + ri->ri_font->fontwidth * startcol; 2563 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 2564 w = ri->ri_font->fontwidth * ncols; 2565 h = ri->ri_font->fontheight; 2566 2567 rasops_unpack_attr(fillattr, &fg, &bg, &ul); 2568 radeonfb_rectfill(dp, x, y, w, h, ri->ri_devcmap[bg & 0xf]); 2569 } 2570 } 2571 2572 static void 2573 radeonfb_cursor(void *cookie, int on, int row, int col) 2574 { 2575 struct rasops_info *ri = cookie; 2576 struct vcons_screen *scr = ri->ri_hw; 2577 struct radeonfb_display *dp = scr->scr_cookie; 2578 int x, y, wi, he; 2579 2580 wi = ri->ri_font->fontwidth; 2581 he = ri->ri_font->fontheight; 2582 2583 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 2584 x = ri->ri_ccol * wi + ri->ri_xorigin; 2585 y = ri->ri_crow * he + ri->ri_yorigin; 2586 /* first turn off the old cursor */ 2587 if (ri->ri_flg & RI_CURSOR) { 2588 radeonfb_bitblt(dp, x, y, x, y, wi, he, 2589 RADEON_ROP3_Dn, 0xffffffff); 2590 ri->ri_flg &= ~RI_CURSOR; 2591 } 2592 ri->ri_crow = row; 2593 ri->ri_ccol = col; 2594 /* then (possibly) turn on the new one */ 2595 if (on) { 2596 x = ri->ri_ccol * wi + ri->ri_xorigin; 2597 y = ri->ri_crow * he + ri->ri_yorigin; 2598 radeonfb_bitblt(dp, x, y, x, y, wi, he, 2599 RADEON_ROP3_Dn, 0xffffffff); 2600 ri->ri_flg |= RI_CURSOR; 2601 } 2602 } else { 2603 scr->scr_ri.ri_crow = row; 2604 scr->scr_ri.ri_ccol = col; 2605 scr->scr_ri.ri_flg &= ~RI_CURSOR; 2606 } 2607 } 2608 2609 static int 2610 radeonfb_allocattr(void *cookie, int fg, int bg, int flags, long *attrp) 2611 { 2612 if ((fg == 0) && (bg == 0)) { 2613 fg = WS_DEFAULT_FG; 2614 bg = WS_DEFAULT_BG; 2615 } 2616 *attrp = ((fg & 0xf) << 24) | ((bg & 0xf) << 16) | (flags & 0xff) << 8; 2617 return 0; 2618 } 2619 2620 /* 2621 * Underlying acceleration support. 2622 */ 2623 2624 static void 2625 radeonfb_rectfill(struct radeonfb_display *dp, int dstx, int dsty, 2626 int width, int height, uint32_t color) 2627 { 2628 struct radeonfb_softc *sc = dp->rd_softc; 2629 uint32_t gmc; 2630 2631 gmc = dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT; 2632 2633 radeonfb_wait_fifo(sc, 6); 2634 2635 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 2636 RADEON_GMC_BRUSH_SOLID_COLOR | 2637 RADEON_GMC_SRC_DATATYPE_COLOR | 2638 RADEON_GMC_CLR_CMP_CNTL_DIS | 2639 RADEON_ROP3_P | gmc); 2640 2641 PUT32(sc, RADEON_DP_BRUSH_FRGD_CLR, color); 2642 PUT32(sc, RADEON_DP_WRITE_MASK, 0xffffffff); 2643 PUT32(sc, RADEON_DP_CNTL, 2644 RADEON_DST_X_LEFT_TO_RIGHT | 2645 RADEON_DST_Y_TOP_TO_BOTTOM); 2646 PUT32(sc, RADEON_DST_Y_X, (dsty << 16) | dstx); 2647 PUT32(sc, RADEON_DST_WIDTH_HEIGHT, (width << 16) | (height)); 2648 2649 } 2650 2651 static void 2652 radeonfb_bitblt(struct radeonfb_display *dp, int srcx, int srcy, 2653 int dstx, int dsty, int width, int height, int rop, uint32_t mask) 2654 { 2655 struct radeonfb_softc *sc = dp->rd_softc; 2656 uint32_t gmc; 2657 uint32_t dir; 2658 2659 if (dsty < srcy) { 2660 dir = RADEON_DST_Y_TOP_TO_BOTTOM; 2661 } else { 2662 srcy += height - 1; 2663 dsty += height - 1; 2664 dir = 0; 2665 } 2666 if (dstx < srcx) { 2667 dir |= RADEON_DST_X_LEFT_TO_RIGHT; 2668 } else { 2669 srcx += width - 1; 2670 dstx += width - 1; 2671 } 2672 2673 gmc = dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT; 2674 2675 radeonfb_wait_fifo(sc, 6); 2676 2677 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 2678 //RADEON_GMC_SRC_CLIPPING | 2679 RADEON_GMC_BRUSH_SOLID_COLOR | 2680 RADEON_GMC_SRC_DATATYPE_COLOR | 2681 RADEON_GMC_CLR_CMP_CNTL_DIS | 2682 RADEON_DP_SRC_SOURCE_MEMORY | 2683 rop | gmc); 2684 2685 PUT32(sc, RADEON_DP_WRITE_MASK, mask); 2686 PUT32(sc, RADEON_DP_CNTL, dir); 2687 PUT32(sc, RADEON_SRC_Y_X, (srcy << 16) | srcx); 2688 PUT32(sc, RADEON_DST_Y_X, (dsty << 16) | dstx); 2689 PUT32(sc, RADEON_DST_WIDTH_HEIGHT, (width << 16) | (height)); 2690 } 2691 2692 static void 2693 radeonfb_engine_idle(struct radeonfb_softc *sc) 2694 { 2695 2696 radeonfb_wait_fifo(sc, 64); 2697 while ((GET32(sc, RADEON_RBBM_STATUS) & 2698 RADEON_RBBM_ACTIVE) != 0); 2699 radeonfb_engine_flush(sc); 2700 } 2701 2702 static void 2703 radeonfb_wait_fifo(struct radeonfb_softc *sc, int n) 2704 { 2705 int i; 2706 2707 for (i = RADEON_TIMEOUT; i; i--) { 2708 if ((GET32(sc, RADEON_RBBM_STATUS) & 2709 RADEON_RBBM_FIFOCNT_MASK) >= n) 2710 return; 2711 } 2712 #ifdef DIAGNOSTIC 2713 if (!i) 2714 printf("%s: timed out waiting for fifo (%x)\n", 2715 XNAME(sc), GET32(sc, RADEON_RBBM_STATUS)); 2716 #endif 2717 } 2718 2719 static void 2720 radeonfb_engine_flush(struct radeonfb_softc *sc) 2721 { 2722 int i = 0; 2723 2724 if (IS_R300(sc)) { 2725 SET32(sc, R300_DSTCACHE_CTLSTAT, R300_RB2D_DC_FLUSH_ALL); 2726 while (GET32(sc, R300_DSTCACHE_CTLSTAT) & R300_RB2D_DC_BUSY) { 2727 i++; 2728 } 2729 } else { 2730 SET32(sc, RADEON_RB2D_DSTCACHE_CTLSTAT, 2731 RADEON_RB2D_DC_FLUSH_ALL); 2732 while (GET32(sc, RADEON_RB2D_DSTCACHE_CTLSTAT) & 2733 RADEON_RB2D_DC_BUSY) { 2734 i++; 2735 } 2736 } 2737 #ifdef DIAGNOSTIC 2738 if (i > RADEON_TIMEOUT) 2739 printf("%s: engine flush timed out!\n", XNAME(sc)); 2740 #endif 2741 } 2742 2743 static inline void 2744 radeonfb_unclip(struct radeonfb_softc *sc) 2745 { 2746 2747 radeonfb_wait_fifo(sc, 2); 2748 PUT32(sc, RADEON_SC_TOP_LEFT, 0); 2749 PUT32(sc, RADEON_SC_BOTTOM_RIGHT, 0x1fff1fff); 2750 } 2751 2752 static void 2753 radeonfb_engine_init(struct radeonfb_display *dp) 2754 { 2755 struct radeonfb_softc *sc = dp->rd_softc; 2756 uint32_t pitch; 2757 volatile uint32_t junk; 2758 2759 /* no 3D */ 2760 PUT32(sc, RADEON_RB3D_CNTL, 0); 2761 2762 radeonfb_engine_reset(sc); 2763 pitch = ((dp->rd_virtx * (dp->rd_bpp / 8) + 0x3f)) >> 6; 2764 //pitch = ((sc->sc_maxx * (sc->sc_maxbpp / 8) + 0x3f)) >> 6; 2765 2766 radeonfb_wait_fifo(sc, 1); 2767 if (!IS_R300(sc)) 2768 PUT32(sc, RADEON_RB2D_DSTCACHE_MODE, 0); 2769 2770 radeonfb_wait_fifo(sc, 3); 2771 PUT32(sc, RADEON_DEFAULT_PITCH_OFFSET, 2772 (pitch << 22) | (sc->sc_aperbase >> 10)); 2773 2774 2775 PUT32(sc, RADEON_DST_PITCH_OFFSET, 2776 (pitch << 22) | (sc->sc_aperbase >> 10)); 2777 PUT32(sc, RADEON_SRC_PITCH_OFFSET, 2778 (pitch << 22) | (sc->sc_aperbase >> 10)); 2779 2780 radeonfb_wait_fifo(sc, 1); 2781 #if _BYTE_ORDER == _BIG_ENDIAN 2782 SET32(sc, RADEON_DP_DATATYPE, RADEON_HOST_BIG_ENDIAN_EN); 2783 #else 2784 CLR32(sc, RADEON_DP_DATATYPE, RADEON_HOST_BIG_ENDIAN_EN); 2785 #endif 2786 junk = GET32(sc, RADEON_DP_DATATYPE); 2787 2788 /* default scissors -- no clipping */ 2789 radeonfb_wait_fifo(sc, 1); 2790 PUT32(sc, RADEON_DEFAULT_SC_BOTTOM_RIGHT, 2791 RADEON_DEFAULT_SC_RIGHT_MAX | RADEON_DEFAULT_SC_BOTTOM_MAX); 2792 2793 radeonfb_wait_fifo(sc, 1); 2794 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 2795 (dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT) | 2796 RADEON_GMC_CLR_CMP_CNTL_DIS | 2797 RADEON_GMC_BRUSH_SOLID_COLOR | 2798 RADEON_GMC_SRC_DATATYPE_COLOR); 2799 2800 radeonfb_wait_fifo(sc, 10); 2801 PUT32(sc, RADEON_DST_LINE_START, 0); 2802 PUT32(sc, RADEON_DST_LINE_END, 0); 2803 PUT32(sc, RADEON_DP_BRUSH_FRGD_CLR, 0xffffffff); 2804 PUT32(sc, RADEON_DP_BRUSH_BKGD_CLR, 0); 2805 PUT32(sc, RADEON_DP_SRC_FRGD_CLR, 0xffffffff); 2806 PUT32(sc, RADEON_DP_SRC_BKGD_CLR, 0); 2807 PUT32(sc, RADEON_DP_WRITE_MASK, 0xffffffff); 2808 PUT32(sc, RADEON_SC_TOP_LEFT, 0); 2809 PUT32(sc, RADEON_SC_BOTTOM_RIGHT, 0x1fff1fff); 2810 PUT32(sc, RADEON_AUX_SC_CNTL, 0); 2811 radeonfb_engine_idle(sc); 2812 } 2813 2814 static void 2815 radeonfb_engine_reset(struct radeonfb_softc *sc) 2816 { 2817 uint32_t hpc, rbbm, mclkcntl, clkindex; 2818 2819 radeonfb_engine_flush(sc); 2820 2821 clkindex = GET32(sc, RADEON_CLOCK_CNTL_INDEX); 2822 if (HAS_R300CG(sc)) 2823 radeonfb_r300cg_workaround(sc); 2824 mclkcntl = GETPLL(sc, RADEON_MCLK_CNTL); 2825 2826 /* 2827 * According to comments in XFree code, resetting the HDP via 2828 * the RBBM_SOFT_RESET can cause bad behavior on some systems. 2829 * So we use HOST_PATH_CNTL instead. 2830 */ 2831 2832 hpc = GET32(sc, RADEON_HOST_PATH_CNTL); 2833 rbbm = GET32(sc, RADEON_RBBM_SOFT_RESET); 2834 if (IS_R300(sc)) { 2835 PUT32(sc, RADEON_RBBM_SOFT_RESET, rbbm | 2836 RADEON_SOFT_RESET_CP | 2837 RADEON_SOFT_RESET_HI | 2838 RADEON_SOFT_RESET_E2); 2839 GET32(sc, RADEON_RBBM_SOFT_RESET); 2840 PUT32(sc, RADEON_RBBM_SOFT_RESET, 0); 2841 /* 2842 * XXX: this bit is not defined in any ATI docs I have, 2843 * nor in the XFree code, but XFree does it. Why? 2844 */ 2845 SET32(sc, RADEON_RB2D_DSTCACHE_MODE, (1<<17)); 2846 } else { 2847 PUT32(sc, RADEON_RBBM_SOFT_RESET, rbbm | 2848 RADEON_SOFT_RESET_CP | 2849 RADEON_SOFT_RESET_SE | 2850 RADEON_SOFT_RESET_RE | 2851 RADEON_SOFT_RESET_PP | 2852 RADEON_SOFT_RESET_E2 | 2853 RADEON_SOFT_RESET_RB); 2854 GET32(sc, RADEON_RBBM_SOFT_RESET); 2855 PUT32(sc, RADEON_RBBM_SOFT_RESET, rbbm & 2856 ~(RADEON_SOFT_RESET_CP | 2857 RADEON_SOFT_RESET_SE | 2858 RADEON_SOFT_RESET_RE | 2859 RADEON_SOFT_RESET_PP | 2860 RADEON_SOFT_RESET_E2 | 2861 RADEON_SOFT_RESET_RB)); 2862 GET32(sc, RADEON_RBBM_SOFT_RESET); 2863 } 2864 2865 PUT32(sc, RADEON_HOST_PATH_CNTL, hpc | RADEON_HDP_SOFT_RESET); 2866 GET32(sc, RADEON_HOST_PATH_CNTL); 2867 PUT32(sc, RADEON_HOST_PATH_CNTL, hpc); 2868 2869 if (IS_R300(sc)) 2870 PUT32(sc, RADEON_RBBM_SOFT_RESET, rbbm); 2871 2872 PUT32(sc, RADEON_CLOCK_CNTL_INDEX, clkindex); 2873 PUTPLL(sc, RADEON_MCLK_CNTL, mclkcntl); 2874 2875 if (HAS_R300CG(sc)) 2876 radeonfb_r300cg_workaround(sc); 2877 } 2878 2879 static int 2880 radeonfb_set_curpos(struct radeonfb_display *dp, struct wsdisplay_curpos *pos) 2881 { 2882 int x, y; 2883 2884 x = pos->x; 2885 y = pos->y; 2886 2887 /* 2888 * This doesn't let a cursor move off the screen. I'm not 2889 * sure if this will have negative effects for e.g. Xinerama. 2890 * I'd guess Xinerama handles it by changing the cursor shape, 2891 * but that needs verification. 2892 */ 2893 if (x >= dp->rd_virtx) 2894 x = dp->rd_virtx - 1; 2895 if (x < 0) 2896 x = 0; 2897 if (y >= dp->rd_virty) 2898 y = dp->rd_virty - 1; 2899 if (y < 0) 2900 y = 0; 2901 2902 dp->rd_cursor.rc_pos.x = x; 2903 dp->rd_cursor.rc_pos.y = y; 2904 2905 radeonfb_cursor_position(dp); 2906 return 0; 2907 } 2908 2909 static int 2910 radeonfb_set_cursor(struct radeonfb_display *dp, struct wsdisplay_cursor *wc) 2911 { 2912 unsigned flags; 2913 2914 uint8_t r[2], g[2], b[2]; 2915 unsigned index, count; 2916 int i, err; 2917 int pitch, size; 2918 struct radeonfb_cursor nc; 2919 2920 flags = wc->which; 2921 2922 /* copy old values */ 2923 nc = dp->rd_cursor; 2924 2925 if (flags & WSDISPLAY_CURSOR_DOCMAP) { 2926 index = wc->cmap.index; 2927 count = wc->cmap.count; 2928 2929 if (index >= 2 || (index + count) > 2) 2930 return EINVAL; 2931 2932 err = copyin(wc->cmap.red, &r[index], count); 2933 if (err) 2934 return err; 2935 err = copyin(wc->cmap.green, &g[index], count); 2936 if (err) 2937 return err; 2938 err = copyin(wc->cmap.blue, &b[index], count); 2939 if (err) 2940 return err; 2941 2942 for (i = index; i < index + count; i++) { 2943 nc.rc_cmap[i] = 2944 (r[i] << 16) + (g[i] << 8) + (b[i] << 0); 2945 } 2946 } 2947 2948 if (flags & WSDISPLAY_CURSOR_DOSHAPE) { 2949 if ((wc->size.x > RADEON_CURSORMAXX) || 2950 (wc->size.y > RADEON_CURSORMAXY)) 2951 return EINVAL; 2952 2953 /* figure bytes per line */ 2954 pitch = (wc->size.x + 7) / 8; 2955 size = pitch * wc->size.y; 2956 2957 /* clear the old cursor and mask */ 2958 memset(nc.rc_image, 0, 512); 2959 memset(nc.rc_mask, 0, 512); 2960 2961 nc.rc_size = wc->size; 2962 2963 if ((err = copyin(wc->image, nc.rc_image, size)) != 0) 2964 return err; 2965 2966 if ((err = copyin(wc->mask, nc.rc_mask, size)) != 0) 2967 return err; 2968 } 2969 2970 if (flags & WSDISPLAY_CURSOR_DOHOT) { 2971 nc.rc_hot = wc->hot; 2972 if (nc.rc_hot.x >= nc.rc_size.x) 2973 nc.rc_hot.x = nc.rc_size.x - 1; 2974 if (nc.rc_hot.y >= nc.rc_size.y) 2975 nc.rc_hot.y = nc.rc_size.y - 1; 2976 } 2977 2978 if (flags & WSDISPLAY_CURSOR_DOPOS) { 2979 nc.rc_pos = wc->pos; 2980 if (nc.rc_pos.x >= dp->rd_virtx) 2981 nc.rc_pos.x = dp->rd_virtx - 1; 2982 #if 0 2983 if (nc.rc_pos.x < 0) 2984 nc.rc_pos.x = 0; 2985 #endif 2986 if (nc.rc_pos.y >= dp->rd_virty) 2987 nc.rc_pos.y = dp->rd_virty - 1; 2988 #if 0 2989 if (nc.rc_pos.y < 0) 2990 nc.rc_pos.y = 0; 2991 #endif 2992 } 2993 if (flags & WSDISPLAY_CURSOR_DOCUR) { 2994 nc.rc_visible = wc->enable; 2995 } 2996 2997 dp->rd_cursor = nc; 2998 radeonfb_cursor_update(dp, wc->which); 2999 3000 return 0; 3001 } 3002 3003 /* 3004 * Change the cursor shape. Call this with the cursor locked to avoid 3005 * flickering/tearing. 3006 */ 3007 static void 3008 radeonfb_cursor_shape(struct radeonfb_display *dp) 3009 { 3010 uint8_t and[512], xor[512]; 3011 int i, j, src, dst, pitch; 3012 const uint8_t *msk = dp->rd_cursor.rc_mask; 3013 const uint8_t *img = dp->rd_cursor.rc_image; 3014 3015 /* 3016 * Radeon cursor data interleaves one line of AND data followed 3017 * by a line of XOR data. (Each line corresponds to a whole hardware 3018 * pitch - i.e. 64 pixels or 8 bytes.) 3019 * 3020 * The cursor is displayed using the following table: 3021 * 3022 * AND XOR Result 3023 * ---------------------- 3024 * 0 0 Cursor color 0 3025 * 0 1 Cursor color 1 3026 * 1 0 Transparent 3027 * 1 1 Complement of background 3028 * 3029 * Our masks are therefore different from what we were passed. 3030 * Passed in, I'm assuming the data represents either color 0 or 1, 3031 * and a mask, so the passed in table looks like: 3032 * 3033 * IMG Mask Result 3034 * ----------------------- 3035 * 0 0 Transparent 3036 * 0 1 Cursor color 0 3037 * 1 0 Transparent 3038 * 1 1 Cursor color 1 3039 * 3040 * IF mask bit == 1, AND = 0, XOR = color. 3041 * IF mask bit == 0, AND = 1, XOR = 0. 3042 * 3043 * hence: AND = ~(mask); XOR = color & ~(mask); 3044 */ 3045 3046 pitch = ((dp->rd_cursor.rc_size.x + 7) / 8); 3047 3048 /* start by assuming all bits are transparent */ 3049 memset(and, 0xff, 512); 3050 memset(xor, 0x00, 512); 3051 3052 src = 0; 3053 dst = 0; 3054 for (i = 0; i < 64; i++) { 3055 for (j = 0; j < 64; j += 8) { 3056 if ((i < dp->rd_cursor.rc_size.y) && 3057 (j < dp->rd_cursor.rc_size.x)) { 3058 3059 /* take care to leave odd bits alone */ 3060 and[dst] &= ~(msk[src]); 3061 xor[dst] = img[src] & msk[src]; 3062 src++; 3063 } 3064 dst++; 3065 } 3066 } 3067 3068 /* copy the image into place */ 3069 for (i = 0; i < 64; i++) { 3070 memcpy((uint8_t *)dp->rd_curptr + (i * 16), 3071 &and[i * 8], 8); 3072 memcpy((uint8_t *)dp->rd_curptr + (i * 16) + 8, 3073 &xor[i * 8], 8); 3074 } 3075 } 3076 3077 static void 3078 radeonfb_cursor_position(struct radeonfb_display *dp) 3079 { 3080 struct radeonfb_softc *sc = dp->rd_softc; 3081 uint32_t offset, hvoff, hvpos; /* registers */ 3082 uint32_t coff; /* cursor offset */ 3083 int i, x, y, xoff, yoff, crtcoff; 3084 3085 /* 3086 * XXX: this also needs to handle pan/scan 3087 */ 3088 for (i = 0; i < dp->rd_ncrtcs; i++) { 3089 3090 struct radeonfb_crtc *rcp = &dp->rd_crtcs[i]; 3091 3092 if (rcp->rc_number) { 3093 offset = RADEON_CUR2_OFFSET; 3094 hvoff = RADEON_CUR2_HORZ_VERT_OFF; 3095 hvpos = RADEON_CUR2_HORZ_VERT_POSN; 3096 crtcoff = RADEON_CRTC2_OFFSET; 3097 } else { 3098 offset = RADEON_CUR_OFFSET; 3099 hvoff = RADEON_CUR_HORZ_VERT_OFF; 3100 hvpos = RADEON_CUR_HORZ_VERT_POSN; 3101 crtcoff = RADEON_CRTC_OFFSET; 3102 } 3103 3104 x = dp->rd_cursor.rc_pos.x; 3105 y = dp->rd_cursor.rc_pos.y; 3106 3107 while (y < rcp->rc_yoffset) { 3108 rcp->rc_yoffset -= RADEON_PANINCREMENT; 3109 } 3110 while (y >= (rcp->rc_yoffset + rcp->rc_videomode.vdisplay)) { 3111 rcp->rc_yoffset += RADEON_PANINCREMENT; 3112 } 3113 while (x < rcp->rc_xoffset) { 3114 rcp->rc_xoffset -= RADEON_PANINCREMENT; 3115 } 3116 while (x >= (rcp->rc_xoffset + rcp->rc_videomode.hdisplay)) { 3117 rcp->rc_xoffset += RADEON_PANINCREMENT; 3118 } 3119 3120 /* adjust for the cursor's hotspot */ 3121 x -= dp->rd_cursor.rc_hot.x; 3122 y -= dp->rd_cursor.rc_hot.y; 3123 xoff = yoff = 0; 3124 3125 if (x >= dp->rd_virtx) 3126 x = dp->rd_virtx - 1; 3127 if (y >= dp->rd_virty) 3128 y = dp->rd_virty - 1; 3129 3130 /* now adjust cursor so it is relative to viewport */ 3131 x -= rcp->rc_xoffset; 3132 y -= rcp->rc_yoffset; 3133 3134 /* 3135 * no need to check for fall off, because we should 3136 * never move off the screen entirely! 3137 */ 3138 coff = 0; 3139 if (x < 0) { 3140 xoff = -x; 3141 x = 0; 3142 } 3143 if (y < 0) { 3144 yoff = -y; 3145 y = 0; 3146 coff = (yoff * 2) * 8; 3147 } 3148 3149 /* pan the display */ 3150 PUT32(sc, crtcoff, (rcp->rc_yoffset * dp->rd_stride) + 3151 rcp->rc_xoffset); 3152 3153 PUT32(sc, offset, (dp->rd_curoff + coff) | RADEON_CUR_LOCK); 3154 PUT32(sc, hvoff, (xoff << 16) | (yoff) | RADEON_CUR_LOCK); 3155 /* NB: this unlocks the cursor */ 3156 PUT32(sc, hvpos, (x << 16) | y); 3157 } 3158 } 3159 3160 static void 3161 radeonfb_cursor_visible(struct radeonfb_display *dp) 3162 { 3163 int i; 3164 uint32_t gencntl, bit; 3165 3166 for (i = 0; i < dp->rd_ncrtcs; i++) { 3167 if (dp->rd_crtcs[i].rc_number) { 3168 gencntl = RADEON_CRTC2_GEN_CNTL; 3169 bit = RADEON_CRTC2_CUR_EN; 3170 } else { 3171 gencntl = RADEON_CRTC_GEN_CNTL; 3172 bit = RADEON_CRTC_CUR_EN; 3173 } 3174 3175 if (dp->rd_cursor.rc_visible) 3176 SET32(dp->rd_softc, gencntl, bit); 3177 else 3178 CLR32(dp->rd_softc, gencntl, bit); 3179 } 3180 } 3181 3182 static void 3183 radeonfb_cursor_cmap(struct radeonfb_display *dp) 3184 { 3185 int i; 3186 uint32_t c0reg, c1reg; 3187 struct radeonfb_softc *sc = dp->rd_softc; 3188 3189 for (i = 0; i < dp->rd_ncrtcs; i++) { 3190 if (dp->rd_crtcs[i].rc_number) { 3191 c0reg = RADEON_CUR2_CLR0; 3192 c1reg = RADEON_CUR2_CLR1; 3193 } else { 3194 c0reg = RADEON_CUR_CLR0; 3195 c1reg = RADEON_CUR_CLR1; 3196 } 3197 3198 PUT32(sc, c0reg, dp->rd_cursor.rc_cmap[0]); 3199 PUT32(sc, c1reg, dp->rd_cursor.rc_cmap[1]); 3200 } 3201 } 3202 3203 static void 3204 radeonfb_cursor_update(struct radeonfb_display *dp, unsigned which) 3205 { 3206 struct radeonfb_softc *sc; 3207 int i; 3208 3209 sc = dp->rd_softc; 3210 for (i = 0; i < dp->rd_ncrtcs; i++) { 3211 if (dp->rd_crtcs[i].rc_number) { 3212 SET32(sc, RADEON_CUR2_OFFSET, RADEON_CUR_LOCK); 3213 } else { 3214 SET32(sc, RADEON_CUR_OFFSET,RADEON_CUR_LOCK); 3215 } 3216 } 3217 3218 if (which & WSDISPLAY_CURSOR_DOCMAP) 3219 radeonfb_cursor_cmap(dp); 3220 3221 if (which & WSDISPLAY_CURSOR_DOSHAPE) 3222 radeonfb_cursor_shape(dp); 3223 3224 if (which & WSDISPLAY_CURSOR_DOCUR) 3225 radeonfb_cursor_visible(dp); 3226 3227 /* this one is unconditional, because it updates other stuff */ 3228 radeonfb_cursor_position(dp); 3229 } 3230 3231 static struct videomode * 3232 radeonfb_best_refresh(struct videomode *m1, struct videomode *m2) 3233 { 3234 int r1, r2; 3235 3236 /* otherwise pick the higher refresh rate */ 3237 r1 = DIVIDE(DIVIDE(m1->dot_clock, m1->htotal), m1->vtotal); 3238 r2 = DIVIDE(DIVIDE(m2->dot_clock, m2->htotal), m2->vtotal); 3239 3240 return (r1 < r2 ? m2 : m1); 3241 } 3242 3243 static const struct videomode * 3244 radeonfb_port_mode(struct radeonfb_softc *sc, struct radeonfb_port *rp, 3245 int x, int y) 3246 { 3247 struct edid_info *ep = &rp->rp_edid; 3248 struct videomode *vmp = NULL; 3249 int i; 3250 3251 if (!rp->rp_edid_valid) { 3252 /* fallback to safe mode */ 3253 return radeonfb_modelookup(sc->sc_defaultmode); 3254 } 3255 3256 /* always choose the preferred mode first! */ 3257 if (ep->edid_preferred_mode) { 3258 3259 /* XXX: add auto-stretching support for native mode */ 3260 3261 /* this may want panning to occur, btw */ 3262 if ((ep->edid_preferred_mode->hdisplay <= x) && 3263 (ep->edid_preferred_mode->vdisplay <= y)) 3264 return ep->edid_preferred_mode; 3265 } 3266 3267 for (i = 0; i < ep->edid_nmodes; i++) { 3268 /* 3269 * We elect to pick a resolution that is too large for 3270 * the monitor than one that is too small. This means 3271 * that we will prefer to pan rather than to try to 3272 * center a smaller display on a larger screen. In 3273 * practice, this shouldn't matter because if a 3274 * monitor can support a larger resolution, it can 3275 * probably also support the smaller. A specific 3276 * exception is fixed format panels, but hopefully 3277 * they are properly dealt with by the "autostretch" 3278 * logic above. 3279 */ 3280 if ((ep->edid_modes[i].hdisplay > x) || 3281 (ep->edid_modes[i].vdisplay > y)) { 3282 continue; 3283 } 3284 3285 /* 3286 * at this point, the display mode is no larger than 3287 * what we've requested. 3288 */ 3289 if (vmp == NULL) 3290 vmp = &ep->edid_modes[i]; 3291 3292 /* eliminate smaller modes */ 3293 if ((vmp->hdisplay >= ep->edid_modes[i].hdisplay) || 3294 (vmp->vdisplay >= ep->edid_modes[i].vdisplay)) 3295 continue; 3296 3297 if ((vmp->hdisplay < ep->edid_modes[i].hdisplay) || 3298 (vmp->vdisplay < ep->edid_modes[i].vdisplay)) { 3299 vmp = &ep->edid_modes[i]; 3300 continue; 3301 } 3302 3303 KASSERT(vmp->hdisplay == ep->edid_modes[i].hdisplay); 3304 KASSERT(vmp->vdisplay == ep->edid_modes[i].vdisplay); 3305 3306 vmp = radeonfb_best_refresh(vmp, &ep->edid_modes[i]); 3307 } 3308 3309 return (vmp ? vmp : radeonfb_modelookup(sc->sc_defaultmode)); 3310 } 3311 3312 static int 3313 radeonfb_hasres(struct videomode *list, int nlist, int x, int y) 3314 { 3315 int i; 3316 3317 for (i = 0; i < nlist; i++) { 3318 if ((x == list[i].hdisplay) && 3319 (y == list[i].vdisplay)) { 3320 return 1; 3321 } 3322 } 3323 return 0; 3324 } 3325 3326 static void 3327 radeonfb_pickres(struct radeonfb_display *dp, uint16_t *x, uint16_t *y, 3328 int pan) 3329 { 3330 struct radeonfb_port *rp; 3331 struct edid_info *ep; 3332 int i, j; 3333 3334 *x = 0; 3335 *y = 0; 3336 3337 if (pan) { 3338 for (i = 0; i < dp->rd_ncrtcs; i++) { 3339 rp = dp->rd_crtcs[i].rc_port; 3340 ep = &rp->rp_edid; 3341 if (!rp->rp_edid_valid) { 3342 /* monitor not present */ 3343 continue; 3344 } 3345 3346 /* 3347 * For now we are ignoring "conflict" that 3348 * could occur when mixing some modes like 3349 * 1280x1024 and 1400x800. It isn't clear 3350 * which is better, so the first one wins. 3351 */ 3352 for (j = 0; j < ep->edid_nmodes; j++) { 3353 /* 3354 * ignore resolutions that are too big for 3355 * the radeon 3356 */ 3357 if (ep->edid_modes[j].hdisplay > 3358 dp->rd_softc->sc_maxx) 3359 continue; 3360 if (ep->edid_modes[j].vdisplay > 3361 dp->rd_softc->sc_maxy) 3362 continue; 3363 3364 /* 3365 * pick largest resolution, the 3366 * smaller monitor will pan 3367 */ 3368 if ((ep->edid_modes[j].hdisplay >= *x) && 3369 (ep->edid_modes[j].vdisplay >= *y)) { 3370 *x = ep->edid_modes[j].hdisplay; 3371 *y = ep->edid_modes[j].vdisplay; 3372 } 3373 } 3374 } 3375 3376 } else { 3377 struct videomode modes[64]; 3378 int nmodes = 0; 3379 int valid = 0; 3380 3381 for (i = 0; i < dp->rd_ncrtcs; i++) { 3382 /* 3383 * pick the largest resolution in common. 3384 */ 3385 rp = dp->rd_crtcs[i].rc_port; 3386 ep = &rp->rp_edid; 3387 3388 if (!rp->rp_edid_valid) 3389 continue; 3390 3391 if (!valid) { 3392 /* 3393 * Pick the preferred mode for this port 3394 * if available. 3395 */ 3396 if (ep->edid_preferred_mode) { 3397 struct videomode *vmp = 3398 ep->edid_preferred_mode; 3399 3400 if ((vmp->hdisplay <= 3401 dp->rd_softc->sc_maxx) && 3402 (vmp->vdisplay <= 3403 dp->rd_softc->sc_maxy)) 3404 modes[nmodes++] = *vmp; 3405 } else { 3406 3407 /* initialize starting list */ 3408 for (j = 0; j < ep->edid_nmodes; j++) { 3409 /* 3410 * ignore resolutions that are 3411 * too big for the radeon 3412 */ 3413 if (ep->edid_modes[j].hdisplay > 3414 dp->rd_softc->sc_maxx) 3415 continue; 3416 if (ep->edid_modes[j].vdisplay > 3417 dp->rd_softc->sc_maxy) 3418 continue; 3419 3420 modes[nmodes] = 3421 ep->edid_modes[j]; 3422 nmodes++; 3423 } 3424 } 3425 valid = 1; 3426 } else { 3427 /* merge into preexisting list */ 3428 for (j = 0; j < nmodes; j++) { 3429 if (!radeonfb_hasres(ep->edid_modes, 3430 ep->edid_nmodes, 3431 modes[j].hdisplay, 3432 modes[j].vdisplay)) { 3433 modes[j] = modes[nmodes]; 3434 j--; 3435 nmodes--; 3436 } 3437 } 3438 } 3439 } 3440 3441 /* now we have to pick from the merged list */ 3442 for (i = 0; i < nmodes; i++) { 3443 if ((modes[i].hdisplay >= *x) && 3444 (modes[i].vdisplay >= *y)) { 3445 *x = modes[i].hdisplay; 3446 *y = modes[i].vdisplay; 3447 } 3448 } 3449 } 3450 3451 if ((*x == 0) || (*y == 0)) { 3452 /* fallback to safe mode */ 3453 *x = 640; 3454 *y = 480; 3455 } 3456 } 3457 3458 /* 3459 * backlight levels are linear on: 3460 * - RV200, RV250, RV280, RV350 3461 * - but NOT on PowerBook4,3 6,3 6,5 3462 * according to Linux' radeonfb 3463 */ 3464 3465 /* Get the current backlight level for the display. */ 3466 3467 static int 3468 radeonfb_get_backlight(struct radeonfb_display *dp) 3469 { 3470 int s; 3471 uint32_t level; 3472 3473 s = spltty(); 3474 3475 level = radeonfb_get32(dp->rd_softc, RADEON_LVDS_GEN_CNTL); 3476 level &= RADEON_LVDS_BL_MOD_LEV_MASK; 3477 level >>= RADEON_LVDS_BL_MOD_LEV_SHIFT; 3478 3479 /* 3480 * On some chips, we should negate the backlight level. 3481 * XXX Find out on which chips. 3482 */ 3483 if (dp->rd_softc->sc_flags & RFB_INV_BLIGHT) 3484 level = RADEONFB_BACKLIGHT_MAX - level; 3485 3486 splx(s); 3487 3488 return level; 3489 } 3490 3491 /* Set the backlight to the given level for the display. */ 3492 3493 static int 3494 radeonfb_set_backlight(struct radeonfb_display *dp, int level) 3495 { 3496 struct radeonfb_softc *sc; 3497 int rlevel, s; 3498 uint32_t lvds; 3499 3500 s = spltty(); 3501 3502 if (level < 0) 3503 level = 0; 3504 else if (level >= RADEONFB_BACKLIGHT_MAX) 3505 level = RADEONFB_BACKLIGHT_MAX; 3506 3507 sc = dp->rd_softc; 3508 3509 /* On some chips, we should negate the backlight level. */ 3510 if (dp->rd_softc->sc_flags & RFB_INV_BLIGHT) { 3511 rlevel = RADEONFB_BACKLIGHT_MAX - level; 3512 } else 3513 rlevel = level; 3514 3515 callout_stop(&dp->rd_bl_lvds_co); 3516 radeonfb_engine_idle(sc); 3517 3518 /* 3519 * Turn off the display if the backlight is set to 0, since the 3520 * display is useless without backlight anyway. 3521 */ 3522 if (level == 0) 3523 radeonfb_blank(dp, 1); 3524 else if (radeonfb_get_backlight(dp) == 0) 3525 radeonfb_blank(dp, 0); 3526 3527 lvds = radeonfb_get32(sc, RADEON_LVDS_GEN_CNTL); 3528 lvds &= ~RADEON_LVDS_DISPLAY_DIS; 3529 if (!(lvds & RADEON_LVDS_BLON) || !(lvds & RADEON_LVDS_ON)) { 3530 lvds |= dp->rd_bl_lvds_val & RADEON_LVDS_DIGON; 3531 lvds |= RADEON_LVDS_BLON | RADEON_LVDS_EN; 3532 radeonfb_put32(sc, RADEON_LVDS_GEN_CNTL, lvds); 3533 lvds &= ~RADEON_LVDS_BL_MOD_LEV_MASK; 3534 lvds |= rlevel << RADEON_LVDS_BL_MOD_LEV_SHIFT; 3535 lvds |= RADEON_LVDS_ON; 3536 lvds |= dp->rd_bl_lvds_val & RADEON_LVDS_BL_MOD_EN; 3537 } else { 3538 lvds &= ~RADEON_LVDS_BL_MOD_LEV_MASK; 3539 lvds |= rlevel << RADEON_LVDS_BL_MOD_LEV_SHIFT; 3540 radeonfb_put32(sc, RADEON_LVDS_GEN_CNTL, lvds); 3541 } 3542 3543 dp->rd_bl_lvds_val &= ~RADEON_LVDS_STATE_MASK; 3544 dp->rd_bl_lvds_val |= lvds & RADEON_LVDS_STATE_MASK; 3545 /* XXX What is the correct delay? */ 3546 callout_schedule(&dp->rd_bl_lvds_co, 200 * hz); 3547 3548 splx(s); 3549 3550 return 0; 3551 } 3552 3553 /* 3554 * Callout function for delayed operations on the LVDS_GEN_CNTL register. 3555 * Set the delayed bits in the register, and clear the stored delayed 3556 * value. 3557 */ 3558 3559 static void radeonfb_lvds_callout(void *arg) 3560 { 3561 struct radeonfb_display *dp = arg; 3562 int s; 3563 3564 s = splhigh(); 3565 3566 radeonfb_mask32(dp->rd_softc, RADEON_LVDS_GEN_CNTL, ~0, 3567 dp->rd_bl_lvds_val); 3568 dp->rd_bl_lvds_val = 0; 3569 3570 splx(s); 3571 } 3572 3573 static void 3574 radeonfb_brightness_up(device_t dev) 3575 { 3576 struct radeonfb_softc *sc = device_private(dev); 3577 int level; 3578 3579 /* we assume the main display is the first one - need a better way */ 3580 if (sc->sc_ndisplays < 1) return; 3581 level = radeonfb_get_backlight(&sc->sc_displays[0]); 3582 level = min(RADEONFB_BACKLIGHT_MAX, level + 5); 3583 radeonfb_set_backlight(&sc->sc_displays[0], level); 3584 } 3585 3586 static void 3587 radeonfb_brightness_down(device_t dev) 3588 { 3589 struct radeonfb_softc *sc = device_private(dev); 3590 int level; 3591 3592 /* we assume the main display is the first one - need a better way */ 3593 if (sc->sc_ndisplays < 1) return; 3594 level = radeonfb_get_backlight(&sc->sc_displays[0]); 3595 level = max(0, level - 5); 3596 radeonfb_set_backlight(&sc->sc_displays[0], level); 3597 } 3598
Indexes created Wed Sep 24 05:09:52 GMT 2025