radeonfb.c revision 1.52
1 /* $NetBSD: radeonfb.c,v 1.52 2012/01/11 16:02:30 macallan Exp $ */ 2 3 /*- 4 * Copyright (c) 2006 Itronix Inc. 5 * All rights reserved. 6 * 7 * Written by Garrett D'Amore for Itronix Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. The name of Itronix Inc. may not be used to endorse 18 * or promote products derived from this software without specific 19 * prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY ITRONIX INC. ``AS IS'' AND ANY EXPRESS 22 * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 23 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL ITRONIX INC. BE LIABLE FOR ANY 25 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE 27 * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 29 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 30 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 31 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * ATI Technologies Inc. ("ATI") has not assisted in the creation of, and 36 * does not endorse, this software. ATI will not be responsible or liable 37 * for any actual or alleged damage or loss caused by or in connection with 38 * the use of or reliance on this software. 39 */ 40 41 /* 42 * Portions of this code were taken from XFree86's Radeon driver, which bears 43 * this notice: 44 * 45 * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and 46 * VA Linux Systems Inc., Fremont, California. 47 * 48 * All Rights Reserved. 49 * 50 * Permission is hereby granted, free of charge, to any person obtaining 51 * a copy of this software and associated documentation files (the 52 * "Software"), to deal in the Software without restriction, including 53 * without limitation on the rights to use, copy, modify, merge, 54 * publish, distribute, sublicense, and/or sell copies of the Software, 55 * and to permit persons to whom the Software is furnished to do so, 56 * subject to the following conditions: 57 * 58 * The above copyright notice and this permission notice (including the 59 * next paragraph) shall be included in all copies or substantial 60 * portions of the Software. 61 * 62 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 63 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 64 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 65 * NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR 66 * THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 67 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 68 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 69 * DEALINGS IN THE SOFTWARE. 70 */ 71 72 #include <sys/cdefs.h> 73 __KERNEL_RCSID(0, "$NetBSD: radeonfb.c,v 1.52 2012/01/11 16:02:30 macallan Exp $"); 74 75 #include <sys/param.h> 76 #include <sys/systm.h> 77 #include <sys/device.h> 78 #include <sys/malloc.h> 79 #include <sys/bus.h> 80 #include <sys/kernel.h> 81 #include <sys/lwp.h> 82 #include <sys/kauth.h> 83 84 #include <dev/wscons/wsdisplayvar.h> 85 #include <dev/wscons/wsconsio.h> 86 #include <dev/wsfont/wsfont.h> 87 #include <dev/rasops/rasops.h> 88 #include <dev/videomode/videomode.h> 89 #include <dev/videomode/edidvar.h> 90 #include <dev/wscons/wsdisplay_vconsvar.h> 91 #include <dev/pci/wsdisplay_pci.h> 92 93 #include <dev/pci/pcidevs.h> 94 #include <dev/pci/pcireg.h> 95 #include <dev/pci/pcivar.h> 96 #include <dev/pci/pciio.h> 97 #include <dev/pci/radeonfbreg.h> 98 #include <dev/pci/radeonfbvar.h> 99 #include "opt_radeonfb.h" 100 #include "opt_vcons.h" 101 102 #ifdef RADEONFB_DEPTH_32 103 #define RADEONFB_DEFAULT_DEPTH 32 104 #else 105 #define RADEONFB_DEFAULT_DEPTH 8 106 #endif 107 108 static int radeonfb_match(device_t, cfdata_t, void *); 109 static void radeonfb_attach(device_t, device_t, void *); 110 static int radeonfb_ioctl(void *, void *, unsigned long, void *, int, 111 struct lwp *); 112 static paddr_t radeonfb_mmap(void *, void *, off_t, int); 113 static int radeonfb_scratch_test(struct radeonfb_softc *, int, uint32_t); 114 static void radeonfb_loadbios(struct radeonfb_softc *, 115 const struct pci_attach_args *); 116 117 static uintmax_t radeonfb_getprop_num(struct radeonfb_softc *, const char *, 118 uintmax_t); 119 static int radeonfb_getclocks(struct radeonfb_softc *); 120 static int radeonfb_gettmds(struct radeonfb_softc *); 121 static int radeonfb_calc_dividers(struct radeonfb_softc *, uint32_t, 122 uint32_t *, uint32_t *); 123 static int radeonfb_getconnectors(struct radeonfb_softc *); 124 static const struct videomode *radeonfb_modelookup(const char *); 125 static void radeonfb_init_screen(void *, struct vcons_screen *, int, long *); 126 static void radeonfb_pllwriteupdate(struct radeonfb_softc *, int); 127 static void radeonfb_pllwaitatomicread(struct radeonfb_softc *, int); 128 static void radeonfb_program_vclk(struct radeonfb_softc *, int, int); 129 static void radeonfb_modeswitch(struct radeonfb_display *); 130 static void radeonfb_setcrtc(struct radeonfb_display *, int); 131 static void radeonfb_init_misc(struct radeonfb_softc *); 132 static void radeonfb_set_fbloc(struct radeonfb_softc *); 133 static void radeonfb_init_palette(struct radeonfb_softc *, int); 134 static void radeonfb_r300cg_workaround(struct radeonfb_softc *); 135 136 static int radeonfb_isblank(struct radeonfb_display *); 137 static void radeonfb_blank(struct radeonfb_display *, int); 138 static int radeonfb_set_cursor(struct radeonfb_display *, 139 struct wsdisplay_cursor *); 140 static int radeonfb_set_curpos(struct radeonfb_display *, 141 struct wsdisplay_curpos *); 142 143 /* acceleration support */ 144 static void radeonfb_rectfill(struct radeonfb_display *, int dstx, int dsty, 145 int width, int height, uint32_t color); 146 static void radeonfb_bitblt(struct radeonfb_display *, int srcx, int srcy, 147 int dstx, int dsty, int width, int height, int rop, uint32_t mask); 148 149 /* hw cursor support */ 150 static void radeonfb_cursor_cmap(struct radeonfb_display *); 151 static void radeonfb_cursor_shape(struct radeonfb_display *); 152 static void radeonfb_cursor_position(struct radeonfb_display *); 153 static void radeonfb_cursor_visible(struct radeonfb_display *); 154 static void radeonfb_cursor_update(struct radeonfb_display *, unsigned); 155 156 static void radeonfb_wait_fifo(struct radeonfb_softc *, int); 157 static void radeonfb_engine_idle(struct radeonfb_softc *); 158 static void radeonfb_engine_flush(struct radeonfb_softc *); 159 static void radeonfb_engine_reset(struct radeonfb_softc *); 160 static void radeonfb_engine_init(struct radeonfb_display *); 161 static inline void radeonfb_unclip(struct radeonfb_softc *); 162 163 static void radeonfb_eraserows(void *, int, int, long); 164 static void radeonfb_erasecols(void *, int, int, int, long); 165 static void radeonfb_copyrows(void *, int, int, int); 166 static void radeonfb_copycols(void *, int, int, int, int); 167 static void radeonfb_cursor(void *, int, int, int); 168 static void radeonfb_putchar(void *, int, int, unsigned, long); 169 static void radeonfb_putchar_aa32(void *, int, int, unsigned, long); 170 static void radeonfb_putchar_wrapper(void *, int, int, unsigned, long); 171 172 static int radeonfb_get_backlight(struct radeonfb_display *); 173 static int radeonfb_set_backlight(struct radeonfb_display *, int); 174 static void radeonfb_lvds_callout(void *); 175 176 static void radeonfb_brightness_up(device_t); 177 static void radeonfb_brightness_down(device_t); 178 179 static struct videomode *radeonfb_best_refresh(struct videomode *, 180 struct videomode *); 181 static void radeonfb_pickres(struct radeonfb_display *, uint16_t *, 182 uint16_t *, int); 183 static const struct videomode *radeonfb_port_mode(struct radeonfb_softc *, 184 struct radeonfb_port *, int, int); 185 186 static int radeonfb_drm_print(void *, const char *); 187 188 #ifdef RADEONFB_DEBUG 189 int radeon_debug = 1; 190 #define DPRINTF(x) \ 191 if (radeon_debug) printf x 192 #define PRINTREG(r) DPRINTF((#r " = %08x\n", GET32(sc, r))) 193 #define PRINTPLL(r) DPRINTF((#r " = %08x\n", GETPLL(sc, r))) 194 #else 195 #define DPRINTF(x) 196 #define PRINTREG(r) 197 #define PRINTPLL(r) 198 #endif 199 200 #define ROUNDUP(x,y) (((x) + ((y) - 1)) & ~((y) - 1)) 201 202 #ifndef RADEON_DEFAULT_MODE 203 /* any reasonably modern display should handle this */ 204 #define RADEON_DEFAULT_MODE "1024x768x60" 205 #endif 206 207 extern const u_char rasops_cmap[768]; 208 209 const char *radeonfb_default_mode = RADEON_DEFAULT_MODE; 210 211 static struct { 212 int size; /* minimum memory size (MB) */ 213 int maxx; /* maximum x dimension */ 214 int maxy; /* maximum y dimension */ 215 int maxbpp; /* maximum bpp */ 216 int maxdisp; /* maximum logical display count */ 217 } radeonfb_limits[] = { 218 { 32, 2048, 1536, 32, 2 }, 219 { 16, 1600, 1200, 32, 2 }, 220 { 8, 1600, 1200, 32, 1 }, 221 { 0, 0, 0, 0, 0 }, 222 }; 223 224 static struct wsscreen_descr radeonfb_stdscreen = { 225 "fb", /* name */ 226 0, 0, /* ncols, nrows */ 227 NULL, /* textops */ 228 8, 16, /* fontwidth, fontheight */ 229 WSSCREEN_WSCOLORS, /* capabilities */ 230 0, /* modecookie */ 231 }; 232 233 struct wsdisplay_accessops radeonfb_accessops = { 234 radeonfb_ioctl, 235 radeonfb_mmap, 236 NULL, /* vcons_alloc_screen */ 237 NULL, /* vcons_free_screen */ 238 NULL, /* vcons_show_screen */ 239 NULL, /* load_font */ 240 NULL, /* pollc */ 241 NULL, /* scroll */ 242 }; 243 244 static struct { 245 uint16_t devid; 246 uint16_t family; 247 uint16_t flags; 248 } radeonfb_devices[] = 249 { 250 /* R100 family */ 251 { PCI_PRODUCT_ATI_RADEON_R100_QD, RADEON_R100, 0 }, 252 { PCI_PRODUCT_ATI_RADEON_R100_QE, RADEON_R100, 0 }, 253 { PCI_PRODUCT_ATI_RADEON_R100_QF, RADEON_R100, 0 }, 254 { PCI_PRODUCT_ATI_RADEON_R100_QG, RADEON_R100, 0 }, 255 256 /* RV100 family */ 257 { PCI_PRODUCT_ATI_RADEON_RV100_LY, RADEON_RV100, RFB_MOB }, 258 { PCI_PRODUCT_ATI_RADEON_RV100_LZ, RADEON_RV100, RFB_MOB }, 259 { PCI_PRODUCT_ATI_RADEON_RV100_QY, RADEON_RV100, 0 }, 260 { PCI_PRODUCT_ATI_RADEON_RV100_QZ, RADEON_RV100, 0 }, 261 262 /* RS100 family */ 263 { PCI_PRODUCT_ATI_RADEON_RS100_4136, RADEON_RS100, 0 }, 264 { PCI_PRODUCT_ATI_RADEON_RS100_4336, RADEON_RS100, RFB_MOB }, 265 266 /* RS200/RS250 family */ 267 { PCI_PRODUCT_ATI_RADEON_RS200_4337, RADEON_RS200, RFB_MOB }, 268 { PCI_PRODUCT_ATI_RADEON_RS200_A7, RADEON_RS200, 0 }, 269 { PCI_PRODUCT_ATI_RADEON_RS250_B7, RADEON_RS200, RFB_MOB }, 270 { PCI_PRODUCT_ATI_RADEON_RS250_D7, RADEON_RS200, 0 }, 271 272 /* R200 family */ 273 /* add more R200 products? , 5148 */ 274 { PCI_PRODUCT_ATI_RADEON_R200_BB, RADEON_R200, 0 }, 275 { PCI_PRODUCT_ATI_RADEON_R200_BC, RADEON_R200, 0 }, 276 { PCI_PRODUCT_ATI_RADEON_R200_QH, RADEON_R200, 0 }, 277 { PCI_PRODUCT_ATI_RADEON_R200_QL, RADEON_R200, 0 }, 278 { PCI_PRODUCT_ATI_RADEON_R200_QM, RADEON_R200, 0 }, 279 280 /* RV200 family */ 281 { PCI_PRODUCT_ATI_RADEON_RV200_LW, RADEON_RV200, RFB_MOB }, 282 { PCI_PRODUCT_ATI_RADEON_RV200_LX, RADEON_RV200, RFB_MOB }, 283 { PCI_PRODUCT_ATI_RADEON_RV200_QW, RADEON_RV200, 0 }, 284 { PCI_PRODUCT_ATI_RADEON_RV200_QX, RADEON_RV200, 0 }, 285 286 /* RV250 family */ 287 { PCI_PRODUCT_ATI_RADEON_RV250_4966, RADEON_RV250, 0 }, 288 { PCI_PRODUCT_ATI_RADEON_RV250_4967, RADEON_RV250, 0 }, 289 { PCI_PRODUCT_ATI_RADEON_RV250_4C64, RADEON_RV250, RFB_MOB }, 290 { PCI_PRODUCT_ATI_RADEON_RV250_4C66, RADEON_RV250, RFB_MOB }, 291 { PCI_PRODUCT_ATI_RADEON_RV250_4C67, RADEON_RV250, RFB_MOB }, 292 293 /* RS300 family */ 294 { PCI_PRODUCT_ATI_RADEON_RS300_X5, RADEON_RS300, 0 }, 295 { PCI_PRODUCT_ATI_RADEON_RS300_X4, RADEON_RS300, 0 }, 296 { PCI_PRODUCT_ATI_RADEON_RS300_7834, RADEON_RS300, 0 }, 297 { PCI_PRODUCT_ATI_RADEON_RS300_7835, RADEON_RS300, RFB_MOB }, 298 299 /* RV280 family */ 300 { PCI_PRODUCT_ATI_RADEON_RV280_5960, RADEON_RV280, 0 }, 301 { PCI_PRODUCT_ATI_RADEON_RV280_5961, RADEON_RV280, 0 }, 302 { PCI_PRODUCT_ATI_RADEON_RV280_5962, RADEON_RV280, 0 }, 303 { PCI_PRODUCT_ATI_RADEON_RV280_5963, RADEON_RV280, 0 }, 304 { PCI_PRODUCT_ATI_RADEON_RV280_5964, RADEON_RV280, 0 }, 305 { PCI_PRODUCT_ATI_RADEON_RV280_5C61, RADEON_RV280, RFB_MOB }, 306 { PCI_PRODUCT_ATI_RADEON_RV280_5C63, RADEON_RV280, RFB_MOB }, 307 308 /* R300 family */ 309 { PCI_PRODUCT_ATI_RADEON_R300_AD, RADEON_R300, 0 }, 310 { PCI_PRODUCT_ATI_RADEON_R300_AE, RADEON_R300, 0 }, 311 { PCI_PRODUCT_ATI_RADEON_R300_AF, RADEON_R300, 0 }, 312 { PCI_PRODUCT_ATI_RADEON_R300_AG, RADEON_R300, 0 }, 313 { PCI_PRODUCT_ATI_RADEON_R300_ND, RADEON_R300, 0 }, 314 { PCI_PRODUCT_ATI_RADEON_R300_NE, RADEON_R300, 0 }, 315 { PCI_PRODUCT_ATI_RADEON_R300_NF, RADEON_R300, 0 }, 316 { PCI_PRODUCT_ATI_RADEON_R300_NG, RADEON_R300, 0 }, 317 318 /* RV350/RV360 family */ 319 { PCI_PRODUCT_ATI_RADEON_RV350_AP, RADEON_RV350, 0 }, 320 { PCI_PRODUCT_ATI_RADEON_RV350_AQ, RADEON_RV350, 0 }, 321 { PCI_PRODUCT_ATI_RADEON_RV360_AR, RADEON_RV350, 0 }, 322 { PCI_PRODUCT_ATI_RADEON_RV350_AS, RADEON_RV350, 0 }, 323 { PCI_PRODUCT_ATI_RADEON_RV350_AT, RADEON_RV350, 0 }, 324 { PCI_PRODUCT_ATI_RADEON_RV350_AV, RADEON_RV350, 0 }, 325 { PCI_PRODUCT_ATI_RADEON_RV350_NP, RADEON_RV350, RFB_MOB }, 326 { PCI_PRODUCT_ATI_RADEON_RV350_NQ, RADEON_RV350, RFB_MOB }, 327 { PCI_PRODUCT_ATI_RADEON_RV350_NR, RADEON_RV350, RFB_MOB }, 328 { PCI_PRODUCT_ATI_RADEON_RV350_NS, RADEON_RV350, RFB_MOB }, 329 { PCI_PRODUCT_ATI_RADEON_RV350_NT, RADEON_RV350, RFB_MOB }, 330 { PCI_PRODUCT_ATI_RADEON_RV350_NV, RADEON_RV350, RFB_MOB }, 331 332 /* R350/R360 family */ 333 { PCI_PRODUCT_ATI_RADEON_R350_AH, RADEON_R350, 0 }, 334 { PCI_PRODUCT_ATI_RADEON_R350_AI, RADEON_R350, 0 }, 335 { PCI_PRODUCT_ATI_RADEON_R350_AJ, RADEON_R350, 0 }, 336 { PCI_PRODUCT_ATI_RADEON_R350_AK, RADEON_R350, 0 }, 337 { PCI_PRODUCT_ATI_RADEON_R350_NH, RADEON_R350, 0 }, 338 { PCI_PRODUCT_ATI_RADEON_R350_NI, RADEON_R350, 0 }, 339 { PCI_PRODUCT_ATI_RADEON_R350_NK, RADEON_R350, 0 }, 340 { PCI_PRODUCT_ATI_RADEON_R360_NJ, RADEON_R350, 0 }, 341 342 /* RV380/RV370 family */ 343 { PCI_PRODUCT_ATI_RADEON_RV380_3150, RADEON_RV380, RFB_MOB }, 344 { PCI_PRODUCT_ATI_RADEON_RV380_3154, RADEON_RV380, RFB_MOB }, 345 { PCI_PRODUCT_ATI_RADEON_RV380_3E50, RADEON_RV380, 0 }, 346 { PCI_PRODUCT_ATI_RADEON_RV380_3E54, RADEON_RV380, 0 }, 347 { PCI_PRODUCT_ATI_RADEON_RV370_5460, RADEON_RV380, RFB_MOB }, 348 { PCI_PRODUCT_ATI_RADEON_RV370_5464, RADEON_RV380, RFB_MOB }, 349 { PCI_PRODUCT_ATI_RADEON_RV370_5B60, RADEON_RV380, 0 }, 350 { PCI_PRODUCT_ATI_RADEON_RV370_5B64, RADEON_RV380, 0 }, 351 { PCI_PRODUCT_ATI_RADEON_RV370_5B65, RADEON_RV380, 0 }, 352 353 /* R420/R423 family */ 354 { PCI_PRODUCT_ATI_RADEON_R420_JH, RADEON_R420, 0 }, 355 { PCI_PRODUCT_ATI_RADEON_R420_JI, RADEON_R420, 0 }, 356 { PCI_PRODUCT_ATI_RADEON_R420_JJ, RADEON_R420, 0 }, 357 { PCI_PRODUCT_ATI_RADEON_R420_JK, RADEON_R420, 0 }, 358 { PCI_PRODUCT_ATI_RADEON_R420_JL, RADEON_R420, 0 }, 359 { PCI_PRODUCT_ATI_RADEON_R420_JM, RADEON_R420, 0 }, 360 { PCI_PRODUCT_ATI_RADEON_R420_JN, RADEON_R420, RFB_MOB }, 361 { PCI_PRODUCT_ATI_RADEON_R420_JP, RADEON_R420, 0 }, 362 { PCI_PRODUCT_ATI_RADEON_R423_UH, RADEON_R420, 0 }, 363 { PCI_PRODUCT_ATI_RADEON_R423_UI, RADEON_R420, 0 }, 364 { PCI_PRODUCT_ATI_RADEON_R423_UJ, RADEON_R420, 0 }, 365 { PCI_PRODUCT_ATI_RADEON_R423_UK, RADEON_R420, 0 }, 366 { PCI_PRODUCT_ATI_RADEON_R423_UQ, RADEON_R420, 0 }, 367 { PCI_PRODUCT_ATI_RADEON_R423_UR, RADEON_R420, 0 }, 368 { PCI_PRODUCT_ATI_RADEON_R423_UT, RADEON_R420, 0 }, 369 { PCI_PRODUCT_ATI_RADEON_R423_5D57, RADEON_R420, 0 }, 370 { PCI_PRODUCT_ATI_RADEON_R430_554F, RADEON_R420, 0 }, 371 372 { 0, 0, 0 } 373 }; 374 375 static struct { 376 int divider; 377 int mask; 378 } radeonfb_dividers[] = { 379 { 1, 0 }, 380 { 2, 1 }, 381 { 3, 4 }, 382 { 4, 2 }, 383 { 6, 6 }, 384 { 8, 3 }, 385 { 12, 7 }, 386 { 0, 0 } 387 }; 388 389 /* 390 * This table taken from X11. 391 */ 392 static const struct { 393 int family; 394 struct radeon_tmds_pll plls[4]; 395 } radeonfb_tmds_pll[] = { 396 { RADEON_R100, {{12000, 0xa1b}, {-1, 0xa3f}}}, 397 { RADEON_RV100, {{12000, 0xa1b}, {-1, 0xa3f}}}, 398 { RADEON_RS100, {{0, 0}}}, 399 { RADEON_RV200, {{15000, 0xa1b}, {-1, 0xa3f}}}, 400 { RADEON_RS200, {{15000, 0xa1b}, {-1, 0xa3f}}}, 401 { RADEON_R200, {{15000, 0xa1b}, {-1, 0xa3f}}}, 402 { RADEON_RV250, {{15500, 0x81b}, {-1, 0x83f}}}, 403 { RADEON_RS300, {{0, 0}}}, 404 { RADEON_RV280, {{13000, 0x400f4}, {15000, 0x400f7}}}, 405 { RADEON_R300, {{-1, 0xb01cb}}}, 406 { RADEON_R350, {{-1, 0xb01cb}}}, 407 { RADEON_RV350, {{15000, 0xb0155}, {-1, 0xb01cb}}}, 408 { RADEON_RV380, {{15000, 0xb0155}, {-1, 0xb01cb}}}, 409 { RADEON_R420, {{-1, 0xb01cb}}}, 410 }; 411 412 #define RADEONFB_BACKLIGHT_MAX 255 /* Maximum backlight level. */ 413 414 415 CFATTACH_DECL_NEW(radeonfb, sizeof (struct radeonfb_softc), 416 radeonfb_match, radeonfb_attach, NULL, NULL); 417 418 static int 419 radeonfb_match(device_t parent, cfdata_t match, void *aux) 420 { 421 const struct pci_attach_args *pa = aux; 422 int i; 423 424 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_ATI) 425 return 0; 426 427 for (i = 0; radeonfb_devices[i].devid; i++) { 428 if (PCI_PRODUCT(pa->pa_id) == radeonfb_devices[i].devid) 429 return 100; /* high to defeat VGA/VESA */ 430 } 431 432 return 0; 433 } 434 435 static void 436 radeonfb_attach(device_t parent, device_t dev, void *aux) 437 { 438 struct radeonfb_softc *sc = device_private(dev); 439 const struct pci_attach_args *pa = aux; 440 const char *mptr; 441 bus_size_t bsz; 442 pcireg_t screg; 443 int i, j, fg, bg, ul, flags; 444 uint32_t v; 445 446 sc->sc_dev = dev; 447 sc->sc_id = pa->pa_id; 448 for (i = 0; radeonfb_devices[i].devid; i++) { 449 if (PCI_PRODUCT(sc->sc_id) == radeonfb_devices[i].devid) 450 break; 451 } 452 453 pci_devinfo(sc->sc_id, pa->pa_class, 0, sc->sc_devinfo, 454 sizeof(sc->sc_devinfo)); 455 456 aprint_naive("\n"); 457 aprint_normal(": %s\n", sc->sc_devinfo); 458 459 DPRINTF((prop_dictionary_externalize(device_properties(dev)))); 460 461 KASSERT(radeonfb_devices[i].devid != 0); 462 sc->sc_pt = pa->pa_tag; 463 sc->sc_iot = pa->pa_iot; 464 sc->sc_pc = pa->pa_pc; 465 sc->sc_family = radeonfb_devices[i].family; 466 sc->sc_flags = radeonfb_devices[i].flags; 467 468 /* enable memory and IO access */ 469 screg = pci_conf_read(sc->sc_pc, sc->sc_pt, PCI_COMMAND_STATUS_REG); 470 screg |= PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE; 471 pci_conf_write(sc->sc_pc, sc->sc_pt, PCI_COMMAND_STATUS_REG, screg); 472 473 /* 474 * Some flags are general to entire chip families, and rather 475 * than clutter up the table with them, we go ahead and set 476 * them here. 477 */ 478 switch (sc->sc_family) { 479 case RADEON_RS100: 480 case RADEON_RS200: 481 sc->sc_flags |= RFB_IGP | RFB_RV100; 482 break; 483 484 case RADEON_RV100: 485 case RADEON_RV200: 486 case RADEON_RV250: 487 case RADEON_RV280: 488 sc->sc_flags |= RFB_RV100; 489 break; 490 491 case RADEON_RS300: 492 sc->sc_flags |= RFB_SDAC | RFB_IGP | RFB_RV100; 493 break; 494 495 case RADEON_R300: 496 case RADEON_RV350: 497 case RADEON_R350: 498 case RADEON_RV380: 499 case RADEON_R420: 500 /* newer chips */ 501 sc->sc_flags |= RFB_R300; 502 break; 503 504 case RADEON_R100: 505 sc->sc_flags |= RFB_NCRTC2; 506 break; 507 } 508 509 if ((sc->sc_family == RADEON_RV200) || 510 (sc->sc_family == RADEON_RV250) || 511 (sc->sc_family == RADEON_RV280) || 512 (sc->sc_family == RADEON_RV350)) { 513 bool inverted = 0; 514 /* backlight level is linear */ 515 DPRINTF(("found RV* chip, backlight is supposedly linear\n")); 516 prop_dictionary_get_bool(device_properties(sc->sc_dev), 517 "backlight_level_reverted", &inverted); 518 if (inverted) { 519 DPRINTF(("nope, it's inverted\n")); 520 sc->sc_flags |= RFB_INV_BLIGHT; 521 } 522 } else 523 sc->sc_flags |= RFB_INV_BLIGHT; 524 525 /* 526 * XXX: to support true multihead, this must change. 527 */ 528 sc->sc_ndisplays = 1; 529 530 /* XXX: */ 531 if (!HAS_CRTC2(sc)) { 532 sc->sc_ndisplays = 1; 533 } 534 535 if (pci_mapreg_map(pa, RADEON_MAPREG_MMIO, PCI_MAPREG_TYPE_MEM, 0, 536 &sc->sc_regt, &sc->sc_regh, &sc->sc_regaddr, 537 &sc->sc_regsz) != 0) { 538 aprint_error("%s: unable to map registers!\n", XNAME(sc)); 539 goto error; 540 } 541 542 if (pci_mapreg_info(sc->sc_pc, sc->sc_pt, PCI_MAPREG_ROM, 543 PCI_MAPREG_TYPE_ROM, &sc->sc_romaddr, &sc->sc_romsz, &flags) != 0) 544 { 545 aprint_error("%s: unable to find ROM!\n", XNAME(sc)); 546 goto error; 547 } 548 sc->sc_romt = sc->sc_memt; 549 550 /* scratch register test... */ 551 if (radeonfb_scratch_test(sc, RADEON_BIOS_0_SCRATCH, 0x55555555) || 552 radeonfb_scratch_test(sc, RADEON_BIOS_0_SCRATCH, 0xaaaaaaaa)) { 553 aprint_error("%s: scratch register test failed!\n", XNAME(sc)); 554 goto error; 555 } 556 557 PRINTREG(RADEON_BIOS_4_SCRATCH); 558 PRINTREG(RADEON_FP_GEN_CNTL); 559 sc->sc_fp_gen_cntl = GET32(sc, RADEON_FP_GEN_CNTL); 560 PRINTREG(RADEON_FP2_GEN_CNTL); 561 PRINTREG(RADEON_TMDS_CNTL); 562 PRINTREG(RADEON_TMDS_TRANSMITTER_CNTL); 563 PRINTREG(RADEON_TMDS_PLL_CNTL); 564 PRINTREG(RADEON_LVDS_GEN_CNTL); 565 PRINTREG(RADEON_FP_HORZ_STRETCH); 566 PRINTREG(RADEON_FP_VERT_STRETCH); 567 568 /* XXX: RV100 specific */ 569 PUT32(sc, RADEON_TMDS_PLL_CNTL, 0xa27); 570 571 PATCH32(sc, RADEON_TMDS_TRANSMITTER_CNTL, 572 RADEON_TMDS_TRANSMITTER_PLLEN, 573 RADEON_TMDS_TRANSMITTER_PLLEN | RADEON_TMDS_TRANSMITTER_PLLRST); 574 575 radeonfb_i2c_init(sc); 576 577 radeonfb_loadbios(sc, pa); 578 579 #ifdef RADEONFB_BIOS_INIT 580 if (radeonfb_bios_init(sc)) { 581 aprint_error("%s: BIOS inititialization failed\n", XNAME(sc)); 582 } 583 #endif 584 585 if (radeonfb_getclocks(sc)) { 586 aprint_error("%s: Unable to get reference clocks from BIOS\n", 587 XNAME(sc)); 588 goto error; 589 } 590 591 if (radeonfb_gettmds(sc)) { 592 aprint_error("%s: Unable to identify TMDS PLL settings\n", 593 XNAME(sc)); 594 goto error; 595 } 596 597 aprint_verbose("%s: refclk = %d.%03d MHz, refdiv = %d " 598 "minpll = %d, maxpll = %d\n", XNAME(sc), 599 (int)sc->sc_refclk / 1000, (int)sc->sc_refclk % 1000, 600 (int)sc->sc_refdiv, (int)sc->sc_minpll, (int)sc->sc_maxpll); 601 602 radeonfb_getconnectors(sc); 603 604 radeonfb_set_fbloc(sc); 605 606 for (i = 0; radeonfb_limits[i].size; i++) { 607 if (sc->sc_memsz >= radeonfb_limits[i].size) { 608 sc->sc_maxx = radeonfb_limits[i].maxx; 609 sc->sc_maxy = radeonfb_limits[i].maxy; 610 sc->sc_maxbpp = radeonfb_limits[i].maxbpp; 611 /* framebuffer offset, start at a 4K page */ 612 sc->sc_fboffset = sc->sc_memsz / 613 radeonfb_limits[i].maxdisp; 614 /* 615 * we use the fbsize to figure out where we can store 616 * things like cursor data. 617 */ 618 sc->sc_fbsize = 619 ROUNDUP(ROUNDUP(sc->sc_maxx * sc->sc_maxbpp / 8 , 620 RADEON_STRIDEALIGN) * sc->sc_maxy, 621 4096); 622 break; 623 } 624 } 625 626 627 radeonfb_init_misc(sc); 628 radeonfb_init_palette(sc, 0); 629 if (HAS_CRTC2(sc)) 630 radeonfb_init_palette(sc, 1); 631 632 /* program the DAC wirings */ 633 for (i = 0; i < (HAS_CRTC2(sc) ? 2 : 1); i++) { 634 switch (sc->sc_ports[i].rp_dac_type) { 635 case RADEON_DAC_PRIMARY: 636 PATCH32(sc, RADEON_DAC_CNTL2, 637 i ? RADEON_DAC2_DAC_CLK_SEL : 0, 638 ~RADEON_DAC2_DAC_CLK_SEL); 639 break; 640 case RADEON_DAC_TVDAC: 641 /* we always use the TVDAC to drive a secondary analog 642 * CRT for now. if we ever support TV-out this will 643 * have to change. 644 */ 645 SET32(sc, RADEON_DAC_CNTL2, 646 RADEON_DAC2_DAC2_CLK_SEL); 647 PATCH32(sc, RADEON_DISP_HW_DEBUG, 648 i ? 0 : RADEON_CRT2_DISP1_SEL, 649 ~RADEON_CRT2_DISP1_SEL); 650 break; 651 } 652 } 653 PRINTREG(RADEON_DAC_CNTL2); 654 PRINTREG(RADEON_DISP_HW_DEBUG); 655 656 /* other DAC programming */ 657 v = GET32(sc, RADEON_DAC_CNTL); 658 v &= (RADEON_DAC_RANGE_CNTL_MASK | RADEON_DAC_BLANKING); 659 v |= RADEON_DAC_MASK_ALL | RADEON_DAC_8BIT_EN; 660 PUT32(sc, RADEON_DAC_CNTL, v); 661 PRINTREG(RADEON_DAC_CNTL); 662 663 /* XXX: this may need more investigation */ 664 PUT32(sc, RADEON_TV_DAC_CNTL, 0x00280203); 665 PRINTREG(RADEON_TV_DAC_CNTL); 666 667 /* enable TMDS */ 668 SET32(sc, RADEON_FP_GEN_CNTL, 669 RADEON_FP_TMDS_EN | 670 RADEON_FP_CRTC_DONT_SHADOW_VPAR | 671 RADEON_FP_CRTC_DONT_SHADOW_HEND); 672 /* 673 * XXX 674 * no idea why this is necessary - if I do not clear this bit on my 675 * iBook G4 the screen remains black, even though it's already clear. 676 * It needs to be set on my Sun XVR-100 for the DVI port to work 677 */ 678 679 if (sc->sc_fp_gen_cntl & RADEON_FP_SEL_CRTC2) { 680 SET32(sc, RADEON_FP_GEN_CNTL, RADEON_FP_SEL_CRTC2); 681 } else 682 CLR32(sc, RADEON_FP_GEN_CNTL, RADEON_FP_SEL_CRTC2); 683 684 if (HAS_CRTC2(sc)) 685 SET32(sc, RADEON_FP2_GEN_CNTL, RADEON_FP2_SRC_SEL_CRTC2); 686 687 /* 688 * we use bus_space_map instead of pci_mapreg, because we don't 689 * need the full aperature space. no point in wasting virtual 690 * address space we don't intend to use, right? 691 */ 692 if ((sc->sc_memsz < (4096 * 1024)) || 693 (pci_mapreg_info(sc->sc_pc, sc->sc_pt, RADEON_MAPREG_VRAM, 694 PCI_MAPREG_TYPE_MEM, &sc->sc_memaddr, &bsz, NULL) != 0) || 695 (bsz < sc->sc_memsz)) { 696 sc->sc_memsz = 0; 697 aprint_error("%s: Bad frame buffer configuration\n", 698 XNAME(sc)); 699 goto error; 700 } 701 702 /* 64 MB should be enough -- more just wastes map entries */ 703 if (sc->sc_memsz > (64 << 20)) 704 sc->sc_memsz = (64 << 20); 705 706 sc->sc_memt = pa->pa_memt; 707 if (bus_space_map(sc->sc_memt, sc->sc_memaddr, sc->sc_memsz, 708 BUS_SPACE_MAP_LINEAR, &sc->sc_memh) != 0) { 709 sc->sc_memsz = 0; 710 aprint_error("%s: Unable to map frame buffer\n", XNAME(sc)); 711 goto error; 712 } 713 714 aprint_normal("%s: %d MB aperture at 0x%08x, " 715 "%d KB registers at 0x%08x\n", XNAME(sc), 716 (int)sc->sc_memsz >> 20, (unsigned)sc->sc_memaddr, 717 (int)sc->sc_regsz >> 10, (unsigned)sc->sc_regaddr); 718 719 /* setup default video mode from devprop (allows PROM override) */ 720 sc->sc_defaultmode = radeonfb_default_mode; 721 if (prop_dictionary_get_cstring_nocopy(device_properties(sc->sc_dev), 722 "videomode", &mptr)) { 723 724 strncpy(sc->sc_modebuf, mptr, sizeof(sc->sc_modebuf)); 725 sc->sc_defaultmode = sc->sc_modebuf; 726 } 727 728 /* initialize some basic display parameters */ 729 for (i = 0; i < sc->sc_ndisplays; i++) { 730 struct radeonfb_display *dp = &sc->sc_displays[i]; 731 struct rasops_info *ri; 732 long defattr; 733 struct wsemuldisplaydev_attach_args aa; 734 735 /* 736 * Figure out how many "displays" (desktops) we are going to 737 * support. If more than one, then each CRTC gets its own 738 * programming. 739 * 740 * XXX: this code needs to change to support mergedfb. 741 * XXX: would be nice to allow this to be overridden 742 */ 743 if (HAS_CRTC2(sc) && (sc->sc_ndisplays == 1)) { 744 DPRINTF(("dual crtcs!\n")); 745 dp->rd_ncrtcs = 2; 746 dp->rd_crtcs[0].rc_number = 0; 747 dp->rd_crtcs[1].rc_number = 1; 748 } else { 749 dp->rd_ncrtcs = 1; 750 dp->rd_crtcs[0].rc_number = i; 751 } 752 753 /* set up port pointer */ 754 for (j = 0; j < dp->rd_ncrtcs; j++) { 755 dp->rd_crtcs[j].rc_port = 756 &sc->sc_ports[dp->rd_crtcs[j].rc_number]; 757 } 758 759 dp->rd_softc = sc; 760 dp->rd_wsmode = WSDISPLAYIO_MODE_EMUL; 761 dp->rd_bg = WS_DEFAULT_BG; 762 dp->rd_bpp = RADEONFB_DEFAULT_DEPTH; /* XXX */ 763 764 /* for text mode, we pick a resolution that won't 765 * require panning */ 766 radeonfb_pickres(dp, &dp->rd_virtx, &dp->rd_virty, 0); 767 768 aprint_normal("%s: display %d: " 769 "initial virtual resolution %dx%d at %d bpp\n", 770 XNAME(sc), i, dp->rd_virtx, dp->rd_virty, dp->rd_bpp); 771 772 /* now select the *video mode* that we will use */ 773 for (j = 0; j < dp->rd_ncrtcs; j++) { 774 const struct videomode *vmp; 775 vmp = radeonfb_port_mode(sc, dp->rd_crtcs[j].rc_port, 776 dp->rd_virtx, dp->rd_virty); 777 778 /* 779 * virtual resolution should be at least as high as 780 * physical 781 */ 782 if (dp->rd_virtx < vmp->hdisplay || 783 dp->rd_virty < vmp->vdisplay) { 784 dp->rd_virtx = vmp->hdisplay; 785 dp->rd_virty = vmp->vdisplay; 786 } 787 788 dp->rd_crtcs[j].rc_videomode = *vmp; 789 printf("%s: port %d: physical %dx%d %dHz\n", 790 XNAME(sc), j, vmp->hdisplay, vmp->vdisplay, 791 DIVIDE(DIVIDE(vmp->dot_clock * 1000, 792 vmp->htotal), vmp->vtotal)); 793 } 794 795 /* N.B.: radeon wants 64-byte aligned stride */ 796 dp->rd_stride = dp->rd_virtx * dp->rd_bpp / 8; 797 dp->rd_stride = ROUNDUP(dp->rd_stride, RADEON_STRIDEALIGN); 798 799 dp->rd_offset = sc->sc_fboffset * i; 800 dp->rd_fbptr = (vaddr_t)bus_space_vaddr(sc->sc_memt, 801 sc->sc_memh) + dp->rd_offset; 802 dp->rd_curoff = sc->sc_fbsize; 803 dp->rd_curptr = dp->rd_fbptr + dp->rd_curoff; 804 805 DPRINTF(("fpbtr = %p\n", (void *)dp->rd_fbptr)); 806 807 switch (dp->rd_bpp) { 808 case 8: 809 dp->rd_format = 2; 810 break; 811 case 32: 812 dp->rd_format = 6; 813 break; 814 default: 815 aprint_error("%s: bad depth %d\n", XNAME(sc), 816 dp->rd_bpp); 817 goto error; 818 } 819 820 DPRINTF(("init engine\n")); 821 /* XXX: this seems suspicious - per display engine 822 initialization? */ 823 radeonfb_engine_init(dp); 824 825 /* copy the template into place */ 826 dp->rd_wsscreens_storage[0] = radeonfb_stdscreen; 827 dp->rd_wsscreens = dp->rd_wsscreens_storage; 828 829 /* and make up the list */ 830 dp->rd_wsscreenlist.nscreens = 1; 831 dp->rd_wsscreenlist.screens = (void *)&dp->rd_wsscreens; 832 833 vcons_init(&dp->rd_vd, dp, dp->rd_wsscreens, 834 &radeonfb_accessops); 835 836 dp->rd_vd.init_screen = radeonfb_init_screen; 837 838 dp->rd_console = 0; 839 prop_dictionary_get_bool(device_properties(sc->sc_dev), 840 "is_console", &dp->rd_console); 841 842 dp->rd_vscreen.scr_flags |= VCONS_SCREEN_IS_STATIC; 843 844 845 vcons_init_screen(&dp->rd_vd, &dp->rd_vscreen, 846 dp->rd_console, &defattr); 847 848 ri = &dp->rd_vscreen.scr_ri; 849 850 /* clear the screen */ 851 rasops_unpack_attr(defattr, &fg, &bg, &ul); 852 radeonfb_rectfill(dp, 0, 0, ri->ri_width, ri->ri_height, 853 ri->ri_devcmap[bg & 0xf]); 854 855 dp->rd_wsscreens->textops = &ri->ri_ops; 856 dp->rd_wsscreens->capabilities = ri->ri_caps; 857 dp->rd_wsscreens->nrows = ri->ri_rows; 858 dp->rd_wsscreens->ncols = ri->ri_cols; 859 860 #ifdef SPLASHSCREEN 861 dp->rd_splash.si_depth = ri->ri_depth; 862 dp->rd_splash.si_bits = ri->ri_bits; 863 dp->rd_splash.si_hwbits = ri->ri_hwbits; 864 dp->rd_splash.si_width = ri->ri_width; 865 dp->rd_splash.si_height = ri->ri_height; 866 dp->rd_splash.si_stride = ri->ri_stride; 867 dp->rd_splash.si_fillrect = NULL; 868 #endif 869 if (dp->rd_console) { 870 871 radeonfb_modeswitch(dp); 872 wsdisplay_cnattach(dp->rd_wsscreens, ri, 0, 0, 873 defattr); 874 #ifdef SPLASHSCREEN 875 if (splash_render(&dp->rd_splash, 876 SPLASH_F_CENTER|SPLASH_F_FILL) == 0) 877 SCREEN_DISABLE_DRAWING(&dp->rd_vscreen); 878 else 879 #endif 880 vcons_replay_msgbuf(&dp->rd_vscreen); 881 } else { 882 883 /* 884 * since we're not the console we can postpone 885 * the rest until someone actually allocates a 886 * screen for us. but we do clear the screen 887 * at least. 888 */ 889 memset(ri->ri_bits, 0, 1024); 890 891 radeonfb_modeswitch(dp); 892 #ifdef SPLASHSCREEN 893 if (splash_render(&dp->rd_splash, 894 SPLASH_F_CENTER|SPLASH_F_FILL) == 0) 895 SCREEN_DISABLE_DRAWING(&dp->rd_vscreen); 896 #endif 897 } 898 899 aa.console = dp->rd_console; 900 aa.scrdata = &dp->rd_wsscreenlist; 901 aa.accessops = &radeonfb_accessops; 902 aa.accesscookie = &dp->rd_vd; 903 904 config_found(sc->sc_dev, &aa, wsemuldisplaydevprint); 905 906 radeonfb_blank(dp, 0); 907 908 /* Initialise delayed lvds operations for backlight. */ 909 callout_init(&dp->rd_bl_lvds_co, 0); 910 callout_setfunc(&dp->rd_bl_lvds_co, 911 radeonfb_lvds_callout, dp); 912 } 913 914 /* 915 * if we have console output via firmware like on sparc64 it may 916 * interfere with DAC programming so program the palette again 917 * here after we took over 918 */ 919 radeonfb_init_palette(sc, 0); 920 if (HAS_CRTC2(sc)) 921 radeonfb_init_palette(sc, 1); 922 923 pmf_event_register(dev, PMFE_DISPLAY_BRIGHTNESS_UP, 924 radeonfb_brightness_up, TRUE); 925 pmf_event_register(dev, PMFE_DISPLAY_BRIGHTNESS_DOWN, 926 radeonfb_brightness_down, TRUE); 927 928 config_found_ia(dev, "drm", aux, radeonfb_drm_print); 929 930 return; 931 932 error: 933 if (sc->sc_biossz) 934 free(sc->sc_bios, M_DEVBUF); 935 936 if (sc->sc_regsz) 937 bus_space_unmap(sc->sc_regt, sc->sc_regh, sc->sc_regsz); 938 939 if (sc->sc_memsz) 940 bus_space_unmap(sc->sc_memt, sc->sc_memh, sc->sc_memsz); 941 } 942 943 static int 944 radeonfb_drm_print(void *aux, const char *pnp) 945 { 946 if (pnp) 947 aprint_normal("drm at %s", pnp); 948 return (UNCONF); 949 } 950 951 int 952 radeonfb_ioctl(void *v, void *vs, 953 unsigned long cmd, void *d, int flag, struct lwp *l) 954 { 955 struct vcons_data *vd; 956 struct radeonfb_display *dp; 957 struct radeonfb_softc *sc; 958 struct wsdisplay_param *param; 959 960 vd = (struct vcons_data *)v; 961 dp = (struct radeonfb_display *)vd->cookie; 962 sc = dp->rd_softc; 963 964 switch (cmd) { 965 case WSDISPLAYIO_GTYPE: 966 *(unsigned *)d = WSDISPLAY_TYPE_PCIMISC; 967 return 0; 968 969 case WSDISPLAYIO_GINFO: 970 if (vd->active != NULL) { 971 struct wsdisplay_fbinfo *fb; 972 fb = (struct wsdisplay_fbinfo *)d; 973 fb->width = dp->rd_virtx; 974 fb->height = dp->rd_virty; 975 fb->depth = dp->rd_bpp; 976 fb->cmsize = 256; 977 return 0; 978 } else 979 return ENODEV; 980 case WSDISPLAYIO_GVIDEO: 981 if (radeonfb_isblank(dp)) 982 *(unsigned *)d = WSDISPLAYIO_VIDEO_OFF; 983 else 984 *(unsigned *)d = WSDISPLAYIO_VIDEO_ON; 985 return 0; 986 987 case WSDISPLAYIO_SVIDEO: 988 radeonfb_blank(dp, 989 (*(unsigned int *)d == WSDISPLAYIO_VIDEO_OFF)); 990 return 0; 991 992 case WSDISPLAYIO_GETCMAP: 993 #if 0 994 if (dp->rd_bpp == 8) 995 return radeonfb_getcmap(sc, 996 (struct wsdisplay_cmap *)d); 997 #endif 998 return EINVAL; 999 1000 case WSDISPLAYIO_PUTCMAP: 1001 #if 0 1002 if (dp->rd_bpp == 8) 1003 return radeonfb_putcmap(sc, 1004 (struct wsdisplay_cmap *)d); 1005 #endif 1006 return EINVAL; 1007 1008 case WSDISPLAYIO_LINEBYTES: 1009 *(unsigned *)d = dp->rd_stride; 1010 return 0; 1011 1012 case WSDISPLAYIO_SMODE: 1013 if (*(int *)d != dp->rd_wsmode) { 1014 dp->rd_wsmode = *(int *)d; 1015 if ((dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) && 1016 (dp->rd_vd.active)) { 1017 radeonfb_engine_init(dp); 1018 radeonfb_init_palette(sc, dp == &sc->sc_displays[0] ? 0 : 1); 1019 radeonfb_modeswitch(dp); 1020 vcons_redraw_screen(dp->rd_vd.active); 1021 } 1022 } 1023 return 0; 1024 1025 case WSDISPLAYIO_GCURMAX: 1026 ((struct wsdisplay_curpos *)d)->x = RADEON_CURSORMAXX; 1027 ((struct wsdisplay_curpos *)d)->y = RADEON_CURSORMAXY; 1028 return 0; 1029 1030 case WSDISPLAYIO_SCURSOR: 1031 return radeonfb_set_cursor(dp, (struct wsdisplay_cursor *)d); 1032 1033 case WSDISPLAYIO_GCURSOR: 1034 return EPASSTHROUGH; 1035 1036 case WSDISPLAYIO_GCURPOS: 1037 ((struct wsdisplay_curpos *)d)->x = dp->rd_cursor.rc_pos.x; 1038 ((struct wsdisplay_curpos *)d)->y = dp->rd_cursor.rc_pos.y; 1039 return 0; 1040 1041 case WSDISPLAYIO_SCURPOS: 1042 return radeonfb_set_curpos(dp, (struct wsdisplay_curpos *)d); 1043 1044 case WSDISPLAYIO_SSPLASH: 1045 #if defined(SPLASHSCREEN) 1046 if (*(int *)d == 1) { 1047 SCREEN_DISABLE_DRAWING(&dp->rd_vscreen); 1048 splash_render(&dp->rd_splash, 1049 SPLASH_F_CENTER|SPLASH_F_FILL); 1050 } else 1051 SCREEN_ENABLE_DRAWING(&dp->rd_vscreen); 1052 return 0; 1053 #else 1054 return ENODEV; 1055 #endif 1056 case WSDISPLAYIO_GETPARAM: 1057 param = (struct wsdisplay_param *)d; 1058 if (param->param == WSDISPLAYIO_PARAM_BACKLIGHT) { 1059 param->min = 0; 1060 param->max = RADEONFB_BACKLIGHT_MAX; 1061 param->curval = radeonfb_get_backlight(dp); 1062 return 0; 1063 } 1064 return EPASSTHROUGH; 1065 1066 case WSDISPLAYIO_SETPARAM: 1067 param = (struct wsdisplay_param *)d; 1068 if (param->param == WSDISPLAYIO_PARAM_BACKLIGHT) { 1069 return radeonfb_set_backlight(dp, param->curval); 1070 } 1071 return EPASSTHROUGH; 1072 1073 /* PCI config read/write passthrough. */ 1074 case PCI_IOC_CFGREAD: 1075 case PCI_IOC_CFGWRITE: 1076 return pci_devioctl(sc->sc_pc, sc->sc_pt, cmd, d, flag, l); 1077 1078 case WSDISPLAYIO_GET_BUSID: 1079 return wsdisplayio_busid_pci(sc->sc_dev, sc->sc_pc, 1080 sc->sc_pt, d); 1081 1082 case WSDISPLAYIO_GET_EDID: { 1083 struct wsdisplayio_edid_info *ei = d; 1084 return wsdisplayio_get_edid(sc->sc_dev, ei); 1085 } 1086 1087 default: 1088 return EPASSTHROUGH; 1089 } 1090 } 1091 1092 paddr_t 1093 radeonfb_mmap(void *v, void *vs, off_t offset, int prot) 1094 { 1095 struct vcons_data *vd; 1096 struct radeonfb_display *dp; 1097 struct radeonfb_softc *sc; 1098 paddr_t pa; 1099 1100 vd = (struct vcons_data *)v; 1101 dp = (struct radeonfb_display *)vd->cookie; 1102 sc = dp->rd_softc; 1103 1104 /* XXX: note that we don't allow mapping of registers right now */ 1105 /* XXX: this means that the XFree86 radeon driver won't work */ 1106 if ((offset >= 0) && (offset < (dp->rd_virty * dp->rd_stride))) { 1107 pa = bus_space_mmap(sc->sc_memt, 1108 sc->sc_memaddr + dp->rd_offset + offset, 0, 1109 prot, BUS_SPACE_MAP_LINEAR); 1110 return pa; 1111 } 1112 1113 #ifdef RADEONFB_MMAP_BARS 1114 /* 1115 * restrict all other mappings to processes with superuser privileges 1116 * or the kernel itself 1117 */ 1118 if (kauth_authorize_generic(kauth_cred_get(), KAUTH_GENERIC_ISSUSER, 1119 NULL) != 0) { 1120 aprint_error_dev(sc->sc_dev, "mmap() rejected.\n"); 1121 return -1; 1122 } 1123 1124 if ((offset >= sc->sc_regaddr) && 1125 (offset < sc->sc_regaddr + sc->sc_regsz)) { 1126 return bus_space_mmap(sc->sc_regt, offset, 0, prot, 1127 BUS_SPACE_MAP_LINEAR); 1128 } 1129 1130 if ((offset >= sc->sc_memaddr) && 1131 (offset < sc->sc_memaddr + sc->sc_memsz)) { 1132 return bus_space_mmap(sc->sc_memt, offset, 0, prot, 1133 BUS_SPACE_MAP_LINEAR); 1134 } 1135 1136 if ((offset >= sc->sc_romaddr) && 1137 (offset < sc->sc_romaddr + sc->sc_romsz)) { 1138 return bus_space_mmap(sc->sc_memt, offset, 0, prot, 1139 BUS_SPACE_MAP_LINEAR); 1140 } 1141 1142 #ifdef PCI_MAGIC_IO_RANGE 1143 /* allow mapping of IO space */ 1144 if ((offset >= PCI_MAGIC_IO_RANGE) && 1145 (offset < PCI_MAGIC_IO_RANGE + 0x10000)) { 1146 pa = bus_space_mmap(sc->sc_iot, offset - PCI_MAGIC_IO_RANGE, 1147 0, prot, 0); 1148 return pa; 1149 } 1150 #endif /* PCI_MAGIC_IO_RANGE */ 1151 1152 #endif /* RADEONFB_MMAP_BARS */ 1153 1154 return -1; 1155 } 1156 1157 static void 1158 radeonfb_loadbios(struct radeonfb_softc *sc, const struct pci_attach_args *pa) 1159 { 1160 bus_space_tag_t romt; 1161 bus_space_handle_t romh, biosh; 1162 bus_size_t romsz; 1163 bus_addr_t ptr; 1164 1165 if (pci_mapreg_map(pa, PCI_MAPREG_ROM, PCI_MAPREG_TYPE_ROM, 1166 BUS_SPACE_MAP_PREFETCHABLE, &romt, &romh, NULL, &romsz) != 0) { 1167 aprint_verbose("%s: unable to map BIOS!\n", XNAME(sc)); 1168 return; 1169 } 1170 1171 pci_find_rom(pa, romt, romh, PCI_ROM_CODE_TYPE_X86, &biosh, 1172 &sc->sc_biossz); 1173 if (sc->sc_biossz == 0) { 1174 aprint_verbose("%s: Video BIOS not present\n", XNAME(sc)); 1175 return; 1176 } 1177 1178 sc->sc_bios = malloc(sc->sc_biossz, M_DEVBUF, M_WAITOK); 1179 bus_space_read_region_1(romt, biosh, 0, sc->sc_bios, sc->sc_biossz); 1180 1181 /* unmap the PCI expansion rom */ 1182 bus_space_unmap(romt, romh, romsz); 1183 1184 /* turn off rom decoder now */ 1185 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM, 1186 pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM) & 1187 ~PCI_MAPREG_ROM_ENABLE); 1188 1189 ptr = GETBIOS16(sc, 0x48); 1190 if ((GETBIOS32(sc, ptr + 4) == 0x41544f4d /* "ATOM" */) || 1191 (GETBIOS32(sc, ptr + 4) == 0x4d4f5441 /* "MOTA" */)) { 1192 sc->sc_flags |= RFB_ATOM; 1193 } 1194 1195 aprint_verbose("%s: Found %d KB %s BIOS\n", XNAME(sc), 1196 (unsigned)sc->sc_biossz >> 10, IS_ATOM(sc) ? "ATOM" : "Legacy"); 1197 } 1198 1199 1200 uint32_t 1201 radeonfb_get32(struct radeonfb_softc *sc, uint32_t reg) 1202 { 1203 1204 return bus_space_read_4(sc->sc_regt, sc->sc_regh, reg); 1205 } 1206 1207 void 1208 radeonfb_put32(struct radeonfb_softc *sc, uint32_t reg, uint32_t val) 1209 { 1210 1211 bus_space_write_4(sc->sc_regt, sc->sc_regh, reg, val); 1212 } 1213 1214 void 1215 radeonfb_mask32(struct radeonfb_softc *sc, uint32_t reg, 1216 uint32_t andmask, uint32_t ormask) 1217 { 1218 int s; 1219 uint32_t val; 1220 1221 s = splhigh(); 1222 val = radeonfb_get32(sc, reg); 1223 val = (val & andmask) | ormask; 1224 radeonfb_put32(sc, reg, val); 1225 splx(s); 1226 } 1227 1228 uint32_t 1229 radeonfb_getindex(struct radeonfb_softc *sc, uint32_t idx) 1230 { 1231 int s; 1232 uint32_t val; 1233 1234 s = splhigh(); 1235 radeonfb_put32(sc, RADEON_MM_INDEX, idx); 1236 val = radeonfb_get32(sc, RADEON_MM_DATA); 1237 splx(s); 1238 1239 return (val); 1240 } 1241 1242 void 1243 radeonfb_putindex(struct radeonfb_softc *sc, uint32_t idx, uint32_t val) 1244 { 1245 int s; 1246 1247 s = splhigh(); 1248 radeonfb_put32(sc, RADEON_MM_INDEX, idx); 1249 radeonfb_put32(sc, RADEON_MM_DATA, val); 1250 splx(s); 1251 } 1252 1253 void 1254 radeonfb_maskindex(struct radeonfb_softc *sc, uint32_t idx, 1255 uint32_t andmask, uint32_t ormask) 1256 { 1257 int s; 1258 uint32_t val; 1259 1260 s = splhigh(); 1261 radeonfb_put32(sc, RADEON_MM_INDEX, idx); 1262 val = radeonfb_get32(sc, RADEON_MM_DATA); 1263 val = (val & andmask) | ormask; 1264 radeonfb_put32(sc, RADEON_MM_DATA, val); 1265 splx(s); 1266 } 1267 1268 uint32_t 1269 radeonfb_getpll(struct radeonfb_softc *sc, uint32_t idx) 1270 { 1271 int s; 1272 uint32_t val; 1273 1274 s = splhigh(); 1275 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, idx & 0x3f); 1276 val = radeonfb_get32(sc, RADEON_CLOCK_CNTL_DATA); 1277 if (HAS_R300CG(sc)) 1278 radeonfb_r300cg_workaround(sc); 1279 splx(s); 1280 1281 return (val); 1282 } 1283 1284 void 1285 radeonfb_putpll(struct radeonfb_softc *sc, uint32_t idx, uint32_t val) 1286 { 1287 int s; 1288 1289 s = splhigh(); 1290 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, (idx & 0x3f) | 1291 RADEON_PLL_WR_EN); 1292 radeonfb_put32(sc, RADEON_CLOCK_CNTL_DATA, val); 1293 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, 0); 1294 splx(s); 1295 } 1296 1297 void 1298 radeonfb_maskpll(struct radeonfb_softc *sc, uint32_t idx, 1299 uint32_t andmask, uint32_t ormask) 1300 { 1301 int s; 1302 uint32_t val; 1303 1304 s = splhigh(); 1305 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, (idx & 0x3f) | 1306 RADEON_PLL_WR_EN); 1307 val = radeonfb_get32(sc, RADEON_CLOCK_CNTL_DATA); 1308 val = (val & andmask) | ormask; 1309 radeonfb_put32(sc, RADEON_CLOCK_CNTL_DATA, val); 1310 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, 0); 1311 splx(s); 1312 } 1313 1314 int 1315 radeonfb_scratch_test(struct radeonfb_softc *sc, int reg, uint32_t v) 1316 { 1317 uint32_t saved; 1318 1319 saved = GET32(sc, reg); 1320 PUT32(sc, reg, v); 1321 if (GET32(sc, reg) != v) { 1322 return -1; 1323 } 1324 PUT32(sc, reg, saved); 1325 return 0; 1326 } 1327 1328 uintmax_t 1329 radeonfb_getprop_num(struct radeonfb_softc *sc, const char *name, 1330 uintmax_t defval) 1331 { 1332 prop_number_t pn; 1333 pn = prop_dictionary_get(device_properties(sc->sc_dev), name); 1334 if (pn == NULL) { 1335 return defval; 1336 } 1337 KASSERT(prop_object_type(pn) == PROP_TYPE_NUMBER); 1338 return (prop_number_integer_value(pn)); 1339 } 1340 1341 int 1342 radeonfb_getclocks(struct radeonfb_softc *sc) 1343 { 1344 bus_addr_t ptr; 1345 int refclk = 0; 1346 int refdiv = 0; 1347 int minpll = 0; 1348 int maxpll = 0; 1349 1350 /* load initial property values if port/board provides them */ 1351 refclk = radeonfb_getprop_num(sc, "refclk", 0) & 0xffff; 1352 refdiv = radeonfb_getprop_num(sc, "refdiv", 0) & 0xffff; 1353 minpll = radeonfb_getprop_num(sc, "minpll", 0) & 0xffffffffU; 1354 maxpll = radeonfb_getprop_num(sc, "maxpll", 0) & 0xffffffffU; 1355 1356 if (refclk && refdiv && minpll && maxpll) 1357 goto dontprobe; 1358 1359 if (!sc->sc_biossz) { 1360 /* no BIOS */ 1361 aprint_verbose("%s: No video BIOS, using default clocks\n", 1362 XNAME(sc)); 1363 if (IS_IGP(sc)) 1364 refclk = refclk ? refclk : 1432; 1365 else 1366 refclk = refclk ? refclk : 2700; 1367 refdiv = refdiv ? refdiv : 12; 1368 minpll = minpll ? minpll : 12500; 1369 maxpll = maxpll ? maxpll : 35000; 1370 } else if (IS_ATOM(sc)) { 1371 /* ATOM BIOS */ 1372 ptr = GETBIOS16(sc, 0x48); 1373 ptr = GETBIOS16(sc, ptr + 32); /* aka MasterDataStart */ 1374 ptr = GETBIOS16(sc, ptr + 12); /* pll info block */ 1375 refclk = refclk ? refclk : GETBIOS16(sc, ptr + 82); 1376 minpll = minpll ? minpll : GETBIOS16(sc, ptr + 78); 1377 maxpll = maxpll ? maxpll : GETBIOS16(sc, ptr + 32); 1378 /* 1379 * ATOM BIOS doesn't supply a reference divider, so we 1380 * have to probe for it. 1381 */ 1382 if (refdiv < 2) 1383 refdiv = GETPLL(sc, RADEON_PPLL_REF_DIV) & 1384 RADEON_PPLL_REF_DIV_MASK; 1385 /* 1386 * if probe is zero, just assume one that should work 1387 * for most parts 1388 */ 1389 if (refdiv < 2) 1390 refdiv = 12; 1391 1392 } else { 1393 /* Legacy BIOS */ 1394 ptr = GETBIOS16(sc, 0x48); 1395 ptr = GETBIOS16(sc, ptr + 0x30); 1396 refclk = refclk ? refclk : GETBIOS16(sc, ptr + 0x0E); 1397 refdiv = refdiv ? refdiv : GETBIOS16(sc, ptr + 0x10); 1398 minpll = minpll ? minpll : GETBIOS32(sc, ptr + 0x12); 1399 maxpll = maxpll ? maxpll : GETBIOS32(sc, ptr + 0x16); 1400 } 1401 1402 1403 dontprobe: 1404 sc->sc_refclk = refclk * 10; 1405 sc->sc_refdiv = refdiv; 1406 sc->sc_minpll = minpll * 10; 1407 sc->sc_maxpll = maxpll * 10; 1408 return 0; 1409 } 1410 1411 int 1412 radeonfb_calc_dividers(struct radeonfb_softc *sc, uint32_t dotclock, 1413 uint32_t *postdivbit, uint32_t *feedbackdiv) 1414 { 1415 int i; 1416 uint32_t outfreq; 1417 int div; 1418 1419 DPRINTF(("dot clock: %u\n", dotclock)); 1420 for (i = 0; (div = radeonfb_dividers[i].divider) != 0; i++) { 1421 outfreq = div * dotclock; 1422 if ((outfreq >= sc->sc_minpll) && 1423 (outfreq <= sc->sc_maxpll)) { 1424 DPRINTF(("outfreq: %u\n", outfreq)); 1425 *postdivbit = 1426 ((uint32_t)radeonfb_dividers[i].mask << 16); 1427 DPRINTF(("post divider: %d (mask %x)\n", div, 1428 *postdivbit)); 1429 break; 1430 } 1431 } 1432 1433 if (div == 0) 1434 return 1; 1435 1436 *feedbackdiv = DIVIDE(sc->sc_refdiv * outfreq, sc->sc_refclk); 1437 DPRINTF(("feedback divider: %d\n", *feedbackdiv)); 1438 return 0; 1439 } 1440 1441 #if 0 1442 #ifdef RADEONFB_DEBUG 1443 static void 1444 dump_buffer(const char *pfx, void *buffer, unsigned int size) 1445 { 1446 char asc[17]; 1447 unsigned ptr = (unsigned)buffer; 1448 char *start = (char *)(ptr & ~0xf); 1449 char *end = (char *)(ptr + size); 1450 1451 end = (char *)(((unsigned)end + 0xf) & ~0xf); 1452 1453 if (pfx == NULL) { 1454 pfx = ""; 1455 } 1456 1457 while (start < end) { 1458 unsigned offset = (unsigned)start & 0xf; 1459 if (offset == 0) { 1460 printf("%s%x: ", pfx, (unsigned)start); 1461 } 1462 if (((unsigned)start < ptr) || 1463 ((unsigned)start >= (ptr + size))) { 1464 printf(" "); 1465 asc[offset] = ' '; 1466 } else { 1467 printf("%02x", *(unsigned char *)start); 1468 if ((*start >= ' ') && (*start <= '~')) { 1469 asc[offset] = *start; 1470 } else { 1471 asc[offset] = '.'; 1472 } 1473 } 1474 asc[offset + 1] = 0; 1475 if (offset % 2) { 1476 printf(" "); 1477 } 1478 if (offset == 15) { 1479 printf(" %s\n", asc); 1480 } 1481 start++; 1482 } 1483 } 1484 #endif 1485 #endif 1486 1487 int 1488 radeonfb_getconnectors(struct radeonfb_softc *sc) 1489 { 1490 int i; 1491 int found = 0; 1492 1493 for (i = 0; i < 2; i++) { 1494 sc->sc_ports[i].rp_mon_type = RADEON_MT_UNKNOWN; 1495 sc->sc_ports[i].rp_ddc_type = RADEON_DDC_NONE; 1496 sc->sc_ports[i].rp_dac_type = RADEON_DAC_UNKNOWN; 1497 sc->sc_ports[i].rp_conn_type = RADEON_CONN_NONE; 1498 sc->sc_ports[i].rp_tmds_type = RADEON_TMDS_UNKNOWN; 1499 } 1500 1501 /* 1502 * This logic is borrowed from Xorg's radeon driver. 1503 */ 1504 if (!sc->sc_biossz) 1505 goto nobios; 1506 1507 if (IS_ATOM(sc)) { 1508 /* not done yet */ 1509 } else { 1510 uint16_t ptr; 1511 int port = 0; 1512 1513 ptr = GETBIOS16(sc, 0x48); 1514 ptr = GETBIOS16(sc, ptr + 0x50); 1515 for (i = 1; i < 4; i++) { 1516 uint16_t entry; 1517 uint8_t conn, ddc, dac, tmds; 1518 1519 /* 1520 * Parse the connector table. From reading the code, 1521 * it appears to made up of 16-bit entries for each 1522 * connector. The 16-bits are defined as: 1523 * 1524 * bits 12-15 - connector type (0 == end of table) 1525 * bits 8-11 - DDC type 1526 * bits 5-7 - ??? 1527 * bit 4 - TMDS type (1 = EXT, 0 = INT) 1528 * bits 1-3 - ??? 1529 * bit 0 - DAC, 1 = TVDAC, 0 = primary 1530 */ 1531 if (!GETBIOS8(sc, ptr + i * 2) && i > 1) 1532 break; 1533 entry = GETBIOS16(sc, ptr + i * 2); 1534 1535 conn = (entry >> 12) & 0xf; 1536 ddc = (entry >> 8) & 0xf; 1537 dac = (entry & 0x1) ? RADEON_DAC_TVDAC : 1538 RADEON_DAC_PRIMARY; 1539 tmds = ((entry >> 4) & 0x1) ? RADEON_TMDS_EXT : 1540 RADEON_TMDS_INT; 1541 1542 if (conn == RADEON_CONN_NONE) 1543 continue; /* no connector */ 1544 1545 if ((found > 0) && 1546 (sc->sc_ports[port].rp_ddc_type == ddc)) { 1547 /* duplicate entry for same connector */ 1548 continue; 1549 } 1550 1551 /* internal DDC_DVI port gets priority */ 1552 if ((ddc == RADEON_DDC_DVI) || (port == 1)) 1553 port = 0; 1554 else 1555 port = 1; 1556 1557 sc->sc_ports[port].rp_ddc_type = 1558 ddc > RADEON_DDC_CRT2 ? RADEON_DDC_NONE : ddc; 1559 sc->sc_ports[port].rp_dac_type = dac; 1560 sc->sc_ports[port].rp_conn_type = 1561 min(conn, RADEON_CONN_UNSUPPORTED) ; 1562 1563 sc->sc_ports[port].rp_tmds_type = tmds; 1564 1565 if ((conn != RADEON_CONN_DVI_I) && 1566 (conn != RADEON_CONN_DVI_D) && 1567 (tmds == RADEON_TMDS_INT)) 1568 sc->sc_ports[port].rp_tmds_type = 1569 RADEON_TMDS_UNKNOWN; 1570 1571 found += (port + 1); 1572 } 1573 } 1574 1575 nobios: 1576 if (!found) { 1577 DPRINTF(("No connector info in BIOS!\n")); 1578 /* default, port 0 = internal TMDS, port 1 = CRT */ 1579 sc->sc_ports[0].rp_mon_type = RADEON_MT_UNKNOWN; 1580 sc->sc_ports[0].rp_ddc_type = RADEON_DDC_DVI; 1581 sc->sc_ports[0].rp_dac_type = RADEON_DAC_TVDAC; 1582 sc->sc_ports[0].rp_conn_type = RADEON_CONN_DVI_D; 1583 sc->sc_ports[0].rp_tmds_type = RADEON_TMDS_INT; 1584 1585 sc->sc_ports[1].rp_mon_type = RADEON_MT_UNKNOWN; 1586 sc->sc_ports[1].rp_ddc_type = RADEON_DDC_VGA; 1587 sc->sc_ports[1].rp_dac_type = RADEON_DAC_PRIMARY; 1588 sc->sc_ports[1].rp_conn_type = RADEON_CONN_CRT; 1589 sc->sc_ports[1].rp_tmds_type = RADEON_TMDS_EXT; 1590 } 1591 1592 /* 1593 * Fixup for RS300/RS350/RS400 chips, that lack a primary DAC. 1594 * these chips should use TVDAC for the VGA port. 1595 */ 1596 if (HAS_SDAC(sc)) { 1597 if (sc->sc_ports[0].rp_conn_type == RADEON_CONN_CRT) { 1598 sc->sc_ports[0].rp_dac_type = RADEON_DAC_TVDAC; 1599 sc->sc_ports[1].rp_dac_type = RADEON_DAC_PRIMARY; 1600 } else { 1601 sc->sc_ports[1].rp_dac_type = RADEON_DAC_TVDAC; 1602 sc->sc_ports[0].rp_dac_type = RADEON_DAC_PRIMARY; 1603 } 1604 } else if (!HAS_CRTC2(sc)) { 1605 sc->sc_ports[0].rp_dac_type = RADEON_DAC_PRIMARY; 1606 } 1607 1608 for (i = 0; i < 2; i++) { 1609 char edid[128]; 1610 uint8_t ddc; 1611 struct edid_info *eip = &sc->sc_ports[i].rp_edid; 1612 prop_data_t edid_data; 1613 1614 DPRINTF(("Port #%d:\n", i)); 1615 DPRINTF((" conn = %d\n", sc->sc_ports[i].rp_conn_type)); 1616 DPRINTF((" ddc = %d\n", sc->sc_ports[i].rp_ddc_type)); 1617 DPRINTF((" dac = %d\n", sc->sc_ports[i].rp_dac_type)); 1618 DPRINTF((" tmds = %d\n", sc->sc_ports[i].rp_tmds_type)); 1619 1620 sc->sc_ports[i].rp_edid_valid = 0; 1621 /* first look for static EDID data */ 1622 if ((edid_data = prop_dictionary_get(device_properties( 1623 sc->sc_dev), "EDID")) != NULL) { 1624 1625 aprint_normal_dev(sc->sc_dev, "using static EDID\n"); 1626 memcpy(edid, prop_data_data_nocopy(edid_data), 128); 1627 if (edid_parse(edid, eip) == 0) { 1628 1629 sc->sc_ports[i].rp_edid_valid = 1; 1630 } 1631 } 1632 /* if we didn't find any we'll try to talk to the monitor */ 1633 if (sc->sc_ports[i].rp_edid_valid != 1) { 1634 1635 ddc = sc->sc_ports[i].rp_ddc_type; 1636 if (ddc != RADEON_DDC_NONE) { 1637 if ((radeonfb_i2c_read_edid(sc, ddc, edid) 1638 == 0) && (edid_parse(edid, eip) == 0)) { 1639 1640 sc->sc_ports[i].rp_edid_valid = 1; 1641 edid_print(eip); 1642 } 1643 } 1644 } 1645 } 1646 1647 return found; 1648 } 1649 1650 int 1651 radeonfb_gettmds(struct radeonfb_softc *sc) 1652 { 1653 int i; 1654 1655 if (!sc->sc_biossz) { 1656 goto nobios; 1657 } 1658 1659 if (IS_ATOM(sc)) { 1660 /* XXX: not done yet */ 1661 } else { 1662 uint16_t ptr; 1663 int n; 1664 1665 ptr = GETBIOS16(sc, 0x48); 1666 ptr = GETBIOS16(sc, ptr + 0x34); 1667 DPRINTF(("DFP table revision %d\n", GETBIOS8(sc, ptr))); 1668 if (GETBIOS8(sc, ptr) == 3) { 1669 /* revision three table */ 1670 n = GETBIOS8(sc, ptr + 5) + 1; 1671 n = min(n, 4); 1672 1673 memset(sc->sc_tmds_pll, 0, sizeof (sc->sc_tmds_pll)); 1674 for (i = 0; i < n; i++) { 1675 sc->sc_tmds_pll[i].rtp_pll = GETBIOS32(sc, 1676 ptr + i * 10 + 8); 1677 sc->sc_tmds_pll[i].rtp_freq = GETBIOS16(sc, 1678 ptr + i * 10 + 0x10); 1679 DPRINTF(("TMDS_PLL dot clock %d pll %x\n", 1680 sc->sc_tmds_pll[i].rtp_freq, 1681 sc->sc_tmds_pll[i].rtp_pll)); 1682 } 1683 return 0; 1684 } 1685 } 1686 1687 nobios: 1688 DPRINTF(("no suitable DFP table present\n")); 1689 for (i = 0; 1690 i < sizeof (radeonfb_tmds_pll) / sizeof (radeonfb_tmds_pll[0]); 1691 i++) { 1692 int j; 1693 1694 if (radeonfb_tmds_pll[i].family != sc->sc_family) 1695 continue; 1696 1697 for (j = 0; j < 4; j++) { 1698 sc->sc_tmds_pll[j] = radeonfb_tmds_pll[i].plls[j]; 1699 DPRINTF(("TMDS_PLL dot clock %d pll %x\n", 1700 sc->sc_tmds_pll[j].rtp_freq, 1701 sc->sc_tmds_pll[j].rtp_pll)); 1702 } 1703 return 0; 1704 } 1705 1706 return -1; 1707 } 1708 1709 const struct videomode * 1710 radeonfb_modelookup(const char *name) 1711 { 1712 int i; 1713 1714 for (i = 0; i < videomode_count; i++) 1715 if (!strcmp(name, videomode_list[i].name)) 1716 return &videomode_list[i]; 1717 1718 return NULL; 1719 } 1720 1721 void 1722 radeonfb_pllwriteupdate(struct radeonfb_softc *sc, int crtc) 1723 { 1724 if (crtc) { 1725 while (GETPLL(sc, RADEON_P2PLL_REF_DIV) & 1726 RADEON_P2PLL_ATOMIC_UPDATE_R); 1727 SETPLL(sc, RADEON_P2PLL_REF_DIV, RADEON_P2PLL_ATOMIC_UPDATE_W); 1728 } else { 1729 while (GETPLL(sc, RADEON_PPLL_REF_DIV) & 1730 RADEON_PPLL_ATOMIC_UPDATE_R); 1731 SETPLL(sc, RADEON_PPLL_REF_DIV, RADEON_PPLL_ATOMIC_UPDATE_W); 1732 } 1733 } 1734 1735 void 1736 radeonfb_pllwaitatomicread(struct radeonfb_softc *sc, int crtc) 1737 { 1738 int i; 1739 1740 for (i = 10000; i; i--) { 1741 if (crtc) { 1742 if (GETPLL(sc, RADEON_P2PLL_REF_DIV) & 1743 RADEON_P2PLL_ATOMIC_UPDATE_R) 1744 break; 1745 } else { 1746 if (GETPLL(sc, RADEON_PPLL_REF_DIV) & 1747 RADEON_PPLL_ATOMIC_UPDATE_R) 1748 break; 1749 } 1750 } 1751 } 1752 1753 void 1754 radeonfb_program_vclk(struct radeonfb_softc *sc, int dotclock, int crtc) 1755 { 1756 uint32_t pbit = 0; 1757 uint32_t feed = 0; 1758 uint32_t data; 1759 #if 1 1760 int i; 1761 #endif 1762 1763 radeonfb_calc_dividers(sc, dotclock, &pbit, &feed); 1764 1765 if (crtc == 0) { 1766 1767 /* XXXX: mobility workaround missing */ 1768 /* XXXX: R300 stuff missing */ 1769 1770 PATCHPLL(sc, RADEON_VCLK_ECP_CNTL, 1771 RADEON_VCLK_SRC_SEL_CPUCLK, 1772 ~RADEON_VCLK_SRC_SEL_MASK); 1773 1774 /* put vclk into reset, use atomic updates */ 1775 SETPLL(sc, RADEON_PPLL_CNTL, 1776 RADEON_PPLL_REFCLK_SEL | 1777 RADEON_PPLL_FBCLK_SEL | 1778 RADEON_PPLL_RESET | 1779 RADEON_PPLL_ATOMIC_UPDATE_EN | 1780 RADEON_PPLL_VGA_ATOMIC_UPDATE_EN); 1781 1782 /* select clock 3 */ 1783 #if 0 1784 PATCH32(sc, RADEON_CLOCK_CNTL_INDEX, RADEON_PLL_DIV_SEL, 1785 ~RADEON_PLL_DIV_SEL); 1786 #else 1787 PATCH32(sc, RADEON_CLOCK_CNTL_INDEX, 0, 1788 ~RADEON_PLL_DIV_SEL); 1789 #endif 1790 1791 /* XXX: R300 family -- program divider differently? */ 1792 1793 /* program reference divider */ 1794 PATCHPLL(sc, RADEON_PPLL_REF_DIV, sc->sc_refdiv, 1795 ~RADEON_PPLL_REF_DIV_MASK); 1796 PRINTPLL(RADEON_PPLL_REF_DIV); 1797 1798 #if 0 1799 data = GETPLL(sc, RADEON_PPLL_DIV_3); 1800 data &= ~(RADEON_PPLL_FB3_DIV_MASK | 1801 RADEON_PPLL_POST3_DIV_MASK); 1802 data |= pbit; 1803 data |= (feed & RADEON_PPLL_FB3_DIV_MASK); 1804 PUTPLL(sc, RADEON_PPLL_DIV_3, data); 1805 #else 1806 for (i = 0; i < 4; i++) { 1807 } 1808 #endif 1809 1810 /* use the atomic update */ 1811 radeonfb_pllwriteupdate(sc, crtc); 1812 1813 /* and wait for it to complete */ 1814 radeonfb_pllwaitatomicread(sc, crtc); 1815 1816 /* program HTOTAL (why?) */ 1817 PUTPLL(sc, RADEON_HTOTAL_CNTL, 0); 1818 1819 /* drop reset */ 1820 CLRPLL(sc, RADEON_PPLL_CNTL, 1821 RADEON_PPLL_RESET | RADEON_PPLL_SLEEP | 1822 RADEON_PPLL_ATOMIC_UPDATE_EN | 1823 RADEON_PPLL_VGA_ATOMIC_UPDATE_EN); 1824 1825 PRINTPLL(RADEON_PPLL_CNTL); 1826 1827 /* give clock time to lock */ 1828 delay(50000); 1829 1830 PATCHPLL(sc, RADEON_VCLK_ECP_CNTL, 1831 RADEON_VCLK_SRC_SEL_PPLLCLK, 1832 ~RADEON_VCLK_SRC_SEL_MASK); 1833 1834 } else { 1835 1836 PATCHPLL(sc, RADEON_PIXCLKS_CNTL, 1837 RADEON_PIX2CLK_SRC_SEL_CPUCLK, 1838 ~RADEON_PIX2CLK_SRC_SEL_MASK); 1839 1840 /* put vclk into reset, use atomic updates */ 1841 SETPLL(sc, RADEON_P2PLL_CNTL, 1842 RADEON_P2PLL_RESET | 1843 RADEON_P2PLL_ATOMIC_UPDATE_EN | 1844 RADEON_P2PLL_VGA_ATOMIC_UPDATE_EN); 1845 1846 /* XXX: R300 family -- program divider differently? */ 1847 1848 /* program reference divider */ 1849 PATCHPLL(sc, RADEON_P2PLL_REF_DIV, sc->sc_refdiv, 1850 ~RADEON_P2PLL_REF_DIV_MASK); 1851 1852 /* program feedback and post dividers */ 1853 data = GETPLL(sc, RADEON_P2PLL_DIV_0); 1854 data &= ~(RADEON_P2PLL_FB0_DIV_MASK | 1855 RADEON_P2PLL_POST0_DIV_MASK); 1856 data |= pbit; 1857 data |= (feed & RADEON_P2PLL_FB0_DIV_MASK); 1858 PUTPLL(sc, RADEON_P2PLL_DIV_0, data); 1859 1860 /* use the atomic update */ 1861 radeonfb_pllwriteupdate(sc, crtc); 1862 1863 /* and wait for it to complete */ 1864 radeonfb_pllwaitatomicread(sc, crtc); 1865 1866 /* program HTOTAL (why?) */ 1867 PUTPLL(sc, RADEON_HTOTAL2_CNTL, 0); 1868 1869 /* drop reset */ 1870 CLRPLL(sc, RADEON_P2PLL_CNTL, 1871 RADEON_P2PLL_RESET | RADEON_P2PLL_SLEEP | 1872 RADEON_P2PLL_ATOMIC_UPDATE_EN | 1873 RADEON_P2PLL_VGA_ATOMIC_UPDATE_EN); 1874 1875 /* allow time for clock to lock */ 1876 delay(50000); 1877 1878 PATCHPLL(sc, RADEON_PIXCLKS_CNTL, 1879 RADEON_PIX2CLK_SRC_SEL_P2PLLCLK, 1880 ~RADEON_PIX2CLK_SRC_SEL_MASK); 1881 } 1882 PRINTREG(RADEON_CRTC_MORE_CNTL); 1883 } 1884 1885 void 1886 radeonfb_modeswitch(struct radeonfb_display *dp) 1887 { 1888 struct radeonfb_softc *sc = dp->rd_softc; 1889 int i; 1890 1891 /* blank the display while we switch modes */ 1892 radeonfb_blank(dp, 1); 1893 1894 #if 0 1895 SET32(sc, RADEON_CRTC_EXT_CNTL, 1896 RADEON_CRTC_VSYNC_DIS | RADEON_CRTC_HSYNC_DIS | 1897 RADEON_CRTC_DISPLAY_DIS /* | RADEON_CRTC_DISP_REQ_EN_B */); 1898 #endif 1899 1900 /* these registers might get in the way... */ 1901 PUT32(sc, RADEON_OVR_CLR, 0); 1902 PUT32(sc, RADEON_OVR_WID_LEFT_RIGHT, 0); 1903 PUT32(sc, RADEON_OVR_WID_TOP_BOTTOM, 0); 1904 PUT32(sc, RADEON_OV0_SCALE_CNTL, 0); 1905 PUT32(sc, RADEON_SUBPIC_CNTL, 0); 1906 PUT32(sc, RADEON_VIPH_CONTROL, 0); 1907 PUT32(sc, RADEON_I2C_CNTL_1, 0); 1908 PUT32(sc, RADEON_GEN_INT_CNTL, 0); 1909 PUT32(sc, RADEON_CAP0_TRIG_CNTL, 0); 1910 PUT32(sc, RADEON_CAP1_TRIG_CNTL, 0); 1911 PUT32(sc, RADEON_SURFACE_CNTL, 0); 1912 1913 for (i = 0; i < dp->rd_ncrtcs; i++) 1914 radeonfb_setcrtc(dp, i); 1915 1916 /* activate the display */ 1917 radeonfb_blank(dp, 0); 1918 } 1919 1920 void 1921 radeonfb_setcrtc(struct radeonfb_display *dp, int index) 1922 { 1923 int crtc; 1924 struct videomode *mode; 1925 struct radeonfb_softc *sc; 1926 struct radeonfb_crtc *cp; 1927 uint32_t v; 1928 uint32_t gencntl; 1929 uint32_t htotaldisp; 1930 uint32_t hsyncstrt; 1931 uint32_t vtotaldisp; 1932 uint32_t vsyncstrt; 1933 uint32_t fphsyncstrt; 1934 uint32_t fpvsyncstrt; 1935 uint32_t fphtotaldisp; 1936 uint32_t fpvtotaldisp; 1937 uint32_t pitch; 1938 1939 sc = dp->rd_softc; 1940 cp = &dp->rd_crtcs[index]; 1941 crtc = cp->rc_number; 1942 mode = &cp->rc_videomode; 1943 1944 #if 1 1945 pitch = (((dp->rd_virtx * dp->rd_bpp) + ((dp->rd_bpp * 8) - 1)) / 1946 (dp->rd_bpp * 8)); 1947 #else 1948 pitch = (((sc->sc_maxx * sc->sc_maxbpp) + ((sc->sc_maxbpp * 8) - 1)) / 1949 (sc->sc_maxbpp * 8)); 1950 #endif 1951 1952 switch (crtc) { 1953 case 0: 1954 gencntl = RADEON_CRTC_GEN_CNTL; 1955 htotaldisp = RADEON_CRTC_H_TOTAL_DISP; 1956 hsyncstrt = RADEON_CRTC_H_SYNC_STRT_WID; 1957 vtotaldisp = RADEON_CRTC_V_TOTAL_DISP; 1958 vsyncstrt = RADEON_CRTC_V_SYNC_STRT_WID; 1959 fpvsyncstrt = RADEON_FP_V_SYNC_STRT_WID; 1960 fphsyncstrt = RADEON_FP_H_SYNC_STRT_WID; 1961 fpvtotaldisp = RADEON_FP_CRTC_V_TOTAL_DISP; 1962 fphtotaldisp = RADEON_FP_CRTC_H_TOTAL_DISP; 1963 break; 1964 case 1: 1965 gencntl = RADEON_CRTC2_GEN_CNTL; 1966 htotaldisp = RADEON_CRTC2_H_TOTAL_DISP; 1967 hsyncstrt = RADEON_CRTC2_H_SYNC_STRT_WID; 1968 vtotaldisp = RADEON_CRTC2_V_TOTAL_DISP; 1969 vsyncstrt = RADEON_CRTC2_V_SYNC_STRT_WID; 1970 fpvsyncstrt = RADEON_FP_V2_SYNC_STRT_WID; 1971 fphsyncstrt = RADEON_FP_H2_SYNC_STRT_WID; 1972 fpvtotaldisp = RADEON_FP_CRTC2_V_TOTAL_DISP; 1973 fphtotaldisp = RADEON_FP_CRTC2_H_TOTAL_DISP; 1974 break; 1975 default: 1976 panic("Bad CRTC!"); 1977 break; 1978 } 1979 1980 /* 1981 * CRTC_GEN_CNTL - depth, accelerator mode, etc. 1982 */ 1983 /* only bother with 32bpp and 8bpp */ 1984 v = dp->rd_format << RADEON_CRTC_PIX_WIDTH_SHIFT; 1985 1986 if (crtc == 1) { 1987 v |= RADEON_CRTC2_CRT2_ON | RADEON_CRTC2_EN; 1988 } else { 1989 v |= RADEON_CRTC_EXT_DISP_EN | RADEON_CRTC_EN; 1990 } 1991 1992 if (mode->flags & VID_DBLSCAN) 1993 v |= RADEON_CRTC2_DBL_SCAN_EN; 1994 1995 if (mode->flags & VID_INTERLACE) 1996 v |= RADEON_CRTC2_INTERLACE_EN; 1997 1998 if (mode->flags & VID_CSYNC) { 1999 v |= RADEON_CRTC2_CSYNC_EN; 2000 if (crtc == 1) 2001 v |= RADEON_CRTC2_VSYNC_TRISTAT; 2002 } 2003 2004 PUT32(sc, gencntl, v); 2005 DPRINTF(("CRTC%s_GEN_CNTL = %08x\n", crtc ? "2" : "", v)); 2006 2007 /* 2008 * CRTC_EXT_CNTL - preserve disable flags, set ATI linear and EXT_CNT 2009 */ 2010 v = GET32(sc, RADEON_CRTC_EXT_CNTL); 2011 if (crtc == 0) { 2012 v &= (RADEON_CRTC_VSYNC_DIS | RADEON_CRTC_HSYNC_DIS | 2013 RADEON_CRTC_DISPLAY_DIS); 2014 v |= RADEON_XCRT_CNT_EN | RADEON_VGA_ATI_LINEAR; 2015 if (mode->flags & VID_CSYNC) 2016 v |= RADEON_CRTC_VSYNC_TRISTAT; 2017 } 2018 /* unconditional turn on CRT, in case first CRTC is DFP */ 2019 v |= RADEON_CRTC_CRT_ON; 2020 PUT32(sc, RADEON_CRTC_EXT_CNTL, v); 2021 PRINTREG(RADEON_CRTC_EXT_CNTL); 2022 2023 /* 2024 * H_TOTAL_DISP 2025 */ 2026 v = ((mode->hdisplay / 8) - 1) << 16; 2027 v |= (mode->htotal / 8) - 1; 2028 PUT32(sc, htotaldisp, v); 2029 DPRINTF(("CRTC%s_H_TOTAL_DISP = %08x\n", crtc ? "2" : "", v)); 2030 PUT32(sc, fphtotaldisp, v); 2031 DPRINTF(("FP_H%s_TOTAL_DISP = %08x\n", crtc ? "2" : "", v)); 2032 2033 /* 2034 * H_SYNC_STRT_WID 2035 */ 2036 v = (((mode->hsync_end - mode->hsync_start) / 8) << 16); 2037 v |= mode->hsync_start; 2038 if (mode->flags & VID_NHSYNC) 2039 v |= RADEON_CRTC_H_SYNC_POL; 2040 PUT32(sc, hsyncstrt, v); 2041 DPRINTF(("CRTC%s_H_SYNC_STRT_WID = %08x\n", crtc ? "2" : "", v)); 2042 PUT32(sc, fphsyncstrt, v); 2043 DPRINTF(("FP_H%s_SYNC_STRT_WID = %08x\n", crtc ? "2" : "", v)); 2044 2045 /* 2046 * V_TOTAL_DISP 2047 */ 2048 v = ((mode->vdisplay - 1) << 16); 2049 v |= (mode->vtotal - 1); 2050 PUT32(sc, vtotaldisp, v); 2051 DPRINTF(("CRTC%s_V_TOTAL_DISP = %08x\n", crtc ? "2" : "", v)); 2052 PUT32(sc, fpvtotaldisp, v); 2053 DPRINTF(("FP_V%s_TOTAL_DISP = %08x\n", crtc ? "2" : "", v)); 2054 2055 /* 2056 * V_SYNC_STRT_WID 2057 */ 2058 v = ((mode->vsync_end - mode->vsync_start) << 16); 2059 v |= (mode->vsync_start - 1); 2060 if (mode->flags & VID_NVSYNC) 2061 v |= RADEON_CRTC_V_SYNC_POL; 2062 PUT32(sc, vsyncstrt, v); 2063 DPRINTF(("CRTC%s_V_SYNC_STRT_WID = %08x\n", crtc ? "2" : "", v)); 2064 PUT32(sc, fpvsyncstrt, v); 2065 DPRINTF(("FP_V%s_SYNC_STRT_WID = %08x\n", crtc ? "2" : "", v)); 2066 2067 radeonfb_program_vclk(sc, mode->dot_clock, crtc); 2068 2069 switch (crtc) { 2070 case 0: 2071 PUT32(sc, RADEON_CRTC_OFFSET, 0); 2072 PUT32(sc, RADEON_CRTC_OFFSET_CNTL, 0); 2073 PUT32(sc, RADEON_CRTC_PITCH, pitch); 2074 CLR32(sc, RADEON_DISP_MERGE_CNTL, RADEON_DISP_RGB_OFFSET_EN); 2075 2076 CLR32(sc, RADEON_CRTC_EXT_CNTL, 2077 RADEON_CRTC_VSYNC_DIS | RADEON_CRTC_HSYNC_DIS | 2078 RADEON_CRTC_DISPLAY_DIS /* | RADEON_CRTC_DISP_REQ_EN_B */); 2079 CLR32(sc, RADEON_CRTC_GEN_CNTL, RADEON_CRTC_DISP_REQ_EN_B); 2080 PRINTREG(RADEON_CRTC_EXT_CNTL); 2081 PRINTREG(RADEON_CRTC_GEN_CNTL); 2082 PRINTREG(RADEON_CLOCK_CNTL_INDEX); 2083 break; 2084 2085 case 1: 2086 PUT32(sc, RADEON_CRTC2_OFFSET, 0); 2087 PUT32(sc, RADEON_CRTC2_OFFSET_CNTL, 0); 2088 PUT32(sc, RADEON_CRTC2_PITCH, pitch); 2089 CLR32(sc, RADEON_DISP2_MERGE_CNTL, RADEON_DISP2_RGB_OFFSET_EN); 2090 CLR32(sc, RADEON_CRTC2_GEN_CNTL, 2091 RADEON_CRTC2_VSYNC_DIS | 2092 RADEON_CRTC2_HSYNC_DIS | 2093 RADEON_CRTC2_DISP_DIS | RADEON_CRTC2_DISP_REQ_EN_B); 2094 PRINTREG(RADEON_CRTC2_GEN_CNTL); 2095 break; 2096 } 2097 } 2098 2099 int 2100 radeonfb_isblank(struct radeonfb_display *dp) 2101 { 2102 uint32_t reg, mask; 2103 2104 if (dp->rd_crtcs[0].rc_number) { 2105 reg = RADEON_CRTC2_GEN_CNTL; 2106 mask = RADEON_CRTC2_DISP_DIS; 2107 } else { 2108 reg = RADEON_CRTC_EXT_CNTL; 2109 mask = RADEON_CRTC_DISPLAY_DIS; 2110 } 2111 return ((GET32(dp->rd_softc, reg) & mask) ? 1 : 0); 2112 } 2113 2114 void 2115 radeonfb_blank(struct radeonfb_display *dp, int blank) 2116 { 2117 struct radeonfb_softc *sc = dp->rd_softc; 2118 uint32_t reg, mask; 2119 uint32_t fpreg, fpval; 2120 int i; 2121 2122 for (i = 0; i < dp->rd_ncrtcs; i++) { 2123 2124 if (dp->rd_crtcs[i].rc_number) { 2125 reg = RADEON_CRTC2_GEN_CNTL; 2126 mask = RADEON_CRTC2_DISP_DIS; 2127 fpreg = RADEON_FP2_GEN_CNTL; 2128 fpval = RADEON_FP2_ON; 2129 } else { 2130 reg = RADEON_CRTC_EXT_CNTL; 2131 mask = RADEON_CRTC_DISPLAY_DIS; 2132 fpreg = RADEON_FP_GEN_CNTL; 2133 fpval = RADEON_FP_FPON; 2134 } 2135 2136 if (blank) { 2137 SET32(sc, reg, mask); 2138 CLR32(sc, fpreg, fpval); 2139 } else { 2140 CLR32(sc, reg, mask); 2141 SET32(sc, fpreg, fpval); 2142 } 2143 } 2144 PRINTREG(RADEON_FP_GEN_CNTL); 2145 PRINTREG(RADEON_FP2_GEN_CNTL); 2146 } 2147 2148 void 2149 radeonfb_init_screen(void *cookie, struct vcons_screen *scr, int existing, 2150 long *defattr) 2151 { 2152 struct radeonfb_display *dp = cookie; 2153 struct rasops_info *ri = &scr->scr_ri; 2154 2155 /* initialize font subsystem */ 2156 wsfont_init(); 2157 2158 DPRINTF(("init screen called, existing %d\n", existing)); 2159 2160 ri->ri_depth = dp->rd_bpp; 2161 ri->ri_width = dp->rd_virtx; 2162 ri->ri_height = dp->rd_virty; 2163 ri->ri_stride = dp->rd_stride; 2164 ri->ri_flg = RI_CENTER; 2165 if (ri->ri_depth == 32) { 2166 ri->ri_flg |= RI_ENABLE_ALPHA; 2167 } 2168 ri->ri_bits = (void *)dp->rd_fbptr; 2169 2170 #ifdef VCONS_DRAW_INTR 2171 scr->scr_flags |= VCONS_DONT_READ; 2172 #endif 2173 2174 /* this is rgb in "big-endian order..." */ 2175 ri->ri_rnum = 8; 2176 ri->ri_gnum = 8; 2177 ri->ri_bnum = 8; 2178 ri->ri_rpos = 16; 2179 ri->ri_gpos = 8; 2180 ri->ri_bpos = 0; 2181 2182 if (existing) { 2183 ri->ri_flg |= RI_CLEAR; 2184 2185 /* start a modeswitch now */ 2186 radeonfb_modeswitch(dp); 2187 } 2188 2189 /* 2190 * XXX: font selection should be based on properties, with some 2191 * normal/reasonable default. 2192 */ 2193 2194 /* initialize and look for an initial font */ 2195 rasops_init(ri, 0, 0); 2196 ri->ri_caps = WSSCREEN_WSCOLORS; 2197 2198 rasops_reconfig(ri, dp->rd_virty / ri->ri_font->fontheight, 2199 dp->rd_virtx / ri->ri_font->fontwidth); 2200 2201 /* enable acceleration */ 2202 dp->rd_putchar = ri->ri_ops.putchar; 2203 ri->ri_ops.copyrows = radeonfb_copyrows; 2204 ri->ri_ops.copycols = radeonfb_copycols; 2205 ri->ri_ops.eraserows = radeonfb_eraserows; 2206 ri->ri_ops.erasecols = radeonfb_erasecols; 2207 /* pick a putchar method based on font and Radeon model */ 2208 if (ri->ri_font->stride < ri->ri_font->fontwidth) { 2209 /* got a bitmap font */ 2210 if (IS_R300(dp->rd_softc)) { 2211 /* 2212 * radeonfb_putchar() doesn't work right on some R3xx 2213 * so we use software drawing here, the wrapper just 2214 * makes sure the engine is idle before scribbling 2215 * into vram 2216 */ 2217 ri->ri_ops.putchar = radeonfb_putchar_wrapper; 2218 } else { 2219 ri->ri_ops.putchar = radeonfb_putchar; 2220 } 2221 } else { 2222 /* got an alpha font */ 2223 ri->ri_ops.putchar = radeonfb_putchar_aa32; 2224 } 2225 ri->ri_ops.cursor = radeonfb_cursor; 2226 } 2227 2228 void 2229 radeonfb_set_fbloc(struct radeonfb_softc *sc) 2230 { 2231 uint32_t gen, ext, gen2 = 0; 2232 uint32_t agploc, aperbase, apersize, mcfbloc; 2233 2234 gen = GET32(sc, RADEON_CRTC_GEN_CNTL); 2235 ext = GET32(sc, RADEON_CRTC_EXT_CNTL); 2236 agploc = GET32(sc, RADEON_MC_AGP_LOCATION); 2237 aperbase = GET32(sc, RADEON_CONFIG_APER_0_BASE); 2238 apersize = GET32(sc, RADEON_CONFIG_APER_SIZE); 2239 2240 PUT32(sc, RADEON_CRTC_GEN_CNTL, gen | RADEON_CRTC_DISP_REQ_EN_B); 2241 PUT32(sc, RADEON_CRTC_EXT_CNTL, ext | RADEON_CRTC_DISPLAY_DIS); 2242 //PUT32(sc, RADEON_CRTC_GEN_CNTL, gen | RADEON_CRTC_DISPLAY_DIS); 2243 //PUT32(sc, RADEON_CRTC_EXT_CNTL, ext | RADEON_CRTC_DISP_REQ_EN_B); 2244 2245 if (HAS_CRTC2(sc)) { 2246 gen2 = GET32(sc, RADEON_CRTC2_GEN_CNTL); 2247 PUT32(sc, RADEON_CRTC2_GEN_CNTL, 2248 gen2 | RADEON_CRTC2_DISP_REQ_EN_B); 2249 } 2250 2251 delay(100000); 2252 2253 mcfbloc = (aperbase >> 16) | 2254 ((aperbase + (apersize - 1)) & 0xffff0000); 2255 2256 sc->sc_aperbase = (mcfbloc & 0xffff) << 16; 2257 sc->sc_memsz = apersize; 2258 2259 if (((agploc & 0xffff) << 16) != 2260 ((mcfbloc & 0xffff0000U) + 0x10000)) { 2261 agploc = mcfbloc & 0xffff0000U; 2262 agploc |= ((agploc + 0x10000) >> 16); 2263 } 2264 2265 PUT32(sc, RADEON_HOST_PATH_CNTL, 0); 2266 2267 PUT32(sc, RADEON_MC_FB_LOCATION, mcfbloc); 2268 PUT32(sc, RADEON_MC_AGP_LOCATION, agploc); 2269 2270 DPRINTF(("aperbase = %u\n", aperbase)); 2271 PRINTREG(RADEON_MC_FB_LOCATION); 2272 PRINTREG(RADEON_MC_AGP_LOCATION); 2273 2274 PUT32(sc, RADEON_DISPLAY_BASE_ADDR, sc->sc_aperbase); 2275 2276 if (HAS_CRTC2(sc)) 2277 PUT32(sc, RADEON_DISPLAY2_BASE_ADDR, sc->sc_aperbase); 2278 2279 PUT32(sc, RADEON_OV0_BASE_ADDR, sc->sc_aperbase); 2280 2281 #if 0 2282 /* XXX: what is this AGP garbage? :-) */ 2283 PUT32(sc, RADEON_AGP_CNTL, 0x00100000); 2284 #endif 2285 2286 delay(100000); 2287 2288 PUT32(sc, RADEON_CRTC_GEN_CNTL, gen); 2289 PUT32(sc, RADEON_CRTC_EXT_CNTL, ext); 2290 2291 if (HAS_CRTC2(sc)) 2292 PUT32(sc, RADEON_CRTC2_GEN_CNTL, gen2); 2293 } 2294 2295 void 2296 radeonfb_init_misc(struct radeonfb_softc *sc) 2297 { 2298 PUT32(sc, RADEON_BUS_CNTL, 2299 RADEON_BUS_MASTER_DIS | 2300 RADEON_BUS_PREFETCH_MODE_ACT | 2301 RADEON_BUS_PCI_READ_RETRY_EN | 2302 RADEON_BUS_PCI_WRT_RETRY_EN | 2303 (3 << RADEON_BUS_RETRY_WS_SHIFT) | 2304 RADEON_BUS_MSTR_RD_MULT | 2305 RADEON_BUS_MSTR_RD_LINE | 2306 RADEON_BUS_RD_DISCARD_EN | 2307 RADEON_BUS_MSTR_DISCONNECT_EN | 2308 RADEON_BUS_READ_BURST); 2309 2310 PUT32(sc, RADEON_BUS_CNTL1, 0xf0); 2311 /* PUT32(sc, RADEON_SEPROM_CNTL1, 0x09ff0000); */ 2312 PUT32(sc, RADEON_FCP_CNTL, RADEON_FCP0_SRC_GND); 2313 PUT32(sc, RADEON_RBBM_CNTL, 2314 (3 << RADEON_RB_SETTLE_SHIFT) | 2315 (4 << RADEON_ABORTCLKS_HI_SHIFT) | 2316 (4 << RADEON_ABORTCLKS_CP_SHIFT) | 2317 (4 << RADEON_ABORTCLKS_CFIFO_SHIFT)); 2318 2319 /* XXX: figure out what these mean! */ 2320 PUT32(sc, RADEON_AGP_CNTL, 0x00100000); 2321 PUT32(sc, RADEON_HOST_PATH_CNTL, 0); 2322 //PUT32(sc, RADEON_DISP_MISC_CNTL, 0x5bb00400); 2323 2324 PUT32(sc, RADEON_GEN_INT_CNTL, 0); 2325 PUT32(sc, RADEON_GEN_INT_STATUS, GET32(sc, RADEON_GEN_INT_STATUS)); 2326 } 2327 2328 /* 2329 * This loads a linear color map for true color. 2330 */ 2331 void 2332 radeonfb_init_palette(struct radeonfb_softc *sc, int crtc) 2333 { 2334 int i; 2335 uint32_t vclk; 2336 2337 #define DAC_WIDTH ((1 << 10) - 1) 2338 #define CLUT_WIDTH ((1 << 8) - 1) 2339 #define CLUT_COLOR(i) ((i * DAC_WIDTH * 2 / CLUT_WIDTH + 1) / 2) 2340 2341 vclk = GETPLL(sc, RADEON_VCLK_ECP_CNTL); 2342 PUTPLL(sc, RADEON_VCLK_ECP_CNTL, vclk & ~RADEON_PIXCLK_DAC_ALWAYS_ONb); 2343 2344 if (crtc) 2345 SET32(sc, RADEON_DAC_CNTL2, RADEON_DAC2_PALETTE_ACC_CTL); 2346 else 2347 CLR32(sc, RADEON_DAC_CNTL2, RADEON_DAC2_PALETTE_ACC_CTL); 2348 2349 PUT32(sc, RADEON_PALETTE_INDEX, 0); 2350 if (sc->sc_displays[crtc].rd_bpp == 0) 2351 sc->sc_displays[crtc].rd_bpp = RADEONFB_DEFAULT_DEPTH; 2352 2353 if (sc->sc_displays[crtc].rd_bpp == 8) { 2354 /* ANSI palette */ 2355 int j = 0; 2356 2357 for (i = 0; i <= CLUT_WIDTH; ++i) { 2358 PUT32(sc, RADEON_PALETTE_30_DATA, 2359 (rasops_cmap[j] << 22) | 2360 (rasops_cmap[j + 1] << 12) | 2361 (rasops_cmap[j + 2] << 2)); 2362 j += 3; 2363 } 2364 } else { 2365 /* linear ramp */ 2366 for (i = 0; i <= CLUT_WIDTH; ++i) { 2367 PUT32(sc, RADEON_PALETTE_30_DATA, 2368 (CLUT_COLOR(i) << 10) | 2369 (CLUT_COLOR(i) << 20) | 2370 (CLUT_COLOR(i))); 2371 } 2372 } 2373 2374 CLR32(sc, RADEON_DAC_CNTL2, RADEON_DAC2_PALETTE_ACC_CTL); 2375 PRINTREG(RADEON_DAC_CNTL2); 2376 2377 PUTPLL(sc, RADEON_VCLK_ECP_CNTL, vclk); 2378 } 2379 2380 /* 2381 * Bugs in some R300 hardware requires this when accessing CLOCK_CNTL_INDEX. 2382 */ 2383 void 2384 radeonfb_r300cg_workaround(struct radeonfb_softc *sc) 2385 { 2386 uint32_t tmp, save; 2387 2388 save = GET32(sc, RADEON_CLOCK_CNTL_INDEX); 2389 tmp = save & ~(0x3f | RADEON_PLL_WR_EN); 2390 PUT32(sc, RADEON_CLOCK_CNTL_INDEX, tmp); 2391 tmp = GET32(sc, RADEON_CLOCK_CNTL_DATA); 2392 PUT32(sc, RADEON_CLOCK_CNTL_INDEX, save); 2393 } 2394 2395 /* 2396 * Acceleration entry points. 2397 */ 2398 2399 /* this one draws characters using bitmap fonts */ 2400 static void 2401 radeonfb_putchar(void *cookie, int row, int col, u_int c, long attr) 2402 { 2403 struct rasops_info *ri = cookie; 2404 struct vcons_screen *scr = ri->ri_hw; 2405 struct radeonfb_display *dp = scr->scr_cookie; 2406 struct radeonfb_softc *sc = dp->rd_softc; 2407 struct wsdisplay_font *font = PICK_FONT(ri, c); 2408 uint32_t w, h; 2409 int xd, yd, offset, i; 2410 uint32_t bg, fg, gmc; 2411 uint32_t reg; 2412 uint8_t *data8; 2413 uint16_t *data16; 2414 void *data; 2415 2416 if (dp->rd_wsmode != WSDISPLAYIO_MODE_EMUL) 2417 return; 2418 2419 if (!CHAR_IN_FONT(c, font)) 2420 return; 2421 2422 w = font->fontwidth; 2423 h = font->fontheight; 2424 2425 bg = ri->ri_devcmap[(attr >> 16) & 0xf]; 2426 fg = ri->ri_devcmap[(attr >> 24) & 0xf]; 2427 2428 xd = ri->ri_xorigin + col * w; 2429 yd = ri->ri_yorigin + row * h; 2430 2431 if (c == 0x20) { 2432 radeonfb_rectfill(dp, xd, yd, w, h, bg); 2433 return; 2434 } 2435 data = WSFONT_GLYPH(c, font); 2436 2437 gmc = dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT; 2438 2439 radeonfb_wait_fifo(sc, 9); 2440 2441 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 2442 RADEON_GMC_BRUSH_NONE | 2443 RADEON_GMC_SRC_DATATYPE_MONO_FG_BG | 2444 RADEON_GMC_DST_CLIPPING | 2445 RADEON_ROP3_S | 2446 RADEON_DP_SRC_SOURCE_HOST_DATA | 2447 RADEON_GMC_CLR_CMP_CNTL_DIS | 2448 RADEON_GMC_WR_MSK_DIS | 2449 gmc); 2450 2451 PUT32(sc, RADEON_SC_LEFT, xd); 2452 PUT32(sc, RADEON_SC_RIGHT, xd + w); 2453 PUT32(sc, RADEON_DP_SRC_FRGD_CLR, fg); 2454 PUT32(sc, RADEON_DP_SRC_BKGD_CLR, bg); 2455 PUT32(sc, RADEON_DP_CNTL, 2456 RADEON_DST_X_LEFT_TO_RIGHT | 2457 RADEON_DST_Y_TOP_TO_BOTTOM); 2458 2459 PUT32(sc, RADEON_SRC_X_Y, 0); 2460 offset = 32 - (font->stride << 3); 2461 PUT32(sc, RADEON_DST_X_Y, ((xd - offset) << 16) | yd); 2462 PUT32(sc, RADEON_DST_WIDTH_HEIGHT, (32 << 16) | h); 2463 2464 radeonfb_wait_fifo(sc, h); 2465 switch (font->stride) { 2466 case 1: { 2467 data8 = data; 2468 for (i = 0; i < h; i++) { 2469 reg = *data8; 2470 bus_space_write_stream_4(sc->sc_regt, 2471 sc->sc_regh, RADEON_HOST_DATA0, reg); 2472 data8++; 2473 } 2474 break; 2475 } 2476 case 2: { 2477 data16 = data; 2478 for (i = 0; i < h; i++) { 2479 reg = *data16; 2480 bus_space_write_stream_4(sc->sc_regt, 2481 sc->sc_regh, RADEON_HOST_DATA0, reg); 2482 data16++; 2483 } 2484 break; 2485 } 2486 } 2487 } 2488 2489 /* ... while this one is for anti-aliased ones */ 2490 static void 2491 radeonfb_putchar_aa32(void *cookie, int row, int col, u_int c, long attr) 2492 { 2493 struct rasops_info *ri = cookie; 2494 struct vcons_screen *scr = ri->ri_hw; 2495 struct radeonfb_display *dp = scr->scr_cookie; 2496 struct radeonfb_softc *sc = dp->rd_softc; 2497 struct wsdisplay_font *font = PICK_FONT(ri, c); 2498 uint32_t bg, fg, gmc; 2499 uint8_t *data; 2500 int w, h, xd, yd; 2501 int i, r, g, b, aval; 2502 int rf, gf, bf, rb, gb, bb; 2503 uint32_t pixel; 2504 2505 if (dp->rd_wsmode != WSDISPLAYIO_MODE_EMUL) 2506 return; 2507 2508 if (!CHAR_IN_FONT(c, font)) 2509 return; 2510 2511 w = font->fontwidth; 2512 h = font->fontheight; 2513 2514 bg = ri->ri_devcmap[(attr >> 16) & 0xf]; 2515 fg = ri->ri_devcmap[(attr >> 24) & 0xf]; 2516 2517 xd = ri->ri_xorigin + col * w; 2518 yd = ri->ri_yorigin + row * h; 2519 2520 if (c == 0x20) { 2521 radeonfb_rectfill(dp, xd, yd, w, h, bg); 2522 return; 2523 } 2524 data = WSFONT_GLYPH(c, font); 2525 2526 gmc = dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT; 2527 2528 radeonfb_wait_fifo(sc, 5); 2529 2530 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 2531 RADEON_GMC_BRUSH_NONE | 2532 RADEON_GMC_SRC_DATATYPE_COLOR | 2533 RADEON_ROP3_S | 2534 RADEON_DP_SRC_SOURCE_HOST_DATA | 2535 RADEON_GMC_CLR_CMP_CNTL_DIS | 2536 RADEON_GMC_WR_MSK_DIS | 2537 gmc); 2538 2539 PUT32(sc, RADEON_DP_CNTL, 2540 RADEON_DST_X_LEFT_TO_RIGHT | 2541 RADEON_DST_Y_TOP_TO_BOTTOM); 2542 2543 PUT32(sc, RADEON_SRC_X_Y, 0); 2544 PUT32(sc, RADEON_DST_X_Y, (xd << 16) | yd); 2545 PUT32(sc, RADEON_DST_WIDTH_HEIGHT, (w << 16) | h); 2546 2547 rf = (fg >> 16) & 0xff; 2548 rb = (bg >> 16) & 0xff; 2549 gf = (fg >> 8) & 0xff; 2550 gb = (bg >> 8) & 0xff; 2551 bf = fg & 0xff; 2552 bb = bg & 0xff; 2553 2554 /* 2555 * I doubt we can upload data faster than even the slowest Radeon 2556 * could process them, especially when doing the alpha blending stuff 2557 * along the way, so just make sure there's some room in the FIFO and 2558 * then hammer away 2559 * As it turns out we can, so make periodic stops to let the FIFO 2560 * drain. 2561 */ 2562 radeonfb_wait_fifo(sc, 20); 2563 for (i = 0; i < ri->ri_fontscale; i++) { 2564 aval = *data; 2565 data++; 2566 if (aval == 0) { 2567 pixel = bg; 2568 } else if (aval == 255) { 2569 pixel = fg; 2570 } else { 2571 r = aval * rf + (255 - aval) * rb; 2572 g = aval * gf + (255 - aval) * gb; 2573 b = aval * bf + (255 - aval) * bb; 2574 pixel = (r & 0xff00) << 8 | 2575 (g & 0xff00) | 2576 (b & 0xff00) >> 8; 2577 } 2578 if (i & 16) 2579 radeonfb_wait_fifo(sc, 20); 2580 PUT32(sc, RADEON_HOST_DATA0, pixel); 2581 } 2582 } 2583 2584 /* 2585 * wrapper for software character drawing 2586 * just sync the engine and call rasops*_putchar() 2587 */ 2588 2589 static void 2590 radeonfb_putchar_wrapper(void *cookie, int row, int col, u_int c, long attr) 2591 { 2592 struct rasops_info *ri = cookie; 2593 struct vcons_screen *scr = ri->ri_hw; 2594 struct radeonfb_display *dp = scr->scr_cookie; 2595 2596 radeonfb_engine_idle(dp->rd_softc); 2597 dp->rd_putchar(ri, row, col, c, attr); 2598 } 2599 2600 static void 2601 radeonfb_eraserows(void *cookie, int row, int nrows, long fillattr) 2602 { 2603 struct rasops_info *ri = cookie; 2604 struct vcons_screen *scr = ri->ri_hw; 2605 struct radeonfb_display *dp = scr->scr_cookie; 2606 uint32_t x, y, w, h, fg, bg, ul; 2607 2608 /* XXX: check for full emulation mode? */ 2609 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 2610 x = ri->ri_xorigin; 2611 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 2612 w = ri->ri_emuwidth; 2613 h = ri->ri_font->fontheight * nrows; 2614 2615 rasops_unpack_attr(fillattr, &fg, &bg, &ul); 2616 radeonfb_rectfill(dp, x, y, w, h, ri->ri_devcmap[bg & 0xf]); 2617 } 2618 } 2619 2620 static void 2621 radeonfb_copyrows(void *cookie, int srcrow, int dstrow, int nrows) 2622 { 2623 struct rasops_info *ri = cookie; 2624 struct vcons_screen *scr = ri->ri_hw; 2625 struct radeonfb_display *dp = scr->scr_cookie; 2626 uint32_t x, ys, yd, w, h; 2627 2628 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 2629 x = ri->ri_xorigin; 2630 ys = ri->ri_yorigin + ri->ri_font->fontheight * srcrow; 2631 yd = ri->ri_yorigin + ri->ri_font->fontheight * dstrow; 2632 w = ri->ri_emuwidth; 2633 h = ri->ri_font->fontheight * nrows; 2634 radeonfb_bitblt(dp, x, ys, x, yd, w, h, 2635 RADEON_ROP3_S, 0xffffffff); 2636 } 2637 } 2638 2639 static void 2640 radeonfb_copycols(void *cookie, int row, int srccol, int dstcol, int ncols) 2641 { 2642 struct rasops_info *ri = cookie; 2643 struct vcons_screen *scr = ri->ri_hw; 2644 struct radeonfb_display *dp = scr->scr_cookie; 2645 uint32_t xs, xd, y, w, h; 2646 2647 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 2648 xs = ri->ri_xorigin + ri->ri_font->fontwidth * srccol; 2649 xd = ri->ri_xorigin + ri->ri_font->fontwidth * dstcol; 2650 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 2651 w = ri->ri_font->fontwidth * ncols; 2652 h = ri->ri_font->fontheight; 2653 radeonfb_bitblt(dp, xs, y, xd, y, w, h, 2654 RADEON_ROP3_S, 0xffffffff); 2655 } 2656 } 2657 2658 static void 2659 radeonfb_erasecols(void *cookie, int row, int startcol, int ncols, 2660 long fillattr) 2661 { 2662 struct rasops_info *ri = cookie; 2663 struct vcons_screen *scr = ri->ri_hw; 2664 struct radeonfb_display *dp = scr->scr_cookie; 2665 uint32_t x, y, w, h, fg, bg, ul; 2666 2667 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 2668 x = ri->ri_xorigin + ri->ri_font->fontwidth * startcol; 2669 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 2670 w = ri->ri_font->fontwidth * ncols; 2671 h = ri->ri_font->fontheight; 2672 2673 rasops_unpack_attr(fillattr, &fg, &bg, &ul); 2674 radeonfb_rectfill(dp, x, y, w, h, ri->ri_devcmap[bg & 0xf]); 2675 } 2676 } 2677 2678 static void 2679 radeonfb_cursor(void *cookie, int on, int row, int col) 2680 { 2681 struct rasops_info *ri = cookie; 2682 struct vcons_screen *scr = ri->ri_hw; 2683 struct radeonfb_display *dp = scr->scr_cookie; 2684 int x, y, wi, he; 2685 2686 wi = ri->ri_font->fontwidth; 2687 he = ri->ri_font->fontheight; 2688 2689 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 2690 x = ri->ri_ccol * wi + ri->ri_xorigin; 2691 y = ri->ri_crow * he + ri->ri_yorigin; 2692 /* first turn off the old cursor */ 2693 if (ri->ri_flg & RI_CURSOR) { 2694 radeonfb_bitblt(dp, x, y, x, y, wi, he, 2695 RADEON_ROP3_Dn, 0xffffffff); 2696 ri->ri_flg &= ~RI_CURSOR; 2697 } 2698 ri->ri_crow = row; 2699 ri->ri_ccol = col; 2700 /* then (possibly) turn on the new one */ 2701 if (on) { 2702 x = ri->ri_ccol * wi + ri->ri_xorigin; 2703 y = ri->ri_crow * he + ri->ri_yorigin; 2704 radeonfb_bitblt(dp, x, y, x, y, wi, he, 2705 RADEON_ROP3_Dn, 0xffffffff); 2706 ri->ri_flg |= RI_CURSOR; 2707 } 2708 } else { 2709 scr->scr_ri.ri_crow = row; 2710 scr->scr_ri.ri_ccol = col; 2711 scr->scr_ri.ri_flg &= ~RI_CURSOR; 2712 } 2713 } 2714 2715 /* 2716 * Underlying acceleration support. 2717 */ 2718 2719 static void 2720 radeonfb_rectfill(struct radeonfb_display *dp, int dstx, int dsty, 2721 int width, int height, uint32_t color) 2722 { 2723 struct radeonfb_softc *sc = dp->rd_softc; 2724 uint32_t gmc; 2725 2726 gmc = dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT; 2727 2728 radeonfb_wait_fifo(sc, 6); 2729 2730 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 2731 RADEON_GMC_BRUSH_SOLID_COLOR | 2732 RADEON_GMC_SRC_DATATYPE_COLOR | 2733 RADEON_GMC_CLR_CMP_CNTL_DIS | 2734 RADEON_ROP3_P | gmc); 2735 2736 PUT32(sc, RADEON_DP_BRUSH_FRGD_CLR, color); 2737 PUT32(sc, RADEON_DP_WRITE_MASK, 0xffffffff); 2738 PUT32(sc, RADEON_DP_CNTL, 2739 RADEON_DST_X_LEFT_TO_RIGHT | 2740 RADEON_DST_Y_TOP_TO_BOTTOM); 2741 PUT32(sc, RADEON_DST_Y_X, (dsty << 16) | dstx); 2742 PUT32(sc, RADEON_DST_WIDTH_HEIGHT, (width << 16) | (height)); 2743 2744 } 2745 2746 static void 2747 radeonfb_bitblt(struct radeonfb_display *dp, int srcx, int srcy, 2748 int dstx, int dsty, int width, int height, int rop, uint32_t mask) 2749 { 2750 struct radeonfb_softc *sc = dp->rd_softc; 2751 uint32_t gmc; 2752 uint32_t dir; 2753 2754 if (dsty < srcy) { 2755 dir = RADEON_DST_Y_TOP_TO_BOTTOM; 2756 } else { 2757 srcy += height - 1; 2758 dsty += height - 1; 2759 dir = 0; 2760 } 2761 if (dstx < srcx) { 2762 dir |= RADEON_DST_X_LEFT_TO_RIGHT; 2763 } else { 2764 srcx += width - 1; 2765 dstx += width - 1; 2766 } 2767 2768 gmc = dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT; 2769 2770 radeonfb_wait_fifo(sc, 6); 2771 2772 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 2773 RADEON_GMC_BRUSH_SOLID_COLOR | 2774 RADEON_GMC_SRC_DATATYPE_COLOR | 2775 RADEON_GMC_CLR_CMP_CNTL_DIS | 2776 RADEON_DP_SRC_SOURCE_MEMORY | 2777 rop | gmc); 2778 2779 PUT32(sc, RADEON_DP_WRITE_MASK, mask); 2780 PUT32(sc, RADEON_DP_CNTL, dir); 2781 PUT32(sc, RADEON_SRC_Y_X, (srcy << 16) | srcx); 2782 PUT32(sc, RADEON_DST_Y_X, (dsty << 16) | dstx); 2783 PUT32(sc, RADEON_DST_WIDTH_HEIGHT, (width << 16) | (height)); 2784 } 2785 2786 static void 2787 radeonfb_engine_idle(struct radeonfb_softc *sc) 2788 { 2789 2790 radeonfb_wait_fifo(sc, 64); 2791 while ((GET32(sc, RADEON_RBBM_STATUS) & 2792 RADEON_RBBM_ACTIVE) != 0); 2793 radeonfb_engine_flush(sc); 2794 } 2795 2796 static void 2797 radeonfb_wait_fifo(struct radeonfb_softc *sc, int n) 2798 { 2799 int i; 2800 2801 for (i = RADEON_TIMEOUT; i; i--) { 2802 if ((GET32(sc, RADEON_RBBM_STATUS) & 2803 RADEON_RBBM_FIFOCNT_MASK) >= n) 2804 return; 2805 } 2806 #ifdef DIAGNOSTIC 2807 if (!i) 2808 printf("%s: timed out waiting for fifo (%x)\n", 2809 XNAME(sc), GET32(sc, RADEON_RBBM_STATUS)); 2810 #endif 2811 } 2812 2813 static void 2814 radeonfb_engine_flush(struct radeonfb_softc *sc) 2815 { 2816 int i = 0; 2817 2818 if (IS_R300(sc)) { 2819 SET32(sc, R300_DSTCACHE_CTLSTAT, R300_RB2D_DC_FLUSH_ALL); 2820 while (GET32(sc, R300_DSTCACHE_CTLSTAT) & R300_RB2D_DC_BUSY) { 2821 i++; 2822 } 2823 } else { 2824 SET32(sc, RADEON_RB2D_DSTCACHE_CTLSTAT, 2825 RADEON_RB2D_DC_FLUSH_ALL); 2826 while (GET32(sc, RADEON_RB2D_DSTCACHE_CTLSTAT) & 2827 RADEON_RB2D_DC_BUSY) { 2828 i++; 2829 } 2830 } 2831 #ifdef DIAGNOSTIC 2832 if (i > RADEON_TIMEOUT) 2833 printf("%s: engine flush timed out!\n", XNAME(sc)); 2834 #endif 2835 } 2836 2837 static inline void 2838 radeonfb_unclip(struct radeonfb_softc *sc) 2839 { 2840 2841 radeonfb_wait_fifo(sc, 2); 2842 PUT32(sc, RADEON_SC_TOP_LEFT, 0); 2843 PUT32(sc, RADEON_SC_BOTTOM_RIGHT, 0x1fff1fff); 2844 } 2845 2846 static void 2847 radeonfb_engine_init(struct radeonfb_display *dp) 2848 { 2849 struct radeonfb_softc *sc = dp->rd_softc; 2850 uint32_t pitch; 2851 volatile uint32_t junk; 2852 2853 /* no 3D */ 2854 PUT32(sc, RADEON_RB3D_CNTL, 0); 2855 2856 radeonfb_engine_reset(sc); 2857 pitch = ((dp->rd_virtx * (dp->rd_bpp / 8) + 0x3f)) >> 6; 2858 2859 radeonfb_wait_fifo(sc, 1); 2860 if (!IS_R300(sc)) 2861 PUT32(sc, RADEON_RB2D_DSTCACHE_MODE, 0); 2862 2863 radeonfb_wait_fifo(sc, 3); 2864 PUT32(sc, RADEON_DEFAULT_PITCH_OFFSET, 2865 (pitch << 22) | (sc->sc_aperbase >> 10)); 2866 2867 2868 PUT32(sc, RADEON_DST_PITCH_OFFSET, 2869 (pitch << 22) | (sc->sc_aperbase >> 10)); 2870 PUT32(sc, RADEON_SRC_PITCH_OFFSET, 2871 (pitch << 22) | (sc->sc_aperbase >> 10)); 2872 2873 radeonfb_wait_fifo(sc, 1); 2874 #if _BYTE_ORDER == _BIG_ENDIAN 2875 SET32(sc, RADEON_DP_DATATYPE, RADEON_HOST_BIG_ENDIAN_EN); 2876 #else 2877 CLR32(sc, RADEON_DP_DATATYPE, RADEON_HOST_BIG_ENDIAN_EN); 2878 #endif 2879 junk = GET32(sc, RADEON_DP_DATATYPE); 2880 2881 /* default scissors -- no clipping */ 2882 radeonfb_wait_fifo(sc, 1); 2883 PUT32(sc, RADEON_DEFAULT_SC_BOTTOM_RIGHT, 2884 RADEON_DEFAULT_SC_RIGHT_MAX | RADEON_DEFAULT_SC_BOTTOM_MAX); 2885 2886 radeonfb_wait_fifo(sc, 1); 2887 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 2888 (dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT) | 2889 RADEON_GMC_CLR_CMP_CNTL_DIS | 2890 RADEON_GMC_BRUSH_SOLID_COLOR | 2891 RADEON_GMC_SRC_DATATYPE_COLOR); 2892 2893 radeonfb_wait_fifo(sc, 10); 2894 PUT32(sc, RADEON_DST_LINE_START, 0); 2895 PUT32(sc, RADEON_DST_LINE_END, 0); 2896 PUT32(sc, RADEON_DP_BRUSH_FRGD_CLR, 0xffffffff); 2897 PUT32(sc, RADEON_DP_BRUSH_BKGD_CLR, 0); 2898 PUT32(sc, RADEON_DP_SRC_FRGD_CLR, 0xffffffff); 2899 PUT32(sc, RADEON_DP_SRC_BKGD_CLR, 0); 2900 PUT32(sc, RADEON_DP_WRITE_MASK, 0xffffffff); 2901 PUT32(sc, RADEON_SC_TOP_LEFT, 0); 2902 PUT32(sc, RADEON_SC_BOTTOM_RIGHT, 0x1fff1fff); 2903 PUT32(sc, RADEON_AUX_SC_CNTL, 0); 2904 radeonfb_engine_idle(sc); 2905 } 2906 2907 static void 2908 radeonfb_engine_reset(struct radeonfb_softc *sc) 2909 { 2910 uint32_t hpc, rbbm, mclkcntl, clkindex; 2911 2912 radeonfb_engine_flush(sc); 2913 2914 clkindex = GET32(sc, RADEON_CLOCK_CNTL_INDEX); 2915 if (HAS_R300CG(sc)) 2916 radeonfb_r300cg_workaround(sc); 2917 mclkcntl = GETPLL(sc, RADEON_MCLK_CNTL); 2918 2919 /* 2920 * According to comments in XFree code, resetting the HDP via 2921 * the RBBM_SOFT_RESET can cause bad behavior on some systems. 2922 * So we use HOST_PATH_CNTL instead. 2923 */ 2924 2925 hpc = GET32(sc, RADEON_HOST_PATH_CNTL); 2926 rbbm = GET32(sc, RADEON_RBBM_SOFT_RESET); 2927 if (IS_R300(sc)) { 2928 PUT32(sc, RADEON_RBBM_SOFT_RESET, rbbm | 2929 RADEON_SOFT_RESET_CP | 2930 RADEON_SOFT_RESET_HI | 2931 RADEON_SOFT_RESET_E2); 2932 GET32(sc, RADEON_RBBM_SOFT_RESET); 2933 PUT32(sc, RADEON_RBBM_SOFT_RESET, 0); 2934 /* 2935 * XXX: this bit is not defined in any ATI docs I have, 2936 * nor in the XFree code, but XFree does it. Why? 2937 */ 2938 SET32(sc, RADEON_RB2D_DSTCACHE_MODE, (1<<17)); 2939 } else { 2940 PUT32(sc, RADEON_RBBM_SOFT_RESET, rbbm | 2941 RADEON_SOFT_RESET_CP | 2942 RADEON_SOFT_RESET_SE | 2943 RADEON_SOFT_RESET_RE | 2944 RADEON_SOFT_RESET_PP | 2945 RADEON_SOFT_RESET_E2 | 2946 RADEON_SOFT_RESET_RB); 2947 GET32(sc, RADEON_RBBM_SOFT_RESET); 2948 PUT32(sc, RADEON_RBBM_SOFT_RESET, rbbm & 2949 ~(RADEON_SOFT_RESET_CP | 2950 RADEON_SOFT_RESET_SE | 2951 RADEON_SOFT_RESET_RE | 2952 RADEON_SOFT_RESET_PP | 2953 RADEON_SOFT_RESET_E2 | 2954 RADEON_SOFT_RESET_RB)); 2955 GET32(sc, RADEON_RBBM_SOFT_RESET); 2956 } 2957 2958 PUT32(sc, RADEON_HOST_PATH_CNTL, hpc | RADEON_HDP_SOFT_RESET); 2959 GET32(sc, RADEON_HOST_PATH_CNTL); 2960 PUT32(sc, RADEON_HOST_PATH_CNTL, hpc); 2961 2962 if (IS_R300(sc)) 2963 PUT32(sc, RADEON_RBBM_SOFT_RESET, rbbm); 2964 2965 PUT32(sc, RADEON_CLOCK_CNTL_INDEX, clkindex); 2966 PUTPLL(sc, RADEON_MCLK_CNTL, mclkcntl); 2967 2968 if (HAS_R300CG(sc)) 2969 radeonfb_r300cg_workaround(sc); 2970 } 2971 2972 static int 2973 radeonfb_set_curpos(struct radeonfb_display *dp, struct wsdisplay_curpos *pos) 2974 { 2975 int x, y; 2976 2977 x = pos->x; 2978 y = pos->y; 2979 2980 /* 2981 * This doesn't let a cursor move off the screen. I'm not 2982 * sure if this will have negative effects for e.g. Xinerama. 2983 * I'd guess Xinerama handles it by changing the cursor shape, 2984 * but that needs verification. 2985 */ 2986 if (x >= dp->rd_virtx) 2987 x = dp->rd_virtx - 1; 2988 if (x < 0) 2989 x = 0; 2990 if (y >= dp->rd_virty) 2991 y = dp->rd_virty - 1; 2992 if (y < 0) 2993 y = 0; 2994 2995 dp->rd_cursor.rc_pos.x = x; 2996 dp->rd_cursor.rc_pos.y = y; 2997 2998 radeonfb_cursor_position(dp); 2999 return 0; 3000 } 3001 3002 static int 3003 radeonfb_set_cursor(struct radeonfb_display *dp, struct wsdisplay_cursor *wc) 3004 { 3005 unsigned flags; 3006 3007 uint8_t r[2], g[2], b[2]; 3008 unsigned index, count; 3009 int i, err; 3010 int pitch, size; 3011 struct radeonfb_cursor nc; 3012 3013 flags = wc->which; 3014 3015 /* copy old values */ 3016 nc = dp->rd_cursor; 3017 3018 if (flags & WSDISPLAY_CURSOR_DOCMAP) { 3019 index = wc->cmap.index; 3020 count = wc->cmap.count; 3021 3022 if (index >= 2 || (index + count) > 2) 3023 return EINVAL; 3024 3025 err = copyin(wc->cmap.red, &r[index], count); 3026 if (err) 3027 return err; 3028 err = copyin(wc->cmap.green, &g[index], count); 3029 if (err) 3030 return err; 3031 err = copyin(wc->cmap.blue, &b[index], count); 3032 if (err) 3033 return err; 3034 3035 for (i = index; i < index + count; i++) { 3036 nc.rc_cmap[i] = 3037 (r[i] << 16) + (g[i] << 8) + (b[i] << 0); 3038 } 3039 } 3040 3041 if (flags & WSDISPLAY_CURSOR_DOSHAPE) { 3042 if ((wc->size.x > RADEON_CURSORMAXX) || 3043 (wc->size.y > RADEON_CURSORMAXY)) 3044 return EINVAL; 3045 3046 /* figure bytes per line */ 3047 pitch = (wc->size.x + 7) / 8; 3048 size = pitch * wc->size.y; 3049 3050 /* clear the old cursor and mask */ 3051 memset(nc.rc_image, 0, 512); 3052 memset(nc.rc_mask, 0, 512); 3053 3054 nc.rc_size = wc->size; 3055 3056 if ((err = copyin(wc->image, nc.rc_image, size)) != 0) 3057 return err; 3058 3059 if ((err = copyin(wc->mask, nc.rc_mask, size)) != 0) 3060 return err; 3061 } 3062 3063 if (flags & WSDISPLAY_CURSOR_DOHOT) { 3064 nc.rc_hot = wc->hot; 3065 if (nc.rc_hot.x >= nc.rc_size.x) 3066 nc.rc_hot.x = nc.rc_size.x - 1; 3067 if (nc.rc_hot.y >= nc.rc_size.y) 3068 nc.rc_hot.y = nc.rc_size.y - 1; 3069 } 3070 3071 if (flags & WSDISPLAY_CURSOR_DOPOS) { 3072 nc.rc_pos = wc->pos; 3073 if (nc.rc_pos.x >= dp->rd_virtx) 3074 nc.rc_pos.x = dp->rd_virtx - 1; 3075 #if 0 3076 if (nc.rc_pos.x < 0) 3077 nc.rc_pos.x = 0; 3078 #endif 3079 if (nc.rc_pos.y >= dp->rd_virty) 3080 nc.rc_pos.y = dp->rd_virty - 1; 3081 #if 0 3082 if (nc.rc_pos.y < 0) 3083 nc.rc_pos.y = 0; 3084 #endif 3085 } 3086 if (flags & WSDISPLAY_CURSOR_DOCUR) { 3087 nc.rc_visible = wc->enable; 3088 } 3089 3090 dp->rd_cursor = nc; 3091 radeonfb_cursor_update(dp, wc->which); 3092 3093 return 0; 3094 } 3095 3096 /* 3097 * Change the cursor shape. Call this with the cursor locked to avoid 3098 * flickering/tearing. 3099 */ 3100 static void 3101 radeonfb_cursor_shape(struct radeonfb_display *dp) 3102 { 3103 uint8_t and[512], xor[512]; 3104 int i, j, src, dst, pitch; 3105 const uint8_t *msk = dp->rd_cursor.rc_mask; 3106 const uint8_t *img = dp->rd_cursor.rc_image; 3107 3108 /* 3109 * Radeon cursor data interleaves one line of AND data followed 3110 * by a line of XOR data. (Each line corresponds to a whole hardware 3111 * pitch - i.e. 64 pixels or 8 bytes.) 3112 * 3113 * The cursor is displayed using the following table: 3114 * 3115 * AND XOR Result 3116 * ---------------------- 3117 * 0 0 Cursor color 0 3118 * 0 1 Cursor color 1 3119 * 1 0 Transparent 3120 * 1 1 Complement of background 3121 * 3122 * Our masks are therefore different from what we were passed. 3123 * Passed in, I'm assuming the data represents either color 0 or 1, 3124 * and a mask, so the passed in table looks like: 3125 * 3126 * IMG Mask Result 3127 * ----------------------- 3128 * 0 0 Transparent 3129 * 0 1 Cursor color 0 3130 * 1 0 Transparent 3131 * 1 1 Cursor color 1 3132 * 3133 * IF mask bit == 1, AND = 0, XOR = color. 3134 * IF mask bit == 0, AND = 1, XOR = 0. 3135 * 3136 * hence: AND = ~(mask); XOR = color & ~(mask); 3137 */ 3138 3139 pitch = ((dp->rd_cursor.rc_size.x + 7) / 8); 3140 3141 /* start by assuming all bits are transparent */ 3142 memset(and, 0xff, 512); 3143 memset(xor, 0x00, 512); 3144 3145 src = 0; 3146 dst = 0; 3147 for (i = 0; i < 64; i++) { 3148 for (j = 0; j < 64; j += 8) { 3149 if ((i < dp->rd_cursor.rc_size.y) && 3150 (j < dp->rd_cursor.rc_size.x)) { 3151 3152 /* take care to leave odd bits alone */ 3153 and[dst] &= ~(msk[src]); 3154 xor[dst] = img[src] & msk[src]; 3155 src++; 3156 } 3157 dst++; 3158 } 3159 } 3160 3161 /* copy the image into place */ 3162 for (i = 0; i < 64; i++) { 3163 memcpy((uint8_t *)dp->rd_curptr + (i * 16), 3164 &and[i * 8], 8); 3165 memcpy((uint8_t *)dp->rd_curptr + (i * 16) + 8, 3166 &xor[i * 8], 8); 3167 } 3168 } 3169 3170 static void 3171 radeonfb_cursor_position(struct radeonfb_display *dp) 3172 { 3173 struct radeonfb_softc *sc = dp->rd_softc; 3174 uint32_t offset, hvoff, hvpos; /* registers */ 3175 uint32_t coff; /* cursor offset */ 3176 int i, x, y, xoff, yoff, crtcoff; 3177 3178 /* 3179 * XXX: this also needs to handle pan/scan 3180 */ 3181 for (i = 0; i < dp->rd_ncrtcs; i++) { 3182 3183 struct radeonfb_crtc *rcp = &dp->rd_crtcs[i]; 3184 3185 if (rcp->rc_number) { 3186 offset = RADEON_CUR2_OFFSET; 3187 hvoff = RADEON_CUR2_HORZ_VERT_OFF; 3188 hvpos = RADEON_CUR2_HORZ_VERT_POSN; 3189 crtcoff = RADEON_CRTC2_OFFSET; 3190 } else { 3191 offset = RADEON_CUR_OFFSET; 3192 hvoff = RADEON_CUR_HORZ_VERT_OFF; 3193 hvpos = RADEON_CUR_HORZ_VERT_POSN; 3194 crtcoff = RADEON_CRTC_OFFSET; 3195 } 3196 3197 x = dp->rd_cursor.rc_pos.x; 3198 y = dp->rd_cursor.rc_pos.y; 3199 3200 while (y < rcp->rc_yoffset) { 3201 rcp->rc_yoffset -= RADEON_PANINCREMENT; 3202 } 3203 while (y >= (rcp->rc_yoffset + rcp->rc_videomode.vdisplay)) { 3204 rcp->rc_yoffset += RADEON_PANINCREMENT; 3205 } 3206 while (x < rcp->rc_xoffset) { 3207 rcp->rc_xoffset -= RADEON_PANINCREMENT; 3208 } 3209 while (x >= (rcp->rc_xoffset + rcp->rc_videomode.hdisplay)) { 3210 rcp->rc_xoffset += RADEON_PANINCREMENT; 3211 } 3212 3213 /* adjust for the cursor's hotspot */ 3214 x -= dp->rd_cursor.rc_hot.x; 3215 y -= dp->rd_cursor.rc_hot.y; 3216 xoff = yoff = 0; 3217 3218 if (x >= dp->rd_virtx) 3219 x = dp->rd_virtx - 1; 3220 if (y >= dp->rd_virty) 3221 y = dp->rd_virty - 1; 3222 3223 /* now adjust cursor so it is relative to viewport */ 3224 x -= rcp->rc_xoffset; 3225 y -= rcp->rc_yoffset; 3226 3227 /* 3228 * no need to check for fall off, because we should 3229 * never move off the screen entirely! 3230 */ 3231 coff = 0; 3232 if (x < 0) { 3233 xoff = -x; 3234 x = 0; 3235 } 3236 if (y < 0) { 3237 yoff = -y; 3238 y = 0; 3239 coff = (yoff * 2) * 8; 3240 } 3241 3242 /* pan the display */ 3243 PUT32(sc, crtcoff, (rcp->rc_yoffset * dp->rd_stride) + 3244 rcp->rc_xoffset); 3245 3246 PUT32(sc, offset, (dp->rd_curoff + coff) | RADEON_CUR_LOCK); 3247 PUT32(sc, hvoff, (xoff << 16) | (yoff) | RADEON_CUR_LOCK); 3248 /* NB: this unlocks the cursor */ 3249 PUT32(sc, hvpos, (x << 16) | y); 3250 } 3251 } 3252 3253 static void 3254 radeonfb_cursor_visible(struct radeonfb_display *dp) 3255 { 3256 int i; 3257 uint32_t gencntl, bit; 3258 3259 for (i = 0; i < dp->rd_ncrtcs; i++) { 3260 if (dp->rd_crtcs[i].rc_number) { 3261 gencntl = RADEON_CRTC2_GEN_CNTL; 3262 bit = RADEON_CRTC2_CUR_EN; 3263 } else { 3264 gencntl = RADEON_CRTC_GEN_CNTL; 3265 bit = RADEON_CRTC_CUR_EN; 3266 } 3267 3268 if (dp->rd_cursor.rc_visible) 3269 SET32(dp->rd_softc, gencntl, bit); 3270 else 3271 CLR32(dp->rd_softc, gencntl, bit); 3272 } 3273 } 3274 3275 static void 3276 radeonfb_cursor_cmap(struct radeonfb_display *dp) 3277 { 3278 int i; 3279 uint32_t c0reg, c1reg; 3280 struct radeonfb_softc *sc = dp->rd_softc; 3281 3282 for (i = 0; i < dp->rd_ncrtcs; i++) { 3283 if (dp->rd_crtcs[i].rc_number) { 3284 c0reg = RADEON_CUR2_CLR0; 3285 c1reg = RADEON_CUR2_CLR1; 3286 } else { 3287 c0reg = RADEON_CUR_CLR0; 3288 c1reg = RADEON_CUR_CLR1; 3289 } 3290 3291 PUT32(sc, c0reg, dp->rd_cursor.rc_cmap[0]); 3292 PUT32(sc, c1reg, dp->rd_cursor.rc_cmap[1]); 3293 } 3294 } 3295 3296 static void 3297 radeonfb_cursor_update(struct radeonfb_display *dp, unsigned which) 3298 { 3299 struct radeonfb_softc *sc; 3300 int i; 3301 3302 sc = dp->rd_softc; 3303 for (i = 0; i < dp->rd_ncrtcs; i++) { 3304 if (dp->rd_crtcs[i].rc_number) { 3305 SET32(sc, RADEON_CUR2_OFFSET, RADEON_CUR_LOCK); 3306 } else { 3307 SET32(sc, RADEON_CUR_OFFSET,RADEON_CUR_LOCK); 3308 } 3309 } 3310 3311 if (which & WSDISPLAY_CURSOR_DOCMAP) 3312 radeonfb_cursor_cmap(dp); 3313 3314 if (which & WSDISPLAY_CURSOR_DOSHAPE) 3315 radeonfb_cursor_shape(dp); 3316 3317 if (which & WSDISPLAY_CURSOR_DOCUR) 3318 radeonfb_cursor_visible(dp); 3319 3320 /* this one is unconditional, because it updates other stuff */ 3321 radeonfb_cursor_position(dp); 3322 } 3323 3324 static struct videomode * 3325 radeonfb_best_refresh(struct videomode *m1, struct videomode *m2) 3326 { 3327 int r1, r2; 3328 3329 /* otherwise pick the higher refresh rate */ 3330 r1 = DIVIDE(DIVIDE(m1->dot_clock, m1->htotal), m1->vtotal); 3331 r2 = DIVIDE(DIVIDE(m2->dot_clock, m2->htotal), m2->vtotal); 3332 3333 return (r1 < r2 ? m2 : m1); 3334 } 3335 3336 static const struct videomode * 3337 radeonfb_port_mode(struct radeonfb_softc *sc, struct radeonfb_port *rp, 3338 int x, int y) 3339 { 3340 struct edid_info *ep = &rp->rp_edid; 3341 struct videomode *vmp = NULL; 3342 int i; 3343 3344 if (!rp->rp_edid_valid) { 3345 /* fallback to safe mode */ 3346 return radeonfb_modelookup(sc->sc_defaultmode); 3347 } 3348 3349 /* always choose the preferred mode first! */ 3350 if (ep->edid_preferred_mode) { 3351 3352 /* XXX: add auto-stretching support for native mode */ 3353 3354 /* this may want panning to occur, btw */ 3355 if ((ep->edid_preferred_mode->hdisplay <= x) && 3356 (ep->edid_preferred_mode->vdisplay <= y)) 3357 return ep->edid_preferred_mode; 3358 } 3359 3360 for (i = 0; i < ep->edid_nmodes; i++) { 3361 /* 3362 * We elect to pick a resolution that is too large for 3363 * the monitor than one that is too small. This means 3364 * that we will prefer to pan rather than to try to 3365 * center a smaller display on a larger screen. In 3366 * practice, this shouldn't matter because if a 3367 * monitor can support a larger resolution, it can 3368 * probably also support the smaller. A specific 3369 * exception is fixed format panels, but hopefully 3370 * they are properly dealt with by the "autostretch" 3371 * logic above. 3372 */ 3373 if ((ep->edid_modes[i].hdisplay > x) || 3374 (ep->edid_modes[i].vdisplay > y)) { 3375 continue; 3376 } 3377 3378 /* 3379 * at this point, the display mode is no larger than 3380 * what we've requested. 3381 */ 3382 if (vmp == NULL) 3383 vmp = &ep->edid_modes[i]; 3384 3385 /* eliminate smaller modes */ 3386 if ((vmp->hdisplay >= ep->edid_modes[i].hdisplay) || 3387 (vmp->vdisplay >= ep->edid_modes[i].vdisplay)) 3388 continue; 3389 3390 if ((vmp->hdisplay < ep->edid_modes[i].hdisplay) || 3391 (vmp->vdisplay < ep->edid_modes[i].vdisplay)) { 3392 vmp = &ep->edid_modes[i]; 3393 continue; 3394 } 3395 3396 KASSERT(vmp->hdisplay == ep->edid_modes[i].hdisplay); 3397 KASSERT(vmp->vdisplay == ep->edid_modes[i].vdisplay); 3398 3399 vmp = radeonfb_best_refresh(vmp, &ep->edid_modes[i]); 3400 } 3401 3402 return (vmp ? vmp : radeonfb_modelookup(sc->sc_defaultmode)); 3403 } 3404 3405 static int 3406 radeonfb_hasres(struct videomode *list, int nlist, int x, int y) 3407 { 3408 int i; 3409 3410 for (i = 0; i < nlist; i++) { 3411 if ((x == list[i].hdisplay) && 3412 (y == list[i].vdisplay)) { 3413 return 1; 3414 } 3415 } 3416 return 0; 3417 } 3418 3419 static void 3420 radeonfb_pickres(struct radeonfb_display *dp, uint16_t *x, uint16_t *y, 3421 int pan) 3422 { 3423 struct radeonfb_port *rp; 3424 struct edid_info *ep; 3425 int i, j; 3426 3427 *x = 0; 3428 *y = 0; 3429 3430 if (pan) { 3431 for (i = 0; i < dp->rd_ncrtcs; i++) { 3432 rp = dp->rd_crtcs[i].rc_port; 3433 ep = &rp->rp_edid; 3434 if (!rp->rp_edid_valid) { 3435 /* monitor not present */ 3436 continue; 3437 } 3438 3439 /* 3440 * For now we are ignoring "conflict" that 3441 * could occur when mixing some modes like 3442 * 1280x1024 and 1400x800. It isn't clear 3443 * which is better, so the first one wins. 3444 */ 3445 for (j = 0; j < ep->edid_nmodes; j++) { 3446 /* 3447 * ignore resolutions that are too big for 3448 * the radeon 3449 */ 3450 if (ep->edid_modes[j].hdisplay > 3451 dp->rd_softc->sc_maxx) 3452 continue; 3453 if (ep->edid_modes[j].vdisplay > 3454 dp->rd_softc->sc_maxy) 3455 continue; 3456 3457 /* 3458 * pick largest resolution, the 3459 * smaller monitor will pan 3460 */ 3461 if ((ep->edid_modes[j].hdisplay >= *x) && 3462 (ep->edid_modes[j].vdisplay >= *y)) { 3463 *x = ep->edid_modes[j].hdisplay; 3464 *y = ep->edid_modes[j].vdisplay; 3465 } 3466 } 3467 } 3468 3469 } else { 3470 struct videomode modes[64]; 3471 int nmodes = 0; 3472 int valid = 0; 3473 3474 for (i = 0; i < dp->rd_ncrtcs; i++) { 3475 /* 3476 * pick the largest resolution in common. 3477 */ 3478 rp = dp->rd_crtcs[i].rc_port; 3479 ep = &rp->rp_edid; 3480 3481 if (!rp->rp_edid_valid) 3482 continue; 3483 3484 if (!valid) { 3485 /* 3486 * Pick the preferred mode for this port 3487 * if available. 3488 */ 3489 if (ep->edid_preferred_mode) { 3490 struct videomode *vmp = 3491 ep->edid_preferred_mode; 3492 3493 if ((vmp->hdisplay <= 3494 dp->rd_softc->sc_maxx) && 3495 (vmp->vdisplay <= 3496 dp->rd_softc->sc_maxy)) 3497 modes[nmodes++] = *vmp; 3498 } else { 3499 3500 /* initialize starting list */ 3501 for (j = 0; j < ep->edid_nmodes; j++) { 3502 /* 3503 * ignore resolutions that are 3504 * too big for the radeon 3505 */ 3506 if (ep->edid_modes[j].hdisplay > 3507 dp->rd_softc->sc_maxx) 3508 continue; 3509 if (ep->edid_modes[j].vdisplay > 3510 dp->rd_softc->sc_maxy) 3511 continue; 3512 3513 modes[nmodes] = 3514 ep->edid_modes[j]; 3515 nmodes++; 3516 } 3517 } 3518 valid = 1; 3519 } else { 3520 /* merge into preexisting list */ 3521 for (j = 0; j < nmodes; j++) { 3522 if (!radeonfb_hasres(ep->edid_modes, 3523 ep->edid_nmodes, 3524 modes[j].hdisplay, 3525 modes[j].vdisplay)) { 3526 modes[j] = modes[nmodes]; 3527 j--; 3528 nmodes--; 3529 } 3530 } 3531 } 3532 } 3533 3534 /* now we have to pick from the merged list */ 3535 for (i = 0; i < nmodes; i++) { 3536 if ((modes[i].hdisplay >= *x) && 3537 (modes[i].vdisplay >= *y)) { 3538 *x = modes[i].hdisplay; 3539 *y = modes[i].vdisplay; 3540 } 3541 } 3542 } 3543 3544 if ((*x == 0) || (*y == 0)) { 3545 /* fallback to safe mode */ 3546 *x = 640; 3547 *y = 480; 3548 } 3549 } 3550 3551 /* 3552 * backlight levels are linear on: 3553 * - RV200, RV250, RV280, RV350 3554 * - but NOT on PowerBook4,3 6,3 6,5 3555 * according to Linux' radeonfb 3556 */ 3557 3558 /* Get the current backlight level for the display. */ 3559 3560 static int 3561 radeonfb_get_backlight(struct radeonfb_display *dp) 3562 { 3563 int s; 3564 uint32_t level; 3565 3566 s = spltty(); 3567 3568 level = radeonfb_get32(dp->rd_softc, RADEON_LVDS_GEN_CNTL); 3569 level &= RADEON_LVDS_BL_MOD_LEV_MASK; 3570 level >>= RADEON_LVDS_BL_MOD_LEV_SHIFT; 3571 3572 /* 3573 * On some chips, we should negate the backlight level. 3574 * XXX Find out on which chips. 3575 */ 3576 if (dp->rd_softc->sc_flags & RFB_INV_BLIGHT) 3577 level = RADEONFB_BACKLIGHT_MAX - level; 3578 3579 splx(s); 3580 3581 return level; 3582 } 3583 3584 /* Set the backlight to the given level for the display. */ 3585 3586 static int 3587 radeonfb_set_backlight(struct radeonfb_display *dp, int level) 3588 { 3589 struct radeonfb_softc *sc; 3590 int rlevel, s; 3591 uint32_t lvds; 3592 3593 s = spltty(); 3594 3595 if (level < 0) 3596 level = 0; 3597 else if (level >= RADEONFB_BACKLIGHT_MAX) 3598 level = RADEONFB_BACKLIGHT_MAX; 3599 3600 sc = dp->rd_softc; 3601 3602 /* On some chips, we should negate the backlight level. */ 3603 if (dp->rd_softc->sc_flags & RFB_INV_BLIGHT) { 3604 rlevel = RADEONFB_BACKLIGHT_MAX - level; 3605 } else 3606 rlevel = level; 3607 3608 callout_stop(&dp->rd_bl_lvds_co); 3609 radeonfb_engine_idle(sc); 3610 3611 /* 3612 * Turn off the display if the backlight is set to 0, since the 3613 * display is useless without backlight anyway. 3614 */ 3615 if (level == 0) 3616 radeonfb_blank(dp, 1); 3617 else if (radeonfb_get_backlight(dp) == 0) 3618 radeonfb_blank(dp, 0); 3619 3620 lvds = radeonfb_get32(sc, RADEON_LVDS_GEN_CNTL); 3621 lvds &= ~RADEON_LVDS_DISPLAY_DIS; 3622 if (!(lvds & RADEON_LVDS_BLON) || !(lvds & RADEON_LVDS_ON)) { 3623 lvds |= dp->rd_bl_lvds_val & RADEON_LVDS_DIGON; 3624 lvds |= RADEON_LVDS_BLON | RADEON_LVDS_EN; 3625 radeonfb_put32(sc, RADEON_LVDS_GEN_CNTL, lvds); 3626 lvds &= ~RADEON_LVDS_BL_MOD_LEV_MASK; 3627 lvds |= rlevel << RADEON_LVDS_BL_MOD_LEV_SHIFT; 3628 lvds |= RADEON_LVDS_ON; 3629 lvds |= dp->rd_bl_lvds_val & RADEON_LVDS_BL_MOD_EN; 3630 } else { 3631 lvds &= ~RADEON_LVDS_BL_MOD_LEV_MASK; 3632 lvds |= rlevel << RADEON_LVDS_BL_MOD_LEV_SHIFT; 3633 radeonfb_put32(sc, RADEON_LVDS_GEN_CNTL, lvds); 3634 } 3635 3636 dp->rd_bl_lvds_val &= ~RADEON_LVDS_STATE_MASK; 3637 dp->rd_bl_lvds_val |= lvds & RADEON_LVDS_STATE_MASK; 3638 /* XXX What is the correct delay? */ 3639 callout_schedule(&dp->rd_bl_lvds_co, 200 * hz); 3640 3641 splx(s); 3642 3643 return 0; 3644 } 3645 3646 /* 3647 * Callout function for delayed operations on the LVDS_GEN_CNTL register. 3648 * Set the delayed bits in the register, and clear the stored delayed 3649 * value. 3650 */ 3651 3652 static void radeonfb_lvds_callout(void *arg) 3653 { 3654 struct radeonfb_display *dp = arg; 3655 int s; 3656 3657 s = splhigh(); 3658 3659 radeonfb_mask32(dp->rd_softc, RADEON_LVDS_GEN_CNTL, ~0, 3660 dp->rd_bl_lvds_val); 3661 dp->rd_bl_lvds_val = 0; 3662 3663 splx(s); 3664 } 3665 3666 static void 3667 radeonfb_brightness_up(device_t dev) 3668 { 3669 struct radeonfb_softc *sc = device_private(dev); 3670 int level; 3671 3672 /* we assume the main display is the first one - need a better way */ 3673 if (sc->sc_ndisplays < 1) return; 3674 level = radeonfb_get_backlight(&sc->sc_displays[0]); 3675 level = min(RADEONFB_BACKLIGHT_MAX, level + 5); 3676 radeonfb_set_backlight(&sc->sc_displays[0], level); 3677 } 3678 3679 static void 3680 radeonfb_brightness_down(device_t dev) 3681 { 3682 struct radeonfb_softc *sc = device_private(dev); 3683 int level; 3684 3685 /* we assume the main display is the first one - need a better way */ 3686 if (sc->sc_ndisplays < 1) return; 3687 level = radeonfb_get_backlight(&sc->sc_displays[0]); 3688 level = max(0, level - 5); 3689 radeonfb_set_backlight(&sc->sc_displays[0], level); 3690 } 3691
Indexes created Wed Sep 24 05:09:52 GMT 2025