radeonfb.c revision 1.53.2.1
1 /* $NetBSD: radeonfb.c,v 1.53.2.1 2012/03/21 16:12:18 riz Exp $ */ 2 3 /*- 4 * Copyright (c) 2006 Itronix Inc. 5 * All rights reserved. 6 * 7 * Written by Garrett D'Amore for Itronix Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. The name of Itronix Inc. may not be used to endorse 18 * or promote products derived from this software without specific 19 * prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY ITRONIX INC. ``AS IS'' AND ANY EXPRESS 22 * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 23 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL ITRONIX INC. BE LIABLE FOR ANY 25 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE 27 * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 29 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 30 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 31 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * ATI Technologies Inc. ("ATI") has not assisted in the creation of, and 36 * does not endorse, this software. ATI will not be responsible or liable 37 * for any actual or alleged damage or loss caused by or in connection with 38 * the use of or reliance on this software. 39 */ 40 41 /* 42 * Portions of this code were taken from XFree86's Radeon driver, which bears 43 * this notice: 44 * 45 * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and 46 * VA Linux Systems Inc., Fremont, California. 47 * 48 * All Rights Reserved. 49 * 50 * Permission is hereby granted, free of charge, to any person obtaining 51 * a copy of this software and associated documentation files (the 52 * "Software"), to deal in the Software without restriction, including 53 * without limitation on the rights to use, copy, modify, merge, 54 * publish, distribute, sublicense, and/or sell copies of the Software, 55 * and to permit persons to whom the Software is furnished to do so, 56 * subject to the following conditions: 57 * 58 * The above copyright notice and this permission notice (including the 59 * next paragraph) shall be included in all copies or substantial 60 * portions of the Software. 61 * 62 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 63 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 64 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 65 * NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR 66 * THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 67 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 68 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 69 * DEALINGS IN THE SOFTWARE. 70 */ 71 72 #include <sys/cdefs.h> 73 __KERNEL_RCSID(0, "$NetBSD: radeonfb.c,v 1.53.2.1 2012/03/21 16:12:18 riz Exp $"); 74 75 #include <sys/param.h> 76 #include <sys/systm.h> 77 #include <sys/device.h> 78 #include <sys/malloc.h> 79 #include <sys/bus.h> 80 #include <sys/kernel.h> 81 #include <sys/lwp.h> 82 #include <sys/kauth.h> 83 84 #include <dev/wscons/wsdisplayvar.h> 85 #include <dev/wscons/wsconsio.h> 86 #include <dev/wsfont/wsfont.h> 87 #include <dev/rasops/rasops.h> 88 #include <dev/videomode/videomode.h> 89 #include <dev/videomode/edidvar.h> 90 #include <dev/wscons/wsdisplay_vconsvar.h> 91 #include <dev/pci/wsdisplay_pci.h> 92 93 #include <dev/pci/pcidevs.h> 94 #include <dev/pci/pcireg.h> 95 #include <dev/pci/pcivar.h> 96 #include <dev/pci/pciio.h> 97 #include <dev/pci/radeonfbreg.h> 98 #include <dev/pci/radeonfbvar.h> 99 #include "opt_radeonfb.h" 100 #include "opt_vcons.h" 101 102 #ifdef RADEONFB_DEPTH_32 103 #define RADEONFB_DEFAULT_DEPTH 32 104 #else 105 #define RADEONFB_DEFAULT_DEPTH 8 106 #endif 107 108 static int radeonfb_match(device_t, cfdata_t, void *); 109 static void radeonfb_attach(device_t, device_t, void *); 110 static int radeonfb_ioctl(void *, void *, unsigned long, void *, int, 111 struct lwp *); 112 static paddr_t radeonfb_mmap(void *, void *, off_t, int); 113 static int radeonfb_scratch_test(struct radeonfb_softc *, int, uint32_t); 114 static void radeonfb_loadbios(struct radeonfb_softc *, 115 const struct pci_attach_args *); 116 117 static uintmax_t radeonfb_getprop_num(struct radeonfb_softc *, const char *, 118 uintmax_t); 119 static int radeonfb_getclocks(struct radeonfb_softc *); 120 static int radeonfb_gettmds(struct radeonfb_softc *); 121 static int radeonfb_calc_dividers(struct radeonfb_softc *, uint32_t, 122 uint32_t *, uint32_t *); 123 static int radeonfb_getconnectors(struct radeonfb_softc *); 124 static const struct videomode *radeonfb_modelookup(const char *); 125 static void radeonfb_init_screen(void *, struct vcons_screen *, int, long *); 126 static void radeonfb_pllwriteupdate(struct radeonfb_softc *, int); 127 static void radeonfb_pllwaitatomicread(struct radeonfb_softc *, int); 128 static void radeonfb_program_vclk(struct radeonfb_softc *, int, int); 129 static void radeonfb_modeswitch(struct radeonfb_display *); 130 static void radeonfb_setcrtc(struct radeonfb_display *, int); 131 static void radeonfb_init_misc(struct radeonfb_softc *); 132 static void radeonfb_set_fbloc(struct radeonfb_softc *); 133 static void radeonfb_init_palette(struct radeonfb_softc *, int); 134 static void radeonfb_r300cg_workaround(struct radeonfb_softc *); 135 136 static int radeonfb_isblank(struct radeonfb_display *); 137 static void radeonfb_blank(struct radeonfb_display *, int); 138 static int radeonfb_set_cursor(struct radeonfb_display *, 139 struct wsdisplay_cursor *); 140 static int radeonfb_set_curpos(struct radeonfb_display *, 141 struct wsdisplay_curpos *); 142 143 /* acceleration support */ 144 static void radeonfb_rectfill(struct radeonfb_display *, int dstx, int dsty, 145 int width, int height, uint32_t color); 146 static void radeonfb_bitblt(struct radeonfb_display *, int srcx, int srcy, 147 int dstx, int dsty, int width, int height, int rop, uint32_t mask); 148 149 /* hw cursor support */ 150 static void radeonfb_cursor_cmap(struct radeonfb_display *); 151 static void radeonfb_cursor_shape(struct radeonfb_display *); 152 static void radeonfb_cursor_position(struct radeonfb_display *); 153 static void radeonfb_cursor_visible(struct radeonfb_display *); 154 static void radeonfb_cursor_update(struct radeonfb_display *, unsigned); 155 156 static void radeonfb_wait_fifo(struct radeonfb_softc *, int); 157 static void radeonfb_engine_idle(struct radeonfb_softc *); 158 static void radeonfb_engine_flush(struct radeonfb_softc *); 159 static void radeonfb_engine_reset(struct radeonfb_softc *); 160 static void radeonfb_engine_init(struct radeonfb_display *); 161 static inline void radeonfb_unclip(struct radeonfb_softc *); 162 163 static void radeonfb_eraserows(void *, int, int, long); 164 static void radeonfb_erasecols(void *, int, int, int, long); 165 static void radeonfb_copyrows(void *, int, int, int); 166 static void radeonfb_copycols(void *, int, int, int, int); 167 static void radeonfb_cursor(void *, int, int, int); 168 static void radeonfb_putchar(void *, int, int, unsigned, long); 169 static void radeonfb_putchar_aa32(void *, int, int, unsigned, long); 170 static void radeonfb_putchar_wrapper(void *, int, int, unsigned, long); 171 172 static int radeonfb_set_backlight(struct radeonfb_display *, int); 173 static int radeonfb_get_backlight(struct radeonfb_display *); 174 static void radeonfb_switch_backlight(struct radeonfb_display *, int); 175 static void radeonfb_lvds_callout(void *); 176 177 static void radeonfb_brightness_up(device_t); 178 static void radeonfb_brightness_down(device_t); 179 180 static struct videomode *radeonfb_best_refresh(struct videomode *, 181 struct videomode *); 182 static void radeonfb_pickres(struct radeonfb_display *, uint16_t *, 183 uint16_t *, int); 184 static const struct videomode *radeonfb_port_mode(struct radeonfb_softc *, 185 struct radeonfb_port *, int, int); 186 187 static int radeonfb_drm_print(void *, const char *); 188 189 #ifdef RADEONFB_DEBUG 190 int radeon_debug = 1; 191 #define DPRINTF(x) \ 192 if (radeon_debug) printf x 193 #define PRINTREG(r) DPRINTF((#r " = %08x\n", GET32(sc, r))) 194 #define PRINTPLL(r) DPRINTF((#r " = %08x\n", GETPLL(sc, r))) 195 #else 196 #define DPRINTF(x) 197 #define PRINTREG(r) 198 #define PRINTPLL(r) 199 #endif 200 201 #define ROUNDUP(x,y) (((x) + ((y) - 1)) & ~((y) - 1)) 202 203 #ifndef RADEON_DEFAULT_MODE 204 /* any reasonably modern display should handle this */ 205 #define RADEON_DEFAULT_MODE "1024x768x60" 206 #endif 207 208 extern const u_char rasops_cmap[768]; 209 210 const char *radeonfb_default_mode = RADEON_DEFAULT_MODE; 211 212 static struct { 213 int size; /* minimum memory size (MB) */ 214 int maxx; /* maximum x dimension */ 215 int maxy; /* maximum y dimension */ 216 int maxbpp; /* maximum bpp */ 217 int maxdisp; /* maximum logical display count */ 218 } radeonfb_limits[] = { 219 { 32, 2048, 1536, 32, 2 }, 220 { 16, 1600, 1200, 32, 2 }, 221 { 8, 1600, 1200, 32, 1 }, 222 { 0, 0, 0, 0, 0 }, 223 }; 224 225 static struct wsscreen_descr radeonfb_stdscreen = { 226 "fb", /* name */ 227 0, 0, /* ncols, nrows */ 228 NULL, /* textops */ 229 8, 16, /* fontwidth, fontheight */ 230 WSSCREEN_WSCOLORS, /* capabilities */ 231 0, /* modecookie */ 232 }; 233 234 struct wsdisplay_accessops radeonfb_accessops = { 235 radeonfb_ioctl, 236 radeonfb_mmap, 237 NULL, /* vcons_alloc_screen */ 238 NULL, /* vcons_free_screen */ 239 NULL, /* vcons_show_screen */ 240 NULL, /* load_font */ 241 NULL, /* pollc */ 242 NULL, /* scroll */ 243 }; 244 245 static struct { 246 uint16_t devid; 247 uint16_t family; 248 uint16_t flags; 249 } radeonfb_devices[] = 250 { 251 /* R100 family */ 252 { PCI_PRODUCT_ATI_RADEON_R100_QD, RADEON_R100, 0 }, 253 { PCI_PRODUCT_ATI_RADEON_R100_QE, RADEON_R100, 0 }, 254 { PCI_PRODUCT_ATI_RADEON_R100_QF, RADEON_R100, 0 }, 255 { PCI_PRODUCT_ATI_RADEON_R100_QG, RADEON_R100, 0 }, 256 257 /* RV100 family */ 258 { PCI_PRODUCT_ATI_RADEON_RV100_LY, RADEON_RV100, RFB_MOB }, 259 { PCI_PRODUCT_ATI_RADEON_RV100_LZ, RADEON_RV100, RFB_MOB }, 260 { PCI_PRODUCT_ATI_RADEON_RV100_QY, RADEON_RV100, 0 }, 261 { PCI_PRODUCT_ATI_RADEON_RV100_QZ, RADEON_RV100, 0 }, 262 263 /* RS100 family */ 264 { PCI_PRODUCT_ATI_RADEON_RS100_4136, RADEON_RS100, 0 }, 265 { PCI_PRODUCT_ATI_RADEON_RS100_4336, RADEON_RS100, RFB_MOB }, 266 267 /* RS200/RS250 family */ 268 { PCI_PRODUCT_ATI_RADEON_RS200_4337, RADEON_RS200, RFB_MOB }, 269 { PCI_PRODUCT_ATI_RADEON_RS200_A7, RADEON_RS200, 0 }, 270 { PCI_PRODUCT_ATI_RADEON_RS250_B7, RADEON_RS200, RFB_MOB }, 271 { PCI_PRODUCT_ATI_RADEON_RS250_D7, RADEON_RS200, 0 }, 272 273 /* R200 family */ 274 /* add more R200 products? , 5148 */ 275 { PCI_PRODUCT_ATI_RADEON_R200_BB, RADEON_R200, 0 }, 276 { PCI_PRODUCT_ATI_RADEON_R200_BC, RADEON_R200, 0 }, 277 { PCI_PRODUCT_ATI_RADEON_R200_QH, RADEON_R200, 0 }, 278 { PCI_PRODUCT_ATI_RADEON_R200_QL, RADEON_R200, 0 }, 279 { PCI_PRODUCT_ATI_RADEON_R200_QM, RADEON_R200, 0 }, 280 281 /* RV200 family */ 282 { PCI_PRODUCT_ATI_RADEON_RV200_LW, RADEON_RV200, RFB_MOB }, 283 { PCI_PRODUCT_ATI_RADEON_RV200_LX, RADEON_RV200, RFB_MOB }, 284 { PCI_PRODUCT_ATI_RADEON_RV200_QW, RADEON_RV200, 0 }, 285 { PCI_PRODUCT_ATI_RADEON_RV200_QX, RADEON_RV200, 0 }, 286 287 /* RV250 family */ 288 { PCI_PRODUCT_ATI_RADEON_RV250_4966, RADEON_RV250, 0 }, 289 { PCI_PRODUCT_ATI_RADEON_RV250_4967, RADEON_RV250, 0 }, 290 { PCI_PRODUCT_ATI_RADEON_RV250_4C64, RADEON_RV250, RFB_MOB }, 291 { PCI_PRODUCT_ATI_RADEON_RV250_4C66, RADEON_RV250, RFB_MOB }, 292 { PCI_PRODUCT_ATI_RADEON_RV250_4C67, RADEON_RV250, RFB_MOB }, 293 294 /* RS300 family */ 295 { PCI_PRODUCT_ATI_RADEON_RS300_X5, RADEON_RS300, 0 }, 296 { PCI_PRODUCT_ATI_RADEON_RS300_X4, RADEON_RS300, 0 }, 297 { PCI_PRODUCT_ATI_RADEON_RS300_7834, RADEON_RS300, 0 }, 298 { PCI_PRODUCT_ATI_RADEON_RS300_7835, RADEON_RS300, RFB_MOB }, 299 300 /* RV280 family */ 301 { PCI_PRODUCT_ATI_RADEON_RV280_5960, RADEON_RV280, 0 }, 302 { PCI_PRODUCT_ATI_RADEON_RV280_5961, RADEON_RV280, 0 }, 303 { PCI_PRODUCT_ATI_RADEON_RV280_5962, RADEON_RV280, 0 }, 304 { PCI_PRODUCT_ATI_RADEON_RV280_5963, RADEON_RV280, 0 }, 305 { PCI_PRODUCT_ATI_RADEON_RV280_5964, RADEON_RV280, 0 }, 306 { PCI_PRODUCT_ATI_RADEON_RV280_5C61, RADEON_RV280, RFB_MOB }, 307 { PCI_PRODUCT_ATI_RADEON_RV280_5C63, RADEON_RV280, RFB_MOB }, 308 309 /* R300 family */ 310 { PCI_PRODUCT_ATI_RADEON_R300_AD, RADEON_R300, 0 }, 311 { PCI_PRODUCT_ATI_RADEON_R300_AE, RADEON_R300, 0 }, 312 { PCI_PRODUCT_ATI_RADEON_R300_AF, RADEON_R300, 0 }, 313 { PCI_PRODUCT_ATI_RADEON_R300_AG, RADEON_R300, 0 }, 314 { PCI_PRODUCT_ATI_RADEON_R300_ND, RADEON_R300, 0 }, 315 { PCI_PRODUCT_ATI_RADEON_R300_NE, RADEON_R300, 0 }, 316 { PCI_PRODUCT_ATI_RADEON_R300_NF, RADEON_R300, 0 }, 317 { PCI_PRODUCT_ATI_RADEON_R300_NG, RADEON_R300, 0 }, 318 319 /* RV350/RV360 family */ 320 { PCI_PRODUCT_ATI_RADEON_RV350_AP, RADEON_RV350, 0 }, 321 { PCI_PRODUCT_ATI_RADEON_RV350_AQ, RADEON_RV350, 0 }, 322 { PCI_PRODUCT_ATI_RADEON_RV360_AR, RADEON_RV350, 0 }, 323 { PCI_PRODUCT_ATI_RADEON_RV350_AS, RADEON_RV350, 0 }, 324 { PCI_PRODUCT_ATI_RADEON_RV350_AT, RADEON_RV350, 0 }, 325 { PCI_PRODUCT_ATI_RADEON_RV350_AV, RADEON_RV350, 0 }, 326 { PCI_PRODUCT_ATI_RADEON_RV350_NP, RADEON_RV350, RFB_MOB }, 327 { PCI_PRODUCT_ATI_RADEON_RV350_NQ, RADEON_RV350, RFB_MOB }, 328 { PCI_PRODUCT_ATI_RADEON_RV350_NR, RADEON_RV350, RFB_MOB }, 329 { PCI_PRODUCT_ATI_RADEON_RV350_NS, RADEON_RV350, RFB_MOB }, 330 { PCI_PRODUCT_ATI_RADEON_RV350_NT, RADEON_RV350, RFB_MOB }, 331 { PCI_PRODUCT_ATI_RADEON_RV350_NV, RADEON_RV350, RFB_MOB }, 332 333 /* R350/R360 family */ 334 { PCI_PRODUCT_ATI_RADEON_R350_AH, RADEON_R350, 0 }, 335 { PCI_PRODUCT_ATI_RADEON_R350_AI, RADEON_R350, 0 }, 336 { PCI_PRODUCT_ATI_RADEON_R350_AJ, RADEON_R350, 0 }, 337 { PCI_PRODUCT_ATI_RADEON_R350_AK, RADEON_R350, 0 }, 338 { PCI_PRODUCT_ATI_RADEON_R350_NH, RADEON_R350, 0 }, 339 { PCI_PRODUCT_ATI_RADEON_R350_NI, RADEON_R350, 0 }, 340 { PCI_PRODUCT_ATI_RADEON_R350_NK, RADEON_R350, 0 }, 341 { PCI_PRODUCT_ATI_RADEON_R360_NJ, RADEON_R350, 0 }, 342 343 /* RV380/RV370 family */ 344 { PCI_PRODUCT_ATI_RADEON_RV380_3150, RADEON_RV380, RFB_MOB }, 345 { PCI_PRODUCT_ATI_RADEON_RV380_3154, RADEON_RV380, RFB_MOB }, 346 { PCI_PRODUCT_ATI_RADEON_RV380_3E50, RADEON_RV380, 0 }, 347 { PCI_PRODUCT_ATI_RADEON_RV380_3E54, RADEON_RV380, 0 }, 348 { PCI_PRODUCT_ATI_RADEON_RV370_5460, RADEON_RV380, RFB_MOB }, 349 { PCI_PRODUCT_ATI_RADEON_RV370_5464, RADEON_RV380, RFB_MOB }, 350 { PCI_PRODUCT_ATI_RADEON_RV370_5B60, RADEON_RV380, 0 }, 351 { PCI_PRODUCT_ATI_RADEON_RV370_5B64, RADEON_RV380, 0 }, 352 { PCI_PRODUCT_ATI_RADEON_RV370_5B65, RADEON_RV380, 0 }, 353 354 /* R420/R423 family */ 355 { PCI_PRODUCT_ATI_RADEON_R420_JH, RADEON_R420, 0 }, 356 { PCI_PRODUCT_ATI_RADEON_R420_JI, RADEON_R420, 0 }, 357 { PCI_PRODUCT_ATI_RADEON_R420_JJ, RADEON_R420, 0 }, 358 { PCI_PRODUCT_ATI_RADEON_R420_JK, RADEON_R420, 0 }, 359 { PCI_PRODUCT_ATI_RADEON_R420_JL, RADEON_R420, 0 }, 360 { PCI_PRODUCT_ATI_RADEON_R420_JM, RADEON_R420, 0 }, 361 { PCI_PRODUCT_ATI_RADEON_R420_JN, RADEON_R420, RFB_MOB }, 362 { PCI_PRODUCT_ATI_RADEON_R420_JP, RADEON_R420, 0 }, 363 { PCI_PRODUCT_ATI_RADEON_R423_UH, RADEON_R420, 0 }, 364 { PCI_PRODUCT_ATI_RADEON_R423_UI, RADEON_R420, 0 }, 365 { PCI_PRODUCT_ATI_RADEON_R423_UJ, RADEON_R420, 0 }, 366 { PCI_PRODUCT_ATI_RADEON_R423_UK, RADEON_R420, 0 }, 367 { PCI_PRODUCT_ATI_RADEON_R423_UQ, RADEON_R420, 0 }, 368 { PCI_PRODUCT_ATI_RADEON_R423_UR, RADEON_R420, 0 }, 369 { PCI_PRODUCT_ATI_RADEON_R423_UT, RADEON_R420, 0 }, 370 { PCI_PRODUCT_ATI_RADEON_R423_5D57, RADEON_R420, 0 }, 371 { PCI_PRODUCT_ATI_RADEON_R430_554F, RADEON_R420, 0 }, 372 373 { 0, 0, 0 } 374 }; 375 376 static struct { 377 int divider; 378 int mask; 379 } radeonfb_dividers[] = { 380 { 1, 0 }, 381 { 2, 1 }, 382 { 3, 4 }, 383 { 4, 2 }, 384 { 6, 6 }, 385 { 8, 3 }, 386 { 12, 7 }, 387 { 0, 0 } 388 }; 389 390 /* 391 * This table taken from X11. 392 */ 393 static const struct { 394 int family; 395 struct radeon_tmds_pll plls[4]; 396 } radeonfb_tmds_pll[] = { 397 { RADEON_R100, {{12000, 0xa1b}, {-1, 0xa3f}}}, 398 { RADEON_RV100, {{12000, 0xa1b}, {-1, 0xa3f}}}, 399 { RADEON_RS100, {{0, 0}}}, 400 { RADEON_RV200, {{15000, 0xa1b}, {-1, 0xa3f}}}, 401 { RADEON_RS200, {{15000, 0xa1b}, {-1, 0xa3f}}}, 402 { RADEON_R200, {{15000, 0xa1b}, {-1, 0xa3f}}}, 403 { RADEON_RV250, {{15500, 0x81b}, {-1, 0x83f}}}, 404 { RADEON_RS300, {{0, 0}}}, 405 { RADEON_RV280, {{13000, 0x400f4}, {15000, 0x400f7}}}, 406 { RADEON_R300, {{-1, 0xb01cb}}}, 407 { RADEON_R350, {{-1, 0xb01cb}}}, 408 { RADEON_RV350, {{15000, 0xb0155}, {-1, 0xb01cb}}}, 409 { RADEON_RV380, {{15000, 0xb0155}, {-1, 0xb01cb}}}, 410 { RADEON_R420, {{-1, 0xb01cb}}}, 411 }; 412 413 #define RADEONFB_BACKLIGHT_MAX 255 /* Maximum backlight level. */ 414 415 416 CFATTACH_DECL_NEW(radeonfb, sizeof (struct radeonfb_softc), 417 radeonfb_match, radeonfb_attach, NULL, NULL); 418 419 static int 420 radeonfb_match(device_t parent, cfdata_t match, void *aux) 421 { 422 const struct pci_attach_args *pa = aux; 423 int i; 424 425 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_ATI) 426 return 0; 427 428 for (i = 0; radeonfb_devices[i].devid; i++) { 429 if (PCI_PRODUCT(pa->pa_id) == radeonfb_devices[i].devid) 430 return 100; /* high to defeat VGA/VESA */ 431 } 432 433 return 0; 434 } 435 436 static void 437 radeonfb_attach(device_t parent, device_t dev, void *aux) 438 { 439 struct radeonfb_softc *sc = device_private(dev); 440 const struct pci_attach_args *pa = aux; 441 const char *mptr; 442 bus_size_t bsz; 443 pcireg_t screg; 444 int i, j, fg, bg, ul, flags; 445 uint32_t v; 446 447 sc->sc_dev = dev; 448 sc->sc_id = pa->pa_id; 449 for (i = 0; radeonfb_devices[i].devid; i++) { 450 if (PCI_PRODUCT(sc->sc_id) == radeonfb_devices[i].devid) 451 break; 452 } 453 454 pci_aprint_devinfo(pa, NULL); 455 456 DPRINTF((prop_dictionary_externalize(device_properties(dev)))); 457 458 KASSERT(radeonfb_devices[i].devid != 0); 459 sc->sc_pt = pa->pa_tag; 460 sc->sc_iot = pa->pa_iot; 461 sc->sc_pc = pa->pa_pc; 462 sc->sc_family = radeonfb_devices[i].family; 463 sc->sc_flags = radeonfb_devices[i].flags; 464 465 /* enable memory and IO access */ 466 screg = pci_conf_read(sc->sc_pc, sc->sc_pt, PCI_COMMAND_STATUS_REG); 467 screg |= PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE; 468 pci_conf_write(sc->sc_pc, sc->sc_pt, PCI_COMMAND_STATUS_REG, screg); 469 470 /* 471 * Some flags are general to entire chip families, and rather 472 * than clutter up the table with them, we go ahead and set 473 * them here. 474 */ 475 switch (sc->sc_family) { 476 case RADEON_RS100: 477 case RADEON_RS200: 478 sc->sc_flags |= RFB_IGP | RFB_RV100; 479 break; 480 481 case RADEON_RV100: 482 case RADEON_RV200: 483 case RADEON_RV250: 484 case RADEON_RV280: 485 sc->sc_flags |= RFB_RV100; 486 break; 487 488 case RADEON_RS300: 489 sc->sc_flags |= RFB_SDAC | RFB_IGP | RFB_RV100; 490 break; 491 492 case RADEON_R300: 493 case RADEON_RV350: 494 case RADEON_R350: 495 case RADEON_RV380: 496 case RADEON_R420: 497 /* newer chips */ 498 sc->sc_flags |= RFB_R300; 499 break; 500 501 case RADEON_R100: 502 sc->sc_flags |= RFB_NCRTC2; 503 break; 504 } 505 506 if ((sc->sc_family == RADEON_RV200) || 507 (sc->sc_family == RADEON_RV250) || 508 (sc->sc_family == RADEON_RV280) || 509 (sc->sc_family == RADEON_RV350)) { 510 bool inverted = 0; 511 /* backlight level is linear */ 512 DPRINTF(("found RV* chip, backlight is supposedly linear\n")); 513 prop_dictionary_get_bool(device_properties(sc->sc_dev), 514 "backlight_level_reverted", &inverted); 515 if (inverted) { 516 DPRINTF(("nope, it's inverted\n")); 517 sc->sc_flags |= RFB_INV_BLIGHT; 518 } 519 } else 520 sc->sc_flags |= RFB_INV_BLIGHT; 521 522 /* 523 * XXX: to support true multihead, this must change. 524 */ 525 sc->sc_ndisplays = 1; 526 527 /* XXX: */ 528 if (!HAS_CRTC2(sc)) { 529 sc->sc_ndisplays = 1; 530 } 531 532 if (pci_mapreg_map(pa, RADEON_MAPREG_MMIO, PCI_MAPREG_TYPE_MEM, 0, 533 &sc->sc_regt, &sc->sc_regh, &sc->sc_regaddr, 534 &sc->sc_regsz) != 0) { 535 aprint_error("%s: unable to map registers!\n", XNAME(sc)); 536 goto error; 537 } 538 539 if (pci_mapreg_info(sc->sc_pc, sc->sc_pt, PCI_MAPREG_ROM, 540 PCI_MAPREG_TYPE_ROM, &sc->sc_romaddr, &sc->sc_romsz, &flags) != 0) 541 { 542 aprint_error("%s: unable to find ROM!\n", XNAME(sc)); 543 goto error; 544 } 545 sc->sc_romt = sc->sc_memt; 546 547 /* scratch register test... */ 548 if (radeonfb_scratch_test(sc, RADEON_BIOS_0_SCRATCH, 0x55555555) || 549 radeonfb_scratch_test(sc, RADEON_BIOS_0_SCRATCH, 0xaaaaaaaa)) { 550 aprint_error("%s: scratch register test failed!\n", XNAME(sc)); 551 goto error; 552 } 553 554 PRINTREG(RADEON_BIOS_4_SCRATCH); 555 PRINTREG(RADEON_FP_GEN_CNTL); 556 sc->sc_fp_gen_cntl = GET32(sc, RADEON_FP_GEN_CNTL); 557 PRINTREG(RADEON_FP2_GEN_CNTL); 558 PRINTREG(RADEON_TMDS_CNTL); 559 PRINTREG(RADEON_TMDS_TRANSMITTER_CNTL); 560 PRINTREG(RADEON_TMDS_PLL_CNTL); 561 PRINTREG(RADEON_LVDS_GEN_CNTL); 562 PRINTREG(RADEON_FP_HORZ_STRETCH); 563 PRINTREG(RADEON_FP_VERT_STRETCH); 564 565 /* XXX: RV100 specific */ 566 PUT32(sc, RADEON_TMDS_PLL_CNTL, 0xa27); 567 568 PATCH32(sc, RADEON_TMDS_TRANSMITTER_CNTL, 569 RADEON_TMDS_TRANSMITTER_PLLEN, 570 RADEON_TMDS_TRANSMITTER_PLLEN | RADEON_TMDS_TRANSMITTER_PLLRST); 571 572 radeonfb_i2c_init(sc); 573 574 radeonfb_loadbios(sc, pa); 575 576 #ifdef RADEONFB_BIOS_INIT 577 if (radeonfb_bios_init(sc)) { 578 aprint_error("%s: BIOS inititialization failed\n", XNAME(sc)); 579 } 580 #endif 581 582 if (radeonfb_getclocks(sc)) { 583 aprint_error("%s: Unable to get reference clocks from BIOS\n", 584 XNAME(sc)); 585 goto error; 586 } 587 588 if (radeonfb_gettmds(sc)) { 589 aprint_error("%s: Unable to identify TMDS PLL settings\n", 590 XNAME(sc)); 591 goto error; 592 } 593 594 aprint_verbose("%s: refclk = %d.%03d MHz, refdiv = %d " 595 "minpll = %d, maxpll = %d\n", XNAME(sc), 596 (int)sc->sc_refclk / 1000, (int)sc->sc_refclk % 1000, 597 (int)sc->sc_refdiv, (int)sc->sc_minpll, (int)sc->sc_maxpll); 598 599 radeonfb_getconnectors(sc); 600 601 radeonfb_set_fbloc(sc); 602 603 for (i = 0; radeonfb_limits[i].size; i++) { 604 if (sc->sc_memsz >= radeonfb_limits[i].size) { 605 sc->sc_maxx = radeonfb_limits[i].maxx; 606 sc->sc_maxy = radeonfb_limits[i].maxy; 607 sc->sc_maxbpp = radeonfb_limits[i].maxbpp; 608 /* framebuffer offset, start at a 4K page */ 609 sc->sc_fboffset = sc->sc_memsz / 610 radeonfb_limits[i].maxdisp; 611 /* 612 * we use the fbsize to figure out where we can store 613 * things like cursor data. 614 */ 615 sc->sc_fbsize = 616 ROUNDUP(ROUNDUP(sc->sc_maxx * sc->sc_maxbpp / 8 , 617 RADEON_STRIDEALIGN) * sc->sc_maxy, 618 4096); 619 break; 620 } 621 } 622 623 624 radeonfb_init_misc(sc); 625 radeonfb_init_palette(sc, 0); 626 if (HAS_CRTC2(sc)) 627 radeonfb_init_palette(sc, 1); 628 629 /* program the DAC wirings */ 630 for (i = 0; i < (HAS_CRTC2(sc) ? 2 : 1); i++) { 631 switch (sc->sc_ports[i].rp_dac_type) { 632 case RADEON_DAC_PRIMARY: 633 PATCH32(sc, RADEON_DAC_CNTL2, 634 i ? RADEON_DAC2_DAC_CLK_SEL : 0, 635 ~RADEON_DAC2_DAC_CLK_SEL); 636 break; 637 case RADEON_DAC_TVDAC: 638 /* we always use the TVDAC to drive a secondary analog 639 * CRT for now. if we ever support TV-out this will 640 * have to change. 641 */ 642 SET32(sc, RADEON_DAC_CNTL2, 643 RADEON_DAC2_DAC2_CLK_SEL); 644 PATCH32(sc, RADEON_DISP_HW_DEBUG, 645 i ? 0 : RADEON_CRT2_DISP1_SEL, 646 ~RADEON_CRT2_DISP1_SEL); 647 break; 648 } 649 } 650 PRINTREG(RADEON_DAC_CNTL2); 651 PRINTREG(RADEON_DISP_HW_DEBUG); 652 653 /* other DAC programming */ 654 v = GET32(sc, RADEON_DAC_CNTL); 655 v &= (RADEON_DAC_RANGE_CNTL_MASK | RADEON_DAC_BLANKING); 656 v |= RADEON_DAC_MASK_ALL | RADEON_DAC_8BIT_EN; 657 PUT32(sc, RADEON_DAC_CNTL, v); 658 PRINTREG(RADEON_DAC_CNTL); 659 660 /* XXX: this may need more investigation */ 661 PUT32(sc, RADEON_TV_DAC_CNTL, 0x00280203); 662 PRINTREG(RADEON_TV_DAC_CNTL); 663 664 /* enable TMDS */ 665 SET32(sc, RADEON_FP_GEN_CNTL, 666 RADEON_FP_TMDS_EN | 667 RADEON_FP_CRTC_DONT_SHADOW_VPAR | 668 RADEON_FP_CRTC_DONT_SHADOW_HEND); 669 /* 670 * XXX 671 * no idea why this is necessary - if I do not clear this bit on my 672 * iBook G4 the screen remains black, even though it's already clear. 673 * It needs to be set on my Sun XVR-100 for the DVI port to work 674 */ 675 676 if (sc->sc_fp_gen_cntl & RADEON_FP_SEL_CRTC2) { 677 SET32(sc, RADEON_FP_GEN_CNTL, RADEON_FP_SEL_CRTC2); 678 } else 679 CLR32(sc, RADEON_FP_GEN_CNTL, RADEON_FP_SEL_CRTC2); 680 681 if (HAS_CRTC2(sc)) 682 SET32(sc, RADEON_FP2_GEN_CNTL, RADEON_FP2_SRC_SEL_CRTC2); 683 684 /* 685 * we use bus_space_map instead of pci_mapreg, because we don't 686 * need the full aperature space. no point in wasting virtual 687 * address space we don't intend to use, right? 688 */ 689 if ((sc->sc_memsz < (4096 * 1024)) || 690 (pci_mapreg_info(sc->sc_pc, sc->sc_pt, RADEON_MAPREG_VRAM, 691 PCI_MAPREG_TYPE_MEM, &sc->sc_memaddr, &bsz, NULL) != 0) || 692 (bsz < sc->sc_memsz)) { 693 sc->sc_memsz = 0; 694 aprint_error("%s: Bad frame buffer configuration\n", 695 XNAME(sc)); 696 goto error; 697 } 698 699 /* 64 MB should be enough -- more just wastes map entries */ 700 if (sc->sc_memsz > (64 << 20)) 701 sc->sc_memsz = (64 << 20); 702 703 sc->sc_memt = pa->pa_memt; 704 if (bus_space_map(sc->sc_memt, sc->sc_memaddr, sc->sc_memsz, 705 BUS_SPACE_MAP_LINEAR, &sc->sc_memh) != 0) { 706 sc->sc_memsz = 0; 707 aprint_error("%s: Unable to map frame buffer\n", XNAME(sc)); 708 goto error; 709 } 710 711 aprint_normal("%s: %d MB aperture at 0x%08x, " 712 "%d KB registers at 0x%08x\n", XNAME(sc), 713 (int)sc->sc_memsz >> 20, (unsigned)sc->sc_memaddr, 714 (int)sc->sc_regsz >> 10, (unsigned)sc->sc_regaddr); 715 716 /* setup default video mode from devprop (allows PROM override) */ 717 sc->sc_defaultmode = radeonfb_default_mode; 718 if (prop_dictionary_get_cstring_nocopy(device_properties(sc->sc_dev), 719 "videomode", &mptr)) { 720 721 strncpy(sc->sc_modebuf, mptr, sizeof(sc->sc_modebuf)); 722 sc->sc_defaultmode = sc->sc_modebuf; 723 } 724 725 /* initialize some basic display parameters */ 726 for (i = 0; i < sc->sc_ndisplays; i++) { 727 struct radeonfb_display *dp = &sc->sc_displays[i]; 728 struct rasops_info *ri; 729 long defattr; 730 struct wsemuldisplaydev_attach_args aa; 731 732 /* 733 * Figure out how many "displays" (desktops) we are going to 734 * support. If more than one, then each CRTC gets its own 735 * programming. 736 * 737 * XXX: this code needs to change to support mergedfb. 738 * XXX: would be nice to allow this to be overridden 739 */ 740 if (HAS_CRTC2(sc) && (sc->sc_ndisplays == 1)) { 741 DPRINTF(("dual crtcs!\n")); 742 dp->rd_ncrtcs = 2; 743 dp->rd_crtcs[0].rc_number = 0; 744 dp->rd_crtcs[1].rc_number = 1; 745 } else { 746 dp->rd_ncrtcs = 1; 747 dp->rd_crtcs[0].rc_number = i; 748 } 749 750 /* set up port pointer */ 751 for (j = 0; j < dp->rd_ncrtcs; j++) { 752 dp->rd_crtcs[j].rc_port = 753 &sc->sc_ports[dp->rd_crtcs[j].rc_number]; 754 } 755 756 dp->rd_softc = sc; 757 dp->rd_wsmode = WSDISPLAYIO_MODE_EMUL; 758 dp->rd_bg = WS_DEFAULT_BG; 759 dp->rd_bpp = RADEONFB_DEFAULT_DEPTH; /* XXX */ 760 761 /* for text mode, we pick a resolution that won't 762 * require panning */ 763 radeonfb_pickres(dp, &dp->rd_virtx, &dp->rd_virty, 0); 764 765 aprint_normal("%s: display %d: " 766 "initial virtual resolution %dx%d at %d bpp\n", 767 XNAME(sc), i, dp->rd_virtx, dp->rd_virty, dp->rd_bpp); 768 769 /* now select the *video mode* that we will use */ 770 for (j = 0; j < dp->rd_ncrtcs; j++) { 771 const struct videomode *vmp; 772 vmp = radeonfb_port_mode(sc, dp->rd_crtcs[j].rc_port, 773 dp->rd_virtx, dp->rd_virty); 774 775 /* 776 * virtual resolution should be at least as high as 777 * physical 778 */ 779 if (dp->rd_virtx < vmp->hdisplay || 780 dp->rd_virty < vmp->vdisplay) { 781 dp->rd_virtx = vmp->hdisplay; 782 dp->rd_virty = vmp->vdisplay; 783 } 784 785 dp->rd_crtcs[j].rc_videomode = *vmp; 786 printf("%s: port %d: physical %dx%d %dHz\n", 787 XNAME(sc), j, vmp->hdisplay, vmp->vdisplay, 788 DIVIDE(DIVIDE(vmp->dot_clock * 1000, 789 vmp->htotal), vmp->vtotal)); 790 } 791 792 /* N.B.: radeon wants 64-byte aligned stride */ 793 dp->rd_stride = dp->rd_virtx * dp->rd_bpp / 8; 794 dp->rd_stride = ROUNDUP(dp->rd_stride, RADEON_STRIDEALIGN); 795 796 dp->rd_offset = sc->sc_fboffset * i; 797 dp->rd_fbptr = (vaddr_t)bus_space_vaddr(sc->sc_memt, 798 sc->sc_memh) + dp->rd_offset; 799 dp->rd_curoff = sc->sc_fbsize; 800 dp->rd_curptr = dp->rd_fbptr + dp->rd_curoff; 801 802 DPRINTF(("fpbtr = %p\n", (void *)dp->rd_fbptr)); 803 804 switch (dp->rd_bpp) { 805 case 8: 806 dp->rd_format = 2; 807 break; 808 case 32: 809 dp->rd_format = 6; 810 break; 811 default: 812 aprint_error("%s: bad depth %d\n", XNAME(sc), 813 dp->rd_bpp); 814 goto error; 815 } 816 817 DPRINTF(("init engine\n")); 818 /* XXX: this seems suspicious - per display engine 819 initialization? */ 820 radeonfb_engine_init(dp); 821 822 /* copy the template into place */ 823 dp->rd_wsscreens_storage[0] = radeonfb_stdscreen; 824 dp->rd_wsscreens = dp->rd_wsscreens_storage; 825 826 /* and make up the list */ 827 dp->rd_wsscreenlist.nscreens = 1; 828 dp->rd_wsscreenlist.screens = (void *)&dp->rd_wsscreens; 829 830 vcons_init(&dp->rd_vd, dp, dp->rd_wsscreens, 831 &radeonfb_accessops); 832 833 dp->rd_vd.init_screen = radeonfb_init_screen; 834 835 dp->rd_console = 0; 836 prop_dictionary_get_bool(device_properties(sc->sc_dev), 837 "is_console", &dp->rd_console); 838 839 dp->rd_vscreen.scr_flags |= VCONS_SCREEN_IS_STATIC; 840 841 842 vcons_init_screen(&dp->rd_vd, &dp->rd_vscreen, 843 dp->rd_console, &defattr); 844 845 ri = &dp->rd_vscreen.scr_ri; 846 847 /* clear the screen */ 848 rasops_unpack_attr(defattr, &fg, &bg, &ul); 849 radeonfb_rectfill(dp, 0, 0, ri->ri_width, ri->ri_height, 850 ri->ri_devcmap[bg & 0xf]); 851 852 dp->rd_wsscreens->textops = &ri->ri_ops; 853 dp->rd_wsscreens->capabilities = ri->ri_caps; 854 dp->rd_wsscreens->nrows = ri->ri_rows; 855 dp->rd_wsscreens->ncols = ri->ri_cols; 856 857 #ifdef SPLASHSCREEN 858 dp->rd_splash.si_depth = ri->ri_depth; 859 dp->rd_splash.si_bits = ri->ri_bits; 860 dp->rd_splash.si_hwbits = ri->ri_hwbits; 861 dp->rd_splash.si_width = ri->ri_width; 862 dp->rd_splash.si_height = ri->ri_height; 863 dp->rd_splash.si_stride = ri->ri_stride; 864 dp->rd_splash.si_fillrect = NULL; 865 #endif 866 if (dp->rd_console) { 867 868 radeonfb_modeswitch(dp); 869 wsdisplay_cnattach(dp->rd_wsscreens, ri, 0, 0, 870 defattr); 871 #ifdef SPLASHSCREEN 872 if (splash_render(&dp->rd_splash, 873 SPLASH_F_CENTER|SPLASH_F_FILL) == 0) 874 SCREEN_DISABLE_DRAWING(&dp->rd_vscreen); 875 else 876 #endif 877 vcons_replay_msgbuf(&dp->rd_vscreen); 878 } else { 879 880 /* 881 * since we're not the console we can postpone 882 * the rest until someone actually allocates a 883 * screen for us. but we do clear the screen 884 * at least. 885 */ 886 memset(ri->ri_bits, 0, 1024); 887 888 radeonfb_modeswitch(dp); 889 #ifdef SPLASHSCREEN 890 if (splash_render(&dp->rd_splash, 891 SPLASH_F_CENTER|SPLASH_F_FILL) == 0) 892 SCREEN_DISABLE_DRAWING(&dp->rd_vscreen); 893 #endif 894 } 895 896 aa.console = dp->rd_console; 897 aa.scrdata = &dp->rd_wsscreenlist; 898 aa.accessops = &radeonfb_accessops; 899 aa.accesscookie = &dp->rd_vd; 900 901 config_found(sc->sc_dev, &aa, wsemuldisplaydevprint); 902 903 radeonfb_blank(dp, 0); 904 905 /* Initialise delayed lvds operations for backlight. */ 906 callout_init(&dp->rd_bl_lvds_co, 0); 907 callout_setfunc(&dp->rd_bl_lvds_co, 908 radeonfb_lvds_callout, dp); 909 dp->rd_bl_on = 1; 910 dp->rd_bl_level = radeonfb_get_backlight(dp); 911 radeonfb_set_backlight(dp, dp->rd_bl_level); 912 } 913 914 /* 915 * if we have console output via firmware like on sparc64 it may 916 * interfere with DAC programming so program the palette again 917 * here after we took over 918 */ 919 radeonfb_init_palette(sc, 0); 920 if (HAS_CRTC2(sc)) 921 radeonfb_init_palette(sc, 1); 922 923 pmf_event_register(dev, PMFE_DISPLAY_BRIGHTNESS_UP, 924 radeonfb_brightness_up, TRUE); 925 pmf_event_register(dev, PMFE_DISPLAY_BRIGHTNESS_DOWN, 926 radeonfb_brightness_down, TRUE); 927 928 config_found_ia(dev, "drm", aux, radeonfb_drm_print); 929 930 return; 931 932 error: 933 if (sc->sc_biossz) 934 free(sc->sc_bios, M_DEVBUF); 935 936 if (sc->sc_regsz) 937 bus_space_unmap(sc->sc_regt, sc->sc_regh, sc->sc_regsz); 938 939 if (sc->sc_memsz) 940 bus_space_unmap(sc->sc_memt, sc->sc_memh, sc->sc_memsz); 941 } 942 943 static int 944 radeonfb_drm_print(void *aux, const char *pnp) 945 { 946 if (pnp) 947 aprint_normal("drm at %s", pnp); 948 return (UNCONF); 949 } 950 951 int 952 radeonfb_ioctl(void *v, void *vs, 953 unsigned long cmd, void *d, int flag, struct lwp *l) 954 { 955 struct vcons_data *vd; 956 struct radeonfb_display *dp; 957 struct radeonfb_softc *sc; 958 struct wsdisplay_param *param; 959 960 vd = (struct vcons_data *)v; 961 dp = (struct radeonfb_display *)vd->cookie; 962 sc = dp->rd_softc; 963 964 switch (cmd) { 965 case WSDISPLAYIO_GTYPE: 966 *(unsigned *)d = WSDISPLAY_TYPE_PCIMISC; 967 return 0; 968 969 case WSDISPLAYIO_GINFO: 970 if (vd->active != NULL) { 971 struct wsdisplay_fbinfo *fb; 972 fb = (struct wsdisplay_fbinfo *)d; 973 fb->width = dp->rd_virtx; 974 fb->height = dp->rd_virty; 975 fb->depth = dp->rd_bpp; 976 fb->cmsize = 256; 977 return 0; 978 } else 979 return ENODEV; 980 case WSDISPLAYIO_GVIDEO: 981 if (radeonfb_isblank(dp)) 982 *(unsigned *)d = WSDISPLAYIO_VIDEO_OFF; 983 else 984 *(unsigned *)d = WSDISPLAYIO_VIDEO_ON; 985 return 0; 986 987 case WSDISPLAYIO_SVIDEO: 988 radeonfb_blank(dp, 989 (*(unsigned int *)d == WSDISPLAYIO_VIDEO_OFF)); 990 return 0; 991 992 case WSDISPLAYIO_GETCMAP: 993 #if 0 994 if (dp->rd_bpp == 8) 995 return radeonfb_getcmap(sc, 996 (struct wsdisplay_cmap *)d); 997 #endif 998 return EINVAL; 999 1000 case WSDISPLAYIO_PUTCMAP: 1001 #if 0 1002 if (dp->rd_bpp == 8) 1003 return radeonfb_putcmap(sc, 1004 (struct wsdisplay_cmap *)d); 1005 #endif 1006 return EINVAL; 1007 1008 case WSDISPLAYIO_LINEBYTES: 1009 *(unsigned *)d = dp->rd_stride; 1010 return 0; 1011 1012 case WSDISPLAYIO_SMODE: 1013 if (*(int *)d != dp->rd_wsmode) { 1014 dp->rd_wsmode = *(int *)d; 1015 if ((dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) && 1016 (dp->rd_vd.active)) { 1017 radeonfb_engine_init(dp); 1018 radeonfb_init_palette(sc, dp == &sc->sc_displays[0] ? 0 : 1); 1019 radeonfb_modeswitch(dp); 1020 vcons_redraw_screen(dp->rd_vd.active); 1021 } 1022 } 1023 return 0; 1024 1025 case WSDISPLAYIO_GCURMAX: 1026 ((struct wsdisplay_curpos *)d)->x = RADEON_CURSORMAXX; 1027 ((struct wsdisplay_curpos *)d)->y = RADEON_CURSORMAXY; 1028 return 0; 1029 1030 case WSDISPLAYIO_SCURSOR: 1031 return radeonfb_set_cursor(dp, (struct wsdisplay_cursor *)d); 1032 1033 case WSDISPLAYIO_GCURSOR: 1034 return EPASSTHROUGH; 1035 1036 case WSDISPLAYIO_GCURPOS: 1037 ((struct wsdisplay_curpos *)d)->x = dp->rd_cursor.rc_pos.x; 1038 ((struct wsdisplay_curpos *)d)->y = dp->rd_cursor.rc_pos.y; 1039 return 0; 1040 1041 case WSDISPLAYIO_SCURPOS: 1042 return radeonfb_set_curpos(dp, (struct wsdisplay_curpos *)d); 1043 1044 case WSDISPLAYIO_SSPLASH: 1045 #if defined(SPLASHSCREEN) 1046 if (*(int *)d == 1) { 1047 SCREEN_DISABLE_DRAWING(&dp->rd_vscreen); 1048 splash_render(&dp->rd_splash, 1049 SPLASH_F_CENTER|SPLASH_F_FILL); 1050 } else 1051 SCREEN_ENABLE_DRAWING(&dp->rd_vscreen); 1052 return 0; 1053 #else 1054 return ENODEV; 1055 #endif 1056 case WSDISPLAYIO_GETPARAM: 1057 param = (struct wsdisplay_param *)d; 1058 switch (param->param) { 1059 case WSDISPLAYIO_PARAM_BRIGHTNESS: 1060 param->min = 0; 1061 param->max = 255; 1062 param->curval = dp->rd_bl_level; 1063 return 0; 1064 case WSDISPLAYIO_PARAM_BACKLIGHT: 1065 param->min = 0; 1066 param->max = RADEONFB_BACKLIGHT_MAX; 1067 param->curval = dp->rd_bl_on; 1068 return 0; 1069 } 1070 return EPASSTHROUGH; 1071 1072 case WSDISPLAYIO_SETPARAM: 1073 param = (struct wsdisplay_param *)d; 1074 switch (param->param) { 1075 case WSDISPLAYIO_PARAM_BRIGHTNESS: 1076 radeonfb_set_backlight(dp, param->curval); 1077 return 0; 1078 case WSDISPLAYIO_PARAM_BACKLIGHT: 1079 radeonfb_switch_backlight(dp, param->curval); 1080 return 0; 1081 } 1082 return EPASSTHROUGH; 1083 1084 /* PCI config read/write passthrough. */ 1085 case PCI_IOC_CFGREAD: 1086 case PCI_IOC_CFGWRITE: 1087 return pci_devioctl(sc->sc_pc, sc->sc_pt, cmd, d, flag, l); 1088 1089 case WSDISPLAYIO_GET_BUSID: 1090 return wsdisplayio_busid_pci(sc->sc_dev, sc->sc_pc, 1091 sc->sc_pt, d); 1092 1093 case WSDISPLAYIO_GET_EDID: { 1094 struct wsdisplayio_edid_info *ei = d; 1095 return wsdisplayio_get_edid(sc->sc_dev, ei); 1096 } 1097 1098 default: 1099 return EPASSTHROUGH; 1100 } 1101 } 1102 1103 paddr_t 1104 radeonfb_mmap(void *v, void *vs, off_t offset, int prot) 1105 { 1106 struct vcons_data *vd; 1107 struct radeonfb_display *dp; 1108 struct radeonfb_softc *sc; 1109 paddr_t pa; 1110 1111 vd = (struct vcons_data *)v; 1112 dp = (struct radeonfb_display *)vd->cookie; 1113 sc = dp->rd_softc; 1114 1115 /* XXX: note that we don't allow mapping of registers right now */ 1116 /* XXX: this means that the XFree86 radeon driver won't work */ 1117 if ((offset >= 0) && (offset < (dp->rd_virty * dp->rd_stride))) { 1118 pa = bus_space_mmap(sc->sc_memt, 1119 sc->sc_memaddr + dp->rd_offset + offset, 0, 1120 prot, BUS_SPACE_MAP_LINEAR); 1121 return pa; 1122 } 1123 1124 #ifdef RADEONFB_MMAP_BARS 1125 /* 1126 * restrict all other mappings to processes with superuser privileges 1127 * or the kernel itself 1128 */ 1129 if (kauth_authorize_generic(kauth_cred_get(), KAUTH_GENERIC_ISSUSER, 1130 NULL) != 0) { 1131 aprint_error_dev(sc->sc_dev, "mmap() rejected.\n"); 1132 return -1; 1133 } 1134 1135 if ((offset >= sc->sc_regaddr) && 1136 (offset < sc->sc_regaddr + sc->sc_regsz)) { 1137 return bus_space_mmap(sc->sc_regt, offset, 0, prot, 1138 BUS_SPACE_MAP_LINEAR); 1139 } 1140 1141 if ((offset >= sc->sc_memaddr) && 1142 (offset < sc->sc_memaddr + sc->sc_memsz)) { 1143 return bus_space_mmap(sc->sc_memt, offset, 0, prot, 1144 BUS_SPACE_MAP_LINEAR); 1145 } 1146 1147 if ((offset >= sc->sc_romaddr) && 1148 (offset < sc->sc_romaddr + sc->sc_romsz)) { 1149 return bus_space_mmap(sc->sc_memt, offset, 0, prot, 1150 BUS_SPACE_MAP_LINEAR); 1151 } 1152 1153 #ifdef PCI_MAGIC_IO_RANGE 1154 /* allow mapping of IO space */ 1155 if ((offset >= PCI_MAGIC_IO_RANGE) && 1156 (offset < PCI_MAGIC_IO_RANGE + 0x10000)) { 1157 pa = bus_space_mmap(sc->sc_iot, offset - PCI_MAGIC_IO_RANGE, 1158 0, prot, 0); 1159 return pa; 1160 } 1161 #endif /* PCI_MAGIC_IO_RANGE */ 1162 1163 #endif /* RADEONFB_MMAP_BARS */ 1164 1165 return -1; 1166 } 1167 1168 static void 1169 radeonfb_loadbios(struct radeonfb_softc *sc, const struct pci_attach_args *pa) 1170 { 1171 bus_space_tag_t romt; 1172 bus_space_handle_t romh, biosh; 1173 bus_size_t romsz; 1174 bus_addr_t ptr; 1175 1176 if (pci_mapreg_map(pa, PCI_MAPREG_ROM, PCI_MAPREG_TYPE_ROM, 1177 BUS_SPACE_MAP_PREFETCHABLE, &romt, &romh, NULL, &romsz) != 0) { 1178 aprint_verbose("%s: unable to map BIOS!\n", XNAME(sc)); 1179 return; 1180 } 1181 1182 pci_find_rom(pa, romt, romh, PCI_ROM_CODE_TYPE_X86, &biosh, 1183 &sc->sc_biossz); 1184 if (sc->sc_biossz == 0) { 1185 aprint_verbose("%s: Video BIOS not present\n", XNAME(sc)); 1186 return; 1187 } 1188 1189 sc->sc_bios = malloc(sc->sc_biossz, M_DEVBUF, M_WAITOK); 1190 bus_space_read_region_1(romt, biosh, 0, sc->sc_bios, sc->sc_biossz); 1191 1192 /* unmap the PCI expansion rom */ 1193 bus_space_unmap(romt, romh, romsz); 1194 1195 /* turn off rom decoder now */ 1196 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM, 1197 pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM) & 1198 ~PCI_MAPREG_ROM_ENABLE); 1199 1200 ptr = GETBIOS16(sc, 0x48); 1201 if ((GETBIOS32(sc, ptr + 4) == 0x41544f4d /* "ATOM" */) || 1202 (GETBIOS32(sc, ptr + 4) == 0x4d4f5441 /* "MOTA" */)) { 1203 sc->sc_flags |= RFB_ATOM; 1204 } 1205 1206 aprint_verbose("%s: Found %d KB %s BIOS\n", XNAME(sc), 1207 (unsigned)sc->sc_biossz >> 10, IS_ATOM(sc) ? "ATOM" : "Legacy"); 1208 } 1209 1210 1211 uint32_t 1212 radeonfb_get32(struct radeonfb_softc *sc, uint32_t reg) 1213 { 1214 1215 return bus_space_read_4(sc->sc_regt, sc->sc_regh, reg); 1216 } 1217 1218 void 1219 radeonfb_put32(struct radeonfb_softc *sc, uint32_t reg, uint32_t val) 1220 { 1221 1222 bus_space_write_4(sc->sc_regt, sc->sc_regh, reg, val); 1223 } 1224 1225 void 1226 radeonfb_mask32(struct radeonfb_softc *sc, uint32_t reg, 1227 uint32_t andmask, uint32_t ormask) 1228 { 1229 int s; 1230 uint32_t val; 1231 1232 s = splhigh(); 1233 val = radeonfb_get32(sc, reg); 1234 val = (val & andmask) | ormask; 1235 radeonfb_put32(sc, reg, val); 1236 splx(s); 1237 } 1238 1239 uint32_t 1240 radeonfb_getindex(struct radeonfb_softc *sc, uint32_t idx) 1241 { 1242 int s; 1243 uint32_t val; 1244 1245 s = splhigh(); 1246 radeonfb_put32(sc, RADEON_MM_INDEX, idx); 1247 val = radeonfb_get32(sc, RADEON_MM_DATA); 1248 splx(s); 1249 1250 return (val); 1251 } 1252 1253 void 1254 radeonfb_putindex(struct radeonfb_softc *sc, uint32_t idx, uint32_t val) 1255 { 1256 int s; 1257 1258 s = splhigh(); 1259 radeonfb_put32(sc, RADEON_MM_INDEX, idx); 1260 radeonfb_put32(sc, RADEON_MM_DATA, val); 1261 splx(s); 1262 } 1263 1264 void 1265 radeonfb_maskindex(struct radeonfb_softc *sc, uint32_t idx, 1266 uint32_t andmask, uint32_t ormask) 1267 { 1268 int s; 1269 uint32_t val; 1270 1271 s = splhigh(); 1272 radeonfb_put32(sc, RADEON_MM_INDEX, idx); 1273 val = radeonfb_get32(sc, RADEON_MM_DATA); 1274 val = (val & andmask) | ormask; 1275 radeonfb_put32(sc, RADEON_MM_DATA, val); 1276 splx(s); 1277 } 1278 1279 uint32_t 1280 radeonfb_getpll(struct radeonfb_softc *sc, uint32_t idx) 1281 { 1282 int s; 1283 uint32_t val; 1284 1285 s = splhigh(); 1286 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, idx & 0x3f); 1287 val = radeonfb_get32(sc, RADEON_CLOCK_CNTL_DATA); 1288 if (HAS_R300CG(sc)) 1289 radeonfb_r300cg_workaround(sc); 1290 splx(s); 1291 1292 return (val); 1293 } 1294 1295 void 1296 radeonfb_putpll(struct radeonfb_softc *sc, uint32_t idx, uint32_t val) 1297 { 1298 int s; 1299 1300 s = splhigh(); 1301 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, (idx & 0x3f) | 1302 RADEON_PLL_WR_EN); 1303 radeonfb_put32(sc, RADEON_CLOCK_CNTL_DATA, val); 1304 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, 0); 1305 splx(s); 1306 } 1307 1308 void 1309 radeonfb_maskpll(struct radeonfb_softc *sc, uint32_t idx, 1310 uint32_t andmask, uint32_t ormask) 1311 { 1312 int s; 1313 uint32_t val; 1314 1315 s = splhigh(); 1316 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, (idx & 0x3f) | 1317 RADEON_PLL_WR_EN); 1318 val = radeonfb_get32(sc, RADEON_CLOCK_CNTL_DATA); 1319 val = (val & andmask) | ormask; 1320 radeonfb_put32(sc, RADEON_CLOCK_CNTL_DATA, val); 1321 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, 0); 1322 splx(s); 1323 } 1324 1325 int 1326 radeonfb_scratch_test(struct radeonfb_softc *sc, int reg, uint32_t v) 1327 { 1328 uint32_t saved; 1329 1330 saved = GET32(sc, reg); 1331 PUT32(sc, reg, v); 1332 if (GET32(sc, reg) != v) { 1333 return -1; 1334 } 1335 PUT32(sc, reg, saved); 1336 return 0; 1337 } 1338 1339 uintmax_t 1340 radeonfb_getprop_num(struct radeonfb_softc *sc, const char *name, 1341 uintmax_t defval) 1342 { 1343 prop_number_t pn; 1344 pn = prop_dictionary_get(device_properties(sc->sc_dev), name); 1345 if (pn == NULL) { 1346 return defval; 1347 } 1348 KASSERT(prop_object_type(pn) == PROP_TYPE_NUMBER); 1349 return (prop_number_integer_value(pn)); 1350 } 1351 1352 int 1353 radeonfb_getclocks(struct radeonfb_softc *sc) 1354 { 1355 bus_addr_t ptr; 1356 int refclk = 0; 1357 int refdiv = 0; 1358 int minpll = 0; 1359 int maxpll = 0; 1360 1361 /* load initial property values if port/board provides them */ 1362 refclk = radeonfb_getprop_num(sc, "refclk", 0) & 0xffff; 1363 refdiv = radeonfb_getprop_num(sc, "refdiv", 0) & 0xffff; 1364 minpll = radeonfb_getprop_num(sc, "minpll", 0) & 0xffffffffU; 1365 maxpll = radeonfb_getprop_num(sc, "maxpll", 0) & 0xffffffffU; 1366 1367 if (refclk && refdiv && minpll && maxpll) 1368 goto dontprobe; 1369 1370 if (!sc->sc_biossz) { 1371 /* no BIOS */ 1372 aprint_verbose("%s: No video BIOS, using default clocks\n", 1373 XNAME(sc)); 1374 if (IS_IGP(sc)) 1375 refclk = refclk ? refclk : 1432; 1376 else 1377 refclk = refclk ? refclk : 2700; 1378 refdiv = refdiv ? refdiv : 12; 1379 minpll = minpll ? minpll : 12500; 1380 maxpll = maxpll ? maxpll : 35000; 1381 } else if (IS_ATOM(sc)) { 1382 /* ATOM BIOS */ 1383 ptr = GETBIOS16(sc, 0x48); 1384 ptr = GETBIOS16(sc, ptr + 32); /* aka MasterDataStart */ 1385 ptr = GETBIOS16(sc, ptr + 12); /* pll info block */ 1386 refclk = refclk ? refclk : GETBIOS16(sc, ptr + 82); 1387 minpll = minpll ? minpll : GETBIOS16(sc, ptr + 78); 1388 maxpll = maxpll ? maxpll : GETBIOS16(sc, ptr + 32); 1389 /* 1390 * ATOM BIOS doesn't supply a reference divider, so we 1391 * have to probe for it. 1392 */ 1393 if (refdiv < 2) 1394 refdiv = GETPLL(sc, RADEON_PPLL_REF_DIV) & 1395 RADEON_PPLL_REF_DIV_MASK; 1396 /* 1397 * if probe is zero, just assume one that should work 1398 * for most parts 1399 */ 1400 if (refdiv < 2) 1401 refdiv = 12; 1402 1403 } else { 1404 /* Legacy BIOS */ 1405 ptr = GETBIOS16(sc, 0x48); 1406 ptr = GETBIOS16(sc, ptr + 0x30); 1407 refclk = refclk ? refclk : GETBIOS16(sc, ptr + 0x0E); 1408 refdiv = refdiv ? refdiv : GETBIOS16(sc, ptr + 0x10); 1409 minpll = minpll ? minpll : GETBIOS32(sc, ptr + 0x12); 1410 maxpll = maxpll ? maxpll : GETBIOS32(sc, ptr + 0x16); 1411 } 1412 1413 1414 dontprobe: 1415 sc->sc_refclk = refclk * 10; 1416 sc->sc_refdiv = refdiv; 1417 sc->sc_minpll = minpll * 10; 1418 sc->sc_maxpll = maxpll * 10; 1419 return 0; 1420 } 1421 1422 int 1423 radeonfb_calc_dividers(struct radeonfb_softc *sc, uint32_t dotclock, 1424 uint32_t *postdivbit, uint32_t *feedbackdiv) 1425 { 1426 int i; 1427 uint32_t outfreq; 1428 int div; 1429 1430 DPRINTF(("dot clock: %u\n", dotclock)); 1431 for (i = 0; (div = radeonfb_dividers[i].divider) != 0; i++) { 1432 outfreq = div * dotclock; 1433 if ((outfreq >= sc->sc_minpll) && 1434 (outfreq <= sc->sc_maxpll)) { 1435 DPRINTF(("outfreq: %u\n", outfreq)); 1436 *postdivbit = 1437 ((uint32_t)radeonfb_dividers[i].mask << 16); 1438 DPRINTF(("post divider: %d (mask %x)\n", div, 1439 *postdivbit)); 1440 break; 1441 } 1442 } 1443 1444 if (div == 0) 1445 return 1; 1446 1447 *feedbackdiv = DIVIDE(sc->sc_refdiv * outfreq, sc->sc_refclk); 1448 DPRINTF(("feedback divider: %d\n", *feedbackdiv)); 1449 return 0; 1450 } 1451 1452 #if 0 1453 #ifdef RADEONFB_DEBUG 1454 static void 1455 dump_buffer(const char *pfx, void *buffer, unsigned int size) 1456 { 1457 char asc[17]; 1458 unsigned ptr = (unsigned)buffer; 1459 char *start = (char *)(ptr & ~0xf); 1460 char *end = (char *)(ptr + size); 1461 1462 end = (char *)(((unsigned)end + 0xf) & ~0xf); 1463 1464 if (pfx == NULL) { 1465 pfx = ""; 1466 } 1467 1468 while (start < end) { 1469 unsigned offset = (unsigned)start & 0xf; 1470 if (offset == 0) { 1471 printf("%s%x: ", pfx, (unsigned)start); 1472 } 1473 if (((unsigned)start < ptr) || 1474 ((unsigned)start >= (ptr + size))) { 1475 printf(" "); 1476 asc[offset] = ' '; 1477 } else { 1478 printf("%02x", *(unsigned char *)start); 1479 if ((*start >= ' ') && (*start <= '~')) { 1480 asc[offset] = *start; 1481 } else { 1482 asc[offset] = '.'; 1483 } 1484 } 1485 asc[offset + 1] = 0; 1486 if (offset % 2) { 1487 printf(" "); 1488 } 1489 if (offset == 15) { 1490 printf(" %s\n", asc); 1491 } 1492 start++; 1493 } 1494 } 1495 #endif 1496 #endif 1497 1498 int 1499 radeonfb_getconnectors(struct radeonfb_softc *sc) 1500 { 1501 int i; 1502 int found = 0; 1503 1504 for (i = 0; i < 2; i++) { 1505 sc->sc_ports[i].rp_mon_type = RADEON_MT_UNKNOWN; 1506 sc->sc_ports[i].rp_ddc_type = RADEON_DDC_NONE; 1507 sc->sc_ports[i].rp_dac_type = RADEON_DAC_UNKNOWN; 1508 sc->sc_ports[i].rp_conn_type = RADEON_CONN_NONE; 1509 sc->sc_ports[i].rp_tmds_type = RADEON_TMDS_UNKNOWN; 1510 } 1511 1512 /* 1513 * This logic is borrowed from Xorg's radeon driver. 1514 */ 1515 if (!sc->sc_biossz) 1516 goto nobios; 1517 1518 if (IS_ATOM(sc)) { 1519 /* not done yet */ 1520 } else { 1521 uint16_t ptr; 1522 int port = 0; 1523 1524 ptr = GETBIOS16(sc, 0x48); 1525 ptr = GETBIOS16(sc, ptr + 0x50); 1526 for (i = 1; i < 4; i++) { 1527 uint16_t entry; 1528 uint8_t conn, ddc, dac, tmds; 1529 1530 /* 1531 * Parse the connector table. From reading the code, 1532 * it appears to made up of 16-bit entries for each 1533 * connector. The 16-bits are defined as: 1534 * 1535 * bits 12-15 - connector type (0 == end of table) 1536 * bits 8-11 - DDC type 1537 * bits 5-7 - ??? 1538 * bit 4 - TMDS type (1 = EXT, 0 = INT) 1539 * bits 1-3 - ??? 1540 * bit 0 - DAC, 1 = TVDAC, 0 = primary 1541 */ 1542 if (!GETBIOS8(sc, ptr + i * 2) && i > 1) 1543 break; 1544 entry = GETBIOS16(sc, ptr + i * 2); 1545 1546 conn = (entry >> 12) & 0xf; 1547 ddc = (entry >> 8) & 0xf; 1548 dac = (entry & 0x1) ? RADEON_DAC_TVDAC : 1549 RADEON_DAC_PRIMARY; 1550 tmds = ((entry >> 4) & 0x1) ? RADEON_TMDS_EXT : 1551 RADEON_TMDS_INT; 1552 1553 if (conn == RADEON_CONN_NONE) 1554 continue; /* no connector */ 1555 1556 if ((found > 0) && 1557 (sc->sc_ports[port].rp_ddc_type == ddc)) { 1558 /* duplicate entry for same connector */ 1559 continue; 1560 } 1561 1562 /* internal DDC_DVI port gets priority */ 1563 if ((ddc == RADEON_DDC_DVI) || (port == 1)) 1564 port = 0; 1565 else 1566 port = 1; 1567 1568 sc->sc_ports[port].rp_ddc_type = 1569 ddc > RADEON_DDC_CRT2 ? RADEON_DDC_NONE : ddc; 1570 sc->sc_ports[port].rp_dac_type = dac; 1571 sc->sc_ports[port].rp_conn_type = 1572 min(conn, RADEON_CONN_UNSUPPORTED) ; 1573 1574 sc->sc_ports[port].rp_tmds_type = tmds; 1575 1576 if ((conn != RADEON_CONN_DVI_I) && 1577 (conn != RADEON_CONN_DVI_D) && 1578 (tmds == RADEON_TMDS_INT)) 1579 sc->sc_ports[port].rp_tmds_type = 1580 RADEON_TMDS_UNKNOWN; 1581 1582 found += (port + 1); 1583 } 1584 } 1585 1586 nobios: 1587 if (!found) { 1588 DPRINTF(("No connector info in BIOS!\n")); 1589 /* default, port 0 = internal TMDS, port 1 = CRT */ 1590 sc->sc_ports[0].rp_mon_type = RADEON_MT_UNKNOWN; 1591 sc->sc_ports[0].rp_ddc_type = RADEON_DDC_DVI; 1592 sc->sc_ports[0].rp_dac_type = RADEON_DAC_TVDAC; 1593 sc->sc_ports[0].rp_conn_type = RADEON_CONN_DVI_D; 1594 sc->sc_ports[0].rp_tmds_type = RADEON_TMDS_INT; 1595 1596 sc->sc_ports[1].rp_mon_type = RADEON_MT_UNKNOWN; 1597 sc->sc_ports[1].rp_ddc_type = RADEON_DDC_VGA; 1598 sc->sc_ports[1].rp_dac_type = RADEON_DAC_PRIMARY; 1599 sc->sc_ports[1].rp_conn_type = RADEON_CONN_CRT; 1600 sc->sc_ports[1].rp_tmds_type = RADEON_TMDS_EXT; 1601 } 1602 1603 /* 1604 * Fixup for RS300/RS350/RS400 chips, that lack a primary DAC. 1605 * these chips should use TVDAC for the VGA port. 1606 */ 1607 if (HAS_SDAC(sc)) { 1608 if (sc->sc_ports[0].rp_conn_type == RADEON_CONN_CRT) { 1609 sc->sc_ports[0].rp_dac_type = RADEON_DAC_TVDAC; 1610 sc->sc_ports[1].rp_dac_type = RADEON_DAC_PRIMARY; 1611 } else { 1612 sc->sc_ports[1].rp_dac_type = RADEON_DAC_TVDAC; 1613 sc->sc_ports[0].rp_dac_type = RADEON_DAC_PRIMARY; 1614 } 1615 } else if (!HAS_CRTC2(sc)) { 1616 sc->sc_ports[0].rp_dac_type = RADEON_DAC_PRIMARY; 1617 } 1618 1619 for (i = 0; i < 2; i++) { 1620 char edid[128]; 1621 uint8_t ddc; 1622 struct edid_info *eip = &sc->sc_ports[i].rp_edid; 1623 prop_data_t edid_data; 1624 1625 DPRINTF(("Port #%d:\n", i)); 1626 DPRINTF((" conn = %d\n", sc->sc_ports[i].rp_conn_type)); 1627 DPRINTF((" ddc = %d\n", sc->sc_ports[i].rp_ddc_type)); 1628 DPRINTF((" dac = %d\n", sc->sc_ports[i].rp_dac_type)); 1629 DPRINTF((" tmds = %d\n", sc->sc_ports[i].rp_tmds_type)); 1630 1631 sc->sc_ports[i].rp_edid_valid = 0; 1632 /* first look for static EDID data */ 1633 if ((edid_data = prop_dictionary_get(device_properties( 1634 sc->sc_dev), "EDID")) != NULL) { 1635 1636 aprint_normal_dev(sc->sc_dev, "using static EDID\n"); 1637 memcpy(edid, prop_data_data_nocopy(edid_data), 128); 1638 if (edid_parse(edid, eip) == 0) { 1639 1640 sc->sc_ports[i].rp_edid_valid = 1; 1641 } 1642 } 1643 /* if we didn't find any we'll try to talk to the monitor */ 1644 if (sc->sc_ports[i].rp_edid_valid != 1) { 1645 1646 ddc = sc->sc_ports[i].rp_ddc_type; 1647 if (ddc != RADEON_DDC_NONE) { 1648 if ((radeonfb_i2c_read_edid(sc, ddc, edid) 1649 == 0) && (edid_parse(edid, eip) == 0)) { 1650 1651 sc->sc_ports[i].rp_edid_valid = 1; 1652 edid_print(eip); 1653 } 1654 } 1655 } 1656 } 1657 1658 return found; 1659 } 1660 1661 int 1662 radeonfb_gettmds(struct radeonfb_softc *sc) 1663 { 1664 int i; 1665 1666 if (!sc->sc_biossz) { 1667 goto nobios; 1668 } 1669 1670 if (IS_ATOM(sc)) { 1671 /* XXX: not done yet */ 1672 } else { 1673 uint16_t ptr; 1674 int n; 1675 1676 ptr = GETBIOS16(sc, 0x48); 1677 ptr = GETBIOS16(sc, ptr + 0x34); 1678 DPRINTF(("DFP table revision %d\n", GETBIOS8(sc, ptr))); 1679 if (GETBIOS8(sc, ptr) == 3) { 1680 /* revision three table */ 1681 n = GETBIOS8(sc, ptr + 5) + 1; 1682 n = min(n, 4); 1683 1684 memset(sc->sc_tmds_pll, 0, sizeof (sc->sc_tmds_pll)); 1685 for (i = 0; i < n; i++) { 1686 sc->sc_tmds_pll[i].rtp_pll = GETBIOS32(sc, 1687 ptr + i * 10 + 8); 1688 sc->sc_tmds_pll[i].rtp_freq = GETBIOS16(sc, 1689 ptr + i * 10 + 0x10); 1690 DPRINTF(("TMDS_PLL dot clock %d pll %x\n", 1691 sc->sc_tmds_pll[i].rtp_freq, 1692 sc->sc_tmds_pll[i].rtp_pll)); 1693 } 1694 return 0; 1695 } 1696 } 1697 1698 nobios: 1699 DPRINTF(("no suitable DFP table present\n")); 1700 for (i = 0; 1701 i < sizeof (radeonfb_tmds_pll) / sizeof (radeonfb_tmds_pll[0]); 1702 i++) { 1703 int j; 1704 1705 if (radeonfb_tmds_pll[i].family != sc->sc_family) 1706 continue; 1707 1708 for (j = 0; j < 4; j++) { 1709 sc->sc_tmds_pll[j] = radeonfb_tmds_pll[i].plls[j]; 1710 DPRINTF(("TMDS_PLL dot clock %d pll %x\n", 1711 sc->sc_tmds_pll[j].rtp_freq, 1712 sc->sc_tmds_pll[j].rtp_pll)); 1713 } 1714 return 0; 1715 } 1716 1717 return -1; 1718 } 1719 1720 const struct videomode * 1721 radeonfb_modelookup(const char *name) 1722 { 1723 int i; 1724 1725 for (i = 0; i < videomode_count; i++) 1726 if (!strcmp(name, videomode_list[i].name)) 1727 return &videomode_list[i]; 1728 1729 return NULL; 1730 } 1731 1732 void 1733 radeonfb_pllwriteupdate(struct radeonfb_softc *sc, int crtc) 1734 { 1735 if (crtc) { 1736 while (GETPLL(sc, RADEON_P2PLL_REF_DIV) & 1737 RADEON_P2PLL_ATOMIC_UPDATE_R); 1738 SETPLL(sc, RADEON_P2PLL_REF_DIV, RADEON_P2PLL_ATOMIC_UPDATE_W); 1739 } else { 1740 while (GETPLL(sc, RADEON_PPLL_REF_DIV) & 1741 RADEON_PPLL_ATOMIC_UPDATE_R); 1742 SETPLL(sc, RADEON_PPLL_REF_DIV, RADEON_PPLL_ATOMIC_UPDATE_W); 1743 } 1744 } 1745 1746 void 1747 radeonfb_pllwaitatomicread(struct radeonfb_softc *sc, int crtc) 1748 { 1749 int i; 1750 1751 for (i = 10000; i; i--) { 1752 if (crtc) { 1753 if (GETPLL(sc, RADEON_P2PLL_REF_DIV) & 1754 RADEON_P2PLL_ATOMIC_UPDATE_R) 1755 break; 1756 } else { 1757 if (GETPLL(sc, RADEON_PPLL_REF_DIV) & 1758 RADEON_PPLL_ATOMIC_UPDATE_R) 1759 break; 1760 } 1761 } 1762 } 1763 1764 void 1765 radeonfb_program_vclk(struct radeonfb_softc *sc, int dotclock, int crtc) 1766 { 1767 uint32_t pbit = 0; 1768 uint32_t feed = 0; 1769 uint32_t data; 1770 #if 1 1771 int i; 1772 #endif 1773 1774 radeonfb_calc_dividers(sc, dotclock, &pbit, &feed); 1775 1776 if (crtc == 0) { 1777 1778 /* XXXX: mobility workaround missing */ 1779 /* XXXX: R300 stuff missing */ 1780 1781 PATCHPLL(sc, RADEON_VCLK_ECP_CNTL, 1782 RADEON_VCLK_SRC_SEL_CPUCLK, 1783 ~RADEON_VCLK_SRC_SEL_MASK); 1784 1785 /* put vclk into reset, use atomic updates */ 1786 SETPLL(sc, RADEON_PPLL_CNTL, 1787 RADEON_PPLL_REFCLK_SEL | 1788 RADEON_PPLL_FBCLK_SEL | 1789 RADEON_PPLL_RESET | 1790 RADEON_PPLL_ATOMIC_UPDATE_EN | 1791 RADEON_PPLL_VGA_ATOMIC_UPDATE_EN); 1792 1793 /* select clock 3 */ 1794 #if 0 1795 PATCH32(sc, RADEON_CLOCK_CNTL_INDEX, RADEON_PLL_DIV_SEL, 1796 ~RADEON_PLL_DIV_SEL); 1797 #else 1798 PATCH32(sc, RADEON_CLOCK_CNTL_INDEX, 0, 1799 ~RADEON_PLL_DIV_SEL); 1800 #endif 1801 1802 /* XXX: R300 family -- program divider differently? */ 1803 1804 /* program reference divider */ 1805 PATCHPLL(sc, RADEON_PPLL_REF_DIV, sc->sc_refdiv, 1806 ~RADEON_PPLL_REF_DIV_MASK); 1807 PRINTPLL(RADEON_PPLL_REF_DIV); 1808 1809 #if 0 1810 data = GETPLL(sc, RADEON_PPLL_DIV_3); 1811 data &= ~(RADEON_PPLL_FB3_DIV_MASK | 1812 RADEON_PPLL_POST3_DIV_MASK); 1813 data |= pbit; 1814 data |= (feed & RADEON_PPLL_FB3_DIV_MASK); 1815 PUTPLL(sc, RADEON_PPLL_DIV_3, data); 1816 #else 1817 for (i = 0; i < 4; i++) { 1818 } 1819 #endif 1820 1821 /* use the atomic update */ 1822 radeonfb_pllwriteupdate(sc, crtc); 1823 1824 /* and wait for it to complete */ 1825 radeonfb_pllwaitatomicread(sc, crtc); 1826 1827 /* program HTOTAL (why?) */ 1828 PUTPLL(sc, RADEON_HTOTAL_CNTL, 0); 1829 1830 /* drop reset */ 1831 CLRPLL(sc, RADEON_PPLL_CNTL, 1832 RADEON_PPLL_RESET | RADEON_PPLL_SLEEP | 1833 RADEON_PPLL_ATOMIC_UPDATE_EN | 1834 RADEON_PPLL_VGA_ATOMIC_UPDATE_EN); 1835 1836 PRINTPLL(RADEON_PPLL_CNTL); 1837 1838 /* give clock time to lock */ 1839 delay(50000); 1840 1841 PATCHPLL(sc, RADEON_VCLK_ECP_CNTL, 1842 RADEON_VCLK_SRC_SEL_PPLLCLK, 1843 ~RADEON_VCLK_SRC_SEL_MASK); 1844 1845 } else { 1846 1847 PATCHPLL(sc, RADEON_PIXCLKS_CNTL, 1848 RADEON_PIX2CLK_SRC_SEL_CPUCLK, 1849 ~RADEON_PIX2CLK_SRC_SEL_MASK); 1850 1851 /* put vclk into reset, use atomic updates */ 1852 SETPLL(sc, RADEON_P2PLL_CNTL, 1853 RADEON_P2PLL_RESET | 1854 RADEON_P2PLL_ATOMIC_UPDATE_EN | 1855 RADEON_P2PLL_VGA_ATOMIC_UPDATE_EN); 1856 1857 /* XXX: R300 family -- program divider differently? */ 1858 1859 /* program reference divider */ 1860 PATCHPLL(sc, RADEON_P2PLL_REF_DIV, sc->sc_refdiv, 1861 ~RADEON_P2PLL_REF_DIV_MASK); 1862 1863 /* program feedback and post dividers */ 1864 data = GETPLL(sc, RADEON_P2PLL_DIV_0); 1865 data &= ~(RADEON_P2PLL_FB0_DIV_MASK | 1866 RADEON_P2PLL_POST0_DIV_MASK); 1867 data |= pbit; 1868 data |= (feed & RADEON_P2PLL_FB0_DIV_MASK); 1869 PUTPLL(sc, RADEON_P2PLL_DIV_0, data); 1870 1871 /* use the atomic update */ 1872 radeonfb_pllwriteupdate(sc, crtc); 1873 1874 /* and wait for it to complete */ 1875 radeonfb_pllwaitatomicread(sc, crtc); 1876 1877 /* program HTOTAL (why?) */ 1878 PUTPLL(sc, RADEON_HTOTAL2_CNTL, 0); 1879 1880 /* drop reset */ 1881 CLRPLL(sc, RADEON_P2PLL_CNTL, 1882 RADEON_P2PLL_RESET | RADEON_P2PLL_SLEEP | 1883 RADEON_P2PLL_ATOMIC_UPDATE_EN | 1884 RADEON_P2PLL_VGA_ATOMIC_UPDATE_EN); 1885 1886 /* allow time for clock to lock */ 1887 delay(50000); 1888 1889 PATCHPLL(sc, RADEON_PIXCLKS_CNTL, 1890 RADEON_PIX2CLK_SRC_SEL_P2PLLCLK, 1891 ~RADEON_PIX2CLK_SRC_SEL_MASK); 1892 } 1893 PRINTREG(RADEON_CRTC_MORE_CNTL); 1894 } 1895 1896 void 1897 radeonfb_modeswitch(struct radeonfb_display *dp) 1898 { 1899 struct radeonfb_softc *sc = dp->rd_softc; 1900 int i; 1901 1902 /* blank the display while we switch modes */ 1903 radeonfb_blank(dp, 1); 1904 1905 #if 0 1906 SET32(sc, RADEON_CRTC_EXT_CNTL, 1907 RADEON_CRTC_VSYNC_DIS | RADEON_CRTC_HSYNC_DIS | 1908 RADEON_CRTC_DISPLAY_DIS /* | RADEON_CRTC_DISP_REQ_EN_B */); 1909 #endif 1910 1911 /* these registers might get in the way... */ 1912 PUT32(sc, RADEON_OVR_CLR, 0); 1913 PUT32(sc, RADEON_OVR_WID_LEFT_RIGHT, 0); 1914 PUT32(sc, RADEON_OVR_WID_TOP_BOTTOM, 0); 1915 PUT32(sc, RADEON_OV0_SCALE_CNTL, 0); 1916 PUT32(sc, RADEON_SUBPIC_CNTL, 0); 1917 PUT32(sc, RADEON_VIPH_CONTROL, 0); 1918 PUT32(sc, RADEON_I2C_CNTL_1, 0); 1919 PUT32(sc, RADEON_GEN_INT_CNTL, 0); 1920 PUT32(sc, RADEON_CAP0_TRIG_CNTL, 0); 1921 PUT32(sc, RADEON_CAP1_TRIG_CNTL, 0); 1922 PUT32(sc, RADEON_SURFACE_CNTL, 0); 1923 1924 for (i = 0; i < dp->rd_ncrtcs; i++) 1925 radeonfb_setcrtc(dp, i); 1926 1927 /* activate the display */ 1928 radeonfb_blank(dp, 0); 1929 } 1930 1931 void 1932 radeonfb_setcrtc(struct radeonfb_display *dp, int index) 1933 { 1934 int crtc; 1935 struct videomode *mode; 1936 struct radeonfb_softc *sc; 1937 struct radeonfb_crtc *cp; 1938 uint32_t v; 1939 uint32_t gencntl; 1940 uint32_t htotaldisp; 1941 uint32_t hsyncstrt; 1942 uint32_t vtotaldisp; 1943 uint32_t vsyncstrt; 1944 uint32_t fphsyncstrt; 1945 uint32_t fpvsyncstrt; 1946 uint32_t fphtotaldisp; 1947 uint32_t fpvtotaldisp; 1948 uint32_t pitch; 1949 1950 sc = dp->rd_softc; 1951 cp = &dp->rd_crtcs[index]; 1952 crtc = cp->rc_number; 1953 mode = &cp->rc_videomode; 1954 1955 #if 1 1956 pitch = (((dp->rd_virtx * dp->rd_bpp) + ((dp->rd_bpp * 8) - 1)) / 1957 (dp->rd_bpp * 8)); 1958 #else 1959 pitch = (((sc->sc_maxx * sc->sc_maxbpp) + ((sc->sc_maxbpp * 8) - 1)) / 1960 (sc->sc_maxbpp * 8)); 1961 #endif 1962 1963 switch (crtc) { 1964 case 0: 1965 gencntl = RADEON_CRTC_GEN_CNTL; 1966 htotaldisp = RADEON_CRTC_H_TOTAL_DISP; 1967 hsyncstrt = RADEON_CRTC_H_SYNC_STRT_WID; 1968 vtotaldisp = RADEON_CRTC_V_TOTAL_DISP; 1969 vsyncstrt = RADEON_CRTC_V_SYNC_STRT_WID; 1970 fpvsyncstrt = RADEON_FP_V_SYNC_STRT_WID; 1971 fphsyncstrt = RADEON_FP_H_SYNC_STRT_WID; 1972 fpvtotaldisp = RADEON_FP_CRTC_V_TOTAL_DISP; 1973 fphtotaldisp = RADEON_FP_CRTC_H_TOTAL_DISP; 1974 break; 1975 case 1: 1976 gencntl = RADEON_CRTC2_GEN_CNTL; 1977 htotaldisp = RADEON_CRTC2_H_TOTAL_DISP; 1978 hsyncstrt = RADEON_CRTC2_H_SYNC_STRT_WID; 1979 vtotaldisp = RADEON_CRTC2_V_TOTAL_DISP; 1980 vsyncstrt = RADEON_CRTC2_V_SYNC_STRT_WID; 1981 fpvsyncstrt = RADEON_FP_V2_SYNC_STRT_WID; 1982 fphsyncstrt = RADEON_FP_H2_SYNC_STRT_WID; 1983 fpvtotaldisp = RADEON_FP_CRTC2_V_TOTAL_DISP; 1984 fphtotaldisp = RADEON_FP_CRTC2_H_TOTAL_DISP; 1985 break; 1986 default: 1987 panic("Bad CRTC!"); 1988 break; 1989 } 1990 1991 /* 1992 * CRTC_GEN_CNTL - depth, accelerator mode, etc. 1993 */ 1994 /* only bother with 32bpp and 8bpp */ 1995 v = dp->rd_format << RADEON_CRTC_PIX_WIDTH_SHIFT; 1996 1997 if (crtc == 1) { 1998 v |= RADEON_CRTC2_CRT2_ON | RADEON_CRTC2_EN; 1999 } else { 2000 v |= RADEON_CRTC_EXT_DISP_EN | RADEON_CRTC_EN; 2001 } 2002 2003 if (mode->flags & VID_DBLSCAN) 2004 v |= RADEON_CRTC2_DBL_SCAN_EN; 2005 2006 if (mode->flags & VID_INTERLACE) 2007 v |= RADEON_CRTC2_INTERLACE_EN; 2008 2009 if (mode->flags & VID_CSYNC) { 2010 v |= RADEON_CRTC2_CSYNC_EN; 2011 if (crtc == 1) 2012 v |= RADEON_CRTC2_VSYNC_TRISTAT; 2013 } 2014 2015 PUT32(sc, gencntl, v); 2016 DPRINTF(("CRTC%s_GEN_CNTL = %08x\n", crtc ? "2" : "", v)); 2017 2018 /* 2019 * CRTC_EXT_CNTL - preserve disable flags, set ATI linear and EXT_CNT 2020 */ 2021 v = GET32(sc, RADEON_CRTC_EXT_CNTL); 2022 if (crtc == 0) { 2023 v &= (RADEON_CRTC_VSYNC_DIS | RADEON_CRTC_HSYNC_DIS | 2024 RADEON_CRTC_DISPLAY_DIS); 2025 v |= RADEON_XCRT_CNT_EN | RADEON_VGA_ATI_LINEAR; 2026 if (mode->flags & VID_CSYNC) 2027 v |= RADEON_CRTC_VSYNC_TRISTAT; 2028 } 2029 /* unconditional turn on CRT, in case first CRTC is DFP */ 2030 v |= RADEON_CRTC_CRT_ON; 2031 PUT32(sc, RADEON_CRTC_EXT_CNTL, v); 2032 PRINTREG(RADEON_CRTC_EXT_CNTL); 2033 2034 /* 2035 * H_TOTAL_DISP 2036 */ 2037 v = ((mode->hdisplay / 8) - 1) << 16; 2038 v |= (mode->htotal / 8) - 1; 2039 PUT32(sc, htotaldisp, v); 2040 DPRINTF(("CRTC%s_H_TOTAL_DISP = %08x\n", crtc ? "2" : "", v)); 2041 PUT32(sc, fphtotaldisp, v); 2042 DPRINTF(("FP_H%s_TOTAL_DISP = %08x\n", crtc ? "2" : "", v)); 2043 2044 /* 2045 * H_SYNC_STRT_WID 2046 */ 2047 v = (((mode->hsync_end - mode->hsync_start) / 8) << 16); 2048 v |= mode->hsync_start; 2049 if (mode->flags & VID_NHSYNC) 2050 v |= RADEON_CRTC_H_SYNC_POL; 2051 PUT32(sc, hsyncstrt, v); 2052 DPRINTF(("CRTC%s_H_SYNC_STRT_WID = %08x\n", crtc ? "2" : "", v)); 2053 PUT32(sc, fphsyncstrt, v); 2054 DPRINTF(("FP_H%s_SYNC_STRT_WID = %08x\n", crtc ? "2" : "", v)); 2055 2056 /* 2057 * V_TOTAL_DISP 2058 */ 2059 v = ((mode->vdisplay - 1) << 16); 2060 v |= (mode->vtotal - 1); 2061 PUT32(sc, vtotaldisp, v); 2062 DPRINTF(("CRTC%s_V_TOTAL_DISP = %08x\n", crtc ? "2" : "", v)); 2063 PUT32(sc, fpvtotaldisp, v); 2064 DPRINTF(("FP_V%s_TOTAL_DISP = %08x\n", crtc ? "2" : "", v)); 2065 2066 /* 2067 * V_SYNC_STRT_WID 2068 */ 2069 v = ((mode->vsync_end - mode->vsync_start) << 16); 2070 v |= (mode->vsync_start - 1); 2071 if (mode->flags & VID_NVSYNC) 2072 v |= RADEON_CRTC_V_SYNC_POL; 2073 PUT32(sc, vsyncstrt, v); 2074 DPRINTF(("CRTC%s_V_SYNC_STRT_WID = %08x\n", crtc ? "2" : "", v)); 2075 PUT32(sc, fpvsyncstrt, v); 2076 DPRINTF(("FP_V%s_SYNC_STRT_WID = %08x\n", crtc ? "2" : "", v)); 2077 2078 radeonfb_program_vclk(sc, mode->dot_clock, crtc); 2079 2080 switch (crtc) { 2081 case 0: 2082 PUT32(sc, RADEON_CRTC_OFFSET, 0); 2083 PUT32(sc, RADEON_CRTC_OFFSET_CNTL, 0); 2084 PUT32(sc, RADEON_CRTC_PITCH, pitch); 2085 CLR32(sc, RADEON_DISP_MERGE_CNTL, RADEON_DISP_RGB_OFFSET_EN); 2086 2087 CLR32(sc, RADEON_CRTC_EXT_CNTL, 2088 RADEON_CRTC_VSYNC_DIS | RADEON_CRTC_HSYNC_DIS | 2089 RADEON_CRTC_DISPLAY_DIS /* | RADEON_CRTC_DISP_REQ_EN_B */); 2090 CLR32(sc, RADEON_CRTC_GEN_CNTL, RADEON_CRTC_DISP_REQ_EN_B); 2091 PRINTREG(RADEON_CRTC_EXT_CNTL); 2092 PRINTREG(RADEON_CRTC_GEN_CNTL); 2093 PRINTREG(RADEON_CLOCK_CNTL_INDEX); 2094 break; 2095 2096 case 1: 2097 PUT32(sc, RADEON_CRTC2_OFFSET, 0); 2098 PUT32(sc, RADEON_CRTC2_OFFSET_CNTL, 0); 2099 PUT32(sc, RADEON_CRTC2_PITCH, pitch); 2100 CLR32(sc, RADEON_DISP2_MERGE_CNTL, RADEON_DISP2_RGB_OFFSET_EN); 2101 CLR32(sc, RADEON_CRTC2_GEN_CNTL, 2102 RADEON_CRTC2_VSYNC_DIS | 2103 RADEON_CRTC2_HSYNC_DIS | 2104 RADEON_CRTC2_DISP_DIS | RADEON_CRTC2_DISP_REQ_EN_B); 2105 PRINTREG(RADEON_CRTC2_GEN_CNTL); 2106 break; 2107 } 2108 } 2109 2110 int 2111 radeonfb_isblank(struct radeonfb_display *dp) 2112 { 2113 uint32_t reg, mask; 2114 2115 if (dp->rd_crtcs[0].rc_number) { 2116 reg = RADEON_CRTC2_GEN_CNTL; 2117 mask = RADEON_CRTC2_DISP_DIS; 2118 } else { 2119 reg = RADEON_CRTC_EXT_CNTL; 2120 mask = RADEON_CRTC_DISPLAY_DIS; 2121 } 2122 return ((GET32(dp->rd_softc, reg) & mask) ? 1 : 0); 2123 } 2124 2125 void 2126 radeonfb_blank(struct radeonfb_display *dp, int blank) 2127 { 2128 struct radeonfb_softc *sc = dp->rd_softc; 2129 uint32_t reg, mask; 2130 uint32_t fpreg, fpval; 2131 int i; 2132 2133 for (i = 0; i < dp->rd_ncrtcs; i++) { 2134 2135 if (dp->rd_crtcs[i].rc_number) { 2136 reg = RADEON_CRTC2_GEN_CNTL; 2137 mask = RADEON_CRTC2_DISP_DIS; 2138 fpreg = RADEON_FP2_GEN_CNTL; 2139 fpval = RADEON_FP2_ON; 2140 } else { 2141 reg = RADEON_CRTC_EXT_CNTL; 2142 mask = RADEON_CRTC_DISPLAY_DIS; 2143 fpreg = RADEON_FP_GEN_CNTL; 2144 fpval = RADEON_FP_FPON; 2145 } 2146 2147 if (blank) { 2148 SET32(sc, reg, mask); 2149 CLR32(sc, fpreg, fpval); 2150 } else { 2151 CLR32(sc, reg, mask); 2152 SET32(sc, fpreg, fpval); 2153 } 2154 } 2155 PRINTREG(RADEON_FP_GEN_CNTL); 2156 PRINTREG(RADEON_FP2_GEN_CNTL); 2157 } 2158 2159 void 2160 radeonfb_init_screen(void *cookie, struct vcons_screen *scr, int existing, 2161 long *defattr) 2162 { 2163 struct radeonfb_display *dp = cookie; 2164 struct rasops_info *ri = &scr->scr_ri; 2165 2166 /* initialize font subsystem */ 2167 wsfont_init(); 2168 2169 DPRINTF(("init screen called, existing %d\n", existing)); 2170 2171 ri->ri_depth = dp->rd_bpp; 2172 ri->ri_width = dp->rd_virtx; 2173 ri->ri_height = dp->rd_virty; 2174 ri->ri_stride = dp->rd_stride; 2175 ri->ri_flg = RI_CENTER; 2176 if (ri->ri_depth == 32) { 2177 ri->ri_flg |= RI_ENABLE_ALPHA; 2178 } 2179 ri->ri_bits = (void *)dp->rd_fbptr; 2180 2181 #ifdef VCONS_DRAW_INTR 2182 scr->scr_flags |= VCONS_DONT_READ; 2183 #endif 2184 2185 /* this is rgb in "big-endian order..." */ 2186 ri->ri_rnum = 8; 2187 ri->ri_gnum = 8; 2188 ri->ri_bnum = 8; 2189 ri->ri_rpos = 16; 2190 ri->ri_gpos = 8; 2191 ri->ri_bpos = 0; 2192 2193 if (existing) { 2194 ri->ri_flg |= RI_CLEAR; 2195 2196 /* start a modeswitch now */ 2197 radeonfb_modeswitch(dp); 2198 } 2199 2200 /* 2201 * XXX: font selection should be based on properties, with some 2202 * normal/reasonable default. 2203 */ 2204 2205 /* initialize and look for an initial font */ 2206 rasops_init(ri, 0, 0); 2207 ri->ri_caps = WSSCREEN_WSCOLORS; 2208 2209 rasops_reconfig(ri, dp->rd_virty / ri->ri_font->fontheight, 2210 dp->rd_virtx / ri->ri_font->fontwidth); 2211 2212 /* enable acceleration */ 2213 dp->rd_putchar = ri->ri_ops.putchar; 2214 ri->ri_ops.copyrows = radeonfb_copyrows; 2215 ri->ri_ops.copycols = radeonfb_copycols; 2216 ri->ri_ops.eraserows = radeonfb_eraserows; 2217 ri->ri_ops.erasecols = radeonfb_erasecols; 2218 /* pick a putchar method based on font and Radeon model */ 2219 if (ri->ri_font->stride < ri->ri_font->fontwidth) { 2220 /* got a bitmap font */ 2221 if (IS_R300(dp->rd_softc)) { 2222 /* 2223 * radeonfb_putchar() doesn't work right on some R3xx 2224 * so we use software drawing here, the wrapper just 2225 * makes sure the engine is idle before scribbling 2226 * into vram 2227 */ 2228 ri->ri_ops.putchar = radeonfb_putchar_wrapper; 2229 } else { 2230 ri->ri_ops.putchar = radeonfb_putchar; 2231 } 2232 } else { 2233 /* got an alpha font */ 2234 ri->ri_ops.putchar = radeonfb_putchar_aa32; 2235 } 2236 ri->ri_ops.cursor = radeonfb_cursor; 2237 } 2238 2239 void 2240 radeonfb_set_fbloc(struct radeonfb_softc *sc) 2241 { 2242 uint32_t gen, ext, gen2 = 0; 2243 uint32_t agploc, aperbase, apersize, mcfbloc; 2244 2245 gen = GET32(sc, RADEON_CRTC_GEN_CNTL); 2246 ext = GET32(sc, RADEON_CRTC_EXT_CNTL); 2247 agploc = GET32(sc, RADEON_MC_AGP_LOCATION); 2248 aperbase = GET32(sc, RADEON_CONFIG_APER_0_BASE); 2249 apersize = GET32(sc, RADEON_CONFIG_APER_SIZE); 2250 2251 PUT32(sc, RADEON_CRTC_GEN_CNTL, gen | RADEON_CRTC_DISP_REQ_EN_B); 2252 PUT32(sc, RADEON_CRTC_EXT_CNTL, ext | RADEON_CRTC_DISPLAY_DIS); 2253 //PUT32(sc, RADEON_CRTC_GEN_CNTL, gen | RADEON_CRTC_DISPLAY_DIS); 2254 //PUT32(sc, RADEON_CRTC_EXT_CNTL, ext | RADEON_CRTC_DISP_REQ_EN_B); 2255 2256 if (HAS_CRTC2(sc)) { 2257 gen2 = GET32(sc, RADEON_CRTC2_GEN_CNTL); 2258 PUT32(sc, RADEON_CRTC2_GEN_CNTL, 2259 gen2 | RADEON_CRTC2_DISP_REQ_EN_B); 2260 } 2261 2262 delay(100000); 2263 2264 mcfbloc = (aperbase >> 16) | 2265 ((aperbase + (apersize - 1)) & 0xffff0000); 2266 2267 sc->sc_aperbase = (mcfbloc & 0xffff) << 16; 2268 sc->sc_memsz = apersize; 2269 2270 if (((agploc & 0xffff) << 16) != 2271 ((mcfbloc & 0xffff0000U) + 0x10000)) { 2272 agploc = mcfbloc & 0xffff0000U; 2273 agploc |= ((agploc + 0x10000) >> 16); 2274 } 2275 2276 PUT32(sc, RADEON_HOST_PATH_CNTL, 0); 2277 2278 PUT32(sc, RADEON_MC_FB_LOCATION, mcfbloc); 2279 PUT32(sc, RADEON_MC_AGP_LOCATION, agploc); 2280 2281 DPRINTF(("aperbase = %u\n", aperbase)); 2282 PRINTREG(RADEON_MC_FB_LOCATION); 2283 PRINTREG(RADEON_MC_AGP_LOCATION); 2284 2285 PUT32(sc, RADEON_DISPLAY_BASE_ADDR, sc->sc_aperbase); 2286 2287 if (HAS_CRTC2(sc)) 2288 PUT32(sc, RADEON_DISPLAY2_BASE_ADDR, sc->sc_aperbase); 2289 2290 PUT32(sc, RADEON_OV0_BASE_ADDR, sc->sc_aperbase); 2291 2292 #if 0 2293 /* XXX: what is this AGP garbage? :-) */ 2294 PUT32(sc, RADEON_AGP_CNTL, 0x00100000); 2295 #endif 2296 2297 delay(100000); 2298 2299 PUT32(sc, RADEON_CRTC_GEN_CNTL, gen); 2300 PUT32(sc, RADEON_CRTC_EXT_CNTL, ext); 2301 2302 if (HAS_CRTC2(sc)) 2303 PUT32(sc, RADEON_CRTC2_GEN_CNTL, gen2); 2304 } 2305 2306 void 2307 radeonfb_init_misc(struct radeonfb_softc *sc) 2308 { 2309 PUT32(sc, RADEON_BUS_CNTL, 2310 RADEON_BUS_MASTER_DIS | 2311 RADEON_BUS_PREFETCH_MODE_ACT | 2312 RADEON_BUS_PCI_READ_RETRY_EN | 2313 RADEON_BUS_PCI_WRT_RETRY_EN | 2314 (3 << RADEON_BUS_RETRY_WS_SHIFT) | 2315 RADEON_BUS_MSTR_RD_MULT | 2316 RADEON_BUS_MSTR_RD_LINE | 2317 RADEON_BUS_RD_DISCARD_EN | 2318 RADEON_BUS_MSTR_DISCONNECT_EN | 2319 RADEON_BUS_READ_BURST); 2320 2321 PUT32(sc, RADEON_BUS_CNTL1, 0xf0); 2322 /* PUT32(sc, RADEON_SEPROM_CNTL1, 0x09ff0000); */ 2323 PUT32(sc, RADEON_FCP_CNTL, RADEON_FCP0_SRC_GND); 2324 PUT32(sc, RADEON_RBBM_CNTL, 2325 (3 << RADEON_RB_SETTLE_SHIFT) | 2326 (4 << RADEON_ABORTCLKS_HI_SHIFT) | 2327 (4 << RADEON_ABORTCLKS_CP_SHIFT) | 2328 (4 << RADEON_ABORTCLKS_CFIFO_SHIFT)); 2329 2330 /* XXX: figure out what these mean! */ 2331 PUT32(sc, RADEON_AGP_CNTL, 0x00100000); 2332 PUT32(sc, RADEON_HOST_PATH_CNTL, 0); 2333 //PUT32(sc, RADEON_DISP_MISC_CNTL, 0x5bb00400); 2334 2335 PUT32(sc, RADEON_GEN_INT_CNTL, 0); 2336 PUT32(sc, RADEON_GEN_INT_STATUS, GET32(sc, RADEON_GEN_INT_STATUS)); 2337 } 2338 2339 /* 2340 * This loads a linear color map for true color. 2341 */ 2342 void 2343 radeonfb_init_palette(struct radeonfb_softc *sc, int crtc) 2344 { 2345 int i; 2346 uint32_t vclk; 2347 2348 #define DAC_WIDTH ((1 << 10) - 1) 2349 #define CLUT_WIDTH ((1 << 8) - 1) 2350 #define CLUT_COLOR(i) ((i * DAC_WIDTH * 2 / CLUT_WIDTH + 1) / 2) 2351 2352 vclk = GETPLL(sc, RADEON_VCLK_ECP_CNTL); 2353 PUTPLL(sc, RADEON_VCLK_ECP_CNTL, vclk & ~RADEON_PIXCLK_DAC_ALWAYS_ONb); 2354 2355 if (crtc) 2356 SET32(sc, RADEON_DAC_CNTL2, RADEON_DAC2_PALETTE_ACC_CTL); 2357 else 2358 CLR32(sc, RADEON_DAC_CNTL2, RADEON_DAC2_PALETTE_ACC_CTL); 2359 2360 PUT32(sc, RADEON_PALETTE_INDEX, 0); 2361 if (sc->sc_displays[crtc].rd_bpp == 0) 2362 sc->sc_displays[crtc].rd_bpp = RADEONFB_DEFAULT_DEPTH; 2363 2364 if (sc->sc_displays[crtc].rd_bpp == 8) { 2365 /* ANSI palette */ 2366 int j = 0; 2367 2368 for (i = 0; i <= CLUT_WIDTH; ++i) { 2369 PUT32(sc, RADEON_PALETTE_30_DATA, 2370 (rasops_cmap[j] << 22) | 2371 (rasops_cmap[j + 1] << 12) | 2372 (rasops_cmap[j + 2] << 2)); 2373 j += 3; 2374 } 2375 } else { 2376 /* linear ramp */ 2377 for (i = 0; i <= CLUT_WIDTH; ++i) { 2378 PUT32(sc, RADEON_PALETTE_30_DATA, 2379 (CLUT_COLOR(i) << 10) | 2380 (CLUT_COLOR(i) << 20) | 2381 (CLUT_COLOR(i))); 2382 } 2383 } 2384 2385 CLR32(sc, RADEON_DAC_CNTL2, RADEON_DAC2_PALETTE_ACC_CTL); 2386 PRINTREG(RADEON_DAC_CNTL2); 2387 2388 PUTPLL(sc, RADEON_VCLK_ECP_CNTL, vclk); 2389 } 2390 2391 /* 2392 * Bugs in some R300 hardware requires this when accessing CLOCK_CNTL_INDEX. 2393 */ 2394 void 2395 radeonfb_r300cg_workaround(struct radeonfb_softc *sc) 2396 { 2397 uint32_t tmp, save; 2398 2399 save = GET32(sc, RADEON_CLOCK_CNTL_INDEX); 2400 tmp = save & ~(0x3f | RADEON_PLL_WR_EN); 2401 PUT32(sc, RADEON_CLOCK_CNTL_INDEX, tmp); 2402 tmp = GET32(sc, RADEON_CLOCK_CNTL_DATA); 2403 PUT32(sc, RADEON_CLOCK_CNTL_INDEX, save); 2404 } 2405 2406 /* 2407 * Acceleration entry points. 2408 */ 2409 2410 /* this one draws characters using bitmap fonts */ 2411 static void 2412 radeonfb_putchar(void *cookie, int row, int col, u_int c, long attr) 2413 { 2414 struct rasops_info *ri = cookie; 2415 struct vcons_screen *scr = ri->ri_hw; 2416 struct radeonfb_display *dp = scr->scr_cookie; 2417 struct radeonfb_softc *sc = dp->rd_softc; 2418 struct wsdisplay_font *font = PICK_FONT(ri, c); 2419 uint32_t w, h; 2420 int xd, yd, offset, i; 2421 uint32_t bg, fg, gmc; 2422 uint32_t reg; 2423 uint8_t *data8; 2424 uint16_t *data16; 2425 void *data; 2426 2427 if (dp->rd_wsmode != WSDISPLAYIO_MODE_EMUL) 2428 return; 2429 2430 if (!CHAR_IN_FONT(c, font)) 2431 return; 2432 2433 w = font->fontwidth; 2434 h = font->fontheight; 2435 2436 bg = ri->ri_devcmap[(attr >> 16) & 0xf]; 2437 fg = ri->ri_devcmap[(attr >> 24) & 0xf]; 2438 2439 xd = ri->ri_xorigin + col * w; 2440 yd = ri->ri_yorigin + row * h; 2441 2442 if (c == 0x20) { 2443 radeonfb_rectfill(dp, xd, yd, w, h, bg); 2444 return; 2445 } 2446 data = WSFONT_GLYPH(c, font); 2447 2448 gmc = dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT; 2449 2450 radeonfb_wait_fifo(sc, 9); 2451 2452 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 2453 RADEON_GMC_BRUSH_NONE | 2454 RADEON_GMC_SRC_DATATYPE_MONO_FG_BG | 2455 RADEON_GMC_DST_CLIPPING | 2456 RADEON_ROP3_S | 2457 RADEON_DP_SRC_SOURCE_HOST_DATA | 2458 RADEON_GMC_CLR_CMP_CNTL_DIS | 2459 RADEON_GMC_WR_MSK_DIS | 2460 gmc); 2461 2462 PUT32(sc, RADEON_SC_LEFT, xd); 2463 PUT32(sc, RADEON_SC_RIGHT, xd + w); 2464 PUT32(sc, RADEON_DP_SRC_FRGD_CLR, fg); 2465 PUT32(sc, RADEON_DP_SRC_BKGD_CLR, bg); 2466 PUT32(sc, RADEON_DP_CNTL, 2467 RADEON_DST_X_LEFT_TO_RIGHT | 2468 RADEON_DST_Y_TOP_TO_BOTTOM); 2469 2470 PUT32(sc, RADEON_SRC_X_Y, 0); 2471 offset = 32 - (font->stride << 3); 2472 PUT32(sc, RADEON_DST_X_Y, ((xd - offset) << 16) | yd); 2473 PUT32(sc, RADEON_DST_WIDTH_HEIGHT, (32 << 16) | h); 2474 2475 radeonfb_wait_fifo(sc, h); 2476 switch (font->stride) { 2477 case 1: { 2478 data8 = data; 2479 for (i = 0; i < h; i++) { 2480 reg = *data8; 2481 bus_space_write_stream_4(sc->sc_regt, 2482 sc->sc_regh, RADEON_HOST_DATA0, reg); 2483 data8++; 2484 } 2485 break; 2486 } 2487 case 2: { 2488 data16 = data; 2489 for (i = 0; i < h; i++) { 2490 reg = *data16; 2491 bus_space_write_stream_4(sc->sc_regt, 2492 sc->sc_regh, RADEON_HOST_DATA0, reg); 2493 data16++; 2494 } 2495 break; 2496 } 2497 } 2498 } 2499 2500 /* ... while this one is for anti-aliased ones */ 2501 static void 2502 radeonfb_putchar_aa32(void *cookie, int row, int col, u_int c, long attr) 2503 { 2504 struct rasops_info *ri = cookie; 2505 struct vcons_screen *scr = ri->ri_hw; 2506 struct radeonfb_display *dp = scr->scr_cookie; 2507 struct radeonfb_softc *sc = dp->rd_softc; 2508 struct wsdisplay_font *font = PICK_FONT(ri, c); 2509 uint32_t bg, fg, gmc; 2510 uint8_t *data; 2511 int w, h, xd, yd; 2512 int i, r, g, b, aval; 2513 int rf, gf, bf, rb, gb, bb; 2514 uint32_t pixel; 2515 2516 if (dp->rd_wsmode != WSDISPLAYIO_MODE_EMUL) 2517 return; 2518 2519 if (!CHAR_IN_FONT(c, font)) 2520 return; 2521 2522 w = font->fontwidth; 2523 h = font->fontheight; 2524 2525 bg = ri->ri_devcmap[(attr >> 16) & 0xf]; 2526 fg = ri->ri_devcmap[(attr >> 24) & 0xf]; 2527 2528 xd = ri->ri_xorigin + col * w; 2529 yd = ri->ri_yorigin + row * h; 2530 2531 if (c == 0x20) { 2532 radeonfb_rectfill(dp, xd, yd, w, h, bg); 2533 return; 2534 } 2535 data = WSFONT_GLYPH(c, font); 2536 2537 gmc = dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT; 2538 2539 radeonfb_wait_fifo(sc, 5); 2540 2541 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 2542 RADEON_GMC_BRUSH_NONE | 2543 RADEON_GMC_SRC_DATATYPE_COLOR | 2544 RADEON_ROP3_S | 2545 RADEON_DP_SRC_SOURCE_HOST_DATA | 2546 RADEON_GMC_CLR_CMP_CNTL_DIS | 2547 RADEON_GMC_WR_MSK_DIS | 2548 gmc); 2549 2550 PUT32(sc, RADEON_DP_CNTL, 2551 RADEON_DST_X_LEFT_TO_RIGHT | 2552 RADEON_DST_Y_TOP_TO_BOTTOM); 2553 2554 PUT32(sc, RADEON_SRC_X_Y, 0); 2555 PUT32(sc, RADEON_DST_X_Y, (xd << 16) | yd); 2556 PUT32(sc, RADEON_DST_WIDTH_HEIGHT, (w << 16) | h); 2557 2558 rf = (fg >> 16) & 0xff; 2559 rb = (bg >> 16) & 0xff; 2560 gf = (fg >> 8) & 0xff; 2561 gb = (bg >> 8) & 0xff; 2562 bf = fg & 0xff; 2563 bb = bg & 0xff; 2564 2565 /* 2566 * I doubt we can upload data faster than even the slowest Radeon 2567 * could process them, especially when doing the alpha blending stuff 2568 * along the way, so just make sure there's some room in the FIFO and 2569 * then hammer away 2570 * As it turns out we can, so make periodic stops to let the FIFO 2571 * drain. 2572 */ 2573 radeonfb_wait_fifo(sc, 20); 2574 for (i = 0; i < ri->ri_fontscale; i++) { 2575 aval = *data; 2576 data++; 2577 if (aval == 0) { 2578 pixel = bg; 2579 } else if (aval == 255) { 2580 pixel = fg; 2581 } else { 2582 r = aval * rf + (255 - aval) * rb; 2583 g = aval * gf + (255 - aval) * gb; 2584 b = aval * bf + (255 - aval) * bb; 2585 pixel = (r & 0xff00) << 8 | 2586 (g & 0xff00) | 2587 (b & 0xff00) >> 8; 2588 } 2589 if (i & 16) 2590 radeonfb_wait_fifo(sc, 20); 2591 PUT32(sc, RADEON_HOST_DATA0, pixel); 2592 } 2593 } 2594 2595 /* 2596 * wrapper for software character drawing 2597 * just sync the engine and call rasops*_putchar() 2598 */ 2599 2600 static void 2601 radeonfb_putchar_wrapper(void *cookie, int row, int col, u_int c, long attr) 2602 { 2603 struct rasops_info *ri = cookie; 2604 struct vcons_screen *scr = ri->ri_hw; 2605 struct radeonfb_display *dp = scr->scr_cookie; 2606 2607 radeonfb_engine_idle(dp->rd_softc); 2608 dp->rd_putchar(ri, row, col, c, attr); 2609 } 2610 2611 static void 2612 radeonfb_eraserows(void *cookie, int row, int nrows, long fillattr) 2613 { 2614 struct rasops_info *ri = cookie; 2615 struct vcons_screen *scr = ri->ri_hw; 2616 struct radeonfb_display *dp = scr->scr_cookie; 2617 uint32_t x, y, w, h, fg, bg, ul; 2618 2619 /* XXX: check for full emulation mode? */ 2620 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 2621 x = ri->ri_xorigin; 2622 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 2623 w = ri->ri_emuwidth; 2624 h = ri->ri_font->fontheight * nrows; 2625 2626 rasops_unpack_attr(fillattr, &fg, &bg, &ul); 2627 radeonfb_rectfill(dp, x, y, w, h, ri->ri_devcmap[bg & 0xf]); 2628 } 2629 } 2630 2631 static void 2632 radeonfb_copyrows(void *cookie, int srcrow, int dstrow, int nrows) 2633 { 2634 struct rasops_info *ri = cookie; 2635 struct vcons_screen *scr = ri->ri_hw; 2636 struct radeonfb_display *dp = scr->scr_cookie; 2637 uint32_t x, ys, yd, w, h; 2638 2639 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 2640 x = ri->ri_xorigin; 2641 ys = ri->ri_yorigin + ri->ri_font->fontheight * srcrow; 2642 yd = ri->ri_yorigin + ri->ri_font->fontheight * dstrow; 2643 w = ri->ri_emuwidth; 2644 h = ri->ri_font->fontheight * nrows; 2645 radeonfb_bitblt(dp, x, ys, x, yd, w, h, 2646 RADEON_ROP3_S, 0xffffffff); 2647 } 2648 } 2649 2650 static void 2651 radeonfb_copycols(void *cookie, int row, int srccol, int dstcol, int ncols) 2652 { 2653 struct rasops_info *ri = cookie; 2654 struct vcons_screen *scr = ri->ri_hw; 2655 struct radeonfb_display *dp = scr->scr_cookie; 2656 uint32_t xs, xd, y, w, h; 2657 2658 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 2659 xs = ri->ri_xorigin + ri->ri_font->fontwidth * srccol; 2660 xd = ri->ri_xorigin + ri->ri_font->fontwidth * dstcol; 2661 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 2662 w = ri->ri_font->fontwidth * ncols; 2663 h = ri->ri_font->fontheight; 2664 radeonfb_bitblt(dp, xs, y, xd, y, w, h, 2665 RADEON_ROP3_S, 0xffffffff); 2666 } 2667 } 2668 2669 static void 2670 radeonfb_erasecols(void *cookie, int row, int startcol, int ncols, 2671 long fillattr) 2672 { 2673 struct rasops_info *ri = cookie; 2674 struct vcons_screen *scr = ri->ri_hw; 2675 struct radeonfb_display *dp = scr->scr_cookie; 2676 uint32_t x, y, w, h, fg, bg, ul; 2677 2678 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 2679 x = ri->ri_xorigin + ri->ri_font->fontwidth * startcol; 2680 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 2681 w = ri->ri_font->fontwidth * ncols; 2682 h = ri->ri_font->fontheight; 2683 2684 rasops_unpack_attr(fillattr, &fg, &bg, &ul); 2685 radeonfb_rectfill(dp, x, y, w, h, ri->ri_devcmap[bg & 0xf]); 2686 } 2687 } 2688 2689 static void 2690 radeonfb_cursor(void *cookie, int on, int row, int col) 2691 { 2692 struct rasops_info *ri = cookie; 2693 struct vcons_screen *scr = ri->ri_hw; 2694 struct radeonfb_display *dp = scr->scr_cookie; 2695 int x, y, wi, he; 2696 2697 wi = ri->ri_font->fontwidth; 2698 he = ri->ri_font->fontheight; 2699 2700 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 2701 x = ri->ri_ccol * wi + ri->ri_xorigin; 2702 y = ri->ri_crow * he + ri->ri_yorigin; 2703 /* first turn off the old cursor */ 2704 if (ri->ri_flg & RI_CURSOR) { 2705 radeonfb_bitblt(dp, x, y, x, y, wi, he, 2706 RADEON_ROP3_Dn, 0xffffffff); 2707 ri->ri_flg &= ~RI_CURSOR; 2708 } 2709 ri->ri_crow = row; 2710 ri->ri_ccol = col; 2711 /* then (possibly) turn on the new one */ 2712 if (on) { 2713 x = ri->ri_ccol * wi + ri->ri_xorigin; 2714 y = ri->ri_crow * he + ri->ri_yorigin; 2715 radeonfb_bitblt(dp, x, y, x, y, wi, he, 2716 RADEON_ROP3_Dn, 0xffffffff); 2717 ri->ri_flg |= RI_CURSOR; 2718 } 2719 } else { 2720 scr->scr_ri.ri_crow = row; 2721 scr->scr_ri.ri_ccol = col; 2722 scr->scr_ri.ri_flg &= ~RI_CURSOR; 2723 } 2724 } 2725 2726 /* 2727 * Underlying acceleration support. 2728 */ 2729 2730 static void 2731 radeonfb_rectfill(struct radeonfb_display *dp, int dstx, int dsty, 2732 int width, int height, uint32_t color) 2733 { 2734 struct radeonfb_softc *sc = dp->rd_softc; 2735 uint32_t gmc; 2736 2737 gmc = dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT; 2738 2739 radeonfb_wait_fifo(sc, 6); 2740 2741 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 2742 RADEON_GMC_BRUSH_SOLID_COLOR | 2743 RADEON_GMC_SRC_DATATYPE_COLOR | 2744 RADEON_GMC_CLR_CMP_CNTL_DIS | 2745 RADEON_ROP3_P | gmc); 2746 2747 PUT32(sc, RADEON_DP_BRUSH_FRGD_CLR, color); 2748 PUT32(sc, RADEON_DP_WRITE_MASK, 0xffffffff); 2749 PUT32(sc, RADEON_DP_CNTL, 2750 RADEON_DST_X_LEFT_TO_RIGHT | 2751 RADEON_DST_Y_TOP_TO_BOTTOM); 2752 PUT32(sc, RADEON_DST_Y_X, (dsty << 16) | dstx); 2753 PUT32(sc, RADEON_DST_WIDTH_HEIGHT, (width << 16) | (height)); 2754 2755 } 2756 2757 static void 2758 radeonfb_bitblt(struct radeonfb_display *dp, int srcx, int srcy, 2759 int dstx, int dsty, int width, int height, int rop, uint32_t mask) 2760 { 2761 struct radeonfb_softc *sc = dp->rd_softc; 2762 uint32_t gmc; 2763 uint32_t dir; 2764 2765 if (dsty < srcy) { 2766 dir = RADEON_DST_Y_TOP_TO_BOTTOM; 2767 } else { 2768 srcy += height - 1; 2769 dsty += height - 1; 2770 dir = 0; 2771 } 2772 if (dstx < srcx) { 2773 dir |= RADEON_DST_X_LEFT_TO_RIGHT; 2774 } else { 2775 srcx += width - 1; 2776 dstx += width - 1; 2777 } 2778 2779 gmc = dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT; 2780 2781 radeonfb_wait_fifo(sc, 6); 2782 2783 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 2784 RADEON_GMC_BRUSH_SOLID_COLOR | 2785 RADEON_GMC_SRC_DATATYPE_COLOR | 2786 RADEON_GMC_CLR_CMP_CNTL_DIS | 2787 RADEON_DP_SRC_SOURCE_MEMORY | 2788 rop | gmc); 2789 2790 PUT32(sc, RADEON_DP_WRITE_MASK, mask); 2791 PUT32(sc, RADEON_DP_CNTL, dir); 2792 PUT32(sc, RADEON_SRC_Y_X, (srcy << 16) | srcx); 2793 PUT32(sc, RADEON_DST_Y_X, (dsty << 16) | dstx); 2794 PUT32(sc, RADEON_DST_WIDTH_HEIGHT, (width << 16) | (height)); 2795 } 2796 2797 static void 2798 radeonfb_engine_idle(struct radeonfb_softc *sc) 2799 { 2800 2801 radeonfb_wait_fifo(sc, 64); 2802 while ((GET32(sc, RADEON_RBBM_STATUS) & 2803 RADEON_RBBM_ACTIVE) != 0); 2804 radeonfb_engine_flush(sc); 2805 } 2806 2807 static void 2808 radeonfb_wait_fifo(struct radeonfb_softc *sc, int n) 2809 { 2810 int i; 2811 2812 for (i = RADEON_TIMEOUT; i; i--) { 2813 if ((GET32(sc, RADEON_RBBM_STATUS) & 2814 RADEON_RBBM_FIFOCNT_MASK) >= n) 2815 return; 2816 } 2817 #ifdef DIAGNOSTIC 2818 if (!i) 2819 printf("%s: timed out waiting for fifo (%x)\n", 2820 XNAME(sc), GET32(sc, RADEON_RBBM_STATUS)); 2821 #endif 2822 } 2823 2824 static void 2825 radeonfb_engine_flush(struct radeonfb_softc *sc) 2826 { 2827 int i = 0; 2828 2829 if (IS_R300(sc)) { 2830 SET32(sc, R300_DSTCACHE_CTLSTAT, R300_RB2D_DC_FLUSH_ALL); 2831 while (GET32(sc, R300_DSTCACHE_CTLSTAT) & R300_RB2D_DC_BUSY) { 2832 i++; 2833 } 2834 } else { 2835 SET32(sc, RADEON_RB2D_DSTCACHE_CTLSTAT, 2836 RADEON_RB2D_DC_FLUSH_ALL); 2837 while (GET32(sc, RADEON_RB2D_DSTCACHE_CTLSTAT) & 2838 RADEON_RB2D_DC_BUSY) { 2839 i++; 2840 } 2841 } 2842 #ifdef DIAGNOSTIC 2843 if (i > RADEON_TIMEOUT) 2844 printf("%s: engine flush timed out!\n", XNAME(sc)); 2845 #endif 2846 } 2847 2848 static inline void 2849 radeonfb_unclip(struct radeonfb_softc *sc) 2850 { 2851 2852 radeonfb_wait_fifo(sc, 2); 2853 PUT32(sc, RADEON_SC_TOP_LEFT, 0); 2854 PUT32(sc, RADEON_SC_BOTTOM_RIGHT, 0x1fff1fff); 2855 } 2856 2857 static void 2858 radeonfb_engine_init(struct radeonfb_display *dp) 2859 { 2860 struct radeonfb_softc *sc = dp->rd_softc; 2861 uint32_t pitch; 2862 volatile uint32_t junk; 2863 2864 /* no 3D */ 2865 PUT32(sc, RADEON_RB3D_CNTL, 0); 2866 2867 radeonfb_engine_reset(sc); 2868 pitch = ((dp->rd_virtx * (dp->rd_bpp / 8) + 0x3f)) >> 6; 2869 2870 radeonfb_wait_fifo(sc, 1); 2871 if (!IS_R300(sc)) 2872 PUT32(sc, RADEON_RB2D_DSTCACHE_MODE, 0); 2873 2874 radeonfb_wait_fifo(sc, 3); 2875 PUT32(sc, RADEON_DEFAULT_PITCH_OFFSET, 2876 (pitch << 22) | (sc->sc_aperbase >> 10)); 2877 2878 2879 PUT32(sc, RADEON_DST_PITCH_OFFSET, 2880 (pitch << 22) | (sc->sc_aperbase >> 10)); 2881 PUT32(sc, RADEON_SRC_PITCH_OFFSET, 2882 (pitch << 22) | (sc->sc_aperbase >> 10)); 2883 2884 radeonfb_wait_fifo(sc, 1); 2885 #if _BYTE_ORDER == _BIG_ENDIAN 2886 SET32(sc, RADEON_DP_DATATYPE, RADEON_HOST_BIG_ENDIAN_EN); 2887 #else 2888 CLR32(sc, RADEON_DP_DATATYPE, RADEON_HOST_BIG_ENDIAN_EN); 2889 #endif 2890 junk = GET32(sc, RADEON_DP_DATATYPE); 2891 2892 /* default scissors -- no clipping */ 2893 radeonfb_wait_fifo(sc, 1); 2894 PUT32(sc, RADEON_DEFAULT_SC_BOTTOM_RIGHT, 2895 RADEON_DEFAULT_SC_RIGHT_MAX | RADEON_DEFAULT_SC_BOTTOM_MAX); 2896 2897 radeonfb_wait_fifo(sc, 1); 2898 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 2899 (dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT) | 2900 RADEON_GMC_CLR_CMP_CNTL_DIS | 2901 RADEON_GMC_BRUSH_SOLID_COLOR | 2902 RADEON_GMC_SRC_DATATYPE_COLOR); 2903 2904 radeonfb_wait_fifo(sc, 10); 2905 PUT32(sc, RADEON_DST_LINE_START, 0); 2906 PUT32(sc, RADEON_DST_LINE_END, 0); 2907 PUT32(sc, RADEON_DP_BRUSH_FRGD_CLR, 0xffffffff); 2908 PUT32(sc, RADEON_DP_BRUSH_BKGD_CLR, 0); 2909 PUT32(sc, RADEON_DP_SRC_FRGD_CLR, 0xffffffff); 2910 PUT32(sc, RADEON_DP_SRC_BKGD_CLR, 0); 2911 PUT32(sc, RADEON_DP_WRITE_MASK, 0xffffffff); 2912 PUT32(sc, RADEON_SC_TOP_LEFT, 0); 2913 PUT32(sc, RADEON_SC_BOTTOM_RIGHT, 0x1fff1fff); 2914 PUT32(sc, RADEON_AUX_SC_CNTL, 0); 2915 radeonfb_engine_idle(sc); 2916 } 2917 2918 static void 2919 radeonfb_engine_reset(struct radeonfb_softc *sc) 2920 { 2921 uint32_t hpc, rbbm, mclkcntl, clkindex; 2922 2923 radeonfb_engine_flush(sc); 2924 2925 clkindex = GET32(sc, RADEON_CLOCK_CNTL_INDEX); 2926 if (HAS_R300CG(sc)) 2927 radeonfb_r300cg_workaround(sc); 2928 mclkcntl = GETPLL(sc, RADEON_MCLK_CNTL); 2929 2930 /* 2931 * According to comments in XFree code, resetting the HDP via 2932 * the RBBM_SOFT_RESET can cause bad behavior on some systems. 2933 * So we use HOST_PATH_CNTL instead. 2934 */ 2935 2936 hpc = GET32(sc, RADEON_HOST_PATH_CNTL); 2937 rbbm = GET32(sc, RADEON_RBBM_SOFT_RESET); 2938 if (IS_R300(sc)) { 2939 PUT32(sc, RADEON_RBBM_SOFT_RESET, rbbm | 2940 RADEON_SOFT_RESET_CP | 2941 RADEON_SOFT_RESET_HI | 2942 RADEON_SOFT_RESET_E2); 2943 GET32(sc, RADEON_RBBM_SOFT_RESET); 2944 PUT32(sc, RADEON_RBBM_SOFT_RESET, 0); 2945 /* 2946 * XXX: this bit is not defined in any ATI docs I have, 2947 * nor in the XFree code, but XFree does it. Why? 2948 */ 2949 SET32(sc, RADEON_RB2D_DSTCACHE_MODE, (1<<17)); 2950 } else { 2951 PUT32(sc, RADEON_RBBM_SOFT_RESET, rbbm | 2952 RADEON_SOFT_RESET_CP | 2953 RADEON_SOFT_RESET_SE | 2954 RADEON_SOFT_RESET_RE | 2955 RADEON_SOFT_RESET_PP | 2956 RADEON_SOFT_RESET_E2 | 2957 RADEON_SOFT_RESET_RB); 2958 GET32(sc, RADEON_RBBM_SOFT_RESET); 2959 PUT32(sc, RADEON_RBBM_SOFT_RESET, rbbm & 2960 ~(RADEON_SOFT_RESET_CP | 2961 RADEON_SOFT_RESET_SE | 2962 RADEON_SOFT_RESET_RE | 2963 RADEON_SOFT_RESET_PP | 2964 RADEON_SOFT_RESET_E2 | 2965 RADEON_SOFT_RESET_RB)); 2966 GET32(sc, RADEON_RBBM_SOFT_RESET); 2967 } 2968 2969 PUT32(sc, RADEON_HOST_PATH_CNTL, hpc | RADEON_HDP_SOFT_RESET); 2970 GET32(sc, RADEON_HOST_PATH_CNTL); 2971 PUT32(sc, RADEON_HOST_PATH_CNTL, hpc); 2972 2973 if (IS_R300(sc)) 2974 PUT32(sc, RADEON_RBBM_SOFT_RESET, rbbm); 2975 2976 PUT32(sc, RADEON_CLOCK_CNTL_INDEX, clkindex); 2977 PUTPLL(sc, RADEON_MCLK_CNTL, mclkcntl); 2978 2979 if (HAS_R300CG(sc)) 2980 radeonfb_r300cg_workaround(sc); 2981 } 2982 2983 static int 2984 radeonfb_set_curpos(struct radeonfb_display *dp, struct wsdisplay_curpos *pos) 2985 { 2986 int x, y; 2987 2988 x = pos->x; 2989 y = pos->y; 2990 2991 /* 2992 * This doesn't let a cursor move off the screen. I'm not 2993 * sure if this will have negative effects for e.g. Xinerama. 2994 * I'd guess Xinerama handles it by changing the cursor shape, 2995 * but that needs verification. 2996 */ 2997 if (x >= dp->rd_virtx) 2998 x = dp->rd_virtx - 1; 2999 if (x < 0) 3000 x = 0; 3001 if (y >= dp->rd_virty) 3002 y = dp->rd_virty - 1; 3003 if (y < 0) 3004 y = 0; 3005 3006 dp->rd_cursor.rc_pos.x = x; 3007 dp->rd_cursor.rc_pos.y = y; 3008 3009 radeonfb_cursor_position(dp); 3010 return 0; 3011 } 3012 3013 static int 3014 radeonfb_set_cursor(struct radeonfb_display *dp, struct wsdisplay_cursor *wc) 3015 { 3016 unsigned flags; 3017 3018 uint8_t r[2], g[2], b[2]; 3019 unsigned index, count; 3020 int i, err; 3021 int pitch, size; 3022 struct radeonfb_cursor nc; 3023 3024 flags = wc->which; 3025 3026 /* copy old values */ 3027 nc = dp->rd_cursor; 3028 3029 if (flags & WSDISPLAY_CURSOR_DOCMAP) { 3030 index = wc->cmap.index; 3031 count = wc->cmap.count; 3032 3033 if (index >= 2 || (index + count) > 2) 3034 return EINVAL; 3035 3036 err = copyin(wc->cmap.red, &r[index], count); 3037 if (err) 3038 return err; 3039 err = copyin(wc->cmap.green, &g[index], count); 3040 if (err) 3041 return err; 3042 err = copyin(wc->cmap.blue, &b[index], count); 3043 if (err) 3044 return err; 3045 3046 for (i = index; i < index + count; i++) { 3047 nc.rc_cmap[i] = 3048 (r[i] << 16) + (g[i] << 8) + (b[i] << 0); 3049 } 3050 } 3051 3052 if (flags & WSDISPLAY_CURSOR_DOSHAPE) { 3053 if ((wc->size.x > RADEON_CURSORMAXX) || 3054 (wc->size.y > RADEON_CURSORMAXY)) 3055 return EINVAL; 3056 3057 /* figure bytes per line */ 3058 pitch = (wc->size.x + 7) / 8; 3059 size = pitch * wc->size.y; 3060 3061 /* clear the old cursor and mask */ 3062 memset(nc.rc_image, 0, 512); 3063 memset(nc.rc_mask, 0, 512); 3064 3065 nc.rc_size = wc->size; 3066 3067 if ((err = copyin(wc->image, nc.rc_image, size)) != 0) 3068 return err; 3069 3070 if ((err = copyin(wc->mask, nc.rc_mask, size)) != 0) 3071 return err; 3072 } 3073 3074 if (flags & WSDISPLAY_CURSOR_DOHOT) { 3075 nc.rc_hot = wc->hot; 3076 if (nc.rc_hot.x >= nc.rc_size.x) 3077 nc.rc_hot.x = nc.rc_size.x - 1; 3078 if (nc.rc_hot.y >= nc.rc_size.y) 3079 nc.rc_hot.y = nc.rc_size.y - 1; 3080 } 3081 3082 if (flags & WSDISPLAY_CURSOR_DOPOS) { 3083 nc.rc_pos = wc->pos; 3084 if (nc.rc_pos.x >= dp->rd_virtx) 3085 nc.rc_pos.x = dp->rd_virtx - 1; 3086 #if 0 3087 if (nc.rc_pos.x < 0) 3088 nc.rc_pos.x = 0; 3089 #endif 3090 if (nc.rc_pos.y >= dp->rd_virty) 3091 nc.rc_pos.y = dp->rd_virty - 1; 3092 #if 0 3093 if (nc.rc_pos.y < 0) 3094 nc.rc_pos.y = 0; 3095 #endif 3096 } 3097 if (flags & WSDISPLAY_CURSOR_DOCUR) { 3098 nc.rc_visible = wc->enable; 3099 } 3100 3101 dp->rd_cursor = nc; 3102 radeonfb_cursor_update(dp, wc->which); 3103 3104 return 0; 3105 } 3106 3107 /* 3108 * Change the cursor shape. Call this with the cursor locked to avoid 3109 * flickering/tearing. 3110 */ 3111 static void 3112 radeonfb_cursor_shape(struct radeonfb_display *dp) 3113 { 3114 uint8_t and[512], xor[512]; 3115 int i, j, src, dst, pitch; 3116 const uint8_t *msk = dp->rd_cursor.rc_mask; 3117 const uint8_t *img = dp->rd_cursor.rc_image; 3118 3119 /* 3120 * Radeon cursor data interleaves one line of AND data followed 3121 * by a line of XOR data. (Each line corresponds to a whole hardware 3122 * pitch - i.e. 64 pixels or 8 bytes.) 3123 * 3124 * The cursor is displayed using the following table: 3125 * 3126 * AND XOR Result 3127 * ---------------------- 3128 * 0 0 Cursor color 0 3129 * 0 1 Cursor color 1 3130 * 1 0 Transparent 3131 * 1 1 Complement of background 3132 * 3133 * Our masks are therefore different from what we were passed. 3134 * Passed in, I'm assuming the data represents either color 0 or 1, 3135 * and a mask, so the passed in table looks like: 3136 * 3137 * IMG Mask Result 3138 * ----------------------- 3139 * 0 0 Transparent 3140 * 0 1 Cursor color 0 3141 * 1 0 Transparent 3142 * 1 1 Cursor color 1 3143 * 3144 * IF mask bit == 1, AND = 0, XOR = color. 3145 * IF mask bit == 0, AND = 1, XOR = 0. 3146 * 3147 * hence: AND = ~(mask); XOR = color & ~(mask); 3148 */ 3149 3150 pitch = ((dp->rd_cursor.rc_size.x + 7) / 8); 3151 3152 /* start by assuming all bits are transparent */ 3153 memset(and, 0xff, 512); 3154 memset(xor, 0x00, 512); 3155 3156 src = 0; 3157 dst = 0; 3158 for (i = 0; i < 64; i++) { 3159 for (j = 0; j < 64; j += 8) { 3160 if ((i < dp->rd_cursor.rc_size.y) && 3161 (j < dp->rd_cursor.rc_size.x)) { 3162 3163 /* take care to leave odd bits alone */ 3164 and[dst] &= ~(msk[src]); 3165 xor[dst] = img[src] & msk[src]; 3166 src++; 3167 } 3168 dst++; 3169 } 3170 } 3171 3172 /* copy the image into place */ 3173 for (i = 0; i < 64; i++) { 3174 memcpy((uint8_t *)dp->rd_curptr + (i * 16), 3175 &and[i * 8], 8); 3176 memcpy((uint8_t *)dp->rd_curptr + (i * 16) + 8, 3177 &xor[i * 8], 8); 3178 } 3179 } 3180 3181 static void 3182 radeonfb_cursor_position(struct radeonfb_display *dp) 3183 { 3184 struct radeonfb_softc *sc = dp->rd_softc; 3185 uint32_t offset, hvoff, hvpos; /* registers */ 3186 uint32_t coff; /* cursor offset */ 3187 int i, x, y, xoff, yoff, crtcoff; 3188 3189 /* 3190 * XXX: this also needs to handle pan/scan 3191 */ 3192 for (i = 0; i < dp->rd_ncrtcs; i++) { 3193 3194 struct radeonfb_crtc *rcp = &dp->rd_crtcs[i]; 3195 3196 if (rcp->rc_number) { 3197 offset = RADEON_CUR2_OFFSET; 3198 hvoff = RADEON_CUR2_HORZ_VERT_OFF; 3199 hvpos = RADEON_CUR2_HORZ_VERT_POSN; 3200 crtcoff = RADEON_CRTC2_OFFSET; 3201 } else { 3202 offset = RADEON_CUR_OFFSET; 3203 hvoff = RADEON_CUR_HORZ_VERT_OFF; 3204 hvpos = RADEON_CUR_HORZ_VERT_POSN; 3205 crtcoff = RADEON_CRTC_OFFSET; 3206 } 3207 3208 x = dp->rd_cursor.rc_pos.x; 3209 y = dp->rd_cursor.rc_pos.y; 3210 3211 while (y < rcp->rc_yoffset) { 3212 rcp->rc_yoffset -= RADEON_PANINCREMENT; 3213 } 3214 while (y >= (rcp->rc_yoffset + rcp->rc_videomode.vdisplay)) { 3215 rcp->rc_yoffset += RADEON_PANINCREMENT; 3216 } 3217 while (x < rcp->rc_xoffset) { 3218 rcp->rc_xoffset -= RADEON_PANINCREMENT; 3219 } 3220 while (x >= (rcp->rc_xoffset + rcp->rc_videomode.hdisplay)) { 3221 rcp->rc_xoffset += RADEON_PANINCREMENT; 3222 } 3223 3224 /* adjust for the cursor's hotspot */ 3225 x -= dp->rd_cursor.rc_hot.x; 3226 y -= dp->rd_cursor.rc_hot.y; 3227 xoff = yoff = 0; 3228 3229 if (x >= dp->rd_virtx) 3230 x = dp->rd_virtx - 1; 3231 if (y >= dp->rd_virty) 3232 y = dp->rd_virty - 1; 3233 3234 /* now adjust cursor so it is relative to viewport */ 3235 x -= rcp->rc_xoffset; 3236 y -= rcp->rc_yoffset; 3237 3238 /* 3239 * no need to check for fall off, because we should 3240 * never move off the screen entirely! 3241 */ 3242 coff = 0; 3243 if (x < 0) { 3244 xoff = -x; 3245 x = 0; 3246 } 3247 if (y < 0) { 3248 yoff = -y; 3249 y = 0; 3250 coff = (yoff * 2) * 8; 3251 } 3252 3253 /* pan the display */ 3254 PUT32(sc, crtcoff, (rcp->rc_yoffset * dp->rd_stride) + 3255 rcp->rc_xoffset); 3256 3257 PUT32(sc, offset, (dp->rd_curoff + coff) | RADEON_CUR_LOCK); 3258 PUT32(sc, hvoff, (xoff << 16) | (yoff) | RADEON_CUR_LOCK); 3259 /* NB: this unlocks the cursor */ 3260 PUT32(sc, hvpos, (x << 16) | y); 3261 } 3262 } 3263 3264 static void 3265 radeonfb_cursor_visible(struct radeonfb_display *dp) 3266 { 3267 int i; 3268 uint32_t gencntl, bit; 3269 3270 for (i = 0; i < dp->rd_ncrtcs; i++) { 3271 if (dp->rd_crtcs[i].rc_number) { 3272 gencntl = RADEON_CRTC2_GEN_CNTL; 3273 bit = RADEON_CRTC2_CUR_EN; 3274 } else { 3275 gencntl = RADEON_CRTC_GEN_CNTL; 3276 bit = RADEON_CRTC_CUR_EN; 3277 } 3278 3279 if (dp->rd_cursor.rc_visible) 3280 SET32(dp->rd_softc, gencntl, bit); 3281 else 3282 CLR32(dp->rd_softc, gencntl, bit); 3283 } 3284 } 3285 3286 static void 3287 radeonfb_cursor_cmap(struct radeonfb_display *dp) 3288 { 3289 int i; 3290 uint32_t c0reg, c1reg; 3291 struct radeonfb_softc *sc = dp->rd_softc; 3292 3293 for (i = 0; i < dp->rd_ncrtcs; i++) { 3294 if (dp->rd_crtcs[i].rc_number) { 3295 c0reg = RADEON_CUR2_CLR0; 3296 c1reg = RADEON_CUR2_CLR1; 3297 } else { 3298 c0reg = RADEON_CUR_CLR0; 3299 c1reg = RADEON_CUR_CLR1; 3300 } 3301 3302 PUT32(sc, c0reg, dp->rd_cursor.rc_cmap[0]); 3303 PUT32(sc, c1reg, dp->rd_cursor.rc_cmap[1]); 3304 } 3305 } 3306 3307 static void 3308 radeonfb_cursor_update(struct radeonfb_display *dp, unsigned which) 3309 { 3310 struct radeonfb_softc *sc; 3311 int i; 3312 3313 sc = dp->rd_softc; 3314 for (i = 0; i < dp->rd_ncrtcs; i++) { 3315 if (dp->rd_crtcs[i].rc_number) { 3316 SET32(sc, RADEON_CUR2_OFFSET, RADEON_CUR_LOCK); 3317 } else { 3318 SET32(sc, RADEON_CUR_OFFSET,RADEON_CUR_LOCK); 3319 } 3320 } 3321 3322 if (which & WSDISPLAY_CURSOR_DOCMAP) 3323 radeonfb_cursor_cmap(dp); 3324 3325 if (which & WSDISPLAY_CURSOR_DOSHAPE) 3326 radeonfb_cursor_shape(dp); 3327 3328 if (which & WSDISPLAY_CURSOR_DOCUR) 3329 radeonfb_cursor_visible(dp); 3330 3331 /* this one is unconditional, because it updates other stuff */ 3332 radeonfb_cursor_position(dp); 3333 } 3334 3335 static struct videomode * 3336 radeonfb_best_refresh(struct videomode *m1, struct videomode *m2) 3337 { 3338 int r1, r2; 3339 3340 /* otherwise pick the higher refresh rate */ 3341 r1 = DIVIDE(DIVIDE(m1->dot_clock, m1->htotal), m1->vtotal); 3342 r2 = DIVIDE(DIVIDE(m2->dot_clock, m2->htotal), m2->vtotal); 3343 3344 return (r1 < r2 ? m2 : m1); 3345 } 3346 3347 static const struct videomode * 3348 radeonfb_port_mode(struct radeonfb_softc *sc, struct radeonfb_port *rp, 3349 int x, int y) 3350 { 3351 struct edid_info *ep = &rp->rp_edid; 3352 struct videomode *vmp = NULL; 3353 int i; 3354 3355 if (!rp->rp_edid_valid) { 3356 /* fallback to safe mode */ 3357 return radeonfb_modelookup(sc->sc_defaultmode); 3358 } 3359 3360 /* always choose the preferred mode first! */ 3361 if (ep->edid_preferred_mode) { 3362 3363 /* XXX: add auto-stretching support for native mode */ 3364 3365 /* this may want panning to occur, btw */ 3366 if ((ep->edid_preferred_mode->hdisplay <= x) && 3367 (ep->edid_preferred_mode->vdisplay <= y)) 3368 return ep->edid_preferred_mode; 3369 } 3370 3371 for (i = 0; i < ep->edid_nmodes; i++) { 3372 /* 3373 * We elect to pick a resolution that is too large for 3374 * the monitor than one that is too small. This means 3375 * that we will prefer to pan rather than to try to 3376 * center a smaller display on a larger screen. In 3377 * practice, this shouldn't matter because if a 3378 * monitor can support a larger resolution, it can 3379 * probably also support the smaller. A specific 3380 * exception is fixed format panels, but hopefully 3381 * they are properly dealt with by the "autostretch" 3382 * logic above. 3383 */ 3384 if ((ep->edid_modes[i].hdisplay > x) || 3385 (ep->edid_modes[i].vdisplay > y)) { 3386 continue; 3387 } 3388 3389 /* 3390 * at this point, the display mode is no larger than 3391 * what we've requested. 3392 */ 3393 if (vmp == NULL) 3394 vmp = &ep->edid_modes[i]; 3395 3396 /* eliminate smaller modes */ 3397 if ((vmp->hdisplay >= ep->edid_modes[i].hdisplay) || 3398 (vmp->vdisplay >= ep->edid_modes[i].vdisplay)) 3399 continue; 3400 3401 if ((vmp->hdisplay < ep->edid_modes[i].hdisplay) || 3402 (vmp->vdisplay < ep->edid_modes[i].vdisplay)) { 3403 vmp = &ep->edid_modes[i]; 3404 continue; 3405 } 3406 3407 KASSERT(vmp->hdisplay == ep->edid_modes[i].hdisplay); 3408 KASSERT(vmp->vdisplay == ep->edid_modes[i].vdisplay); 3409 3410 vmp = radeonfb_best_refresh(vmp, &ep->edid_modes[i]); 3411 } 3412 3413 return (vmp ? vmp : radeonfb_modelookup(sc->sc_defaultmode)); 3414 } 3415 3416 static int 3417 radeonfb_hasres(struct videomode *list, int nlist, int x, int y) 3418 { 3419 int i; 3420 3421 for (i = 0; i < nlist; i++) { 3422 if ((x == list[i].hdisplay) && 3423 (y == list[i].vdisplay)) { 3424 return 1; 3425 } 3426 } 3427 return 0; 3428 } 3429 3430 static void 3431 radeonfb_pickres(struct radeonfb_display *dp, uint16_t *x, uint16_t *y, 3432 int pan) 3433 { 3434 struct radeonfb_port *rp; 3435 struct edid_info *ep; 3436 int i, j; 3437 3438 *x = 0; 3439 *y = 0; 3440 3441 if (pan) { 3442 for (i = 0; i < dp->rd_ncrtcs; i++) { 3443 rp = dp->rd_crtcs[i].rc_port; 3444 ep = &rp->rp_edid; 3445 if (!rp->rp_edid_valid) { 3446 /* monitor not present */ 3447 continue; 3448 } 3449 3450 /* 3451 * For now we are ignoring "conflict" that 3452 * could occur when mixing some modes like 3453 * 1280x1024 and 1400x800. It isn't clear 3454 * which is better, so the first one wins. 3455 */ 3456 for (j = 0; j < ep->edid_nmodes; j++) { 3457 /* 3458 * ignore resolutions that are too big for 3459 * the radeon 3460 */ 3461 if (ep->edid_modes[j].hdisplay > 3462 dp->rd_softc->sc_maxx) 3463 continue; 3464 if (ep->edid_modes[j].vdisplay > 3465 dp->rd_softc->sc_maxy) 3466 continue; 3467 3468 /* 3469 * pick largest resolution, the 3470 * smaller monitor will pan 3471 */ 3472 if ((ep->edid_modes[j].hdisplay >= *x) && 3473 (ep->edid_modes[j].vdisplay >= *y)) { 3474 *x = ep->edid_modes[j].hdisplay; 3475 *y = ep->edid_modes[j].vdisplay; 3476 } 3477 } 3478 } 3479 3480 } else { 3481 struct videomode modes[64]; 3482 int nmodes = 0; 3483 int valid = 0; 3484 3485 for (i = 0; i < dp->rd_ncrtcs; i++) { 3486 /* 3487 * pick the largest resolution in common. 3488 */ 3489 rp = dp->rd_crtcs[i].rc_port; 3490 ep = &rp->rp_edid; 3491 3492 if (!rp->rp_edid_valid) 3493 continue; 3494 3495 if (!valid) { 3496 /* 3497 * Pick the preferred mode for this port 3498 * if available. 3499 */ 3500 if (ep->edid_preferred_mode) { 3501 struct videomode *vmp = 3502 ep->edid_preferred_mode; 3503 3504 if ((vmp->hdisplay <= 3505 dp->rd_softc->sc_maxx) && 3506 (vmp->vdisplay <= 3507 dp->rd_softc->sc_maxy)) 3508 modes[nmodes++] = *vmp; 3509 } else { 3510 3511 /* initialize starting list */ 3512 for (j = 0; j < ep->edid_nmodes; j++) { 3513 /* 3514 * ignore resolutions that are 3515 * too big for the radeon 3516 */ 3517 if (ep->edid_modes[j].hdisplay > 3518 dp->rd_softc->sc_maxx) 3519 continue; 3520 if (ep->edid_modes[j].vdisplay > 3521 dp->rd_softc->sc_maxy) 3522 continue; 3523 3524 modes[nmodes] = 3525 ep->edid_modes[j]; 3526 nmodes++; 3527 } 3528 } 3529 valid = 1; 3530 } else { 3531 /* merge into preexisting list */ 3532 for (j = 0; j < nmodes; j++) { 3533 if (!radeonfb_hasres(ep->edid_modes, 3534 ep->edid_nmodes, 3535 modes[j].hdisplay, 3536 modes[j].vdisplay)) { 3537 modes[j] = modes[nmodes]; 3538 j--; 3539 nmodes--; 3540 } 3541 } 3542 } 3543 } 3544 3545 /* now we have to pick from the merged list */ 3546 for (i = 0; i < nmodes; i++) { 3547 if ((modes[i].hdisplay >= *x) && 3548 (modes[i].vdisplay >= *y)) { 3549 *x = modes[i].hdisplay; 3550 *y = modes[i].vdisplay; 3551 } 3552 } 3553 } 3554 3555 if ((*x == 0) || (*y == 0)) { 3556 /* fallback to safe mode */ 3557 *x = 640; 3558 *y = 480; 3559 } 3560 } 3561 3562 /* 3563 * backlight levels are linear on: 3564 * - RV200, RV250, RV280, RV350 3565 * - but NOT on PowerBook4,3 6,3 6,5 3566 * according to Linux' radeonfb 3567 */ 3568 3569 /* Get the current backlight level for the display. */ 3570 3571 static int 3572 radeonfb_get_backlight(struct radeonfb_display *dp) 3573 { 3574 int s; 3575 uint32_t level; 3576 3577 s = spltty(); 3578 3579 level = radeonfb_get32(dp->rd_softc, RADEON_LVDS_GEN_CNTL); 3580 level &= RADEON_LVDS_BL_MOD_LEV_MASK; 3581 level >>= RADEON_LVDS_BL_MOD_LEV_SHIFT; 3582 3583 /* 3584 * On some chips, we should negate the backlight level. 3585 * XXX Find out on which chips. 3586 */ 3587 if (dp->rd_softc->sc_flags & RFB_INV_BLIGHT) 3588 level = RADEONFB_BACKLIGHT_MAX - level; 3589 3590 splx(s); 3591 3592 return level; 3593 } 3594 3595 /* Set the backlight to the given level for the display. */ 3596 static void 3597 radeonfb_switch_backlight(struct radeonfb_display *dp, int on) 3598 { 3599 if (dp->rd_bl_on == on) 3600 return; 3601 dp->rd_bl_on = on; 3602 radeonfb_set_backlight(dp, dp->rd_bl_level); 3603 } 3604 3605 static int 3606 radeonfb_set_backlight(struct radeonfb_display *dp, int level) 3607 { 3608 struct radeonfb_softc *sc; 3609 int rlevel, s; 3610 uint32_t lvds; 3611 3612 s = spltty(); 3613 3614 dp->rd_bl_level = level; 3615 if (dp->rd_bl_on == 0) 3616 level = 0; 3617 3618 if (level < 0) 3619 level = 0; 3620 else if (level >= RADEONFB_BACKLIGHT_MAX) 3621 level = RADEONFB_BACKLIGHT_MAX; 3622 3623 sc = dp->rd_softc; 3624 3625 /* On some chips, we should negate the backlight level. */ 3626 if (dp->rd_softc->sc_flags & RFB_INV_BLIGHT) { 3627 rlevel = RADEONFB_BACKLIGHT_MAX - level; 3628 } else 3629 rlevel = level; 3630 3631 callout_stop(&dp->rd_bl_lvds_co); 3632 radeonfb_engine_idle(sc); 3633 3634 /* 3635 * Turn off the display if the backlight is set to 0, since the 3636 * display is useless without backlight anyway. 3637 */ 3638 if (level == 0) 3639 radeonfb_blank(dp, 1); 3640 else if (radeonfb_get_backlight(dp) == 0) 3641 radeonfb_blank(dp, 0); 3642 3643 lvds = radeonfb_get32(sc, RADEON_LVDS_GEN_CNTL); 3644 lvds &= ~RADEON_LVDS_DISPLAY_DIS; 3645 if (!(lvds & RADEON_LVDS_BLON) || !(lvds & RADEON_LVDS_ON)) { 3646 lvds |= dp->rd_bl_lvds_val & RADEON_LVDS_DIGON; 3647 lvds |= RADEON_LVDS_BLON | RADEON_LVDS_EN; 3648 radeonfb_put32(sc, RADEON_LVDS_GEN_CNTL, lvds); 3649 lvds &= ~RADEON_LVDS_BL_MOD_LEV_MASK; 3650 lvds |= rlevel << RADEON_LVDS_BL_MOD_LEV_SHIFT; 3651 lvds |= RADEON_LVDS_ON; 3652 lvds |= dp->rd_bl_lvds_val & RADEON_LVDS_BL_MOD_EN; 3653 } else { 3654 lvds &= ~RADEON_LVDS_BL_MOD_LEV_MASK; 3655 lvds |= rlevel << RADEON_LVDS_BL_MOD_LEV_SHIFT; 3656 radeonfb_put32(sc, RADEON_LVDS_GEN_CNTL, lvds); 3657 } 3658 3659 dp->rd_bl_lvds_val &= ~RADEON_LVDS_STATE_MASK; 3660 dp->rd_bl_lvds_val |= lvds & RADEON_LVDS_STATE_MASK; 3661 /* XXX What is the correct delay? */ 3662 callout_schedule(&dp->rd_bl_lvds_co, 200 * hz); 3663 3664 splx(s); 3665 3666 return 0; 3667 } 3668 3669 /* 3670 * Callout function for delayed operations on the LVDS_GEN_CNTL register. 3671 * Set the delayed bits in the register, and clear the stored delayed 3672 * value. 3673 */ 3674 3675 static void radeonfb_lvds_callout(void *arg) 3676 { 3677 struct radeonfb_display *dp = arg; 3678 int s; 3679 3680 s = splhigh(); 3681 3682 radeonfb_mask32(dp->rd_softc, RADEON_LVDS_GEN_CNTL, ~0, 3683 dp->rd_bl_lvds_val); 3684 dp->rd_bl_lvds_val = 0; 3685 3686 splx(s); 3687 } 3688 3689 static void 3690 radeonfb_brightness_up(device_t dev) 3691 { 3692 struct radeonfb_softc *sc = device_private(dev); 3693 struct radeonfb_display *dp = &sc->sc_displays[0]; 3694 int level; 3695 3696 /* we assume the main display is the first one - need a better way */ 3697 if (sc->sc_ndisplays < 1) return; 3698 /* make sure pushing the hotkeys always has an effect */ 3699 dp->rd_bl_on = 1; 3700 level = dp->rd_bl_level; 3701 level = min(RADEONFB_BACKLIGHT_MAX, level + 5); 3702 radeonfb_set_backlight(dp, level); 3703 } 3704 3705 static void 3706 radeonfb_brightness_down(device_t dev) 3707 { 3708 struct radeonfb_softc *sc = device_private(dev); 3709 struct radeonfb_display *dp = &sc->sc_displays[0]; 3710 int level; 3711 3712 /* we assume the main display is the first one - need a better way */ 3713 if (sc->sc_ndisplays < 1) return; 3714 /* make sure pushing the hotkeys always has an effect */ 3715 dp->rd_bl_on = 1; 3716 level = dp->rd_bl_level; 3717 level = max(0, level - 5); 3718 radeonfb_set_backlight(dp, level); 3719 } 3720
Indexes created Fri Oct 17 17:09:57 GMT 2025