radeonfb.c revision 1.54
1 /* $NetBSD: radeonfb.c,v 1.54 2012/02/16 17:33:28 macallan Exp $ */ 2 3 /*- 4 * Copyright (c) 2006 Itronix Inc. 5 * All rights reserved. 6 * 7 * Written by Garrett D'Amore for Itronix Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. The name of Itronix Inc. may not be used to endorse 18 * or promote products derived from this software without specific 19 * prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY ITRONIX INC. ``AS IS'' AND ANY EXPRESS 22 * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 23 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL ITRONIX INC. BE LIABLE FOR ANY 25 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE 27 * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 29 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 30 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 31 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * ATI Technologies Inc. ("ATI") has not assisted in the creation of, and 36 * does not endorse, this software. ATI will not be responsible or liable 37 * for any actual or alleged damage or loss caused by or in connection with 38 * the use of or reliance on this software. 39 */ 40 41 /* 42 * Portions of this code were taken from XFree86's Radeon driver, which bears 43 * this notice: 44 * 45 * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and 46 * VA Linux Systems Inc., Fremont, California. 47 * 48 * All Rights Reserved. 49 * 50 * Permission is hereby granted, free of charge, to any person obtaining 51 * a copy of this software and associated documentation files (the 52 * "Software"), to deal in the Software without restriction, including 53 * without limitation on the rights to use, copy, modify, merge, 54 * publish, distribute, sublicense, and/or sell copies of the Software, 55 * and to permit persons to whom the Software is furnished to do so, 56 * subject to the following conditions: 57 * 58 * The above copyright notice and this permission notice (including the 59 * next paragraph) shall be included in all copies or substantial 60 * portions of the Software. 61 * 62 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 63 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 64 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 65 * NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR 66 * THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 67 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 68 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 69 * DEALINGS IN THE SOFTWARE. 70 */ 71 72 #include <sys/cdefs.h> 73 __KERNEL_RCSID(0, "$NetBSD: radeonfb.c,v 1.54 2012/02/16 17:33:28 macallan Exp $"); 74 75 #include <sys/param.h> 76 #include <sys/systm.h> 77 #include <sys/device.h> 78 #include <sys/malloc.h> 79 #include <sys/bus.h> 80 #include <sys/kernel.h> 81 #include <sys/lwp.h> 82 #include <sys/kauth.h> 83 84 #include <dev/wscons/wsdisplayvar.h> 85 #include <dev/wscons/wsconsio.h> 86 #include <dev/wsfont/wsfont.h> 87 #include <dev/rasops/rasops.h> 88 #include <dev/videomode/videomode.h> 89 #include <dev/videomode/edidvar.h> 90 #include <dev/wscons/wsdisplay_vconsvar.h> 91 #include <dev/pci/wsdisplay_pci.h> 92 #include <dev/wscons/wsdisplay_glyphcachevar.h> 93 94 #include <dev/pci/pcidevs.h> 95 #include <dev/pci/pcireg.h> 96 #include <dev/pci/pcivar.h> 97 #include <dev/pci/pciio.h> 98 #include <dev/pci/radeonfbreg.h> 99 #include <dev/pci/radeonfbvar.h> 100 #include "opt_radeonfb.h" 101 #include "opt_vcons.h" 102 103 #ifdef RADEONFB_DEPTH_32 104 #define RADEONFB_DEFAULT_DEPTH 32 105 #else 106 #define RADEONFB_DEFAULT_DEPTH 8 107 #endif 108 109 static int radeonfb_match(device_t, cfdata_t, void *); 110 static void radeonfb_attach(device_t, device_t, void *); 111 static int radeonfb_ioctl(void *, void *, unsigned long, void *, int, 112 struct lwp *); 113 static paddr_t radeonfb_mmap(void *, void *, off_t, int); 114 static int radeonfb_scratch_test(struct radeonfb_softc *, int, uint32_t); 115 static void radeonfb_loadbios(struct radeonfb_softc *, 116 const struct pci_attach_args *); 117 118 static uintmax_t radeonfb_getprop_num(struct radeonfb_softc *, const char *, 119 uintmax_t); 120 static int radeonfb_getclocks(struct radeonfb_softc *); 121 static int radeonfb_gettmds(struct radeonfb_softc *); 122 static int radeonfb_calc_dividers(struct radeonfb_softc *, uint32_t, 123 uint32_t *, uint32_t *); 124 static int radeonfb_getconnectors(struct radeonfb_softc *); 125 static const struct videomode *radeonfb_modelookup(const char *); 126 static void radeonfb_init_screen(void *, struct vcons_screen *, int, long *); 127 static void radeonfb_pllwriteupdate(struct radeonfb_softc *, int); 128 static void radeonfb_pllwaitatomicread(struct radeonfb_softc *, int); 129 static void radeonfb_program_vclk(struct radeonfb_softc *, int, int); 130 static void radeonfb_modeswitch(struct radeonfb_display *); 131 static void radeonfb_setcrtc(struct radeonfb_display *, int); 132 static void radeonfb_init_misc(struct radeonfb_softc *); 133 static void radeonfb_set_fbloc(struct radeonfb_softc *); 134 static void radeonfb_init_palette(struct radeonfb_softc *, int); 135 static void radeonfb_r300cg_workaround(struct radeonfb_softc *); 136 137 static int radeonfb_isblank(struct radeonfb_display *); 138 static void radeonfb_blank(struct radeonfb_display *, int); 139 static int radeonfb_set_cursor(struct radeonfb_display *, 140 struct wsdisplay_cursor *); 141 static int radeonfb_set_curpos(struct radeonfb_display *, 142 struct wsdisplay_curpos *); 143 144 /* acceleration support */ 145 static void radeonfb_rectfill(struct radeonfb_display *, int dstx, int dsty, 146 int width, int height, uint32_t color); 147 static void radeonfb_bitblt(void *, int srcx, int srcy, 148 int dstx, int dsty, int width, int height, int rop); 149 150 /* hw cursor support */ 151 static void radeonfb_cursor_cmap(struct radeonfb_display *); 152 static void radeonfb_cursor_shape(struct radeonfb_display *); 153 static void radeonfb_cursor_position(struct radeonfb_display *); 154 static void radeonfb_cursor_visible(struct radeonfb_display *); 155 static void radeonfb_cursor_update(struct radeonfb_display *, unsigned); 156 157 static void radeonfb_wait_fifo(struct radeonfb_softc *, int); 158 static void radeonfb_engine_idle(struct radeonfb_softc *); 159 static void radeonfb_engine_flush(struct radeonfb_softc *); 160 static void radeonfb_engine_reset(struct radeonfb_softc *); 161 static void radeonfb_engine_init(struct radeonfb_display *); 162 static inline void radeonfb_unclip(struct radeonfb_softc *); 163 164 static void radeonfb_eraserows(void *, int, int, long); 165 static void radeonfb_erasecols(void *, int, int, int, long); 166 static void radeonfb_copyrows(void *, int, int, int); 167 static void radeonfb_copycols(void *, int, int, int, int); 168 static void radeonfb_cursor(void *, int, int, int); 169 static void radeonfb_putchar(void *, int, int, unsigned, long); 170 static void radeonfb_putchar_aa32(void *, int, int, unsigned, long); 171 static void radeonfb_putchar_wrapper(void *, int, int, unsigned, long); 172 173 static int radeonfb_get_backlight(struct radeonfb_display *); 174 static int radeonfb_set_backlight(struct radeonfb_display *, int); 175 static void radeonfb_lvds_callout(void *); 176 177 static void radeonfb_brightness_up(device_t); 178 static void radeonfb_brightness_down(device_t); 179 180 static struct videomode *radeonfb_best_refresh(struct videomode *, 181 struct videomode *); 182 static void radeonfb_pickres(struct radeonfb_display *, uint16_t *, 183 uint16_t *, int); 184 static const struct videomode *radeonfb_port_mode(struct radeonfb_softc *, 185 struct radeonfb_port *, int, int); 186 187 static int radeonfb_drm_print(void *, const char *); 188 189 #ifdef RADEONFB_DEBUG 190 int radeon_debug = 1; 191 #define DPRINTF(x) \ 192 if (radeon_debug) printf x 193 #define PRINTREG(r) DPRINTF((#r " = %08x\n", GET32(sc, r))) 194 #define PRINTPLL(r) DPRINTF((#r " = %08x\n", GETPLL(sc, r))) 195 #else 196 #define DPRINTF(x) 197 #define PRINTREG(r) 198 #define PRINTPLL(r) 199 #endif 200 201 #define ROUNDUP(x,y) (((x) + ((y) - 1)) & ~((y) - 1)) 202 203 #ifndef RADEON_DEFAULT_MODE 204 /* any reasonably modern display should handle this */ 205 #define RADEON_DEFAULT_MODE "1024x768x60" 206 #endif 207 208 extern const u_char rasops_cmap[768]; 209 210 const char *radeonfb_default_mode = RADEON_DEFAULT_MODE; 211 212 static struct { 213 int size; /* minimum memory size (MB) */ 214 int maxx; /* maximum x dimension */ 215 int maxy; /* maximum y dimension */ 216 int maxbpp; /* maximum bpp */ 217 int maxdisp; /* maximum logical display count */ 218 } radeonfb_limits[] = { 219 { 32, 2048, 1536, 32, 2 }, 220 { 16, 1600, 1200, 32, 2 }, 221 { 8, 1600, 1200, 32, 1 }, 222 { 0, 0, 0, 0, 0 }, 223 }; 224 225 static struct wsscreen_descr radeonfb_stdscreen = { 226 "fb", /* name */ 227 0, 0, /* ncols, nrows */ 228 NULL, /* textops */ 229 8, 16, /* fontwidth, fontheight */ 230 WSSCREEN_WSCOLORS, /* capabilities */ 231 0, /* modecookie */ 232 }; 233 234 struct wsdisplay_accessops radeonfb_accessops = { 235 radeonfb_ioctl, 236 radeonfb_mmap, 237 NULL, /* vcons_alloc_screen */ 238 NULL, /* vcons_free_screen */ 239 NULL, /* vcons_show_screen */ 240 NULL, /* load_font */ 241 NULL, /* pollc */ 242 NULL, /* scroll */ 243 }; 244 245 static struct { 246 uint16_t devid; 247 uint16_t family; 248 uint16_t flags; 249 } radeonfb_devices[] = 250 { 251 /* R100 family */ 252 { PCI_PRODUCT_ATI_RADEON_R100_QD, RADEON_R100, 0 }, 253 { PCI_PRODUCT_ATI_RADEON_R100_QE, RADEON_R100, 0 }, 254 { PCI_PRODUCT_ATI_RADEON_R100_QF, RADEON_R100, 0 }, 255 { PCI_PRODUCT_ATI_RADEON_R100_QG, RADEON_R100, 0 }, 256 257 /* RV100 family */ 258 { PCI_PRODUCT_ATI_RADEON_RV100_LY, RADEON_RV100, RFB_MOB }, 259 { PCI_PRODUCT_ATI_RADEON_RV100_LZ, RADEON_RV100, RFB_MOB }, 260 { PCI_PRODUCT_ATI_RADEON_RV100_QY, RADEON_RV100, 0 }, 261 { PCI_PRODUCT_ATI_RADEON_RV100_QZ, RADEON_RV100, 0 }, 262 263 /* RS100 family */ 264 { PCI_PRODUCT_ATI_RADEON_RS100_4136, RADEON_RS100, 0 }, 265 { PCI_PRODUCT_ATI_RADEON_RS100_4336, RADEON_RS100, RFB_MOB }, 266 267 /* RS200/RS250 family */ 268 { PCI_PRODUCT_ATI_RADEON_RS200_4337, RADEON_RS200, RFB_MOB }, 269 { PCI_PRODUCT_ATI_RADEON_RS200_A7, RADEON_RS200, 0 }, 270 { PCI_PRODUCT_ATI_RADEON_RS250_B7, RADEON_RS200, RFB_MOB }, 271 { PCI_PRODUCT_ATI_RADEON_RS250_D7, RADEON_RS200, 0 }, 272 273 /* R200 family */ 274 /* add more R200 products? , 5148 */ 275 { PCI_PRODUCT_ATI_RADEON_R200_BB, RADEON_R200, 0 }, 276 { PCI_PRODUCT_ATI_RADEON_R200_BC, RADEON_R200, 0 }, 277 { PCI_PRODUCT_ATI_RADEON_R200_QH, RADEON_R200, 0 }, 278 { PCI_PRODUCT_ATI_RADEON_R200_QL, RADEON_R200, 0 }, 279 { PCI_PRODUCT_ATI_RADEON_R200_QM, RADEON_R200, 0 }, 280 281 /* RV200 family */ 282 { PCI_PRODUCT_ATI_RADEON_RV200_LW, RADEON_RV200, RFB_MOB }, 283 { PCI_PRODUCT_ATI_RADEON_RV200_LX, RADEON_RV200, RFB_MOB }, 284 { PCI_PRODUCT_ATI_RADEON_RV200_QW, RADEON_RV200, 0 }, 285 { PCI_PRODUCT_ATI_RADEON_RV200_QX, RADEON_RV200, 0 }, 286 287 /* RV250 family */ 288 { PCI_PRODUCT_ATI_RADEON_RV250_4966, RADEON_RV250, 0 }, 289 { PCI_PRODUCT_ATI_RADEON_RV250_4967, RADEON_RV250, 0 }, 290 { PCI_PRODUCT_ATI_RADEON_RV250_4C64, RADEON_RV250, RFB_MOB }, 291 { PCI_PRODUCT_ATI_RADEON_RV250_4C66, RADEON_RV250, RFB_MOB }, 292 { PCI_PRODUCT_ATI_RADEON_RV250_4C67, RADEON_RV250, RFB_MOB }, 293 294 /* RS300 family */ 295 { PCI_PRODUCT_ATI_RADEON_RS300_X5, RADEON_RS300, 0 }, 296 { PCI_PRODUCT_ATI_RADEON_RS300_X4, RADEON_RS300, 0 }, 297 { PCI_PRODUCT_ATI_RADEON_RS300_7834, RADEON_RS300, 0 }, 298 { PCI_PRODUCT_ATI_RADEON_RS300_7835, RADEON_RS300, RFB_MOB }, 299 300 /* RV280 family */ 301 { PCI_PRODUCT_ATI_RADEON_RV280_5960, RADEON_RV280, 0 }, 302 { PCI_PRODUCT_ATI_RADEON_RV280_5961, RADEON_RV280, 0 }, 303 { PCI_PRODUCT_ATI_RADEON_RV280_5962, RADEON_RV280, 0 }, 304 { PCI_PRODUCT_ATI_RADEON_RV280_5963, RADEON_RV280, 0 }, 305 { PCI_PRODUCT_ATI_RADEON_RV280_5964, RADEON_RV280, 0 }, 306 { PCI_PRODUCT_ATI_RADEON_RV280_5C61, RADEON_RV280, RFB_MOB }, 307 { PCI_PRODUCT_ATI_RADEON_RV280_5C63, RADEON_RV280, RFB_MOB }, 308 309 /* R300 family */ 310 { PCI_PRODUCT_ATI_RADEON_R300_AD, RADEON_R300, 0 }, 311 { PCI_PRODUCT_ATI_RADEON_R300_AE, RADEON_R300, 0 }, 312 { PCI_PRODUCT_ATI_RADEON_R300_AF, RADEON_R300, 0 }, 313 { PCI_PRODUCT_ATI_RADEON_R300_AG, RADEON_R300, 0 }, 314 { PCI_PRODUCT_ATI_RADEON_R300_ND, RADEON_R300, 0 }, 315 { PCI_PRODUCT_ATI_RADEON_R300_NE, RADEON_R300, 0 }, 316 { PCI_PRODUCT_ATI_RADEON_R300_NF, RADEON_R300, 0 }, 317 { PCI_PRODUCT_ATI_RADEON_R300_NG, RADEON_R300, 0 }, 318 319 /* RV350/RV360 family */ 320 { PCI_PRODUCT_ATI_RADEON_RV350_AP, RADEON_RV350, 0 }, 321 { PCI_PRODUCT_ATI_RADEON_RV350_AQ, RADEON_RV350, 0 }, 322 { PCI_PRODUCT_ATI_RADEON_RV360_AR, RADEON_RV350, 0 }, 323 { PCI_PRODUCT_ATI_RADEON_RV350_AS, RADEON_RV350, 0 }, 324 { PCI_PRODUCT_ATI_RADEON_RV350_AT, RADEON_RV350, 0 }, 325 { PCI_PRODUCT_ATI_RADEON_RV350_AV, RADEON_RV350, 0 }, 326 { PCI_PRODUCT_ATI_RADEON_RV350_NP, RADEON_RV350, RFB_MOB }, 327 { PCI_PRODUCT_ATI_RADEON_RV350_NQ, RADEON_RV350, RFB_MOB }, 328 { PCI_PRODUCT_ATI_RADEON_RV350_NR, RADEON_RV350, RFB_MOB }, 329 { PCI_PRODUCT_ATI_RADEON_RV350_NS, RADEON_RV350, RFB_MOB }, 330 { PCI_PRODUCT_ATI_RADEON_RV350_NT, RADEON_RV350, RFB_MOB }, 331 { PCI_PRODUCT_ATI_RADEON_RV350_NV, RADEON_RV350, RFB_MOB }, 332 333 /* R350/R360 family */ 334 { PCI_PRODUCT_ATI_RADEON_R350_AH, RADEON_R350, 0 }, 335 { PCI_PRODUCT_ATI_RADEON_R350_AI, RADEON_R350, 0 }, 336 { PCI_PRODUCT_ATI_RADEON_R350_AJ, RADEON_R350, 0 }, 337 { PCI_PRODUCT_ATI_RADEON_R350_AK, RADEON_R350, 0 }, 338 { PCI_PRODUCT_ATI_RADEON_R350_NH, RADEON_R350, 0 }, 339 { PCI_PRODUCT_ATI_RADEON_R350_NI, RADEON_R350, 0 }, 340 { PCI_PRODUCT_ATI_RADEON_R350_NK, RADEON_R350, 0 }, 341 { PCI_PRODUCT_ATI_RADEON_R360_NJ, RADEON_R350, 0 }, 342 343 /* RV380/RV370 family */ 344 { PCI_PRODUCT_ATI_RADEON_RV380_3150, RADEON_RV380, RFB_MOB }, 345 { PCI_PRODUCT_ATI_RADEON_RV380_3154, RADEON_RV380, RFB_MOB }, 346 { PCI_PRODUCT_ATI_RADEON_RV380_3E50, RADEON_RV380, 0 }, 347 { PCI_PRODUCT_ATI_RADEON_RV380_3E54, RADEON_RV380, 0 }, 348 { PCI_PRODUCT_ATI_RADEON_RV370_5460, RADEON_RV380, RFB_MOB }, 349 { PCI_PRODUCT_ATI_RADEON_RV370_5464, RADEON_RV380, RFB_MOB }, 350 { PCI_PRODUCT_ATI_RADEON_RV370_5B60, RADEON_RV380, 0 }, 351 { PCI_PRODUCT_ATI_RADEON_RV370_5B64, RADEON_RV380, 0 }, 352 { PCI_PRODUCT_ATI_RADEON_RV370_5B65, RADEON_RV380, 0 }, 353 354 /* R420/R423 family */ 355 { PCI_PRODUCT_ATI_RADEON_R420_JH, RADEON_R420, 0 }, 356 { PCI_PRODUCT_ATI_RADEON_R420_JI, RADEON_R420, 0 }, 357 { PCI_PRODUCT_ATI_RADEON_R420_JJ, RADEON_R420, 0 }, 358 { PCI_PRODUCT_ATI_RADEON_R420_JK, RADEON_R420, 0 }, 359 { PCI_PRODUCT_ATI_RADEON_R420_JL, RADEON_R420, 0 }, 360 { PCI_PRODUCT_ATI_RADEON_R420_JM, RADEON_R420, 0 }, 361 { PCI_PRODUCT_ATI_RADEON_R420_JN, RADEON_R420, RFB_MOB }, 362 { PCI_PRODUCT_ATI_RADEON_R420_JP, RADEON_R420, 0 }, 363 { PCI_PRODUCT_ATI_RADEON_R423_UH, RADEON_R420, 0 }, 364 { PCI_PRODUCT_ATI_RADEON_R423_UI, RADEON_R420, 0 }, 365 { PCI_PRODUCT_ATI_RADEON_R423_UJ, RADEON_R420, 0 }, 366 { PCI_PRODUCT_ATI_RADEON_R423_UK, RADEON_R420, 0 }, 367 { PCI_PRODUCT_ATI_RADEON_R423_UQ, RADEON_R420, 0 }, 368 { PCI_PRODUCT_ATI_RADEON_R423_UR, RADEON_R420, 0 }, 369 { PCI_PRODUCT_ATI_RADEON_R423_UT, RADEON_R420, 0 }, 370 { PCI_PRODUCT_ATI_RADEON_R423_5D57, RADEON_R420, 0 }, 371 { PCI_PRODUCT_ATI_RADEON_R430_554F, RADEON_R420, 0 }, 372 373 { 0, 0, 0 } 374 }; 375 376 static struct { 377 int divider; 378 int mask; 379 } radeonfb_dividers[] = { 380 { 1, 0 }, 381 { 2, 1 }, 382 { 3, 4 }, 383 { 4, 2 }, 384 { 6, 6 }, 385 { 8, 3 }, 386 { 12, 7 }, 387 { 0, 0 } 388 }; 389 390 /* 391 * This table taken from X11. 392 */ 393 static const struct { 394 int family; 395 struct radeon_tmds_pll plls[4]; 396 } radeonfb_tmds_pll[] = { 397 { RADEON_R100, {{12000, 0xa1b}, {-1, 0xa3f}}}, 398 { RADEON_RV100, {{12000, 0xa1b}, {-1, 0xa3f}}}, 399 { RADEON_RS100, {{0, 0}}}, 400 { RADEON_RV200, {{15000, 0xa1b}, {-1, 0xa3f}}}, 401 { RADEON_RS200, {{15000, 0xa1b}, {-1, 0xa3f}}}, 402 { RADEON_R200, {{15000, 0xa1b}, {-1, 0xa3f}}}, 403 { RADEON_RV250, {{15500, 0x81b}, {-1, 0x83f}}}, 404 { RADEON_RS300, {{0, 0}}}, 405 { RADEON_RV280, {{13000, 0x400f4}, {15000, 0x400f7}}}, 406 { RADEON_R300, {{-1, 0xb01cb}}}, 407 { RADEON_R350, {{-1, 0xb01cb}}}, 408 { RADEON_RV350, {{15000, 0xb0155}, {-1, 0xb01cb}}}, 409 { RADEON_RV380, {{15000, 0xb0155}, {-1, 0xb01cb}}}, 410 { RADEON_R420, {{-1, 0xb01cb}}}, 411 }; 412 413 #define RADEONFB_BACKLIGHT_MAX 255 /* Maximum backlight level. */ 414 415 416 CFATTACH_DECL_NEW(radeonfb, sizeof (struct radeonfb_softc), 417 radeonfb_match, radeonfb_attach, NULL, NULL); 418 419 static int 420 radeonfb_match(device_t parent, cfdata_t match, void *aux) 421 { 422 const struct pci_attach_args *pa = aux; 423 int i; 424 425 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_ATI) 426 return 0; 427 428 for (i = 0; radeonfb_devices[i].devid; i++) { 429 if (PCI_PRODUCT(pa->pa_id) == radeonfb_devices[i].devid) 430 return 100; /* high to defeat VGA/VESA */ 431 } 432 433 return 0; 434 } 435 436 static void 437 radeonfb_attach(device_t parent, device_t dev, void *aux) 438 { 439 struct radeonfb_softc *sc = device_private(dev); 440 const struct pci_attach_args *pa = aux; 441 const char *mptr; 442 bus_size_t bsz; 443 pcireg_t screg; 444 int i, j, fg, bg, ul, flags; 445 uint32_t v; 446 447 sc->sc_dev = dev; 448 sc->sc_id = pa->pa_id; 449 for (i = 0; radeonfb_devices[i].devid; i++) { 450 if (PCI_PRODUCT(sc->sc_id) == radeonfb_devices[i].devid) 451 break; 452 } 453 454 pci_aprint_devinfo(pa, NULL); 455 456 DPRINTF((prop_dictionary_externalize(device_properties(dev)))); 457 458 KASSERT(radeonfb_devices[i].devid != 0); 459 sc->sc_pt = pa->pa_tag; 460 sc->sc_iot = pa->pa_iot; 461 sc->sc_pc = pa->pa_pc; 462 sc->sc_family = radeonfb_devices[i].family; 463 sc->sc_flags = radeonfb_devices[i].flags; 464 465 /* enable memory and IO access */ 466 screg = pci_conf_read(sc->sc_pc, sc->sc_pt, PCI_COMMAND_STATUS_REG); 467 screg |= PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE; 468 pci_conf_write(sc->sc_pc, sc->sc_pt, PCI_COMMAND_STATUS_REG, screg); 469 470 /* 471 * Some flags are general to entire chip families, and rather 472 * than clutter up the table with them, we go ahead and set 473 * them here. 474 */ 475 switch (sc->sc_family) { 476 case RADEON_RS100: 477 case RADEON_RS200: 478 sc->sc_flags |= RFB_IGP | RFB_RV100; 479 break; 480 481 case RADEON_RV100: 482 case RADEON_RV200: 483 case RADEON_RV250: 484 case RADEON_RV280: 485 sc->sc_flags |= RFB_RV100; 486 break; 487 488 case RADEON_RS300: 489 sc->sc_flags |= RFB_SDAC | RFB_IGP | RFB_RV100; 490 break; 491 492 case RADEON_R300: 493 case RADEON_RV350: 494 case RADEON_R350: 495 case RADEON_RV380: 496 case RADEON_R420: 497 /* newer chips */ 498 sc->sc_flags |= RFB_R300; 499 break; 500 501 case RADEON_R100: 502 sc->sc_flags |= RFB_NCRTC2; 503 break; 504 } 505 506 if ((sc->sc_family == RADEON_RV200) || 507 (sc->sc_family == RADEON_RV250) || 508 (sc->sc_family == RADEON_RV280) || 509 (sc->sc_family == RADEON_RV350)) { 510 bool inverted = 0; 511 /* backlight level is linear */ 512 DPRINTF(("found RV* chip, backlight is supposedly linear\n")); 513 prop_dictionary_get_bool(device_properties(sc->sc_dev), 514 "backlight_level_reverted", &inverted); 515 if (inverted) { 516 DPRINTF(("nope, it's inverted\n")); 517 sc->sc_flags |= RFB_INV_BLIGHT; 518 } 519 } else 520 sc->sc_flags |= RFB_INV_BLIGHT; 521 522 /* 523 * XXX: to support true multihead, this must change. 524 */ 525 sc->sc_ndisplays = 1; 526 527 /* XXX: */ 528 if (!HAS_CRTC2(sc)) { 529 sc->sc_ndisplays = 1; 530 } 531 532 if (pci_mapreg_map(pa, RADEON_MAPREG_MMIO, PCI_MAPREG_TYPE_MEM, 0, 533 &sc->sc_regt, &sc->sc_regh, &sc->sc_regaddr, 534 &sc->sc_regsz) != 0) { 535 aprint_error("%s: unable to map registers!\n", XNAME(sc)); 536 goto error; 537 } 538 539 if (pci_mapreg_info(sc->sc_pc, sc->sc_pt, PCI_MAPREG_ROM, 540 PCI_MAPREG_TYPE_ROM, &sc->sc_romaddr, &sc->sc_romsz, &flags) != 0) 541 { 542 aprint_error("%s: unable to find ROM!\n", XNAME(sc)); 543 goto error; 544 } 545 sc->sc_romt = sc->sc_memt; 546 547 /* scratch register test... */ 548 if (radeonfb_scratch_test(sc, RADEON_BIOS_0_SCRATCH, 0x55555555) || 549 radeonfb_scratch_test(sc, RADEON_BIOS_0_SCRATCH, 0xaaaaaaaa)) { 550 aprint_error("%s: scratch register test failed!\n", XNAME(sc)); 551 goto error; 552 } 553 554 PRINTREG(RADEON_BIOS_4_SCRATCH); 555 PRINTREG(RADEON_FP_GEN_CNTL); 556 sc->sc_fp_gen_cntl = GET32(sc, RADEON_FP_GEN_CNTL); 557 PRINTREG(RADEON_FP2_GEN_CNTL); 558 PRINTREG(RADEON_TMDS_CNTL); 559 PRINTREG(RADEON_TMDS_TRANSMITTER_CNTL); 560 PRINTREG(RADEON_TMDS_PLL_CNTL); 561 PRINTREG(RADEON_LVDS_GEN_CNTL); 562 PRINTREG(RADEON_FP_HORZ_STRETCH); 563 PRINTREG(RADEON_FP_VERT_STRETCH); 564 565 /* XXX: RV100 specific */ 566 PUT32(sc, RADEON_TMDS_PLL_CNTL, 0xa27); 567 568 PATCH32(sc, RADEON_TMDS_TRANSMITTER_CNTL, 569 RADEON_TMDS_TRANSMITTER_PLLEN, 570 RADEON_TMDS_TRANSMITTER_PLLEN | RADEON_TMDS_TRANSMITTER_PLLRST); 571 572 radeonfb_i2c_init(sc); 573 574 radeonfb_loadbios(sc, pa); 575 576 #ifdef RADEONFB_BIOS_INIT 577 if (radeonfb_bios_init(sc)) { 578 aprint_error("%s: BIOS inititialization failed\n", XNAME(sc)); 579 } 580 #endif 581 582 if (radeonfb_getclocks(sc)) { 583 aprint_error("%s: Unable to get reference clocks from BIOS\n", 584 XNAME(sc)); 585 goto error; 586 } 587 588 if (radeonfb_gettmds(sc)) { 589 aprint_error("%s: Unable to identify TMDS PLL settings\n", 590 XNAME(sc)); 591 goto error; 592 } 593 594 aprint_verbose("%s: refclk = %d.%03d MHz, refdiv = %d " 595 "minpll = %d, maxpll = %d\n", XNAME(sc), 596 (int)sc->sc_refclk / 1000, (int)sc->sc_refclk % 1000, 597 (int)sc->sc_refdiv, (int)sc->sc_minpll, (int)sc->sc_maxpll); 598 599 radeonfb_getconnectors(sc); 600 601 radeonfb_set_fbloc(sc); 602 603 for (i = 0; radeonfb_limits[i].size; i++) { 604 if (sc->sc_memsz >= radeonfb_limits[i].size) { 605 sc->sc_maxx = radeonfb_limits[i].maxx; 606 sc->sc_maxy = radeonfb_limits[i].maxy; 607 sc->sc_maxbpp = radeonfb_limits[i].maxbpp; 608 /* framebuffer offset, start at a 4K page */ 609 sc->sc_fboffset = sc->sc_memsz / 610 radeonfb_limits[i].maxdisp; 611 /* 612 * we use the fbsize to figure out where we can store 613 * things like cursor data. 614 */ 615 sc->sc_fbsize = 616 ROUNDUP(ROUNDUP(sc->sc_maxx * sc->sc_maxbpp / 8 , 617 RADEON_STRIDEALIGN) * sc->sc_maxy, 618 4096); 619 break; 620 } 621 } 622 623 624 radeonfb_init_misc(sc); 625 radeonfb_init_palette(sc, 0); 626 if (HAS_CRTC2(sc)) 627 radeonfb_init_palette(sc, 1); 628 629 /* program the DAC wirings */ 630 for (i = 0; i < (HAS_CRTC2(sc) ? 2 : 1); i++) { 631 switch (sc->sc_ports[i].rp_dac_type) { 632 case RADEON_DAC_PRIMARY: 633 PATCH32(sc, RADEON_DAC_CNTL2, 634 i ? RADEON_DAC2_DAC_CLK_SEL : 0, 635 ~RADEON_DAC2_DAC_CLK_SEL); 636 break; 637 case RADEON_DAC_TVDAC: 638 /* we always use the TVDAC to drive a secondary analog 639 * CRT for now. if we ever support TV-out this will 640 * have to change. 641 */ 642 SET32(sc, RADEON_DAC_CNTL2, 643 RADEON_DAC2_DAC2_CLK_SEL); 644 PATCH32(sc, RADEON_DISP_HW_DEBUG, 645 i ? 0 : RADEON_CRT2_DISP1_SEL, 646 ~RADEON_CRT2_DISP1_SEL); 647 break; 648 } 649 } 650 PRINTREG(RADEON_DAC_CNTL2); 651 PRINTREG(RADEON_DISP_HW_DEBUG); 652 653 /* other DAC programming */ 654 v = GET32(sc, RADEON_DAC_CNTL); 655 v &= (RADEON_DAC_RANGE_CNTL_MASK | RADEON_DAC_BLANKING); 656 v |= RADEON_DAC_MASK_ALL | RADEON_DAC_8BIT_EN; 657 PUT32(sc, RADEON_DAC_CNTL, v); 658 PRINTREG(RADEON_DAC_CNTL); 659 660 /* XXX: this may need more investigation */ 661 PUT32(sc, RADEON_TV_DAC_CNTL, 0x00280203); 662 PRINTREG(RADEON_TV_DAC_CNTL); 663 664 /* enable TMDS */ 665 SET32(sc, RADEON_FP_GEN_CNTL, 666 RADEON_FP_TMDS_EN | 667 RADEON_FP_CRTC_DONT_SHADOW_VPAR | 668 RADEON_FP_CRTC_DONT_SHADOW_HEND); 669 /* 670 * XXX 671 * no idea why this is necessary - if I do not clear this bit on my 672 * iBook G4 the screen remains black, even though it's already clear. 673 * It needs to be set on my Sun XVR-100 for the DVI port to work 674 */ 675 676 if (sc->sc_fp_gen_cntl & RADEON_FP_SEL_CRTC2) { 677 SET32(sc, RADEON_FP_GEN_CNTL, RADEON_FP_SEL_CRTC2); 678 } else 679 CLR32(sc, RADEON_FP_GEN_CNTL, RADEON_FP_SEL_CRTC2); 680 681 if (HAS_CRTC2(sc)) 682 SET32(sc, RADEON_FP2_GEN_CNTL, RADEON_FP2_SRC_SEL_CRTC2); 683 684 /* 685 * we use bus_space_map instead of pci_mapreg, because we don't 686 * need the full aperature space. no point in wasting virtual 687 * address space we don't intend to use, right? 688 */ 689 if ((sc->sc_memsz < (4096 * 1024)) || 690 (pci_mapreg_info(sc->sc_pc, sc->sc_pt, RADEON_MAPREG_VRAM, 691 PCI_MAPREG_TYPE_MEM, &sc->sc_memaddr, &bsz, NULL) != 0) || 692 (bsz < sc->sc_memsz)) { 693 sc->sc_memsz = 0; 694 aprint_error("%s: Bad frame buffer configuration\n", 695 XNAME(sc)); 696 goto error; 697 } 698 699 /* 64 MB should be enough -- more just wastes map entries */ 700 if (sc->sc_memsz > (64 << 20)) 701 sc->sc_memsz = (64 << 20); 702 703 sc->sc_memt = pa->pa_memt; 704 if (bus_space_map(sc->sc_memt, sc->sc_memaddr, sc->sc_memsz, 705 BUS_SPACE_MAP_LINEAR, &sc->sc_memh) != 0) { 706 sc->sc_memsz = 0; 707 aprint_error("%s: Unable to map frame buffer\n", XNAME(sc)); 708 goto error; 709 } 710 711 aprint_normal("%s: %d MB aperture at 0x%08x, " 712 "%d KB registers at 0x%08x\n", XNAME(sc), 713 (int)sc->sc_memsz >> 20, (unsigned)sc->sc_memaddr, 714 (int)sc->sc_regsz >> 10, (unsigned)sc->sc_regaddr); 715 716 /* setup default video mode from devprop (allows PROM override) */ 717 sc->sc_defaultmode = radeonfb_default_mode; 718 if (prop_dictionary_get_cstring_nocopy(device_properties(sc->sc_dev), 719 "videomode", &mptr)) { 720 721 strncpy(sc->sc_modebuf, mptr, sizeof(sc->sc_modebuf)); 722 sc->sc_defaultmode = sc->sc_modebuf; 723 } 724 725 /* initialize some basic display parameters */ 726 for (i = 0; i < sc->sc_ndisplays; i++) { 727 struct radeonfb_display *dp = &sc->sc_displays[i]; 728 struct rasops_info *ri; 729 long defattr; 730 struct wsemuldisplaydev_attach_args aa; 731 732 /* 733 * Figure out how many "displays" (desktops) we are going to 734 * support. If more than one, then each CRTC gets its own 735 * programming. 736 * 737 * XXX: this code needs to change to support mergedfb. 738 * XXX: would be nice to allow this to be overridden 739 */ 740 if (HAS_CRTC2(sc) && (sc->sc_ndisplays == 1)) { 741 DPRINTF(("dual crtcs!\n")); 742 dp->rd_ncrtcs = 2; 743 dp->rd_crtcs[0].rc_number = 0; 744 dp->rd_crtcs[1].rc_number = 1; 745 } else { 746 dp->rd_ncrtcs = 1; 747 dp->rd_crtcs[0].rc_number = i; 748 } 749 750 /* set up port pointer */ 751 for (j = 0; j < dp->rd_ncrtcs; j++) { 752 dp->rd_crtcs[j].rc_port = 753 &sc->sc_ports[dp->rd_crtcs[j].rc_number]; 754 } 755 756 dp->rd_softc = sc; 757 dp->rd_wsmode = WSDISPLAYIO_MODE_EMUL; 758 dp->rd_bg = WS_DEFAULT_BG; 759 dp->rd_bpp = RADEONFB_DEFAULT_DEPTH; /* XXX */ 760 761 /* for text mode, we pick a resolution that won't 762 * require panning */ 763 radeonfb_pickres(dp, &dp->rd_virtx, &dp->rd_virty, 0); 764 765 aprint_normal("%s: display %d: " 766 "initial virtual resolution %dx%d at %d bpp\n", 767 XNAME(sc), i, dp->rd_virtx, dp->rd_virty, dp->rd_bpp); 768 769 /* now select the *video mode* that we will use */ 770 for (j = 0; j < dp->rd_ncrtcs; j++) { 771 const struct videomode *vmp; 772 vmp = radeonfb_port_mode(sc, dp->rd_crtcs[j].rc_port, 773 dp->rd_virtx, dp->rd_virty); 774 775 /* 776 * virtual resolution should be at least as high as 777 * physical 778 */ 779 if (dp->rd_virtx < vmp->hdisplay || 780 dp->rd_virty < vmp->vdisplay) { 781 dp->rd_virtx = vmp->hdisplay; 782 dp->rd_virty = vmp->vdisplay; 783 } 784 785 dp->rd_crtcs[j].rc_videomode = *vmp; 786 printf("%s: port %d: physical %dx%d %dHz\n", 787 XNAME(sc), j, vmp->hdisplay, vmp->vdisplay, 788 DIVIDE(DIVIDE(vmp->dot_clock * 1000, 789 vmp->htotal), vmp->vtotal)); 790 } 791 792 /* N.B.: radeon wants 64-byte aligned stride */ 793 dp->rd_stride = dp->rd_virtx * dp->rd_bpp / 8; 794 dp->rd_stride = ROUNDUP(dp->rd_stride, RADEON_STRIDEALIGN); 795 796 dp->rd_offset = sc->sc_fboffset * i; 797 dp->rd_fbptr = (vaddr_t)bus_space_vaddr(sc->sc_memt, 798 sc->sc_memh) + dp->rd_offset; 799 dp->rd_curoff = sc->sc_fbsize; 800 dp->rd_curptr = dp->rd_fbptr + dp->rd_curoff; 801 802 DPRINTF(("fpbtr = %p\n", (void *)dp->rd_fbptr)); 803 804 switch (dp->rd_bpp) { 805 case 8: 806 dp->rd_format = 2; 807 break; 808 case 32: 809 dp->rd_format = 6; 810 break; 811 default: 812 aprint_error("%s: bad depth %d\n", XNAME(sc), 813 dp->rd_bpp); 814 goto error; 815 } 816 817 DPRINTF(("init engine\n")); 818 /* XXX: this seems suspicious - per display engine 819 initialization? */ 820 radeonfb_engine_init(dp); 821 822 /* copy the template into place */ 823 dp->rd_wsscreens_storage[0] = radeonfb_stdscreen; 824 dp->rd_wsscreens = dp->rd_wsscreens_storage; 825 826 /* and make up the list */ 827 dp->rd_wsscreenlist.nscreens = 1; 828 dp->rd_wsscreenlist.screens = (void *)&dp->rd_wsscreens; 829 830 vcons_init(&dp->rd_vd, dp, dp->rd_wsscreens, 831 &radeonfb_accessops); 832 833 dp->rd_vd.init_screen = radeonfb_init_screen; 834 835 dp->rd_console = 0; 836 prop_dictionary_get_bool(device_properties(sc->sc_dev), 837 "is_console", &dp->rd_console); 838 839 dp->rd_vscreen.scr_flags |= VCONS_SCREEN_IS_STATIC; 840 841 842 vcons_init_screen(&dp->rd_vd, &dp->rd_vscreen, 843 dp->rd_console, &defattr); 844 845 ri = &dp->rd_vscreen.scr_ri; 846 847 /* clear the screen */ 848 rasops_unpack_attr(defattr, &fg, &bg, &ul); 849 radeonfb_rectfill(dp, 0, 0, ri->ri_width, ri->ri_height, 850 ri->ri_devcmap[bg & 0xf]); 851 852 dp->rd_wsscreens->textops = &ri->ri_ops; 853 dp->rd_wsscreens->capabilities = ri->ri_caps; 854 dp->rd_wsscreens->nrows = ri->ri_rows; 855 dp->rd_wsscreens->ncols = ri->ri_cols; 856 857 #ifdef SPLASHSCREEN 858 dp->rd_splash.si_depth = ri->ri_depth; 859 dp->rd_splash.si_bits = ri->ri_bits; 860 dp->rd_splash.si_hwbits = ri->ri_hwbits; 861 dp->rd_splash.si_width = ri->ri_width; 862 dp->rd_splash.si_height = ri->ri_height; 863 dp->rd_splash.si_stride = ri->ri_stride; 864 dp->rd_splash.si_fillrect = NULL; 865 #endif 866 dp->rd_gc.gc_bitblt = radeonfb_bitblt; 867 dp->rd_gc.gc_rop = RADEON_ROP3_S; 868 dp->rd_gc.gc_blitcookie = dp; 869 glyphcache_init(&dp->rd_gc, dp->rd_virty + 4, 870 (0x800000 / dp->rd_stride) - (dp->rd_virty + 4), 871 dp->rd_virty, 872 ri->ri_font->fontwidth, 873 ri->ri_font->fontheight, 874 defattr); 875 if (dp->rd_console) { 876 877 radeonfb_modeswitch(dp); 878 wsdisplay_cnattach(dp->rd_wsscreens, ri, 0, 0, 879 defattr); 880 #ifdef SPLASHSCREEN 881 if (splash_render(&dp->rd_splash, 882 SPLASH_F_CENTER|SPLASH_F_FILL) == 0) 883 SCREEN_DISABLE_DRAWING(&dp->rd_vscreen); 884 else 885 #endif 886 vcons_replay_msgbuf(&dp->rd_vscreen); 887 } else { 888 889 /* 890 * since we're not the console we can postpone 891 * the rest until someone actually allocates a 892 * screen for us. but we do clear the screen 893 * at least. 894 */ 895 memset(ri->ri_bits, 0, 1024); 896 897 radeonfb_modeswitch(dp); 898 #ifdef SPLASHSCREEN 899 if (splash_render(&dp->rd_splash, 900 SPLASH_F_CENTER|SPLASH_F_FILL) == 0) 901 SCREEN_DISABLE_DRAWING(&dp->rd_vscreen); 902 #endif 903 } 904 905 aa.console = dp->rd_console; 906 aa.scrdata = &dp->rd_wsscreenlist; 907 aa.accessops = &radeonfb_accessops; 908 aa.accesscookie = &dp->rd_vd; 909 910 config_found(sc->sc_dev, &aa, wsemuldisplaydevprint); 911 912 radeonfb_blank(dp, 0); 913 914 /* Initialise delayed lvds operations for backlight. */ 915 callout_init(&dp->rd_bl_lvds_co, 0); 916 callout_setfunc(&dp->rd_bl_lvds_co, 917 radeonfb_lvds_callout, dp); 918 } 919 920 /* 921 * if we have console output via firmware like on sparc64 it may 922 * interfere with DAC programming so program the palette again 923 * here after we took over 924 */ 925 radeonfb_init_palette(sc, 0); 926 if (HAS_CRTC2(sc)) 927 radeonfb_init_palette(sc, 1); 928 929 pmf_event_register(dev, PMFE_DISPLAY_BRIGHTNESS_UP, 930 radeonfb_brightness_up, TRUE); 931 pmf_event_register(dev, PMFE_DISPLAY_BRIGHTNESS_DOWN, 932 radeonfb_brightness_down, TRUE); 933 934 config_found_ia(dev, "drm", aux, radeonfb_drm_print); 935 936 return; 937 938 error: 939 if (sc->sc_biossz) 940 free(sc->sc_bios, M_DEVBUF); 941 942 if (sc->sc_regsz) 943 bus_space_unmap(sc->sc_regt, sc->sc_regh, sc->sc_regsz); 944 945 if (sc->sc_memsz) 946 bus_space_unmap(sc->sc_memt, sc->sc_memh, sc->sc_memsz); 947 } 948 949 static int 950 radeonfb_drm_print(void *aux, const char *pnp) 951 { 952 if (pnp) 953 aprint_normal("drm at %s", pnp); 954 return (UNCONF); 955 } 956 957 int 958 radeonfb_ioctl(void *v, void *vs, 959 unsigned long cmd, void *d, int flag, struct lwp *l) 960 { 961 struct vcons_data *vd; 962 struct radeonfb_display *dp; 963 struct radeonfb_softc *sc; 964 struct wsdisplay_param *param; 965 966 vd = (struct vcons_data *)v; 967 dp = (struct radeonfb_display *)vd->cookie; 968 sc = dp->rd_softc; 969 970 switch (cmd) { 971 case WSDISPLAYIO_GTYPE: 972 *(unsigned *)d = WSDISPLAY_TYPE_PCIMISC; 973 return 0; 974 975 case WSDISPLAYIO_GINFO: 976 if (vd->active != NULL) { 977 struct wsdisplay_fbinfo *fb; 978 fb = (struct wsdisplay_fbinfo *)d; 979 fb->width = dp->rd_virtx; 980 fb->height = dp->rd_virty; 981 fb->depth = dp->rd_bpp; 982 fb->cmsize = 256; 983 return 0; 984 } else 985 return ENODEV; 986 case WSDISPLAYIO_GVIDEO: 987 if (radeonfb_isblank(dp)) 988 *(unsigned *)d = WSDISPLAYIO_VIDEO_OFF; 989 else 990 *(unsigned *)d = WSDISPLAYIO_VIDEO_ON; 991 return 0; 992 993 case WSDISPLAYIO_SVIDEO: 994 radeonfb_blank(dp, 995 (*(unsigned int *)d == WSDISPLAYIO_VIDEO_OFF)); 996 return 0; 997 998 case WSDISPLAYIO_GETCMAP: 999 #if 0 1000 if (dp->rd_bpp == 8) 1001 return radeonfb_getcmap(sc, 1002 (struct wsdisplay_cmap *)d); 1003 #endif 1004 return EINVAL; 1005 1006 case WSDISPLAYIO_PUTCMAP: 1007 #if 0 1008 if (dp->rd_bpp == 8) 1009 return radeonfb_putcmap(sc, 1010 (struct wsdisplay_cmap *)d); 1011 #endif 1012 return EINVAL; 1013 1014 case WSDISPLAYIO_LINEBYTES: 1015 *(unsigned *)d = dp->rd_stride; 1016 return 0; 1017 1018 case WSDISPLAYIO_SMODE: 1019 if (*(int *)d != dp->rd_wsmode) { 1020 dp->rd_wsmode = *(int *)d; 1021 if ((dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) && 1022 (dp->rd_vd.active)) { 1023 radeonfb_engine_init(dp); 1024 glyphcache_wipe(&dp->rd_gc); 1025 radeonfb_init_palette(sc, dp == &sc->sc_displays[0] ? 0 : 1); 1026 radeonfb_modeswitch(dp); 1027 vcons_redraw_screen(dp->rd_vd.active); 1028 } 1029 } 1030 return 0; 1031 1032 case WSDISPLAYIO_GCURMAX: 1033 ((struct wsdisplay_curpos *)d)->x = RADEON_CURSORMAXX; 1034 ((struct wsdisplay_curpos *)d)->y = RADEON_CURSORMAXY; 1035 return 0; 1036 1037 case WSDISPLAYIO_SCURSOR: 1038 return radeonfb_set_cursor(dp, (struct wsdisplay_cursor *)d); 1039 1040 case WSDISPLAYIO_GCURSOR: 1041 return EPASSTHROUGH; 1042 1043 case WSDISPLAYIO_GCURPOS: 1044 ((struct wsdisplay_curpos *)d)->x = dp->rd_cursor.rc_pos.x; 1045 ((struct wsdisplay_curpos *)d)->y = dp->rd_cursor.rc_pos.y; 1046 return 0; 1047 1048 case WSDISPLAYIO_SCURPOS: 1049 return radeonfb_set_curpos(dp, (struct wsdisplay_curpos *)d); 1050 1051 case WSDISPLAYIO_SSPLASH: 1052 #if defined(SPLASHSCREEN) 1053 if (*(int *)d == 1) { 1054 SCREEN_DISABLE_DRAWING(&dp->rd_vscreen); 1055 splash_render(&dp->rd_splash, 1056 SPLASH_F_CENTER|SPLASH_F_FILL); 1057 } else 1058 SCREEN_ENABLE_DRAWING(&dp->rd_vscreen); 1059 return 0; 1060 #else 1061 return ENODEV; 1062 #endif 1063 case WSDISPLAYIO_GETPARAM: 1064 param = (struct wsdisplay_param *)d; 1065 if (param->param == WSDISPLAYIO_PARAM_BACKLIGHT) { 1066 param->min = 0; 1067 param->max = RADEONFB_BACKLIGHT_MAX; 1068 param->curval = radeonfb_get_backlight(dp); 1069 return 0; 1070 } 1071 return EPASSTHROUGH; 1072 1073 case WSDISPLAYIO_SETPARAM: 1074 param = (struct wsdisplay_param *)d; 1075 if (param->param == WSDISPLAYIO_PARAM_BACKLIGHT) { 1076 return radeonfb_set_backlight(dp, param->curval); 1077 } 1078 return EPASSTHROUGH; 1079 1080 /* PCI config read/write passthrough. */ 1081 case PCI_IOC_CFGREAD: 1082 case PCI_IOC_CFGWRITE: 1083 return pci_devioctl(sc->sc_pc, sc->sc_pt, cmd, d, flag, l); 1084 1085 case WSDISPLAYIO_GET_BUSID: 1086 return wsdisplayio_busid_pci(sc->sc_dev, sc->sc_pc, 1087 sc->sc_pt, d); 1088 1089 case WSDISPLAYIO_GET_EDID: { 1090 struct wsdisplayio_edid_info *ei = d; 1091 return wsdisplayio_get_edid(sc->sc_dev, ei); 1092 } 1093 1094 default: 1095 return EPASSTHROUGH; 1096 } 1097 } 1098 1099 paddr_t 1100 radeonfb_mmap(void *v, void *vs, off_t offset, int prot) 1101 { 1102 struct vcons_data *vd; 1103 struct radeonfb_display *dp; 1104 struct radeonfb_softc *sc; 1105 paddr_t pa; 1106 1107 vd = (struct vcons_data *)v; 1108 dp = (struct radeonfb_display *)vd->cookie; 1109 sc = dp->rd_softc; 1110 1111 /* XXX: note that we don't allow mapping of registers right now */ 1112 /* XXX: this means that the XFree86 radeon driver won't work */ 1113 if ((offset >= 0) && (offset < (dp->rd_virty * dp->rd_stride))) { 1114 pa = bus_space_mmap(sc->sc_memt, 1115 sc->sc_memaddr + dp->rd_offset + offset, 0, 1116 prot, BUS_SPACE_MAP_LINEAR); 1117 return pa; 1118 } 1119 1120 #ifdef RADEONFB_MMAP_BARS 1121 /* 1122 * restrict all other mappings to processes with superuser privileges 1123 * or the kernel itself 1124 */ 1125 if (kauth_authorize_generic(kauth_cred_get(), KAUTH_GENERIC_ISSUSER, 1126 NULL) != 0) { 1127 aprint_error_dev(sc->sc_dev, "mmap() rejected.\n"); 1128 return -1; 1129 } 1130 1131 if ((offset >= sc->sc_regaddr) && 1132 (offset < sc->sc_regaddr + sc->sc_regsz)) { 1133 return bus_space_mmap(sc->sc_regt, offset, 0, prot, 1134 BUS_SPACE_MAP_LINEAR); 1135 } 1136 1137 if ((offset >= sc->sc_memaddr) && 1138 (offset < sc->sc_memaddr + sc->sc_memsz)) { 1139 return bus_space_mmap(sc->sc_memt, offset, 0, prot, 1140 BUS_SPACE_MAP_LINEAR); 1141 } 1142 1143 if ((offset >= sc->sc_romaddr) && 1144 (offset < sc->sc_romaddr + sc->sc_romsz)) { 1145 return bus_space_mmap(sc->sc_memt, offset, 0, prot, 1146 BUS_SPACE_MAP_LINEAR); 1147 } 1148 1149 #ifdef PCI_MAGIC_IO_RANGE 1150 /* allow mapping of IO space */ 1151 if ((offset >= PCI_MAGIC_IO_RANGE) && 1152 (offset < PCI_MAGIC_IO_RANGE + 0x10000)) { 1153 pa = bus_space_mmap(sc->sc_iot, offset - PCI_MAGIC_IO_RANGE, 1154 0, prot, 0); 1155 return pa; 1156 } 1157 #endif /* PCI_MAGIC_IO_RANGE */ 1158 1159 #endif /* RADEONFB_MMAP_BARS */ 1160 1161 return -1; 1162 } 1163 1164 static void 1165 radeonfb_loadbios(struct radeonfb_softc *sc, const struct pci_attach_args *pa) 1166 { 1167 bus_space_tag_t romt; 1168 bus_space_handle_t romh, biosh; 1169 bus_size_t romsz; 1170 bus_addr_t ptr; 1171 1172 if (pci_mapreg_map(pa, PCI_MAPREG_ROM, PCI_MAPREG_TYPE_ROM, 1173 BUS_SPACE_MAP_PREFETCHABLE, &romt, &romh, NULL, &romsz) != 0) { 1174 aprint_verbose("%s: unable to map BIOS!\n", XNAME(sc)); 1175 return; 1176 } 1177 1178 pci_find_rom(pa, romt, romh, PCI_ROM_CODE_TYPE_X86, &biosh, 1179 &sc->sc_biossz); 1180 if (sc->sc_biossz == 0) { 1181 aprint_verbose("%s: Video BIOS not present\n", XNAME(sc)); 1182 return; 1183 } 1184 1185 sc->sc_bios = malloc(sc->sc_biossz, M_DEVBUF, M_WAITOK); 1186 bus_space_read_region_1(romt, biosh, 0, sc->sc_bios, sc->sc_biossz); 1187 1188 /* unmap the PCI expansion rom */ 1189 bus_space_unmap(romt, romh, romsz); 1190 1191 /* turn off rom decoder now */ 1192 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM, 1193 pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM) & 1194 ~PCI_MAPREG_ROM_ENABLE); 1195 1196 ptr = GETBIOS16(sc, 0x48); 1197 if ((GETBIOS32(sc, ptr + 4) == 0x41544f4d /* "ATOM" */) || 1198 (GETBIOS32(sc, ptr + 4) == 0x4d4f5441 /* "MOTA" */)) { 1199 sc->sc_flags |= RFB_ATOM; 1200 } 1201 1202 aprint_verbose("%s: Found %d KB %s BIOS\n", XNAME(sc), 1203 (unsigned)sc->sc_biossz >> 10, IS_ATOM(sc) ? "ATOM" : "Legacy"); 1204 } 1205 1206 1207 uint32_t 1208 radeonfb_get32(struct radeonfb_softc *sc, uint32_t reg) 1209 { 1210 1211 return bus_space_read_4(sc->sc_regt, sc->sc_regh, reg); 1212 } 1213 1214 void 1215 radeonfb_put32(struct radeonfb_softc *sc, uint32_t reg, uint32_t val) 1216 { 1217 1218 bus_space_write_4(sc->sc_regt, sc->sc_regh, reg, val); 1219 } 1220 1221 void 1222 radeonfb_mask32(struct radeonfb_softc *sc, uint32_t reg, 1223 uint32_t andmask, uint32_t ormask) 1224 { 1225 int s; 1226 uint32_t val; 1227 1228 s = splhigh(); 1229 val = radeonfb_get32(sc, reg); 1230 val = (val & andmask) | ormask; 1231 radeonfb_put32(sc, reg, val); 1232 splx(s); 1233 } 1234 1235 uint32_t 1236 radeonfb_getindex(struct radeonfb_softc *sc, uint32_t idx) 1237 { 1238 int s; 1239 uint32_t val; 1240 1241 s = splhigh(); 1242 radeonfb_put32(sc, RADEON_MM_INDEX, idx); 1243 val = radeonfb_get32(sc, RADEON_MM_DATA); 1244 splx(s); 1245 1246 return (val); 1247 } 1248 1249 void 1250 radeonfb_putindex(struct radeonfb_softc *sc, uint32_t idx, uint32_t val) 1251 { 1252 int s; 1253 1254 s = splhigh(); 1255 radeonfb_put32(sc, RADEON_MM_INDEX, idx); 1256 radeonfb_put32(sc, RADEON_MM_DATA, val); 1257 splx(s); 1258 } 1259 1260 void 1261 radeonfb_maskindex(struct radeonfb_softc *sc, uint32_t idx, 1262 uint32_t andmask, uint32_t ormask) 1263 { 1264 int s; 1265 uint32_t val; 1266 1267 s = splhigh(); 1268 radeonfb_put32(sc, RADEON_MM_INDEX, idx); 1269 val = radeonfb_get32(sc, RADEON_MM_DATA); 1270 val = (val & andmask) | ormask; 1271 radeonfb_put32(sc, RADEON_MM_DATA, val); 1272 splx(s); 1273 } 1274 1275 uint32_t 1276 radeonfb_getpll(struct radeonfb_softc *sc, uint32_t idx) 1277 { 1278 int s; 1279 uint32_t val; 1280 1281 s = splhigh(); 1282 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, idx & 0x3f); 1283 val = radeonfb_get32(sc, RADEON_CLOCK_CNTL_DATA); 1284 if (HAS_R300CG(sc)) 1285 radeonfb_r300cg_workaround(sc); 1286 splx(s); 1287 1288 return (val); 1289 } 1290 1291 void 1292 radeonfb_putpll(struct radeonfb_softc *sc, uint32_t idx, uint32_t val) 1293 { 1294 int s; 1295 1296 s = splhigh(); 1297 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, (idx & 0x3f) | 1298 RADEON_PLL_WR_EN); 1299 radeonfb_put32(sc, RADEON_CLOCK_CNTL_DATA, val); 1300 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, 0); 1301 splx(s); 1302 } 1303 1304 void 1305 radeonfb_maskpll(struct radeonfb_softc *sc, uint32_t idx, 1306 uint32_t andmask, uint32_t ormask) 1307 { 1308 int s; 1309 uint32_t val; 1310 1311 s = splhigh(); 1312 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, (idx & 0x3f) | 1313 RADEON_PLL_WR_EN); 1314 val = radeonfb_get32(sc, RADEON_CLOCK_CNTL_DATA); 1315 val = (val & andmask) | ormask; 1316 radeonfb_put32(sc, RADEON_CLOCK_CNTL_DATA, val); 1317 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, 0); 1318 splx(s); 1319 } 1320 1321 int 1322 radeonfb_scratch_test(struct radeonfb_softc *sc, int reg, uint32_t v) 1323 { 1324 uint32_t saved; 1325 1326 saved = GET32(sc, reg); 1327 PUT32(sc, reg, v); 1328 if (GET32(sc, reg) != v) { 1329 return -1; 1330 } 1331 PUT32(sc, reg, saved); 1332 return 0; 1333 } 1334 1335 uintmax_t 1336 radeonfb_getprop_num(struct radeonfb_softc *sc, const char *name, 1337 uintmax_t defval) 1338 { 1339 prop_number_t pn; 1340 pn = prop_dictionary_get(device_properties(sc->sc_dev), name); 1341 if (pn == NULL) { 1342 return defval; 1343 } 1344 KASSERT(prop_object_type(pn) == PROP_TYPE_NUMBER); 1345 return (prop_number_integer_value(pn)); 1346 } 1347 1348 int 1349 radeonfb_getclocks(struct radeonfb_softc *sc) 1350 { 1351 bus_addr_t ptr; 1352 int refclk = 0; 1353 int refdiv = 0; 1354 int minpll = 0; 1355 int maxpll = 0; 1356 1357 /* load initial property values if port/board provides them */ 1358 refclk = radeonfb_getprop_num(sc, "refclk", 0) & 0xffff; 1359 refdiv = radeonfb_getprop_num(sc, "refdiv", 0) & 0xffff; 1360 minpll = radeonfb_getprop_num(sc, "minpll", 0) & 0xffffffffU; 1361 maxpll = radeonfb_getprop_num(sc, "maxpll", 0) & 0xffffffffU; 1362 1363 if (refclk && refdiv && minpll && maxpll) 1364 goto dontprobe; 1365 1366 if (!sc->sc_biossz) { 1367 /* no BIOS */ 1368 aprint_verbose("%s: No video BIOS, using default clocks\n", 1369 XNAME(sc)); 1370 if (IS_IGP(sc)) 1371 refclk = refclk ? refclk : 1432; 1372 else 1373 refclk = refclk ? refclk : 2700; 1374 refdiv = refdiv ? refdiv : 12; 1375 minpll = minpll ? minpll : 12500; 1376 maxpll = maxpll ? maxpll : 35000; 1377 } else if (IS_ATOM(sc)) { 1378 /* ATOM BIOS */ 1379 ptr = GETBIOS16(sc, 0x48); 1380 ptr = GETBIOS16(sc, ptr + 32); /* aka MasterDataStart */ 1381 ptr = GETBIOS16(sc, ptr + 12); /* pll info block */ 1382 refclk = refclk ? refclk : GETBIOS16(sc, ptr + 82); 1383 minpll = minpll ? minpll : GETBIOS16(sc, ptr + 78); 1384 maxpll = maxpll ? maxpll : GETBIOS16(sc, ptr + 32); 1385 /* 1386 * ATOM BIOS doesn't supply a reference divider, so we 1387 * have to probe for it. 1388 */ 1389 if (refdiv < 2) 1390 refdiv = GETPLL(sc, RADEON_PPLL_REF_DIV) & 1391 RADEON_PPLL_REF_DIV_MASK; 1392 /* 1393 * if probe is zero, just assume one that should work 1394 * for most parts 1395 */ 1396 if (refdiv < 2) 1397 refdiv = 12; 1398 1399 } else { 1400 /* Legacy BIOS */ 1401 ptr = GETBIOS16(sc, 0x48); 1402 ptr = GETBIOS16(sc, ptr + 0x30); 1403 refclk = refclk ? refclk : GETBIOS16(sc, ptr + 0x0E); 1404 refdiv = refdiv ? refdiv : GETBIOS16(sc, ptr + 0x10); 1405 minpll = minpll ? minpll : GETBIOS32(sc, ptr + 0x12); 1406 maxpll = maxpll ? maxpll : GETBIOS32(sc, ptr + 0x16); 1407 } 1408 1409 1410 dontprobe: 1411 sc->sc_refclk = refclk * 10; 1412 sc->sc_refdiv = refdiv; 1413 sc->sc_minpll = minpll * 10; 1414 sc->sc_maxpll = maxpll * 10; 1415 return 0; 1416 } 1417 1418 int 1419 radeonfb_calc_dividers(struct radeonfb_softc *sc, uint32_t dotclock, 1420 uint32_t *postdivbit, uint32_t *feedbackdiv) 1421 { 1422 int i; 1423 uint32_t outfreq; 1424 int div; 1425 1426 DPRINTF(("dot clock: %u\n", dotclock)); 1427 for (i = 0; (div = radeonfb_dividers[i].divider) != 0; i++) { 1428 outfreq = div * dotclock; 1429 if ((outfreq >= sc->sc_minpll) && 1430 (outfreq <= sc->sc_maxpll)) { 1431 DPRINTF(("outfreq: %u\n", outfreq)); 1432 *postdivbit = 1433 ((uint32_t)radeonfb_dividers[i].mask << 16); 1434 DPRINTF(("post divider: %d (mask %x)\n", div, 1435 *postdivbit)); 1436 break; 1437 } 1438 } 1439 1440 if (div == 0) 1441 return 1; 1442 1443 *feedbackdiv = DIVIDE(sc->sc_refdiv * outfreq, sc->sc_refclk); 1444 DPRINTF(("feedback divider: %d\n", *feedbackdiv)); 1445 return 0; 1446 } 1447 1448 #if 0 1449 #ifdef RADEONFB_DEBUG 1450 static void 1451 dump_buffer(const char *pfx, void *buffer, unsigned int size) 1452 { 1453 char asc[17]; 1454 unsigned ptr = (unsigned)buffer; 1455 char *start = (char *)(ptr & ~0xf); 1456 char *end = (char *)(ptr + size); 1457 1458 end = (char *)(((unsigned)end + 0xf) & ~0xf); 1459 1460 if (pfx == NULL) { 1461 pfx = ""; 1462 } 1463 1464 while (start < end) { 1465 unsigned offset = (unsigned)start & 0xf; 1466 if (offset == 0) { 1467 printf("%s%x: ", pfx, (unsigned)start); 1468 } 1469 if (((unsigned)start < ptr) || 1470 ((unsigned)start >= (ptr + size))) { 1471 printf(" "); 1472 asc[offset] = ' '; 1473 } else { 1474 printf("%02x", *(unsigned char *)start); 1475 if ((*start >= ' ') && (*start <= '~')) { 1476 asc[offset] = *start; 1477 } else { 1478 asc[offset] = '.'; 1479 } 1480 } 1481 asc[offset + 1] = 0; 1482 if (offset % 2) { 1483 printf(" "); 1484 } 1485 if (offset == 15) { 1486 printf(" %s\n", asc); 1487 } 1488 start++; 1489 } 1490 } 1491 #endif 1492 #endif 1493 1494 int 1495 radeonfb_getconnectors(struct radeonfb_softc *sc) 1496 { 1497 int i; 1498 int found = 0; 1499 1500 for (i = 0; i < 2; i++) { 1501 sc->sc_ports[i].rp_mon_type = RADEON_MT_UNKNOWN; 1502 sc->sc_ports[i].rp_ddc_type = RADEON_DDC_NONE; 1503 sc->sc_ports[i].rp_dac_type = RADEON_DAC_UNKNOWN; 1504 sc->sc_ports[i].rp_conn_type = RADEON_CONN_NONE; 1505 sc->sc_ports[i].rp_tmds_type = RADEON_TMDS_UNKNOWN; 1506 } 1507 1508 /* 1509 * This logic is borrowed from Xorg's radeon driver. 1510 */ 1511 if (!sc->sc_biossz) 1512 goto nobios; 1513 1514 if (IS_ATOM(sc)) { 1515 /* not done yet */ 1516 } else { 1517 uint16_t ptr; 1518 int port = 0; 1519 1520 ptr = GETBIOS16(sc, 0x48); 1521 ptr = GETBIOS16(sc, ptr + 0x50); 1522 for (i = 1; i < 4; i++) { 1523 uint16_t entry; 1524 uint8_t conn, ddc, dac, tmds; 1525 1526 /* 1527 * Parse the connector table. From reading the code, 1528 * it appears to made up of 16-bit entries for each 1529 * connector. The 16-bits are defined as: 1530 * 1531 * bits 12-15 - connector type (0 == end of table) 1532 * bits 8-11 - DDC type 1533 * bits 5-7 - ??? 1534 * bit 4 - TMDS type (1 = EXT, 0 = INT) 1535 * bits 1-3 - ??? 1536 * bit 0 - DAC, 1 = TVDAC, 0 = primary 1537 */ 1538 if (!GETBIOS8(sc, ptr + i * 2) && i > 1) 1539 break; 1540 entry = GETBIOS16(sc, ptr + i * 2); 1541 1542 conn = (entry >> 12) & 0xf; 1543 ddc = (entry >> 8) & 0xf; 1544 dac = (entry & 0x1) ? RADEON_DAC_TVDAC : 1545 RADEON_DAC_PRIMARY; 1546 tmds = ((entry >> 4) & 0x1) ? RADEON_TMDS_EXT : 1547 RADEON_TMDS_INT; 1548 1549 if (conn == RADEON_CONN_NONE) 1550 continue; /* no connector */ 1551 1552 if ((found > 0) && 1553 (sc->sc_ports[port].rp_ddc_type == ddc)) { 1554 /* duplicate entry for same connector */ 1555 continue; 1556 } 1557 1558 /* internal DDC_DVI port gets priority */ 1559 if ((ddc == RADEON_DDC_DVI) || (port == 1)) 1560 port = 0; 1561 else 1562 port = 1; 1563 1564 sc->sc_ports[port].rp_ddc_type = 1565 ddc > RADEON_DDC_CRT2 ? RADEON_DDC_NONE : ddc; 1566 sc->sc_ports[port].rp_dac_type = dac; 1567 sc->sc_ports[port].rp_conn_type = 1568 min(conn, RADEON_CONN_UNSUPPORTED) ; 1569 1570 sc->sc_ports[port].rp_tmds_type = tmds; 1571 1572 if ((conn != RADEON_CONN_DVI_I) && 1573 (conn != RADEON_CONN_DVI_D) && 1574 (tmds == RADEON_TMDS_INT)) 1575 sc->sc_ports[port].rp_tmds_type = 1576 RADEON_TMDS_UNKNOWN; 1577 1578 found += (port + 1); 1579 } 1580 } 1581 1582 nobios: 1583 if (!found) { 1584 DPRINTF(("No connector info in BIOS!\n")); 1585 /* default, port 0 = internal TMDS, port 1 = CRT */ 1586 sc->sc_ports[0].rp_mon_type = RADEON_MT_UNKNOWN; 1587 sc->sc_ports[0].rp_ddc_type = RADEON_DDC_DVI; 1588 sc->sc_ports[0].rp_dac_type = RADEON_DAC_TVDAC; 1589 sc->sc_ports[0].rp_conn_type = RADEON_CONN_DVI_D; 1590 sc->sc_ports[0].rp_tmds_type = RADEON_TMDS_INT; 1591 1592 sc->sc_ports[1].rp_mon_type = RADEON_MT_UNKNOWN; 1593 sc->sc_ports[1].rp_ddc_type = RADEON_DDC_VGA; 1594 sc->sc_ports[1].rp_dac_type = RADEON_DAC_PRIMARY; 1595 sc->sc_ports[1].rp_conn_type = RADEON_CONN_CRT; 1596 sc->sc_ports[1].rp_tmds_type = RADEON_TMDS_EXT; 1597 } 1598 1599 /* 1600 * Fixup for RS300/RS350/RS400 chips, that lack a primary DAC. 1601 * these chips should use TVDAC for the VGA port. 1602 */ 1603 if (HAS_SDAC(sc)) { 1604 if (sc->sc_ports[0].rp_conn_type == RADEON_CONN_CRT) { 1605 sc->sc_ports[0].rp_dac_type = RADEON_DAC_TVDAC; 1606 sc->sc_ports[1].rp_dac_type = RADEON_DAC_PRIMARY; 1607 } else { 1608 sc->sc_ports[1].rp_dac_type = RADEON_DAC_TVDAC; 1609 sc->sc_ports[0].rp_dac_type = RADEON_DAC_PRIMARY; 1610 } 1611 } else if (!HAS_CRTC2(sc)) { 1612 sc->sc_ports[0].rp_dac_type = RADEON_DAC_PRIMARY; 1613 } 1614 1615 for (i = 0; i < 2; i++) { 1616 char edid[128]; 1617 uint8_t ddc; 1618 struct edid_info *eip = &sc->sc_ports[i].rp_edid; 1619 prop_data_t edid_data; 1620 1621 DPRINTF(("Port #%d:\n", i)); 1622 DPRINTF((" conn = %d\n", sc->sc_ports[i].rp_conn_type)); 1623 DPRINTF((" ddc = %d\n", sc->sc_ports[i].rp_ddc_type)); 1624 DPRINTF((" dac = %d\n", sc->sc_ports[i].rp_dac_type)); 1625 DPRINTF((" tmds = %d\n", sc->sc_ports[i].rp_tmds_type)); 1626 1627 sc->sc_ports[i].rp_edid_valid = 0; 1628 /* first look for static EDID data */ 1629 if ((edid_data = prop_dictionary_get(device_properties( 1630 sc->sc_dev), "EDID")) != NULL) { 1631 1632 aprint_normal_dev(sc->sc_dev, "using static EDID\n"); 1633 memcpy(edid, prop_data_data_nocopy(edid_data), 128); 1634 if (edid_parse(edid, eip) == 0) { 1635 1636 sc->sc_ports[i].rp_edid_valid = 1; 1637 } 1638 } 1639 /* if we didn't find any we'll try to talk to the monitor */ 1640 if (sc->sc_ports[i].rp_edid_valid != 1) { 1641 1642 ddc = sc->sc_ports[i].rp_ddc_type; 1643 if (ddc != RADEON_DDC_NONE) { 1644 if ((radeonfb_i2c_read_edid(sc, ddc, edid) 1645 == 0) && (edid_parse(edid, eip) == 0)) { 1646 1647 sc->sc_ports[i].rp_edid_valid = 1; 1648 edid_print(eip); 1649 } 1650 } 1651 } 1652 } 1653 1654 return found; 1655 } 1656 1657 int 1658 radeonfb_gettmds(struct radeonfb_softc *sc) 1659 { 1660 int i; 1661 1662 if (!sc->sc_biossz) { 1663 goto nobios; 1664 } 1665 1666 if (IS_ATOM(sc)) { 1667 /* XXX: not done yet */ 1668 } else { 1669 uint16_t ptr; 1670 int n; 1671 1672 ptr = GETBIOS16(sc, 0x48); 1673 ptr = GETBIOS16(sc, ptr + 0x34); 1674 DPRINTF(("DFP table revision %d\n", GETBIOS8(sc, ptr))); 1675 if (GETBIOS8(sc, ptr) == 3) { 1676 /* revision three table */ 1677 n = GETBIOS8(sc, ptr + 5) + 1; 1678 n = min(n, 4); 1679 1680 memset(sc->sc_tmds_pll, 0, sizeof (sc->sc_tmds_pll)); 1681 for (i = 0; i < n; i++) { 1682 sc->sc_tmds_pll[i].rtp_pll = GETBIOS32(sc, 1683 ptr + i * 10 + 8); 1684 sc->sc_tmds_pll[i].rtp_freq = GETBIOS16(sc, 1685 ptr + i * 10 + 0x10); 1686 DPRINTF(("TMDS_PLL dot clock %d pll %x\n", 1687 sc->sc_tmds_pll[i].rtp_freq, 1688 sc->sc_tmds_pll[i].rtp_pll)); 1689 } 1690 return 0; 1691 } 1692 } 1693 1694 nobios: 1695 DPRINTF(("no suitable DFP table present\n")); 1696 for (i = 0; 1697 i < sizeof (radeonfb_tmds_pll) / sizeof (radeonfb_tmds_pll[0]); 1698 i++) { 1699 int j; 1700 1701 if (radeonfb_tmds_pll[i].family != sc->sc_family) 1702 continue; 1703 1704 for (j = 0; j < 4; j++) { 1705 sc->sc_tmds_pll[j] = radeonfb_tmds_pll[i].plls[j]; 1706 DPRINTF(("TMDS_PLL dot clock %d pll %x\n", 1707 sc->sc_tmds_pll[j].rtp_freq, 1708 sc->sc_tmds_pll[j].rtp_pll)); 1709 } 1710 return 0; 1711 } 1712 1713 return -1; 1714 } 1715 1716 const struct videomode * 1717 radeonfb_modelookup(const char *name) 1718 { 1719 int i; 1720 1721 for (i = 0; i < videomode_count; i++) 1722 if (!strcmp(name, videomode_list[i].name)) 1723 return &videomode_list[i]; 1724 1725 return NULL; 1726 } 1727 1728 void 1729 radeonfb_pllwriteupdate(struct radeonfb_softc *sc, int crtc) 1730 { 1731 if (crtc) { 1732 while (GETPLL(sc, RADEON_P2PLL_REF_DIV) & 1733 RADEON_P2PLL_ATOMIC_UPDATE_R); 1734 SETPLL(sc, RADEON_P2PLL_REF_DIV, RADEON_P2PLL_ATOMIC_UPDATE_W); 1735 } else { 1736 while (GETPLL(sc, RADEON_PPLL_REF_DIV) & 1737 RADEON_PPLL_ATOMIC_UPDATE_R); 1738 SETPLL(sc, RADEON_PPLL_REF_DIV, RADEON_PPLL_ATOMIC_UPDATE_W); 1739 } 1740 } 1741 1742 void 1743 radeonfb_pllwaitatomicread(struct radeonfb_softc *sc, int crtc) 1744 { 1745 int i; 1746 1747 for (i = 10000; i; i--) { 1748 if (crtc) { 1749 if (GETPLL(sc, RADEON_P2PLL_REF_DIV) & 1750 RADEON_P2PLL_ATOMIC_UPDATE_R) 1751 break; 1752 } else { 1753 if (GETPLL(sc, RADEON_PPLL_REF_DIV) & 1754 RADEON_PPLL_ATOMIC_UPDATE_R) 1755 break; 1756 } 1757 } 1758 } 1759 1760 void 1761 radeonfb_program_vclk(struct radeonfb_softc *sc, int dotclock, int crtc) 1762 { 1763 uint32_t pbit = 0; 1764 uint32_t feed = 0; 1765 uint32_t data; 1766 #if 1 1767 int i; 1768 #endif 1769 1770 radeonfb_calc_dividers(sc, dotclock, &pbit, &feed); 1771 1772 if (crtc == 0) { 1773 1774 /* XXXX: mobility workaround missing */ 1775 /* XXXX: R300 stuff missing */ 1776 1777 PATCHPLL(sc, RADEON_VCLK_ECP_CNTL, 1778 RADEON_VCLK_SRC_SEL_CPUCLK, 1779 ~RADEON_VCLK_SRC_SEL_MASK); 1780 1781 /* put vclk into reset, use atomic updates */ 1782 SETPLL(sc, RADEON_PPLL_CNTL, 1783 RADEON_PPLL_REFCLK_SEL | 1784 RADEON_PPLL_FBCLK_SEL | 1785 RADEON_PPLL_RESET | 1786 RADEON_PPLL_ATOMIC_UPDATE_EN | 1787 RADEON_PPLL_VGA_ATOMIC_UPDATE_EN); 1788 1789 /* select clock 3 */ 1790 #if 0 1791 PATCH32(sc, RADEON_CLOCK_CNTL_INDEX, RADEON_PLL_DIV_SEL, 1792 ~RADEON_PLL_DIV_SEL); 1793 #else 1794 PATCH32(sc, RADEON_CLOCK_CNTL_INDEX, 0, 1795 ~RADEON_PLL_DIV_SEL); 1796 #endif 1797 1798 /* XXX: R300 family -- program divider differently? */ 1799 1800 /* program reference divider */ 1801 PATCHPLL(sc, RADEON_PPLL_REF_DIV, sc->sc_refdiv, 1802 ~RADEON_PPLL_REF_DIV_MASK); 1803 PRINTPLL(RADEON_PPLL_REF_DIV); 1804 1805 #if 0 1806 data = GETPLL(sc, RADEON_PPLL_DIV_3); 1807 data &= ~(RADEON_PPLL_FB3_DIV_MASK | 1808 RADEON_PPLL_POST3_DIV_MASK); 1809 data |= pbit; 1810 data |= (feed & RADEON_PPLL_FB3_DIV_MASK); 1811 PUTPLL(sc, RADEON_PPLL_DIV_3, data); 1812 #else 1813 for (i = 0; i < 4; i++) { 1814 } 1815 #endif 1816 1817 /* use the atomic update */ 1818 radeonfb_pllwriteupdate(sc, crtc); 1819 1820 /* and wait for it to complete */ 1821 radeonfb_pllwaitatomicread(sc, crtc); 1822 1823 /* program HTOTAL (why?) */ 1824 PUTPLL(sc, RADEON_HTOTAL_CNTL, 0); 1825 1826 /* drop reset */ 1827 CLRPLL(sc, RADEON_PPLL_CNTL, 1828 RADEON_PPLL_RESET | RADEON_PPLL_SLEEP | 1829 RADEON_PPLL_ATOMIC_UPDATE_EN | 1830 RADEON_PPLL_VGA_ATOMIC_UPDATE_EN); 1831 1832 PRINTPLL(RADEON_PPLL_CNTL); 1833 1834 /* give clock time to lock */ 1835 delay(50000); 1836 1837 PATCHPLL(sc, RADEON_VCLK_ECP_CNTL, 1838 RADEON_VCLK_SRC_SEL_PPLLCLK, 1839 ~RADEON_VCLK_SRC_SEL_MASK); 1840 1841 } else { 1842 1843 PATCHPLL(sc, RADEON_PIXCLKS_CNTL, 1844 RADEON_PIX2CLK_SRC_SEL_CPUCLK, 1845 ~RADEON_PIX2CLK_SRC_SEL_MASK); 1846 1847 /* put vclk into reset, use atomic updates */ 1848 SETPLL(sc, RADEON_P2PLL_CNTL, 1849 RADEON_P2PLL_RESET | 1850 RADEON_P2PLL_ATOMIC_UPDATE_EN | 1851 RADEON_P2PLL_VGA_ATOMIC_UPDATE_EN); 1852 1853 /* XXX: R300 family -- program divider differently? */ 1854 1855 /* program reference divider */ 1856 PATCHPLL(sc, RADEON_P2PLL_REF_DIV, sc->sc_refdiv, 1857 ~RADEON_P2PLL_REF_DIV_MASK); 1858 1859 /* program feedback and post dividers */ 1860 data = GETPLL(sc, RADEON_P2PLL_DIV_0); 1861 data &= ~(RADEON_P2PLL_FB0_DIV_MASK | 1862 RADEON_P2PLL_POST0_DIV_MASK); 1863 data |= pbit; 1864 data |= (feed & RADEON_P2PLL_FB0_DIV_MASK); 1865 PUTPLL(sc, RADEON_P2PLL_DIV_0, data); 1866 1867 /* use the atomic update */ 1868 radeonfb_pllwriteupdate(sc, crtc); 1869 1870 /* and wait for it to complete */ 1871 radeonfb_pllwaitatomicread(sc, crtc); 1872 1873 /* program HTOTAL (why?) */ 1874 PUTPLL(sc, RADEON_HTOTAL2_CNTL, 0); 1875 1876 /* drop reset */ 1877 CLRPLL(sc, RADEON_P2PLL_CNTL, 1878 RADEON_P2PLL_RESET | RADEON_P2PLL_SLEEP | 1879 RADEON_P2PLL_ATOMIC_UPDATE_EN | 1880 RADEON_P2PLL_VGA_ATOMIC_UPDATE_EN); 1881 1882 /* allow time for clock to lock */ 1883 delay(50000); 1884 1885 PATCHPLL(sc, RADEON_PIXCLKS_CNTL, 1886 RADEON_PIX2CLK_SRC_SEL_P2PLLCLK, 1887 ~RADEON_PIX2CLK_SRC_SEL_MASK); 1888 } 1889 PRINTREG(RADEON_CRTC_MORE_CNTL); 1890 } 1891 1892 void 1893 radeonfb_modeswitch(struct radeonfb_display *dp) 1894 { 1895 struct radeonfb_softc *sc = dp->rd_softc; 1896 int i; 1897 1898 /* blank the display while we switch modes */ 1899 radeonfb_blank(dp, 1); 1900 1901 #if 0 1902 SET32(sc, RADEON_CRTC_EXT_CNTL, 1903 RADEON_CRTC_VSYNC_DIS | RADEON_CRTC_HSYNC_DIS | 1904 RADEON_CRTC_DISPLAY_DIS /* | RADEON_CRTC_DISP_REQ_EN_B */); 1905 #endif 1906 1907 /* these registers might get in the way... */ 1908 PUT32(sc, RADEON_OVR_CLR, 0); 1909 PUT32(sc, RADEON_OVR_WID_LEFT_RIGHT, 0); 1910 PUT32(sc, RADEON_OVR_WID_TOP_BOTTOM, 0); 1911 PUT32(sc, RADEON_OV0_SCALE_CNTL, 0); 1912 PUT32(sc, RADEON_SUBPIC_CNTL, 0); 1913 PUT32(sc, RADEON_VIPH_CONTROL, 0); 1914 PUT32(sc, RADEON_I2C_CNTL_1, 0); 1915 PUT32(sc, RADEON_GEN_INT_CNTL, 0); 1916 PUT32(sc, RADEON_CAP0_TRIG_CNTL, 0); 1917 PUT32(sc, RADEON_CAP1_TRIG_CNTL, 0); 1918 PUT32(sc, RADEON_SURFACE_CNTL, 0); 1919 1920 for (i = 0; i < dp->rd_ncrtcs; i++) 1921 radeonfb_setcrtc(dp, i); 1922 1923 /* activate the display */ 1924 radeonfb_blank(dp, 0); 1925 } 1926 1927 void 1928 radeonfb_setcrtc(struct radeonfb_display *dp, int index) 1929 { 1930 int crtc; 1931 struct videomode *mode; 1932 struct radeonfb_softc *sc; 1933 struct radeonfb_crtc *cp; 1934 uint32_t v; 1935 uint32_t gencntl; 1936 uint32_t htotaldisp; 1937 uint32_t hsyncstrt; 1938 uint32_t vtotaldisp; 1939 uint32_t vsyncstrt; 1940 uint32_t fphsyncstrt; 1941 uint32_t fpvsyncstrt; 1942 uint32_t fphtotaldisp; 1943 uint32_t fpvtotaldisp; 1944 uint32_t pitch; 1945 1946 sc = dp->rd_softc; 1947 cp = &dp->rd_crtcs[index]; 1948 crtc = cp->rc_number; 1949 mode = &cp->rc_videomode; 1950 1951 #if 1 1952 pitch = (((dp->rd_virtx * dp->rd_bpp) + ((dp->rd_bpp * 8) - 1)) / 1953 (dp->rd_bpp * 8)); 1954 #else 1955 pitch = (((sc->sc_maxx * sc->sc_maxbpp) + ((sc->sc_maxbpp * 8) - 1)) / 1956 (sc->sc_maxbpp * 8)); 1957 #endif 1958 1959 switch (crtc) { 1960 case 0: 1961 gencntl = RADEON_CRTC_GEN_CNTL; 1962 htotaldisp = RADEON_CRTC_H_TOTAL_DISP; 1963 hsyncstrt = RADEON_CRTC_H_SYNC_STRT_WID; 1964 vtotaldisp = RADEON_CRTC_V_TOTAL_DISP; 1965 vsyncstrt = RADEON_CRTC_V_SYNC_STRT_WID; 1966 fpvsyncstrt = RADEON_FP_V_SYNC_STRT_WID; 1967 fphsyncstrt = RADEON_FP_H_SYNC_STRT_WID; 1968 fpvtotaldisp = RADEON_FP_CRTC_V_TOTAL_DISP; 1969 fphtotaldisp = RADEON_FP_CRTC_H_TOTAL_DISP; 1970 break; 1971 case 1: 1972 gencntl = RADEON_CRTC2_GEN_CNTL; 1973 htotaldisp = RADEON_CRTC2_H_TOTAL_DISP; 1974 hsyncstrt = RADEON_CRTC2_H_SYNC_STRT_WID; 1975 vtotaldisp = RADEON_CRTC2_V_TOTAL_DISP; 1976 vsyncstrt = RADEON_CRTC2_V_SYNC_STRT_WID; 1977 fpvsyncstrt = RADEON_FP_V2_SYNC_STRT_WID; 1978 fphsyncstrt = RADEON_FP_H2_SYNC_STRT_WID; 1979 fpvtotaldisp = RADEON_FP_CRTC2_V_TOTAL_DISP; 1980 fphtotaldisp = RADEON_FP_CRTC2_H_TOTAL_DISP; 1981 break; 1982 default: 1983 panic("Bad CRTC!"); 1984 break; 1985 } 1986 1987 /* 1988 * CRTC_GEN_CNTL - depth, accelerator mode, etc. 1989 */ 1990 /* only bother with 32bpp and 8bpp */ 1991 v = dp->rd_format << RADEON_CRTC_PIX_WIDTH_SHIFT; 1992 1993 if (crtc == 1) { 1994 v |= RADEON_CRTC2_CRT2_ON | RADEON_CRTC2_EN; 1995 } else { 1996 v |= RADEON_CRTC_EXT_DISP_EN | RADEON_CRTC_EN; 1997 } 1998 1999 if (mode->flags & VID_DBLSCAN) 2000 v |= RADEON_CRTC2_DBL_SCAN_EN; 2001 2002 if (mode->flags & VID_INTERLACE) 2003 v |= RADEON_CRTC2_INTERLACE_EN; 2004 2005 if (mode->flags & VID_CSYNC) { 2006 v |= RADEON_CRTC2_CSYNC_EN; 2007 if (crtc == 1) 2008 v |= RADEON_CRTC2_VSYNC_TRISTAT; 2009 } 2010 2011 PUT32(sc, gencntl, v); 2012 DPRINTF(("CRTC%s_GEN_CNTL = %08x\n", crtc ? "2" : "", v)); 2013 2014 /* 2015 * CRTC_EXT_CNTL - preserve disable flags, set ATI linear and EXT_CNT 2016 */ 2017 v = GET32(sc, RADEON_CRTC_EXT_CNTL); 2018 if (crtc == 0) { 2019 v &= (RADEON_CRTC_VSYNC_DIS | RADEON_CRTC_HSYNC_DIS | 2020 RADEON_CRTC_DISPLAY_DIS); 2021 v |= RADEON_XCRT_CNT_EN | RADEON_VGA_ATI_LINEAR; 2022 if (mode->flags & VID_CSYNC) 2023 v |= RADEON_CRTC_VSYNC_TRISTAT; 2024 } 2025 /* unconditional turn on CRT, in case first CRTC is DFP */ 2026 v |= RADEON_CRTC_CRT_ON; 2027 PUT32(sc, RADEON_CRTC_EXT_CNTL, v); 2028 PRINTREG(RADEON_CRTC_EXT_CNTL); 2029 2030 /* 2031 * H_TOTAL_DISP 2032 */ 2033 v = ((mode->hdisplay / 8) - 1) << 16; 2034 v |= (mode->htotal / 8) - 1; 2035 PUT32(sc, htotaldisp, v); 2036 DPRINTF(("CRTC%s_H_TOTAL_DISP = %08x\n", crtc ? "2" : "", v)); 2037 PUT32(sc, fphtotaldisp, v); 2038 DPRINTF(("FP_H%s_TOTAL_DISP = %08x\n", crtc ? "2" : "", v)); 2039 2040 /* 2041 * H_SYNC_STRT_WID 2042 */ 2043 v = (((mode->hsync_end - mode->hsync_start) / 8) << 16); 2044 v |= mode->hsync_start; 2045 if (mode->flags & VID_NHSYNC) 2046 v |= RADEON_CRTC_H_SYNC_POL; 2047 PUT32(sc, hsyncstrt, v); 2048 DPRINTF(("CRTC%s_H_SYNC_STRT_WID = %08x\n", crtc ? "2" : "", v)); 2049 PUT32(sc, fphsyncstrt, v); 2050 DPRINTF(("FP_H%s_SYNC_STRT_WID = %08x\n", crtc ? "2" : "", v)); 2051 2052 /* 2053 * V_TOTAL_DISP 2054 */ 2055 v = ((mode->vdisplay - 1) << 16); 2056 v |= (mode->vtotal - 1); 2057 PUT32(sc, vtotaldisp, v); 2058 DPRINTF(("CRTC%s_V_TOTAL_DISP = %08x\n", crtc ? "2" : "", v)); 2059 PUT32(sc, fpvtotaldisp, v); 2060 DPRINTF(("FP_V%s_TOTAL_DISP = %08x\n", crtc ? "2" : "", v)); 2061 2062 /* 2063 * V_SYNC_STRT_WID 2064 */ 2065 v = ((mode->vsync_end - mode->vsync_start) << 16); 2066 v |= (mode->vsync_start - 1); 2067 if (mode->flags & VID_NVSYNC) 2068 v |= RADEON_CRTC_V_SYNC_POL; 2069 PUT32(sc, vsyncstrt, v); 2070 DPRINTF(("CRTC%s_V_SYNC_STRT_WID = %08x\n", crtc ? "2" : "", v)); 2071 PUT32(sc, fpvsyncstrt, v); 2072 DPRINTF(("FP_V%s_SYNC_STRT_WID = %08x\n", crtc ? "2" : "", v)); 2073 2074 radeonfb_program_vclk(sc, mode->dot_clock, crtc); 2075 2076 switch (crtc) { 2077 case 0: 2078 PUT32(sc, RADEON_CRTC_OFFSET, 0); 2079 PUT32(sc, RADEON_CRTC_OFFSET_CNTL, 0); 2080 PUT32(sc, RADEON_CRTC_PITCH, pitch); 2081 CLR32(sc, RADEON_DISP_MERGE_CNTL, RADEON_DISP_RGB_OFFSET_EN); 2082 2083 CLR32(sc, RADEON_CRTC_EXT_CNTL, 2084 RADEON_CRTC_VSYNC_DIS | RADEON_CRTC_HSYNC_DIS | 2085 RADEON_CRTC_DISPLAY_DIS /* | RADEON_CRTC_DISP_REQ_EN_B */); 2086 CLR32(sc, RADEON_CRTC_GEN_CNTL, RADEON_CRTC_DISP_REQ_EN_B); 2087 PRINTREG(RADEON_CRTC_EXT_CNTL); 2088 PRINTREG(RADEON_CRTC_GEN_CNTL); 2089 PRINTREG(RADEON_CLOCK_CNTL_INDEX); 2090 break; 2091 2092 case 1: 2093 PUT32(sc, RADEON_CRTC2_OFFSET, 0); 2094 PUT32(sc, RADEON_CRTC2_OFFSET_CNTL, 0); 2095 PUT32(sc, RADEON_CRTC2_PITCH, pitch); 2096 CLR32(sc, RADEON_DISP2_MERGE_CNTL, RADEON_DISP2_RGB_OFFSET_EN); 2097 CLR32(sc, RADEON_CRTC2_GEN_CNTL, 2098 RADEON_CRTC2_VSYNC_DIS | 2099 RADEON_CRTC2_HSYNC_DIS | 2100 RADEON_CRTC2_DISP_DIS | RADEON_CRTC2_DISP_REQ_EN_B); 2101 PRINTREG(RADEON_CRTC2_GEN_CNTL); 2102 break; 2103 } 2104 } 2105 2106 int 2107 radeonfb_isblank(struct radeonfb_display *dp) 2108 { 2109 uint32_t reg, mask; 2110 2111 if (dp->rd_crtcs[0].rc_number) { 2112 reg = RADEON_CRTC2_GEN_CNTL; 2113 mask = RADEON_CRTC2_DISP_DIS; 2114 } else { 2115 reg = RADEON_CRTC_EXT_CNTL; 2116 mask = RADEON_CRTC_DISPLAY_DIS; 2117 } 2118 return ((GET32(dp->rd_softc, reg) & mask) ? 1 : 0); 2119 } 2120 2121 void 2122 radeonfb_blank(struct radeonfb_display *dp, int blank) 2123 { 2124 struct radeonfb_softc *sc = dp->rd_softc; 2125 uint32_t reg, mask; 2126 uint32_t fpreg, fpval; 2127 int i; 2128 2129 for (i = 0; i < dp->rd_ncrtcs; i++) { 2130 2131 if (dp->rd_crtcs[i].rc_number) { 2132 reg = RADEON_CRTC2_GEN_CNTL; 2133 mask = RADEON_CRTC2_DISP_DIS; 2134 fpreg = RADEON_FP2_GEN_CNTL; 2135 fpval = RADEON_FP2_ON; 2136 } else { 2137 reg = RADEON_CRTC_EXT_CNTL; 2138 mask = RADEON_CRTC_DISPLAY_DIS; 2139 fpreg = RADEON_FP_GEN_CNTL; 2140 fpval = RADEON_FP_FPON; 2141 } 2142 2143 if (blank) { 2144 SET32(sc, reg, mask); 2145 CLR32(sc, fpreg, fpval); 2146 } else { 2147 CLR32(sc, reg, mask); 2148 SET32(sc, fpreg, fpval); 2149 } 2150 } 2151 PRINTREG(RADEON_FP_GEN_CNTL); 2152 PRINTREG(RADEON_FP2_GEN_CNTL); 2153 } 2154 2155 void 2156 radeonfb_init_screen(void *cookie, struct vcons_screen *scr, int existing, 2157 long *defattr) 2158 { 2159 struct radeonfb_display *dp = cookie; 2160 struct rasops_info *ri = &scr->scr_ri; 2161 2162 /* initialize font subsystem */ 2163 wsfont_init(); 2164 2165 DPRINTF(("init screen called, existing %d\n", existing)); 2166 2167 ri->ri_depth = dp->rd_bpp; 2168 ri->ri_width = dp->rd_virtx; 2169 ri->ri_height = dp->rd_virty; 2170 ri->ri_stride = dp->rd_stride; 2171 ri->ri_flg = RI_CENTER; 2172 if (ri->ri_depth == 32) { 2173 ri->ri_flg |= RI_ENABLE_ALPHA; 2174 } 2175 ri->ri_bits = (void *)dp->rd_fbptr; 2176 2177 #ifdef VCONS_DRAW_INTR 2178 scr->scr_flags |= VCONS_DONT_READ; 2179 #endif 2180 2181 /* this is rgb in "big-endian order..." */ 2182 ri->ri_rnum = 8; 2183 ri->ri_gnum = 8; 2184 ri->ri_bnum = 8; 2185 ri->ri_rpos = 16; 2186 ri->ri_gpos = 8; 2187 ri->ri_bpos = 0; 2188 2189 if (existing) { 2190 ri->ri_flg |= RI_CLEAR; 2191 2192 /* start a modeswitch now */ 2193 radeonfb_modeswitch(dp); 2194 } 2195 2196 /* 2197 * XXX: font selection should be based on properties, with some 2198 * normal/reasonable default. 2199 */ 2200 2201 /* initialize and look for an initial font */ 2202 rasops_init(ri, 0, 0); 2203 ri->ri_caps = WSSCREEN_WSCOLORS; 2204 2205 rasops_reconfig(ri, dp->rd_virty / ri->ri_font->fontheight, 2206 dp->rd_virtx / ri->ri_font->fontwidth); 2207 2208 /* enable acceleration */ 2209 dp->rd_putchar = ri->ri_ops.putchar; 2210 ri->ri_ops.copyrows = radeonfb_copyrows; 2211 ri->ri_ops.copycols = radeonfb_copycols; 2212 ri->ri_ops.eraserows = radeonfb_eraserows; 2213 ri->ri_ops.erasecols = radeonfb_erasecols; 2214 /* pick a putchar method based on font and Radeon model */ 2215 if (ri->ri_font->stride < ri->ri_font->fontwidth) { 2216 /* got a bitmap font */ 2217 if (IS_R300(dp->rd_softc)) { 2218 /* 2219 * radeonfb_putchar() doesn't work right on some R3xx 2220 * so we use software drawing here, the wrapper just 2221 * makes sure the engine is idle before scribbling 2222 * into vram 2223 */ 2224 ri->ri_ops.putchar = radeonfb_putchar_wrapper; 2225 } else { 2226 ri->ri_ops.putchar = radeonfb_putchar; 2227 } 2228 } else { 2229 /* got an alpha font */ 2230 ri->ri_ops.putchar = radeonfb_putchar_aa32; 2231 } 2232 ri->ri_ops.cursor = radeonfb_cursor; 2233 } 2234 2235 void 2236 radeonfb_set_fbloc(struct radeonfb_softc *sc) 2237 { 2238 uint32_t gen, ext, gen2 = 0; 2239 uint32_t agploc, aperbase, apersize, mcfbloc; 2240 2241 gen = GET32(sc, RADEON_CRTC_GEN_CNTL); 2242 ext = GET32(sc, RADEON_CRTC_EXT_CNTL); 2243 agploc = GET32(sc, RADEON_MC_AGP_LOCATION); 2244 aperbase = GET32(sc, RADEON_CONFIG_APER_0_BASE); 2245 apersize = GET32(sc, RADEON_CONFIG_APER_SIZE); 2246 2247 PUT32(sc, RADEON_CRTC_GEN_CNTL, gen | RADEON_CRTC_DISP_REQ_EN_B); 2248 PUT32(sc, RADEON_CRTC_EXT_CNTL, ext | RADEON_CRTC_DISPLAY_DIS); 2249 //PUT32(sc, RADEON_CRTC_GEN_CNTL, gen | RADEON_CRTC_DISPLAY_DIS); 2250 //PUT32(sc, RADEON_CRTC_EXT_CNTL, ext | RADEON_CRTC_DISP_REQ_EN_B); 2251 2252 if (HAS_CRTC2(sc)) { 2253 gen2 = GET32(sc, RADEON_CRTC2_GEN_CNTL); 2254 PUT32(sc, RADEON_CRTC2_GEN_CNTL, 2255 gen2 | RADEON_CRTC2_DISP_REQ_EN_B); 2256 } 2257 2258 delay(100000); 2259 2260 mcfbloc = (aperbase >> 16) | 2261 ((aperbase + (apersize - 1)) & 0xffff0000); 2262 2263 sc->sc_aperbase = (mcfbloc & 0xffff) << 16; 2264 sc->sc_memsz = apersize; 2265 2266 if (((agploc & 0xffff) << 16) != 2267 ((mcfbloc & 0xffff0000U) + 0x10000)) { 2268 agploc = mcfbloc & 0xffff0000U; 2269 agploc |= ((agploc + 0x10000) >> 16); 2270 } 2271 2272 PUT32(sc, RADEON_HOST_PATH_CNTL, 0); 2273 2274 PUT32(sc, RADEON_MC_FB_LOCATION, mcfbloc); 2275 PUT32(sc, RADEON_MC_AGP_LOCATION, agploc); 2276 2277 DPRINTF(("aperbase = %u\n", aperbase)); 2278 PRINTREG(RADEON_MC_FB_LOCATION); 2279 PRINTREG(RADEON_MC_AGP_LOCATION); 2280 2281 PUT32(sc, RADEON_DISPLAY_BASE_ADDR, sc->sc_aperbase); 2282 2283 if (HAS_CRTC2(sc)) 2284 PUT32(sc, RADEON_DISPLAY2_BASE_ADDR, sc->sc_aperbase); 2285 2286 PUT32(sc, RADEON_OV0_BASE_ADDR, sc->sc_aperbase); 2287 2288 #if 0 2289 /* XXX: what is this AGP garbage? :-) */ 2290 PUT32(sc, RADEON_AGP_CNTL, 0x00100000); 2291 #endif 2292 2293 delay(100000); 2294 2295 PUT32(sc, RADEON_CRTC_GEN_CNTL, gen); 2296 PUT32(sc, RADEON_CRTC_EXT_CNTL, ext); 2297 2298 if (HAS_CRTC2(sc)) 2299 PUT32(sc, RADEON_CRTC2_GEN_CNTL, gen2); 2300 } 2301 2302 void 2303 radeonfb_init_misc(struct radeonfb_softc *sc) 2304 { 2305 PUT32(sc, RADEON_BUS_CNTL, 2306 RADEON_BUS_MASTER_DIS | 2307 RADEON_BUS_PREFETCH_MODE_ACT | 2308 RADEON_BUS_PCI_READ_RETRY_EN | 2309 RADEON_BUS_PCI_WRT_RETRY_EN | 2310 (3 << RADEON_BUS_RETRY_WS_SHIFT) | 2311 RADEON_BUS_MSTR_RD_MULT | 2312 RADEON_BUS_MSTR_RD_LINE | 2313 RADEON_BUS_RD_DISCARD_EN | 2314 RADEON_BUS_MSTR_DISCONNECT_EN | 2315 RADEON_BUS_READ_BURST); 2316 2317 PUT32(sc, RADEON_BUS_CNTL1, 0xf0); 2318 /* PUT32(sc, RADEON_SEPROM_CNTL1, 0x09ff0000); */ 2319 PUT32(sc, RADEON_FCP_CNTL, RADEON_FCP0_SRC_GND); 2320 PUT32(sc, RADEON_RBBM_CNTL, 2321 (3 << RADEON_RB_SETTLE_SHIFT) | 2322 (4 << RADEON_ABORTCLKS_HI_SHIFT) | 2323 (4 << RADEON_ABORTCLKS_CP_SHIFT) | 2324 (4 << RADEON_ABORTCLKS_CFIFO_SHIFT)); 2325 2326 /* XXX: figure out what these mean! */ 2327 PUT32(sc, RADEON_AGP_CNTL, 0x00100000); 2328 PUT32(sc, RADEON_HOST_PATH_CNTL, 0); 2329 //PUT32(sc, RADEON_DISP_MISC_CNTL, 0x5bb00400); 2330 2331 PUT32(sc, RADEON_GEN_INT_CNTL, 0); 2332 PUT32(sc, RADEON_GEN_INT_STATUS, GET32(sc, RADEON_GEN_INT_STATUS)); 2333 } 2334 2335 /* 2336 * This loads a linear color map for true color. 2337 */ 2338 void 2339 radeonfb_init_palette(struct radeonfb_softc *sc, int crtc) 2340 { 2341 int i; 2342 uint32_t vclk; 2343 2344 #define DAC_WIDTH ((1 << 10) - 1) 2345 #define CLUT_WIDTH ((1 << 8) - 1) 2346 #define CLUT_COLOR(i) ((i * DAC_WIDTH * 2 / CLUT_WIDTH + 1) / 2) 2347 2348 vclk = GETPLL(sc, RADEON_VCLK_ECP_CNTL); 2349 PUTPLL(sc, RADEON_VCLK_ECP_CNTL, vclk & ~RADEON_PIXCLK_DAC_ALWAYS_ONb); 2350 2351 if (crtc) 2352 SET32(sc, RADEON_DAC_CNTL2, RADEON_DAC2_PALETTE_ACC_CTL); 2353 else 2354 CLR32(sc, RADEON_DAC_CNTL2, RADEON_DAC2_PALETTE_ACC_CTL); 2355 2356 PUT32(sc, RADEON_PALETTE_INDEX, 0); 2357 if (sc->sc_displays[crtc].rd_bpp == 0) 2358 sc->sc_displays[crtc].rd_bpp = RADEONFB_DEFAULT_DEPTH; 2359 2360 if (sc->sc_displays[crtc].rd_bpp == 8) { 2361 /* ANSI palette */ 2362 int j = 0; 2363 2364 for (i = 0; i <= CLUT_WIDTH; ++i) { 2365 PUT32(sc, RADEON_PALETTE_30_DATA, 2366 (rasops_cmap[j] << 22) | 2367 (rasops_cmap[j + 1] << 12) | 2368 (rasops_cmap[j + 2] << 2)); 2369 j += 3; 2370 } 2371 } else { 2372 /* linear ramp */ 2373 for (i = 0; i <= CLUT_WIDTH; ++i) { 2374 PUT32(sc, RADEON_PALETTE_30_DATA, 2375 (CLUT_COLOR(i) << 10) | 2376 (CLUT_COLOR(i) << 20) | 2377 (CLUT_COLOR(i))); 2378 } 2379 } 2380 2381 CLR32(sc, RADEON_DAC_CNTL2, RADEON_DAC2_PALETTE_ACC_CTL); 2382 PRINTREG(RADEON_DAC_CNTL2); 2383 2384 PUTPLL(sc, RADEON_VCLK_ECP_CNTL, vclk); 2385 } 2386 2387 /* 2388 * Bugs in some R300 hardware requires this when accessing CLOCK_CNTL_INDEX. 2389 */ 2390 void 2391 radeonfb_r300cg_workaround(struct radeonfb_softc *sc) 2392 { 2393 uint32_t tmp, save; 2394 2395 save = GET32(sc, RADEON_CLOCK_CNTL_INDEX); 2396 tmp = save & ~(0x3f | RADEON_PLL_WR_EN); 2397 PUT32(sc, RADEON_CLOCK_CNTL_INDEX, tmp); 2398 tmp = GET32(sc, RADEON_CLOCK_CNTL_DATA); 2399 PUT32(sc, RADEON_CLOCK_CNTL_INDEX, save); 2400 } 2401 2402 /* 2403 * Acceleration entry points. 2404 */ 2405 2406 /* this one draws characters using bitmap fonts */ 2407 static void 2408 radeonfb_putchar(void *cookie, int row, int col, u_int c, long attr) 2409 { 2410 struct rasops_info *ri = cookie; 2411 struct vcons_screen *scr = ri->ri_hw; 2412 struct radeonfb_display *dp = scr->scr_cookie; 2413 struct radeonfb_softc *sc = dp->rd_softc; 2414 struct wsdisplay_font *font = PICK_FONT(ri, c); 2415 uint32_t w, h; 2416 int xd, yd, offset, i; 2417 uint32_t bg, fg, gmc; 2418 uint32_t reg; 2419 uint8_t *data8; 2420 uint16_t *data16; 2421 void *data; 2422 2423 if (dp->rd_wsmode != WSDISPLAYIO_MODE_EMUL) 2424 return; 2425 2426 if (!CHAR_IN_FONT(c, font)) 2427 return; 2428 2429 w = font->fontwidth; 2430 h = font->fontheight; 2431 2432 bg = ri->ri_devcmap[(attr >> 16) & 0xf]; 2433 fg = ri->ri_devcmap[(attr >> 24) & 0xf]; 2434 2435 xd = ri->ri_xorigin + col * w; 2436 yd = ri->ri_yorigin + row * h; 2437 2438 if (c == 0x20) { 2439 radeonfb_rectfill(dp, xd, yd, w, h, bg); 2440 return; 2441 } 2442 data = WSFONT_GLYPH(c, font); 2443 2444 gmc = dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT; 2445 2446 radeonfb_wait_fifo(sc, 9); 2447 2448 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 2449 RADEON_GMC_BRUSH_NONE | 2450 RADEON_GMC_SRC_DATATYPE_MONO_FG_BG | 2451 RADEON_GMC_DST_CLIPPING | 2452 RADEON_ROP3_S | 2453 RADEON_DP_SRC_SOURCE_HOST_DATA | 2454 RADEON_GMC_CLR_CMP_CNTL_DIS | 2455 RADEON_GMC_WR_MSK_DIS | 2456 gmc); 2457 2458 PUT32(sc, RADEON_SC_LEFT, xd); 2459 PUT32(sc, RADEON_SC_RIGHT, xd + w); 2460 PUT32(sc, RADEON_DP_SRC_FRGD_CLR, fg); 2461 PUT32(sc, RADEON_DP_SRC_BKGD_CLR, bg); 2462 PUT32(sc, RADEON_DP_CNTL, 2463 RADEON_DST_X_LEFT_TO_RIGHT | 2464 RADEON_DST_Y_TOP_TO_BOTTOM); 2465 2466 PUT32(sc, RADEON_SRC_X_Y, 0); 2467 offset = 32 - (font->stride << 3); 2468 PUT32(sc, RADEON_DST_X_Y, ((xd - offset) << 16) | yd); 2469 PUT32(sc, RADEON_DST_WIDTH_HEIGHT, (32 << 16) | h); 2470 2471 radeonfb_wait_fifo(sc, h); 2472 switch (font->stride) { 2473 case 1: { 2474 data8 = data; 2475 for (i = 0; i < h; i++) { 2476 reg = *data8; 2477 bus_space_write_stream_4(sc->sc_regt, 2478 sc->sc_regh, RADEON_HOST_DATA0, reg); 2479 data8++; 2480 } 2481 break; 2482 } 2483 case 2: { 2484 data16 = data; 2485 for (i = 0; i < h; i++) { 2486 reg = *data16; 2487 bus_space_write_stream_4(sc->sc_regt, 2488 sc->sc_regh, RADEON_HOST_DATA0, reg); 2489 data16++; 2490 } 2491 break; 2492 } 2493 } 2494 } 2495 2496 /* ... while this one is for anti-aliased ones */ 2497 static void 2498 radeonfb_putchar_aa32(void *cookie, int row, int col, u_int c, long attr) 2499 { 2500 struct rasops_info *ri = cookie; 2501 struct vcons_screen *scr = ri->ri_hw; 2502 struct radeonfb_display *dp = scr->scr_cookie; 2503 struct radeonfb_softc *sc = dp->rd_softc; 2504 struct wsdisplay_font *font = PICK_FONT(ri, c); 2505 uint32_t bg, fg, gmc; 2506 uint8_t *data; 2507 int w, h, xd, yd; 2508 int i, r, g, b, aval; 2509 int rf, gf, bf, rb, gb, bb; 2510 uint32_t pixel; 2511 int rv; 2512 2513 if (dp->rd_wsmode != WSDISPLAYIO_MODE_EMUL) 2514 return; 2515 2516 if (!CHAR_IN_FONT(c, font)) 2517 return; 2518 2519 w = font->fontwidth; 2520 h = font->fontheight; 2521 2522 bg = ri->ri_devcmap[(attr >> 16) & 0xf]; 2523 fg = ri->ri_devcmap[(attr >> 24) & 0xf]; 2524 2525 xd = ri->ri_xorigin + col * w; 2526 yd = ri->ri_yorigin + row * h; 2527 2528 if (c == 0x20) { 2529 radeonfb_rectfill(dp, xd, yd, w, h, bg); 2530 return; 2531 } 2532 rv = glyphcache_try(&dp->rd_gc, c, xd, yd, attr); 2533 if (rv == GC_OK) 2534 return; 2535 2536 data = WSFONT_GLYPH(c, font); 2537 2538 gmc = dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT; 2539 2540 radeonfb_wait_fifo(sc, 5); 2541 2542 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 2543 RADEON_GMC_BRUSH_NONE | 2544 RADEON_GMC_SRC_DATATYPE_COLOR | 2545 RADEON_ROP3_S | 2546 RADEON_DP_SRC_SOURCE_HOST_DATA | 2547 RADEON_GMC_CLR_CMP_CNTL_DIS | 2548 RADEON_GMC_WR_MSK_DIS | 2549 gmc); 2550 2551 PUT32(sc, RADEON_DP_CNTL, 2552 RADEON_DST_X_LEFT_TO_RIGHT | 2553 RADEON_DST_Y_TOP_TO_BOTTOM); 2554 2555 PUT32(sc, RADEON_SRC_X_Y, 0); 2556 PUT32(sc, RADEON_DST_X_Y, (xd << 16) | yd); 2557 PUT32(sc, RADEON_DST_WIDTH_HEIGHT, (w << 16) | h); 2558 2559 rf = (fg >> 16) & 0xff; 2560 rb = (bg >> 16) & 0xff; 2561 gf = (fg >> 8) & 0xff; 2562 gb = (bg >> 8) & 0xff; 2563 bf = fg & 0xff; 2564 bb = bg & 0xff; 2565 2566 /* 2567 * I doubt we can upload data faster than even the slowest Radeon 2568 * could process them, especially when doing the alpha blending stuff 2569 * along the way, so just make sure there's some room in the FIFO and 2570 * then hammer away 2571 * As it turns out we can, so make periodic stops to let the FIFO 2572 * drain. 2573 */ 2574 radeonfb_wait_fifo(sc, 20); 2575 for (i = 0; i < ri->ri_fontscale; i++) { 2576 aval = *data; 2577 data++; 2578 if (aval == 0) { 2579 pixel = bg; 2580 } else if (aval == 255) { 2581 pixel = fg; 2582 } else { 2583 r = aval * rf + (255 - aval) * rb; 2584 g = aval * gf + (255 - aval) * gb; 2585 b = aval * bf + (255 - aval) * bb; 2586 pixel = (r & 0xff00) << 8 | 2587 (g & 0xff00) | 2588 (b & 0xff00) >> 8; 2589 } 2590 if (i & 16) 2591 radeonfb_wait_fifo(sc, 20); 2592 PUT32(sc, RADEON_HOST_DATA0, pixel); 2593 } 2594 if (rv == GC_ADD) 2595 glyphcache_add(&dp->rd_gc, c, xd, yd); 2596 } 2597 2598 /* 2599 * wrapper for software character drawing 2600 * just sync the engine and call rasops*_putchar() 2601 */ 2602 2603 static void 2604 radeonfb_putchar_wrapper(void *cookie, int row, int col, u_int c, long attr) 2605 { 2606 struct rasops_info *ri = cookie; 2607 struct vcons_screen *scr = ri->ri_hw; 2608 struct radeonfb_display *dp = scr->scr_cookie; 2609 2610 radeonfb_engine_idle(dp->rd_softc); 2611 dp->rd_putchar(ri, row, col, c, attr); 2612 } 2613 2614 static void 2615 radeonfb_eraserows(void *cookie, int row, int nrows, long fillattr) 2616 { 2617 struct rasops_info *ri = cookie; 2618 struct vcons_screen *scr = ri->ri_hw; 2619 struct radeonfb_display *dp = scr->scr_cookie; 2620 uint32_t x, y, w, h, fg, bg, ul; 2621 2622 /* XXX: check for full emulation mode? */ 2623 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 2624 x = ri->ri_xorigin; 2625 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 2626 w = ri->ri_emuwidth; 2627 h = ri->ri_font->fontheight * nrows; 2628 2629 rasops_unpack_attr(fillattr, &fg, &bg, &ul); 2630 radeonfb_rectfill(dp, x, y, w, h, ri->ri_devcmap[bg & 0xf]); 2631 } 2632 } 2633 2634 static void 2635 radeonfb_copyrows(void *cookie, int srcrow, int dstrow, int nrows) 2636 { 2637 struct rasops_info *ri = cookie; 2638 struct vcons_screen *scr = ri->ri_hw; 2639 struct radeonfb_display *dp = scr->scr_cookie; 2640 uint32_t x, ys, yd, w, h; 2641 2642 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 2643 x = ri->ri_xorigin; 2644 ys = ri->ri_yorigin + ri->ri_font->fontheight * srcrow; 2645 yd = ri->ri_yorigin + ri->ri_font->fontheight * dstrow; 2646 w = ri->ri_emuwidth; 2647 h = ri->ri_font->fontheight * nrows; 2648 radeonfb_bitblt(dp, x, ys, x, yd, w, h, 2649 RADEON_ROP3_S); 2650 } 2651 } 2652 2653 static void 2654 radeonfb_copycols(void *cookie, int row, int srccol, int dstcol, int ncols) 2655 { 2656 struct rasops_info *ri = cookie; 2657 struct vcons_screen *scr = ri->ri_hw; 2658 struct radeonfb_display *dp = scr->scr_cookie; 2659 uint32_t xs, xd, y, w, h; 2660 2661 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 2662 xs = ri->ri_xorigin + ri->ri_font->fontwidth * srccol; 2663 xd = ri->ri_xorigin + ri->ri_font->fontwidth * dstcol; 2664 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 2665 w = ri->ri_font->fontwidth * ncols; 2666 h = ri->ri_font->fontheight; 2667 radeonfb_bitblt(dp, xs, y, xd, y, w, h, 2668 RADEON_ROP3_S); 2669 } 2670 } 2671 2672 static void 2673 radeonfb_erasecols(void *cookie, int row, int startcol, int ncols, 2674 long fillattr) 2675 { 2676 struct rasops_info *ri = cookie; 2677 struct vcons_screen *scr = ri->ri_hw; 2678 struct radeonfb_display *dp = scr->scr_cookie; 2679 uint32_t x, y, w, h, fg, bg, ul; 2680 2681 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 2682 x = ri->ri_xorigin + ri->ri_font->fontwidth * startcol; 2683 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 2684 w = ri->ri_font->fontwidth * ncols; 2685 h = ri->ri_font->fontheight; 2686 2687 rasops_unpack_attr(fillattr, &fg, &bg, &ul); 2688 radeonfb_rectfill(dp, x, y, w, h, ri->ri_devcmap[bg & 0xf]); 2689 } 2690 } 2691 2692 static void 2693 radeonfb_cursor(void *cookie, int on, int row, int col) 2694 { 2695 struct rasops_info *ri = cookie; 2696 struct vcons_screen *scr = ri->ri_hw; 2697 struct radeonfb_display *dp = scr->scr_cookie; 2698 int x, y, wi, he; 2699 2700 wi = ri->ri_font->fontwidth; 2701 he = ri->ri_font->fontheight; 2702 2703 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 2704 x = ri->ri_ccol * wi + ri->ri_xorigin; 2705 y = ri->ri_crow * he + ri->ri_yorigin; 2706 /* first turn off the old cursor */ 2707 if (ri->ri_flg & RI_CURSOR) { 2708 radeonfb_bitblt(dp, x, y, x, y, wi, he, 2709 RADEON_ROP3_Dn); 2710 ri->ri_flg &= ~RI_CURSOR; 2711 } 2712 ri->ri_crow = row; 2713 ri->ri_ccol = col; 2714 /* then (possibly) turn on the new one */ 2715 if (on) { 2716 x = ri->ri_ccol * wi + ri->ri_xorigin; 2717 y = ri->ri_crow * he + ri->ri_yorigin; 2718 radeonfb_bitblt(dp, x, y, x, y, wi, he, 2719 RADEON_ROP3_Dn); 2720 ri->ri_flg |= RI_CURSOR; 2721 } 2722 } else { 2723 scr->scr_ri.ri_crow = row; 2724 scr->scr_ri.ri_ccol = col; 2725 scr->scr_ri.ri_flg &= ~RI_CURSOR; 2726 } 2727 } 2728 2729 /* 2730 * Underlying acceleration support. 2731 */ 2732 2733 static void 2734 radeonfb_rectfill(struct radeonfb_display *dp, int dstx, int dsty, 2735 int width, int height, uint32_t color) 2736 { 2737 struct radeonfb_softc *sc = dp->rd_softc; 2738 uint32_t gmc; 2739 2740 gmc = dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT; 2741 2742 radeonfb_wait_fifo(sc, 6); 2743 2744 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 2745 RADEON_GMC_BRUSH_SOLID_COLOR | 2746 RADEON_GMC_SRC_DATATYPE_COLOR | 2747 RADEON_GMC_CLR_CMP_CNTL_DIS | 2748 RADEON_ROP3_P | gmc); 2749 2750 PUT32(sc, RADEON_DP_BRUSH_FRGD_CLR, color); 2751 PUT32(sc, RADEON_DP_WRITE_MASK, 0xffffffff); 2752 PUT32(sc, RADEON_DP_CNTL, 2753 RADEON_DST_X_LEFT_TO_RIGHT | 2754 RADEON_DST_Y_TOP_TO_BOTTOM); 2755 PUT32(sc, RADEON_DST_Y_X, (dsty << 16) | dstx); 2756 PUT32(sc, RADEON_DST_WIDTH_HEIGHT, (width << 16) | (height)); 2757 2758 } 2759 2760 static void 2761 radeonfb_bitblt(void *cookie, int srcx, int srcy, 2762 int dstx, int dsty, int width, int height, int rop) 2763 { 2764 struct radeonfb_display *dp = cookie; 2765 struct radeonfb_softc *sc = dp->rd_softc; 2766 uint32_t gmc; 2767 uint32_t dir; 2768 2769 if (dsty < srcy) { 2770 dir = RADEON_DST_Y_TOP_TO_BOTTOM; 2771 } else { 2772 srcy += height - 1; 2773 dsty += height - 1; 2774 dir = 0; 2775 } 2776 if (dstx < srcx) { 2777 dir |= RADEON_DST_X_LEFT_TO_RIGHT; 2778 } else { 2779 srcx += width - 1; 2780 dstx += width - 1; 2781 } 2782 2783 gmc = dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT; 2784 2785 radeonfb_wait_fifo(sc, 6); 2786 2787 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 2788 RADEON_GMC_BRUSH_SOLID_COLOR | 2789 RADEON_GMC_SRC_DATATYPE_COLOR | 2790 RADEON_GMC_CLR_CMP_CNTL_DIS | 2791 RADEON_DP_SRC_SOURCE_MEMORY | 2792 rop | gmc); 2793 2794 PUT32(sc, RADEON_DP_WRITE_MASK, 0xffffffff); 2795 PUT32(sc, RADEON_DP_CNTL, dir); 2796 PUT32(sc, RADEON_SRC_Y_X, (srcy << 16) | srcx); 2797 PUT32(sc, RADEON_DST_Y_X, (dsty << 16) | dstx); 2798 PUT32(sc, RADEON_DST_WIDTH_HEIGHT, (width << 16) | (height)); 2799 } 2800 2801 static void 2802 radeonfb_engine_idle(struct radeonfb_softc *sc) 2803 { 2804 2805 radeonfb_wait_fifo(sc, 64); 2806 while ((GET32(sc, RADEON_RBBM_STATUS) & 2807 RADEON_RBBM_ACTIVE) != 0); 2808 radeonfb_engine_flush(sc); 2809 } 2810 2811 static void 2812 radeonfb_wait_fifo(struct radeonfb_softc *sc, int n) 2813 { 2814 int i; 2815 2816 for (i = RADEON_TIMEOUT; i; i--) { 2817 if ((GET32(sc, RADEON_RBBM_STATUS) & 2818 RADEON_RBBM_FIFOCNT_MASK) >= n) 2819 return; 2820 } 2821 #ifdef DIAGNOSTIC 2822 if (!i) 2823 printf("%s: timed out waiting for fifo (%x)\n", 2824 XNAME(sc), GET32(sc, RADEON_RBBM_STATUS)); 2825 #endif 2826 } 2827 2828 static void 2829 radeonfb_engine_flush(struct radeonfb_softc *sc) 2830 { 2831 int i = 0; 2832 2833 if (IS_R300(sc)) { 2834 SET32(sc, R300_DSTCACHE_CTLSTAT, R300_RB2D_DC_FLUSH_ALL); 2835 while (GET32(sc, R300_DSTCACHE_CTLSTAT) & R300_RB2D_DC_BUSY) { 2836 i++; 2837 } 2838 } else { 2839 SET32(sc, RADEON_RB2D_DSTCACHE_CTLSTAT, 2840 RADEON_RB2D_DC_FLUSH_ALL); 2841 while (GET32(sc, RADEON_RB2D_DSTCACHE_CTLSTAT) & 2842 RADEON_RB2D_DC_BUSY) { 2843 i++; 2844 } 2845 } 2846 #ifdef DIAGNOSTIC 2847 if (i > RADEON_TIMEOUT) 2848 printf("%s: engine flush timed out!\n", XNAME(sc)); 2849 #endif 2850 } 2851 2852 static inline void 2853 radeonfb_unclip(struct radeonfb_softc *sc) 2854 { 2855 2856 radeonfb_wait_fifo(sc, 2); 2857 PUT32(sc, RADEON_SC_TOP_LEFT, 0); 2858 PUT32(sc, RADEON_SC_BOTTOM_RIGHT, 0x1fff1fff); 2859 } 2860 2861 static void 2862 radeonfb_engine_init(struct radeonfb_display *dp) 2863 { 2864 struct radeonfb_softc *sc = dp->rd_softc; 2865 uint32_t pitch; 2866 volatile uint32_t junk; 2867 2868 /* no 3D */ 2869 PUT32(sc, RADEON_RB3D_CNTL, 0); 2870 2871 radeonfb_engine_reset(sc); 2872 pitch = ((dp->rd_virtx * (dp->rd_bpp / 8) + 0x3f)) >> 6; 2873 2874 radeonfb_wait_fifo(sc, 1); 2875 if (!IS_R300(sc)) 2876 PUT32(sc, RADEON_RB2D_DSTCACHE_MODE, 0); 2877 2878 radeonfb_wait_fifo(sc, 3); 2879 PUT32(sc, RADEON_DEFAULT_PITCH_OFFSET, 2880 (pitch << 22) | (sc->sc_aperbase >> 10)); 2881 2882 2883 PUT32(sc, RADEON_DST_PITCH_OFFSET, 2884 (pitch << 22) | (sc->sc_aperbase >> 10)); 2885 PUT32(sc, RADEON_SRC_PITCH_OFFSET, 2886 (pitch << 22) | (sc->sc_aperbase >> 10)); 2887 2888 radeonfb_wait_fifo(sc, 1); 2889 #if _BYTE_ORDER == _BIG_ENDIAN 2890 SET32(sc, RADEON_DP_DATATYPE, RADEON_HOST_BIG_ENDIAN_EN); 2891 #else 2892 CLR32(sc, RADEON_DP_DATATYPE, RADEON_HOST_BIG_ENDIAN_EN); 2893 #endif 2894 junk = GET32(sc, RADEON_DP_DATATYPE); 2895 2896 /* default scissors -- no clipping */ 2897 radeonfb_wait_fifo(sc, 1); 2898 PUT32(sc, RADEON_DEFAULT_SC_BOTTOM_RIGHT, 2899 RADEON_DEFAULT_SC_RIGHT_MAX | RADEON_DEFAULT_SC_BOTTOM_MAX); 2900 2901 radeonfb_wait_fifo(sc, 1); 2902 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 2903 (dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT) | 2904 RADEON_GMC_CLR_CMP_CNTL_DIS | 2905 RADEON_GMC_BRUSH_SOLID_COLOR | 2906 RADEON_GMC_SRC_DATATYPE_COLOR); 2907 2908 radeonfb_wait_fifo(sc, 10); 2909 PUT32(sc, RADEON_DST_LINE_START, 0); 2910 PUT32(sc, RADEON_DST_LINE_END, 0); 2911 PUT32(sc, RADEON_DP_BRUSH_FRGD_CLR, 0xffffffff); 2912 PUT32(sc, RADEON_DP_BRUSH_BKGD_CLR, 0); 2913 PUT32(sc, RADEON_DP_SRC_FRGD_CLR, 0xffffffff); 2914 PUT32(sc, RADEON_DP_SRC_BKGD_CLR, 0); 2915 PUT32(sc, RADEON_DP_WRITE_MASK, 0xffffffff); 2916 PUT32(sc, RADEON_SC_TOP_LEFT, 0); 2917 PUT32(sc, RADEON_SC_BOTTOM_RIGHT, 0x1fff1fff); 2918 PUT32(sc, RADEON_AUX_SC_CNTL, 0); 2919 radeonfb_engine_idle(sc); 2920 } 2921 2922 static void 2923 radeonfb_engine_reset(struct radeonfb_softc *sc) 2924 { 2925 uint32_t hpc, rbbm, mclkcntl, clkindex; 2926 2927 radeonfb_engine_flush(sc); 2928 2929 clkindex = GET32(sc, RADEON_CLOCK_CNTL_INDEX); 2930 if (HAS_R300CG(sc)) 2931 radeonfb_r300cg_workaround(sc); 2932 mclkcntl = GETPLL(sc, RADEON_MCLK_CNTL); 2933 2934 /* 2935 * According to comments in XFree code, resetting the HDP via 2936 * the RBBM_SOFT_RESET can cause bad behavior on some systems. 2937 * So we use HOST_PATH_CNTL instead. 2938 */ 2939 2940 hpc = GET32(sc, RADEON_HOST_PATH_CNTL); 2941 rbbm = GET32(sc, RADEON_RBBM_SOFT_RESET); 2942 if (IS_R300(sc)) { 2943 PUT32(sc, RADEON_RBBM_SOFT_RESET, rbbm | 2944 RADEON_SOFT_RESET_CP | 2945 RADEON_SOFT_RESET_HI | 2946 RADEON_SOFT_RESET_E2); 2947 GET32(sc, RADEON_RBBM_SOFT_RESET); 2948 PUT32(sc, RADEON_RBBM_SOFT_RESET, 0); 2949 /* 2950 * XXX: this bit is not defined in any ATI docs I have, 2951 * nor in the XFree code, but XFree does it. Why? 2952 */ 2953 SET32(sc, RADEON_RB2D_DSTCACHE_MODE, (1<<17)); 2954 } else { 2955 PUT32(sc, RADEON_RBBM_SOFT_RESET, rbbm | 2956 RADEON_SOFT_RESET_CP | 2957 RADEON_SOFT_RESET_SE | 2958 RADEON_SOFT_RESET_RE | 2959 RADEON_SOFT_RESET_PP | 2960 RADEON_SOFT_RESET_E2 | 2961 RADEON_SOFT_RESET_RB); 2962 GET32(sc, RADEON_RBBM_SOFT_RESET); 2963 PUT32(sc, RADEON_RBBM_SOFT_RESET, rbbm & 2964 ~(RADEON_SOFT_RESET_CP | 2965 RADEON_SOFT_RESET_SE | 2966 RADEON_SOFT_RESET_RE | 2967 RADEON_SOFT_RESET_PP | 2968 RADEON_SOFT_RESET_E2 | 2969 RADEON_SOFT_RESET_RB)); 2970 GET32(sc, RADEON_RBBM_SOFT_RESET); 2971 } 2972 2973 PUT32(sc, RADEON_HOST_PATH_CNTL, hpc | RADEON_HDP_SOFT_RESET); 2974 GET32(sc, RADEON_HOST_PATH_CNTL); 2975 PUT32(sc, RADEON_HOST_PATH_CNTL, hpc); 2976 2977 if (IS_R300(sc)) 2978 PUT32(sc, RADEON_RBBM_SOFT_RESET, rbbm); 2979 2980 PUT32(sc, RADEON_CLOCK_CNTL_INDEX, clkindex); 2981 PUTPLL(sc, RADEON_MCLK_CNTL, mclkcntl); 2982 2983 if (HAS_R300CG(sc)) 2984 radeonfb_r300cg_workaround(sc); 2985 } 2986 2987 static int 2988 radeonfb_set_curpos(struct radeonfb_display *dp, struct wsdisplay_curpos *pos) 2989 { 2990 int x, y; 2991 2992 x = pos->x; 2993 y = pos->y; 2994 2995 /* 2996 * This doesn't let a cursor move off the screen. I'm not 2997 * sure if this will have negative effects for e.g. Xinerama. 2998 * I'd guess Xinerama handles it by changing the cursor shape, 2999 * but that needs verification. 3000 */ 3001 if (x >= dp->rd_virtx) 3002 x = dp->rd_virtx - 1; 3003 if (x < 0) 3004 x = 0; 3005 if (y >= dp->rd_virty) 3006 y = dp->rd_virty - 1; 3007 if (y < 0) 3008 y = 0; 3009 3010 dp->rd_cursor.rc_pos.x = x; 3011 dp->rd_cursor.rc_pos.y = y; 3012 3013 radeonfb_cursor_position(dp); 3014 return 0; 3015 } 3016 3017 static int 3018 radeonfb_set_cursor(struct radeonfb_display *dp, struct wsdisplay_cursor *wc) 3019 { 3020 unsigned flags; 3021 3022 uint8_t r[2], g[2], b[2]; 3023 unsigned index, count; 3024 int i, err; 3025 int pitch, size; 3026 struct radeonfb_cursor nc; 3027 3028 flags = wc->which; 3029 3030 /* copy old values */ 3031 nc = dp->rd_cursor; 3032 3033 if (flags & WSDISPLAY_CURSOR_DOCMAP) { 3034 index = wc->cmap.index; 3035 count = wc->cmap.count; 3036 3037 if (index >= 2 || (index + count) > 2) 3038 return EINVAL; 3039 3040 err = copyin(wc->cmap.red, &r[index], count); 3041 if (err) 3042 return err; 3043 err = copyin(wc->cmap.green, &g[index], count); 3044 if (err) 3045 return err; 3046 err = copyin(wc->cmap.blue, &b[index], count); 3047 if (err) 3048 return err; 3049 3050 for (i = index; i < index + count; i++) { 3051 nc.rc_cmap[i] = 3052 (r[i] << 16) + (g[i] << 8) + (b[i] << 0); 3053 } 3054 } 3055 3056 if (flags & WSDISPLAY_CURSOR_DOSHAPE) { 3057 if ((wc->size.x > RADEON_CURSORMAXX) || 3058 (wc->size.y > RADEON_CURSORMAXY)) 3059 return EINVAL; 3060 3061 /* figure bytes per line */ 3062 pitch = (wc->size.x + 7) / 8; 3063 size = pitch * wc->size.y; 3064 3065 /* clear the old cursor and mask */ 3066 memset(nc.rc_image, 0, 512); 3067 memset(nc.rc_mask, 0, 512); 3068 3069 nc.rc_size = wc->size; 3070 3071 if ((err = copyin(wc->image, nc.rc_image, size)) != 0) 3072 return err; 3073 3074 if ((err = copyin(wc->mask, nc.rc_mask, size)) != 0) 3075 return err; 3076 } 3077 3078 if (flags & WSDISPLAY_CURSOR_DOHOT) { 3079 nc.rc_hot = wc->hot; 3080 if (nc.rc_hot.x >= nc.rc_size.x) 3081 nc.rc_hot.x = nc.rc_size.x - 1; 3082 if (nc.rc_hot.y >= nc.rc_size.y) 3083 nc.rc_hot.y = nc.rc_size.y - 1; 3084 } 3085 3086 if (flags & WSDISPLAY_CURSOR_DOPOS) { 3087 nc.rc_pos = wc->pos; 3088 if (nc.rc_pos.x >= dp->rd_virtx) 3089 nc.rc_pos.x = dp->rd_virtx - 1; 3090 #if 0 3091 if (nc.rc_pos.x < 0) 3092 nc.rc_pos.x = 0; 3093 #endif 3094 if (nc.rc_pos.y >= dp->rd_virty) 3095 nc.rc_pos.y = dp->rd_virty - 1; 3096 #if 0 3097 if (nc.rc_pos.y < 0) 3098 nc.rc_pos.y = 0; 3099 #endif 3100 } 3101 if (flags & WSDISPLAY_CURSOR_DOCUR) { 3102 nc.rc_visible = wc->enable; 3103 } 3104 3105 dp->rd_cursor = nc; 3106 radeonfb_cursor_update(dp, wc->which); 3107 3108 return 0; 3109 } 3110 3111 /* 3112 * Change the cursor shape. Call this with the cursor locked to avoid 3113 * flickering/tearing. 3114 */ 3115 static void 3116 radeonfb_cursor_shape(struct radeonfb_display *dp) 3117 { 3118 uint8_t and[512], xor[512]; 3119 int i, j, src, dst, pitch; 3120 const uint8_t *msk = dp->rd_cursor.rc_mask; 3121 const uint8_t *img = dp->rd_cursor.rc_image; 3122 3123 /* 3124 * Radeon cursor data interleaves one line of AND data followed 3125 * by a line of XOR data. (Each line corresponds to a whole hardware 3126 * pitch - i.e. 64 pixels or 8 bytes.) 3127 * 3128 * The cursor is displayed using the following table: 3129 * 3130 * AND XOR Result 3131 * ---------------------- 3132 * 0 0 Cursor color 0 3133 * 0 1 Cursor color 1 3134 * 1 0 Transparent 3135 * 1 1 Complement of background 3136 * 3137 * Our masks are therefore different from what we were passed. 3138 * Passed in, I'm assuming the data represents either color 0 or 1, 3139 * and a mask, so the passed in table looks like: 3140 * 3141 * IMG Mask Result 3142 * ----------------------- 3143 * 0 0 Transparent 3144 * 0 1 Cursor color 0 3145 * 1 0 Transparent 3146 * 1 1 Cursor color 1 3147 * 3148 * IF mask bit == 1, AND = 0, XOR = color. 3149 * IF mask bit == 0, AND = 1, XOR = 0. 3150 * 3151 * hence: AND = ~(mask); XOR = color & ~(mask); 3152 */ 3153 3154 pitch = ((dp->rd_cursor.rc_size.x + 7) / 8); 3155 3156 /* start by assuming all bits are transparent */ 3157 memset(and, 0xff, 512); 3158 memset(xor, 0x00, 512); 3159 3160 src = 0; 3161 dst = 0; 3162 for (i = 0; i < 64; i++) { 3163 for (j = 0; j < 64; j += 8) { 3164 if ((i < dp->rd_cursor.rc_size.y) && 3165 (j < dp->rd_cursor.rc_size.x)) { 3166 3167 /* take care to leave odd bits alone */ 3168 and[dst] &= ~(msk[src]); 3169 xor[dst] = img[src] & msk[src]; 3170 src++; 3171 } 3172 dst++; 3173 } 3174 } 3175 3176 /* copy the image into place */ 3177 for (i = 0; i < 64; i++) { 3178 memcpy((uint8_t *)dp->rd_curptr + (i * 16), 3179 &and[i * 8], 8); 3180 memcpy((uint8_t *)dp->rd_curptr + (i * 16) + 8, 3181 &xor[i * 8], 8); 3182 } 3183 } 3184 3185 static void 3186 radeonfb_cursor_position(struct radeonfb_display *dp) 3187 { 3188 struct radeonfb_softc *sc = dp->rd_softc; 3189 uint32_t offset, hvoff, hvpos; /* registers */ 3190 uint32_t coff; /* cursor offset */ 3191 int i, x, y, xoff, yoff, crtcoff; 3192 3193 /* 3194 * XXX: this also needs to handle pan/scan 3195 */ 3196 for (i = 0; i < dp->rd_ncrtcs; i++) { 3197 3198 struct radeonfb_crtc *rcp = &dp->rd_crtcs[i]; 3199 3200 if (rcp->rc_number) { 3201 offset = RADEON_CUR2_OFFSET; 3202 hvoff = RADEON_CUR2_HORZ_VERT_OFF; 3203 hvpos = RADEON_CUR2_HORZ_VERT_POSN; 3204 crtcoff = RADEON_CRTC2_OFFSET; 3205 } else { 3206 offset = RADEON_CUR_OFFSET; 3207 hvoff = RADEON_CUR_HORZ_VERT_OFF; 3208 hvpos = RADEON_CUR_HORZ_VERT_POSN; 3209 crtcoff = RADEON_CRTC_OFFSET; 3210 } 3211 3212 x = dp->rd_cursor.rc_pos.x; 3213 y = dp->rd_cursor.rc_pos.y; 3214 3215 while (y < rcp->rc_yoffset) { 3216 rcp->rc_yoffset -= RADEON_PANINCREMENT; 3217 } 3218 while (y >= (rcp->rc_yoffset + rcp->rc_videomode.vdisplay)) { 3219 rcp->rc_yoffset += RADEON_PANINCREMENT; 3220 } 3221 while (x < rcp->rc_xoffset) { 3222 rcp->rc_xoffset -= RADEON_PANINCREMENT; 3223 } 3224 while (x >= (rcp->rc_xoffset + rcp->rc_videomode.hdisplay)) { 3225 rcp->rc_xoffset += RADEON_PANINCREMENT; 3226 } 3227 3228 /* adjust for the cursor's hotspot */ 3229 x -= dp->rd_cursor.rc_hot.x; 3230 y -= dp->rd_cursor.rc_hot.y; 3231 xoff = yoff = 0; 3232 3233 if (x >= dp->rd_virtx) 3234 x = dp->rd_virtx - 1; 3235 if (y >= dp->rd_virty) 3236 y = dp->rd_virty - 1; 3237 3238 /* now adjust cursor so it is relative to viewport */ 3239 x -= rcp->rc_xoffset; 3240 y -= rcp->rc_yoffset; 3241 3242 /* 3243 * no need to check for fall off, because we should 3244 * never move off the screen entirely! 3245 */ 3246 coff = 0; 3247 if (x < 0) { 3248 xoff = -x; 3249 x = 0; 3250 } 3251 if (y < 0) { 3252 yoff = -y; 3253 y = 0; 3254 coff = (yoff * 2) * 8; 3255 } 3256 3257 /* pan the display */ 3258 PUT32(sc, crtcoff, (rcp->rc_yoffset * dp->rd_stride) + 3259 rcp->rc_xoffset); 3260 3261 PUT32(sc, offset, (dp->rd_curoff + coff) | RADEON_CUR_LOCK); 3262 PUT32(sc, hvoff, (xoff << 16) | (yoff) | RADEON_CUR_LOCK); 3263 /* NB: this unlocks the cursor */ 3264 PUT32(sc, hvpos, (x << 16) | y); 3265 } 3266 } 3267 3268 static void 3269 radeonfb_cursor_visible(struct radeonfb_display *dp) 3270 { 3271 int i; 3272 uint32_t gencntl, bit; 3273 3274 for (i = 0; i < dp->rd_ncrtcs; i++) { 3275 if (dp->rd_crtcs[i].rc_number) { 3276 gencntl = RADEON_CRTC2_GEN_CNTL; 3277 bit = RADEON_CRTC2_CUR_EN; 3278 } else { 3279 gencntl = RADEON_CRTC_GEN_CNTL; 3280 bit = RADEON_CRTC_CUR_EN; 3281 } 3282 3283 if (dp->rd_cursor.rc_visible) 3284 SET32(dp->rd_softc, gencntl, bit); 3285 else 3286 CLR32(dp->rd_softc, gencntl, bit); 3287 } 3288 } 3289 3290 static void 3291 radeonfb_cursor_cmap(struct radeonfb_display *dp) 3292 { 3293 int i; 3294 uint32_t c0reg, c1reg; 3295 struct radeonfb_softc *sc = dp->rd_softc; 3296 3297 for (i = 0; i < dp->rd_ncrtcs; i++) { 3298 if (dp->rd_crtcs[i].rc_number) { 3299 c0reg = RADEON_CUR2_CLR0; 3300 c1reg = RADEON_CUR2_CLR1; 3301 } else { 3302 c0reg = RADEON_CUR_CLR0; 3303 c1reg = RADEON_CUR_CLR1; 3304 } 3305 3306 PUT32(sc, c0reg, dp->rd_cursor.rc_cmap[0]); 3307 PUT32(sc, c1reg, dp->rd_cursor.rc_cmap[1]); 3308 } 3309 } 3310 3311 static void 3312 radeonfb_cursor_update(struct radeonfb_display *dp, unsigned which) 3313 { 3314 struct radeonfb_softc *sc; 3315 int i; 3316 3317 sc = dp->rd_softc; 3318 for (i = 0; i < dp->rd_ncrtcs; i++) { 3319 if (dp->rd_crtcs[i].rc_number) { 3320 SET32(sc, RADEON_CUR2_OFFSET, RADEON_CUR_LOCK); 3321 } else { 3322 SET32(sc, RADEON_CUR_OFFSET,RADEON_CUR_LOCK); 3323 } 3324 } 3325 3326 if (which & WSDISPLAY_CURSOR_DOCMAP) 3327 radeonfb_cursor_cmap(dp); 3328 3329 if (which & WSDISPLAY_CURSOR_DOSHAPE) 3330 radeonfb_cursor_shape(dp); 3331 3332 if (which & WSDISPLAY_CURSOR_DOCUR) 3333 radeonfb_cursor_visible(dp); 3334 3335 /* this one is unconditional, because it updates other stuff */ 3336 radeonfb_cursor_position(dp); 3337 } 3338 3339 static struct videomode * 3340 radeonfb_best_refresh(struct videomode *m1, struct videomode *m2) 3341 { 3342 int r1, r2; 3343 3344 /* otherwise pick the higher refresh rate */ 3345 r1 = DIVIDE(DIVIDE(m1->dot_clock, m1->htotal), m1->vtotal); 3346 r2 = DIVIDE(DIVIDE(m2->dot_clock, m2->htotal), m2->vtotal); 3347 3348 return (r1 < r2 ? m2 : m1); 3349 } 3350 3351 static const struct videomode * 3352 radeonfb_port_mode(struct radeonfb_softc *sc, struct radeonfb_port *rp, 3353 int x, int y) 3354 { 3355 struct edid_info *ep = &rp->rp_edid; 3356 struct videomode *vmp = NULL; 3357 int i; 3358 3359 if (!rp->rp_edid_valid) { 3360 /* fallback to safe mode */ 3361 return radeonfb_modelookup(sc->sc_defaultmode); 3362 } 3363 3364 /* always choose the preferred mode first! */ 3365 if (ep->edid_preferred_mode) { 3366 3367 /* XXX: add auto-stretching support for native mode */ 3368 3369 /* this may want panning to occur, btw */ 3370 if ((ep->edid_preferred_mode->hdisplay <= x) && 3371 (ep->edid_preferred_mode->vdisplay <= y)) 3372 return ep->edid_preferred_mode; 3373 } 3374 3375 for (i = 0; i < ep->edid_nmodes; i++) { 3376 /* 3377 * We elect to pick a resolution that is too large for 3378 * the monitor than one that is too small. This means 3379 * that we will prefer to pan rather than to try to 3380 * center a smaller display on a larger screen. In 3381 * practice, this shouldn't matter because if a 3382 * monitor can support a larger resolution, it can 3383 * probably also support the smaller. A specific 3384 * exception is fixed format panels, but hopefully 3385 * they are properly dealt with by the "autostretch" 3386 * logic above. 3387 */ 3388 if ((ep->edid_modes[i].hdisplay > x) || 3389 (ep->edid_modes[i].vdisplay > y)) { 3390 continue; 3391 } 3392 3393 /* 3394 * at this point, the display mode is no larger than 3395 * what we've requested. 3396 */ 3397 if (vmp == NULL) 3398 vmp = &ep->edid_modes[i]; 3399 3400 /* eliminate smaller modes */ 3401 if ((vmp->hdisplay >= ep->edid_modes[i].hdisplay) || 3402 (vmp->vdisplay >= ep->edid_modes[i].vdisplay)) 3403 continue; 3404 3405 if ((vmp->hdisplay < ep->edid_modes[i].hdisplay) || 3406 (vmp->vdisplay < ep->edid_modes[i].vdisplay)) { 3407 vmp = &ep->edid_modes[i]; 3408 continue; 3409 } 3410 3411 KASSERT(vmp->hdisplay == ep->edid_modes[i].hdisplay); 3412 KASSERT(vmp->vdisplay == ep->edid_modes[i].vdisplay); 3413 3414 vmp = radeonfb_best_refresh(vmp, &ep->edid_modes[i]); 3415 } 3416 3417 return (vmp ? vmp : radeonfb_modelookup(sc->sc_defaultmode)); 3418 } 3419 3420 static int 3421 radeonfb_hasres(struct videomode *list, int nlist, int x, int y) 3422 { 3423 int i; 3424 3425 for (i = 0; i < nlist; i++) { 3426 if ((x == list[i].hdisplay) && 3427 (y == list[i].vdisplay)) { 3428 return 1; 3429 } 3430 } 3431 return 0; 3432 } 3433 3434 static void 3435 radeonfb_pickres(struct radeonfb_display *dp, uint16_t *x, uint16_t *y, 3436 int pan) 3437 { 3438 struct radeonfb_port *rp; 3439 struct edid_info *ep; 3440 int i, j; 3441 3442 *x = 0; 3443 *y = 0; 3444 3445 if (pan) { 3446 for (i = 0; i < dp->rd_ncrtcs; i++) { 3447 rp = dp->rd_crtcs[i].rc_port; 3448 ep = &rp->rp_edid; 3449 if (!rp->rp_edid_valid) { 3450 /* monitor not present */ 3451 continue; 3452 } 3453 3454 /* 3455 * For now we are ignoring "conflict" that 3456 * could occur when mixing some modes like 3457 * 1280x1024 and 1400x800. It isn't clear 3458 * which is better, so the first one wins. 3459 */ 3460 for (j = 0; j < ep->edid_nmodes; j++) { 3461 /* 3462 * ignore resolutions that are too big for 3463 * the radeon 3464 */ 3465 if (ep->edid_modes[j].hdisplay > 3466 dp->rd_softc->sc_maxx) 3467 continue; 3468 if (ep->edid_modes[j].vdisplay > 3469 dp->rd_softc->sc_maxy) 3470 continue; 3471 3472 /* 3473 * pick largest resolution, the 3474 * smaller monitor will pan 3475 */ 3476 if ((ep->edid_modes[j].hdisplay >= *x) && 3477 (ep->edid_modes[j].vdisplay >= *y)) { 3478 *x = ep->edid_modes[j].hdisplay; 3479 *y = ep->edid_modes[j].vdisplay; 3480 } 3481 } 3482 } 3483 3484 } else { 3485 struct videomode modes[64]; 3486 int nmodes = 0; 3487 int valid = 0; 3488 3489 for (i = 0; i < dp->rd_ncrtcs; i++) { 3490 /* 3491 * pick the largest resolution in common. 3492 */ 3493 rp = dp->rd_crtcs[i].rc_port; 3494 ep = &rp->rp_edid; 3495 3496 if (!rp->rp_edid_valid) 3497 continue; 3498 3499 if (!valid) { 3500 /* 3501 * Pick the preferred mode for this port 3502 * if available. 3503 */ 3504 if (ep->edid_preferred_mode) { 3505 struct videomode *vmp = 3506 ep->edid_preferred_mode; 3507 3508 if ((vmp->hdisplay <= 3509 dp->rd_softc->sc_maxx) && 3510 (vmp->vdisplay <= 3511 dp->rd_softc->sc_maxy)) 3512 modes[nmodes++] = *vmp; 3513 } else { 3514 3515 /* initialize starting list */ 3516 for (j = 0; j < ep->edid_nmodes; j++) { 3517 /* 3518 * ignore resolutions that are 3519 * too big for the radeon 3520 */ 3521 if (ep->edid_modes[j].hdisplay > 3522 dp->rd_softc->sc_maxx) 3523 continue; 3524 if (ep->edid_modes[j].vdisplay > 3525 dp->rd_softc->sc_maxy) 3526 continue; 3527 3528 modes[nmodes] = 3529 ep->edid_modes[j]; 3530 nmodes++; 3531 } 3532 } 3533 valid = 1; 3534 } else { 3535 /* merge into preexisting list */ 3536 for (j = 0; j < nmodes; j++) { 3537 if (!radeonfb_hasres(ep->edid_modes, 3538 ep->edid_nmodes, 3539 modes[j].hdisplay, 3540 modes[j].vdisplay)) { 3541 modes[j] = modes[nmodes]; 3542 j--; 3543 nmodes--; 3544 } 3545 } 3546 } 3547 } 3548 3549 /* now we have to pick from the merged list */ 3550 for (i = 0; i < nmodes; i++) { 3551 if ((modes[i].hdisplay >= *x) && 3552 (modes[i].vdisplay >= *y)) { 3553 *x = modes[i].hdisplay; 3554 *y = modes[i].vdisplay; 3555 } 3556 } 3557 } 3558 3559 if ((*x == 0) || (*y == 0)) { 3560 /* fallback to safe mode */ 3561 *x = 640; 3562 *y = 480; 3563 } 3564 } 3565 3566 /* 3567 * backlight levels are linear on: 3568 * - RV200, RV250, RV280, RV350 3569 * - but NOT on PowerBook4,3 6,3 6,5 3570 * according to Linux' radeonfb 3571 */ 3572 3573 /* Get the current backlight level for the display. */ 3574 3575 static int 3576 radeonfb_get_backlight(struct radeonfb_display *dp) 3577 { 3578 int s; 3579 uint32_t level; 3580 3581 s = spltty(); 3582 3583 level = radeonfb_get32(dp->rd_softc, RADEON_LVDS_GEN_CNTL); 3584 level &= RADEON_LVDS_BL_MOD_LEV_MASK; 3585 level >>= RADEON_LVDS_BL_MOD_LEV_SHIFT; 3586 3587 /* 3588 * On some chips, we should negate the backlight level. 3589 * XXX Find out on which chips. 3590 */ 3591 if (dp->rd_softc->sc_flags & RFB_INV_BLIGHT) 3592 level = RADEONFB_BACKLIGHT_MAX - level; 3593 3594 splx(s); 3595 3596 return level; 3597 } 3598 3599 /* Set the backlight to the given level for the display. */ 3600 3601 static int 3602 radeonfb_set_backlight(struct radeonfb_display *dp, int level) 3603 { 3604 struct radeonfb_softc *sc; 3605 int rlevel, s; 3606 uint32_t lvds; 3607 3608 s = spltty(); 3609 3610 if (level < 0) 3611 level = 0; 3612 else if (level >= RADEONFB_BACKLIGHT_MAX) 3613 level = RADEONFB_BACKLIGHT_MAX; 3614 3615 sc = dp->rd_softc; 3616 3617 /* On some chips, we should negate the backlight level. */ 3618 if (dp->rd_softc->sc_flags & RFB_INV_BLIGHT) { 3619 rlevel = RADEONFB_BACKLIGHT_MAX - level; 3620 } else 3621 rlevel = level; 3622 3623 callout_stop(&dp->rd_bl_lvds_co); 3624 radeonfb_engine_idle(sc); 3625 3626 /* 3627 * Turn off the display if the backlight is set to 0, since the 3628 * display is useless without backlight anyway. 3629 */ 3630 if (level == 0) 3631 radeonfb_blank(dp, 1); 3632 else if (radeonfb_get_backlight(dp) == 0) 3633 radeonfb_blank(dp, 0); 3634 3635 lvds = radeonfb_get32(sc, RADEON_LVDS_GEN_CNTL); 3636 lvds &= ~RADEON_LVDS_DISPLAY_DIS; 3637 if (!(lvds & RADEON_LVDS_BLON) || !(lvds & RADEON_LVDS_ON)) { 3638 lvds |= dp->rd_bl_lvds_val & RADEON_LVDS_DIGON; 3639 lvds |= RADEON_LVDS_BLON | RADEON_LVDS_EN; 3640 radeonfb_put32(sc, RADEON_LVDS_GEN_CNTL, lvds); 3641 lvds &= ~RADEON_LVDS_BL_MOD_LEV_MASK; 3642 lvds |= rlevel << RADEON_LVDS_BL_MOD_LEV_SHIFT; 3643 lvds |= RADEON_LVDS_ON; 3644 lvds |= dp->rd_bl_lvds_val & RADEON_LVDS_BL_MOD_EN; 3645 } else { 3646 lvds &= ~RADEON_LVDS_BL_MOD_LEV_MASK; 3647 lvds |= rlevel << RADEON_LVDS_BL_MOD_LEV_SHIFT; 3648 radeonfb_put32(sc, RADEON_LVDS_GEN_CNTL, lvds); 3649 } 3650 3651 dp->rd_bl_lvds_val &= ~RADEON_LVDS_STATE_MASK; 3652 dp->rd_bl_lvds_val |= lvds & RADEON_LVDS_STATE_MASK; 3653 /* XXX What is the correct delay? */ 3654 callout_schedule(&dp->rd_bl_lvds_co, 200 * hz); 3655 3656 splx(s); 3657 3658 return 0; 3659 } 3660 3661 /* 3662 * Callout function for delayed operations on the LVDS_GEN_CNTL register. 3663 * Set the delayed bits in the register, and clear the stored delayed 3664 * value. 3665 */ 3666 3667 static void radeonfb_lvds_callout(void *arg) 3668 { 3669 struct radeonfb_display *dp = arg; 3670 int s; 3671 3672 s = splhigh(); 3673 3674 radeonfb_mask32(dp->rd_softc, RADEON_LVDS_GEN_CNTL, ~0, 3675 dp->rd_bl_lvds_val); 3676 dp->rd_bl_lvds_val = 0; 3677 3678 splx(s); 3679 } 3680 3681 static void 3682 radeonfb_brightness_up(device_t dev) 3683 { 3684 struct radeonfb_softc *sc = device_private(dev); 3685 int level; 3686 3687 /* we assume the main display is the first one - need a better way */ 3688 if (sc->sc_ndisplays < 1) return; 3689 level = radeonfb_get_backlight(&sc->sc_displays[0]); 3690 level = min(RADEONFB_BACKLIGHT_MAX, level + 5); 3691 radeonfb_set_backlight(&sc->sc_displays[0], level); 3692 } 3693 3694 static void 3695 radeonfb_brightness_down(device_t dev) 3696 { 3697 struct radeonfb_softc *sc = device_private(dev); 3698 int level; 3699 3700 /* we assume the main display is the first one - need a better way */ 3701 if (sc->sc_ndisplays < 1) return; 3702 level = radeonfb_get_backlight(&sc->sc_displays[0]); 3703 level = max(0, level - 5); 3704 radeonfb_set_backlight(&sc->sc_displays[0], level); 3705 } 3706
Indexes created Thu Sep 25 08:09:54 GMT 2025