radeonfb.c revision 1.58
1 /* $NetBSD: radeonfb.c,v 1.58 2012/03/13 18:40:33 elad Exp $ */ 2 3 /*- 4 * Copyright (c) 2006 Itronix Inc. 5 * All rights reserved. 6 * 7 * Written by Garrett D'Amore for Itronix Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. The name of Itronix Inc. may not be used to endorse 18 * or promote products derived from this software without specific 19 * prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY ITRONIX INC. ``AS IS'' AND ANY EXPRESS 22 * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 23 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL ITRONIX INC. BE LIABLE FOR ANY 25 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE 27 * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 29 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 30 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 31 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * ATI Technologies Inc. ("ATI") has not assisted in the creation of, and 36 * does not endorse, this software. ATI will not be responsible or liable 37 * for any actual or alleged damage or loss caused by or in connection with 38 * the use of or reliance on this software. 39 */ 40 41 /* 42 * Portions of this code were taken from XFree86's Radeon driver, which bears 43 * this notice: 44 * 45 * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and 46 * VA Linux Systems Inc., Fremont, California. 47 * 48 * All Rights Reserved. 49 * 50 * Permission is hereby granted, free of charge, to any person obtaining 51 * a copy of this software and associated documentation files (the 52 * "Software"), to deal in the Software without restriction, including 53 * without limitation on the rights to use, copy, modify, merge, 54 * publish, distribute, sublicense, and/or sell copies of the Software, 55 * and to permit persons to whom the Software is furnished to do so, 56 * subject to the following conditions: 57 * 58 * The above copyright notice and this permission notice (including the 59 * next paragraph) shall be included in all copies or substantial 60 * portions of the Software. 61 * 62 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 63 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 64 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 65 * NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR 66 * THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 67 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 68 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 69 * DEALINGS IN THE SOFTWARE. 70 */ 71 72 #include <sys/cdefs.h> 73 __KERNEL_RCSID(0, "$NetBSD: radeonfb.c,v 1.58 2012/03/13 18:40:33 elad Exp $"); 74 75 #include <sys/param.h> 76 #include <sys/systm.h> 77 #include <sys/device.h> 78 #include <sys/malloc.h> 79 #include <sys/bus.h> 80 #include <sys/kernel.h> 81 #include <sys/lwp.h> 82 #include <sys/kauth.h> 83 84 #include <dev/wscons/wsdisplayvar.h> 85 #include <dev/wscons/wsconsio.h> 86 #include <dev/wsfont/wsfont.h> 87 #include <dev/rasops/rasops.h> 88 #include <dev/videomode/videomode.h> 89 #include <dev/videomode/edidvar.h> 90 #include <dev/wscons/wsdisplay_vconsvar.h> 91 #include <dev/pci/wsdisplay_pci.h> 92 #include <dev/wscons/wsdisplay_glyphcachevar.h> 93 94 #include <dev/pci/pcidevs.h> 95 #include <dev/pci/pcireg.h> 96 #include <dev/pci/pcivar.h> 97 #include <dev/pci/pciio.h> 98 #include <dev/pci/radeonfbreg.h> 99 #include <dev/pci/radeonfbvar.h> 100 #include "opt_radeonfb.h" 101 #include "opt_vcons.h" 102 103 #ifdef RADEONFB_DEPTH_32 104 #define RADEONFB_DEFAULT_DEPTH 32 105 #else 106 #define RADEONFB_DEFAULT_DEPTH 8 107 #endif 108 109 static int radeonfb_match(device_t, cfdata_t, void *); 110 static void radeonfb_attach(device_t, device_t, void *); 111 static int radeonfb_ioctl(void *, void *, unsigned long, void *, int, 112 struct lwp *); 113 static paddr_t radeonfb_mmap(void *, void *, off_t, int); 114 static int radeonfb_scratch_test(struct radeonfb_softc *, int, uint32_t); 115 static void radeonfb_loadbios(struct radeonfb_softc *, 116 const struct pci_attach_args *); 117 118 static uintmax_t radeonfb_getprop_num(struct radeonfb_softc *, const char *, 119 uintmax_t); 120 static int radeonfb_getclocks(struct radeonfb_softc *); 121 static int radeonfb_gettmds(struct radeonfb_softc *); 122 static int radeonfb_calc_dividers(struct radeonfb_softc *, uint32_t, 123 uint32_t *, uint32_t *); 124 static int radeonfb_getconnectors(struct radeonfb_softc *); 125 static const struct videomode *radeonfb_modelookup(const char *); 126 static void radeonfb_init_screen(void *, struct vcons_screen *, int, long *); 127 static void radeonfb_pllwriteupdate(struct radeonfb_softc *, int); 128 static void radeonfb_pllwaitatomicread(struct radeonfb_softc *, int); 129 static void radeonfb_program_vclk(struct radeonfb_softc *, int, int); 130 static void radeonfb_modeswitch(struct radeonfb_display *); 131 static void radeonfb_setcrtc(struct radeonfb_display *, int); 132 static void radeonfb_init_misc(struct radeonfb_softc *); 133 static void radeonfb_set_fbloc(struct radeonfb_softc *); 134 static void radeonfb_init_palette(struct radeonfb_softc *, int); 135 static void radeonfb_r300cg_workaround(struct radeonfb_softc *); 136 137 static int radeonfb_isblank(struct radeonfb_display *); 138 static void radeonfb_blank(struct radeonfb_display *, int); 139 static int radeonfb_set_cursor(struct radeonfb_display *, 140 struct wsdisplay_cursor *); 141 static int radeonfb_set_curpos(struct radeonfb_display *, 142 struct wsdisplay_curpos *); 143 144 /* acceleration support */ 145 static void radeonfb_rectfill(struct radeonfb_display *, int dstx, int dsty, 146 int width, int height, uint32_t color); 147 static void radeonfb_bitblt(void *, int srcx, int srcy, 148 int dstx, int dsty, int width, int height, int rop); 149 150 /* hw cursor support */ 151 static void radeonfb_cursor_cmap(struct radeonfb_display *); 152 static void radeonfb_cursor_shape(struct radeonfb_display *); 153 static void radeonfb_cursor_position(struct radeonfb_display *); 154 static void radeonfb_cursor_visible(struct radeonfb_display *); 155 static void radeonfb_cursor_update(struct radeonfb_display *, unsigned); 156 157 static void radeonfb_wait_fifo(struct radeonfb_softc *, int); 158 static void radeonfb_engine_idle(struct radeonfb_softc *); 159 static void radeonfb_engine_flush(struct radeonfb_softc *); 160 static void radeonfb_engine_reset(struct radeonfb_softc *); 161 static void radeonfb_engine_init(struct radeonfb_display *); 162 static inline void radeonfb_unclip(struct radeonfb_softc *); 163 164 static void radeonfb_eraserows(void *, int, int, long); 165 static void radeonfb_erasecols(void *, int, int, int, long); 166 static void radeonfb_copyrows(void *, int, int, int); 167 static void radeonfb_copycols(void *, int, int, int, int); 168 static void radeonfb_cursor(void *, int, int, int); 169 static void radeonfb_putchar(void *, int, int, unsigned, long); 170 static void radeonfb_putchar_aa32(void *, int, int, unsigned, long); 171 static void radeonfb_putchar_aa8(void *, int, int, unsigned, long); 172 static void radeonfb_putchar_wrapper(void *, int, int, unsigned, long); 173 174 static int radeonfb_get_backlight(struct radeonfb_display *); 175 static int radeonfb_set_backlight(struct radeonfb_display *, int); 176 static void radeonfb_lvds_callout(void *); 177 178 static void radeonfb_brightness_up(device_t); 179 static void radeonfb_brightness_down(device_t); 180 181 static struct videomode *radeonfb_best_refresh(struct videomode *, 182 struct videomode *); 183 static void radeonfb_pickres(struct radeonfb_display *, uint16_t *, 184 uint16_t *, int); 185 static const struct videomode *radeonfb_port_mode(struct radeonfb_softc *, 186 struct radeonfb_port *, int, int); 187 188 static int radeonfb_drm_print(void *, const char *); 189 190 #ifdef RADEONFB_DEBUG 191 int radeon_debug = 1; 192 #define DPRINTF(x) \ 193 if (radeon_debug) printf x 194 #define PRINTREG(r) DPRINTF((#r " = %08x\n", GET32(sc, r))) 195 #define PRINTPLL(r) DPRINTF((#r " = %08x\n", GETPLL(sc, r))) 196 #else 197 #define DPRINTF(x) 198 #define PRINTREG(r) 199 #define PRINTPLL(r) 200 #endif 201 202 #define ROUNDUP(x,y) (((x) + ((y) - 1)) & ~((y) - 1)) 203 204 #ifndef RADEON_DEFAULT_MODE 205 /* any reasonably modern display should handle this */ 206 #define RADEON_DEFAULT_MODE "1024x768x60" 207 #endif 208 209 extern const u_char rasops_cmap[768]; 210 211 const char *radeonfb_default_mode = RADEON_DEFAULT_MODE; 212 213 static struct { 214 int size; /* minimum memory size (MB) */ 215 int maxx; /* maximum x dimension */ 216 int maxy; /* maximum y dimension */ 217 int maxbpp; /* maximum bpp */ 218 int maxdisp; /* maximum logical display count */ 219 } radeonfb_limits[] = { 220 { 32, 2048, 1536, 32, 2 }, 221 { 16, 1600, 1200, 32, 2 }, 222 { 8, 1600, 1200, 32, 1 }, 223 { 0, 0, 0, 0, 0 }, 224 }; 225 226 static struct wsscreen_descr radeonfb_stdscreen = { 227 "fb", /* name */ 228 0, 0, /* ncols, nrows */ 229 NULL, /* textops */ 230 8, 16, /* fontwidth, fontheight */ 231 WSSCREEN_WSCOLORS, /* capabilities */ 232 0, /* modecookie */ 233 }; 234 235 struct wsdisplay_accessops radeonfb_accessops = { 236 radeonfb_ioctl, 237 radeonfb_mmap, 238 NULL, /* vcons_alloc_screen */ 239 NULL, /* vcons_free_screen */ 240 NULL, /* vcons_show_screen */ 241 NULL, /* load_font */ 242 NULL, /* pollc */ 243 NULL, /* scroll */ 244 }; 245 246 static struct { 247 uint16_t devid; 248 uint16_t family; 249 uint16_t flags; 250 } radeonfb_devices[] = 251 { 252 /* R100 family */ 253 { PCI_PRODUCT_ATI_RADEON_R100_QD, RADEON_R100, 0 }, 254 { PCI_PRODUCT_ATI_RADEON_R100_QE, RADEON_R100, 0 }, 255 { PCI_PRODUCT_ATI_RADEON_R100_QF, RADEON_R100, 0 }, 256 { PCI_PRODUCT_ATI_RADEON_R100_QG, RADEON_R100, 0 }, 257 258 /* RV100 family */ 259 { PCI_PRODUCT_ATI_RADEON_RV100_LY, RADEON_RV100, RFB_MOB }, 260 { PCI_PRODUCT_ATI_RADEON_RV100_LZ, RADEON_RV100, RFB_MOB }, 261 { PCI_PRODUCT_ATI_RADEON_RV100_QY, RADEON_RV100, 0 }, 262 { PCI_PRODUCT_ATI_RADEON_RV100_QZ, RADEON_RV100, 0 }, 263 264 /* RS100 family */ 265 { PCI_PRODUCT_ATI_RADEON_RS100_4136, RADEON_RS100, 0 }, 266 { PCI_PRODUCT_ATI_RADEON_RS100_4336, RADEON_RS100, RFB_MOB }, 267 268 /* RS200/RS250 family */ 269 { PCI_PRODUCT_ATI_RADEON_RS200_4337, RADEON_RS200, RFB_MOB }, 270 { PCI_PRODUCT_ATI_RADEON_RS200_A7, RADEON_RS200, 0 }, 271 { PCI_PRODUCT_ATI_RADEON_RS250_B7, RADEON_RS200, RFB_MOB }, 272 { PCI_PRODUCT_ATI_RADEON_RS250_D7, RADEON_RS200, 0 }, 273 274 /* R200 family */ 275 /* add more R200 products? , 5148 */ 276 { PCI_PRODUCT_ATI_RADEON_R200_BB, RADEON_R200, 0 }, 277 { PCI_PRODUCT_ATI_RADEON_R200_BC, RADEON_R200, 0 }, 278 { PCI_PRODUCT_ATI_RADEON_R200_QH, RADEON_R200, 0 }, 279 { PCI_PRODUCT_ATI_RADEON_R200_QL, RADEON_R200, 0 }, 280 { PCI_PRODUCT_ATI_RADEON_R200_QM, RADEON_R200, 0 }, 281 282 /* RV200 family */ 283 { PCI_PRODUCT_ATI_RADEON_RV200_LW, RADEON_RV200, RFB_MOB }, 284 { PCI_PRODUCT_ATI_RADEON_RV200_LX, RADEON_RV200, RFB_MOB }, 285 { PCI_PRODUCT_ATI_RADEON_RV200_QW, RADEON_RV200, 0 }, 286 { PCI_PRODUCT_ATI_RADEON_RV200_QX, RADEON_RV200, 0 }, 287 288 /* RV250 family */ 289 { PCI_PRODUCT_ATI_RADEON_RV250_4966, RADEON_RV250, 0 }, 290 { PCI_PRODUCT_ATI_RADEON_RV250_4967, RADEON_RV250, 0 }, 291 { PCI_PRODUCT_ATI_RADEON_RV250_4C64, RADEON_RV250, RFB_MOB }, 292 { PCI_PRODUCT_ATI_RADEON_RV250_4C66, RADEON_RV250, RFB_MOB }, 293 { PCI_PRODUCT_ATI_RADEON_RV250_4C67, RADEON_RV250, RFB_MOB }, 294 295 /* RS300 family */ 296 { PCI_PRODUCT_ATI_RADEON_RS300_X5, RADEON_RS300, 0 }, 297 { PCI_PRODUCT_ATI_RADEON_RS300_X4, RADEON_RS300, 0 }, 298 { PCI_PRODUCT_ATI_RADEON_RS300_7834, RADEON_RS300, 0 }, 299 { PCI_PRODUCT_ATI_RADEON_RS300_7835, RADEON_RS300, RFB_MOB }, 300 301 /* RV280 family */ 302 { PCI_PRODUCT_ATI_RADEON_RV280_5960, RADEON_RV280, 0 }, 303 { PCI_PRODUCT_ATI_RADEON_RV280_5961, RADEON_RV280, 0 }, 304 { PCI_PRODUCT_ATI_RADEON_RV280_5962, RADEON_RV280, 0 }, 305 { PCI_PRODUCT_ATI_RADEON_RV280_5963, RADEON_RV280, 0 }, 306 { PCI_PRODUCT_ATI_RADEON_RV280_5964, RADEON_RV280, 0 }, 307 { PCI_PRODUCT_ATI_RADEON_RV280_5C61, RADEON_RV280, RFB_MOB }, 308 { PCI_PRODUCT_ATI_RADEON_RV280_5C63, RADEON_RV280, RFB_MOB }, 309 310 /* R300 family */ 311 { PCI_PRODUCT_ATI_RADEON_R300_AD, RADEON_R300, 0 }, 312 { PCI_PRODUCT_ATI_RADEON_R300_AE, RADEON_R300, 0 }, 313 { PCI_PRODUCT_ATI_RADEON_R300_AF, RADEON_R300, 0 }, 314 { PCI_PRODUCT_ATI_RADEON_R300_AG, RADEON_R300, 0 }, 315 { PCI_PRODUCT_ATI_RADEON_R300_ND, RADEON_R300, 0 }, 316 { PCI_PRODUCT_ATI_RADEON_R300_NE, RADEON_R300, 0 }, 317 { PCI_PRODUCT_ATI_RADEON_R300_NF, RADEON_R300, 0 }, 318 { PCI_PRODUCT_ATI_RADEON_R300_NG, RADEON_R300, 0 }, 319 320 /* RV350/RV360 family */ 321 { PCI_PRODUCT_ATI_RADEON_RV350_AP, RADEON_RV350, 0 }, 322 { PCI_PRODUCT_ATI_RADEON_RV350_AQ, RADEON_RV350, 0 }, 323 { PCI_PRODUCT_ATI_RADEON_RV360_AR, RADEON_RV350, 0 }, 324 { PCI_PRODUCT_ATI_RADEON_RV350_AS, RADEON_RV350, 0 }, 325 { PCI_PRODUCT_ATI_RADEON_RV350_AT, RADEON_RV350, 0 }, 326 { PCI_PRODUCT_ATI_RADEON_RV350_AV, RADEON_RV350, 0 }, 327 { PCI_PRODUCT_ATI_RADEON_RV350_NP, RADEON_RV350, RFB_MOB }, 328 { PCI_PRODUCT_ATI_RADEON_RV350_NQ, RADEON_RV350, RFB_MOB }, 329 { PCI_PRODUCT_ATI_RADEON_RV350_NR, RADEON_RV350, RFB_MOB }, 330 { PCI_PRODUCT_ATI_RADEON_RV350_NS, RADEON_RV350, RFB_MOB }, 331 { PCI_PRODUCT_ATI_RADEON_RV350_NT, RADEON_RV350, RFB_MOB }, 332 { PCI_PRODUCT_ATI_RADEON_RV350_NV, RADEON_RV350, RFB_MOB }, 333 334 /* R350/R360 family */ 335 { PCI_PRODUCT_ATI_RADEON_R350_AH, RADEON_R350, 0 }, 336 { PCI_PRODUCT_ATI_RADEON_R350_AI, RADEON_R350, 0 }, 337 { PCI_PRODUCT_ATI_RADEON_R350_AJ, RADEON_R350, 0 }, 338 { PCI_PRODUCT_ATI_RADEON_R350_AK, RADEON_R350, 0 }, 339 { PCI_PRODUCT_ATI_RADEON_R350_NH, RADEON_R350, 0 }, 340 { PCI_PRODUCT_ATI_RADEON_R350_NI, RADEON_R350, 0 }, 341 { PCI_PRODUCT_ATI_RADEON_R350_NK, RADEON_R350, 0 }, 342 { PCI_PRODUCT_ATI_RADEON_R360_NJ, RADEON_R350, 0 }, 343 344 /* RV380/RV370 family */ 345 { PCI_PRODUCT_ATI_RADEON_RV380_3150, RADEON_RV380, RFB_MOB }, 346 { PCI_PRODUCT_ATI_RADEON_RV380_3154, RADEON_RV380, RFB_MOB }, 347 { PCI_PRODUCT_ATI_RADEON_RV380_3E50, RADEON_RV380, 0 }, 348 { PCI_PRODUCT_ATI_RADEON_RV380_3E54, RADEON_RV380, 0 }, 349 { PCI_PRODUCT_ATI_RADEON_RV370_5460, RADEON_RV380, RFB_MOB }, 350 { PCI_PRODUCT_ATI_RADEON_RV370_5464, RADEON_RV380, RFB_MOB }, 351 { PCI_PRODUCT_ATI_RADEON_RV370_5B60, RADEON_RV380, 0 }, 352 { PCI_PRODUCT_ATI_RADEON_RV370_5B64, RADEON_RV380, 0 }, 353 { PCI_PRODUCT_ATI_RADEON_RV370_5B65, RADEON_RV380, 0 }, 354 355 /* R420/R423 family */ 356 { PCI_PRODUCT_ATI_RADEON_R420_JH, RADEON_R420, 0 }, 357 { PCI_PRODUCT_ATI_RADEON_R420_JI, RADEON_R420, 0 }, 358 { PCI_PRODUCT_ATI_RADEON_R420_JJ, RADEON_R420, 0 }, 359 { PCI_PRODUCT_ATI_RADEON_R420_JK, RADEON_R420, 0 }, 360 { PCI_PRODUCT_ATI_RADEON_R420_JL, RADEON_R420, 0 }, 361 { PCI_PRODUCT_ATI_RADEON_R420_JM, RADEON_R420, 0 }, 362 { PCI_PRODUCT_ATI_RADEON_R420_JN, RADEON_R420, RFB_MOB }, 363 { PCI_PRODUCT_ATI_RADEON_R420_JP, RADEON_R420, 0 }, 364 { PCI_PRODUCT_ATI_RADEON_R423_UH, RADEON_R420, 0 }, 365 { PCI_PRODUCT_ATI_RADEON_R423_UI, RADEON_R420, 0 }, 366 { PCI_PRODUCT_ATI_RADEON_R423_UJ, RADEON_R420, 0 }, 367 { PCI_PRODUCT_ATI_RADEON_R423_UK, RADEON_R420, 0 }, 368 { PCI_PRODUCT_ATI_RADEON_R423_UQ, RADEON_R420, 0 }, 369 { PCI_PRODUCT_ATI_RADEON_R423_UR, RADEON_R420, 0 }, 370 { PCI_PRODUCT_ATI_RADEON_R423_UT, RADEON_R420, 0 }, 371 { PCI_PRODUCT_ATI_RADEON_R423_5D57, RADEON_R420, 0 }, 372 { PCI_PRODUCT_ATI_RADEON_R430_554F, RADEON_R420, 0 }, 373 374 { 0, 0, 0 } 375 }; 376 377 static struct { 378 int divider; 379 int mask; 380 } radeonfb_dividers[] = { 381 { 1, 0 }, 382 { 2, 1 }, 383 { 3, 4 }, 384 { 4, 2 }, 385 { 6, 6 }, 386 { 8, 3 }, 387 { 12, 7 }, 388 { 0, 0 } 389 }; 390 391 /* 392 * This table taken from X11. 393 */ 394 static const struct { 395 int family; 396 struct radeon_tmds_pll plls[4]; 397 } radeonfb_tmds_pll[] = { 398 { RADEON_R100, {{12000, 0xa1b}, {-1, 0xa3f}}}, 399 { RADEON_RV100, {{12000, 0xa1b}, {-1, 0xa3f}}}, 400 { RADEON_RS100, {{0, 0}}}, 401 { RADEON_RV200, {{15000, 0xa1b}, {-1, 0xa3f}}}, 402 { RADEON_RS200, {{15000, 0xa1b}, {-1, 0xa3f}}}, 403 { RADEON_R200, {{15000, 0xa1b}, {-1, 0xa3f}}}, 404 { RADEON_RV250, {{15500, 0x81b}, {-1, 0x83f}}}, 405 { RADEON_RS300, {{0, 0}}}, 406 { RADEON_RV280, {{13000, 0x400f4}, {15000, 0x400f7}}}, 407 { RADEON_R300, {{-1, 0xb01cb}}}, 408 { RADEON_R350, {{-1, 0xb01cb}}}, 409 { RADEON_RV350, {{15000, 0xb0155}, {-1, 0xb01cb}}}, 410 { RADEON_RV380, {{15000, 0xb0155}, {-1, 0xb01cb}}}, 411 { RADEON_R420, {{-1, 0xb01cb}}}, 412 }; 413 414 #define RADEONFB_BACKLIGHT_MAX 255 /* Maximum backlight level. */ 415 416 417 CFATTACH_DECL_NEW(radeonfb, sizeof (struct radeonfb_softc), 418 radeonfb_match, radeonfb_attach, NULL, NULL); 419 420 static int 421 radeonfb_match(device_t parent, cfdata_t match, void *aux) 422 { 423 const struct pci_attach_args *pa = aux; 424 int i; 425 426 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_ATI) 427 return 0; 428 429 for (i = 0; radeonfb_devices[i].devid; i++) { 430 if (PCI_PRODUCT(pa->pa_id) == radeonfb_devices[i].devid) 431 return 100; /* high to defeat VGA/VESA */ 432 } 433 434 return 0; 435 } 436 437 static void 438 radeonfb_attach(device_t parent, device_t dev, void *aux) 439 { 440 struct radeonfb_softc *sc = device_private(dev); 441 const struct pci_attach_args *pa = aux; 442 const char *mptr; 443 bus_size_t bsz; 444 pcireg_t screg; 445 int i, j, fg, bg, ul, flags; 446 uint32_t v; 447 448 sc->sc_dev = dev; 449 sc->sc_id = pa->pa_id; 450 for (i = 0; radeonfb_devices[i].devid; i++) { 451 if (PCI_PRODUCT(sc->sc_id) == radeonfb_devices[i].devid) 452 break; 453 } 454 455 pci_aprint_devinfo(pa, NULL); 456 457 DPRINTF((prop_dictionary_externalize(device_properties(dev)))); 458 459 KASSERT(radeonfb_devices[i].devid != 0); 460 sc->sc_pt = pa->pa_tag; 461 sc->sc_iot = pa->pa_iot; 462 sc->sc_pc = pa->pa_pc; 463 sc->sc_family = radeonfb_devices[i].family; 464 sc->sc_flags = radeonfb_devices[i].flags; 465 466 /* enable memory and IO access */ 467 screg = pci_conf_read(sc->sc_pc, sc->sc_pt, PCI_COMMAND_STATUS_REG); 468 screg |= PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE; 469 pci_conf_write(sc->sc_pc, sc->sc_pt, PCI_COMMAND_STATUS_REG, screg); 470 471 /* 472 * Some flags are general to entire chip families, and rather 473 * than clutter up the table with them, we go ahead and set 474 * them here. 475 */ 476 switch (sc->sc_family) { 477 case RADEON_RS100: 478 case RADEON_RS200: 479 sc->sc_flags |= RFB_IGP | RFB_RV100; 480 break; 481 482 case RADEON_RV100: 483 case RADEON_RV200: 484 case RADEON_RV250: 485 case RADEON_RV280: 486 sc->sc_flags |= RFB_RV100; 487 break; 488 489 case RADEON_RS300: 490 sc->sc_flags |= RFB_SDAC | RFB_IGP | RFB_RV100; 491 break; 492 493 case RADEON_R300: 494 case RADEON_RV350: 495 case RADEON_R350: 496 case RADEON_RV380: 497 case RADEON_R420: 498 /* newer chips */ 499 sc->sc_flags |= RFB_R300; 500 break; 501 502 case RADEON_R100: 503 sc->sc_flags |= RFB_NCRTC2; 504 break; 505 } 506 507 if ((sc->sc_family == RADEON_RV200) || 508 (sc->sc_family == RADEON_RV250) || 509 (sc->sc_family == RADEON_RV280) || 510 (sc->sc_family == RADEON_RV350)) { 511 bool inverted = 0; 512 /* backlight level is linear */ 513 DPRINTF(("found RV* chip, backlight is supposedly linear\n")); 514 prop_dictionary_get_bool(device_properties(sc->sc_dev), 515 "backlight_level_reverted", &inverted); 516 if (inverted) { 517 DPRINTF(("nope, it's inverted\n")); 518 sc->sc_flags |= RFB_INV_BLIGHT; 519 } 520 } else 521 sc->sc_flags |= RFB_INV_BLIGHT; 522 523 /* 524 * XXX: to support true multihead, this must change. 525 */ 526 sc->sc_ndisplays = 1; 527 528 /* XXX: */ 529 if (!HAS_CRTC2(sc)) { 530 sc->sc_ndisplays = 1; 531 } 532 533 if (pci_mapreg_map(pa, RADEON_MAPREG_MMIO, PCI_MAPREG_TYPE_MEM, 0, 534 &sc->sc_regt, &sc->sc_regh, &sc->sc_regaddr, 535 &sc->sc_regsz) != 0) { 536 aprint_error("%s: unable to map registers!\n", XNAME(sc)); 537 goto error; 538 } 539 540 if (pci_mapreg_info(sc->sc_pc, sc->sc_pt, PCI_MAPREG_ROM, 541 PCI_MAPREG_TYPE_ROM, &sc->sc_romaddr, &sc->sc_romsz, &flags) != 0) 542 { 543 aprint_error("%s: unable to find ROM!\n", XNAME(sc)); 544 goto error; 545 } 546 sc->sc_romt = sc->sc_memt; 547 548 /* scratch register test... */ 549 if (radeonfb_scratch_test(sc, RADEON_BIOS_0_SCRATCH, 0x55555555) || 550 radeonfb_scratch_test(sc, RADEON_BIOS_0_SCRATCH, 0xaaaaaaaa)) { 551 aprint_error("%s: scratch register test failed!\n", XNAME(sc)); 552 goto error; 553 } 554 555 PRINTREG(RADEON_BIOS_4_SCRATCH); 556 PRINTREG(RADEON_FP_GEN_CNTL); 557 sc->sc_fp_gen_cntl = GET32(sc, RADEON_FP_GEN_CNTL); 558 PRINTREG(RADEON_FP2_GEN_CNTL); 559 PRINTREG(RADEON_TMDS_CNTL); 560 PRINTREG(RADEON_TMDS_TRANSMITTER_CNTL); 561 PRINTREG(RADEON_TMDS_PLL_CNTL); 562 PRINTREG(RADEON_LVDS_GEN_CNTL); 563 PRINTREG(RADEON_FP_HORZ_STRETCH); 564 PRINTREG(RADEON_FP_VERT_STRETCH); 565 566 /* XXX: RV100 specific */ 567 PUT32(sc, RADEON_TMDS_PLL_CNTL, 0xa27); 568 569 PATCH32(sc, RADEON_TMDS_TRANSMITTER_CNTL, 570 RADEON_TMDS_TRANSMITTER_PLLEN, 571 RADEON_TMDS_TRANSMITTER_PLLEN | RADEON_TMDS_TRANSMITTER_PLLRST); 572 573 radeonfb_i2c_init(sc); 574 575 radeonfb_loadbios(sc, pa); 576 577 #ifdef RADEONFB_BIOS_INIT 578 if (radeonfb_bios_init(sc)) { 579 aprint_error("%s: BIOS inititialization failed\n", XNAME(sc)); 580 } 581 #endif 582 583 if (radeonfb_getclocks(sc)) { 584 aprint_error("%s: Unable to get reference clocks from BIOS\n", 585 XNAME(sc)); 586 goto error; 587 } 588 589 if (radeonfb_gettmds(sc)) { 590 aprint_error("%s: Unable to identify TMDS PLL settings\n", 591 XNAME(sc)); 592 goto error; 593 } 594 595 aprint_verbose("%s: refclk = %d.%03d MHz, refdiv = %d " 596 "minpll = %d, maxpll = %d\n", XNAME(sc), 597 (int)sc->sc_refclk / 1000, (int)sc->sc_refclk % 1000, 598 (int)sc->sc_refdiv, (int)sc->sc_minpll, (int)sc->sc_maxpll); 599 600 radeonfb_getconnectors(sc); 601 602 radeonfb_set_fbloc(sc); 603 604 for (i = 0; radeonfb_limits[i].size; i++) { 605 if (sc->sc_memsz >= radeonfb_limits[i].size) { 606 sc->sc_maxx = radeonfb_limits[i].maxx; 607 sc->sc_maxy = radeonfb_limits[i].maxy; 608 sc->sc_maxbpp = radeonfb_limits[i].maxbpp; 609 /* framebuffer offset, start at a 4K page */ 610 sc->sc_fboffset = sc->sc_memsz / 611 radeonfb_limits[i].maxdisp; 612 /* 613 * we use the fbsize to figure out where we can store 614 * things like cursor data. 615 */ 616 sc->sc_fbsize = 617 ROUNDUP(ROUNDUP(sc->sc_maxx * sc->sc_maxbpp / 8 , 618 RADEON_STRIDEALIGN) * sc->sc_maxy, 619 4096); 620 break; 621 } 622 } 623 624 625 radeonfb_init_misc(sc); 626 radeonfb_init_palette(sc, 0); 627 if (HAS_CRTC2(sc)) 628 radeonfb_init_palette(sc, 1); 629 630 /* program the DAC wirings */ 631 for (i = 0; i < (HAS_CRTC2(sc) ? 2 : 1); i++) { 632 switch (sc->sc_ports[i].rp_dac_type) { 633 case RADEON_DAC_PRIMARY: 634 PATCH32(sc, RADEON_DAC_CNTL2, 635 i ? RADEON_DAC2_DAC_CLK_SEL : 0, 636 ~RADEON_DAC2_DAC_CLK_SEL); 637 break; 638 case RADEON_DAC_TVDAC: 639 /* we always use the TVDAC to drive a secondary analog 640 * CRT for now. if we ever support TV-out this will 641 * have to change. 642 */ 643 SET32(sc, RADEON_DAC_CNTL2, 644 RADEON_DAC2_DAC2_CLK_SEL); 645 PATCH32(sc, RADEON_DISP_HW_DEBUG, 646 i ? 0 : RADEON_CRT2_DISP1_SEL, 647 ~RADEON_CRT2_DISP1_SEL); 648 break; 649 } 650 } 651 PRINTREG(RADEON_DAC_CNTL2); 652 PRINTREG(RADEON_DISP_HW_DEBUG); 653 654 /* other DAC programming */ 655 v = GET32(sc, RADEON_DAC_CNTL); 656 v &= (RADEON_DAC_RANGE_CNTL_MASK | RADEON_DAC_BLANKING); 657 v |= RADEON_DAC_MASK_ALL | RADEON_DAC_8BIT_EN; 658 PUT32(sc, RADEON_DAC_CNTL, v); 659 PRINTREG(RADEON_DAC_CNTL); 660 661 /* XXX: this may need more investigation */ 662 PUT32(sc, RADEON_TV_DAC_CNTL, 0x00280203); 663 PRINTREG(RADEON_TV_DAC_CNTL); 664 665 /* enable TMDS */ 666 SET32(sc, RADEON_FP_GEN_CNTL, 667 RADEON_FP_TMDS_EN | 668 RADEON_FP_CRTC_DONT_SHADOW_VPAR | 669 RADEON_FP_CRTC_DONT_SHADOW_HEND); 670 /* 671 * XXX 672 * no idea why this is necessary - if I do not clear this bit on my 673 * iBook G4 the screen remains black, even though it's already clear. 674 * It needs to be set on my Sun XVR-100 for the DVI port to work 675 */ 676 677 if (sc->sc_fp_gen_cntl & RADEON_FP_SEL_CRTC2) { 678 SET32(sc, RADEON_FP_GEN_CNTL, RADEON_FP_SEL_CRTC2); 679 } else 680 CLR32(sc, RADEON_FP_GEN_CNTL, RADEON_FP_SEL_CRTC2); 681 682 if (HAS_CRTC2(sc)) 683 SET32(sc, RADEON_FP2_GEN_CNTL, RADEON_FP2_SRC_SEL_CRTC2); 684 685 /* 686 * we use bus_space_map instead of pci_mapreg, because we don't 687 * need the full aperature space. no point in wasting virtual 688 * address space we don't intend to use, right? 689 */ 690 if ((sc->sc_memsz < (4096 * 1024)) || 691 (pci_mapreg_info(sc->sc_pc, sc->sc_pt, RADEON_MAPREG_VRAM, 692 PCI_MAPREG_TYPE_MEM, &sc->sc_memaddr, &bsz, NULL) != 0) || 693 (bsz < sc->sc_memsz)) { 694 sc->sc_memsz = 0; 695 aprint_error("%s: Bad frame buffer configuration\n", 696 XNAME(sc)); 697 goto error; 698 } 699 700 /* 64 MB should be enough -- more just wastes map entries */ 701 if (sc->sc_memsz > (64 << 20)) 702 sc->sc_memsz = (64 << 20); 703 704 sc->sc_memt = pa->pa_memt; 705 if (bus_space_map(sc->sc_memt, sc->sc_memaddr, sc->sc_memsz, 706 BUS_SPACE_MAP_LINEAR, &sc->sc_memh) != 0) { 707 sc->sc_memsz = 0; 708 aprint_error("%s: Unable to map frame buffer\n", XNAME(sc)); 709 goto error; 710 } 711 712 aprint_normal("%s: %d MB aperture at 0x%08x, " 713 "%d KB registers at 0x%08x\n", XNAME(sc), 714 (int)sc->sc_memsz >> 20, (unsigned)sc->sc_memaddr, 715 (int)sc->sc_regsz >> 10, (unsigned)sc->sc_regaddr); 716 717 /* setup default video mode from devprop (allows PROM override) */ 718 sc->sc_defaultmode = radeonfb_default_mode; 719 if (prop_dictionary_get_cstring_nocopy(device_properties(sc->sc_dev), 720 "videomode", &mptr)) { 721 722 strncpy(sc->sc_modebuf, mptr, sizeof(sc->sc_modebuf)); 723 sc->sc_defaultmode = sc->sc_modebuf; 724 } 725 726 /* initialize some basic display parameters */ 727 for (i = 0; i < sc->sc_ndisplays; i++) { 728 struct radeonfb_display *dp = &sc->sc_displays[i]; 729 struct rasops_info *ri; 730 long defattr; 731 struct wsemuldisplaydev_attach_args aa; 732 733 /* 734 * Figure out how many "displays" (desktops) we are going to 735 * support. If more than one, then each CRTC gets its own 736 * programming. 737 * 738 * XXX: this code needs to change to support mergedfb. 739 * XXX: would be nice to allow this to be overridden 740 */ 741 if (HAS_CRTC2(sc) && (sc->sc_ndisplays == 1)) { 742 DPRINTF(("dual crtcs!\n")); 743 dp->rd_ncrtcs = 2; 744 dp->rd_crtcs[0].rc_number = 0; 745 dp->rd_crtcs[1].rc_number = 1; 746 } else { 747 dp->rd_ncrtcs = 1; 748 dp->rd_crtcs[0].rc_number = i; 749 } 750 751 /* set up port pointer */ 752 for (j = 0; j < dp->rd_ncrtcs; j++) { 753 dp->rd_crtcs[j].rc_port = 754 &sc->sc_ports[dp->rd_crtcs[j].rc_number]; 755 } 756 757 dp->rd_softc = sc; 758 dp->rd_wsmode = WSDISPLAYIO_MODE_EMUL; 759 dp->rd_bg = WS_DEFAULT_BG; 760 dp->rd_bpp = RADEONFB_DEFAULT_DEPTH; /* XXX */ 761 762 /* for text mode, we pick a resolution that won't 763 * require panning */ 764 radeonfb_pickres(dp, &dp->rd_virtx, &dp->rd_virty, 0); 765 766 aprint_normal("%s: display %d: " 767 "initial virtual resolution %dx%d at %d bpp\n", 768 XNAME(sc), i, dp->rd_virtx, dp->rd_virty, dp->rd_bpp); 769 770 /* now select the *video mode* that we will use */ 771 for (j = 0; j < dp->rd_ncrtcs; j++) { 772 const struct videomode *vmp; 773 vmp = radeonfb_port_mode(sc, dp->rd_crtcs[j].rc_port, 774 dp->rd_virtx, dp->rd_virty); 775 776 /* 777 * virtual resolution should be at least as high as 778 * physical 779 */ 780 if (dp->rd_virtx < vmp->hdisplay || 781 dp->rd_virty < vmp->vdisplay) { 782 dp->rd_virtx = vmp->hdisplay; 783 dp->rd_virty = vmp->vdisplay; 784 } 785 786 dp->rd_crtcs[j].rc_videomode = *vmp; 787 printf("%s: port %d: physical %dx%d %dHz\n", 788 XNAME(sc), j, vmp->hdisplay, vmp->vdisplay, 789 DIVIDE(DIVIDE(vmp->dot_clock * 1000, 790 vmp->htotal), vmp->vtotal)); 791 } 792 793 /* N.B.: radeon wants 64-byte aligned stride */ 794 dp->rd_stride = dp->rd_virtx * dp->rd_bpp / 8; 795 dp->rd_stride = ROUNDUP(dp->rd_stride, RADEON_STRIDEALIGN); 796 797 dp->rd_offset = sc->sc_fboffset * i; 798 dp->rd_fbptr = (vaddr_t)bus_space_vaddr(sc->sc_memt, 799 sc->sc_memh) + dp->rd_offset; 800 dp->rd_curoff = sc->sc_fbsize; 801 dp->rd_curptr = dp->rd_fbptr + dp->rd_curoff; 802 803 DPRINTF(("fpbtr = %p\n", (void *)dp->rd_fbptr)); 804 805 switch (dp->rd_bpp) { 806 case 8: 807 dp->rd_format = 2; 808 break; 809 case 32: 810 dp->rd_format = 6; 811 break; 812 default: 813 aprint_error("%s: bad depth %d\n", XNAME(sc), 814 dp->rd_bpp); 815 goto error; 816 } 817 818 DPRINTF(("init engine\n")); 819 /* XXX: this seems suspicious - per display engine 820 initialization? */ 821 radeonfb_engine_init(dp); 822 823 /* copy the template into place */ 824 dp->rd_wsscreens_storage[0] = radeonfb_stdscreen; 825 dp->rd_wsscreens = dp->rd_wsscreens_storage; 826 827 /* and make up the list */ 828 dp->rd_wsscreenlist.nscreens = 1; 829 dp->rd_wsscreenlist.screens = (void *)&dp->rd_wsscreens; 830 831 vcons_init(&dp->rd_vd, dp, dp->rd_wsscreens, 832 &radeonfb_accessops); 833 834 dp->rd_vd.init_screen = radeonfb_init_screen; 835 836 dp->rd_console = 0; 837 prop_dictionary_get_bool(device_properties(sc->sc_dev), 838 "is_console", &dp->rd_console); 839 840 dp->rd_vscreen.scr_flags |= VCONS_SCREEN_IS_STATIC; 841 842 843 vcons_init_screen(&dp->rd_vd, &dp->rd_vscreen, 844 dp->rd_console, &defattr); 845 846 ri = &dp->rd_vscreen.scr_ri; 847 848 /* clear the screen */ 849 rasops_unpack_attr(defattr, &fg, &bg, &ul); 850 radeonfb_rectfill(dp, 0, 0, ri->ri_width, ri->ri_height, 851 ri->ri_devcmap[bg & 0xf]); 852 853 dp->rd_wsscreens->textops = &ri->ri_ops; 854 dp->rd_wsscreens->capabilities = ri->ri_caps; 855 dp->rd_wsscreens->nrows = ri->ri_rows; 856 dp->rd_wsscreens->ncols = ri->ri_cols; 857 858 #ifdef SPLASHSCREEN 859 dp->rd_splash.si_depth = ri->ri_depth; 860 dp->rd_splash.si_bits = ri->ri_bits; 861 dp->rd_splash.si_hwbits = ri->ri_hwbits; 862 dp->rd_splash.si_width = ri->ri_width; 863 dp->rd_splash.si_height = ri->ri_height; 864 dp->rd_splash.si_stride = ri->ri_stride; 865 dp->rd_splash.si_fillrect = NULL; 866 #endif 867 dp->rd_gc.gc_bitblt = radeonfb_bitblt; 868 dp->rd_gc.gc_rop = RADEON_ROP3_S; 869 dp->rd_gc.gc_blitcookie = dp; 870 glyphcache_init(&dp->rd_gc, dp->rd_virty + 4, 871 (0x800000 / dp->rd_stride) - (dp->rd_virty + 4), 872 dp->rd_virty, 873 ri->ri_font->fontwidth, 874 ri->ri_font->fontheight, 875 defattr); 876 if (dp->rd_console) { 877 878 radeonfb_modeswitch(dp); 879 wsdisplay_cnattach(dp->rd_wsscreens, ri, 0, 0, 880 defattr); 881 #ifdef SPLASHSCREEN 882 if (splash_render(&dp->rd_splash, 883 SPLASH_F_CENTER|SPLASH_F_FILL) == 0) 884 SCREEN_DISABLE_DRAWING(&dp->rd_vscreen); 885 else 886 #endif 887 vcons_replay_msgbuf(&dp->rd_vscreen); 888 } else { 889 890 /* 891 * since we're not the console we can postpone 892 * the rest until someone actually allocates a 893 * screen for us. but we do clear the screen 894 * at least. 895 */ 896 memset(ri->ri_bits, 0, 1024); 897 898 radeonfb_modeswitch(dp); 899 #ifdef SPLASHSCREEN 900 if (splash_render(&dp->rd_splash, 901 SPLASH_F_CENTER|SPLASH_F_FILL) == 0) 902 SCREEN_DISABLE_DRAWING(&dp->rd_vscreen); 903 #endif 904 } 905 906 aa.console = dp->rd_console; 907 aa.scrdata = &dp->rd_wsscreenlist; 908 aa.accessops = &radeonfb_accessops; 909 aa.accesscookie = &dp->rd_vd; 910 911 config_found(sc->sc_dev, &aa, wsemuldisplaydevprint); 912 913 radeonfb_blank(dp, 0); 914 915 /* Initialise delayed lvds operations for backlight. */ 916 callout_init(&dp->rd_bl_lvds_co, 0); 917 callout_setfunc(&dp->rd_bl_lvds_co, 918 radeonfb_lvds_callout, dp); 919 } 920 921 /* 922 * if we have console output via firmware like on sparc64 it may 923 * interfere with DAC programming so program the palette again 924 * here after we took over 925 */ 926 radeonfb_init_palette(sc, 0); 927 if (HAS_CRTC2(sc)) 928 radeonfb_init_palette(sc, 1); 929 930 pmf_event_register(dev, PMFE_DISPLAY_BRIGHTNESS_UP, 931 radeonfb_brightness_up, TRUE); 932 pmf_event_register(dev, PMFE_DISPLAY_BRIGHTNESS_DOWN, 933 radeonfb_brightness_down, TRUE); 934 935 config_found_ia(dev, "drm", aux, radeonfb_drm_print); 936 937 return; 938 939 error: 940 if (sc->sc_biossz) 941 free(sc->sc_bios, M_DEVBUF); 942 943 if (sc->sc_regsz) 944 bus_space_unmap(sc->sc_regt, sc->sc_regh, sc->sc_regsz); 945 946 if (sc->sc_memsz) 947 bus_space_unmap(sc->sc_memt, sc->sc_memh, sc->sc_memsz); 948 } 949 950 static void 951 radeonfb_map(struct radeonfb_softc *sc) 952 { 953 if (bus_space_map(sc->sc_regt, sc->sc_regaddr, sc->sc_regsz, 0, 954 &sc->sc_regh) != 0) { 955 aprint_error("%s: unable to map registers!\n", XNAME(sc)); 956 return; 957 } 958 if (bus_space_map(sc->sc_memt, sc->sc_memaddr, sc->sc_memsz, 959 BUS_SPACE_MAP_LINEAR, &sc->sc_memh) != 0) { 960 sc->sc_memsz = 0; 961 aprint_error("%s: Unable to map frame buffer\n", XNAME(sc)); 962 return; 963 } 964 } 965 966 static void 967 radeonfb_unmap(struct radeonfb_softc *sc) 968 { 969 bus_space_unmap(sc->sc_regt, sc->sc_regh, sc->sc_regsz); 970 bus_space_unmap(sc->sc_memt, sc->sc_memh, sc->sc_memsz); 971 } 972 973 static int 974 radeonfb_drm_print(void *aux, const char *pnp) 975 { 976 if (pnp) 977 aprint_normal("drm at %s", pnp); 978 return (UNCONF); 979 } 980 981 int 982 radeonfb_ioctl(void *v, void *vs, 983 unsigned long cmd, void *d, int flag, struct lwp *l) 984 { 985 struct vcons_data *vd; 986 struct radeonfb_display *dp; 987 struct radeonfb_softc *sc; 988 struct wsdisplay_param *param; 989 990 vd = (struct vcons_data *)v; 991 dp = (struct radeonfb_display *)vd->cookie; 992 sc = dp->rd_softc; 993 994 switch (cmd) { 995 case WSDISPLAYIO_GTYPE: 996 *(unsigned *)d = WSDISPLAY_TYPE_PCIMISC; 997 return 0; 998 999 case WSDISPLAYIO_GINFO: 1000 if (vd->active != NULL) { 1001 struct wsdisplay_fbinfo *fb; 1002 fb = (struct wsdisplay_fbinfo *)d; 1003 fb->width = dp->rd_virtx; 1004 fb->height = dp->rd_virty; 1005 fb->depth = dp->rd_bpp; 1006 fb->cmsize = 256; 1007 return 0; 1008 } else 1009 return ENODEV; 1010 case WSDISPLAYIO_GVIDEO: 1011 if (radeonfb_isblank(dp)) 1012 *(unsigned *)d = WSDISPLAYIO_VIDEO_OFF; 1013 else 1014 *(unsigned *)d = WSDISPLAYIO_VIDEO_ON; 1015 return 0; 1016 1017 case WSDISPLAYIO_SVIDEO: 1018 radeonfb_blank(dp, 1019 (*(unsigned int *)d == WSDISPLAYIO_VIDEO_OFF)); 1020 return 0; 1021 1022 case WSDISPLAYIO_GETCMAP: 1023 #if 0 1024 if (dp->rd_bpp == 8) 1025 return radeonfb_getcmap(sc, 1026 (struct wsdisplay_cmap *)d); 1027 #endif 1028 return EINVAL; 1029 1030 case WSDISPLAYIO_PUTCMAP: 1031 #if 0 1032 if (dp->rd_bpp == 8) 1033 return radeonfb_putcmap(sc, 1034 (struct wsdisplay_cmap *)d); 1035 #endif 1036 return EINVAL; 1037 1038 case WSDISPLAYIO_LINEBYTES: 1039 *(unsigned *)d = dp->rd_stride; 1040 return 0; 1041 1042 case WSDISPLAYIO_SMODE: 1043 if (*(int *)d != dp->rd_wsmode) { 1044 dp->rd_wsmode = *(int *)d; 1045 if ((dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) && 1046 (dp->rd_vd.active)) { 1047 radeonfb_map(sc); 1048 radeonfb_engine_init(dp); 1049 glyphcache_wipe(&dp->rd_gc); 1050 radeonfb_init_palette(sc, dp == &sc->sc_displays[0] ? 0 : 1); 1051 radeonfb_modeswitch(dp); 1052 vcons_redraw_screen(dp->rd_vd.active); 1053 } else { 1054 radeonfb_unmap(sc); 1055 } 1056 } 1057 return 0; 1058 1059 case WSDISPLAYIO_GCURMAX: 1060 ((struct wsdisplay_curpos *)d)->x = RADEON_CURSORMAXX; 1061 ((struct wsdisplay_curpos *)d)->y = RADEON_CURSORMAXY; 1062 return 0; 1063 1064 case WSDISPLAYIO_SCURSOR: 1065 return radeonfb_set_cursor(dp, (struct wsdisplay_cursor *)d); 1066 1067 case WSDISPLAYIO_GCURSOR: 1068 return EPASSTHROUGH; 1069 1070 case WSDISPLAYIO_GCURPOS: 1071 ((struct wsdisplay_curpos *)d)->x = dp->rd_cursor.rc_pos.x; 1072 ((struct wsdisplay_curpos *)d)->y = dp->rd_cursor.rc_pos.y; 1073 return 0; 1074 1075 case WSDISPLAYIO_SCURPOS: 1076 return radeonfb_set_curpos(dp, (struct wsdisplay_curpos *)d); 1077 1078 case WSDISPLAYIO_SSPLASH: 1079 #if defined(SPLASHSCREEN) 1080 if (*(int *)d == 1) { 1081 SCREEN_DISABLE_DRAWING(&dp->rd_vscreen); 1082 splash_render(&dp->rd_splash, 1083 SPLASH_F_CENTER|SPLASH_F_FILL); 1084 } else 1085 SCREEN_ENABLE_DRAWING(&dp->rd_vscreen); 1086 return 0; 1087 #else 1088 return ENODEV; 1089 #endif 1090 case WSDISPLAYIO_GETPARAM: 1091 param = (struct wsdisplay_param *)d; 1092 if (param->param == WSDISPLAYIO_PARAM_BACKLIGHT) { 1093 param->min = 0; 1094 param->max = RADEONFB_BACKLIGHT_MAX; 1095 param->curval = radeonfb_get_backlight(dp); 1096 return 0; 1097 } 1098 return EPASSTHROUGH; 1099 1100 case WSDISPLAYIO_SETPARAM: 1101 param = (struct wsdisplay_param *)d; 1102 if (param->param == WSDISPLAYIO_PARAM_BACKLIGHT) { 1103 return radeonfb_set_backlight(dp, param->curval); 1104 } 1105 return EPASSTHROUGH; 1106 1107 /* PCI config read/write passthrough. */ 1108 case PCI_IOC_CFGREAD: 1109 case PCI_IOC_CFGWRITE: 1110 return pci_devioctl(sc->sc_pc, sc->sc_pt, cmd, d, flag, l); 1111 1112 case WSDISPLAYIO_GET_BUSID: 1113 return wsdisplayio_busid_pci(sc->sc_dev, sc->sc_pc, 1114 sc->sc_pt, d); 1115 1116 case WSDISPLAYIO_GET_EDID: { 1117 struct wsdisplayio_edid_info *ei = d; 1118 return wsdisplayio_get_edid(sc->sc_dev, ei); 1119 } 1120 1121 default: 1122 return EPASSTHROUGH; 1123 } 1124 } 1125 1126 paddr_t 1127 radeonfb_mmap(void *v, void *vs, off_t offset, int prot) 1128 { 1129 struct vcons_data *vd; 1130 struct radeonfb_display *dp; 1131 struct radeonfb_softc *sc; 1132 paddr_t pa; 1133 1134 vd = (struct vcons_data *)v; 1135 dp = (struct radeonfb_display *)vd->cookie; 1136 sc = dp->rd_softc; 1137 1138 /* XXX: note that we don't allow mapping of registers right now */ 1139 /* XXX: this means that the XFree86 radeon driver won't work */ 1140 if ((offset >= 0) && (offset < (dp->rd_virty * dp->rd_stride))) { 1141 pa = bus_space_mmap(sc->sc_memt, 1142 sc->sc_memaddr + dp->rd_offset + offset, 0, 1143 prot, BUS_SPACE_MAP_LINEAR); 1144 return pa; 1145 } 1146 1147 #ifdef RADEONFB_MMAP_BARS 1148 /* 1149 * restrict all other mappings to processes with superuser privileges 1150 * or the kernel itself 1151 */ 1152 if (kauth_authorize_machdep(kauth_cred_get(), KAUTH_MACHDEP_UNMANAGEDMEM, 1153 NULL, NULL, NULL, NULL) != 0) { 1154 aprint_error_dev(sc->sc_dev, "mmap() rejected.\n"); 1155 return -1; 1156 } 1157 1158 if ((offset >= sc->sc_regaddr) && 1159 (offset < sc->sc_regaddr + sc->sc_regsz)) { 1160 return bus_space_mmap(sc->sc_regt, offset, 0, prot, 1161 BUS_SPACE_MAP_LINEAR); 1162 } 1163 1164 if ((offset >= sc->sc_memaddr) && 1165 (offset < sc->sc_memaddr + sc->sc_memsz)) { 1166 return bus_space_mmap(sc->sc_memt, offset, 0, prot, 1167 BUS_SPACE_MAP_LINEAR); 1168 } 1169 1170 if ((offset >= sc->sc_romaddr) && 1171 (offset < sc->sc_romaddr + sc->sc_romsz)) { 1172 return bus_space_mmap(sc->sc_memt, offset, 0, prot, 1173 BUS_SPACE_MAP_LINEAR); 1174 } 1175 1176 #ifdef PCI_MAGIC_IO_RANGE 1177 /* allow mapping of IO space */ 1178 if ((offset >= PCI_MAGIC_IO_RANGE) && 1179 (offset < PCI_MAGIC_IO_RANGE + 0x10000)) { 1180 pa = bus_space_mmap(sc->sc_iot, offset - PCI_MAGIC_IO_RANGE, 1181 0, prot, 0); 1182 return pa; 1183 } 1184 #endif /* PCI_MAGIC_IO_RANGE */ 1185 1186 #endif /* RADEONFB_MMAP_BARS */ 1187 1188 return -1; 1189 } 1190 1191 static void 1192 radeonfb_loadbios(struct radeonfb_softc *sc, const struct pci_attach_args *pa) 1193 { 1194 bus_space_tag_t romt; 1195 bus_space_handle_t romh, biosh; 1196 bus_size_t romsz; 1197 bus_addr_t ptr; 1198 1199 if (pci_mapreg_map(pa, PCI_MAPREG_ROM, PCI_MAPREG_TYPE_ROM, 1200 BUS_SPACE_MAP_PREFETCHABLE, &romt, &romh, NULL, &romsz) != 0) { 1201 aprint_verbose("%s: unable to map BIOS!\n", XNAME(sc)); 1202 return; 1203 } 1204 1205 pci_find_rom(pa, romt, romh, PCI_ROM_CODE_TYPE_X86, &biosh, 1206 &sc->sc_biossz); 1207 if (sc->sc_biossz == 0) { 1208 aprint_verbose("%s: Video BIOS not present\n", XNAME(sc)); 1209 return; 1210 } 1211 1212 sc->sc_bios = malloc(sc->sc_biossz, M_DEVBUF, M_WAITOK); 1213 bus_space_read_region_1(romt, biosh, 0, sc->sc_bios, sc->sc_biossz); 1214 1215 /* unmap the PCI expansion rom */ 1216 bus_space_unmap(romt, romh, romsz); 1217 1218 /* turn off rom decoder now */ 1219 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM, 1220 pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM) & 1221 ~PCI_MAPREG_ROM_ENABLE); 1222 1223 ptr = GETBIOS16(sc, 0x48); 1224 if ((GETBIOS32(sc, ptr + 4) == 0x41544f4d /* "ATOM" */) || 1225 (GETBIOS32(sc, ptr + 4) == 0x4d4f5441 /* "MOTA" */)) { 1226 sc->sc_flags |= RFB_ATOM; 1227 } 1228 1229 aprint_verbose("%s: Found %d KB %s BIOS\n", XNAME(sc), 1230 (unsigned)sc->sc_biossz >> 10, IS_ATOM(sc) ? "ATOM" : "Legacy"); 1231 } 1232 1233 1234 uint32_t 1235 radeonfb_get32(struct radeonfb_softc *sc, uint32_t reg) 1236 { 1237 1238 return bus_space_read_4(sc->sc_regt, sc->sc_regh, reg); 1239 } 1240 1241 void 1242 radeonfb_put32(struct radeonfb_softc *sc, uint32_t reg, uint32_t val) 1243 { 1244 1245 bus_space_write_4(sc->sc_regt, sc->sc_regh, reg, val); 1246 } 1247 1248 void 1249 radeonfb_put32s(struct radeonfb_softc *sc, uint32_t reg, uint32_t val) 1250 { 1251 1252 bus_space_write_stream_4(sc->sc_regt, sc->sc_regh, reg, val); 1253 } 1254 1255 void 1256 radeonfb_mask32(struct radeonfb_softc *sc, uint32_t reg, 1257 uint32_t andmask, uint32_t ormask) 1258 { 1259 int s; 1260 uint32_t val; 1261 1262 s = splhigh(); 1263 val = radeonfb_get32(sc, reg); 1264 val = (val & andmask) | ormask; 1265 radeonfb_put32(sc, reg, val); 1266 splx(s); 1267 } 1268 1269 uint32_t 1270 radeonfb_getindex(struct radeonfb_softc *sc, uint32_t idx) 1271 { 1272 int s; 1273 uint32_t val; 1274 1275 s = splhigh(); 1276 radeonfb_put32(sc, RADEON_MM_INDEX, idx); 1277 val = radeonfb_get32(sc, RADEON_MM_DATA); 1278 splx(s); 1279 1280 return (val); 1281 } 1282 1283 void 1284 radeonfb_putindex(struct radeonfb_softc *sc, uint32_t idx, uint32_t val) 1285 { 1286 int s; 1287 1288 s = splhigh(); 1289 radeonfb_put32(sc, RADEON_MM_INDEX, idx); 1290 radeonfb_put32(sc, RADEON_MM_DATA, val); 1291 splx(s); 1292 } 1293 1294 void 1295 radeonfb_maskindex(struct radeonfb_softc *sc, uint32_t idx, 1296 uint32_t andmask, uint32_t ormask) 1297 { 1298 int s; 1299 uint32_t val; 1300 1301 s = splhigh(); 1302 radeonfb_put32(sc, RADEON_MM_INDEX, idx); 1303 val = radeonfb_get32(sc, RADEON_MM_DATA); 1304 val = (val & andmask) | ormask; 1305 radeonfb_put32(sc, RADEON_MM_DATA, val); 1306 splx(s); 1307 } 1308 1309 uint32_t 1310 radeonfb_getpll(struct radeonfb_softc *sc, uint32_t idx) 1311 { 1312 int s; 1313 uint32_t val; 1314 1315 s = splhigh(); 1316 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, idx & 0x3f); 1317 val = radeonfb_get32(sc, RADEON_CLOCK_CNTL_DATA); 1318 if (HAS_R300CG(sc)) 1319 radeonfb_r300cg_workaround(sc); 1320 splx(s); 1321 1322 return (val); 1323 } 1324 1325 void 1326 radeonfb_putpll(struct radeonfb_softc *sc, uint32_t idx, uint32_t val) 1327 { 1328 int s; 1329 1330 s = splhigh(); 1331 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, (idx & 0x3f) | 1332 RADEON_PLL_WR_EN); 1333 radeonfb_put32(sc, RADEON_CLOCK_CNTL_DATA, val); 1334 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, 0); 1335 splx(s); 1336 } 1337 1338 void 1339 radeonfb_maskpll(struct radeonfb_softc *sc, uint32_t idx, 1340 uint32_t andmask, uint32_t ormask) 1341 { 1342 int s; 1343 uint32_t val; 1344 1345 s = splhigh(); 1346 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, (idx & 0x3f) | 1347 RADEON_PLL_WR_EN); 1348 val = radeonfb_get32(sc, RADEON_CLOCK_CNTL_DATA); 1349 val = (val & andmask) | ormask; 1350 radeonfb_put32(sc, RADEON_CLOCK_CNTL_DATA, val); 1351 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, 0); 1352 splx(s); 1353 } 1354 1355 int 1356 radeonfb_scratch_test(struct radeonfb_softc *sc, int reg, uint32_t v) 1357 { 1358 uint32_t saved; 1359 1360 saved = GET32(sc, reg); 1361 PUT32(sc, reg, v); 1362 if (GET32(sc, reg) != v) { 1363 return -1; 1364 } 1365 PUT32(sc, reg, saved); 1366 return 0; 1367 } 1368 1369 uintmax_t 1370 radeonfb_getprop_num(struct radeonfb_softc *sc, const char *name, 1371 uintmax_t defval) 1372 { 1373 prop_number_t pn; 1374 pn = prop_dictionary_get(device_properties(sc->sc_dev), name); 1375 if (pn == NULL) { 1376 return defval; 1377 } 1378 KASSERT(prop_object_type(pn) == PROP_TYPE_NUMBER); 1379 return (prop_number_integer_value(pn)); 1380 } 1381 1382 int 1383 radeonfb_getclocks(struct radeonfb_softc *sc) 1384 { 1385 bus_addr_t ptr; 1386 int refclk = 0; 1387 int refdiv = 0; 1388 int minpll = 0; 1389 int maxpll = 0; 1390 1391 /* load initial property values if port/board provides them */ 1392 refclk = radeonfb_getprop_num(sc, "refclk", 0) & 0xffff; 1393 refdiv = radeonfb_getprop_num(sc, "refdiv", 0) & 0xffff; 1394 minpll = radeonfb_getprop_num(sc, "minpll", 0) & 0xffffffffU; 1395 maxpll = radeonfb_getprop_num(sc, "maxpll", 0) & 0xffffffffU; 1396 1397 if (refclk && refdiv && minpll && maxpll) 1398 goto dontprobe; 1399 1400 if (!sc->sc_biossz) { 1401 /* no BIOS */ 1402 aprint_verbose("%s: No video BIOS, using default clocks\n", 1403 XNAME(sc)); 1404 if (IS_IGP(sc)) 1405 refclk = refclk ? refclk : 1432; 1406 else 1407 refclk = refclk ? refclk : 2700; 1408 refdiv = refdiv ? refdiv : 12; 1409 minpll = minpll ? minpll : 12500; 1410 maxpll = maxpll ? maxpll : 35000; 1411 } else if (IS_ATOM(sc)) { 1412 /* ATOM BIOS */ 1413 ptr = GETBIOS16(sc, 0x48); 1414 ptr = GETBIOS16(sc, ptr + 32); /* aka MasterDataStart */ 1415 ptr = GETBIOS16(sc, ptr + 12); /* pll info block */ 1416 refclk = refclk ? refclk : GETBIOS16(sc, ptr + 82); 1417 minpll = minpll ? minpll : GETBIOS16(sc, ptr + 78); 1418 maxpll = maxpll ? maxpll : GETBIOS16(sc, ptr + 32); 1419 /* 1420 * ATOM BIOS doesn't supply a reference divider, so we 1421 * have to probe for it. 1422 */ 1423 if (refdiv < 2) 1424 refdiv = GETPLL(sc, RADEON_PPLL_REF_DIV) & 1425 RADEON_PPLL_REF_DIV_MASK; 1426 /* 1427 * if probe is zero, just assume one that should work 1428 * for most parts 1429 */ 1430 if (refdiv < 2) 1431 refdiv = 12; 1432 1433 } else { 1434 /* Legacy BIOS */ 1435 ptr = GETBIOS16(sc, 0x48); 1436 ptr = GETBIOS16(sc, ptr + 0x30); 1437 refclk = refclk ? refclk : GETBIOS16(sc, ptr + 0x0E); 1438 refdiv = refdiv ? refdiv : GETBIOS16(sc, ptr + 0x10); 1439 minpll = minpll ? minpll : GETBIOS32(sc, ptr + 0x12); 1440 maxpll = maxpll ? maxpll : GETBIOS32(sc, ptr + 0x16); 1441 } 1442 1443 1444 dontprobe: 1445 sc->sc_refclk = refclk * 10; 1446 sc->sc_refdiv = refdiv; 1447 sc->sc_minpll = minpll * 10; 1448 sc->sc_maxpll = maxpll * 10; 1449 return 0; 1450 } 1451 1452 int 1453 radeonfb_calc_dividers(struct radeonfb_softc *sc, uint32_t dotclock, 1454 uint32_t *postdivbit, uint32_t *feedbackdiv) 1455 { 1456 int i; 1457 uint32_t outfreq; 1458 int div; 1459 1460 DPRINTF(("dot clock: %u\n", dotclock)); 1461 for (i = 0; (div = radeonfb_dividers[i].divider) != 0; i++) { 1462 outfreq = div * dotclock; 1463 if ((outfreq >= sc->sc_minpll) && 1464 (outfreq <= sc->sc_maxpll)) { 1465 DPRINTF(("outfreq: %u\n", outfreq)); 1466 *postdivbit = 1467 ((uint32_t)radeonfb_dividers[i].mask << 16); 1468 DPRINTF(("post divider: %d (mask %x)\n", div, 1469 *postdivbit)); 1470 break; 1471 } 1472 } 1473 1474 if (div == 0) 1475 return 1; 1476 1477 *feedbackdiv = DIVIDE(sc->sc_refdiv * outfreq, sc->sc_refclk); 1478 DPRINTF(("feedback divider: %d\n", *feedbackdiv)); 1479 return 0; 1480 } 1481 1482 #if 0 1483 #ifdef RADEONFB_DEBUG 1484 static void 1485 dump_buffer(const char *pfx, void *buffer, unsigned int size) 1486 { 1487 char asc[17]; 1488 unsigned ptr = (unsigned)buffer; 1489 char *start = (char *)(ptr & ~0xf); 1490 char *end = (char *)(ptr + size); 1491 1492 end = (char *)(((unsigned)end + 0xf) & ~0xf); 1493 1494 if (pfx == NULL) { 1495 pfx = ""; 1496 } 1497 1498 while (start < end) { 1499 unsigned offset = (unsigned)start & 0xf; 1500 if (offset == 0) { 1501 printf("%s%x: ", pfx, (unsigned)start); 1502 } 1503 if (((unsigned)start < ptr) || 1504 ((unsigned)start >= (ptr + size))) { 1505 printf(" "); 1506 asc[offset] = ' '; 1507 } else { 1508 printf("%02x", *(unsigned char *)start); 1509 if ((*start >= ' ') && (*start <= '~')) { 1510 asc[offset] = *start; 1511 } else { 1512 asc[offset] = '.'; 1513 } 1514 } 1515 asc[offset + 1] = 0; 1516 if (offset % 2) { 1517 printf(" "); 1518 } 1519 if (offset == 15) { 1520 printf(" %s\n", asc); 1521 } 1522 start++; 1523 } 1524 } 1525 #endif 1526 #endif 1527 1528 int 1529 radeonfb_getconnectors(struct radeonfb_softc *sc) 1530 { 1531 int i; 1532 int found = 0; 1533 1534 for (i = 0; i < 2; i++) { 1535 sc->sc_ports[i].rp_mon_type = RADEON_MT_UNKNOWN; 1536 sc->sc_ports[i].rp_ddc_type = RADEON_DDC_NONE; 1537 sc->sc_ports[i].rp_dac_type = RADEON_DAC_UNKNOWN; 1538 sc->sc_ports[i].rp_conn_type = RADEON_CONN_NONE; 1539 sc->sc_ports[i].rp_tmds_type = RADEON_TMDS_UNKNOWN; 1540 } 1541 1542 /* 1543 * This logic is borrowed from Xorg's radeon driver. 1544 */ 1545 if (!sc->sc_biossz) 1546 goto nobios; 1547 1548 if (IS_ATOM(sc)) { 1549 /* not done yet */ 1550 } else { 1551 uint16_t ptr; 1552 int port = 0; 1553 1554 ptr = GETBIOS16(sc, 0x48); 1555 ptr = GETBIOS16(sc, ptr + 0x50); 1556 for (i = 1; i < 4; i++) { 1557 uint16_t entry; 1558 uint8_t conn, ddc, dac, tmds; 1559 1560 /* 1561 * Parse the connector table. From reading the code, 1562 * it appears to made up of 16-bit entries for each 1563 * connector. The 16-bits are defined as: 1564 * 1565 * bits 12-15 - connector type (0 == end of table) 1566 * bits 8-11 - DDC type 1567 * bits 5-7 - ??? 1568 * bit 4 - TMDS type (1 = EXT, 0 = INT) 1569 * bits 1-3 - ??? 1570 * bit 0 - DAC, 1 = TVDAC, 0 = primary 1571 */ 1572 if (!GETBIOS8(sc, ptr + i * 2) && i > 1) 1573 break; 1574 entry = GETBIOS16(sc, ptr + i * 2); 1575 1576 conn = (entry >> 12) & 0xf; 1577 ddc = (entry >> 8) & 0xf; 1578 dac = (entry & 0x1) ? RADEON_DAC_TVDAC : 1579 RADEON_DAC_PRIMARY; 1580 tmds = ((entry >> 4) & 0x1) ? RADEON_TMDS_EXT : 1581 RADEON_TMDS_INT; 1582 1583 if (conn == RADEON_CONN_NONE) 1584 continue; /* no connector */ 1585 1586 if ((found > 0) && 1587 (sc->sc_ports[port].rp_ddc_type == ddc)) { 1588 /* duplicate entry for same connector */ 1589 continue; 1590 } 1591 1592 /* internal DDC_DVI port gets priority */ 1593 if ((ddc == RADEON_DDC_DVI) || (port == 1)) 1594 port = 0; 1595 else 1596 port = 1; 1597 1598 sc->sc_ports[port].rp_ddc_type = 1599 ddc > RADEON_DDC_CRT2 ? RADEON_DDC_NONE : ddc; 1600 sc->sc_ports[port].rp_dac_type = dac; 1601 sc->sc_ports[port].rp_conn_type = 1602 min(conn, RADEON_CONN_UNSUPPORTED) ; 1603 1604 sc->sc_ports[port].rp_tmds_type = tmds; 1605 1606 if ((conn != RADEON_CONN_DVI_I) && 1607 (conn != RADEON_CONN_DVI_D) && 1608 (tmds == RADEON_TMDS_INT)) 1609 sc->sc_ports[port].rp_tmds_type = 1610 RADEON_TMDS_UNKNOWN; 1611 1612 found += (port + 1); 1613 } 1614 } 1615 1616 nobios: 1617 if (!found) { 1618 DPRINTF(("No connector info in BIOS!\n")); 1619 /* default, port 0 = internal TMDS, port 1 = CRT */ 1620 sc->sc_ports[0].rp_mon_type = RADEON_MT_UNKNOWN; 1621 sc->sc_ports[0].rp_ddc_type = RADEON_DDC_DVI; 1622 sc->sc_ports[0].rp_dac_type = RADEON_DAC_TVDAC; 1623 sc->sc_ports[0].rp_conn_type = RADEON_CONN_DVI_D; 1624 sc->sc_ports[0].rp_tmds_type = RADEON_TMDS_INT; 1625 1626 sc->sc_ports[1].rp_mon_type = RADEON_MT_UNKNOWN; 1627 sc->sc_ports[1].rp_ddc_type = RADEON_DDC_VGA; 1628 sc->sc_ports[1].rp_dac_type = RADEON_DAC_PRIMARY; 1629 sc->sc_ports[1].rp_conn_type = RADEON_CONN_CRT; 1630 sc->sc_ports[1].rp_tmds_type = RADEON_TMDS_EXT; 1631 } 1632 1633 /* 1634 * Fixup for RS300/RS350/RS400 chips, that lack a primary DAC. 1635 * these chips should use TVDAC for the VGA port. 1636 */ 1637 if (HAS_SDAC(sc)) { 1638 if (sc->sc_ports[0].rp_conn_type == RADEON_CONN_CRT) { 1639 sc->sc_ports[0].rp_dac_type = RADEON_DAC_TVDAC; 1640 sc->sc_ports[1].rp_dac_type = RADEON_DAC_PRIMARY; 1641 } else { 1642 sc->sc_ports[1].rp_dac_type = RADEON_DAC_TVDAC; 1643 sc->sc_ports[0].rp_dac_type = RADEON_DAC_PRIMARY; 1644 } 1645 } else if (!HAS_CRTC2(sc)) { 1646 sc->sc_ports[0].rp_dac_type = RADEON_DAC_PRIMARY; 1647 } 1648 1649 for (i = 0; i < 2; i++) { 1650 char edid[128]; 1651 uint8_t ddc; 1652 struct edid_info *eip = &sc->sc_ports[i].rp_edid; 1653 prop_data_t edid_data; 1654 1655 DPRINTF(("Port #%d:\n", i)); 1656 DPRINTF((" conn = %d\n", sc->sc_ports[i].rp_conn_type)); 1657 DPRINTF((" ddc = %d\n", sc->sc_ports[i].rp_ddc_type)); 1658 DPRINTF((" dac = %d\n", sc->sc_ports[i].rp_dac_type)); 1659 DPRINTF((" tmds = %d\n", sc->sc_ports[i].rp_tmds_type)); 1660 1661 sc->sc_ports[i].rp_edid_valid = 0; 1662 /* first look for static EDID data */ 1663 if ((edid_data = prop_dictionary_get(device_properties( 1664 sc->sc_dev), "EDID")) != NULL) { 1665 1666 aprint_normal_dev(sc->sc_dev, "using static EDID\n"); 1667 memcpy(edid, prop_data_data_nocopy(edid_data), 128); 1668 if (edid_parse(edid, eip) == 0) { 1669 1670 sc->sc_ports[i].rp_edid_valid = 1; 1671 } 1672 } 1673 /* if we didn't find any we'll try to talk to the monitor */ 1674 if (sc->sc_ports[i].rp_edid_valid != 1) { 1675 1676 ddc = sc->sc_ports[i].rp_ddc_type; 1677 if (ddc != RADEON_DDC_NONE) { 1678 if ((radeonfb_i2c_read_edid(sc, ddc, edid) 1679 == 0) && (edid_parse(edid, eip) == 0)) { 1680 1681 sc->sc_ports[i].rp_edid_valid = 1; 1682 edid_print(eip); 1683 } 1684 } 1685 } 1686 } 1687 1688 return found; 1689 } 1690 1691 int 1692 radeonfb_gettmds(struct radeonfb_softc *sc) 1693 { 1694 int i; 1695 1696 if (!sc->sc_biossz) { 1697 goto nobios; 1698 } 1699 1700 if (IS_ATOM(sc)) { 1701 /* XXX: not done yet */ 1702 } else { 1703 uint16_t ptr; 1704 int n; 1705 1706 ptr = GETBIOS16(sc, 0x48); 1707 ptr = GETBIOS16(sc, ptr + 0x34); 1708 DPRINTF(("DFP table revision %d\n", GETBIOS8(sc, ptr))); 1709 if (GETBIOS8(sc, ptr) == 3) { 1710 /* revision three table */ 1711 n = GETBIOS8(sc, ptr + 5) + 1; 1712 n = min(n, 4); 1713 1714 memset(sc->sc_tmds_pll, 0, sizeof (sc->sc_tmds_pll)); 1715 for (i = 0; i < n; i++) { 1716 sc->sc_tmds_pll[i].rtp_pll = GETBIOS32(sc, 1717 ptr + i * 10 + 8); 1718 sc->sc_tmds_pll[i].rtp_freq = GETBIOS16(sc, 1719 ptr + i * 10 + 0x10); 1720 DPRINTF(("TMDS_PLL dot clock %d pll %x\n", 1721 sc->sc_tmds_pll[i].rtp_freq, 1722 sc->sc_tmds_pll[i].rtp_pll)); 1723 } 1724 return 0; 1725 } 1726 } 1727 1728 nobios: 1729 DPRINTF(("no suitable DFP table present\n")); 1730 for (i = 0; 1731 i < sizeof (radeonfb_tmds_pll) / sizeof (radeonfb_tmds_pll[0]); 1732 i++) { 1733 int j; 1734 1735 if (radeonfb_tmds_pll[i].family != sc->sc_family) 1736 continue; 1737 1738 for (j = 0; j < 4; j++) { 1739 sc->sc_tmds_pll[j] = radeonfb_tmds_pll[i].plls[j]; 1740 DPRINTF(("TMDS_PLL dot clock %d pll %x\n", 1741 sc->sc_tmds_pll[j].rtp_freq, 1742 sc->sc_tmds_pll[j].rtp_pll)); 1743 } 1744 return 0; 1745 } 1746 1747 return -1; 1748 } 1749 1750 const struct videomode * 1751 radeonfb_modelookup(const char *name) 1752 { 1753 int i; 1754 1755 for (i = 0; i < videomode_count; i++) 1756 if (!strcmp(name, videomode_list[i].name)) 1757 return &videomode_list[i]; 1758 1759 return NULL; 1760 } 1761 1762 void 1763 radeonfb_pllwriteupdate(struct radeonfb_softc *sc, int crtc) 1764 { 1765 if (crtc) { 1766 while (GETPLL(sc, RADEON_P2PLL_REF_DIV) & 1767 RADEON_P2PLL_ATOMIC_UPDATE_R); 1768 SETPLL(sc, RADEON_P2PLL_REF_DIV, RADEON_P2PLL_ATOMIC_UPDATE_W); 1769 } else { 1770 while (GETPLL(sc, RADEON_PPLL_REF_DIV) & 1771 RADEON_PPLL_ATOMIC_UPDATE_R); 1772 SETPLL(sc, RADEON_PPLL_REF_DIV, RADEON_PPLL_ATOMIC_UPDATE_W); 1773 } 1774 } 1775 1776 void 1777 radeonfb_pllwaitatomicread(struct radeonfb_softc *sc, int crtc) 1778 { 1779 int i; 1780 1781 for (i = 10000; i; i--) { 1782 if (crtc) { 1783 if (GETPLL(sc, RADEON_P2PLL_REF_DIV) & 1784 RADEON_P2PLL_ATOMIC_UPDATE_R) 1785 break; 1786 } else { 1787 if (GETPLL(sc, RADEON_PPLL_REF_DIV) & 1788 RADEON_PPLL_ATOMIC_UPDATE_R) 1789 break; 1790 } 1791 } 1792 } 1793 1794 void 1795 radeonfb_program_vclk(struct radeonfb_softc *sc, int dotclock, int crtc) 1796 { 1797 uint32_t pbit = 0; 1798 uint32_t feed = 0; 1799 uint32_t data; 1800 #if 1 1801 int i; 1802 #endif 1803 1804 radeonfb_calc_dividers(sc, dotclock, &pbit, &feed); 1805 1806 if (crtc == 0) { 1807 1808 /* XXXX: mobility workaround missing */ 1809 /* XXXX: R300 stuff missing */ 1810 1811 PATCHPLL(sc, RADEON_VCLK_ECP_CNTL, 1812 RADEON_VCLK_SRC_SEL_CPUCLK, 1813 ~RADEON_VCLK_SRC_SEL_MASK); 1814 1815 /* put vclk into reset, use atomic updates */ 1816 SETPLL(sc, RADEON_PPLL_CNTL, 1817 RADEON_PPLL_REFCLK_SEL | 1818 RADEON_PPLL_FBCLK_SEL | 1819 RADEON_PPLL_RESET | 1820 RADEON_PPLL_ATOMIC_UPDATE_EN | 1821 RADEON_PPLL_VGA_ATOMIC_UPDATE_EN); 1822 1823 /* select clock 3 */ 1824 #if 0 1825 PATCH32(sc, RADEON_CLOCK_CNTL_INDEX, RADEON_PLL_DIV_SEL, 1826 ~RADEON_PLL_DIV_SEL); 1827 #else 1828 PATCH32(sc, RADEON_CLOCK_CNTL_INDEX, 0, 1829 ~RADEON_PLL_DIV_SEL); 1830 #endif 1831 1832 /* XXX: R300 family -- program divider differently? */ 1833 1834 /* program reference divider */ 1835 PATCHPLL(sc, RADEON_PPLL_REF_DIV, sc->sc_refdiv, 1836 ~RADEON_PPLL_REF_DIV_MASK); 1837 PRINTPLL(RADEON_PPLL_REF_DIV); 1838 1839 #if 0 1840 data = GETPLL(sc, RADEON_PPLL_DIV_3); 1841 data &= ~(RADEON_PPLL_FB3_DIV_MASK | 1842 RADEON_PPLL_POST3_DIV_MASK); 1843 data |= pbit; 1844 data |= (feed & RADEON_PPLL_FB3_DIV_MASK); 1845 PUTPLL(sc, RADEON_PPLL_DIV_3, data); 1846 #else 1847 for (i = 0; i < 4; i++) { 1848 } 1849 #endif 1850 1851 /* use the atomic update */ 1852 radeonfb_pllwriteupdate(sc, crtc); 1853 1854 /* and wait for it to complete */ 1855 radeonfb_pllwaitatomicread(sc, crtc); 1856 1857 /* program HTOTAL (why?) */ 1858 PUTPLL(sc, RADEON_HTOTAL_CNTL, 0); 1859 1860 /* drop reset */ 1861 CLRPLL(sc, RADEON_PPLL_CNTL, 1862 RADEON_PPLL_RESET | RADEON_PPLL_SLEEP | 1863 RADEON_PPLL_ATOMIC_UPDATE_EN | 1864 RADEON_PPLL_VGA_ATOMIC_UPDATE_EN); 1865 1866 PRINTPLL(RADEON_PPLL_CNTL); 1867 1868 /* give clock time to lock */ 1869 delay(50000); 1870 1871 PATCHPLL(sc, RADEON_VCLK_ECP_CNTL, 1872 RADEON_VCLK_SRC_SEL_PPLLCLK, 1873 ~RADEON_VCLK_SRC_SEL_MASK); 1874 1875 } else { 1876 1877 PATCHPLL(sc, RADEON_PIXCLKS_CNTL, 1878 RADEON_PIX2CLK_SRC_SEL_CPUCLK, 1879 ~RADEON_PIX2CLK_SRC_SEL_MASK); 1880 1881 /* put vclk into reset, use atomic updates */ 1882 SETPLL(sc, RADEON_P2PLL_CNTL, 1883 RADEON_P2PLL_RESET | 1884 RADEON_P2PLL_ATOMIC_UPDATE_EN | 1885 RADEON_P2PLL_VGA_ATOMIC_UPDATE_EN); 1886 1887 /* XXX: R300 family -- program divider differently? */ 1888 1889 /* program reference divider */ 1890 PATCHPLL(sc, RADEON_P2PLL_REF_DIV, sc->sc_refdiv, 1891 ~RADEON_P2PLL_REF_DIV_MASK); 1892 1893 /* program feedback and post dividers */ 1894 data = GETPLL(sc, RADEON_P2PLL_DIV_0); 1895 data &= ~(RADEON_P2PLL_FB0_DIV_MASK | 1896 RADEON_P2PLL_POST0_DIV_MASK); 1897 data |= pbit; 1898 data |= (feed & RADEON_P2PLL_FB0_DIV_MASK); 1899 PUTPLL(sc, RADEON_P2PLL_DIV_0, data); 1900 1901 /* use the atomic update */ 1902 radeonfb_pllwriteupdate(sc, crtc); 1903 1904 /* and wait for it to complete */ 1905 radeonfb_pllwaitatomicread(sc, crtc); 1906 1907 /* program HTOTAL (why?) */ 1908 PUTPLL(sc, RADEON_HTOTAL2_CNTL, 0); 1909 1910 /* drop reset */ 1911 CLRPLL(sc, RADEON_P2PLL_CNTL, 1912 RADEON_P2PLL_RESET | RADEON_P2PLL_SLEEP | 1913 RADEON_P2PLL_ATOMIC_UPDATE_EN | 1914 RADEON_P2PLL_VGA_ATOMIC_UPDATE_EN); 1915 1916 /* allow time for clock to lock */ 1917 delay(50000); 1918 1919 PATCHPLL(sc, RADEON_PIXCLKS_CNTL, 1920 RADEON_PIX2CLK_SRC_SEL_P2PLLCLK, 1921 ~RADEON_PIX2CLK_SRC_SEL_MASK); 1922 } 1923 PRINTREG(RADEON_CRTC_MORE_CNTL); 1924 } 1925 1926 void 1927 radeonfb_modeswitch(struct radeonfb_display *dp) 1928 { 1929 struct radeonfb_softc *sc = dp->rd_softc; 1930 int i; 1931 1932 /* blank the display while we switch modes */ 1933 radeonfb_blank(dp, 1); 1934 1935 #if 0 1936 SET32(sc, RADEON_CRTC_EXT_CNTL, 1937 RADEON_CRTC_VSYNC_DIS | RADEON_CRTC_HSYNC_DIS | 1938 RADEON_CRTC_DISPLAY_DIS /* | RADEON_CRTC_DISP_REQ_EN_B */); 1939 #endif 1940 1941 /* these registers might get in the way... */ 1942 PUT32(sc, RADEON_OVR_CLR, 0); 1943 PUT32(sc, RADEON_OVR_WID_LEFT_RIGHT, 0); 1944 PUT32(sc, RADEON_OVR_WID_TOP_BOTTOM, 0); 1945 PUT32(sc, RADEON_OV0_SCALE_CNTL, 0); 1946 PUT32(sc, RADEON_SUBPIC_CNTL, 0); 1947 PUT32(sc, RADEON_VIPH_CONTROL, 0); 1948 PUT32(sc, RADEON_I2C_CNTL_1, 0); 1949 PUT32(sc, RADEON_GEN_INT_CNTL, 0); 1950 PUT32(sc, RADEON_CAP0_TRIG_CNTL, 0); 1951 PUT32(sc, RADEON_CAP1_TRIG_CNTL, 0); 1952 PUT32(sc, RADEON_SURFACE_CNTL, 0); 1953 1954 for (i = 0; i < dp->rd_ncrtcs; i++) 1955 radeonfb_setcrtc(dp, i); 1956 1957 /* activate the display */ 1958 radeonfb_blank(dp, 0); 1959 } 1960 1961 void 1962 radeonfb_setcrtc(struct radeonfb_display *dp, int index) 1963 { 1964 int crtc; 1965 struct videomode *mode; 1966 struct radeonfb_softc *sc; 1967 struct radeonfb_crtc *cp; 1968 uint32_t v; 1969 uint32_t gencntl; 1970 uint32_t htotaldisp; 1971 uint32_t hsyncstrt; 1972 uint32_t vtotaldisp; 1973 uint32_t vsyncstrt; 1974 uint32_t fphsyncstrt; 1975 uint32_t fpvsyncstrt; 1976 uint32_t fphtotaldisp; 1977 uint32_t fpvtotaldisp; 1978 uint32_t pitch; 1979 1980 sc = dp->rd_softc; 1981 cp = &dp->rd_crtcs[index]; 1982 crtc = cp->rc_number; 1983 mode = &cp->rc_videomode; 1984 1985 #if 1 1986 pitch = (((dp->rd_virtx * dp->rd_bpp) + ((dp->rd_bpp * 8) - 1)) / 1987 (dp->rd_bpp * 8)); 1988 #else 1989 pitch = (((sc->sc_maxx * sc->sc_maxbpp) + ((sc->sc_maxbpp * 8) - 1)) / 1990 (sc->sc_maxbpp * 8)); 1991 #endif 1992 1993 switch (crtc) { 1994 case 0: 1995 gencntl = RADEON_CRTC_GEN_CNTL; 1996 htotaldisp = RADEON_CRTC_H_TOTAL_DISP; 1997 hsyncstrt = RADEON_CRTC_H_SYNC_STRT_WID; 1998 vtotaldisp = RADEON_CRTC_V_TOTAL_DISP; 1999 vsyncstrt = RADEON_CRTC_V_SYNC_STRT_WID; 2000 fpvsyncstrt = RADEON_FP_V_SYNC_STRT_WID; 2001 fphsyncstrt = RADEON_FP_H_SYNC_STRT_WID; 2002 fpvtotaldisp = RADEON_FP_CRTC_V_TOTAL_DISP; 2003 fphtotaldisp = RADEON_FP_CRTC_H_TOTAL_DISP; 2004 break; 2005 case 1: 2006 gencntl = RADEON_CRTC2_GEN_CNTL; 2007 htotaldisp = RADEON_CRTC2_H_TOTAL_DISP; 2008 hsyncstrt = RADEON_CRTC2_H_SYNC_STRT_WID; 2009 vtotaldisp = RADEON_CRTC2_V_TOTAL_DISP; 2010 vsyncstrt = RADEON_CRTC2_V_SYNC_STRT_WID; 2011 fpvsyncstrt = RADEON_FP_V2_SYNC_STRT_WID; 2012 fphsyncstrt = RADEON_FP_H2_SYNC_STRT_WID; 2013 fpvtotaldisp = RADEON_FP_CRTC2_V_TOTAL_DISP; 2014 fphtotaldisp = RADEON_FP_CRTC2_H_TOTAL_DISP; 2015 break; 2016 default: 2017 panic("Bad CRTC!"); 2018 break; 2019 } 2020 2021 /* 2022 * CRTC_GEN_CNTL - depth, accelerator mode, etc. 2023 */ 2024 /* only bother with 32bpp and 8bpp */ 2025 v = dp->rd_format << RADEON_CRTC_PIX_WIDTH_SHIFT; 2026 2027 if (crtc == 1) { 2028 v |= RADEON_CRTC2_CRT2_ON | RADEON_CRTC2_EN; 2029 } else { 2030 v |= RADEON_CRTC_EXT_DISP_EN | RADEON_CRTC_EN; 2031 } 2032 2033 if (mode->flags & VID_DBLSCAN) 2034 v |= RADEON_CRTC2_DBL_SCAN_EN; 2035 2036 if (mode->flags & VID_INTERLACE) 2037 v |= RADEON_CRTC2_INTERLACE_EN; 2038 2039 if (mode->flags & VID_CSYNC) { 2040 v |= RADEON_CRTC2_CSYNC_EN; 2041 if (crtc == 1) 2042 v |= RADEON_CRTC2_VSYNC_TRISTAT; 2043 } 2044 2045 PUT32(sc, gencntl, v); 2046 DPRINTF(("CRTC%s_GEN_CNTL = %08x\n", crtc ? "2" : "", v)); 2047 2048 /* 2049 * CRTC_EXT_CNTL - preserve disable flags, set ATI linear and EXT_CNT 2050 */ 2051 v = GET32(sc, RADEON_CRTC_EXT_CNTL); 2052 if (crtc == 0) { 2053 v &= (RADEON_CRTC_VSYNC_DIS | RADEON_CRTC_HSYNC_DIS | 2054 RADEON_CRTC_DISPLAY_DIS); 2055 v |= RADEON_XCRT_CNT_EN | RADEON_VGA_ATI_LINEAR; 2056 if (mode->flags & VID_CSYNC) 2057 v |= RADEON_CRTC_VSYNC_TRISTAT; 2058 } 2059 /* unconditional turn on CRT, in case first CRTC is DFP */ 2060 v |= RADEON_CRTC_CRT_ON; 2061 PUT32(sc, RADEON_CRTC_EXT_CNTL, v); 2062 PRINTREG(RADEON_CRTC_EXT_CNTL); 2063 2064 /* 2065 * H_TOTAL_DISP 2066 */ 2067 v = ((mode->hdisplay / 8) - 1) << 16; 2068 v |= (mode->htotal / 8) - 1; 2069 PUT32(sc, htotaldisp, v); 2070 DPRINTF(("CRTC%s_H_TOTAL_DISP = %08x\n", crtc ? "2" : "", v)); 2071 PUT32(sc, fphtotaldisp, v); 2072 DPRINTF(("FP_H%s_TOTAL_DISP = %08x\n", crtc ? "2" : "", v)); 2073 2074 /* 2075 * H_SYNC_STRT_WID 2076 */ 2077 v = (((mode->hsync_end - mode->hsync_start) / 8) << 16); 2078 v |= mode->hsync_start; 2079 if (mode->flags & VID_NHSYNC) 2080 v |= RADEON_CRTC_H_SYNC_POL; 2081 PUT32(sc, hsyncstrt, v); 2082 DPRINTF(("CRTC%s_H_SYNC_STRT_WID = %08x\n", crtc ? "2" : "", v)); 2083 PUT32(sc, fphsyncstrt, v); 2084 DPRINTF(("FP_H%s_SYNC_STRT_WID = %08x\n", crtc ? "2" : "", v)); 2085 2086 /* 2087 * V_TOTAL_DISP 2088 */ 2089 v = ((mode->vdisplay - 1) << 16); 2090 v |= (mode->vtotal - 1); 2091 PUT32(sc, vtotaldisp, v); 2092 DPRINTF(("CRTC%s_V_TOTAL_DISP = %08x\n", crtc ? "2" : "", v)); 2093 PUT32(sc, fpvtotaldisp, v); 2094 DPRINTF(("FP_V%s_TOTAL_DISP = %08x\n", crtc ? "2" : "", v)); 2095 2096 /* 2097 * V_SYNC_STRT_WID 2098 */ 2099 v = ((mode->vsync_end - mode->vsync_start) << 16); 2100 v |= (mode->vsync_start - 1); 2101 if (mode->flags & VID_NVSYNC) 2102 v |= RADEON_CRTC_V_SYNC_POL; 2103 PUT32(sc, vsyncstrt, v); 2104 DPRINTF(("CRTC%s_V_SYNC_STRT_WID = %08x\n", crtc ? "2" : "", v)); 2105 PUT32(sc, fpvsyncstrt, v); 2106 DPRINTF(("FP_V%s_SYNC_STRT_WID = %08x\n", crtc ? "2" : "", v)); 2107 2108 radeonfb_program_vclk(sc, mode->dot_clock, crtc); 2109 2110 switch (crtc) { 2111 case 0: 2112 PUT32(sc, RADEON_CRTC_OFFSET, 0); 2113 PUT32(sc, RADEON_CRTC_OFFSET_CNTL, 0); 2114 PUT32(sc, RADEON_CRTC_PITCH, pitch); 2115 CLR32(sc, RADEON_DISP_MERGE_CNTL, RADEON_DISP_RGB_OFFSET_EN); 2116 2117 CLR32(sc, RADEON_CRTC_EXT_CNTL, 2118 RADEON_CRTC_VSYNC_DIS | RADEON_CRTC_HSYNC_DIS | 2119 RADEON_CRTC_DISPLAY_DIS /* | RADEON_CRTC_DISP_REQ_EN_B */); 2120 CLR32(sc, RADEON_CRTC_GEN_CNTL, RADEON_CRTC_DISP_REQ_EN_B); 2121 PRINTREG(RADEON_CRTC_EXT_CNTL); 2122 PRINTREG(RADEON_CRTC_GEN_CNTL); 2123 PRINTREG(RADEON_CLOCK_CNTL_INDEX); 2124 break; 2125 2126 case 1: 2127 PUT32(sc, RADEON_CRTC2_OFFSET, 0); 2128 PUT32(sc, RADEON_CRTC2_OFFSET_CNTL, 0); 2129 PUT32(sc, RADEON_CRTC2_PITCH, pitch); 2130 CLR32(sc, RADEON_DISP2_MERGE_CNTL, RADEON_DISP2_RGB_OFFSET_EN); 2131 CLR32(sc, RADEON_CRTC2_GEN_CNTL, 2132 RADEON_CRTC2_VSYNC_DIS | 2133 RADEON_CRTC2_HSYNC_DIS | 2134 RADEON_CRTC2_DISP_DIS | RADEON_CRTC2_DISP_REQ_EN_B); 2135 PRINTREG(RADEON_CRTC2_GEN_CNTL); 2136 break; 2137 } 2138 } 2139 2140 int 2141 radeonfb_isblank(struct radeonfb_display *dp) 2142 { 2143 uint32_t reg, mask; 2144 2145 if (dp->rd_crtcs[0].rc_number) { 2146 reg = RADEON_CRTC2_GEN_CNTL; 2147 mask = RADEON_CRTC2_DISP_DIS; 2148 } else { 2149 reg = RADEON_CRTC_EXT_CNTL; 2150 mask = RADEON_CRTC_DISPLAY_DIS; 2151 } 2152 return ((GET32(dp->rd_softc, reg) & mask) ? 1 : 0); 2153 } 2154 2155 void 2156 radeonfb_blank(struct radeonfb_display *dp, int blank) 2157 { 2158 struct radeonfb_softc *sc = dp->rd_softc; 2159 uint32_t reg, mask; 2160 uint32_t fpreg, fpval; 2161 int i; 2162 2163 for (i = 0; i < dp->rd_ncrtcs; i++) { 2164 2165 if (dp->rd_crtcs[i].rc_number) { 2166 reg = RADEON_CRTC2_GEN_CNTL; 2167 mask = RADEON_CRTC2_DISP_DIS; 2168 fpreg = RADEON_FP2_GEN_CNTL; 2169 fpval = RADEON_FP2_ON; 2170 } else { 2171 reg = RADEON_CRTC_EXT_CNTL; 2172 mask = RADEON_CRTC_DISPLAY_DIS; 2173 fpreg = RADEON_FP_GEN_CNTL; 2174 fpval = RADEON_FP_FPON; 2175 } 2176 2177 if (blank) { 2178 SET32(sc, reg, mask); 2179 CLR32(sc, fpreg, fpval); 2180 } else { 2181 CLR32(sc, reg, mask); 2182 SET32(sc, fpreg, fpval); 2183 } 2184 } 2185 PRINTREG(RADEON_FP_GEN_CNTL); 2186 PRINTREG(RADEON_FP2_GEN_CNTL); 2187 } 2188 2189 void 2190 radeonfb_init_screen(void *cookie, struct vcons_screen *scr, int existing, 2191 long *defattr) 2192 { 2193 struct radeonfb_display *dp = cookie; 2194 struct rasops_info *ri = &scr->scr_ri; 2195 2196 /* initialize font subsystem */ 2197 wsfont_init(); 2198 2199 DPRINTF(("init screen called, existing %d\n", existing)); 2200 2201 ri->ri_depth = dp->rd_bpp; 2202 ri->ri_width = dp->rd_virtx; 2203 ri->ri_height = dp->rd_virty; 2204 ri->ri_stride = dp->rd_stride; 2205 ri->ri_flg = RI_CENTER; 2206 if (ri->ri_depth == 32) { 2207 ri->ri_flg |= RI_ENABLE_ALPHA; 2208 } 2209 if (ri->ri_depth == 8) { 2210 ri->ri_flg |= RI_ENABLE_ALPHA | RI_8BIT_IS_RGB; 2211 } 2212 ri->ri_bits = (void *)dp->rd_fbptr; 2213 2214 #ifdef VCONS_DRAW_INTR 2215 scr->scr_flags |= VCONS_DONT_READ; 2216 #endif 2217 2218 /* this is rgb in "big-endian order..." */ 2219 ri->ri_rnum = 8; 2220 ri->ri_gnum = 8; 2221 ri->ri_bnum = 8; 2222 ri->ri_rpos = 16; 2223 ri->ri_gpos = 8; 2224 ri->ri_bpos = 0; 2225 2226 if (existing) { 2227 ri->ri_flg |= RI_CLEAR; 2228 2229 /* start a modeswitch now */ 2230 radeonfb_modeswitch(dp); 2231 } 2232 2233 /* 2234 * XXX: font selection should be based on properties, with some 2235 * normal/reasonable default. 2236 */ 2237 2238 /* initialize and look for an initial font */ 2239 rasops_init(ri, 0, 0); 2240 ri->ri_caps = WSSCREEN_WSCOLORS; 2241 2242 rasops_reconfig(ri, dp->rd_virty / ri->ri_font->fontheight, 2243 dp->rd_virtx / ri->ri_font->fontwidth); 2244 2245 /* enable acceleration */ 2246 dp->rd_putchar = ri->ri_ops.putchar; 2247 ri->ri_ops.copyrows = radeonfb_copyrows; 2248 ri->ri_ops.copycols = radeonfb_copycols; 2249 ri->ri_ops.eraserows = radeonfb_eraserows; 2250 ri->ri_ops.erasecols = radeonfb_erasecols; 2251 /* pick a putchar method based on font and Radeon model */ 2252 if (ri->ri_font->stride < ri->ri_font->fontwidth) { 2253 /* got a bitmap font */ 2254 if (IS_R300(dp->rd_softc)) { 2255 /* 2256 * radeonfb_putchar() doesn't work right on some R3xx 2257 * so we use software drawing here, the wrapper just 2258 * makes sure the engine is idle before scribbling 2259 * into vram 2260 */ 2261 ri->ri_ops.putchar = radeonfb_putchar_wrapper; 2262 } else { 2263 ri->ri_ops.putchar = radeonfb_putchar; 2264 } 2265 } else { 2266 /* got an alpha font */ 2267 switch(ri->ri_depth) { 2268 case 32: 2269 ri->ri_ops.putchar = radeonfb_putchar_aa32; 2270 break; 2271 case 8: 2272 ri->ri_ops.putchar = radeonfb_putchar_aa8; 2273 break; 2274 default: 2275 /* XXX this should never happen */ 2276 panic("%s: depth is not 8 or 32 but we got an alpha font?!", 2277 __func__); 2278 } 2279 } 2280 ri->ri_ops.cursor = radeonfb_cursor; 2281 } 2282 2283 void 2284 radeonfb_set_fbloc(struct radeonfb_softc *sc) 2285 { 2286 uint32_t gen, ext, gen2 = 0; 2287 uint32_t agploc, aperbase, apersize, mcfbloc; 2288 2289 gen = GET32(sc, RADEON_CRTC_GEN_CNTL); 2290 ext = GET32(sc, RADEON_CRTC_EXT_CNTL); 2291 agploc = GET32(sc, RADEON_MC_AGP_LOCATION); 2292 aperbase = GET32(sc, RADEON_CONFIG_APER_0_BASE); 2293 apersize = GET32(sc, RADEON_CONFIG_APER_SIZE); 2294 2295 PUT32(sc, RADEON_CRTC_GEN_CNTL, gen | RADEON_CRTC_DISP_REQ_EN_B); 2296 PUT32(sc, RADEON_CRTC_EXT_CNTL, ext | RADEON_CRTC_DISPLAY_DIS); 2297 //PUT32(sc, RADEON_CRTC_GEN_CNTL, gen | RADEON_CRTC_DISPLAY_DIS); 2298 //PUT32(sc, RADEON_CRTC_EXT_CNTL, ext | RADEON_CRTC_DISP_REQ_EN_B); 2299 2300 if (HAS_CRTC2(sc)) { 2301 gen2 = GET32(sc, RADEON_CRTC2_GEN_CNTL); 2302 PUT32(sc, RADEON_CRTC2_GEN_CNTL, 2303 gen2 | RADEON_CRTC2_DISP_REQ_EN_B); 2304 } 2305 2306 delay(100000); 2307 2308 mcfbloc = (aperbase >> 16) | 2309 ((aperbase + (apersize - 1)) & 0xffff0000); 2310 2311 sc->sc_aperbase = (mcfbloc & 0xffff) << 16; 2312 sc->sc_memsz = apersize; 2313 2314 if (((agploc & 0xffff) << 16) != 2315 ((mcfbloc & 0xffff0000U) + 0x10000)) { 2316 agploc = mcfbloc & 0xffff0000U; 2317 agploc |= ((agploc + 0x10000) >> 16); 2318 } 2319 2320 PUT32(sc, RADEON_HOST_PATH_CNTL, 0); 2321 2322 PUT32(sc, RADEON_MC_FB_LOCATION, mcfbloc); 2323 PUT32(sc, RADEON_MC_AGP_LOCATION, agploc); 2324 2325 DPRINTF(("aperbase = %u\n", aperbase)); 2326 PRINTREG(RADEON_MC_FB_LOCATION); 2327 PRINTREG(RADEON_MC_AGP_LOCATION); 2328 2329 PUT32(sc, RADEON_DISPLAY_BASE_ADDR, sc->sc_aperbase); 2330 2331 if (HAS_CRTC2(sc)) 2332 PUT32(sc, RADEON_DISPLAY2_BASE_ADDR, sc->sc_aperbase); 2333 2334 PUT32(sc, RADEON_OV0_BASE_ADDR, sc->sc_aperbase); 2335 2336 #if 0 2337 /* XXX: what is this AGP garbage? :-) */ 2338 PUT32(sc, RADEON_AGP_CNTL, 0x00100000); 2339 #endif 2340 2341 delay(100000); 2342 2343 PUT32(sc, RADEON_CRTC_GEN_CNTL, gen); 2344 PUT32(sc, RADEON_CRTC_EXT_CNTL, ext); 2345 2346 if (HAS_CRTC2(sc)) 2347 PUT32(sc, RADEON_CRTC2_GEN_CNTL, gen2); 2348 } 2349 2350 void 2351 radeonfb_init_misc(struct radeonfb_softc *sc) 2352 { 2353 PUT32(sc, RADEON_BUS_CNTL, 2354 RADEON_BUS_MASTER_DIS | 2355 RADEON_BUS_PREFETCH_MODE_ACT | 2356 RADEON_BUS_PCI_READ_RETRY_EN | 2357 RADEON_BUS_PCI_WRT_RETRY_EN | 2358 (3 << RADEON_BUS_RETRY_WS_SHIFT) | 2359 RADEON_BUS_MSTR_RD_MULT | 2360 RADEON_BUS_MSTR_RD_LINE | 2361 RADEON_BUS_RD_DISCARD_EN | 2362 RADEON_BUS_MSTR_DISCONNECT_EN | 2363 RADEON_BUS_READ_BURST); 2364 2365 PUT32(sc, RADEON_BUS_CNTL1, 0xf0); 2366 /* PUT32(sc, RADEON_SEPROM_CNTL1, 0x09ff0000); */ 2367 PUT32(sc, RADEON_FCP_CNTL, RADEON_FCP0_SRC_GND); 2368 PUT32(sc, RADEON_RBBM_CNTL, 2369 (3 << RADEON_RB_SETTLE_SHIFT) | 2370 (4 << RADEON_ABORTCLKS_HI_SHIFT) | 2371 (4 << RADEON_ABORTCLKS_CP_SHIFT) | 2372 (4 << RADEON_ABORTCLKS_CFIFO_SHIFT)); 2373 2374 /* XXX: figure out what these mean! */ 2375 PUT32(sc, RADEON_AGP_CNTL, 0x00100000); 2376 PUT32(sc, RADEON_HOST_PATH_CNTL, 0); 2377 //PUT32(sc, RADEON_DISP_MISC_CNTL, 0x5bb00400); 2378 2379 PUT32(sc, RADEON_GEN_INT_CNTL, 0); 2380 PUT32(sc, RADEON_GEN_INT_STATUS, GET32(sc, RADEON_GEN_INT_STATUS)); 2381 } 2382 2383 /* 2384 * This loads a linear color map for true color. 2385 */ 2386 void 2387 radeonfb_init_palette(struct radeonfb_softc *sc, int crtc) 2388 { 2389 int i; 2390 uint32_t vclk; 2391 2392 #define DAC_WIDTH ((1 << 10) - 1) 2393 #define CLUT_WIDTH ((1 << 8) - 1) 2394 #define CLUT_COLOR(i) ((i * DAC_WIDTH * 2 / CLUT_WIDTH + 1) / 2) 2395 2396 vclk = GETPLL(sc, RADEON_VCLK_ECP_CNTL); 2397 PUTPLL(sc, RADEON_VCLK_ECP_CNTL, vclk & ~RADEON_PIXCLK_DAC_ALWAYS_ONb); 2398 2399 if (crtc) 2400 SET32(sc, RADEON_DAC_CNTL2, RADEON_DAC2_PALETTE_ACC_CTL); 2401 else 2402 CLR32(sc, RADEON_DAC_CNTL2, RADEON_DAC2_PALETTE_ACC_CTL); 2403 2404 PUT32(sc, RADEON_PALETTE_INDEX, 0); 2405 if (sc->sc_displays[crtc].rd_bpp == 0) 2406 sc->sc_displays[crtc].rd_bpp = RADEONFB_DEFAULT_DEPTH; 2407 2408 if (sc->sc_displays[crtc].rd_bpp == 8) { 2409 /* ANSI palette */ 2410 int j = 0; 2411 uint32_t tmp, r, g, b; 2412 2413 for (i = 0; i <= CLUT_WIDTH; ++i) { 2414 tmp = i & 0xe0; 2415 /* 2416 * replicate bits so 0xe0 maps to a red value of 0xff 2417 * in order to make white look actually white 2418 */ 2419 tmp |= (tmp >> 3) | (tmp >> 6); 2420 r = tmp; 2421 2422 tmp = (i & 0x1c) << 3; 2423 tmp |= (tmp >> 3) | (tmp >> 6); 2424 g = tmp; 2425 2426 tmp = (i & 0x03) << 6; 2427 tmp |= tmp >> 2; 2428 tmp |= tmp >> 4; 2429 b = tmp; 2430 PUT32(sc, RADEON_PALETTE_30_DATA, 2431 (r << 22) | 2432 (g << 12) | 2433 (b << 2)); 2434 j += 3; 2435 } 2436 } else { 2437 /* linear ramp */ 2438 for (i = 0; i <= CLUT_WIDTH; ++i) { 2439 PUT32(sc, RADEON_PALETTE_30_DATA, 2440 (CLUT_COLOR(i) << 10) | 2441 (CLUT_COLOR(i) << 20) | 2442 (CLUT_COLOR(i))); 2443 } 2444 } 2445 2446 CLR32(sc, RADEON_DAC_CNTL2, RADEON_DAC2_PALETTE_ACC_CTL); 2447 PRINTREG(RADEON_DAC_CNTL2); 2448 2449 PUTPLL(sc, RADEON_VCLK_ECP_CNTL, vclk); 2450 } 2451 2452 /* 2453 * Bugs in some R300 hardware requires this when accessing CLOCK_CNTL_INDEX. 2454 */ 2455 void 2456 radeonfb_r300cg_workaround(struct radeonfb_softc *sc) 2457 { 2458 uint32_t tmp, save; 2459 2460 save = GET32(sc, RADEON_CLOCK_CNTL_INDEX); 2461 tmp = save & ~(0x3f | RADEON_PLL_WR_EN); 2462 PUT32(sc, RADEON_CLOCK_CNTL_INDEX, tmp); 2463 tmp = GET32(sc, RADEON_CLOCK_CNTL_DATA); 2464 PUT32(sc, RADEON_CLOCK_CNTL_INDEX, save); 2465 } 2466 2467 /* 2468 * Acceleration entry points. 2469 */ 2470 2471 /* this one draws characters using bitmap fonts */ 2472 static void 2473 radeonfb_putchar(void *cookie, int row, int col, u_int c, long attr) 2474 { 2475 struct rasops_info *ri = cookie; 2476 struct vcons_screen *scr = ri->ri_hw; 2477 struct radeonfb_display *dp = scr->scr_cookie; 2478 struct radeonfb_softc *sc = dp->rd_softc; 2479 struct wsdisplay_font *font = PICK_FONT(ri, c); 2480 uint32_t w, h; 2481 int xd, yd, offset, i; 2482 uint32_t bg, fg, gmc; 2483 uint32_t reg; 2484 uint8_t *data8; 2485 uint16_t *data16; 2486 void *data; 2487 2488 if (dp->rd_wsmode != WSDISPLAYIO_MODE_EMUL) 2489 return; 2490 2491 if (!CHAR_IN_FONT(c, font)) 2492 return; 2493 2494 w = font->fontwidth; 2495 h = font->fontheight; 2496 2497 bg = ri->ri_devcmap[(attr >> 16) & 0xf]; 2498 fg = ri->ri_devcmap[(attr >> 24) & 0xf]; 2499 2500 xd = ri->ri_xorigin + col * w; 2501 yd = ri->ri_yorigin + row * h; 2502 2503 if (c == 0x20) { 2504 radeonfb_rectfill(dp, xd, yd, w, h, bg); 2505 return; 2506 } 2507 data = WSFONT_GLYPH(c, font); 2508 2509 gmc = dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT; 2510 2511 radeonfb_wait_fifo(sc, 9); 2512 2513 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 2514 RADEON_GMC_BRUSH_NONE | 2515 RADEON_GMC_SRC_DATATYPE_MONO_FG_BG | 2516 RADEON_GMC_DST_CLIPPING | 2517 RADEON_ROP3_S | 2518 RADEON_DP_SRC_SOURCE_HOST_DATA | 2519 RADEON_GMC_CLR_CMP_CNTL_DIS | 2520 RADEON_GMC_WR_MSK_DIS | 2521 gmc); 2522 2523 PUT32(sc, RADEON_SC_LEFT, xd); 2524 PUT32(sc, RADEON_SC_RIGHT, xd + w); 2525 PUT32(sc, RADEON_DP_SRC_FRGD_CLR, fg); 2526 PUT32(sc, RADEON_DP_SRC_BKGD_CLR, bg); 2527 PUT32(sc, RADEON_DP_CNTL, 2528 RADEON_DST_X_LEFT_TO_RIGHT | 2529 RADEON_DST_Y_TOP_TO_BOTTOM); 2530 2531 PUT32(sc, RADEON_SRC_X_Y, 0); 2532 offset = 32 - (font->stride << 3); 2533 PUT32(sc, RADEON_DST_X_Y, ((xd - offset) << 16) | yd); 2534 PUT32(sc, RADEON_DST_WIDTH_HEIGHT, (32 << 16) | h); 2535 2536 radeonfb_wait_fifo(sc, h); 2537 switch (font->stride) { 2538 case 1: { 2539 data8 = data; 2540 for (i = 0; i < h; i++) { 2541 reg = *data8; 2542 bus_space_write_stream_4(sc->sc_regt, 2543 sc->sc_regh, RADEON_HOST_DATA0, reg); 2544 data8++; 2545 } 2546 break; 2547 } 2548 case 2: { 2549 data16 = data; 2550 for (i = 0; i < h; i++) { 2551 reg = *data16; 2552 bus_space_write_stream_4(sc->sc_regt, 2553 sc->sc_regh, RADEON_HOST_DATA0, reg); 2554 data16++; 2555 } 2556 break; 2557 } 2558 } 2559 } 2560 2561 /* ... while this one is for anti-aliased ones */ 2562 static void 2563 radeonfb_putchar_aa32(void *cookie, int row, int col, u_int c, long attr) 2564 { 2565 struct rasops_info *ri = cookie; 2566 struct vcons_screen *scr = ri->ri_hw; 2567 struct radeonfb_display *dp = scr->scr_cookie; 2568 struct radeonfb_softc *sc = dp->rd_softc; 2569 struct wsdisplay_font *font = PICK_FONT(ri, c); 2570 uint32_t bg, fg, gmc; 2571 uint8_t *data; 2572 int w, h, xd, yd; 2573 int i, r, g, b, aval; 2574 int rf, gf, bf, rb, gb, bb; 2575 uint32_t pixel; 2576 int rv; 2577 2578 if (dp->rd_wsmode != WSDISPLAYIO_MODE_EMUL) 2579 return; 2580 2581 if (!CHAR_IN_FONT(c, font)) 2582 return; 2583 2584 w = font->fontwidth; 2585 h = font->fontheight; 2586 2587 bg = ri->ri_devcmap[(attr >> 16) & 0xf]; 2588 fg = ri->ri_devcmap[(attr >> 24) & 0xf]; 2589 2590 xd = ri->ri_xorigin + col * w; 2591 yd = ri->ri_yorigin + row * h; 2592 2593 if (c == 0x20) { 2594 radeonfb_rectfill(dp, xd, yd, w, h, bg); 2595 return; 2596 } 2597 rv = glyphcache_try(&dp->rd_gc, c, xd, yd, attr); 2598 if (rv == GC_OK) 2599 return; 2600 2601 data = WSFONT_GLYPH(c, font); 2602 2603 gmc = dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT; 2604 2605 radeonfb_wait_fifo(sc, 5); 2606 2607 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 2608 RADEON_GMC_BRUSH_NONE | 2609 RADEON_GMC_SRC_DATATYPE_COLOR | 2610 RADEON_ROP3_S | 2611 RADEON_DP_SRC_SOURCE_HOST_DATA | 2612 RADEON_GMC_CLR_CMP_CNTL_DIS | 2613 RADEON_GMC_WR_MSK_DIS | 2614 gmc); 2615 2616 PUT32(sc, RADEON_DP_CNTL, 2617 RADEON_DST_X_LEFT_TO_RIGHT | 2618 RADEON_DST_Y_TOP_TO_BOTTOM); 2619 2620 PUT32(sc, RADEON_SRC_X_Y, 0); 2621 PUT32(sc, RADEON_DST_X_Y, (xd << 16) | yd); 2622 PUT32(sc, RADEON_DST_WIDTH_HEIGHT, (w << 16) | h); 2623 2624 rf = (fg >> 16) & 0xff; 2625 rb = (bg >> 16) & 0xff; 2626 gf = (fg >> 8) & 0xff; 2627 gb = (bg >> 8) & 0xff; 2628 bf = fg & 0xff; 2629 bb = bg & 0xff; 2630 2631 /* 2632 * I doubt we can upload data faster than even the slowest Radeon 2633 * could process them, especially when doing the alpha blending stuff 2634 * along the way, so just make sure there's some room in the FIFO and 2635 * then hammer away 2636 * As it turns out we can, so make periodic stops to let the FIFO 2637 * drain. 2638 */ 2639 radeonfb_wait_fifo(sc, 20); 2640 for (i = 0; i < ri->ri_fontscale; i++) { 2641 aval = *data; 2642 data++; 2643 if (aval == 0) { 2644 pixel = bg; 2645 } else if (aval == 255) { 2646 pixel = fg; 2647 } else { 2648 r = aval * rf + (255 - aval) * rb; 2649 g = aval * gf + (255 - aval) * gb; 2650 b = aval * bf + (255 - aval) * bb; 2651 pixel = (r & 0xff00) << 8 | 2652 (g & 0xff00) | 2653 (b & 0xff00) >> 8; 2654 } 2655 if (i & 16) 2656 radeonfb_wait_fifo(sc, 20); 2657 PUT32(sc, RADEON_HOST_DATA0, pixel); 2658 } 2659 if (rv == GC_ADD) 2660 glyphcache_add(&dp->rd_gc, c, xd, yd); 2661 } 2662 2663 static void 2664 radeonfb_putchar_aa8(void *cookie, int row, int col, u_int c, long attr) 2665 { 2666 struct rasops_info *ri = cookie; 2667 struct vcons_screen *scr = ri->ri_hw; 2668 struct radeonfb_display *dp = scr->scr_cookie; 2669 struct radeonfb_softc *sc = dp->rd_softc; 2670 struct wsdisplay_font *font = PICK_FONT(ri, c); 2671 uint32_t bg, latch = 0, bg8, fg8, pixel, gmc; 2672 int i, x, y, wi, he, r, g, b, aval; 2673 int r1, g1, b1, r0, g0, b0, fgo, bgo; 2674 uint8_t *data8; 2675 int rv, cnt; 2676 2677 if (dp->rd_wsmode != WSDISPLAYIO_MODE_EMUL) 2678 return; 2679 2680 if (!CHAR_IN_FONT(c, font)) 2681 return; 2682 2683 wi = font->fontwidth; 2684 he = font->fontheight; 2685 2686 bg = ri->ri_devcmap[(attr >> 16) & 0xf]; 2687 2688 x = ri->ri_xorigin + col * wi; 2689 y = ri->ri_yorigin + row * he; 2690 2691 if (c == 0x20) { 2692 radeonfb_rectfill(dp, x, y, wi, he, bg); 2693 return; 2694 } 2695 rv = glyphcache_try(&dp->rd_gc, c, x, y, attr); 2696 if (rv == GC_OK) 2697 return; 2698 2699 data8 = WSFONT_GLYPH(c, font); 2700 2701 gmc = dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT; 2702 2703 radeonfb_wait_fifo(sc, 5); 2704 2705 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 2706 RADEON_GMC_BRUSH_NONE | 2707 RADEON_GMC_SRC_DATATYPE_COLOR | 2708 RADEON_ROP3_S | 2709 RADEON_DP_SRC_SOURCE_HOST_DATA | 2710 RADEON_GMC_CLR_CMP_CNTL_DIS | 2711 RADEON_GMC_WR_MSK_DIS | 2712 gmc); 2713 2714 PUT32(sc, RADEON_DP_CNTL, 2715 RADEON_DST_X_LEFT_TO_RIGHT | 2716 RADEON_DST_Y_TOP_TO_BOTTOM); 2717 2718 PUT32(sc, RADEON_SRC_X_Y, 0); 2719 PUT32(sc, RADEON_DST_X_Y, (x << 16) | y); 2720 PUT32(sc, RADEON_DST_WIDTH_HEIGHT, (wi << 16) | he); 2721 2722 /* 2723 * we need the RGB colours here, so get offsets into rasops_cmap 2724 */ 2725 fgo = ((attr >> 24) & 0xf) * 3; 2726 bgo = ((attr >> 16) & 0xf) * 3; 2727 2728 r0 = rasops_cmap[bgo]; 2729 r1 = rasops_cmap[fgo]; 2730 g0 = rasops_cmap[bgo + 1]; 2731 g1 = rasops_cmap[fgo + 1]; 2732 b0 = rasops_cmap[bgo + 2]; 2733 b1 = rasops_cmap[fgo + 2]; 2734 #define R3G3B2(r, g, b) ((r & 0xe0) | ((g >> 3) & 0x1c) | (b >> 6)) 2735 bg8 = R3G3B2(r0, g0, b0); 2736 fg8 = R3G3B2(r1, g1, b1); 2737 2738 radeonfb_wait_fifo(sc, 20); 2739 cnt = 0; 2740 for (i = 0; i < ri->ri_fontscale; i++) { 2741 aval = *data8; 2742 if (aval == 0) { 2743 pixel = bg8; 2744 } else if (aval == 255) { 2745 pixel = fg8; 2746 } else { 2747 r = aval * r1 + (255 - aval) * r0; 2748 g = aval * g1 + (255 - aval) * g0; 2749 b = aval * b1 + (255 - aval) * b0; 2750 pixel = ((r & 0xe000) >> 8) | 2751 ((g & 0xe000) >> 11) | 2752 ((b & 0xc000) >> 14); 2753 } 2754 latch = (latch << 8) | pixel; 2755 /* write in 32bit chunks */ 2756 if ((i & 3) == 3) { 2757 PUT32S(sc, RADEON_HOST_DATA0, latch); 2758 /* 2759 * not strictly necessary, old data should be shifted 2760 * out 2761 */ 2762 latch = 0; 2763 cnt++; 2764 if (cnt > 16) { 2765 cnt = 0; 2766 radeonfb_wait_fifo(sc, 20); 2767 } 2768 } 2769 data8++; 2770 } 2771 /* if we have pixels left in latch write them out */ 2772 if ((i & 3) != 0) { 2773 latch = latch << ((4 - (i & 3)) << 3); 2774 PUT32(sc, RADEON_HOST_DATA0, latch); 2775 } 2776 2777 if (rv == GC_ADD) 2778 glyphcache_add(&dp->rd_gc, c, x, y); 2779 } 2780 2781 /* 2782 * wrapper for software character drawing 2783 * just sync the engine and call rasops*_putchar() 2784 */ 2785 2786 static void 2787 radeonfb_putchar_wrapper(void *cookie, int row, int col, u_int c, long attr) 2788 { 2789 struct rasops_info *ri = cookie; 2790 struct vcons_screen *scr = ri->ri_hw; 2791 struct radeonfb_display *dp = scr->scr_cookie; 2792 2793 radeonfb_engine_idle(dp->rd_softc); 2794 dp->rd_putchar(ri, row, col, c, attr); 2795 } 2796 2797 static void 2798 radeonfb_eraserows(void *cookie, int row, int nrows, long fillattr) 2799 { 2800 struct rasops_info *ri = cookie; 2801 struct vcons_screen *scr = ri->ri_hw; 2802 struct radeonfb_display *dp = scr->scr_cookie; 2803 uint32_t x, y, w, h, fg, bg, ul; 2804 2805 /* XXX: check for full emulation mode? */ 2806 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 2807 x = ri->ri_xorigin; 2808 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 2809 w = ri->ri_emuwidth; 2810 h = ri->ri_font->fontheight * nrows; 2811 2812 rasops_unpack_attr(fillattr, &fg, &bg, &ul); 2813 radeonfb_rectfill(dp, x, y, w, h, ri->ri_devcmap[bg & 0xf]); 2814 } 2815 } 2816 2817 static void 2818 radeonfb_copyrows(void *cookie, int srcrow, int dstrow, int nrows) 2819 { 2820 struct rasops_info *ri = cookie; 2821 struct vcons_screen *scr = ri->ri_hw; 2822 struct radeonfb_display *dp = scr->scr_cookie; 2823 uint32_t x, ys, yd, w, h; 2824 2825 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 2826 x = ri->ri_xorigin; 2827 ys = ri->ri_yorigin + ri->ri_font->fontheight * srcrow; 2828 yd = ri->ri_yorigin + ri->ri_font->fontheight * dstrow; 2829 w = ri->ri_emuwidth; 2830 h = ri->ri_font->fontheight * nrows; 2831 radeonfb_bitblt(dp, x, ys, x, yd, w, h, 2832 RADEON_ROP3_S); 2833 } 2834 } 2835 2836 static void 2837 radeonfb_copycols(void *cookie, int row, int srccol, int dstcol, int ncols) 2838 { 2839 struct rasops_info *ri = cookie; 2840 struct vcons_screen *scr = ri->ri_hw; 2841 struct radeonfb_display *dp = scr->scr_cookie; 2842 uint32_t xs, xd, y, w, h; 2843 2844 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 2845 xs = ri->ri_xorigin + ri->ri_font->fontwidth * srccol; 2846 xd = ri->ri_xorigin + ri->ri_font->fontwidth * dstcol; 2847 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 2848 w = ri->ri_font->fontwidth * ncols; 2849 h = ri->ri_font->fontheight; 2850 radeonfb_bitblt(dp, xs, y, xd, y, w, h, 2851 RADEON_ROP3_S); 2852 } 2853 } 2854 2855 static void 2856 radeonfb_erasecols(void *cookie, int row, int startcol, int ncols, 2857 long fillattr) 2858 { 2859 struct rasops_info *ri = cookie; 2860 struct vcons_screen *scr = ri->ri_hw; 2861 struct radeonfb_display *dp = scr->scr_cookie; 2862 uint32_t x, y, w, h, fg, bg, ul; 2863 2864 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 2865 x = ri->ri_xorigin + ri->ri_font->fontwidth * startcol; 2866 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 2867 w = ri->ri_font->fontwidth * ncols; 2868 h = ri->ri_font->fontheight; 2869 2870 rasops_unpack_attr(fillattr, &fg, &bg, &ul); 2871 radeonfb_rectfill(dp, x, y, w, h, ri->ri_devcmap[bg & 0xf]); 2872 } 2873 } 2874 2875 static void 2876 radeonfb_cursor(void *cookie, int on, int row, int col) 2877 { 2878 struct rasops_info *ri = cookie; 2879 struct vcons_screen *scr = ri->ri_hw; 2880 struct radeonfb_display *dp = scr->scr_cookie; 2881 int x, y, wi, he; 2882 2883 wi = ri->ri_font->fontwidth; 2884 he = ri->ri_font->fontheight; 2885 2886 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 2887 x = ri->ri_ccol * wi + ri->ri_xorigin; 2888 y = ri->ri_crow * he + ri->ri_yorigin; 2889 /* first turn off the old cursor */ 2890 if (ri->ri_flg & RI_CURSOR) { 2891 radeonfb_bitblt(dp, x, y, x, y, wi, he, 2892 RADEON_ROP3_Dn); 2893 ri->ri_flg &= ~RI_CURSOR; 2894 } 2895 ri->ri_crow = row; 2896 ri->ri_ccol = col; 2897 /* then (possibly) turn on the new one */ 2898 if (on) { 2899 x = ri->ri_ccol * wi + ri->ri_xorigin; 2900 y = ri->ri_crow * he + ri->ri_yorigin; 2901 radeonfb_bitblt(dp, x, y, x, y, wi, he, 2902 RADEON_ROP3_Dn); 2903 ri->ri_flg |= RI_CURSOR; 2904 } 2905 } else { 2906 scr->scr_ri.ri_crow = row; 2907 scr->scr_ri.ri_ccol = col; 2908 scr->scr_ri.ri_flg &= ~RI_CURSOR; 2909 } 2910 } 2911 2912 /* 2913 * Underlying acceleration support. 2914 */ 2915 2916 static void 2917 radeonfb_rectfill(struct radeonfb_display *dp, int dstx, int dsty, 2918 int width, int height, uint32_t color) 2919 { 2920 struct radeonfb_softc *sc = dp->rd_softc; 2921 uint32_t gmc; 2922 2923 gmc = dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT; 2924 2925 radeonfb_wait_fifo(sc, 6); 2926 2927 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 2928 RADEON_GMC_BRUSH_SOLID_COLOR | 2929 RADEON_GMC_SRC_DATATYPE_COLOR | 2930 RADEON_GMC_CLR_CMP_CNTL_DIS | 2931 RADEON_ROP3_P | gmc); 2932 2933 PUT32(sc, RADEON_DP_BRUSH_FRGD_CLR, color); 2934 PUT32(sc, RADEON_DP_WRITE_MASK, 0xffffffff); 2935 PUT32(sc, RADEON_DP_CNTL, 2936 RADEON_DST_X_LEFT_TO_RIGHT | 2937 RADEON_DST_Y_TOP_TO_BOTTOM); 2938 PUT32(sc, RADEON_DST_Y_X, (dsty << 16) | dstx); 2939 PUT32(sc, RADEON_DST_WIDTH_HEIGHT, (width << 16) | (height)); 2940 2941 } 2942 2943 static void 2944 radeonfb_bitblt(void *cookie, int srcx, int srcy, 2945 int dstx, int dsty, int width, int height, int rop) 2946 { 2947 struct radeonfb_display *dp = cookie; 2948 struct radeonfb_softc *sc = dp->rd_softc; 2949 uint32_t gmc; 2950 uint32_t dir; 2951 2952 if (dsty < srcy) { 2953 dir = RADEON_DST_Y_TOP_TO_BOTTOM; 2954 } else { 2955 srcy += height - 1; 2956 dsty += height - 1; 2957 dir = 0; 2958 } 2959 if (dstx < srcx) { 2960 dir |= RADEON_DST_X_LEFT_TO_RIGHT; 2961 } else { 2962 srcx += width - 1; 2963 dstx += width - 1; 2964 } 2965 2966 gmc = dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT; 2967 2968 radeonfb_wait_fifo(sc, 6); 2969 2970 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 2971 RADEON_GMC_BRUSH_SOLID_COLOR | 2972 RADEON_GMC_SRC_DATATYPE_COLOR | 2973 RADEON_GMC_CLR_CMP_CNTL_DIS | 2974 RADEON_DP_SRC_SOURCE_MEMORY | 2975 rop | gmc); 2976 2977 PUT32(sc, RADEON_DP_WRITE_MASK, 0xffffffff); 2978 PUT32(sc, RADEON_DP_CNTL, dir); 2979 PUT32(sc, RADEON_SRC_Y_X, (srcy << 16) | srcx); 2980 PUT32(sc, RADEON_DST_Y_X, (dsty << 16) | dstx); 2981 PUT32(sc, RADEON_DST_WIDTH_HEIGHT, (width << 16) | (height)); 2982 } 2983 2984 static void 2985 radeonfb_engine_idle(struct radeonfb_softc *sc) 2986 { 2987 2988 radeonfb_wait_fifo(sc, 64); 2989 while ((GET32(sc, RADEON_RBBM_STATUS) & 2990 RADEON_RBBM_ACTIVE) != 0); 2991 radeonfb_engine_flush(sc); 2992 } 2993 2994 static inline void 2995 radeonfb_wait_fifo(struct radeonfb_softc *sc, int n) 2996 { 2997 int i; 2998 2999 for (i = RADEON_TIMEOUT; i; i--) { 3000 if ((GET32(sc, RADEON_RBBM_STATUS) & 3001 RADEON_RBBM_FIFOCNT_MASK) >= n) 3002 return; 3003 } 3004 #ifdef DIAGNOSTIC 3005 if (!i) 3006 printf("%s: timed out waiting for fifo (%x)\n", 3007 XNAME(sc), GET32(sc, RADEON_RBBM_STATUS)); 3008 #endif 3009 } 3010 3011 static void 3012 radeonfb_engine_flush(struct radeonfb_softc *sc) 3013 { 3014 int i = 0; 3015 3016 if (IS_R300(sc)) { 3017 SET32(sc, R300_DSTCACHE_CTLSTAT, R300_RB2D_DC_FLUSH_ALL); 3018 while (GET32(sc, R300_DSTCACHE_CTLSTAT) & R300_RB2D_DC_BUSY) { 3019 i++; 3020 } 3021 } else { 3022 SET32(sc, RADEON_RB2D_DSTCACHE_CTLSTAT, 3023 RADEON_RB2D_DC_FLUSH_ALL); 3024 while (GET32(sc, RADEON_RB2D_DSTCACHE_CTLSTAT) & 3025 RADEON_RB2D_DC_BUSY) { 3026 i++; 3027 } 3028 } 3029 #ifdef DIAGNOSTIC 3030 if (i > RADEON_TIMEOUT) 3031 printf("%s: engine flush timed out!\n", XNAME(sc)); 3032 #endif 3033 } 3034 3035 static inline void 3036 radeonfb_unclip(struct radeonfb_softc *sc) 3037 { 3038 3039 radeonfb_wait_fifo(sc, 2); 3040 PUT32(sc, RADEON_SC_TOP_LEFT, 0); 3041 PUT32(sc, RADEON_SC_BOTTOM_RIGHT, 0x1fff1fff); 3042 } 3043 3044 static void 3045 radeonfb_engine_init(struct radeonfb_display *dp) 3046 { 3047 struct radeonfb_softc *sc = dp->rd_softc; 3048 uint32_t pitch; 3049 volatile uint32_t junk; 3050 3051 /* no 3D */ 3052 PUT32(sc, RADEON_RB3D_CNTL, 0); 3053 3054 radeonfb_engine_reset(sc); 3055 pitch = ((dp->rd_virtx * (dp->rd_bpp / 8) + 0x3f)) >> 6; 3056 3057 radeonfb_wait_fifo(sc, 1); 3058 if (!IS_R300(sc)) 3059 PUT32(sc, RADEON_RB2D_DSTCACHE_MODE, 0); 3060 3061 radeonfb_wait_fifo(sc, 3); 3062 PUT32(sc, RADEON_DEFAULT_PITCH_OFFSET, 3063 (pitch << 22) | (sc->sc_aperbase >> 10)); 3064 3065 3066 PUT32(sc, RADEON_DST_PITCH_OFFSET, 3067 (pitch << 22) | (sc->sc_aperbase >> 10)); 3068 PUT32(sc, RADEON_SRC_PITCH_OFFSET, 3069 (pitch << 22) | (sc->sc_aperbase >> 10)); 3070 3071 radeonfb_wait_fifo(sc, 1); 3072 #if _BYTE_ORDER == _BIG_ENDIAN 3073 SET32(sc, RADEON_DP_DATATYPE, RADEON_HOST_BIG_ENDIAN_EN); 3074 #else 3075 CLR32(sc, RADEON_DP_DATATYPE, RADEON_HOST_BIG_ENDIAN_EN); 3076 #endif 3077 junk = GET32(sc, RADEON_DP_DATATYPE); 3078 3079 /* default scissors -- no clipping */ 3080 radeonfb_wait_fifo(sc, 1); 3081 PUT32(sc, RADEON_DEFAULT_SC_BOTTOM_RIGHT, 3082 RADEON_DEFAULT_SC_RIGHT_MAX | RADEON_DEFAULT_SC_BOTTOM_MAX); 3083 3084 radeonfb_wait_fifo(sc, 1); 3085 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 3086 (dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT) | 3087 RADEON_GMC_CLR_CMP_CNTL_DIS | 3088 RADEON_GMC_BRUSH_SOLID_COLOR | 3089 RADEON_GMC_SRC_DATATYPE_COLOR); 3090 3091 radeonfb_wait_fifo(sc, 10); 3092 PUT32(sc, RADEON_DST_LINE_START, 0); 3093 PUT32(sc, RADEON_DST_LINE_END, 0); 3094 PUT32(sc, RADEON_DP_BRUSH_FRGD_CLR, 0xffffffff); 3095 PUT32(sc, RADEON_DP_BRUSH_BKGD_CLR, 0); 3096 PUT32(sc, RADEON_DP_SRC_FRGD_CLR, 0xffffffff); 3097 PUT32(sc, RADEON_DP_SRC_BKGD_CLR, 0); 3098 PUT32(sc, RADEON_DP_WRITE_MASK, 0xffffffff); 3099 PUT32(sc, RADEON_SC_TOP_LEFT, 0); 3100 PUT32(sc, RADEON_SC_BOTTOM_RIGHT, 0x1fff1fff); 3101 PUT32(sc, RADEON_AUX_SC_CNTL, 0); 3102 radeonfb_engine_idle(sc); 3103 } 3104 3105 static void 3106 radeonfb_engine_reset(struct radeonfb_softc *sc) 3107 { 3108 uint32_t hpc, rbbm, mclkcntl, clkindex; 3109 3110 radeonfb_engine_flush(sc); 3111 3112 clkindex = GET32(sc, RADEON_CLOCK_CNTL_INDEX); 3113 if (HAS_R300CG(sc)) 3114 radeonfb_r300cg_workaround(sc); 3115 mclkcntl = GETPLL(sc, RADEON_MCLK_CNTL); 3116 3117 /* 3118 * According to comments in XFree code, resetting the HDP via 3119 * the RBBM_SOFT_RESET can cause bad behavior on some systems. 3120 * So we use HOST_PATH_CNTL instead. 3121 */ 3122 3123 hpc = GET32(sc, RADEON_HOST_PATH_CNTL); 3124 rbbm = GET32(sc, RADEON_RBBM_SOFT_RESET); 3125 if (IS_R300(sc)) { 3126 PUT32(sc, RADEON_RBBM_SOFT_RESET, rbbm | 3127 RADEON_SOFT_RESET_CP | 3128 RADEON_SOFT_RESET_HI | 3129 RADEON_SOFT_RESET_E2); 3130 GET32(sc, RADEON_RBBM_SOFT_RESET); 3131 PUT32(sc, RADEON_RBBM_SOFT_RESET, 0); 3132 /* 3133 * XXX: this bit is not defined in any ATI docs I have, 3134 * nor in the XFree code, but XFree does it. Why? 3135 */ 3136 SET32(sc, RADEON_RB2D_DSTCACHE_MODE, (1<<17)); 3137 } else { 3138 PUT32(sc, RADEON_RBBM_SOFT_RESET, rbbm | 3139 RADEON_SOFT_RESET_CP | 3140 RADEON_SOFT_RESET_SE | 3141 RADEON_SOFT_RESET_RE | 3142 RADEON_SOFT_RESET_PP | 3143 RADEON_SOFT_RESET_E2 | 3144 RADEON_SOFT_RESET_RB); 3145 GET32(sc, RADEON_RBBM_SOFT_RESET); 3146 PUT32(sc, RADEON_RBBM_SOFT_RESET, rbbm & 3147 ~(RADEON_SOFT_RESET_CP | 3148 RADEON_SOFT_RESET_SE | 3149 RADEON_SOFT_RESET_RE | 3150 RADEON_SOFT_RESET_PP | 3151 RADEON_SOFT_RESET_E2 | 3152 RADEON_SOFT_RESET_RB)); 3153 GET32(sc, RADEON_RBBM_SOFT_RESET); 3154 } 3155 3156 PUT32(sc, RADEON_HOST_PATH_CNTL, hpc | RADEON_HDP_SOFT_RESET); 3157 GET32(sc, RADEON_HOST_PATH_CNTL); 3158 PUT32(sc, RADEON_HOST_PATH_CNTL, hpc); 3159 3160 if (IS_R300(sc)) 3161 PUT32(sc, RADEON_RBBM_SOFT_RESET, rbbm); 3162 3163 PUT32(sc, RADEON_CLOCK_CNTL_INDEX, clkindex); 3164 PUTPLL(sc, RADEON_MCLK_CNTL, mclkcntl); 3165 3166 if (HAS_R300CG(sc)) 3167 radeonfb_r300cg_workaround(sc); 3168 } 3169 3170 static int 3171 radeonfb_set_curpos(struct radeonfb_display *dp, struct wsdisplay_curpos *pos) 3172 { 3173 int x, y; 3174 3175 x = pos->x; 3176 y = pos->y; 3177 3178 /* 3179 * This doesn't let a cursor move off the screen. I'm not 3180 * sure if this will have negative effects for e.g. Xinerama. 3181 * I'd guess Xinerama handles it by changing the cursor shape, 3182 * but that needs verification. 3183 */ 3184 if (x >= dp->rd_virtx) 3185 x = dp->rd_virtx - 1; 3186 if (x < 0) 3187 x = 0; 3188 if (y >= dp->rd_virty) 3189 y = dp->rd_virty - 1; 3190 if (y < 0) 3191 y = 0; 3192 3193 dp->rd_cursor.rc_pos.x = x; 3194 dp->rd_cursor.rc_pos.y = y; 3195 3196 radeonfb_cursor_position(dp); 3197 return 0; 3198 } 3199 3200 static int 3201 radeonfb_set_cursor(struct radeonfb_display *dp, struct wsdisplay_cursor *wc) 3202 { 3203 unsigned flags; 3204 3205 uint8_t r[2], g[2], b[2]; 3206 unsigned index, count; 3207 int i, err; 3208 int pitch, size; 3209 struct radeonfb_cursor nc; 3210 3211 flags = wc->which; 3212 3213 /* copy old values */ 3214 nc = dp->rd_cursor; 3215 3216 if (flags & WSDISPLAY_CURSOR_DOCMAP) { 3217 index = wc->cmap.index; 3218 count = wc->cmap.count; 3219 3220 if (index >= 2 || (index + count) > 2) 3221 return EINVAL; 3222 3223 err = copyin(wc->cmap.red, &r[index], count); 3224 if (err) 3225 return err; 3226 err = copyin(wc->cmap.green, &g[index], count); 3227 if (err) 3228 return err; 3229 err = copyin(wc->cmap.blue, &b[index], count); 3230 if (err) 3231 return err; 3232 3233 for (i = index; i < index + count; i++) { 3234 nc.rc_cmap[i] = 3235 (r[i] << 16) + (g[i] << 8) + (b[i] << 0); 3236 } 3237 } 3238 3239 if (flags & WSDISPLAY_CURSOR_DOSHAPE) { 3240 if ((wc->size.x > RADEON_CURSORMAXX) || 3241 (wc->size.y > RADEON_CURSORMAXY)) 3242 return EINVAL; 3243 3244 /* figure bytes per line */ 3245 pitch = (wc->size.x + 7) / 8; 3246 size = pitch * wc->size.y; 3247 3248 /* clear the old cursor and mask */ 3249 memset(nc.rc_image, 0, 512); 3250 memset(nc.rc_mask, 0, 512); 3251 3252 nc.rc_size = wc->size; 3253 3254 if ((err = copyin(wc->image, nc.rc_image, size)) != 0) 3255 return err; 3256 3257 if ((err = copyin(wc->mask, nc.rc_mask, size)) != 0) 3258 return err; 3259 } 3260 3261 if (flags & WSDISPLAY_CURSOR_DOHOT) { 3262 nc.rc_hot = wc->hot; 3263 if (nc.rc_hot.x >= nc.rc_size.x) 3264 nc.rc_hot.x = nc.rc_size.x - 1; 3265 if (nc.rc_hot.y >= nc.rc_size.y) 3266 nc.rc_hot.y = nc.rc_size.y - 1; 3267 } 3268 3269 if (flags & WSDISPLAY_CURSOR_DOPOS) { 3270 nc.rc_pos = wc->pos; 3271 if (nc.rc_pos.x >= dp->rd_virtx) 3272 nc.rc_pos.x = dp->rd_virtx - 1; 3273 #if 0 3274 if (nc.rc_pos.x < 0) 3275 nc.rc_pos.x = 0; 3276 #endif 3277 if (nc.rc_pos.y >= dp->rd_virty) 3278 nc.rc_pos.y = dp->rd_virty - 1; 3279 #if 0 3280 if (nc.rc_pos.y < 0) 3281 nc.rc_pos.y = 0; 3282 #endif 3283 } 3284 if (flags & WSDISPLAY_CURSOR_DOCUR) { 3285 nc.rc_visible = wc->enable; 3286 } 3287 3288 dp->rd_cursor = nc; 3289 radeonfb_cursor_update(dp, wc->which); 3290 3291 return 0; 3292 } 3293 3294 /* 3295 * Change the cursor shape. Call this with the cursor locked to avoid 3296 * flickering/tearing. 3297 */ 3298 static void 3299 radeonfb_cursor_shape(struct radeonfb_display *dp) 3300 { 3301 uint8_t and[512], xor[512]; 3302 int i, j, src, dst, pitch; 3303 const uint8_t *msk = dp->rd_cursor.rc_mask; 3304 const uint8_t *img = dp->rd_cursor.rc_image; 3305 3306 /* 3307 * Radeon cursor data interleaves one line of AND data followed 3308 * by a line of XOR data. (Each line corresponds to a whole hardware 3309 * pitch - i.e. 64 pixels or 8 bytes.) 3310 * 3311 * The cursor is displayed using the following table: 3312 * 3313 * AND XOR Result 3314 * ---------------------- 3315 * 0 0 Cursor color 0 3316 * 0 1 Cursor color 1 3317 * 1 0 Transparent 3318 * 1 1 Complement of background 3319 * 3320 * Our masks are therefore different from what we were passed. 3321 * Passed in, I'm assuming the data represents either color 0 or 1, 3322 * and a mask, so the passed in table looks like: 3323 * 3324 * IMG Mask Result 3325 * ----------------------- 3326 * 0 0 Transparent 3327 * 0 1 Cursor color 0 3328 * 1 0 Transparent 3329 * 1 1 Cursor color 1 3330 * 3331 * IF mask bit == 1, AND = 0, XOR = color. 3332 * IF mask bit == 0, AND = 1, XOR = 0. 3333 * 3334 * hence: AND = ~(mask); XOR = color & ~(mask); 3335 */ 3336 3337 pitch = ((dp->rd_cursor.rc_size.x + 7) / 8); 3338 3339 /* start by assuming all bits are transparent */ 3340 memset(and, 0xff, 512); 3341 memset(xor, 0x00, 512); 3342 3343 src = 0; 3344 dst = 0; 3345 for (i = 0; i < 64; i++) { 3346 for (j = 0; j < 64; j += 8) { 3347 if ((i < dp->rd_cursor.rc_size.y) && 3348 (j < dp->rd_cursor.rc_size.x)) { 3349 3350 /* take care to leave odd bits alone */ 3351 and[dst] &= ~(msk[src]); 3352 xor[dst] = img[src] & msk[src]; 3353 src++; 3354 } 3355 dst++; 3356 } 3357 } 3358 3359 /* copy the image into place */ 3360 for (i = 0; i < 64; i++) { 3361 memcpy((uint8_t *)dp->rd_curptr + (i * 16), 3362 &and[i * 8], 8); 3363 memcpy((uint8_t *)dp->rd_curptr + (i * 16) + 8, 3364 &xor[i * 8], 8); 3365 } 3366 } 3367 3368 static void 3369 radeonfb_cursor_position(struct radeonfb_display *dp) 3370 { 3371 struct radeonfb_softc *sc = dp->rd_softc; 3372 uint32_t offset, hvoff, hvpos; /* registers */ 3373 uint32_t coff; /* cursor offset */ 3374 int i, x, y, xoff, yoff, crtcoff; 3375 3376 /* 3377 * XXX: this also needs to handle pan/scan 3378 */ 3379 for (i = 0; i < dp->rd_ncrtcs; i++) { 3380 3381 struct radeonfb_crtc *rcp = &dp->rd_crtcs[i]; 3382 3383 if (rcp->rc_number) { 3384 offset = RADEON_CUR2_OFFSET; 3385 hvoff = RADEON_CUR2_HORZ_VERT_OFF; 3386 hvpos = RADEON_CUR2_HORZ_VERT_POSN; 3387 crtcoff = RADEON_CRTC2_OFFSET; 3388 } else { 3389 offset = RADEON_CUR_OFFSET; 3390 hvoff = RADEON_CUR_HORZ_VERT_OFF; 3391 hvpos = RADEON_CUR_HORZ_VERT_POSN; 3392 crtcoff = RADEON_CRTC_OFFSET; 3393 } 3394 3395 x = dp->rd_cursor.rc_pos.x; 3396 y = dp->rd_cursor.rc_pos.y; 3397 3398 while (y < rcp->rc_yoffset) { 3399 rcp->rc_yoffset -= RADEON_PANINCREMENT; 3400 } 3401 while (y >= (rcp->rc_yoffset + rcp->rc_videomode.vdisplay)) { 3402 rcp->rc_yoffset += RADEON_PANINCREMENT; 3403 } 3404 while (x < rcp->rc_xoffset) { 3405 rcp->rc_xoffset -= RADEON_PANINCREMENT; 3406 } 3407 while (x >= (rcp->rc_xoffset + rcp->rc_videomode.hdisplay)) { 3408 rcp->rc_xoffset += RADEON_PANINCREMENT; 3409 } 3410 3411 /* adjust for the cursor's hotspot */ 3412 x -= dp->rd_cursor.rc_hot.x; 3413 y -= dp->rd_cursor.rc_hot.y; 3414 xoff = yoff = 0; 3415 3416 if (x >= dp->rd_virtx) 3417 x = dp->rd_virtx - 1; 3418 if (y >= dp->rd_virty) 3419 y = dp->rd_virty - 1; 3420 3421 /* now adjust cursor so it is relative to viewport */ 3422 x -= rcp->rc_xoffset; 3423 y -= rcp->rc_yoffset; 3424 3425 /* 3426 * no need to check for fall off, because we should 3427 * never move off the screen entirely! 3428 */ 3429 coff = 0; 3430 if (x < 0) { 3431 xoff = -x; 3432 x = 0; 3433 } 3434 if (y < 0) { 3435 yoff = -y; 3436 y = 0; 3437 coff = (yoff * 2) * 8; 3438 } 3439 3440 /* pan the display */ 3441 PUT32(sc, crtcoff, (rcp->rc_yoffset * dp->rd_stride) + 3442 rcp->rc_xoffset); 3443 3444 PUT32(sc, offset, (dp->rd_curoff + coff) | RADEON_CUR_LOCK); 3445 PUT32(sc, hvoff, (xoff << 16) | (yoff) | RADEON_CUR_LOCK); 3446 /* NB: this unlocks the cursor */ 3447 PUT32(sc, hvpos, (x << 16) | y); 3448 } 3449 } 3450 3451 static void 3452 radeonfb_cursor_visible(struct radeonfb_display *dp) 3453 { 3454 int i; 3455 uint32_t gencntl, bit; 3456 3457 for (i = 0; i < dp->rd_ncrtcs; i++) { 3458 if (dp->rd_crtcs[i].rc_number) { 3459 gencntl = RADEON_CRTC2_GEN_CNTL; 3460 bit = RADEON_CRTC2_CUR_EN; 3461 } else { 3462 gencntl = RADEON_CRTC_GEN_CNTL; 3463 bit = RADEON_CRTC_CUR_EN; 3464 } 3465 3466 if (dp->rd_cursor.rc_visible) 3467 SET32(dp->rd_softc, gencntl, bit); 3468 else 3469 CLR32(dp->rd_softc, gencntl, bit); 3470 } 3471 } 3472 3473 static void 3474 radeonfb_cursor_cmap(struct radeonfb_display *dp) 3475 { 3476 int i; 3477 uint32_t c0reg, c1reg; 3478 struct radeonfb_softc *sc = dp->rd_softc; 3479 3480 for (i = 0; i < dp->rd_ncrtcs; i++) { 3481 if (dp->rd_crtcs[i].rc_number) { 3482 c0reg = RADEON_CUR2_CLR0; 3483 c1reg = RADEON_CUR2_CLR1; 3484 } else { 3485 c0reg = RADEON_CUR_CLR0; 3486 c1reg = RADEON_CUR_CLR1; 3487 } 3488 3489 PUT32(sc, c0reg, dp->rd_cursor.rc_cmap[0]); 3490 PUT32(sc, c1reg, dp->rd_cursor.rc_cmap[1]); 3491 } 3492 } 3493 3494 static void 3495 radeonfb_cursor_update(struct radeonfb_display *dp, unsigned which) 3496 { 3497 struct radeonfb_softc *sc; 3498 int i; 3499 3500 sc = dp->rd_softc; 3501 for (i = 0; i < dp->rd_ncrtcs; i++) { 3502 if (dp->rd_crtcs[i].rc_number) { 3503 SET32(sc, RADEON_CUR2_OFFSET, RADEON_CUR_LOCK); 3504 } else { 3505 SET32(sc, RADEON_CUR_OFFSET,RADEON_CUR_LOCK); 3506 } 3507 } 3508 3509 if (which & WSDISPLAY_CURSOR_DOCMAP) 3510 radeonfb_cursor_cmap(dp); 3511 3512 if (which & WSDISPLAY_CURSOR_DOSHAPE) 3513 radeonfb_cursor_shape(dp); 3514 3515 if (which & WSDISPLAY_CURSOR_DOCUR) 3516 radeonfb_cursor_visible(dp); 3517 3518 /* this one is unconditional, because it updates other stuff */ 3519 radeonfb_cursor_position(dp); 3520 } 3521 3522 static struct videomode * 3523 radeonfb_best_refresh(struct videomode *m1, struct videomode *m2) 3524 { 3525 int r1, r2; 3526 3527 /* otherwise pick the higher refresh rate */ 3528 r1 = DIVIDE(DIVIDE(m1->dot_clock, m1->htotal), m1->vtotal); 3529 r2 = DIVIDE(DIVIDE(m2->dot_clock, m2->htotal), m2->vtotal); 3530 3531 return (r1 < r2 ? m2 : m1); 3532 } 3533 3534 static const struct videomode * 3535 radeonfb_port_mode(struct radeonfb_softc *sc, struct radeonfb_port *rp, 3536 int x, int y) 3537 { 3538 struct edid_info *ep = &rp->rp_edid; 3539 struct videomode *vmp = NULL; 3540 int i; 3541 3542 if (!rp->rp_edid_valid) { 3543 /* fallback to safe mode */ 3544 return radeonfb_modelookup(sc->sc_defaultmode); 3545 } 3546 3547 /* always choose the preferred mode first! */ 3548 if (ep->edid_preferred_mode) { 3549 3550 /* XXX: add auto-stretching support for native mode */ 3551 3552 /* this may want panning to occur, btw */ 3553 if ((ep->edid_preferred_mode->hdisplay <= x) && 3554 (ep->edid_preferred_mode->vdisplay <= y)) 3555 return ep->edid_preferred_mode; 3556 } 3557 3558 for (i = 0; i < ep->edid_nmodes; i++) { 3559 /* 3560 * We elect to pick a resolution that is too large for 3561 * the monitor than one that is too small. This means 3562 * that we will prefer to pan rather than to try to 3563 * center a smaller display on a larger screen. In 3564 * practice, this shouldn't matter because if a 3565 * monitor can support a larger resolution, it can 3566 * probably also support the smaller. A specific 3567 * exception is fixed format panels, but hopefully 3568 * they are properly dealt with by the "autostretch" 3569 * logic above. 3570 */ 3571 if ((ep->edid_modes[i].hdisplay > x) || 3572 (ep->edid_modes[i].vdisplay > y)) { 3573 continue; 3574 } 3575 3576 /* 3577 * at this point, the display mode is no larger than 3578 * what we've requested. 3579 */ 3580 if (vmp == NULL) 3581 vmp = &ep->edid_modes[i]; 3582 3583 /* eliminate smaller modes */ 3584 if ((vmp->hdisplay >= ep->edid_modes[i].hdisplay) || 3585 (vmp->vdisplay >= ep->edid_modes[i].vdisplay)) 3586 continue; 3587 3588 if ((vmp->hdisplay < ep->edid_modes[i].hdisplay) || 3589 (vmp->vdisplay < ep->edid_modes[i].vdisplay)) { 3590 vmp = &ep->edid_modes[i]; 3591 continue; 3592 } 3593 3594 KASSERT(vmp->hdisplay == ep->edid_modes[i].hdisplay); 3595 KASSERT(vmp->vdisplay == ep->edid_modes[i].vdisplay); 3596 3597 vmp = radeonfb_best_refresh(vmp, &ep->edid_modes[i]); 3598 } 3599 3600 return (vmp ? vmp : radeonfb_modelookup(sc->sc_defaultmode)); 3601 } 3602 3603 static int 3604 radeonfb_hasres(struct videomode *list, int nlist, int x, int y) 3605 { 3606 int i; 3607 3608 for (i = 0; i < nlist; i++) { 3609 if ((x == list[i].hdisplay) && 3610 (y == list[i].vdisplay)) { 3611 return 1; 3612 } 3613 } 3614 return 0; 3615 } 3616 3617 static void 3618 radeonfb_pickres(struct radeonfb_display *dp, uint16_t *x, uint16_t *y, 3619 int pan) 3620 { 3621 struct radeonfb_port *rp; 3622 struct edid_info *ep; 3623 int i, j; 3624 3625 *x = 0; 3626 *y = 0; 3627 3628 if (pan) { 3629 for (i = 0; i < dp->rd_ncrtcs; i++) { 3630 rp = dp->rd_crtcs[i].rc_port; 3631 ep = &rp->rp_edid; 3632 if (!rp->rp_edid_valid) { 3633 /* monitor not present */ 3634 continue; 3635 } 3636 3637 /* 3638 * For now we are ignoring "conflict" that 3639 * could occur when mixing some modes like 3640 * 1280x1024 and 1400x800. It isn't clear 3641 * which is better, so the first one wins. 3642 */ 3643 for (j = 0; j < ep->edid_nmodes; j++) { 3644 /* 3645 * ignore resolutions that are too big for 3646 * the radeon 3647 */ 3648 if (ep->edid_modes[j].hdisplay > 3649 dp->rd_softc->sc_maxx) 3650 continue; 3651 if (ep->edid_modes[j].vdisplay > 3652 dp->rd_softc->sc_maxy) 3653 continue; 3654 3655 /* 3656 * pick largest resolution, the 3657 * smaller monitor will pan 3658 */ 3659 if ((ep->edid_modes[j].hdisplay >= *x) && 3660 (ep->edid_modes[j].vdisplay >= *y)) { 3661 *x = ep->edid_modes[j].hdisplay; 3662 *y = ep->edid_modes[j].vdisplay; 3663 } 3664 } 3665 } 3666 3667 } else { 3668 struct videomode modes[64]; 3669 int nmodes = 0; 3670 int valid = 0; 3671 3672 for (i = 0; i < dp->rd_ncrtcs; i++) { 3673 /* 3674 * pick the largest resolution in common. 3675 */ 3676 rp = dp->rd_crtcs[i].rc_port; 3677 ep = &rp->rp_edid; 3678 3679 if (!rp->rp_edid_valid) 3680 continue; 3681 3682 if (!valid) { 3683 /* 3684 * Pick the preferred mode for this port 3685 * if available. 3686 */ 3687 if (ep->edid_preferred_mode) { 3688 struct videomode *vmp = 3689 ep->edid_preferred_mode; 3690 3691 if ((vmp->hdisplay <= 3692 dp->rd_softc->sc_maxx) && 3693 (vmp->vdisplay <= 3694 dp->rd_softc->sc_maxy)) 3695 modes[nmodes++] = *vmp; 3696 } else { 3697 3698 /* initialize starting list */ 3699 for (j = 0; j < ep->edid_nmodes; j++) { 3700 /* 3701 * ignore resolutions that are 3702 * too big for the radeon 3703 */ 3704 if (ep->edid_modes[j].hdisplay > 3705 dp->rd_softc->sc_maxx) 3706 continue; 3707 if (ep->edid_modes[j].vdisplay > 3708 dp->rd_softc->sc_maxy) 3709 continue; 3710 3711 modes[nmodes] = 3712 ep->edid_modes[j]; 3713 nmodes++; 3714 } 3715 } 3716 valid = 1; 3717 } else { 3718 /* merge into preexisting list */ 3719 for (j = 0; j < nmodes; j++) { 3720 if (!radeonfb_hasres(ep->edid_modes, 3721 ep->edid_nmodes, 3722 modes[j].hdisplay, 3723 modes[j].vdisplay)) { 3724 modes[j] = modes[nmodes]; 3725 j--; 3726 nmodes--; 3727 } 3728 } 3729 } 3730 } 3731 3732 /* now we have to pick from the merged list */ 3733 for (i = 0; i < nmodes; i++) { 3734 if ((modes[i].hdisplay >= *x) && 3735 (modes[i].vdisplay >= *y)) { 3736 *x = modes[i].hdisplay; 3737 *y = modes[i].vdisplay; 3738 } 3739 } 3740 } 3741 3742 if ((*x == 0) || (*y == 0)) { 3743 /* fallback to safe mode */ 3744 *x = 640; 3745 *y = 480; 3746 } 3747 } 3748 3749 /* 3750 * backlight levels are linear on: 3751 * - RV200, RV250, RV280, RV350 3752 * - but NOT on PowerBook4,3 6,3 6,5 3753 * according to Linux' radeonfb 3754 */ 3755 3756 /* Get the current backlight level for the display. */ 3757 3758 static int 3759 radeonfb_get_backlight(struct radeonfb_display *dp) 3760 { 3761 int s; 3762 uint32_t level; 3763 3764 s = spltty(); 3765 3766 level = radeonfb_get32(dp->rd_softc, RADEON_LVDS_GEN_CNTL); 3767 level &= RADEON_LVDS_BL_MOD_LEV_MASK; 3768 level >>= RADEON_LVDS_BL_MOD_LEV_SHIFT; 3769 3770 /* 3771 * On some chips, we should negate the backlight level. 3772 * XXX Find out on which chips. 3773 */ 3774 if (dp->rd_softc->sc_flags & RFB_INV_BLIGHT) 3775 level = RADEONFB_BACKLIGHT_MAX - level; 3776 3777 splx(s); 3778 3779 return level; 3780 } 3781 3782 /* Set the backlight to the given level for the display. */ 3783 3784 static int 3785 radeonfb_set_backlight(struct radeonfb_display *dp, int level) 3786 { 3787 struct radeonfb_softc *sc; 3788 int rlevel, s; 3789 uint32_t lvds; 3790 3791 s = spltty(); 3792 3793 if (level < 0) 3794 level = 0; 3795 else if (level >= RADEONFB_BACKLIGHT_MAX) 3796 level = RADEONFB_BACKLIGHT_MAX; 3797 3798 sc = dp->rd_softc; 3799 3800 /* On some chips, we should negate the backlight level. */ 3801 if (dp->rd_softc->sc_flags & RFB_INV_BLIGHT) { 3802 rlevel = RADEONFB_BACKLIGHT_MAX - level; 3803 } else 3804 rlevel = level; 3805 3806 callout_stop(&dp->rd_bl_lvds_co); 3807 radeonfb_engine_idle(sc); 3808 3809 /* 3810 * Turn off the display if the backlight is set to 0, since the 3811 * display is useless without backlight anyway. 3812 */ 3813 if (level == 0) 3814 radeonfb_blank(dp, 1); 3815 else if (radeonfb_get_backlight(dp) == 0) 3816 radeonfb_blank(dp, 0); 3817 3818 lvds = radeonfb_get32(sc, RADEON_LVDS_GEN_CNTL); 3819 lvds &= ~RADEON_LVDS_DISPLAY_DIS; 3820 if (!(lvds & RADEON_LVDS_BLON) || !(lvds & RADEON_LVDS_ON)) { 3821 lvds |= dp->rd_bl_lvds_val & RADEON_LVDS_DIGON; 3822 lvds |= RADEON_LVDS_BLON | RADEON_LVDS_EN; 3823 radeonfb_put32(sc, RADEON_LVDS_GEN_CNTL, lvds); 3824 lvds &= ~RADEON_LVDS_BL_MOD_LEV_MASK; 3825 lvds |= rlevel << RADEON_LVDS_BL_MOD_LEV_SHIFT; 3826 lvds |= RADEON_LVDS_ON; 3827 lvds |= dp->rd_bl_lvds_val & RADEON_LVDS_BL_MOD_EN; 3828 } else { 3829 lvds &= ~RADEON_LVDS_BL_MOD_LEV_MASK; 3830 lvds |= rlevel << RADEON_LVDS_BL_MOD_LEV_SHIFT; 3831 radeonfb_put32(sc, RADEON_LVDS_GEN_CNTL, lvds); 3832 } 3833 3834 dp->rd_bl_lvds_val &= ~RADEON_LVDS_STATE_MASK; 3835 dp->rd_bl_lvds_val |= lvds & RADEON_LVDS_STATE_MASK; 3836 /* XXX What is the correct delay? */ 3837 callout_schedule(&dp->rd_bl_lvds_co, 200 * hz); 3838 3839 splx(s); 3840 3841 return 0; 3842 } 3843 3844 /* 3845 * Callout function for delayed operations on the LVDS_GEN_CNTL register. 3846 * Set the delayed bits in the register, and clear the stored delayed 3847 * value. 3848 */ 3849 3850 static void radeonfb_lvds_callout(void *arg) 3851 { 3852 struct radeonfb_display *dp = arg; 3853 int s; 3854 3855 s = splhigh(); 3856 3857 radeonfb_mask32(dp->rd_softc, RADEON_LVDS_GEN_CNTL, ~0, 3858 dp->rd_bl_lvds_val); 3859 dp->rd_bl_lvds_val = 0; 3860 3861 splx(s); 3862 } 3863 3864 static void 3865 radeonfb_brightness_up(device_t dev) 3866 { 3867 struct radeonfb_softc *sc = device_private(dev); 3868 int level; 3869 3870 /* we assume the main display is the first one - need a better way */ 3871 if (sc->sc_ndisplays < 1) return; 3872 level = radeonfb_get_backlight(&sc->sc_displays[0]); 3873 level = min(RADEONFB_BACKLIGHT_MAX, level + 5); 3874 radeonfb_set_backlight(&sc->sc_displays[0], level); 3875 } 3876 3877 static void 3878 radeonfb_brightness_down(device_t dev) 3879 { 3880 struct radeonfb_softc *sc = device_private(dev); 3881 int level; 3882 3883 /* we assume the main display is the first one - need a better way */ 3884 if (sc->sc_ndisplays < 1) return; 3885 level = radeonfb_get_backlight(&sc->sc_displays[0]); 3886 level = max(0, level - 5); 3887 radeonfb_set_backlight(&sc->sc_displays[0], level); 3888 } 3889
Indexes created Fri Sep 26 08:10:20 GMT 2025