radeonfb.c revision 1.6
1 /* $NetBSD: radeonfb.c,v 1.6 2006/10/07 21:36:12 gdamore Exp $ */ 2 3 /*- 4 * Copyright (c) 2006 Itronix Inc. 5 * All rights reserved. 6 * 7 * Written by Garrett D'Amore for Itronix Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. The name of Itronix Inc. may not be used to endorse 18 * or promote products derived from this software without specific 19 * prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY ITRONIX INC. ``AS IS'' AND ANY EXPRESS 22 * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 23 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL ITRONIX INC. BE LIABLE FOR ANY 25 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE 27 * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 29 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 30 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 31 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * ATI Technologies Inc. ("ATI") has not assisted in the creation of, and 36 * does not endorse, this software. ATI will not be responsible or liable 37 * for any actual or alleged damage or loss caused by or in connection with 38 * the use of or reliance on this software. 39 */ 40 41 /* 42 * Portions of this code were taken from XFree86's Radeon driver, which bears 43 * this notice: 44 * 45 * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and 46 * VA Linux Systems Inc., Fremont, California. 47 * 48 * All Rights Reserved. 49 * 50 * Permission is hereby granted, free of charge, to any person obtaining 51 * a copy of this software and associated documentation files (the 52 * "Software"), to deal in the Software without restriction, including 53 * without limitation on the rights to use, copy, modify, merge, 54 * publish, distribute, sublicense, and/or sell copies of the Software, 55 * and to permit persons to whom the Software is furnished to do so, 56 * subject to the following conditions: 57 * 58 * The above copyright notice and this permission notice (including the 59 * next paragraph) shall be included in all copies or substantial 60 * portions of the Software. 61 * 62 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 63 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 64 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 65 * NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR 66 * THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 67 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 68 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 69 * DEALINGS IN THE SOFTWARE. 70 */ 71 72 #include <sys/cdefs.h> 73 __KERNEL_RCSID(0, "$NetBSD: radeonfb.c,v 1.6 2006/10/07 21:36:12 gdamore Exp $"); 74 75 #define RADEONFB_DEFAULT_DEPTH 32 76 77 #include <sys/param.h> 78 #include <sys/systm.h> 79 #include <sys/device.h> 80 #include <sys/malloc.h> 81 #include <machine/bus.h> 82 #include <sys/kernel.h> 83 #include <sys/lwp.h> 84 #include <sys/kauth.h> 85 86 #include <dev/wscons/wsdisplayvar.h> 87 #include <dev/wscons/wsconsio.h> 88 #include <dev/wsfont/wsfont.h> 89 #include <dev/rasops/rasops.h> 90 #include <dev/videomode/videomode.h> 91 #include <dev/videomode/edidvar.h> 92 #include <dev/wscons/wsdisplay_vconsvar.h> 93 94 #include <dev/pci/pcidevs.h> 95 #include <dev/pci/pcireg.h> 96 #include <dev/pci/pcivar.h> 97 #include <dev/pci/radeonfbreg.h> 98 #include <dev/pci/radeonfbvar.h> 99 100 static int radeonfb_match(struct device *, struct cfdata *, void *); 101 static void radeonfb_attach(struct device *, struct device *, void *); 102 static int radeonfb_ioctl(void *, void *, unsigned long, caddr_t, int, 103 struct lwp *); 104 static paddr_t radeonfb_mmap(void *, void *, off_t, int); 105 static int radeonfb_scratch_test(struct radeonfb_softc *, int, uint32_t); 106 static void radeonfb_loadbios(struct radeonfb_softc *, 107 struct pci_attach_args *); 108 109 static uintmax_t radeonfb_getprop_num(struct radeonfb_softc *, const char *, 110 uintmax_t); 111 static int radeonfb_getclocks(struct radeonfb_softc *); 112 static int radeonfb_gettmds(struct radeonfb_softc *); 113 static int radeonfb_calc_dividers(struct radeonfb_softc *, uint32_t, 114 uint32_t *, uint32_t *); 115 static int radeonfb_getconnectors(struct radeonfb_softc *); 116 static const struct videomode *radeonfb_modelookup(const char *); 117 static void radeonfb_init_screen(void *, struct vcons_screen *, int, long *); 118 static void radeonfb_pllwriteupdate(struct radeonfb_softc *, int); 119 static void radeonfb_pllwaitatomicread(struct radeonfb_softc *, int); 120 static void radeonfb_program_vclk(struct radeonfb_softc *, int, int); 121 static void radeonfb_modeswitch(struct radeonfb_display *); 122 static void radeonfb_setcrtc(struct radeonfb_display *, int); 123 static void radeonfb_init_misc(struct radeonfb_softc *); 124 static void radeonfb_set_fbloc(struct radeonfb_softc *); 125 static void radeonfb_init_palette(struct radeonfb_softc *, int); 126 static void radeonfb_r300cg_workaround(struct radeonfb_softc *); 127 128 static int radeonfb_isblank(struct radeonfb_display *); 129 static void radeonfb_blank(struct radeonfb_display *, int); 130 static int radeonfb_set_cursor(struct radeonfb_display *, 131 struct wsdisplay_cursor *); 132 static int radeonfb_set_curpos(struct radeonfb_display *, 133 struct wsdisplay_curpos *); 134 135 /* acceleration support */ 136 static void radeonfb_rectfill(struct radeonfb_display *, int dstx, int dsty, 137 int width, int height, uint32_t color); 138 static void radeonfb_bitblt(struct radeonfb_display *, int srcx, int srcy, 139 int dstx, int dsty, int width, int height, int rop, uint32_t mask); 140 static void radeonfb_feed_bytes(struct radeonfb_display *, int, uint8_t *); 141 static void radeonfb_setup_mono(struct radeonfb_display *, int, int, int, 142 int, uint32_t, uint32_t); 143 144 /* hw cursor support */ 145 static void radeonfb_cursor_cmap(struct radeonfb_display *); 146 static void radeonfb_cursor_shape(struct radeonfb_display *); 147 static void radeonfb_cursor_position(struct radeonfb_display *); 148 static void radeonfb_cursor_visible(struct radeonfb_display *); 149 static void radeonfb_cursor_update(struct radeonfb_display *, unsigned); 150 151 static void radeonfb_wait_fifo(struct radeonfb_softc *, int); 152 static void radeonfb_engine_idle(struct radeonfb_softc *); 153 static void radeonfb_engine_flush(struct radeonfb_softc *); 154 static void radeonfb_engine_reset(struct radeonfb_softc *); 155 static void radeonfb_engine_init(struct radeonfb_display *); 156 static inline void radeonfb_unclip(struct radeonfb_softc *); 157 158 static void radeonfb_eraserows(void *, int, int, long); 159 static void radeonfb_erasecols(void *, int, int, int, long); 160 static void radeonfb_copyrows(void *, int, int, int); 161 static void radeonfb_copycols(void *, int, int, int, int); 162 static void radeonfb_cursor(void *, int, int, int); 163 static void radeonfb_putchar(void *, int, int, unsigned, long); 164 static int radeonfb_allocattr(void *, int, int, int, long *); 165 166 static struct videomode *radeonfb_best_refresh(struct videomode *, 167 struct videomode *); 168 static void radeonfb_pickres(struct radeonfb_display *, uint16_t *, 169 uint16_t *, int); 170 static const struct videomode *radeonfb_port_mode(struct radeonfb_port *, 171 int, int); 172 173 174 #define RADEON_DEBUG 175 #ifdef RADEON_DEBUG 176 int radeon_debug = 1; 177 #define DPRINTF(x) \ 178 if (radeon_debug) printf x 179 #define PRINTREG(r) DPRINTF((#r " = %08x\n", GET32(sc, r))) 180 #define PRINTPLL(r) DPRINTF((#r " = %08x\n", GETPLL(sc, r))) 181 #else 182 #define DPRINTF(x) 183 #define PRINTREG(r) 184 #define PRINTPLL(r) 185 #endif 186 187 #define ROUNDUP(x,y) (((x) + ((y) - 1)) & ~((y) - 1)) 188 189 #ifndef RADEON_DEFAULT_MODE 190 /* any reasonably modern display should handle this */ 191 #define RADEON_DEFAULT_MODE "1024x768x60" 192 //#define RADEON_DEFAULT_MODE "1280x1024x60" 193 #endif 194 195 const char *radeonfb_default_mode = RADEON_DEFAULT_MODE; 196 197 static struct { 198 int size; /* minimum memory size (MB) */ 199 int maxx; /* maximum x dimension */ 200 int maxy; /* maximum y dimension */ 201 int maxbpp; /* maximum bpp */ 202 int maxdisp; /* maximum logical display count */ 203 } radeonfb_limits[] = { 204 { 32, 2048, 1536, 32, 2 }, 205 { 16, 1600, 1200, 32, 2 }, 206 { 8, 1600, 1200, 32, 1 }, 207 { 0, 0, 0, 0 }, 208 }; 209 210 static struct wsscreen_descr radeonfb_stdscreen = { 211 "fb", /* name */ 212 0, 0, /* ncols, nrows */ 213 NULL, /* textops */ 214 8, 16, /* fontwidth, fontheight */ 215 WSSCREEN_WSCOLORS, 216 }; 217 218 struct wsdisplay_accessops radeonfb_accessops = { 219 radeonfb_ioctl, 220 radeonfb_mmap, 221 NULL, /* vcons_alloc_screen */ 222 NULL, /* vcons_free_screen */ 223 NULL, /* vcons_show_screen */ 224 NULL /* load_font */ 225 }; 226 227 static struct { 228 uint16_t devid; 229 uint16_t family; 230 uint16_t flags; 231 } radeonfb_devices[] = 232 { 233 /* R100 family */ 234 { PCI_PRODUCT_ATI_RADEON_R100_QD, RADEON_R100, 0 }, 235 { PCI_PRODUCT_ATI_RADEON_R100_QE, RADEON_R100, 0 }, 236 { PCI_PRODUCT_ATI_RADEON_R100_QF, RADEON_R100, 0 }, 237 { PCI_PRODUCT_ATI_RADEON_R100_QG, RADEON_R100, 0 }, 238 239 /* RV100 family */ 240 { PCI_PRODUCT_ATI_RADEON_RV100_LY, RADEON_RV100, RFB_MOB }, 241 { PCI_PRODUCT_ATI_RADEON_RV100_LZ, RADEON_RV100, RFB_MOB }, 242 { PCI_PRODUCT_ATI_RADEON_RV100_QY, RADEON_RV100, 0 }, 243 { PCI_PRODUCT_ATI_RADEON_RV100_QZ, RADEON_RV100, 0 }, 244 245 /* RS100 family */ 246 { PCI_PRODUCT_ATI_RADEON_RS100_4136, RADEON_RS100, 0 }, 247 { PCI_PRODUCT_ATI_RADEON_RS100_4336, RADEON_RS100, RFB_MOB }, 248 249 /* RS200/RS250 family */ 250 { PCI_PRODUCT_ATI_RADEON_RS200_4337, RADEON_RS200, RFB_MOB }, 251 { PCI_PRODUCT_ATI_RADEON_RS200_A7, RADEON_RS200, 0 }, 252 { PCI_PRODUCT_ATI_RADEON_RS250_B7, RADEON_RS200, RFB_MOB }, 253 { PCI_PRODUCT_ATI_RADEON_RS250_D7, RADEON_RS200, 0 }, 254 255 /* R200 family */ 256 /* add more R200 products? , 5148 */ 257 { PCI_PRODUCT_ATI_RADEON_R200_BB, RADEON_R200, 0 }, 258 { PCI_PRODUCT_ATI_RADEON_R200_BC, RADEON_R200, 0 }, 259 { PCI_PRODUCT_ATI_RADEON_R200_QH, RADEON_R200, 0 }, 260 { PCI_PRODUCT_ATI_RADEON_R200_QL, RADEON_R200, 0 }, 261 { PCI_PRODUCT_ATI_RADEON_R200_QM, RADEON_R200, 0 }, 262 263 /* RV200 family */ 264 { PCI_PRODUCT_ATI_RADEON_RV200_LW, RADEON_RV200, RFB_MOB }, 265 { PCI_PRODUCT_ATI_RADEON_RV200_LX, RADEON_RV200, RFB_MOB }, 266 { PCI_PRODUCT_ATI_RADEON_RV200_QW, RADEON_RV200, 0 }, 267 { PCI_PRODUCT_ATI_RADEON_RV200_QX, RADEON_RV200, 0 }, 268 269 /* RV250 family */ 270 { PCI_PRODUCT_ATI_RADEON_RV250_4966, RADEON_RV250, 0 }, 271 { PCI_PRODUCT_ATI_RADEON_RV250_4967, RADEON_RV250, 0 }, 272 { PCI_PRODUCT_ATI_RADEON_RV250_4C64, RADEON_RV250, RFB_MOB }, 273 { PCI_PRODUCT_ATI_RADEON_RV250_4C66, RADEON_RV250, RFB_MOB }, 274 { PCI_PRODUCT_ATI_RADEON_RV250_4C67, RADEON_RV250, RFB_MOB }, 275 276 /* RS300 family */ 277 { PCI_PRODUCT_ATI_RADEON_RS300_X5, RADEON_RS300, 0 }, 278 { PCI_PRODUCT_ATI_RADEON_RS300_X4, RADEON_RS300, 0 }, 279 { PCI_PRODUCT_ATI_RADEON_RS300_7834, RADEON_RS300, 0 }, 280 { PCI_PRODUCT_ATI_RADEON_RS300_7835, RADEON_RS300, RFB_MOB }, 281 282 /* RV280 family */ 283 { PCI_PRODUCT_ATI_RADEON_RV280_5960, RADEON_RV280, 0 }, 284 { PCI_PRODUCT_ATI_RADEON_RV280_5961, RADEON_RV280, 0 }, 285 { PCI_PRODUCT_ATI_RADEON_RV280_5962, RADEON_RV280, 0 }, 286 { PCI_PRODUCT_ATI_RADEON_RV280_5963, RADEON_RV280, 0 }, 287 { PCI_PRODUCT_ATI_RADEON_RV280_5964, RADEON_RV280, 0 }, 288 { PCI_PRODUCT_ATI_RADEON_RV280_5C61, RADEON_RV280, RFB_MOB }, 289 { PCI_PRODUCT_ATI_RADEON_RV280_5C63, RADEON_RV280, RFB_MOB }, 290 291 /* R300 family */ 292 { PCI_PRODUCT_ATI_RADEON_R300_AD, RADEON_R300, 0 }, 293 { PCI_PRODUCT_ATI_RADEON_R300_AE, RADEON_R300, 0 }, 294 { PCI_PRODUCT_ATI_RADEON_R300_AF, RADEON_R300, 0 }, 295 { PCI_PRODUCT_ATI_RADEON_R300_AG, RADEON_R300, 0 }, 296 { PCI_PRODUCT_ATI_RADEON_R300_ND, RADEON_R300, 0 }, 297 { PCI_PRODUCT_ATI_RADEON_R300_NE, RADEON_R300, 0 }, 298 { PCI_PRODUCT_ATI_RADEON_R300_NF, RADEON_R300, 0 }, 299 { PCI_PRODUCT_ATI_RADEON_R300_NG, RADEON_R300, 0 }, 300 301 /* RV350/RV360 family */ 302 { PCI_PRODUCT_ATI_RADEON_RV350_AP, RADEON_RV350, 0 }, 303 { PCI_PRODUCT_ATI_RADEON_RV350_AQ, RADEON_RV350, 0 }, 304 { PCI_PRODUCT_ATI_RADEON_RV360_AR, RADEON_RV350, 0 }, 305 { PCI_PRODUCT_ATI_RADEON_RV350_AS, RADEON_RV350, 0 }, 306 { PCI_PRODUCT_ATI_RADEON_RV350_AT, RADEON_RV350, 0 }, 307 { PCI_PRODUCT_ATI_RADEON_RV350_AV, RADEON_RV350, 0 }, 308 { PCI_PRODUCT_ATI_RADEON_RV350_NP, RADEON_RV350, RFB_MOB }, 309 { PCI_PRODUCT_ATI_RADEON_RV350_NQ, RADEON_RV350, RFB_MOB }, 310 { PCI_PRODUCT_ATI_RADEON_RV350_NR, RADEON_RV350, RFB_MOB }, 311 { PCI_PRODUCT_ATI_RADEON_RV350_NS, RADEON_RV350, RFB_MOB }, 312 { PCI_PRODUCT_ATI_RADEON_RV350_NT, RADEON_RV350, RFB_MOB }, 313 { PCI_PRODUCT_ATI_RADEON_RV350_NV, RADEON_RV350, RFB_MOB }, 314 315 /* R350/R360 family */ 316 { PCI_PRODUCT_ATI_RADEON_R350_AH, RADEON_R350, 0 }, 317 { PCI_PRODUCT_ATI_RADEON_R350_AI, RADEON_R350, 0 }, 318 { PCI_PRODUCT_ATI_RADEON_R350_AJ, RADEON_R350, 0 }, 319 { PCI_PRODUCT_ATI_RADEON_R350_AK, RADEON_R350, 0 }, 320 { PCI_PRODUCT_ATI_RADEON_R350_NH, RADEON_R350, 0 }, 321 { PCI_PRODUCT_ATI_RADEON_R350_NI, RADEON_R350, 0 }, 322 { PCI_PRODUCT_ATI_RADEON_R350_NK, RADEON_R350, 0 }, 323 { PCI_PRODUCT_ATI_RADEON_R360_NJ, RADEON_R350, 0 }, 324 325 /* RV380/RV370 family */ 326 { PCI_PRODUCT_ATI_RADEON_RV380_3150, RADEON_RV380, RFB_MOB }, 327 { PCI_PRODUCT_ATI_RADEON_RV380_3154, RADEON_RV380, RFB_MOB }, 328 { PCI_PRODUCT_ATI_RADEON_RV380_3E50, RADEON_RV380, 0 }, 329 { PCI_PRODUCT_ATI_RADEON_RV380_3E54, RADEON_RV380, 0 }, 330 { PCI_PRODUCT_ATI_RADEON_RV370_5460, RADEON_RV380, RFB_MOB }, 331 { PCI_PRODUCT_ATI_RADEON_RV370_5464, RADEON_RV380, RFB_MOB }, 332 { PCI_PRODUCT_ATI_RADEON_RV370_5B60, RADEON_RV380, 0 }, 333 { PCI_PRODUCT_ATI_RADEON_RV370_5B64, RADEON_RV380, 0 }, 334 { PCI_PRODUCT_ATI_RADEON_RV370_5B65, RADEON_RV380, 0 }, 335 336 /* R420/R423 family */ 337 { PCI_PRODUCT_ATI_RADEON_R420_JH, RADEON_R420, 0 }, 338 { PCI_PRODUCT_ATI_RADEON_R420_JI, RADEON_R420, 0 }, 339 { PCI_PRODUCT_ATI_RADEON_R420_JJ, RADEON_R420, 0 }, 340 { PCI_PRODUCT_ATI_RADEON_R420_JK, RADEON_R420, 0 }, 341 { PCI_PRODUCT_ATI_RADEON_R420_JL, RADEON_R420, 0 }, 342 { PCI_PRODUCT_ATI_RADEON_R420_JM, RADEON_R420, 0 }, 343 { PCI_PRODUCT_ATI_RADEON_R420_JN, RADEON_R420, RFB_MOB }, 344 { PCI_PRODUCT_ATI_RADEON_R420_JP, RADEON_R420, 0 }, 345 { PCI_PRODUCT_ATI_RADEON_R423_UH, RADEON_R420, 0 }, 346 { PCI_PRODUCT_ATI_RADEON_R423_UI, RADEON_R420, 0 }, 347 { PCI_PRODUCT_ATI_RADEON_R423_UJ, RADEON_R420, 0 }, 348 { PCI_PRODUCT_ATI_RADEON_R423_UK, RADEON_R420, 0 }, 349 { PCI_PRODUCT_ATI_RADEON_R423_UQ, RADEON_R420, 0 }, 350 { PCI_PRODUCT_ATI_RADEON_R423_UR, RADEON_R420, 0 }, 351 { PCI_PRODUCT_ATI_RADEON_R423_UT, RADEON_R420, 0 }, 352 { PCI_PRODUCT_ATI_RADEON_R423_5D57, RADEON_R420, 0 }, 353 354 { 0, 0, 0 } 355 }; 356 357 static struct { 358 int divider; 359 int mask; 360 } radeonfb_dividers[] = { 361 { 1, 0 }, 362 { 2, 1 }, 363 { 3, 4 }, 364 { 4, 2 }, 365 { 6, 6 }, 366 { 8, 3 }, 367 { 12, 7 }, 368 { 0, 0 } 369 }; 370 371 /* 372 * This table taken from X11. 373 */ 374 static const struct { 375 int family; 376 struct radeon_tmds_pll plls[4]; 377 } radeonfb_tmds_pll[] = { 378 { RADEON_R100, {{12000, 0xa1b}, {-1, 0xa3f}}}, 379 { RADEON_RV100, {{12000, 0xa1b}, {-1, 0xa3f}}}, 380 { RADEON_RS100, {{0, 0}}}, 381 { RADEON_RV200, {{15000, 0xa1b}, {-1, 0xa3f}}}, 382 { RADEON_RS200, {{15000, 0xa1b}, {-1, 0xa3f}}}, 383 { RADEON_R200, {{15000, 0xa1b}, {-1, 0xa3f}}}, 384 { RADEON_RV250, {{15500, 0x81b}, {-1, 0x83f}}}, 385 { RADEON_RS300, {{0, 0}}}, 386 { RADEON_RV280, {{13000, 0x400f4}, {15000, 0x400f7}}}, 387 { RADEON_R300, {{-1, 0xb01cb}}}, 388 { RADEON_R350, {{-1, 0xb01cb}}}, 389 { RADEON_RV350, {{15000, 0xb0155}, {-1, 0xb01cb}}}, 390 { RADEON_RV380, {{15000, 0xb0155}, {-1, 0xb01cb}}}, 391 { RADEON_R420, {{-1, 0xb01cb}}}, 392 }; 393 394 395 CFATTACH_DECL(radeonfb, sizeof (struct radeonfb_softc), 396 radeonfb_match, radeonfb_attach, NULL, NULL); 397 398 static int 399 radeonfb_match(struct device *parent, struct cfdata *match, void *aux) 400 { 401 struct pci_attach_args *pa = aux; 402 int i; 403 404 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_ATI) 405 return 0; 406 407 for (i = 0; radeonfb_devices[i].devid; i++) { 408 if (PCI_PRODUCT(pa->pa_id) == radeonfb_devices[i].devid) 409 return 100; /* high to defeat VGA/VESA */ 410 } 411 412 return 0; 413 } 414 415 static void 416 radeonfb_attach(struct device *parent, struct device *dev, void *aux) 417 { 418 struct radeonfb_softc *sc = (struct radeonfb_softc *)dev; 419 struct pci_attach_args *pa = aux; 420 bus_size_t bsz; 421 pcireg_t screg; 422 int i, j; 423 uint32_t v; 424 425 sc->sc_id = pa->pa_id; 426 for (i = 0; radeonfb_devices[i].devid; i++) { 427 if (PCI_PRODUCT(sc->sc_id) == radeonfb_devices[i].devid) 428 break; 429 } 430 431 pci_devinfo(sc->sc_id, pa->pa_class, 0, sc->sc_devinfo, 432 sizeof(sc->sc_devinfo)); 433 434 aprint_naive("\n"); 435 aprint_normal(": %s\n", sc->sc_devinfo); 436 437 KASSERT(radeonfb_devices[i].devid != 0); 438 sc->sc_pt = pa->pa_tag; 439 sc->sc_pc = pa->pa_pc; 440 sc->sc_family = radeonfb_devices[i].family; 441 sc->sc_flags = radeonfb_devices[i].flags; 442 443 /* enable memory and IO access */ 444 screg = pci_conf_read(sc->sc_pc, sc->sc_pt, PCI_COMMAND_STATUS_REG); 445 screg |= PCI_FLAGS_IO_ENABLED | PCI_FLAGS_MEM_ENABLED; 446 pci_conf_write(sc->sc_pc, sc->sc_pt, PCI_COMMAND_STATUS_REG, screg); 447 448 /* 449 * Some flags are general to entire chip families, and rather 450 * than clutter up the table with them, we go ahead and set 451 * them here. 452 */ 453 switch (sc->sc_family) { 454 case RADEON_RS100: 455 case RADEON_RS200: 456 sc->sc_flags |= RFB_IGP | RFB_RV100; 457 break; 458 459 case RADEON_RV100: 460 case RADEON_RV200: 461 case RADEON_RV250: 462 case RADEON_RV280: 463 sc->sc_flags |= RFB_RV100; 464 break; 465 466 case RADEON_RS300: 467 sc->sc_flags |= RFB_SDAC | RFB_IGP | RFB_RV100; 468 break; 469 470 case RADEON_R300: 471 case RADEON_RV350: 472 case RADEON_R350: 473 case RADEON_RV380: 474 case RADEON_R420: 475 /* newer chips */ 476 sc->sc_flags |= RFB_R300; 477 break; 478 479 case RADEON_R100: 480 sc->sc_flags |= RFB_NCRTC2; 481 break; 482 } 483 484 /* 485 * XXX: to support true multihead, this must change. 486 */ 487 sc->sc_ndisplays = 1; 488 489 /* XXX: */ 490 if (!HAS_CRTC2(sc)) { 491 sc->sc_ndisplays = 1; 492 } 493 494 if (pci_mapreg_map(pa, RADEON_MAPREG_MMIO, PCI_MAPREG_TYPE_MEM, 0, 495 &sc->sc_regt, &sc->sc_regh, &sc->sc_regaddr, 496 &sc->sc_regsz) != 0) { 497 aprint_error("%s: unable to map registers!\n", XNAME(sc)); 498 goto error; 499 } 500 501 if (pci_mapreg_map(pa, RADEON_MAPREG_IO, PCI_MAPREG_TYPE_IO, 0, 502 &sc->sc_iot, &sc->sc_ioh, &sc->sc_ioaddr, 503 &sc->sc_iosz) != 0) { 504 aprint_error("%s: unable to map IO registers!\n", XNAME(sc)); 505 } 506 507 /* scratch register test... */ 508 if (radeonfb_scratch_test(sc, RADEON_BIOS_0_SCRATCH, 0x55555555) || 509 radeonfb_scratch_test(sc, RADEON_BIOS_0_SCRATCH, 0xaaaaaaaa)) { 510 aprint_error("%s: scratch register test failed!\n", XNAME(sc)); 511 goto error; 512 } 513 514 PRINTREG(RADEON_BIOS_4_SCRATCH); 515 PRINTREG(RADEON_FP_GEN_CNTL); 516 PRINTREG(RADEON_FP2_GEN_CNTL); 517 PRINTREG(RADEON_TMDS_CNTL); 518 PRINTREG(RADEON_TMDS_TRANSMITTER_CNTL); 519 PRINTREG(RADEON_TMDS_PLL_CNTL); 520 PRINTREG(RADEON_LVDS_GEN_CNTL); 521 PRINTREG(RADEON_FP_HORZ_STRETCH); 522 PRINTREG(RADEON_FP_VERT_STRETCH); 523 524 /* XXX: RV100 specific */ 525 PUT32(sc, RADEON_TMDS_PLL_CNTL, 0xa27); 526 527 PATCH32(sc, RADEON_TMDS_TRANSMITTER_CNTL, 528 RADEON_TMDS_TRANSMITTER_PLLEN, 529 RADEON_TMDS_TRANSMITTER_PLLEN | RADEON_TMDS_TRANSMITTER_PLLRST); 530 531 radeonfb_i2c_init(sc); 532 533 radeonfb_loadbios(sc, pa); 534 535 #ifdef RADEON_BIOS_INIT 536 if (radeonfb_bios_init(sc)) { 537 aprint_error("%s: BIOS inititialization failed\n", XNAME(sc)); 538 goto error; 539 } 540 #endif 541 542 if (radeonfb_getclocks(sc)) { 543 aprint_error("%s: Unable to get reference clocks from BIOS\n", 544 XNAME(sc)); 545 goto error; 546 } 547 548 if (radeonfb_gettmds(sc)) { 549 aprint_error("%s: Unable to identify TMDS PLL settings\n", 550 XNAME(sc)); 551 goto error; 552 } 553 554 aprint_verbose("%s: refclk = %d.%03d MHz, refdiv = %d " 555 "minpll = %d, maxpll = %d\n", XNAME(sc), 556 (int)sc->sc_refclk / 1000, (int)sc->sc_refclk % 1000, 557 (int)sc->sc_refdiv, (int)sc->sc_minpll, (int)sc->sc_maxpll); 558 559 radeonfb_getconnectors(sc); 560 561 radeonfb_set_fbloc(sc); 562 563 for (i = 0; radeonfb_limits[i].size; i++) { 564 if (sc->sc_memsz >= radeonfb_limits[i].size) { 565 sc->sc_maxx = radeonfb_limits[i].maxx; 566 sc->sc_maxy = radeonfb_limits[i].maxy; 567 sc->sc_maxbpp = radeonfb_limits[i].maxbpp; 568 /* framebuffer offset, start at a 4K page */ 569 sc->sc_fboffset = sc->sc_memsz / 570 radeonfb_limits[i].maxdisp; 571 /* 572 * we use the fbsize to figure out where we can store 573 * things like cursor data. 574 */ 575 sc->sc_fbsize = 576 ROUNDUP(ROUNDUP(sc->sc_maxx * sc->sc_maxbpp / 8 , 577 RADEON_STRIDEALIGN) * sc->sc_maxy, 578 4096); 579 break; 580 } 581 } 582 583 584 radeonfb_init_misc(sc); 585 radeonfb_init_palette(sc, 0); 586 if (HAS_CRTC2(sc)) 587 radeonfb_init_palette(sc, 1); 588 589 /* program the DAC wirings */ 590 for (i = 0; i < (HAS_CRTC2(sc) ? 2 : 1); i++) { 591 switch (sc->sc_ports[i].rp_dac_type) { 592 case RADEON_DAC_PRIMARY: 593 PATCH32(sc, RADEON_DAC_CNTL2, 594 i ? RADEON_DAC2_DAC_CLK_SEL : 0, 595 ~RADEON_DAC2_DAC_CLK_SEL); 596 break; 597 case RADEON_DAC_TVDAC: 598 /* we always use the TVDAC to drive a secondary analog 599 * CRT for now. if we ever support TV-out this will 600 * have to change. 601 */ 602 SET32(sc, RADEON_DAC_CNTL2, 603 RADEON_DAC2_DAC2_CLK_SEL); 604 PATCH32(sc, RADEON_DISP_HW_DEBUG, 605 i ? 0 : RADEON_CRT2_DISP1_SEL, 606 ~RADEON_CRT2_DISP1_SEL); 607 break; 608 } 609 } 610 PRINTREG(RADEON_DAC_CNTL2); 611 PRINTREG(RADEON_DISP_HW_DEBUG); 612 613 /* other DAC programming */ 614 v = GET32(sc, RADEON_DAC_CNTL); 615 v &= (RADEON_DAC_RANGE_CNTL_MASK | RADEON_DAC_BLANKING); 616 v |= RADEON_DAC_MASK_ALL | RADEON_DAC_8BIT_EN; 617 PUT32(sc, RADEON_DAC_CNTL, v); 618 PRINTREG(RADEON_DAC_CNTL); 619 620 /* XXX: this may need more investigation */ 621 PUT32(sc, RADEON_TV_DAC_CNTL, 0x00280203); 622 PRINTREG(RADEON_TV_DAC_CNTL); 623 624 /* enable TMDS */ 625 SET32(sc, RADEON_FP_GEN_CNTL, 626 RADEON_FP_TMDS_EN | 627 RADEON_FP_CRTC_DONT_SHADOW_VPAR | 628 RADEON_FP_CRTC_DONT_SHADOW_HEND); 629 CLR32(sc, RADEON_FP_GEN_CNTL, RADEON_FP_SEL_CRTC2); 630 if (HAS_CRTC2(sc)) 631 SET32(sc, RADEON_FP2_GEN_CNTL, RADEON_FP2_SRC_SEL_CRTC2); 632 633 /* 634 * we use bus_space_map instead of pci_mapreg, because we don't 635 * need the full aperature space. no point in wasting virtual 636 * address space we don't intend to use, right? 637 */ 638 if ((sc->sc_memsz < (4096 * 1024)) || 639 (pci_mapreg_info(sc->sc_pc, sc->sc_pt, RADEON_MAPREG_VRAM, 640 PCI_MAPREG_TYPE_MEM, &sc->sc_memaddr, &bsz, NULL) != 0) || 641 (bsz < sc->sc_memsz)) { 642 sc->sc_memsz = 0; 643 aprint_error("%s: Bad frame buffer configuration\n", 644 XNAME(sc)); 645 goto error; 646 } 647 648 /* 64 MB should be enough -- more just wastes map entries */ 649 if (sc->sc_memsz > (64 << 20)) 650 sc->sc_memsz = (64 << 20); 651 652 sc->sc_memt = pa->pa_memt; 653 if (bus_space_map(sc->sc_memt, sc->sc_memaddr, sc->sc_memsz, 654 BUS_SPACE_MAP_LINEAR, &sc->sc_memh) != 0) { 655 sc->sc_memsz = 0; 656 aprint_error("%s: Unable to map frame buffer\n", XNAME(sc)); 657 goto error; 658 } 659 660 aprint_normal("%s: %d MB aperture at 0x%08x, " 661 "%d KB registers at 0x%08x\n", XNAME(sc), 662 (int)sc->sc_memsz >> 20, (unsigned)sc->sc_memaddr, 663 (int)sc->sc_regsz >> 10, (unsigned)sc->sc_regaddr); 664 665 #if 0 666 /* setup default video mode from devprop (allows PROM override) */ 667 sc->sc_defaultmode = radeonfb_default_mode; 668 ps = prop_dictionary_get(device_properties(&sc->sc_dev), 669 "videomode"); 670 if (ps != NULL) { 671 sc->sc_modebuf = prop_string_cstring(ps); 672 if (sc->sc_modebuf) 673 sc->sc_defaultmode = sc->sc_modebuf; 674 } 675 #endif 676 677 /* initialize some basic display parameters */ 678 for (i = 0; i < sc->sc_ndisplays; i++) { 679 struct radeonfb_display *dp = &sc->sc_displays[i]; 680 struct rasops_info *ri; 681 long defattr; 682 struct wsemuldisplaydev_attach_args aa; 683 684 /* 685 * Figure out how many "displays" (desktops) we are going to 686 * support. If more than one, then each CRTC gets its own 687 * programming. 688 * 689 * XXX: this code needs to change to support mergedfb. 690 * XXX: would be nice to allow this to be overridden 691 */ 692 if (HAS_CRTC2(sc) && (sc->sc_ndisplays == 1)) { 693 DPRINTF(("dual crtcs!\n")); 694 dp->rd_ncrtcs = 2; 695 dp->rd_crtcs[0].rc_number = 0; 696 dp->rd_crtcs[1].rc_number = 1; 697 } else { 698 dp->rd_ncrtcs = 1; 699 dp->rd_crtcs[0].rc_number = i; 700 } 701 702 /* set up port pointer */ 703 for (j = 0; j < dp->rd_ncrtcs; j++) { 704 dp->rd_crtcs[j].rc_port = 705 &sc->sc_ports[dp->rd_crtcs[j].rc_number]; 706 } 707 708 dp->rd_softc = sc; 709 dp->rd_wsmode = WSDISPLAYIO_MODE_EMUL; 710 dp->rd_bg = WS_DEFAULT_BG; 711 #if 0 712 dp->rd_bpp = sc->sc_maxbpp; /* XXX: for now */ 713 #else 714 dp->rd_bpp = RADEONFB_DEFAULT_DEPTH; /* XXX */ 715 #endif 716 /* for text mode, we pick a resolution that won't 717 * require panning */ 718 radeonfb_pickres(dp, &dp->rd_virtx, &dp->rd_virty, 0); 719 720 aprint_normal("%s: display %d: " 721 "virtual resolution %dx%d at %d bpp\n", 722 XNAME(sc), i, dp->rd_virtx, dp->rd_virty, dp->rd_bpp); 723 724 /* now select the *video mode* that we will use */ 725 for (j = 0; j < dp->rd_ncrtcs; j++) { 726 const struct videomode *vmp; 727 vmp = radeonfb_port_mode(dp->rd_crtcs[j].rc_port, 728 dp->rd_virtx, dp->rd_virty); 729 dp->rd_crtcs[j].rc_videomode = *vmp; 730 printf("%s: port %d: physical %dx%d %dHz\n", 731 XNAME(sc), j, vmp->hdisplay, vmp->vdisplay, 732 DIVIDE(DIVIDE(vmp->dot_clock * 1000, 733 vmp->htotal), vmp->vtotal)); 734 } 735 736 /* N.B.: radeon wants 64-byte aligned stride */ 737 dp->rd_stride = dp->rd_virtx * dp->rd_bpp / 8; 738 //dp->rd_stride = sc->sc_maxx * sc->sc_maxbpp / 8; 739 dp->rd_stride = ROUNDUP(dp->rd_stride, RADEON_STRIDEALIGN); 740 741 dp->rd_offset = sc->sc_fboffset * i; 742 dp->rd_fbptr = (vaddr_t)bus_space_vaddr(sc->sc_memt, 743 sc->sc_memh) + dp->rd_offset; 744 dp->rd_curoff = sc->sc_fbsize; 745 dp->rd_curptr = dp->rd_fbptr + dp->rd_curoff; 746 747 DPRINTF(("fpbtr = %p\n", (void *)dp->rd_fbptr)); 748 749 switch (dp->rd_bpp) { 750 case 8: 751 dp->rd_format = 2; 752 break; 753 case 32: 754 dp->rd_format = 6; 755 break; 756 default: 757 aprint_error("%s: bad depth %d\n", XNAME(sc), 758 dp->rd_bpp); 759 goto error; 760 } 761 762 printf("init engine\n"); 763 /* XXX: this seems suspicious - per display engine 764 initialization? */ 765 radeonfb_engine_init(dp); 766 767 /* copy the template into place */ 768 dp->rd_wsscreens_storage[0] = radeonfb_stdscreen; 769 dp->rd_wsscreens = dp->rd_wsscreens_storage; 770 771 /* and make up the list */ 772 dp->rd_wsscreenlist.nscreens = 1; 773 dp->rd_wsscreenlist.screens = 774 (const struct wsscreen_descr **)&dp->rd_wsscreens; 775 776 vcons_init(&dp->rd_vd, dp, dp->rd_wsscreens, 777 &radeonfb_accessops); 778 779 dp->rd_vd.init_screen = radeonfb_init_screen; 780 781 dp->rd_console = 1; 782 783 dp->rd_vscreen.scr_flags |= VCONS_SCREEN_IS_STATIC; 784 785 vcons_init_screen(&dp->rd_vd, &dp->rd_vscreen, 786 dp->rd_console, &defattr); 787 788 ri = &dp->rd_vscreen.scr_ri; 789 dp->rd_wsscreens->textops = &ri->ri_ops; 790 dp->rd_wsscreens->capabilities = ri->ri_caps; 791 dp->rd_wsscreens->nrows = ri->ri_rows; 792 dp->rd_wsscreens->ncols = ri->ri_cols; 793 794 #ifdef SPLASHSCREEN 795 dp->rd_splash.si_depth = ri->ri_depth; 796 dp->rd_splash.si_bits = ri->ri_bits; 797 dp->rd_splash.si_hwbits = ri->ri_hwbits; 798 dp->rd_splash.si_width = ri->ri_width; 799 dp->rd_splash.si_height = ri->ri_height; 800 dp->rd_splash.si_stride = ri->ri_stride; 801 dp->rd_splash.si_fillrect = NULL; 802 #endif 803 if (dp->rd_console) { 804 805 wsdisplay_cnattach(dp->rd_wsscreens, ri, 0, 0, 806 defattr); 807 #ifdef SPLASHSCREEN 808 splash_render(&dp->rd_splash, 809 SPLASH_F_CENTER|SPLASH_F_FILL); 810 #endif 811 812 #ifdef SPLASHSCREEN_PROGRESS 813 dp->rd_progress.sp_top = (dp->rd_virty / 8) * 7; 814 dp->rd_progress.sp_width = (dp->rd_virtx / 4) * 3; 815 dp->rd_progress.sp_left = (dp->rd_virtx - 816 dp->rd_progress.sp_width) / 2; 817 dp->rd_progress.sp_height = 20; 818 dp->rd_progress.sp_state = -1; 819 dp->rd_progress.sp_si = &dp->rd_splash; 820 splash_progress_init(&dp->rd_progress); 821 SCREEN_DISABLE_DRAWING(&dp->rd_vscreen); 822 #endif 823 824 } else { 825 826 /* 827 * since we're not the console we can postpone 828 * the rest until someone actually allocates a 829 * screen for us. but we do clear the screen 830 * at least. 831 */ 832 memset(ri->ri_bits, 0, 1024); 833 834 radeonfb_modeswitch(dp); 835 #ifdef SPLASHSCREEN 836 splash_render(&dp->rd_splash, 837 SPLASH_F_CENTER|SPLASH_F_FILL); 838 SCREEN_DISABLE_DRAWING(&dp->rd_vscreen); 839 #endif 840 } 841 842 aa.console = dp->rd_console; 843 aa.scrdata = &dp->rd_wsscreenlist; 844 aa.accessops = &radeonfb_accessops; 845 aa.accesscookie = &dp->rd_vd; 846 847 config_found(&sc->sc_dev, &aa, wsemuldisplaydevprint); 848 radeonfb_blank(dp, 0); 849 } 850 851 return; 852 853 error: 854 if (sc->sc_biossz) 855 free(sc->sc_bios, M_DEVBUF); 856 857 if (sc->sc_regsz) 858 bus_space_unmap(sc->sc_regt, sc->sc_regh, sc->sc_regsz); 859 860 if (sc->sc_memsz) 861 bus_space_unmap(sc->sc_memt, sc->sc_memh, sc->sc_memsz); 862 } 863 864 int 865 radeonfb_ioctl(void *v, void *vs, 866 unsigned long cmd, caddr_t d, int flag, struct lwp *l) 867 { 868 struct vcons_data *vd; 869 struct radeonfb_display *dp; 870 struct radeonfb_softc *sc; 871 872 vd = (struct vcons_data *)v; 873 dp = (struct radeonfb_display *)vd->cookie; 874 sc = dp->rd_softc; 875 876 switch (cmd) { 877 case WSDISPLAYIO_GTYPE: 878 *(unsigned *)d = WSDISPLAY_TYPE_PCIMISC; 879 return 0; 880 881 case WSDISPLAYIO_GINFO: 882 if (vd->active != NULL) { 883 struct wsdisplay_fbinfo *fb; 884 fb = (struct wsdisplay_fbinfo *)d; 885 fb->width = dp->rd_virtx; 886 fb->height = dp->rd_virty; 887 fb->depth = dp->rd_bpp; 888 fb->cmsize = 256; 889 return 0; 890 } else 891 return ENODEV; 892 case WSDISPLAYIO_GVIDEO: 893 if (radeonfb_isblank(dp)) 894 *(unsigned *)d = WSDISPLAYIO_VIDEO_OFF; 895 else 896 *(unsigned *)d = WSDISPLAYIO_VIDEO_ON; 897 return 0; 898 899 case WSDISPLAYIO_SVIDEO: 900 radeonfb_blank(dp, 901 (*(unsigned int *)d == WSDISPLAYIO_VIDEO_OFF)); 902 return 0; 903 904 case WSDISPLAYIO_GETCMAP: 905 #if 0 906 if (dp->rd_bpp == 8) 907 return radeonfb_getcmap(sc, 908 (struct wsdisplay_cmap *)d); 909 #endif 910 return EINVAL; 911 912 case WSDISPLAYIO_PUTCMAP: 913 #if 0 914 if (dp->rd_bpp == 8) 915 return radeonfb_putcmap(sc, 916 (struct wsdisplay_cmap *)d); 917 #endif 918 return EINVAL; 919 920 case WSDISPLAYIO_LINEBYTES: 921 *(unsigned *)d = dp->rd_stride; 922 return 0; 923 924 case WSDISPLAYIO_SMODE: 925 if (*(int *)d != dp->rd_wsmode) { 926 dp->rd_wsmode = *(int *)d; 927 if ((dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) && 928 (dp->rd_vd.active)) { 929 vcons_redraw_screen(dp->rd_vd.active); 930 } 931 } 932 return 0; 933 934 case WSDISPLAYIO_GCURMAX: 935 ((struct wsdisplay_curpos *)d)->x = RADEON_CURSORMAXX; 936 ((struct wsdisplay_curpos *)d)->y = RADEON_CURSORMAXY; 937 return 0; 938 939 case WSDISPLAYIO_SCURSOR: 940 return radeonfb_set_cursor(dp, (struct wsdisplay_cursor *)d); 941 942 case WSDISPLAYIO_GCURSOR: 943 return EPASSTHROUGH; 944 945 case WSDISPLAYIO_GCURPOS: 946 ((struct wsdisplay_curpos *)d)->x = dp->rd_cursor.rc_pos.x; 947 ((struct wsdisplay_curpos *)d)->y = dp->rd_cursor.rc_pos.y; 948 return 0; 949 950 case WSDISPLAYIO_SCURPOS: 951 return radeonfb_set_curpos(dp, (struct wsdisplay_curpos *)d); 952 953 case WSDISPLAYIO_SSPLASH: 954 #if defined(SPLASHSCREEN) 955 if (*(int *)d == 1) { 956 SCREEN_DISABLE_DRAWING(&dp->rd_vscreen); 957 splash_render(&dp->rd_splash, 958 SPLASH_F_CENTER|SPLASH_F_FILL); 959 } else 960 SCREEN_ENABLE_DRAWING(&dp->rd_vscreen); 961 return 0; 962 #else 963 return ENODEV; 964 #endif 965 case WSDISPLAYIO_SPROGRESS: 966 #if defined(SPLASHSCREEN) && defined(SPLASHSCREEN_PROGRESS) 967 dp->rd_progress.sp_force = 1; 968 splash_progress_update(&dp->rd_progress); 969 dp->rd_progress.sp_force = 0; 970 return 0; 971 #else 972 return ENODEV; 973 #endif 974 975 default: 976 return EPASSTHROUGH; 977 } 978 } 979 980 paddr_t 981 radeonfb_mmap(void *v, void *vs, off_t offset, int prot) 982 { 983 struct vcons_data *vd; 984 struct radeonfb_display *dp; 985 struct radeonfb_softc *sc; 986 #ifdef RADEONFB_MMAP_BARS 987 struct lwp *me; 988 #endif 989 paddr_t pa; 990 991 vd = (struct vcons_data *)v; 992 dp = (struct radeonfb_display *)vd->cookie; 993 sc = dp->rd_softc; 994 995 /* XXX: note that we don't allow mapping of registers right now */ 996 /* XXX: this means that the XFree86 radeon driver won't work */ 997 998 if ((offset >= 0) && (offset < (dp->rd_virty * dp->rd_stride))) { 999 pa = bus_space_mmap(sc->sc_memt, 1000 sc->sc_memaddr + dp->rd_offset + offset, 0, 1001 prot, BUS_SPACE_MAP_LINEAR); 1002 return pa; 1003 } 1004 1005 #ifdef RADEONFB_MMAP_BARS 1006 /* 1007 * restrict all other mappings to processes with superuser privileges 1008 * or the kernel itself 1009 */ 1010 me = curlwp; 1011 if (me != NULL) { 1012 if (kauth_authorize_generic(me->l_cred, KAUTH_GENERIC_ISSUSER, 1013 NULL) != 0) { 1014 printf("%s: mmap() rejected.\n", sc->sc_dev.dv_xname); 1015 return -1; 1016 } 1017 } 1018 1019 if ((offset >= sc->sc_regaddr) && 1020 (offset < sc->sc_regaddr + sc->sc_regsz)) { 1021 return bus_space_mmap(sc->sc_regt, offset, 0, prot, 1022 BUS_SPACE_MAP_LINEAR); 1023 } 1024 1025 if ((offset >= sc->sc_memaddr) && 1026 (offset < sc->sc_memaddr + sc->sc_memsz)) { 1027 return bus_space_mmap(sc->sc_memt, offset, 0, prot, 1028 BUS_SPACE_MAP_LINEAR); 1029 } 1030 1031 #ifdef macppc 1032 /* allow mapping of IO space */ 1033 if ((offset >= 0xf2000000) && (offset < 0xf2800000)) { 1034 pa = bus_space_mmap(sc->sc_iot, offset-0xf2000000, 0, prot, 1035 BUS_SPACE_MAP_LINEAR); 1036 return pa; 1037 } 1038 #endif /* macppc */ 1039 1040 #endif /* RADEONFB_MMAP_BARS */ 1041 1042 return -1; 1043 } 1044 1045 static void 1046 radeonfb_loadbios(struct radeonfb_softc *sc, struct pci_attach_args *pa) 1047 { 1048 bus_space_tag_t romt; 1049 bus_space_handle_t romh, biosh; 1050 bus_size_t romsz; 1051 bus_addr_t ptr; 1052 1053 if (pci_mapreg_map(pa, PCI_MAPREG_ROM, PCI_MAPREG_TYPE_ROM, 1054 BUS_SPACE_MAP_PREFETCHABLE, &romt, &romh, NULL, &romsz) != 0) { 1055 aprint_verbose("%s: unable to map BIOS!\n", XNAME(sc)); 1056 return; 1057 } 1058 1059 pci_find_rom(pa, romt, romh, PCI_ROM_CODE_TYPE_X86, &biosh, 1060 &sc->sc_biossz); 1061 if (sc->sc_biossz == 0) { 1062 aprint_verbose("%s: Video BIOS not present\n", XNAME(sc)); 1063 return; 1064 } 1065 1066 sc->sc_bios = malloc(sc->sc_biossz, M_DEVBUF, M_WAITOK); 1067 bus_space_read_region_1(romt, biosh, 0, sc->sc_bios, sc->sc_biossz); 1068 1069 /* unmap the PCI expansion rom */ 1070 bus_space_unmap(romt, romh, romsz); 1071 1072 /* turn off rom decoder now */ 1073 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM, 1074 pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM) & 1075 ~PCI_MAPREG_ROM_ENABLE); 1076 1077 ptr = GETBIOS16(sc, 0x48); 1078 if ((GETBIOS32(sc, ptr + 4) == 0x41544f4d /* "ATOM" */) || 1079 (GETBIOS32(sc, ptr + 4) == 0x4d4f5441 /* "MOTA" */)) { 1080 sc->sc_flags |= RFB_ATOM; 1081 } 1082 1083 aprint_verbose("%s: Found %d KB %s BIOS\n", XNAME(sc), 1084 (unsigned)sc->sc_biossz >> 10, IS_ATOM(sc) ? "ATOM" : "Legacy"); 1085 } 1086 1087 1088 uint32_t 1089 radeonfb_get32(struct radeonfb_softc *sc, uint32_t reg) 1090 { 1091 1092 return bus_space_read_4(sc->sc_regt, sc->sc_regh, reg); 1093 } 1094 1095 void 1096 radeonfb_put32(struct radeonfb_softc *sc, uint32_t reg, uint32_t val) 1097 { 1098 1099 bus_space_write_4(sc->sc_regt, sc->sc_regh, reg, val); 1100 } 1101 1102 void 1103 radeonfb_mask32(struct radeonfb_softc *sc, uint32_t reg, 1104 uint32_t andmask, uint32_t ormask) 1105 { 1106 int s; 1107 uint32_t val; 1108 1109 s = splhigh(); 1110 val = radeonfb_get32(sc, reg); 1111 val = (val & andmask) | ormask; 1112 radeonfb_put32(sc, reg, val); 1113 splx(s); 1114 } 1115 1116 uint32_t 1117 radeonfb_getindex(struct radeonfb_softc *sc, uint32_t idx) 1118 { 1119 int s; 1120 uint32_t val; 1121 1122 s = splhigh(); 1123 radeonfb_put32(sc, RADEON_MM_INDEX, idx); 1124 val = radeonfb_get32(sc, RADEON_MM_DATA); 1125 splx(s); 1126 1127 return (val); 1128 } 1129 1130 void 1131 radeonfb_putindex(struct radeonfb_softc *sc, uint32_t idx, uint32_t val) 1132 { 1133 int s; 1134 1135 s = splhigh(); 1136 radeonfb_put32(sc, RADEON_MM_INDEX, idx); 1137 radeonfb_put32(sc, RADEON_MM_DATA, val); 1138 splx(s); 1139 } 1140 1141 void 1142 radeonfb_maskindex(struct radeonfb_softc *sc, uint32_t idx, 1143 uint32_t andmask, uint32_t ormask) 1144 { 1145 int s; 1146 uint32_t val; 1147 1148 s = splhigh(); 1149 radeonfb_put32(sc, RADEON_MM_INDEX, idx); 1150 val = radeonfb_get32(sc, RADEON_MM_DATA); 1151 val = (val & andmask) | ormask; 1152 radeonfb_put32(sc, RADEON_MM_DATA, val); 1153 splx(s); 1154 } 1155 1156 uint32_t 1157 radeonfb_getpll(struct radeonfb_softc *sc, uint32_t idx) 1158 { 1159 int s; 1160 uint32_t val; 1161 1162 s = splhigh(); 1163 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, idx & 0x3f); 1164 val = radeonfb_get32(sc, RADEON_CLOCK_CNTL_DATA); 1165 if (HAS_R300CG(sc)) 1166 radeonfb_r300cg_workaround(sc); 1167 splx(s); 1168 1169 return (val); 1170 } 1171 1172 void 1173 radeonfb_putpll(struct radeonfb_softc *sc, uint32_t idx, uint32_t val) 1174 { 1175 int s; 1176 1177 s = splhigh(); 1178 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, (idx & 0x3f) | 1179 RADEON_PLL_WR_EN); 1180 radeonfb_put32(sc, RADEON_CLOCK_CNTL_DATA, val); 1181 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, 0); 1182 splx(s); 1183 } 1184 1185 void 1186 radeonfb_maskpll(struct radeonfb_softc *sc, uint32_t idx, 1187 uint32_t andmask, uint32_t ormask) 1188 { 1189 int s; 1190 uint32_t val; 1191 1192 s = splhigh(); 1193 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, (idx & 0x3f) | 1194 RADEON_PLL_WR_EN); 1195 val = radeonfb_get32(sc, RADEON_CLOCK_CNTL_DATA); 1196 val = (val & andmask) | ormask; 1197 radeonfb_put32(sc, RADEON_CLOCK_CNTL_DATA, val); 1198 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, 0); 1199 splx(s); 1200 } 1201 1202 int 1203 radeonfb_scratch_test(struct radeonfb_softc *sc, int reg, uint32_t v) 1204 { 1205 uint32_t saved; 1206 1207 saved = GET32(sc, reg); 1208 PUT32(sc, reg, v); 1209 if (GET32(sc, reg) != v) { 1210 return -1; 1211 } 1212 PUT32(sc, reg, saved); 1213 return 0; 1214 } 1215 1216 uintmax_t 1217 radeonfb_getprop_num(struct radeonfb_softc *sc, const char *name, 1218 uintmax_t defval) 1219 { 1220 prop_number_t pn; 1221 pn = prop_dictionary_get(device_properties(&sc->sc_dev), name); 1222 if (pn == NULL) { 1223 return defval; 1224 } 1225 KASSERT(prop_object_type(pn) == PROP_TYPE_NUMBER); 1226 return (prop_number_integer_value(pn)); 1227 } 1228 1229 int 1230 radeonfb_getclocks(struct radeonfb_softc *sc) 1231 { 1232 bus_addr_t ptr; 1233 int refclk = 0; 1234 int refdiv = 0; 1235 int minpll = 0; 1236 int maxpll = 0; 1237 1238 /* load initial property values if port/board provides them */ 1239 refclk = radeonfb_getprop_num(sc, "refclk", 0) & 0xffff; 1240 refdiv = radeonfb_getprop_num(sc, "refdiv", 0) & 0xffff; 1241 minpll = radeonfb_getprop_num(sc, "minpll", 0) & 0xffffffffU; 1242 maxpll = radeonfb_getprop_num(sc, "maxpll", 0) & 0xffffffffU; 1243 1244 if (refclk && refdiv && minpll && maxpll) 1245 goto dontprobe; 1246 1247 if (!sc->sc_biossz) { 1248 /* no BIOS */ 1249 aprint_verbose("%s: No video BIOS, using default clocks\n", 1250 XNAME(sc)); 1251 if (IS_IGP(sc)) 1252 refclk = refclk ? refclk : 1432; 1253 else 1254 refclk = refclk ? refclk : 2700; 1255 refdiv = refdiv ? refdiv : 12; 1256 minpll = minpll ? minpll : 12500; 1257 maxpll = maxpll ? maxpll : 35000; 1258 } else if (IS_ATOM(sc)) { 1259 /* ATOM BIOS */ 1260 ptr = GETBIOS16(sc, 0x48); 1261 ptr = GETBIOS16(sc, ptr + 32); /* aka MasterDataStart */ 1262 ptr = GETBIOS16(sc, ptr + 12); /* pll info block */ 1263 refclk = refclk ? refclk : GETBIOS16(sc, ptr + 82); 1264 minpll = minpll ? minpll : GETBIOS16(sc, ptr + 78); 1265 maxpll = maxpll ? maxpll : GETBIOS16(sc, ptr + 32); 1266 /* 1267 * ATOM BIOS doesn't supply a reference divider, so we 1268 * have to probe for it. 1269 */ 1270 if (refdiv < 2) 1271 refdiv = GETPLL(sc, RADEON_PPLL_REF_DIV) & 1272 RADEON_PPLL_REF_DIV_MASK; 1273 /* 1274 * if probe is zero, just assume one that should work 1275 * for most parts 1276 */ 1277 if (refdiv < 2) 1278 refdiv = 12; 1279 1280 } else { 1281 /* Legacy BIOS */ 1282 ptr = GETBIOS16(sc, 0x48); 1283 ptr = GETBIOS16(sc, ptr + 0x30); 1284 refclk = refclk ? refclk : GETBIOS16(sc, ptr + 0x0E); 1285 refdiv = refdiv ? refdiv : GETBIOS16(sc, ptr + 0x10); 1286 minpll = minpll ? minpll : GETBIOS32(sc, ptr + 0x12); 1287 maxpll = maxpll ? maxpll : GETBIOS32(sc, ptr + 0x16); 1288 } 1289 1290 1291 dontprobe: 1292 sc->sc_refclk = refclk * 10; 1293 sc->sc_refdiv = refdiv; 1294 sc->sc_minpll = minpll * 10; 1295 sc->sc_maxpll = maxpll * 10; 1296 return 0; 1297 } 1298 1299 int 1300 radeonfb_calc_dividers(struct radeonfb_softc *sc, uint32_t dotclock, 1301 uint32_t *postdivbit, uint32_t *feedbackdiv) 1302 { 1303 int i; 1304 uint32_t outfreq; 1305 int div; 1306 1307 DPRINTF(("dot clock: %u\n", dotclock)); 1308 for (i = 0; (div = radeonfb_dividers[i].divider) != 0; i++) { 1309 outfreq = div * dotclock; 1310 if ((outfreq >= sc->sc_minpll) && 1311 (outfreq <= sc->sc_maxpll)) { 1312 DPRINTF(("outfreq: %u\n", outfreq)); 1313 *postdivbit = 1314 ((uint32_t)radeonfb_dividers[i].mask << 16); 1315 DPRINTF(("post divider: %d (mask %x)\n", div, 1316 *postdivbit)); 1317 break; 1318 } 1319 } 1320 1321 if (div == 0) 1322 return 1; 1323 1324 *feedbackdiv = DIVIDE(sc->sc_refdiv * outfreq, sc->sc_refclk); 1325 DPRINTF(("feedback divider: %d\n", *feedbackdiv)); 1326 return 0; 1327 } 1328 1329 #if 0 1330 #ifdef RADEON_DEBUG 1331 static void 1332 dump_buffer(const char *pfx, void *buffer, unsigned int size) 1333 { 1334 char asc[17]; 1335 unsigned ptr = (unsigned)buffer; 1336 char *start = (char *)(ptr & ~0xf); 1337 char *end = (char *)(ptr + size); 1338 1339 end = (char *)(((unsigned)end + 0xf) & ~0xf); 1340 1341 if (pfx == NULL) { 1342 pfx = ""; 1343 } 1344 1345 while (start < end) { 1346 unsigned offset = (unsigned)start & 0xf; 1347 if (offset == 0) { 1348 printf("%s%x: ", pfx, (unsigned)start); 1349 } 1350 if (((unsigned)start < ptr) || 1351 ((unsigned)start >= (ptr + size))) { 1352 printf(" "); 1353 asc[offset] = ' '; 1354 } else { 1355 printf("%02x", *(unsigned char *)start); 1356 if ((*start >= ' ') && (*start <= '~')) { 1357 asc[offset] = *start; 1358 } else { 1359 asc[offset] = '.'; 1360 } 1361 } 1362 asc[offset + 1] = 0; 1363 if (offset % 2) { 1364 printf(" "); 1365 } 1366 if (offset == 15) { 1367 printf(" %s\n", asc); 1368 } 1369 start++; 1370 } 1371 } 1372 #endif 1373 #endif 1374 1375 int 1376 radeonfb_getconnectors(struct radeonfb_softc *sc) 1377 { 1378 int i; 1379 int found = 0; 1380 1381 for (i = 0; i < 2; i++) { 1382 sc->sc_ports[i].rp_mon_type = RADEON_MT_UNKNOWN; 1383 sc->sc_ports[i].rp_ddc_type = RADEON_DDC_NONE; 1384 sc->sc_ports[i].rp_dac_type = RADEON_DAC_UNKNOWN; 1385 sc->sc_ports[i].rp_conn_type = RADEON_CONN_NONE; 1386 sc->sc_ports[i].rp_tmds_type = RADEON_TMDS_UNKNOWN; 1387 } 1388 1389 /* 1390 * This logic is borrowed from Xorg's radeon driver. 1391 */ 1392 if (!sc->sc_biossz) 1393 goto nobios; 1394 1395 if (IS_ATOM(sc)) { 1396 /* not done yet */ 1397 } else { 1398 uint16_t ptr; 1399 int port = 0; 1400 1401 ptr = GETBIOS16(sc, 0x48); 1402 ptr = GETBIOS16(sc, ptr + 0x50); 1403 for (i = 1; i < 4; i++) { 1404 uint16_t entry; 1405 uint8_t conn, ddc, dac, tmds; 1406 1407 /* 1408 * Parse the connector table. From reading the code, 1409 * it appears to made up of 16-bit entries for each 1410 * connector. The 16-bits are defined as: 1411 * 1412 * bits 12-15 - connector type (0 == end of table) 1413 * bits 8-11 - DDC type 1414 * bits 5-7 - ??? 1415 * bit 4 - TMDS type (1 = EXT, 0 = INT) 1416 * bits 1-3 - ??? 1417 * bit 0 - DAC, 1 = TVDAC, 0 = primary 1418 */ 1419 if (!GETBIOS8(sc, ptr + i * 2) && i > 1) 1420 break; 1421 entry = GETBIOS16(sc, ptr + i * 2); 1422 1423 conn = (entry >> 12) & 0xf; 1424 ddc = (entry >> 8) & 0xf; 1425 dac = (entry & 0x1) ? RADEON_DAC_TVDAC : 1426 RADEON_DAC_PRIMARY; 1427 tmds = ((entry >> 4) & 0x1) ? RADEON_TMDS_EXT : 1428 RADEON_TMDS_INT; 1429 1430 if (conn == RADEON_CONN_NONE) 1431 continue; /* no connector */ 1432 1433 if ((found > 0) && 1434 (sc->sc_ports[port].rp_ddc_type == ddc)) { 1435 /* duplicate entry for same connector */ 1436 continue; 1437 } 1438 1439 /* internal DDC_DVI port gets priority */ 1440 if ((ddc == RADEON_DDC_DVI) || (port == 1)) 1441 port = 0; 1442 else 1443 port = 1; 1444 1445 sc->sc_ports[port].rp_ddc_type = 1446 ddc > RADEON_DDC_CRT2 ? RADEON_DDC_NONE : ddc; 1447 sc->sc_ports[port].rp_dac_type = dac; 1448 sc->sc_ports[port].rp_conn_type = 1449 min(conn, RADEON_CONN_UNSUPPORTED) ; 1450 1451 sc->sc_ports[port].rp_tmds_type = tmds; 1452 1453 if ((conn != RADEON_CONN_DVI_I) && 1454 (conn != RADEON_CONN_DVI_D) && 1455 (tmds == RADEON_TMDS_INT)) 1456 sc->sc_ports[port].rp_tmds_type = 1457 RADEON_TMDS_UNKNOWN; 1458 1459 found += (port + 1); 1460 } 1461 } 1462 1463 nobios: 1464 if (!found) { 1465 DPRINTF(("No connector info in BIOS!\n")); 1466 /* default, port 0 = internal TMDS, port 1 = CRT */ 1467 sc->sc_ports[0].rp_mon_type = RADEON_MT_UNKNOWN; 1468 sc->sc_ports[0].rp_ddc_type = RADEON_DDC_DVI; 1469 sc->sc_ports[0].rp_dac_type = RADEON_DAC_TVDAC; 1470 sc->sc_ports[0].rp_conn_type = RADEON_CONN_DVI_D; 1471 sc->sc_ports[0].rp_tmds_type = RADEON_TMDS_INT; 1472 1473 sc->sc_ports[1].rp_mon_type = RADEON_MT_UNKNOWN; 1474 sc->sc_ports[1].rp_ddc_type = RADEON_DDC_VGA; 1475 sc->sc_ports[1].rp_dac_type = RADEON_DAC_PRIMARY; 1476 sc->sc_ports[1].rp_conn_type = RADEON_CONN_CRT; 1477 sc->sc_ports[1].rp_tmds_type = RADEON_TMDS_EXT; 1478 } 1479 1480 /* 1481 * Fixup for RS300/RS350/RS400 chips, that lack a primary DAC. 1482 * these chips should use TVDAC for the VGA port. 1483 */ 1484 if (HAS_SDAC(sc)) { 1485 if (sc->sc_ports[0].rp_conn_type == RADEON_CONN_CRT) { 1486 sc->sc_ports[0].rp_dac_type = RADEON_DAC_TVDAC; 1487 sc->sc_ports[1].rp_dac_type = RADEON_DAC_PRIMARY; 1488 } else { 1489 sc->sc_ports[1].rp_dac_type = RADEON_DAC_TVDAC; 1490 sc->sc_ports[0].rp_dac_type = RADEON_DAC_PRIMARY; 1491 } 1492 } else if (!HAS_CRTC2(sc)) { 1493 sc->sc_ports[0].rp_dac_type = RADEON_DAC_PRIMARY; 1494 } 1495 1496 for (i = 0; i < 2; i++) { 1497 char edid[128]; 1498 uint8_t ddc; 1499 struct edid_info *eip = &sc->sc_ports[i].rp_edid; 1500 1501 DPRINTF(("Port #%d:\n", i)); 1502 DPRINTF((" conn = %d\n", sc->sc_ports[i].rp_conn_type)); 1503 DPRINTF((" ddc = %d\n", sc->sc_ports[i].rp_ddc_type)); 1504 DPRINTF((" dac = %d\n", sc->sc_ports[i].rp_dac_type)); 1505 DPRINTF((" tmds = %d\n", sc->sc_ports[i].rp_tmds_type)); 1506 1507 sc->sc_ports[i].rp_edid_valid = 0; 1508 ddc = sc->sc_ports[i].rp_ddc_type; 1509 if (ddc != RADEON_DDC_NONE) { 1510 if ((radeonfb_i2c_read_edid(sc, ddc, edid) == 0) && 1511 (edid_parse(edid, eip) == 0)) { 1512 sc->sc_ports[i].rp_edid_valid = 1; 1513 edid_print(eip); 1514 } 1515 } 1516 } 1517 1518 return found; 1519 } 1520 1521 int 1522 radeonfb_gettmds(struct radeonfb_softc *sc) 1523 { 1524 int i; 1525 1526 if (!sc->sc_biossz) { 1527 goto nobios; 1528 } 1529 1530 if (IS_ATOM(sc)) { 1531 /* XXX: not done yet */ 1532 } else { 1533 uint16_t ptr; 1534 int n; 1535 1536 ptr = GETBIOS16(sc, 0x48); 1537 ptr = GETBIOS16(sc, ptr + 0x34); 1538 DPRINTF(("DFP table revision %d\n", GETBIOS8(sc, ptr))); 1539 if (GETBIOS8(sc, ptr) == 3) { 1540 /* revision three table */ 1541 n = GETBIOS8(sc, ptr + 5) + 1; 1542 n = min(n, 4); 1543 1544 memset(sc->sc_tmds_pll, 0, sizeof (sc->sc_tmds_pll)); 1545 for (i = 0; i < n; i++) { 1546 sc->sc_tmds_pll[i].rtp_pll = GETBIOS32(sc, 1547 ptr + i * 10 + 8); 1548 sc->sc_tmds_pll[i].rtp_freq = GETBIOS16(sc, 1549 ptr + i * 10 + 0x10); 1550 DPRINTF(("TMDS_PLL dot clock %d pll %x\n", 1551 sc->sc_tmds_pll[i].rtp_freq, 1552 sc->sc_tmds_pll[i].rtp_pll)); 1553 } 1554 return 0; 1555 } 1556 } 1557 1558 nobios: 1559 DPRINTF(("no suitable DFP table present\n")); 1560 for (i = 0; 1561 i < sizeof (radeonfb_tmds_pll) / sizeof (radeonfb_tmds_pll[0]); 1562 i++) { 1563 int j; 1564 1565 if (radeonfb_tmds_pll[i].family != sc->sc_family) 1566 continue; 1567 1568 for (j = 0; j < 4; j++) { 1569 sc->sc_tmds_pll[j] = radeonfb_tmds_pll[i].plls[j]; 1570 DPRINTF(("TMDS_PLL dot clock %d pll %x\n", 1571 sc->sc_tmds_pll[j].rtp_freq, 1572 sc->sc_tmds_pll[j].rtp_pll)); 1573 } 1574 return 0; 1575 } 1576 1577 return -1; 1578 } 1579 1580 const struct videomode * 1581 radeonfb_modelookup(const char *name) 1582 { 1583 int i; 1584 1585 for (i = 0; i < videomode_count; i++) 1586 if (!strcmp(name, videomode_list[i].name)) 1587 return &videomode_list[i]; 1588 1589 return NULL; 1590 } 1591 1592 void 1593 radeonfb_pllwriteupdate(struct radeonfb_softc *sc, int crtc) 1594 { 1595 if (crtc) { 1596 while (GETPLL(sc, RADEON_P2PLL_REF_DIV) & 1597 RADEON_P2PLL_ATOMIC_UPDATE_R); 1598 SETPLL(sc, RADEON_P2PLL_REF_DIV, RADEON_P2PLL_ATOMIC_UPDATE_W); 1599 } else { 1600 while (GETPLL(sc, RADEON_PPLL_REF_DIV) & 1601 RADEON_PPLL_ATOMIC_UPDATE_R); 1602 SETPLL(sc, RADEON_PPLL_REF_DIV, RADEON_PPLL_ATOMIC_UPDATE_W); 1603 } 1604 } 1605 1606 void 1607 radeonfb_pllwaitatomicread(struct radeonfb_softc *sc, int crtc) 1608 { 1609 int i; 1610 1611 for (i = 10000; i; i--) { 1612 if (crtc) { 1613 if (GETPLL(sc, RADEON_P2PLL_REF_DIV) & 1614 RADEON_P2PLL_ATOMIC_UPDATE_R) 1615 break; 1616 } else { 1617 if (GETPLL(sc, RADEON_PPLL_REF_DIV) & 1618 RADEON_PPLL_ATOMIC_UPDATE_R) 1619 break; 1620 } 1621 } 1622 } 1623 1624 void 1625 radeonfb_program_vclk(struct radeonfb_softc *sc, int dotclock, int crtc) 1626 { 1627 uint32_t pbit = 0; 1628 uint32_t feed = 0; 1629 uint32_t data; 1630 #if 1 1631 int i; 1632 #endif 1633 1634 radeonfb_calc_dividers(sc, dotclock, &pbit, &feed); 1635 1636 if (crtc == 0) { 1637 1638 /* XXXX: mobility workaround missing */ 1639 /* XXXX: R300 stuff missing */ 1640 1641 PATCHPLL(sc, RADEON_VCLK_ECP_CNTL, 1642 RADEON_VCLK_SRC_SEL_CPUCLK, 1643 ~RADEON_VCLK_SRC_SEL_MASK); 1644 1645 /* put vclk into reset, use atomic updates */ 1646 SETPLL(sc, RADEON_PPLL_CNTL, 1647 RADEON_PPLL_REFCLK_SEL | 1648 RADEON_PPLL_FBCLK_SEL | 1649 RADEON_PPLL_RESET | 1650 RADEON_PPLL_ATOMIC_UPDATE_EN | 1651 RADEON_PPLL_VGA_ATOMIC_UPDATE_EN); 1652 1653 /* select clock 3 */ 1654 #if 0 1655 PATCH32(sc, RADEON_CLOCK_CNTL_INDEX, RADEON_PLL_DIV_SEL, 1656 ~RADEON_PLL_DIV_SEL); 1657 #else 1658 PATCH32(sc, RADEON_CLOCK_CNTL_INDEX, 0, 1659 ~RADEON_PLL_DIV_SEL); 1660 #endif 1661 1662 /* XXX: R300 family -- program divider differently? */ 1663 1664 /* program reference divider */ 1665 PATCHPLL(sc, RADEON_PPLL_REF_DIV, sc->sc_refdiv, 1666 ~RADEON_PPLL_REF_DIV_MASK); 1667 PRINTPLL(RADEON_PPLL_REF_DIV); 1668 1669 #if 0 1670 data = GETPLL(sc, RADEON_PPLL_DIV_3); 1671 data &= ~(RADEON_PPLL_FB3_DIV_MASK | 1672 RADEON_PPLL_POST3_DIV_MASK); 1673 data |= pbit; 1674 data |= (feed & RADEON_PPLL_FB3_DIV_MASK); 1675 PUTPLL(sc, RADEON_PPLL_DIV_3, data); 1676 #else 1677 for (i = 0; i < 4; i++) { 1678 } 1679 #endif 1680 1681 /* use the atomic update */ 1682 radeonfb_pllwriteupdate(sc, crtc); 1683 1684 /* and wait for it to complete */ 1685 radeonfb_pllwaitatomicread(sc, crtc); 1686 1687 /* program HTOTAL (why?) */ 1688 PUTPLL(sc, RADEON_HTOTAL_CNTL, 0); 1689 1690 /* drop reset */ 1691 CLRPLL(sc, RADEON_PPLL_CNTL, 1692 RADEON_PPLL_RESET | RADEON_PPLL_SLEEP | 1693 RADEON_PPLL_ATOMIC_UPDATE_EN | 1694 RADEON_PPLL_VGA_ATOMIC_UPDATE_EN); 1695 1696 PRINTPLL(RADEON_PPLL_CNTL); 1697 1698 /* give clock time to lock */ 1699 delay(50000); 1700 1701 PATCHPLL(sc, RADEON_VCLK_ECP_CNTL, 1702 RADEON_VCLK_SRC_SEL_PPLLCLK, 1703 ~RADEON_VCLK_SRC_SEL_MASK); 1704 1705 } else { 1706 1707 PATCHPLL(sc, RADEON_PIXCLKS_CNTL, 1708 RADEON_PIX2CLK_SRC_SEL_CPUCLK, 1709 ~RADEON_PIX2CLK_SRC_SEL_MASK); 1710 1711 /* put vclk into reset, use atomic updates */ 1712 SETPLL(sc, RADEON_P2PLL_CNTL, 1713 RADEON_P2PLL_RESET | 1714 RADEON_P2PLL_ATOMIC_UPDATE_EN | 1715 RADEON_P2PLL_VGA_ATOMIC_UPDATE_EN); 1716 1717 /* XXX: R300 family -- program divider differently? */ 1718 1719 /* program reference divider */ 1720 PATCHPLL(sc, RADEON_P2PLL_REF_DIV, sc->sc_refdiv, 1721 ~RADEON_P2PLL_REF_DIV_MASK); 1722 1723 /* program feedback and post dividers */ 1724 data = GETPLL(sc, RADEON_P2PLL_DIV_0); 1725 data &= ~(RADEON_P2PLL_FB0_DIV_MASK | 1726 RADEON_P2PLL_POST0_DIV_MASK); 1727 data |= pbit; 1728 data |= (feed & RADEON_P2PLL_FB0_DIV_MASK); 1729 PUTPLL(sc, RADEON_P2PLL_DIV_0, data); 1730 1731 /* use the atomic update */ 1732 radeonfb_pllwriteupdate(sc, crtc); 1733 1734 /* and wait for it to complete */ 1735 radeonfb_pllwaitatomicread(sc, crtc); 1736 1737 /* program HTOTAL (why?) */ 1738 PUTPLL(sc, RADEON_HTOTAL2_CNTL, 0); 1739 1740 /* drop reset */ 1741 CLRPLL(sc, RADEON_P2PLL_CNTL, 1742 RADEON_P2PLL_RESET | RADEON_P2PLL_SLEEP | 1743 RADEON_P2PLL_ATOMIC_UPDATE_EN | 1744 RADEON_P2PLL_VGA_ATOMIC_UPDATE_EN); 1745 1746 /* allow time for clock to lock */ 1747 delay(50000); 1748 1749 PATCHPLL(sc, RADEON_PIXCLKS_CNTL, 1750 RADEON_PIX2CLK_SRC_SEL_P2PLLCLK, 1751 ~RADEON_PIX2CLK_SRC_SEL_MASK); 1752 } 1753 PRINTREG(RADEON_CRTC_MORE_CNTL); 1754 } 1755 1756 void 1757 radeonfb_modeswitch(struct radeonfb_display *dp) 1758 { 1759 struct radeonfb_softc *sc = dp->rd_softc; 1760 int i; 1761 1762 /* blank the display while we switch modes */ 1763 //radeonfb_blank(dp, 1); 1764 1765 #if 0 1766 SET32(sc, RADEON_CRTC_EXT_CNTL, 1767 RADEON_CRTC_VSYNC_DIS | RADEON_CRTC_HSYNC_DIS | 1768 RADEON_CRTC_DISPLAY_DIS /* | RADEON_CRTC_DISP_REQ_EN_B */); 1769 #endif 1770 1771 /* these registers might get in the way... */ 1772 PUT32(sc, RADEON_OVR_CLR, 0); 1773 PUT32(sc, RADEON_OVR_WID_LEFT_RIGHT, 0); 1774 PUT32(sc, RADEON_OVR_WID_TOP_BOTTOM, 0); 1775 PUT32(sc, RADEON_OV0_SCALE_CNTL, 0); 1776 PUT32(sc, RADEON_SUBPIC_CNTL, 0); 1777 PUT32(sc, RADEON_VIPH_CONTROL, 0); 1778 PUT32(sc, RADEON_I2C_CNTL_1, 0); 1779 PUT32(sc, RADEON_GEN_INT_CNTL, 0); 1780 PUT32(sc, RADEON_CAP0_TRIG_CNTL, 0); 1781 PUT32(sc, RADEON_CAP1_TRIG_CNTL, 0); 1782 PUT32(sc, RADEON_SURFACE_CNTL, 0); 1783 1784 for (i = 0; i < dp->rd_ncrtcs; i++) 1785 radeonfb_setcrtc(dp, i); 1786 1787 /* activate the display */ 1788 //radeonfb_blank(dp, 0); 1789 } 1790 1791 void 1792 radeonfb_setcrtc(struct radeonfb_display *dp, int index) 1793 { 1794 int crtc; 1795 struct videomode *mode; 1796 struct radeonfb_softc *sc; 1797 struct radeonfb_crtc *cp; 1798 uint32_t v; 1799 uint32_t gencntl; 1800 uint32_t htotaldisp; 1801 uint32_t hsyncstrt; 1802 uint32_t vtotaldisp; 1803 uint32_t vsyncstrt; 1804 uint32_t fphsyncstrt; 1805 uint32_t fpvsyncstrt; 1806 uint32_t fphtotaldisp; 1807 uint32_t fpvtotaldisp; 1808 uint32_t pitch; 1809 1810 sc = dp->rd_softc; 1811 cp = &dp->rd_crtcs[index]; 1812 crtc = cp->rc_number; 1813 mode = &cp->rc_videomode; 1814 1815 #if 1 1816 pitch = (((dp->rd_virtx * dp->rd_bpp) + ((dp->rd_bpp * 8) - 1)) / 1817 (dp->rd_bpp * 8)); 1818 #else 1819 pitch = (((sc->sc_maxx * sc->sc_maxbpp) + ((sc->sc_maxbpp * 8) - 1)) / 1820 (sc->sc_maxbpp * 8)); 1821 #endif 1822 //pitch = pitch | (pitch << 16); 1823 1824 switch (crtc) { 1825 case 0: 1826 gencntl = RADEON_CRTC_GEN_CNTL; 1827 htotaldisp = RADEON_CRTC_H_TOTAL_DISP; 1828 hsyncstrt = RADEON_CRTC_H_SYNC_STRT_WID; 1829 vtotaldisp = RADEON_CRTC_V_TOTAL_DISP; 1830 vsyncstrt = RADEON_CRTC_V_SYNC_STRT_WID; 1831 fpvsyncstrt = RADEON_FP_V_SYNC_STRT_WID; 1832 fphsyncstrt = RADEON_FP_H_SYNC_STRT_WID; 1833 fpvtotaldisp = RADEON_FP_CRTC_V_TOTAL_DISP; 1834 fphtotaldisp = RADEON_FP_CRTC_H_TOTAL_DISP; 1835 break; 1836 case 1: 1837 gencntl = RADEON_CRTC2_GEN_CNTL; 1838 htotaldisp = RADEON_CRTC2_H_TOTAL_DISP; 1839 hsyncstrt = RADEON_CRTC2_H_SYNC_STRT_WID; 1840 vtotaldisp = RADEON_CRTC2_V_TOTAL_DISP; 1841 vsyncstrt = RADEON_CRTC2_V_SYNC_STRT_WID; 1842 fpvsyncstrt = RADEON_FP_V2_SYNC_STRT_WID; 1843 fphsyncstrt = RADEON_FP_H2_SYNC_STRT_WID; 1844 fpvtotaldisp = RADEON_FP_CRTC2_V_TOTAL_DISP; 1845 fphtotaldisp = RADEON_FP_CRTC2_H_TOTAL_DISP; 1846 break; 1847 default: 1848 panic("Bad CRTC!"); 1849 break; 1850 } 1851 1852 /* 1853 * CRTC_GEN_CNTL - depth, accelerator mode, etc. 1854 */ 1855 /* only bother with 32bpp and 8bpp */ 1856 v = dp->rd_format << RADEON_CRTC_PIX_WIDTH_SHIFT; 1857 1858 if (crtc == 1) { 1859 v |= RADEON_CRTC2_CRT2_ON | RADEON_CRTC2_EN; 1860 } else { 1861 v |= RADEON_CRTC_EXT_DISP_EN | RADEON_CRTC_EN; 1862 } 1863 1864 if (mode->flags & VID_DBLSCAN) 1865 v |= RADEON_CRTC2_DBL_SCAN_EN; 1866 1867 if (mode->flags & VID_INTERLACE) 1868 v |= RADEON_CRTC2_INTERLACE_EN; 1869 1870 if (mode->flags & VID_CSYNC) { 1871 v |= RADEON_CRTC2_CSYNC_EN; 1872 if (crtc == 1) 1873 v |= RADEON_CRTC2_VSYNC_TRISTAT; 1874 } 1875 1876 PUT32(sc, gencntl, v); 1877 DPRINTF(("CRTC%s_GEN_CNTL = %08x\n", crtc ? "2" : "", v)); 1878 1879 /* 1880 * CRTC_EXT_CNTL - preserve disable flags, set ATI linear and EXT_CNT 1881 */ 1882 v = GET32(sc, RADEON_CRTC_EXT_CNTL); 1883 if (crtc == 0) { 1884 v &= (RADEON_CRTC_VSYNC_DIS | RADEON_CRTC_HSYNC_DIS | 1885 RADEON_CRTC_DISPLAY_DIS); 1886 v |= RADEON_XCRT_CNT_EN | RADEON_VGA_ATI_LINEAR; 1887 if (mode->flags & VID_CSYNC) 1888 v |= RADEON_CRTC_VSYNC_TRISTAT; 1889 } 1890 /* unconditional turn on CRT, in case first CRTC is DFP */ 1891 v |= RADEON_CRTC_CRT_ON; 1892 PUT32(sc, RADEON_CRTC_EXT_CNTL, v); 1893 PRINTREG(RADEON_CRTC_EXT_CNTL); 1894 1895 /* 1896 * H_TOTAL_DISP 1897 */ 1898 v = ((mode->hdisplay / 8) - 1) << 16; 1899 v |= (mode->htotal / 8) - 1; 1900 PUT32(sc, htotaldisp, v); 1901 DPRINTF(("CRTC%s_H_TOTAL_DISP = %08x\n", crtc ? "2" : "", v)); 1902 PUT32(sc, fphtotaldisp, v); 1903 DPRINTF(("FP_H%s_TOTAL_DISP = %08x\n", crtc ? "2" : "", v)); 1904 1905 /* 1906 * H_SYNC_STRT_WID 1907 */ 1908 v = (((mode->hsync_end - mode->hsync_start) / 8) << 16); 1909 v |= mode->hsync_start; 1910 if (mode->flags & VID_NHSYNC) 1911 v |= RADEON_CRTC_H_SYNC_POL; 1912 PUT32(sc, hsyncstrt, v); 1913 DPRINTF(("CRTC%s_H_SYNC_STRT_WID = %08x\n", crtc ? "2" : "", v)); 1914 PUT32(sc, fphsyncstrt, v); 1915 DPRINTF(("FP_H%s_SYNC_STRT_WID = %08x\n", crtc ? "2" : "", v)); 1916 1917 /* 1918 * V_TOTAL_DISP 1919 */ 1920 v = ((mode->vdisplay - 1) << 16); 1921 v |= (mode->vtotal - 1); 1922 PUT32(sc, vtotaldisp, v); 1923 DPRINTF(("CRTC%s_V_TOTAL_DISP = %08x\n", crtc ? "2" : "", v)); 1924 PUT32(sc, fpvtotaldisp, v); 1925 DPRINTF(("FP_V%s_TOTAL_DISP = %08x\n", crtc ? "2" : "", v)); 1926 1927 /* 1928 * V_SYNC_STRT_WID 1929 */ 1930 v = ((mode->vsync_end - mode->vsync_start) << 16); 1931 v |= (mode->vsync_start - 1); 1932 if (mode->flags & VID_NVSYNC) 1933 v |= RADEON_CRTC_V_SYNC_POL; 1934 PUT32(sc, vsyncstrt, v); 1935 DPRINTF(("CRTC%s_V_SYNC_STRT_WID = %08x\n", crtc ? "2" : "", v)); 1936 PUT32(sc, fpvsyncstrt, v); 1937 DPRINTF(("FP_V%s_SYNC_STRT_WID = %08x\n", crtc ? "2" : "", v)); 1938 1939 radeonfb_program_vclk(sc, mode->dot_clock, crtc); 1940 1941 switch (crtc) { 1942 case 0: 1943 PUT32(sc, RADEON_CRTC_OFFSET, 0); 1944 PUT32(sc, RADEON_CRTC_OFFSET_CNTL, 0); 1945 PUT32(sc, RADEON_CRTC_PITCH, pitch); 1946 CLR32(sc, RADEON_DISP_MERGE_CNTL, RADEON_DISP_RGB_OFFSET_EN); 1947 1948 CLR32(sc, RADEON_CRTC_EXT_CNTL, 1949 RADEON_CRTC_VSYNC_DIS | RADEON_CRTC_HSYNC_DIS | 1950 RADEON_CRTC_DISPLAY_DIS /* | RADEON_CRTC_DISP_REQ_EN_B */); 1951 CLR32(sc, RADEON_CRTC_GEN_CNTL, RADEON_CRTC_DISP_REQ_EN_B); 1952 PRINTREG(RADEON_CRTC_EXT_CNTL); 1953 PRINTREG(RADEON_CRTC_GEN_CNTL); 1954 PRINTREG(RADEON_CLOCK_CNTL_INDEX); 1955 break; 1956 1957 case 1: 1958 PUT32(sc, RADEON_CRTC2_OFFSET, 0); 1959 PUT32(sc, RADEON_CRTC2_OFFSET_CNTL, 0); 1960 PUT32(sc, RADEON_CRTC2_PITCH, pitch); 1961 CLR32(sc, RADEON_DISP2_MERGE_CNTL, RADEON_DISP2_RGB_OFFSET_EN); 1962 CLR32(sc, RADEON_CRTC2_GEN_CNTL, 1963 RADEON_CRTC2_VSYNC_DIS | 1964 RADEON_CRTC2_HSYNC_DIS | 1965 RADEON_CRTC2_DISP_DIS | RADEON_CRTC2_DISP_REQ_EN_B); 1966 PRINTREG(RADEON_CRTC2_GEN_CNTL); 1967 break; 1968 } 1969 } 1970 1971 int 1972 radeonfb_isblank(struct radeonfb_display *dp) 1973 { 1974 uint32_t reg, mask; 1975 1976 if (dp->rd_crtcs[0].rc_number) { 1977 reg = RADEON_CRTC2_GEN_CNTL; 1978 mask = RADEON_CRTC2_DISP_DIS; 1979 } else { 1980 reg = RADEON_CRTC_EXT_CNTL; 1981 mask = RADEON_CRTC_DISPLAY_DIS; 1982 } 1983 return ((GET32(dp->rd_softc, reg) & mask) ? 1 : 0); 1984 } 1985 1986 void 1987 radeonfb_blank(struct radeonfb_display *dp, int blank) 1988 { 1989 struct radeonfb_softc *sc = dp->rd_softc; 1990 uint32_t reg, mask; 1991 uint32_t fpreg, fpval; 1992 int i; 1993 1994 for (i = 0; i < dp->rd_ncrtcs; i++) { 1995 1996 if (dp->rd_crtcs[i].rc_number) { 1997 reg = RADEON_CRTC2_GEN_CNTL; 1998 mask = RADEON_CRTC2_DISP_DIS; 1999 fpreg = RADEON_FP2_GEN_CNTL; 2000 fpval = RADEON_FP2_ON; 2001 } else { 2002 reg = RADEON_CRTC_EXT_CNTL; 2003 mask = RADEON_CRTC_DISPLAY_DIS; 2004 fpreg = RADEON_FP_GEN_CNTL; 2005 fpval = RADEON_FP_FPON; 2006 } 2007 2008 if (blank) { 2009 SET32(sc, reg, mask); 2010 CLR32(sc, fpreg, fpval); 2011 } else { 2012 CLR32(sc, reg, mask); 2013 SET32(sc, fpreg, fpval); 2014 } 2015 } 2016 PRINTREG(RADEON_FP_GEN_CNTL); 2017 PRINTREG(RADEON_FP2_GEN_CNTL); 2018 } 2019 2020 void 2021 radeonfb_init_screen(void *cookie, struct vcons_screen *scr, int existing, 2022 long *defattr) 2023 { 2024 struct radeonfb_display *dp = cookie; 2025 struct rasops_info *ri = &scr->scr_ri; 2026 2027 /* initialize font subsystem */ 2028 wsfont_init(); 2029 2030 DPRINTF(("init screen called, existing %d\n", existing)); 2031 2032 ri->ri_depth = dp->rd_bpp; 2033 ri->ri_width = dp->rd_virtx; 2034 ri->ri_height = dp->rd_virty; 2035 ri->ri_stride = dp->rd_stride; 2036 ri->ri_flg = RI_CENTER; 2037 ri->ri_bits = (void *)dp->rd_fbptr; 2038 2039 /* XXX: 32 bpp only */ 2040 /* this is rgb in "big-endian order..." */ 2041 ri->ri_rnum = 8; 2042 ri->ri_gnum = 8; 2043 ri->ri_bnum = 8; 2044 ri->ri_rpos = 16; 2045 ri->ri_gpos = 8; 2046 ri->ri_bpos = 0; 2047 2048 if (existing) { 2049 ri->ri_flg |= RI_CLEAR; 2050 2051 /* start a modeswitch now */ 2052 radeonfb_modeswitch(dp); 2053 } 2054 2055 /* 2056 * XXX: font selection should be based on properties, with some 2057 * normal/reasonable default. 2058 */ 2059 ri->ri_caps = WSSCREEN_WSCOLORS; 2060 2061 /* initialize and look for an initial font */ 2062 rasops_init(ri, dp->rd_virty/8, dp->rd_virtx/8); 2063 2064 rasops_reconfig(ri, dp->rd_virty / ri->ri_font->fontheight, 2065 dp->rd_virtx / ri->ri_font->fontwidth); 2066 2067 /* enable acceleration */ 2068 ri->ri_ops.copyrows = radeonfb_copyrows; 2069 ri->ri_ops.copycols = radeonfb_copycols; 2070 ri->ri_ops.eraserows = radeonfb_eraserows; 2071 ri->ri_ops.erasecols = radeonfb_erasecols; 2072 ri->ri_ops.allocattr = radeonfb_allocattr; 2073 ri->ri_ops.putchar = radeonfb_putchar; 2074 ri->ri_ops.cursor = radeonfb_cursor; 2075 } 2076 2077 void 2078 radeonfb_set_fbloc(struct radeonfb_softc *sc) 2079 { 2080 uint32_t gen, ext, gen2 = 0; 2081 uint32_t agploc, aperbase, apersize, mcfbloc; 2082 2083 gen = GET32(sc, RADEON_CRTC_GEN_CNTL); 2084 ext = GET32(sc, RADEON_CRTC_EXT_CNTL); 2085 agploc = GET32(sc, RADEON_MC_AGP_LOCATION); 2086 aperbase = GET32(sc, RADEON_CONFIG_APER_0_BASE); 2087 apersize = GET32(sc, RADEON_CONFIG_APER_SIZE); 2088 2089 PUT32(sc, RADEON_CRTC_GEN_CNTL, gen | RADEON_CRTC_DISP_REQ_EN_B); 2090 PUT32(sc, RADEON_CRTC_EXT_CNTL, ext | RADEON_CRTC_DISPLAY_DIS); 2091 //PUT32(sc, RADEON_CRTC_GEN_CNTL, gen | RADEON_CRTC_DISPLAY_DIS); 2092 //PUT32(sc, RADEON_CRTC_EXT_CNTL, ext | RADEON_CRTC_DISP_REQ_EN_B); 2093 2094 if (HAS_CRTC2(sc)) { 2095 gen2 = GET32(sc, RADEON_CRTC2_GEN_CNTL); 2096 PUT32(sc, RADEON_CRTC2_GEN_CNTL, 2097 gen2 | RADEON_CRTC2_DISP_REQ_EN_B); 2098 } 2099 2100 delay(100000); 2101 2102 mcfbloc = (aperbase >> 16) | 2103 ((aperbase + (apersize - 1)) & 0xffff0000); 2104 2105 sc->sc_aperbase = (mcfbloc & 0xffff) << 16; 2106 sc->sc_memsz = apersize; 2107 2108 if (((agploc & 0xffff) << 16) != 2109 ((mcfbloc & 0xffff0000U) + 0x10000)) { 2110 agploc = mcfbloc & 0xffff0000U; 2111 agploc |= ((agploc + 0x10000) >> 16); 2112 } 2113 2114 PUT32(sc, RADEON_HOST_PATH_CNTL, 0); 2115 2116 PUT32(sc, RADEON_MC_FB_LOCATION, mcfbloc); 2117 PUT32(sc, RADEON_MC_AGP_LOCATION, agploc); 2118 2119 DPRINTF(("aperbase = %u\n", aperbase)); 2120 PRINTREG(RADEON_MC_FB_LOCATION); 2121 PRINTREG(RADEON_MC_AGP_LOCATION); 2122 2123 PUT32(sc, RADEON_DISPLAY_BASE_ADDR, sc->sc_aperbase); 2124 2125 if (HAS_CRTC2(sc)) 2126 PUT32(sc, RADEON_DISPLAY2_BASE_ADDR, sc->sc_aperbase); 2127 2128 PUT32(sc, RADEON_OV0_BASE_ADDR, sc->sc_aperbase); 2129 2130 #if 0 2131 /* XXX: what is this AGP garbage? :-) */ 2132 PUT32(sc, RADEON_AGP_CNTL, 0x00100000); 2133 #endif 2134 2135 delay(100000); 2136 2137 PUT32(sc, RADEON_CRTC_GEN_CNTL, gen); 2138 PUT32(sc, RADEON_CRTC_EXT_CNTL, ext); 2139 2140 if (HAS_CRTC2(sc)) 2141 PUT32(sc, RADEON_CRTC2_GEN_CNTL, gen2); 2142 } 2143 2144 void 2145 radeonfb_init_misc(struct radeonfb_softc *sc) 2146 { 2147 PUT32(sc, RADEON_BUS_CNTL, 2148 RADEON_BUS_MASTER_DIS | 2149 RADEON_BUS_PREFETCH_MODE_ACT | 2150 RADEON_BUS_PCI_READ_RETRY_EN | 2151 RADEON_BUS_PCI_WRT_RETRY_EN | 2152 (3 << RADEON_BUS_RETRY_WS_SHIFT) | 2153 RADEON_BUS_MSTR_RD_MULT | 2154 RADEON_BUS_MSTR_RD_LINE | 2155 RADEON_BUS_RD_DISCARD_EN | 2156 RADEON_BUS_MSTR_DISCONNECT_EN | 2157 RADEON_BUS_READ_BURST); 2158 2159 PUT32(sc, RADEON_BUS_CNTL1, 0xf0); 2160 /* PUT32(sc, RADEON_SEPROM_CNTL1, 0x09ff0000); */ 2161 PUT32(sc, RADEON_FCP_CNTL, RADEON_FCP0_SRC_GND); 2162 PUT32(sc, RADEON_RBBM_CNTL, 2163 (3 << RADEON_RB_SETTLE_SHIFT) | 2164 (4 << RADEON_ABORTCLKS_HI_SHIFT) | 2165 (4 << RADEON_ABORTCLKS_CP_SHIFT) | 2166 (4 << RADEON_ABORTCLKS_CFIFO_SHIFT)); 2167 2168 /* XXX: figure out what these mean! */ 2169 PUT32(sc, RADEON_AGP_CNTL, 0x00100000); 2170 PUT32(sc, RADEON_HOST_PATH_CNTL, 0); 2171 //PUT32(sc, RADEON_DISP_MISC_CNTL, 0x5bb00400); 2172 2173 PUT32(sc, RADEON_GEN_INT_CNTL, 0); 2174 PUT32(sc, RADEON_GEN_INT_STATUS, GET32(sc, RADEON_GEN_INT_STATUS)); 2175 } 2176 2177 /* 2178 * This loads a linear color map for true color. 2179 */ 2180 void 2181 radeonfb_init_palette(struct radeonfb_softc *sc, int crtc) 2182 { 2183 int i; 2184 uint32_t vclk; 2185 2186 #define DAC_WIDTH ((1 << 10) - 1) 2187 #define CLUT_WIDTH ((1 << 8) - 1) 2188 #define CLUT_COLOR(i) ((i * DAC_WIDTH * 2 / CLUT_WIDTH + 1) / 2) 2189 2190 vclk = GETPLL(sc, RADEON_VCLK_ECP_CNTL); 2191 PUTPLL(sc, RADEON_VCLK_ECP_CNTL, vclk & ~RADEON_PIXCLK_DAC_ALWAYS_ONb); 2192 2193 if (crtc) 2194 SET32(sc, RADEON_DAC_CNTL2, RADEON_DAC2_PALETTE_ACC_CTL); 2195 else 2196 CLR32(sc, RADEON_DAC_CNTL2, RADEON_DAC2_PALETTE_ACC_CTL); 2197 2198 PUT32(sc, RADEON_PALETTE_INDEX, 0); 2199 for (i = 0; i <= CLUT_WIDTH; ++i) { 2200 PUT32(sc, RADEON_PALETTE_30_DATA, 2201 (CLUT_COLOR(i) << 10) | 2202 (CLUT_COLOR(i) << 20) | 2203 (CLUT_COLOR(i))); 2204 } 2205 2206 CLR32(sc, RADEON_DAC_CNTL2, RADEON_DAC2_PALETTE_ACC_CTL); 2207 PRINTREG(RADEON_DAC_CNTL2); 2208 2209 PUTPLL(sc, RADEON_VCLK_ECP_CNTL, vclk); 2210 } 2211 2212 /* 2213 * Bugs in some R300 hardware requires this when accessing CLOCK_CNTL_INDEX. 2214 */ 2215 void 2216 radeonfb_r300cg_workaround(struct radeonfb_softc *sc) 2217 { 2218 uint32_t tmp, save; 2219 2220 save = GET32(sc, RADEON_CLOCK_CNTL_INDEX); 2221 tmp = save & ~(0x3f | RADEON_PLL_WR_EN); 2222 PUT32(sc, RADEON_CLOCK_CNTL_INDEX, tmp); 2223 tmp = GET32(sc, RADEON_CLOCK_CNTL_DATA); 2224 PUT32(sc, RADEON_CLOCK_CNTL_INDEX, save); 2225 } 2226 2227 /* 2228 * Acceleration entry points. 2229 */ 2230 static void 2231 radeonfb_putchar(void *cookie, int row, int col, u_int c, long attr) 2232 { 2233 struct rasops_info *ri = cookie; 2234 struct vcons_screen *scr = ri->ri_hw; 2235 struct radeonfb_display *dp = scr->scr_cookie; 2236 uint32_t x, y, w, h; 2237 uint32_t bg, fg; 2238 uint8_t *data; 2239 2240 if (dp->rd_wsmode != WSDISPLAYIO_MODE_EMUL) 2241 return; 2242 2243 if (!CHAR_IN_FONT(c, ri->ri_font)) 2244 return; 2245 2246 w = ri->ri_font->fontwidth; 2247 h = ri->ri_font->fontheight; 2248 2249 bg = ri->ri_devcmap[(attr >> 16) & 0xf]; 2250 fg = ri->ri_devcmap[(attr >> 24) & 0xf]; 2251 2252 x = ri->ri_xorigin + col * w; 2253 y = ri->ri_yorigin + row * h; 2254 2255 if (c == 0x20) { 2256 radeonfb_rectfill(dp, x, y, w, h, bg); 2257 } else { 2258 data = (uint8_t *)ri->ri_font->data + 2259 (c - ri->ri_font->firstchar) * ri->ri_fontscale; 2260 2261 radeonfb_setup_mono(dp, x, y, w, h, fg, bg); 2262 radeonfb_feed_bytes(dp, ri->ri_fontscale, data); 2263 } 2264 } 2265 2266 static void 2267 radeonfb_eraserows(void *cookie, int row, int nrows, long fillattr) 2268 { 2269 struct rasops_info *ri = cookie; 2270 struct vcons_screen *scr = ri->ri_hw; 2271 struct radeonfb_display *dp = scr->scr_cookie; 2272 uint32_t x, y, w, h, fg, bg, ul; 2273 2274 /* XXX: check for full emulation mode? */ 2275 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 2276 x = ri->ri_xorigin; 2277 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 2278 w = ri->ri_emuwidth; 2279 h = ri->ri_font->fontheight * nrows; 2280 2281 rasops_unpack_attr(fillattr, &fg, &bg, &ul); 2282 radeonfb_rectfill(dp, x, y, w, h, ri->ri_devcmap[bg & 0xf]); 2283 } 2284 } 2285 2286 static void 2287 radeonfb_copyrows(void *cookie, int srcrow, int dstrow, int nrows) 2288 { 2289 struct rasops_info *ri = cookie; 2290 struct vcons_screen *scr = ri->ri_hw; 2291 struct radeonfb_display *dp = scr->scr_cookie; 2292 uint32_t x, ys, yd, w, h; 2293 2294 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 2295 x = ri->ri_xorigin; 2296 ys = ri->ri_yorigin + ri->ri_font->fontheight * srcrow; 2297 yd = ri->ri_yorigin + ri->ri_font->fontheight * dstrow; 2298 w = ri->ri_emuwidth; 2299 h = ri->ri_font->fontheight * nrows; 2300 radeonfb_bitblt(dp, x, ys, x, yd, w, h, 2301 RADEON_ROP3_S, 0xffffffff); 2302 } 2303 } 2304 2305 static void 2306 radeonfb_copycols(void *cookie, int row, int srccol, int dstcol, int ncols) 2307 { 2308 struct rasops_info *ri = cookie; 2309 struct vcons_screen *scr = ri->ri_hw; 2310 struct radeonfb_display *dp = scr->scr_cookie; 2311 uint32_t xs, xd, y, w, h; 2312 2313 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 2314 xs = ri->ri_xorigin + ri->ri_font->fontwidth * srccol; 2315 xd = ri->ri_xorigin + ri->ri_font->fontwidth * dstcol; 2316 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 2317 w = ri->ri_font->fontwidth * ncols; 2318 h = ri->ri_font->fontheight; 2319 radeonfb_bitblt(dp, xs, y, xd, y, w, h, 2320 RADEON_ROP3_S, 0xffffffff); 2321 } 2322 } 2323 2324 static void 2325 radeonfb_erasecols(void *cookie, int row, int startcol, int ncols, 2326 long fillattr) 2327 { 2328 struct rasops_info *ri = cookie; 2329 struct vcons_screen *scr = ri->ri_hw; 2330 struct radeonfb_display *dp = scr->scr_cookie; 2331 uint32_t x, y, w, h, fg, bg, ul; 2332 2333 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 2334 x = ri->ri_xorigin + ri->ri_font->fontwidth * startcol; 2335 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 2336 w = ri->ri_font->fontwidth * ncols; 2337 h = ri->ri_font->fontheight; 2338 2339 rasops_unpack_attr(fillattr, &fg, &bg, &ul); 2340 radeonfb_rectfill(dp, x, y, w, h, ri->ri_devcmap[bg & 0xf]); 2341 } 2342 } 2343 2344 static void 2345 radeonfb_cursor(void *cookie, int on, int row, int col) 2346 { 2347 struct rasops_info *ri = cookie; 2348 struct vcons_screen *scr = ri->ri_hw; 2349 struct radeonfb_display *dp = scr->scr_cookie; 2350 int x, y, wi, he; 2351 2352 wi = ri->ri_font->fontwidth; 2353 he = ri->ri_font->fontheight; 2354 2355 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 2356 x = ri->ri_ccol * wi + ri->ri_xorigin; 2357 y = ri->ri_crow * he + ri->ri_yorigin; 2358 /* first turn off the old cursor */ 2359 if (ri->ri_flg & RI_CURSOR) { 2360 radeonfb_bitblt(dp, x, y, x, y, wi, he, 2361 RADEON_ROP3_Dn, 0xffffffff); 2362 ri->ri_flg &= ~RI_CURSOR; 2363 } 2364 ri->ri_crow = row; 2365 ri->ri_ccol = col; 2366 /* then (possibly) turn on the new one */ 2367 if (on) { 2368 x = ri->ri_ccol * wi + ri->ri_xorigin; 2369 y = ri->ri_crow * he + ri->ri_yorigin; 2370 radeonfb_bitblt(dp, x, y, x, y, wi, he, 2371 RADEON_ROP3_Dn, 0xffffffff); 2372 ri->ri_flg |= RI_CURSOR; 2373 } 2374 } else { 2375 scr->scr_ri.ri_crow = row; 2376 scr->scr_ri.ri_ccol = col; 2377 scr->scr_ri.ri_flg &= ~RI_CURSOR; 2378 } 2379 } 2380 2381 static int 2382 radeonfb_allocattr(void *cookie, int fg, int bg, int flags, long *attrp) 2383 { 2384 if ((fg == 0) && (bg == 0)) { 2385 fg = WS_DEFAULT_FG; 2386 bg = WS_DEFAULT_BG; 2387 } 2388 *attrp = ((fg & 0xf) << 24) | ((bg & 0xf) << 16) | (flags & 0xff) << 8; 2389 return 0; 2390 } 2391 2392 /* 2393 * Underlying acceleration support. 2394 */ 2395 static void 2396 radeonfb_setup_mono(struct radeonfb_display *dp, int xd, int yd, int width, 2397 int height, uint32_t fg, uint32_t bg) 2398 { 2399 struct radeonfb_softc *sc = dp->rd_softc; 2400 uint32_t gmc; 2401 uint32_t padded_width = (width+7) & 0xfff8; 2402 uint32_t topleft, bottomright; 2403 2404 gmc = dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT; 2405 2406 if (width != padded_width) { 2407 2408 radeonfb_wait_fifo(sc, 2); 2409 topleft = ((yd << 16) & 0x1fff0000) | (xd & 0x1fff); 2410 bottomright = (((yd + height) << 16) & 0x1fff0000) | 2411 ((xd + width) & 0x1fff); 2412 PUT32(sc, RADEON_SC_TOP_LEFT, topleft); 2413 PUT32(sc, RADEON_SC_BOTTOM_RIGHT, bottomright); 2414 } 2415 2416 radeonfb_wait_fifo(sc, 5); 2417 2418 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 2419 RADEON_GMC_BRUSH_NONE | 2420 RADEON_GMC_SRC_DATATYPE_MONO_FG_BG | 2421 //RADEON_GMC_BYTE_LSB_TO_MSB | 2422 RADEON_GMC_DST_CLIPPING | 2423 RADEON_ROP3_S | 2424 RADEON_DP_SRC_SOURCE_HOST_DATA | 2425 RADEON_GMC_CLR_CMP_CNTL_DIS | 2426 RADEON_GMC_WR_MSK_DIS | 2427 gmc); 2428 2429 PUT32(sc, RADEON_DP_SRC_FRGD_CLR, fg); 2430 PUT32(sc, RADEON_DP_SRC_BKGD_CLR, bg); 2431 2432 PUT32(sc, RADEON_DST_X_Y, (xd << 16) | yd); 2433 PUT32(sc, RADEON_DST_WIDTH_HEIGHT, (padded_width << 16) | height); 2434 2435 } 2436 2437 static void 2438 radeonfb_feed_bytes(struct radeonfb_display *dp, int count, uint8_t *data) 2439 { 2440 struct radeonfb_softc *sc = dp->rd_softc; 2441 int i; 2442 uint32_t latch = 0; 2443 int shift = 0; 2444 2445 for (i = 0; i < count; i++) { 2446 latch |= (data[i] << shift); 2447 if (shift == 24) { 2448 radeonfb_wait_fifo(sc, 1); 2449 PUT32(sc, RADEON_HOST_DATA0, latch); 2450 latch = 0; 2451 shift = 0; 2452 } else 2453 shift += 8; 2454 } 2455 if (shift != 0) { 2456 radeonfb_wait_fifo(sc, 1); 2457 PUT32(sc, RADEON_HOST_DATA0, latch); 2458 } 2459 radeonfb_unclip(sc); 2460 } 2461 2462 static void 2463 radeonfb_rectfill(struct radeonfb_display *dp, int dstx, int dsty, 2464 int width, int height, uint32_t color) 2465 { 2466 struct radeonfb_softc *sc = dp->rd_softc; 2467 uint32_t gmc; 2468 2469 gmc = dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT; 2470 2471 radeonfb_wait_fifo(sc, 6); 2472 2473 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 2474 RADEON_GMC_BRUSH_SOLID_COLOR | 2475 RADEON_GMC_SRC_DATATYPE_COLOR | 2476 RADEON_GMC_CLR_CMP_CNTL_DIS | 2477 RADEON_ROP3_P | gmc); 2478 2479 PUT32(sc, RADEON_DP_BRUSH_FRGD_CLR, color); 2480 PUT32(sc, RADEON_DP_WRITE_MASK, 0xffffffff); 2481 PUT32(sc, RADEON_DP_CNTL, 2482 RADEON_DST_X_LEFT_TO_RIGHT | 2483 RADEON_DST_Y_TOP_TO_BOTTOM); 2484 PUT32(sc, RADEON_DST_Y_X, (dsty << 16) | dstx); 2485 PUT32(sc, RADEON_DST_WIDTH_HEIGHT, (width << 16) | (height)); 2486 2487 /* 2488 * XXX: we don't wait for the fifo to empty -- that would slow 2489 * things down! The linux radeonfb driver waits, but xfree doesn't 2490 */ 2491 /* XXX: for now we do, to make it safe for direct drawing */ 2492 radeonfb_engine_idle(sc); 2493 } 2494 2495 static void 2496 radeonfb_bitblt(struct radeonfb_display *dp, int srcx, int srcy, 2497 int dstx, int dsty, int width, int height, int rop, uint32_t mask) 2498 { 2499 struct radeonfb_softc *sc = dp->rd_softc; 2500 uint32_t gmc; 2501 uint32_t dir; 2502 2503 if (dsty < srcy) { 2504 dir = RADEON_DST_Y_TOP_TO_BOTTOM; 2505 } else { 2506 srcy += height - 1; 2507 dsty += height - 1; 2508 dir = 0; 2509 } 2510 if (dstx < srcx) { 2511 dir |= RADEON_DST_X_LEFT_TO_RIGHT; 2512 } else { 2513 srcx += width - 1; 2514 dstx += width - 1; 2515 } 2516 2517 gmc = dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT; 2518 2519 radeonfb_wait_fifo(sc, 6); 2520 2521 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 2522 //RADEON_GMC_SRC_CLIPPING | 2523 RADEON_GMC_BRUSH_SOLID_COLOR | 2524 RADEON_GMC_SRC_DATATYPE_COLOR | 2525 RADEON_GMC_CLR_CMP_CNTL_DIS | 2526 RADEON_DP_SRC_SOURCE_MEMORY | 2527 rop | gmc); 2528 2529 PUT32(sc, RADEON_DP_WRITE_MASK, mask); 2530 PUT32(sc, RADEON_DP_CNTL, dir); 2531 PUT32(sc, RADEON_SRC_Y_X, (srcy << 16) | srcx); 2532 PUT32(sc, RADEON_DST_Y_X, (dsty << 16) | dstx); 2533 PUT32(sc, RADEON_DST_WIDTH_HEIGHT, (width << 16) | (height)); 2534 2535 /* 2536 * XXX: we don't wait for the fifo to empty -- that would slow 2537 * things down! The linux radeonfb driver waits, but xfree doesn't 2538 */ 2539 /* XXX: for now we do, to make it safe for direct drawing */ 2540 radeonfb_engine_idle(sc); 2541 } 2542 2543 static void 2544 radeonfb_engine_idle(struct radeonfb_softc *sc) 2545 { 2546 int i; 2547 2548 radeonfb_wait_fifo(sc, 64); 2549 for (i = RADEON_TIMEOUT; i; i--) { 2550 if ((GET32(sc, RADEON_RBBM_STATUS) & 2551 RADEON_RBBM_ACTIVE) == 0) { 2552 radeonfb_engine_flush(sc); 2553 break; 2554 } 2555 } 2556 } 2557 2558 static void 2559 radeonfb_wait_fifo(struct radeonfb_softc *sc, int n) 2560 { 2561 int i; 2562 2563 for (i = RADEON_TIMEOUT; i; i--) { 2564 if ((GET32(sc, RADEON_RBBM_STATUS) & 2565 RADEON_RBBM_FIFOCNT_MASK) >= n) 2566 return; 2567 } 2568 #ifdef DIAGNOSTIC 2569 if (!i) 2570 printf("%s: timed out waiting for fifo (%x)\n", 2571 XNAME(sc), GET32(sc, RADEON_RBBM_STATUS)); 2572 #endif 2573 } 2574 2575 static void 2576 radeonfb_engine_flush(struct radeonfb_softc *sc) 2577 { 2578 int i; 2579 SET32(sc, RADEON_RB2D_DSTCACHE_CTLSTAT, RADEON_RB2D_DC_FLUSH_ALL); 2580 for (i = RADEON_TIMEOUT; i; i--) { 2581 if ((GET32(sc, RADEON_RB2D_DSTCACHE_CTLSTAT) & 2582 RADEON_RB2D_DC_BUSY) == 0) 2583 break; 2584 } 2585 #ifdef DIAGNOSTIC 2586 if (!i) 2587 printf("%s: engine flush timed out!\n", XNAME(sc)); 2588 #endif 2589 } 2590 2591 static inline void 2592 radeonfb_unclip(struct radeonfb_softc *sc) 2593 { 2594 2595 radeonfb_wait_fifo(sc, 2); 2596 PUT32(sc, RADEON_SC_TOP_LEFT, 0); 2597 PUT32(sc, RADEON_SC_BOTTOM_RIGHT, 0x1fff1fff); 2598 } 2599 2600 static void 2601 radeonfb_engine_init(struct radeonfb_display *dp) 2602 { 2603 struct radeonfb_softc *sc = dp->rd_softc; 2604 uint32_t pitch; 2605 2606 /* no 3D */ 2607 PUT32(sc, RADEON_RB3D_CNTL, 0); 2608 2609 radeonfb_engine_reset(sc); 2610 pitch = ((dp->rd_virtx * (dp->rd_bpp / 8) + 0x3f)) >> 6; 2611 //pitch = ((sc->sc_maxx * (sc->sc_maxbpp / 8) + 0x3f)) >> 6; 2612 2613 radeonfb_wait_fifo(sc, 1); 2614 if (!IS_R300(sc)) 2615 PUT32(sc, RADEON_RB2D_DSTCACHE_MODE, 0); 2616 2617 radeonfb_wait_fifo(sc, 3); 2618 PUT32(sc, RADEON_DEFAULT_PITCH_OFFSET, 2619 (pitch << 22) | (sc->sc_aperbase >> 10)); 2620 2621 2622 PUT32(sc, RADEON_DST_PITCH_OFFSET, 2623 (pitch << 22) | (sc->sc_aperbase >> 10)); 2624 PUT32(sc, RADEON_SRC_PITCH_OFFSET, 2625 (pitch << 22) | (sc->sc_aperbase >> 10)); 2626 2627 radeonfb_wait_fifo(sc, 1); 2628 #if _BYTE_ORDER == _BIG_ENDIAN 2629 SET32(sc, RADEON_DP_DATATYPE, RADEON_HOST_BIG_ENDIAN_EN); 2630 #else 2631 CLR32(sc, RADEON_DP_DATATYPE, RADEON_HOST_BIG_ENDIAN_EN); 2632 #endif 2633 2634 /* default scissors -- no clipping */ 2635 radeonfb_wait_fifo(sc, 1); 2636 PUT32(sc, RADEON_DEFAULT_SC_BOTTOM_RIGHT, 2637 RADEON_DEFAULT_SC_RIGHT_MAX | RADEON_DEFAULT_SC_BOTTOM_MAX); 2638 2639 radeonfb_wait_fifo(sc, 1); 2640 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 2641 (dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT) | 2642 RADEON_GMC_CLR_CMP_CNTL_DIS | 2643 RADEON_GMC_BRUSH_SOLID_COLOR | 2644 RADEON_GMC_SRC_DATATYPE_COLOR); 2645 2646 radeonfb_wait_fifo(sc, 7); 2647 PUT32(sc, RADEON_DST_LINE_START, 0); 2648 PUT32(sc, RADEON_DST_LINE_END, 0); 2649 PUT32(sc, RADEON_DP_BRUSH_FRGD_CLR, 0xffffffff); 2650 PUT32(sc, RADEON_DP_BRUSH_BKGD_CLR, 0); 2651 PUT32(sc, RADEON_DP_SRC_FRGD_CLR, 0xffffffff); 2652 PUT32(sc, RADEON_DP_SRC_BKGD_CLR, 0); 2653 PUT32(sc, RADEON_DP_WRITE_MASK, 0xffffffff); 2654 2655 radeonfb_engine_idle(sc); 2656 } 2657 2658 static void 2659 radeonfb_engine_reset(struct radeonfb_softc *sc) 2660 { 2661 uint32_t hpc, rbbm, mclkcntl, clkindex; 2662 2663 radeonfb_engine_flush(sc); 2664 2665 clkindex = GET32(sc, RADEON_CLOCK_CNTL_INDEX); 2666 if (HAS_R300CG(sc)) 2667 radeonfb_r300cg_workaround(sc); 2668 mclkcntl = GETPLL(sc, RADEON_MCLK_CNTL); 2669 2670 /* 2671 * According to comments in XFree code, resetting the HDP via 2672 * the RBBM_SOFT_RESET can cause bad behavior on some systems. 2673 * So we use HOST_PATH_CNTL instead. 2674 */ 2675 2676 hpc = GET32(sc, RADEON_HOST_PATH_CNTL); 2677 rbbm = GET32(sc, RADEON_RBBM_SOFT_RESET); 2678 if (IS_R300(sc)) { 2679 PUT32(sc, RADEON_RBBM_SOFT_RESET, rbbm | 2680 RADEON_SOFT_RESET_CP | 2681 RADEON_SOFT_RESET_HI | 2682 RADEON_SOFT_RESET_E2); 2683 GET32(sc, RADEON_RBBM_SOFT_RESET); 2684 PUT32(sc, RADEON_RBBM_SOFT_RESET, 0); 2685 /* 2686 * XXX: this bit is not defined in any ATI docs I have, 2687 * nor in the XFree code, but XFree does it. Why? 2688 */ 2689 SET32(sc, RADEON_RB2D_DSTCACHE_MODE, (1<<17)); 2690 } else { 2691 PUT32(sc, RADEON_RBBM_SOFT_RESET, rbbm | 2692 RADEON_SOFT_RESET_CP | 2693 RADEON_SOFT_RESET_SE | 2694 RADEON_SOFT_RESET_RE | 2695 RADEON_SOFT_RESET_PP | 2696 RADEON_SOFT_RESET_E2 | 2697 RADEON_SOFT_RESET_RB); 2698 GET32(sc, RADEON_RBBM_SOFT_RESET); 2699 PUT32(sc, RADEON_RBBM_SOFT_RESET, rbbm & 2700 ~(RADEON_SOFT_RESET_CP | 2701 RADEON_SOFT_RESET_SE | 2702 RADEON_SOFT_RESET_RE | 2703 RADEON_SOFT_RESET_PP | 2704 RADEON_SOFT_RESET_E2 | 2705 RADEON_SOFT_RESET_RB)); 2706 GET32(sc, RADEON_RBBM_SOFT_RESET); 2707 } 2708 2709 PUT32(sc, RADEON_HOST_PATH_CNTL, hpc | RADEON_HDP_SOFT_RESET); 2710 GET32(sc, RADEON_HOST_PATH_CNTL); 2711 PUT32(sc, RADEON_HOST_PATH_CNTL, hpc); 2712 2713 if (IS_R300(sc)) 2714 PUT32(sc, RADEON_RBBM_SOFT_RESET, rbbm); 2715 2716 PUT32(sc, RADEON_CLOCK_CNTL_INDEX, clkindex); 2717 PUTPLL(sc, RADEON_MCLK_CNTL, mclkcntl); 2718 2719 if (HAS_R300CG(sc)) 2720 radeonfb_r300cg_workaround(sc); 2721 } 2722 2723 static int 2724 radeonfb_set_curpos(struct radeonfb_display *dp, struct wsdisplay_curpos *pos) 2725 { 2726 int x, y; 2727 2728 x = pos->x; 2729 y = pos->y; 2730 2731 /* 2732 * This doesn't let a cursor move off the screen. I'm not 2733 * sure if this will have negative effects for e.g. Xinerama. 2734 * I'd guess Xinerama handles it by changing the cursor shape, 2735 * but that needs verification. 2736 */ 2737 if (x >= dp->rd_virtx) 2738 x = dp->rd_virtx - 1; 2739 if (x < 0) 2740 x = 0; 2741 if (y >= dp->rd_virty) 2742 y = dp->rd_virty - 1; 2743 if (y < 0) 2744 y = 0; 2745 2746 dp->rd_cursor.rc_pos.x = x; 2747 dp->rd_cursor.rc_pos.y = y; 2748 2749 radeonfb_cursor_position(dp); 2750 return 0; 2751 } 2752 2753 static int 2754 radeonfb_set_cursor(struct radeonfb_display *dp, struct wsdisplay_cursor *wc) 2755 { 2756 unsigned flags; 2757 2758 uint8_t r[2], g[2], b[2]; 2759 unsigned index, count; 2760 int i, err; 2761 int pitch, size; 2762 struct radeonfb_cursor nc; 2763 2764 flags = wc->which; 2765 2766 /* copy old values */ 2767 nc = dp->rd_cursor; 2768 2769 if (flags & WSDISPLAY_CURSOR_DOCMAP) { 2770 index = wc->cmap.index; 2771 count = wc->cmap.count; 2772 2773 if (index >= 2 || (index + count) > 2) 2774 return EINVAL; 2775 2776 err = copyin(wc->cmap.red, &r[index], count); 2777 if (err) 2778 return err; 2779 err = copyin(wc->cmap.green, &g[index], count); 2780 if (err) 2781 return err; 2782 err = copyin(wc->cmap.blue, &b[index], count); 2783 if (err) 2784 return err; 2785 2786 for (i = index; i < index + count; i++) { 2787 nc.rc_cmap[i] = 2788 (r[i] << 16) + (g[i] << 8) + (b[i] << 0); 2789 } 2790 } 2791 2792 if (flags & WSDISPLAY_CURSOR_DOSHAPE) { 2793 if ((wc->size.x > RADEON_CURSORMAXX) || 2794 (wc->size.y > RADEON_CURSORMAXY)) 2795 return EINVAL; 2796 2797 /* figure bytes per line */ 2798 pitch = (wc->size.x + 7) / 8; 2799 size = pitch * wc->size.y; 2800 2801 /* clear the old cursor and mask */ 2802 memset(nc.rc_image, 0, 512); 2803 memset(nc.rc_mask, 0, 512); 2804 2805 nc.rc_size = wc->size; 2806 2807 if ((err = copyin(wc->image, nc.rc_image, size)) != 0) 2808 return err; 2809 2810 if ((err = copyin(wc->mask, nc.rc_mask, size)) != 0) 2811 return err; 2812 } 2813 2814 if (flags & WSDISPLAY_CURSOR_DOHOT) { 2815 nc.rc_hot = wc->hot; 2816 if (nc.rc_hot.x >= nc.rc_size.x) 2817 nc.rc_hot.x = nc.rc_size.x - 1; 2818 if (nc.rc_hot.y >= nc.rc_size.y) 2819 nc.rc_hot.y = nc.rc_size.y - 1; 2820 } 2821 2822 if (flags & WSDISPLAY_CURSOR_DOPOS) { 2823 nc.rc_pos = wc->pos; 2824 if (nc.rc_pos.x >= dp->rd_virtx) 2825 nc.rc_pos.x = dp->rd_virtx - 1; 2826 if (nc.rc_pos.x < 0) 2827 nc.rc_pos.x = 0; 2828 if (nc.rc_pos.y >= dp->rd_virty) 2829 nc.rc_pos.y = dp->rd_virty - 1; 2830 if (nc.rc_pos.y < 0) 2831 nc.rc_pos.y = 0; 2832 } 2833 if (flags & WSDISPLAY_CURSOR_DOCUR) { 2834 nc.rc_visible = wc->enable; 2835 } 2836 2837 dp->rd_cursor = nc; 2838 radeonfb_cursor_update(dp, wc->which); 2839 2840 return 0; 2841 } 2842 2843 /* 2844 * Change the cursor shape. Call this with the cursor locked to avoid 2845 * flickering/tearing. 2846 */ 2847 static void 2848 radeonfb_cursor_shape(struct radeonfb_display *dp) 2849 { 2850 uint8_t and[512], xor[512]; 2851 int i, j, src, dst, pitch; 2852 const uint8_t *msk = dp->rd_cursor.rc_mask; 2853 const uint8_t *img = dp->rd_cursor.rc_image; 2854 2855 /* 2856 * Radeon cursor data interleaves one line of AND data followed 2857 * by a line of XOR data. (Each line corresponds to a whole hardware 2858 * pitch - i.e. 64 pixels or 8 bytes.) 2859 * 2860 * The cursor is displayed using the following table: 2861 * 2862 * AND XOR Result 2863 * ---------------------- 2864 * 0 0 Cursor color 0 2865 * 0 1 Cursor color 1 2866 * 1 0 Transparent 2867 * 1 1 Complement of background 2868 * 2869 * Our masks are therefore different from what we were passed. 2870 * Passed in, I'm assuming the data represents either color 0 or 1, 2871 * and a mask, so the passed in table looks like: 2872 * 2873 * IMG Mask Result 2874 * ----------------------- 2875 * 0 0 Transparent 2876 * 0 1 Cursor color 0 2877 * 1 0 Transparent 2878 * 1 1 Cursor color 1 2879 * 2880 * IF mask bit == 1, AND = 0, XOR = color. 2881 * IF mask bit == 0, AND = 1, XOR = 0. 2882 * 2883 * hence: AND = ~(mask); XOR = color & ~(mask); 2884 */ 2885 2886 pitch = ((dp->rd_cursor.rc_size.x + 7) / 8); 2887 2888 /* start by assuming all bits are transparent */ 2889 memset(and, 0xff, 512); 2890 memset(xor, 0x00, 512); 2891 2892 src = 0; 2893 dst = 0; 2894 for (i = 0; i < 64; i++) { 2895 for (j = 0; j < 64; j += 8) { 2896 if ((i < dp->rd_cursor.rc_size.y) && 2897 (j < dp->rd_cursor.rc_size.x)) { 2898 2899 /* take care to leave odd bits alone */ 2900 and[dst] &= ~(msk[src]); 2901 xor[dst] = img[src] & msk[src]; 2902 src++; 2903 } 2904 dst++; 2905 } 2906 } 2907 2908 /* copy the image into place */ 2909 for (i = 0; i < 64; i++) { 2910 memcpy((uint8_t *)dp->rd_curptr + (i * 16), 2911 &and[i * 8], 8); 2912 memcpy((uint8_t *)dp->rd_curptr + (i * 16) + 8, 2913 &xor[i * 8], 8); 2914 } 2915 } 2916 2917 static void 2918 radeonfb_cursor_position(struct radeonfb_display *dp) 2919 { 2920 struct radeonfb_softc *sc = dp->rd_softc; 2921 uint32_t offset, hvoff, hvpos; /* registers */ 2922 uint32_t coff; /* cursor offset */ 2923 int i, x, y, xoff, yoff, crtcoff; 2924 2925 /* 2926 * XXX: this also needs to handle pan/scan 2927 */ 2928 for (i = 0; i < dp->rd_ncrtcs; i++) { 2929 2930 struct radeonfb_crtc *rcp = &dp->rd_crtcs[i]; 2931 2932 if (rcp->rc_number) { 2933 offset = RADEON_CUR2_OFFSET; 2934 hvoff = RADEON_CUR2_HORZ_VERT_OFF; 2935 hvpos = RADEON_CUR2_HORZ_VERT_POSN; 2936 crtcoff = RADEON_CRTC2_OFFSET; 2937 } else { 2938 offset = RADEON_CUR_OFFSET; 2939 hvoff = RADEON_CUR_HORZ_VERT_OFF; 2940 hvpos = RADEON_CUR_HORZ_VERT_POSN; 2941 crtcoff = RADEON_CRTC_OFFSET; 2942 } 2943 2944 x = dp->rd_cursor.rc_pos.x; 2945 y = dp->rd_cursor.rc_pos.y; 2946 2947 while (y < rcp->rc_yoffset) { 2948 rcp->rc_yoffset -= RADEON_PANINCREMENT; 2949 } 2950 while (y >= (rcp->rc_yoffset + rcp->rc_videomode.vdisplay)) { 2951 rcp->rc_yoffset += RADEON_PANINCREMENT; 2952 } 2953 while (x < rcp->rc_xoffset) { 2954 rcp->rc_xoffset -= RADEON_PANINCREMENT; 2955 } 2956 while (x >= (rcp->rc_xoffset + rcp->rc_videomode.hdisplay)) { 2957 rcp->rc_xoffset += RADEON_PANINCREMENT; 2958 } 2959 2960 /* adjust for the cursor's hotspot */ 2961 x -= dp->rd_cursor.rc_hot.x; 2962 y -= dp->rd_cursor.rc_hot.y; 2963 xoff = yoff = 0; 2964 2965 if (x >= dp->rd_virtx) 2966 x = dp->rd_virtx - 1; 2967 if (y >= dp->rd_virty) 2968 y = dp->rd_virty - 1; 2969 2970 /* now adjust cursor so it is relative to viewport */ 2971 x -= rcp->rc_xoffset; 2972 y -= rcp->rc_yoffset; 2973 2974 /* 2975 * no need to check for fall off, because we should 2976 * never move off the screen entirely! 2977 */ 2978 coff = 0; 2979 if (x < 0) { 2980 xoff = -x; 2981 x = 0; 2982 } 2983 if (y < 0) { 2984 yoff = -y; 2985 y = 0; 2986 coff = (yoff * 2) * 8; 2987 } 2988 2989 /* pan the display */ 2990 PUT32(sc, crtcoff, (rcp->rc_yoffset * dp->rd_stride) + 2991 rcp->rc_xoffset); 2992 2993 PUT32(sc, offset, (dp->rd_curoff + coff) | RADEON_CUR_LOCK); 2994 PUT32(sc, hvoff, (xoff << 16) | (yoff) | RADEON_CUR_LOCK); 2995 /* NB: this unlocks the cursor */ 2996 PUT32(sc, hvpos, (x << 16) | y); 2997 } 2998 } 2999 3000 static void 3001 radeonfb_cursor_visible(struct radeonfb_display *dp) 3002 { 3003 int i; 3004 uint32_t gencntl, bit; 3005 3006 for (i = 0; i < dp->rd_ncrtcs; i++) { 3007 if (dp->rd_crtcs[i].rc_number) { 3008 gencntl = RADEON_CRTC2_GEN_CNTL; 3009 bit = RADEON_CRTC2_CUR_EN; 3010 } else { 3011 gencntl = RADEON_CRTC_GEN_CNTL; 3012 bit = RADEON_CRTC_CUR_EN; 3013 } 3014 3015 if (dp->rd_cursor.rc_visible) 3016 SET32(dp->rd_softc, gencntl, bit); 3017 else 3018 CLR32(dp->rd_softc, gencntl, bit); 3019 } 3020 } 3021 3022 static void 3023 radeonfb_cursor_cmap(struct radeonfb_display *dp) 3024 { 3025 int i; 3026 uint32_t c0reg, c1reg; 3027 struct radeonfb_softc *sc = dp->rd_softc; 3028 3029 for (i = 0; i < dp->rd_ncrtcs; i++) { 3030 if (dp->rd_crtcs[i].rc_number) { 3031 c0reg = RADEON_CUR2_CLR0; 3032 c1reg = RADEON_CUR2_CLR1; 3033 } else { 3034 c0reg = RADEON_CUR_CLR0; 3035 c1reg = RADEON_CUR_CLR1; 3036 } 3037 3038 PUT32(sc, c0reg, dp->rd_cursor.rc_cmap[0]); 3039 PUT32(sc, c1reg, dp->rd_cursor.rc_cmap[1]); 3040 } 3041 } 3042 3043 static void 3044 radeonfb_cursor_update(struct radeonfb_display *dp, unsigned which) 3045 { 3046 struct radeonfb_softc *sc; 3047 int i; 3048 3049 sc = dp->rd_softc; 3050 for (i = 0; i < dp->rd_ncrtcs; i++) { 3051 if (dp->rd_crtcs[i].rc_number) { 3052 SET32(sc, RADEON_CUR2_OFFSET, RADEON_CUR_LOCK); 3053 } else { 3054 SET32(sc, RADEON_CUR_OFFSET,RADEON_CUR_LOCK); 3055 } 3056 } 3057 3058 if (which & WSDISPLAY_CURSOR_DOCMAP) 3059 radeonfb_cursor_cmap(dp); 3060 3061 if (which & WSDISPLAY_CURSOR_DOSHAPE) 3062 radeonfb_cursor_shape(dp); 3063 3064 if (which & WSDISPLAY_CURSOR_DOCUR) 3065 radeonfb_cursor_visible(dp); 3066 3067 /* this one is unconditional, because it updates other stuff */ 3068 radeonfb_cursor_position(dp); 3069 } 3070 3071 static struct videomode * 3072 radeonfb_best_refresh(struct videomode *m1, struct videomode *m2) 3073 { 3074 int r1, r2; 3075 3076 /* otherwise pick the higher refresh rate */ 3077 r1 = DIVIDE(DIVIDE(m1->dot_clock, m1->htotal), m1->vtotal); 3078 r2 = DIVIDE(DIVIDE(m2->dot_clock, m2->htotal), m2->vtotal); 3079 3080 return (r1 < r2 ? m2 : m1); 3081 } 3082 3083 static const struct videomode * 3084 radeonfb_port_mode(struct radeonfb_port *rp, int x, int y) 3085 { 3086 struct edid_info *ep = &rp->rp_edid; 3087 struct videomode *vmp = NULL; 3088 int i; 3089 3090 if (!rp->rp_edid_valid) { 3091 /* fallback to safe mode */ 3092 return radeonfb_modelookup(RADEON_DEFAULT_MODE); 3093 } 3094 3095 /* always choose the preferred mode first! */ 3096 if (ep->edid_preferred_mode) { 3097 3098 /* XXX: add auto-stretching support for native mode */ 3099 3100 /* this may want panning to occur, btw */ 3101 if ((ep->edid_preferred_mode->hdisplay <= x) && 3102 (ep->edid_preferred_mode->vdisplay <= y)) 3103 return ep->edid_preferred_mode; 3104 } 3105 3106 for (i = 0; i < ep->edid_nmodes; i++) { 3107 /* 3108 * We elect to pick a resolution that is too large for 3109 * the monitor than one that is too small. This means 3110 * that we will prefer to pan rather than to try to 3111 * center a smaller display on a larger screen. In 3112 * practice, this shouldn't matter because if a 3113 * monitor can support a larger resolution, it can 3114 * probably also support the smaller. A specific 3115 * exception is fixed format panels, but hopefully 3116 * they are properly dealt with by the "autostretch" 3117 * logic above. 3118 */ 3119 if ((ep->edid_modes[i].hdisplay > x) || 3120 (ep->edid_modes[i].vdisplay > y)) { 3121 continue; 3122 } 3123 3124 /* 3125 * at this point, the display mode is no larger than 3126 * what we've requested. 3127 */ 3128 if (vmp == NULL) 3129 vmp = &ep->edid_modes[i]; 3130 3131 /* eliminate smaller modes */ 3132 if ((vmp->hdisplay >= ep->edid_modes[i].hdisplay) || 3133 (vmp->vdisplay >= ep->edid_modes[i].vdisplay)) 3134 continue; 3135 3136 if ((vmp->hdisplay < ep->edid_modes[i].hdisplay) || 3137 (vmp->vdisplay < ep->edid_modes[i].vdisplay)) { 3138 vmp = &ep->edid_modes[i]; 3139 continue; 3140 } 3141 3142 KASSERT(vmp->hdisplay == ep->edid_modes[i].hdisplay); 3143 KASSERT(vmp->vdisplay == ep->edid_modes[i].vdisplay); 3144 3145 vmp = radeonfb_best_refresh(vmp, &ep->edid_modes[i]); 3146 } 3147 3148 return (vmp ? vmp : radeonfb_modelookup(RADEON_DEFAULT_MODE)); 3149 } 3150 3151 static int 3152 radeonfb_hasres(struct videomode *list, int nlist, int x, int y) 3153 { 3154 int i; 3155 3156 for (i = 0; i < nlist; i++) { 3157 if ((x == list[i].hdisplay) && 3158 (y == list[i].vdisplay)) { 3159 return 1; 3160 } 3161 } 3162 return 0; 3163 } 3164 3165 static void 3166 radeonfb_pickres(struct radeonfb_display *dp, uint16_t *x, uint16_t *y, 3167 int pan) 3168 { 3169 struct radeonfb_port *rp; 3170 struct edid_info *ep; 3171 int i, j; 3172 3173 *x = 0; 3174 *y = 0; 3175 3176 if (pan) { 3177 for (i = 0; i < dp->rd_ncrtcs; i++) { 3178 rp = dp->rd_crtcs[i].rc_port; 3179 ep = &rp->rp_edid; 3180 if (!rp->rp_edid_valid) { 3181 /* monitor not present */ 3182 continue; 3183 } 3184 3185 /* 3186 * For now we are ignoring "conflict" that 3187 * could occur when mixing some modes like 3188 * 1280x1024 and 1400x800. It isn't clear 3189 * which is better, so the first one wins. 3190 */ 3191 for (j = 0; j < ep->edid_nmodes; j++) { 3192 /* 3193 * ignore resolutions that are too big for 3194 * the radeon 3195 */ 3196 if (ep->edid_modes[j].hdisplay > 3197 dp->rd_softc->sc_maxx) 3198 continue; 3199 if (ep->edid_modes[j].vdisplay > 3200 dp->rd_softc->sc_maxy) 3201 continue; 3202 3203 /* 3204 * pick largest resolution, the 3205 * smaller monitor will pan 3206 */ 3207 if ((ep->edid_modes[j].hdisplay >= *x) && 3208 (ep->edid_modes[j].vdisplay >= *y)) { 3209 *x = ep->edid_modes[j].hdisplay; 3210 *y = ep->edid_modes[j].vdisplay; 3211 } 3212 } 3213 } 3214 3215 } else { 3216 struct videomode modes[64]; 3217 int nmodes = 0; 3218 int valid = 0; 3219 3220 for (i = 0; i < dp->rd_ncrtcs; i++) { 3221 /* 3222 * pick the largest resolution in common. 3223 */ 3224 rp = dp->rd_crtcs[i].rc_port; 3225 ep = &rp->rp_edid; 3226 3227 if (!rp->rp_edid_valid) 3228 continue; 3229 3230 if (!valid) { 3231 /* initialize starting list */ 3232 for (j = 0; j < ep->edid_nmodes; j++) { 3233 /* 3234 * ignore resolutions that are 3235 * too big for the radeon 3236 */ 3237 if (ep->edid_modes[j].hdisplay > 3238 dp->rd_softc->sc_maxx) 3239 continue; 3240 if (ep->edid_modes[j].vdisplay > 3241 dp->rd_softc->sc_maxy) 3242 continue; 3243 3244 modes[nmodes] = ep->edid_modes[j]; 3245 nmodes++; 3246 } 3247 valid = 1; 3248 } else { 3249 /* merge into preexisting list */ 3250 for (j = 0; j < nmodes; j++) { 3251 if (!radeonfb_hasres(ep->edid_modes, 3252 ep->edid_nmodes, 3253 modes[j].hdisplay, 3254 modes[j].vdisplay)) { 3255 modes[j] = modes[nmodes]; 3256 j--; 3257 nmodes--; 3258 } 3259 } 3260 } 3261 } 3262 3263 /* now we have to pick from the merged list */ 3264 for (i = 0; i < nmodes; i++) { 3265 if ((modes[i].hdisplay >= *x) && 3266 (modes[i].vdisplay >= *y)) { 3267 *x = modes[i].hdisplay; 3268 *y = modes[i].vdisplay; 3269 } 3270 } 3271 } 3272 3273 if ((*x == 0) || (*y == 0)) { 3274 /* fallback to safe mode */ 3275 *x = 640; 3276 *y = 480; 3277 } 3278 } 3279
Indexes created Mon Sep 22 13:09:51 GMT 2025