radeonfb.c revision 1.60
1 /* $NetBSD: radeonfb.c,v 1.60 2012/03/26 21:59:01 macallan Exp $ */ 2 3 /*- 4 * Copyright (c) 2006 Itronix Inc. 5 * All rights reserved. 6 * 7 * Written by Garrett D'Amore for Itronix Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. The name of Itronix Inc. may not be used to endorse 18 * or promote products derived from this software without specific 19 * prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY ITRONIX INC. ``AS IS'' AND ANY EXPRESS 22 * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 23 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL ITRONIX INC. BE LIABLE FOR ANY 25 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE 27 * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 29 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 30 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 31 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * ATI Technologies Inc. ("ATI") has not assisted in the creation of, and 36 * does not endorse, this software. ATI will not be responsible or liable 37 * for any actual or alleged damage or loss caused by or in connection with 38 * the use of or reliance on this software. 39 */ 40 41 /* 42 * Portions of this code were taken from XFree86's Radeon driver, which bears 43 * this notice: 44 * 45 * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and 46 * VA Linux Systems Inc., Fremont, California. 47 * 48 * All Rights Reserved. 49 * 50 * Permission is hereby granted, free of charge, to any person obtaining 51 * a copy of this software and associated documentation files (the 52 * "Software"), to deal in the Software without restriction, including 53 * without limitation on the rights to use, copy, modify, merge, 54 * publish, distribute, sublicense, and/or sell copies of the Software, 55 * and to permit persons to whom the Software is furnished to do so, 56 * subject to the following conditions: 57 * 58 * The above copyright notice and this permission notice (including the 59 * next paragraph) shall be included in all copies or substantial 60 * portions of the Software. 61 * 62 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 63 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 64 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 65 * NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR 66 * THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 67 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 68 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 69 * DEALINGS IN THE SOFTWARE. 70 */ 71 72 #include <sys/cdefs.h> 73 __KERNEL_RCSID(0, "$NetBSD: radeonfb.c,v 1.60 2012/03/26 21:59:01 macallan Exp $"); 74 75 #include <sys/param.h> 76 #include <sys/systm.h> 77 #include <sys/device.h> 78 #include <sys/malloc.h> 79 #include <sys/bus.h> 80 #include <sys/kernel.h> 81 #include <sys/lwp.h> 82 #include <sys/kauth.h> 83 84 #include <dev/wscons/wsdisplayvar.h> 85 #include <dev/wscons/wsconsio.h> 86 #include <dev/wsfont/wsfont.h> 87 #include <dev/rasops/rasops.h> 88 #include <dev/videomode/videomode.h> 89 #include <dev/videomode/edidvar.h> 90 #include <dev/wscons/wsdisplay_vconsvar.h> 91 #include <dev/pci/wsdisplay_pci.h> 92 #include <dev/wscons/wsdisplay_glyphcachevar.h> 93 94 #include <dev/pci/pcidevs.h> 95 #include <dev/pci/pcireg.h> 96 #include <dev/pci/pcivar.h> 97 #include <dev/pci/pciio.h> 98 #include <dev/pci/radeonfbreg.h> 99 #include <dev/pci/radeonfbvar.h> 100 #include "opt_radeonfb.h" 101 #include "opt_vcons.h" 102 103 #ifdef RADEONFB_DEPTH_32 104 #define RADEONFB_DEFAULT_DEPTH 32 105 #else 106 #define RADEONFB_DEFAULT_DEPTH 8 107 #endif 108 109 static int radeonfb_match(device_t, cfdata_t, void *); 110 static void radeonfb_attach(device_t, device_t, void *); 111 static int radeonfb_ioctl(void *, void *, unsigned long, void *, int, 112 struct lwp *); 113 static paddr_t radeonfb_mmap(void *, void *, off_t, int); 114 static int radeonfb_scratch_test(struct radeonfb_softc *, int, uint32_t); 115 static void radeonfb_loadbios(struct radeonfb_softc *, 116 const struct pci_attach_args *); 117 118 static uintmax_t radeonfb_getprop_num(struct radeonfb_softc *, const char *, 119 uintmax_t); 120 static int radeonfb_getclocks(struct radeonfb_softc *); 121 static int radeonfb_gettmds(struct radeonfb_softc *); 122 static int radeonfb_calc_dividers(struct radeonfb_softc *, uint32_t, 123 uint32_t *, uint32_t *); 124 static int radeonfb_getconnectors(struct radeonfb_softc *); 125 static const struct videomode *radeonfb_modelookup(const char *); 126 static void radeonfb_init_screen(void *, struct vcons_screen *, int, long *); 127 static void radeonfb_pllwriteupdate(struct radeonfb_softc *, int); 128 static void radeonfb_pllwaitatomicread(struct radeonfb_softc *, int); 129 static void radeonfb_program_vclk(struct radeonfb_softc *, int, int); 130 static void radeonfb_modeswitch(struct radeonfb_display *); 131 static void radeonfb_setcrtc(struct radeonfb_display *, int); 132 static void radeonfb_init_misc(struct radeonfb_softc *); 133 static void radeonfb_set_fbloc(struct radeonfb_softc *); 134 static void radeonfb_init_palette(struct radeonfb_softc *, int); 135 static void radeonfb_r300cg_workaround(struct radeonfb_softc *); 136 137 static int radeonfb_isblank(struct radeonfb_display *); 138 static void radeonfb_blank(struct radeonfb_display *, int); 139 static int radeonfb_set_cursor(struct radeonfb_display *, 140 struct wsdisplay_cursor *); 141 static int radeonfb_set_curpos(struct radeonfb_display *, 142 struct wsdisplay_curpos *); 143 144 /* acceleration support */ 145 static void radeonfb_rectfill(struct radeonfb_display *, int dstx, int dsty, 146 int width, int height, uint32_t color); 147 static void radeonfb_bitblt(void *, int srcx, int srcy, 148 int dstx, int dsty, int width, int height, int rop); 149 150 /* hw cursor support */ 151 static void radeonfb_cursor_cmap(struct radeonfb_display *); 152 static void radeonfb_cursor_shape(struct radeonfb_display *); 153 static void radeonfb_cursor_position(struct radeonfb_display *); 154 static void radeonfb_cursor_visible(struct radeonfb_display *); 155 static void radeonfb_cursor_update(struct radeonfb_display *, unsigned); 156 157 static void radeonfb_wait_fifo(struct radeonfb_softc *, int); 158 static void radeonfb_engine_idle(struct radeonfb_softc *); 159 static void radeonfb_engine_flush(struct radeonfb_softc *); 160 static void radeonfb_engine_reset(struct radeonfb_softc *); 161 static void radeonfb_engine_init(struct radeonfb_display *); 162 static inline void radeonfb_unclip(struct radeonfb_softc *); 163 164 static void radeonfb_eraserows(void *, int, int, long); 165 static void radeonfb_erasecols(void *, int, int, int, long); 166 static void radeonfb_copyrows(void *, int, int, int); 167 static void radeonfb_copycols(void *, int, int, int, int); 168 static void radeonfb_cursor(void *, int, int, int); 169 static void radeonfb_putchar(void *, int, int, unsigned, long); 170 static void radeonfb_putchar_aa32(void *, int, int, unsigned, long); 171 static void radeonfb_putchar_aa8(void *, int, int, unsigned, long); 172 static void radeonfb_putchar_wrapper(void *, int, int, unsigned, long); 173 174 static int radeonfb_set_backlight(struct radeonfb_display *, int); 175 static int radeonfb_get_backlight(struct radeonfb_display *); 176 static void radeonfb_switch_backlight(struct radeonfb_display *, int); 177 static void radeonfb_lvds_callout(void *); 178 179 static void radeonfb_brightness_up(device_t); 180 static void radeonfb_brightness_down(device_t); 181 182 static struct videomode *radeonfb_best_refresh(struct videomode *, 183 struct videomode *); 184 static void radeonfb_pickres(struct radeonfb_display *, uint16_t *, 185 uint16_t *, int); 186 static const struct videomode *radeonfb_port_mode(struct radeonfb_softc *, 187 struct radeonfb_port *, int, int); 188 189 static int radeonfb_drm_print(void *, const char *); 190 191 #ifdef RADEONFB_DEBUG 192 int radeon_debug = 1; 193 #define DPRINTF(x) \ 194 if (radeon_debug) printf x 195 #define PRINTREG(r) DPRINTF((#r " = %08x\n", GET32(sc, r))) 196 #define PRINTPLL(r) DPRINTF((#r " = %08x\n", GETPLL(sc, r))) 197 #else 198 #define DPRINTF(x) 199 #define PRINTREG(r) 200 #define PRINTPLL(r) 201 #endif 202 203 #define ROUNDUP(x,y) (((x) + ((y) - 1)) & ~((y) - 1)) 204 205 #ifndef RADEON_DEFAULT_MODE 206 /* any reasonably modern display should handle this */ 207 #define RADEON_DEFAULT_MODE "1024x768x60" 208 #endif 209 210 extern const u_char rasops_cmap[768]; 211 212 const char *radeonfb_default_mode = RADEON_DEFAULT_MODE; 213 214 static struct { 215 int size; /* minimum memory size (MB) */ 216 int maxx; /* maximum x dimension */ 217 int maxy; /* maximum y dimension */ 218 int maxbpp; /* maximum bpp */ 219 int maxdisp; /* maximum logical display count */ 220 } radeonfb_limits[] = { 221 { 32, 2048, 1536, 32, 2 }, 222 { 16, 1600, 1200, 32, 2 }, 223 { 8, 1600, 1200, 32, 1 }, 224 { 0, 0, 0, 0, 0 }, 225 }; 226 227 static struct wsscreen_descr radeonfb_stdscreen = { 228 "fb", /* name */ 229 0, 0, /* ncols, nrows */ 230 NULL, /* textops */ 231 8, 16, /* fontwidth, fontheight */ 232 WSSCREEN_WSCOLORS, /* capabilities */ 233 0, /* modecookie */ 234 }; 235 236 struct wsdisplay_accessops radeonfb_accessops = { 237 radeonfb_ioctl, 238 radeonfb_mmap, 239 NULL, /* vcons_alloc_screen */ 240 NULL, /* vcons_free_screen */ 241 NULL, /* vcons_show_screen */ 242 NULL, /* load_font */ 243 NULL, /* pollc */ 244 NULL, /* scroll */ 245 }; 246 247 static struct { 248 uint16_t devid; 249 uint16_t family; 250 uint16_t flags; 251 } radeonfb_devices[] = 252 { 253 /* R100 family */ 254 { PCI_PRODUCT_ATI_RADEON_R100_QD, RADEON_R100, 0 }, 255 { PCI_PRODUCT_ATI_RADEON_R100_QE, RADEON_R100, 0 }, 256 { PCI_PRODUCT_ATI_RADEON_R100_QF, RADEON_R100, 0 }, 257 { PCI_PRODUCT_ATI_RADEON_R100_QG, RADEON_R100, 0 }, 258 259 /* RV100 family */ 260 { PCI_PRODUCT_ATI_RADEON_RV100_LY, RADEON_RV100, RFB_MOB }, 261 { PCI_PRODUCT_ATI_RADEON_RV100_LZ, RADEON_RV100, RFB_MOB }, 262 { PCI_PRODUCT_ATI_RADEON_RV100_QY, RADEON_RV100, 0 }, 263 { PCI_PRODUCT_ATI_RADEON_RV100_QZ, RADEON_RV100, 0 }, 264 265 /* RS100 family */ 266 { PCI_PRODUCT_ATI_RADEON_RS100_4136, RADEON_RS100, 0 }, 267 { PCI_PRODUCT_ATI_RADEON_RS100_4336, RADEON_RS100, RFB_MOB }, 268 269 /* RS200/RS250 family */ 270 { PCI_PRODUCT_ATI_RADEON_RS200_4337, RADEON_RS200, RFB_MOB }, 271 { PCI_PRODUCT_ATI_RADEON_RS200_A7, RADEON_RS200, 0 }, 272 { PCI_PRODUCT_ATI_RADEON_RS250_B7, RADEON_RS200, RFB_MOB }, 273 { PCI_PRODUCT_ATI_RADEON_RS250_D7, RADEON_RS200, 0 }, 274 275 /* R200 family */ 276 /* add more R200 products? , 5148 */ 277 { PCI_PRODUCT_ATI_RADEON_R200_BB, RADEON_R200, 0 }, 278 { PCI_PRODUCT_ATI_RADEON_R200_BC, RADEON_R200, 0 }, 279 { PCI_PRODUCT_ATI_RADEON_R200_QH, RADEON_R200, 0 }, 280 { PCI_PRODUCT_ATI_RADEON_R200_QL, RADEON_R200, 0 }, 281 { PCI_PRODUCT_ATI_RADEON_R200_QM, RADEON_R200, 0 }, 282 283 /* RV200 family */ 284 { PCI_PRODUCT_ATI_RADEON_RV200_LW, RADEON_RV200, RFB_MOB }, 285 { PCI_PRODUCT_ATI_RADEON_RV200_LX, RADEON_RV200, RFB_MOB }, 286 { PCI_PRODUCT_ATI_RADEON_RV200_QW, RADEON_RV200, 0 }, 287 { PCI_PRODUCT_ATI_RADEON_RV200_QX, RADEON_RV200, 0 }, 288 289 /* RV250 family */ 290 { PCI_PRODUCT_ATI_RADEON_RV250_4966, RADEON_RV250, 0 }, 291 { PCI_PRODUCT_ATI_RADEON_RV250_4967, RADEON_RV250, 0 }, 292 { PCI_PRODUCT_ATI_RADEON_RV250_4C64, RADEON_RV250, RFB_MOB }, 293 { PCI_PRODUCT_ATI_RADEON_RV250_4C66, RADEON_RV250, RFB_MOB }, 294 { PCI_PRODUCT_ATI_RADEON_RV250_4C67, RADEON_RV250, RFB_MOB }, 295 296 /* RS300 family */ 297 { PCI_PRODUCT_ATI_RADEON_RS300_X5, RADEON_RS300, 0 }, 298 { PCI_PRODUCT_ATI_RADEON_RS300_X4, RADEON_RS300, 0 }, 299 { PCI_PRODUCT_ATI_RADEON_RS300_7834, RADEON_RS300, 0 }, 300 { PCI_PRODUCT_ATI_RADEON_RS300_7835, RADEON_RS300, RFB_MOB }, 301 302 /* RV280 family */ 303 { PCI_PRODUCT_ATI_RADEON_RV280_5960, RADEON_RV280, 0 }, 304 { PCI_PRODUCT_ATI_RADEON_RV280_5961, RADEON_RV280, 0 }, 305 { PCI_PRODUCT_ATI_RADEON_RV280_5962, RADEON_RV280, 0 }, 306 { PCI_PRODUCT_ATI_RADEON_RV280_5963, RADEON_RV280, 0 }, 307 { PCI_PRODUCT_ATI_RADEON_RV280_5964, RADEON_RV280, 0 }, 308 { PCI_PRODUCT_ATI_RADEON_RV280_5C61, RADEON_RV280, RFB_MOB }, 309 { PCI_PRODUCT_ATI_RADEON_RV280_5C63, RADEON_RV280, RFB_MOB }, 310 311 /* R300 family */ 312 { PCI_PRODUCT_ATI_RADEON_R300_AD, RADEON_R300, 0 }, 313 { PCI_PRODUCT_ATI_RADEON_R300_AE, RADEON_R300, 0 }, 314 { PCI_PRODUCT_ATI_RADEON_R300_AF, RADEON_R300, 0 }, 315 { PCI_PRODUCT_ATI_RADEON_R300_AG, RADEON_R300, 0 }, 316 { PCI_PRODUCT_ATI_RADEON_R300_ND, RADEON_R300, 0 }, 317 { PCI_PRODUCT_ATI_RADEON_R300_NE, RADEON_R300, 0 }, 318 { PCI_PRODUCT_ATI_RADEON_R300_NF, RADEON_R300, 0 }, 319 { PCI_PRODUCT_ATI_RADEON_R300_NG, RADEON_R300, 0 }, 320 321 /* RV350/RV360 family */ 322 { PCI_PRODUCT_ATI_RADEON_RV350_AP, RADEON_RV350, 0 }, 323 { PCI_PRODUCT_ATI_RADEON_RV350_AQ, RADEON_RV350, 0 }, 324 { PCI_PRODUCT_ATI_RADEON_RV360_AR, RADEON_RV350, 0 }, 325 { PCI_PRODUCT_ATI_RADEON_RV350_AS, RADEON_RV350, 0 }, 326 { PCI_PRODUCT_ATI_RADEON_RV350_AT, RADEON_RV350, 0 }, 327 { PCI_PRODUCT_ATI_RADEON_RV350_AV, RADEON_RV350, 0 }, 328 { PCI_PRODUCT_ATI_RADEON_RV350_NP, RADEON_RV350, RFB_MOB }, 329 { PCI_PRODUCT_ATI_RADEON_RV350_NQ, RADEON_RV350, RFB_MOB }, 330 { PCI_PRODUCT_ATI_RADEON_RV350_NR, RADEON_RV350, RFB_MOB }, 331 { PCI_PRODUCT_ATI_RADEON_RV350_NS, RADEON_RV350, RFB_MOB }, 332 { PCI_PRODUCT_ATI_RADEON_RV350_NT, RADEON_RV350, RFB_MOB }, 333 { PCI_PRODUCT_ATI_RADEON_RV350_NV, RADEON_RV350, RFB_MOB }, 334 335 /* R350/R360 family */ 336 { PCI_PRODUCT_ATI_RADEON_R350_AH, RADEON_R350, 0 }, 337 { PCI_PRODUCT_ATI_RADEON_R350_AI, RADEON_R350, 0 }, 338 { PCI_PRODUCT_ATI_RADEON_R350_AJ, RADEON_R350, 0 }, 339 { PCI_PRODUCT_ATI_RADEON_R350_AK, RADEON_R350, 0 }, 340 { PCI_PRODUCT_ATI_RADEON_R350_NH, RADEON_R350, 0 }, 341 { PCI_PRODUCT_ATI_RADEON_R350_NI, RADEON_R350, 0 }, 342 { PCI_PRODUCT_ATI_RADEON_R350_NK, RADEON_R350, 0 }, 343 { PCI_PRODUCT_ATI_RADEON_R360_NJ, RADEON_R350, 0 }, 344 345 /* RV380/RV370 family */ 346 { PCI_PRODUCT_ATI_RADEON_RV380_3150, RADEON_RV380, RFB_MOB }, 347 { PCI_PRODUCT_ATI_RADEON_RV380_3154, RADEON_RV380, RFB_MOB }, 348 { PCI_PRODUCT_ATI_RADEON_RV380_3E50, RADEON_RV380, 0 }, 349 { PCI_PRODUCT_ATI_RADEON_RV380_3E54, RADEON_RV380, 0 }, 350 { PCI_PRODUCT_ATI_RADEON_RV370_5460, RADEON_RV380, RFB_MOB }, 351 { PCI_PRODUCT_ATI_RADEON_RV370_5464, RADEON_RV380, RFB_MOB }, 352 { PCI_PRODUCT_ATI_RADEON_RV370_5B60, RADEON_RV380, 0 }, 353 { PCI_PRODUCT_ATI_RADEON_RV370_5B64, RADEON_RV380, 0 }, 354 { PCI_PRODUCT_ATI_RADEON_RV370_5B65, RADEON_RV380, 0 }, 355 356 /* R420/R423 family */ 357 { PCI_PRODUCT_ATI_RADEON_R420_JH, RADEON_R420, 0 }, 358 { PCI_PRODUCT_ATI_RADEON_R420_JI, RADEON_R420, 0 }, 359 { PCI_PRODUCT_ATI_RADEON_R420_JJ, RADEON_R420, 0 }, 360 { PCI_PRODUCT_ATI_RADEON_R420_JK, RADEON_R420, 0 }, 361 { PCI_PRODUCT_ATI_RADEON_R420_JL, RADEON_R420, 0 }, 362 { PCI_PRODUCT_ATI_RADEON_R420_JM, RADEON_R420, 0 }, 363 { PCI_PRODUCT_ATI_RADEON_R420_JN, RADEON_R420, RFB_MOB }, 364 { PCI_PRODUCT_ATI_RADEON_R420_JP, RADEON_R420, 0 }, 365 { PCI_PRODUCT_ATI_RADEON_R423_UH, RADEON_R420, 0 }, 366 { PCI_PRODUCT_ATI_RADEON_R423_UI, RADEON_R420, 0 }, 367 { PCI_PRODUCT_ATI_RADEON_R423_UJ, RADEON_R420, 0 }, 368 { PCI_PRODUCT_ATI_RADEON_R423_UK, RADEON_R420, 0 }, 369 { PCI_PRODUCT_ATI_RADEON_R423_UQ, RADEON_R420, 0 }, 370 { PCI_PRODUCT_ATI_RADEON_R423_UR, RADEON_R420, 0 }, 371 { PCI_PRODUCT_ATI_RADEON_R423_UT, RADEON_R420, 0 }, 372 { PCI_PRODUCT_ATI_RADEON_R423_5D57, RADEON_R420, 0 }, 373 { PCI_PRODUCT_ATI_RADEON_R430_554F, RADEON_R420, 0 }, 374 375 { 0, 0, 0 } 376 }; 377 378 static struct { 379 int divider; 380 int mask; 381 } radeonfb_dividers[] = { 382 { 1, 0 }, 383 { 2, 1 }, 384 { 3, 4 }, 385 { 4, 2 }, 386 { 6, 6 }, 387 { 8, 3 }, 388 { 12, 7 }, 389 { 0, 0 } 390 }; 391 392 /* 393 * This table taken from X11. 394 */ 395 static const struct { 396 int family; 397 struct radeon_tmds_pll plls[4]; 398 } radeonfb_tmds_pll[] = { 399 { RADEON_R100, {{12000, 0xa1b}, {-1, 0xa3f}}}, 400 { RADEON_RV100, {{12000, 0xa1b}, {-1, 0xa3f}}}, 401 { RADEON_RS100, {{0, 0}}}, 402 { RADEON_RV200, {{15000, 0xa1b}, {-1, 0xa3f}}}, 403 { RADEON_RS200, {{15000, 0xa1b}, {-1, 0xa3f}}}, 404 { RADEON_R200, {{15000, 0xa1b}, {-1, 0xa3f}}}, 405 { RADEON_RV250, {{15500, 0x81b}, {-1, 0x83f}}}, 406 { RADEON_RS300, {{0, 0}}}, 407 { RADEON_RV280, {{13000, 0x400f4}, {15000, 0x400f7}}}, 408 { RADEON_R300, {{-1, 0xb01cb}}}, 409 { RADEON_R350, {{-1, 0xb01cb}}}, 410 { RADEON_RV350, {{15000, 0xb0155}, {-1, 0xb01cb}}}, 411 { RADEON_RV380, {{15000, 0xb0155}, {-1, 0xb01cb}}}, 412 { RADEON_R420, {{-1, 0xb01cb}}}, 413 }; 414 415 #define RADEONFB_BACKLIGHT_MAX 255 /* Maximum backlight level. */ 416 417 418 CFATTACH_DECL_NEW(radeonfb, sizeof (struct radeonfb_softc), 419 radeonfb_match, radeonfb_attach, NULL, NULL); 420 421 static int 422 radeonfb_match(device_t parent, cfdata_t match, void *aux) 423 { 424 const struct pci_attach_args *pa = aux; 425 int i; 426 427 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_ATI) 428 return 0; 429 430 for (i = 0; radeonfb_devices[i].devid; i++) { 431 if (PCI_PRODUCT(pa->pa_id) == radeonfb_devices[i].devid) 432 return 100; /* high to defeat VGA/VESA */ 433 } 434 435 return 0; 436 } 437 438 static void 439 radeonfb_attach(device_t parent, device_t dev, void *aux) 440 { 441 struct radeonfb_softc *sc = device_private(dev); 442 const struct pci_attach_args *pa = aux; 443 const char *mptr; 444 bus_size_t bsz; 445 pcireg_t screg; 446 int i, j, fg, bg, ul, flags; 447 uint32_t v; 448 449 sc->sc_dev = dev; 450 sc->sc_id = pa->pa_id; 451 for (i = 0; radeonfb_devices[i].devid; i++) { 452 if (PCI_PRODUCT(sc->sc_id) == radeonfb_devices[i].devid) 453 break; 454 } 455 456 pci_aprint_devinfo(pa, NULL); 457 458 DPRINTF((prop_dictionary_externalize(device_properties(dev)))); 459 460 KASSERT(radeonfb_devices[i].devid != 0); 461 sc->sc_pt = pa->pa_tag; 462 sc->sc_iot = pa->pa_iot; 463 sc->sc_pc = pa->pa_pc; 464 sc->sc_family = radeonfb_devices[i].family; 465 sc->sc_flags = radeonfb_devices[i].flags; 466 467 /* enable memory and IO access */ 468 screg = pci_conf_read(sc->sc_pc, sc->sc_pt, PCI_COMMAND_STATUS_REG); 469 screg |= PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE; 470 pci_conf_write(sc->sc_pc, sc->sc_pt, PCI_COMMAND_STATUS_REG, screg); 471 472 /* 473 * Some flags are general to entire chip families, and rather 474 * than clutter up the table with them, we go ahead and set 475 * them here. 476 */ 477 switch (sc->sc_family) { 478 case RADEON_RS100: 479 case RADEON_RS200: 480 sc->sc_flags |= RFB_IGP | RFB_RV100; 481 break; 482 483 case RADEON_RV100: 484 case RADEON_RV200: 485 case RADEON_RV250: 486 case RADEON_RV280: 487 sc->sc_flags |= RFB_RV100; 488 break; 489 490 case RADEON_RS300: 491 sc->sc_flags |= RFB_SDAC | RFB_IGP | RFB_RV100; 492 break; 493 494 case RADEON_R300: 495 case RADEON_RV350: 496 case RADEON_R350: 497 case RADEON_RV380: 498 case RADEON_R420: 499 /* newer chips */ 500 sc->sc_flags |= RFB_R300; 501 break; 502 503 case RADEON_R100: 504 sc->sc_flags |= RFB_NCRTC2; 505 break; 506 } 507 508 if ((sc->sc_family == RADEON_RV200) || 509 (sc->sc_family == RADEON_RV250) || 510 (sc->sc_family == RADEON_RV280) || 511 (sc->sc_family == RADEON_RV350)) { 512 bool inverted = 0; 513 /* backlight level is linear */ 514 DPRINTF(("found RV* chip, backlight is supposedly linear\n")); 515 prop_dictionary_get_bool(device_properties(sc->sc_dev), 516 "backlight_level_reverted", &inverted); 517 if (inverted) { 518 DPRINTF(("nope, it's inverted\n")); 519 sc->sc_flags |= RFB_INV_BLIGHT; 520 } 521 } else 522 sc->sc_flags |= RFB_INV_BLIGHT; 523 524 /* 525 * XXX: to support true multihead, this must change. 526 */ 527 sc->sc_ndisplays = 1; 528 529 /* XXX: */ 530 if (!HAS_CRTC2(sc)) { 531 sc->sc_ndisplays = 1; 532 } 533 534 if (pci_mapreg_map(pa, RADEON_MAPREG_MMIO, PCI_MAPREG_TYPE_MEM, 0, 535 &sc->sc_regt, &sc->sc_regh, &sc->sc_regaddr, 536 &sc->sc_regsz) != 0) { 537 aprint_error("%s: unable to map registers!\n", XNAME(sc)); 538 goto error; 539 } 540 541 if (pci_mapreg_info(sc->sc_pc, sc->sc_pt, PCI_MAPREG_ROM, 542 PCI_MAPREG_TYPE_ROM, &sc->sc_romaddr, &sc->sc_romsz, &flags) != 0) 543 { 544 aprint_error("%s: unable to find ROM!\n", XNAME(sc)); 545 goto error; 546 } 547 sc->sc_romt = sc->sc_memt; 548 549 /* scratch register test... */ 550 if (radeonfb_scratch_test(sc, RADEON_BIOS_0_SCRATCH, 0x55555555) || 551 radeonfb_scratch_test(sc, RADEON_BIOS_0_SCRATCH, 0xaaaaaaaa)) { 552 aprint_error("%s: scratch register test failed!\n", XNAME(sc)); 553 goto error; 554 } 555 556 PRINTREG(RADEON_BIOS_4_SCRATCH); 557 PRINTREG(RADEON_FP_GEN_CNTL); 558 sc->sc_fp_gen_cntl = GET32(sc, RADEON_FP_GEN_CNTL); 559 PRINTREG(RADEON_FP2_GEN_CNTL); 560 PRINTREG(RADEON_TMDS_CNTL); 561 PRINTREG(RADEON_TMDS_TRANSMITTER_CNTL); 562 PRINTREG(RADEON_TMDS_PLL_CNTL); 563 PRINTREG(RADEON_LVDS_GEN_CNTL); 564 PRINTREG(RADEON_FP_HORZ_STRETCH); 565 PRINTREG(RADEON_FP_VERT_STRETCH); 566 567 /* XXX: RV100 specific */ 568 PUT32(sc, RADEON_TMDS_PLL_CNTL, 0xa27); 569 570 PATCH32(sc, RADEON_TMDS_TRANSMITTER_CNTL, 571 RADEON_TMDS_TRANSMITTER_PLLEN, 572 RADEON_TMDS_TRANSMITTER_PLLEN | RADEON_TMDS_TRANSMITTER_PLLRST); 573 574 radeonfb_i2c_init(sc); 575 576 radeonfb_loadbios(sc, pa); 577 578 #ifdef RADEONFB_BIOS_INIT 579 if (radeonfb_bios_init(sc)) { 580 aprint_error("%s: BIOS inititialization failed\n", XNAME(sc)); 581 } 582 #endif 583 584 if (radeonfb_getclocks(sc)) { 585 aprint_error("%s: Unable to get reference clocks from BIOS\n", 586 XNAME(sc)); 587 goto error; 588 } 589 590 if (radeonfb_gettmds(sc)) { 591 aprint_error("%s: Unable to identify TMDS PLL settings\n", 592 XNAME(sc)); 593 goto error; 594 } 595 596 aprint_verbose("%s: refclk = %d.%03d MHz, refdiv = %d " 597 "minpll = %d, maxpll = %d\n", XNAME(sc), 598 (int)sc->sc_refclk / 1000, (int)sc->sc_refclk % 1000, 599 (int)sc->sc_refdiv, (int)sc->sc_minpll, (int)sc->sc_maxpll); 600 601 radeonfb_getconnectors(sc); 602 603 radeonfb_set_fbloc(sc); 604 605 for (i = 0; radeonfb_limits[i].size; i++) { 606 if (sc->sc_memsz >= radeonfb_limits[i].size) { 607 sc->sc_maxx = radeonfb_limits[i].maxx; 608 sc->sc_maxy = radeonfb_limits[i].maxy; 609 sc->sc_maxbpp = radeonfb_limits[i].maxbpp; 610 /* framebuffer offset, start at a 4K page */ 611 sc->sc_fboffset = sc->sc_memsz / 612 radeonfb_limits[i].maxdisp; 613 /* 614 * we use the fbsize to figure out where we can store 615 * things like cursor data. 616 */ 617 sc->sc_fbsize = 618 ROUNDUP(ROUNDUP(sc->sc_maxx * sc->sc_maxbpp / 8 , 619 RADEON_STRIDEALIGN) * sc->sc_maxy, 620 4096); 621 break; 622 } 623 } 624 625 626 radeonfb_init_misc(sc); 627 radeonfb_init_palette(sc, 0); 628 if (HAS_CRTC2(sc)) 629 radeonfb_init_palette(sc, 1); 630 631 /* program the DAC wirings */ 632 for (i = 0; i < (HAS_CRTC2(sc) ? 2 : 1); i++) { 633 switch (sc->sc_ports[i].rp_dac_type) { 634 case RADEON_DAC_PRIMARY: 635 PATCH32(sc, RADEON_DAC_CNTL2, 636 i ? RADEON_DAC2_DAC_CLK_SEL : 0, 637 ~RADEON_DAC2_DAC_CLK_SEL); 638 break; 639 case RADEON_DAC_TVDAC: 640 /* we always use the TVDAC to drive a secondary analog 641 * CRT for now. if we ever support TV-out this will 642 * have to change. 643 */ 644 SET32(sc, RADEON_DAC_CNTL2, 645 RADEON_DAC2_DAC2_CLK_SEL); 646 PATCH32(sc, RADEON_DISP_HW_DEBUG, 647 i ? 0 : RADEON_CRT2_DISP1_SEL, 648 ~RADEON_CRT2_DISP1_SEL); 649 break; 650 } 651 } 652 PRINTREG(RADEON_DAC_CNTL2); 653 PRINTREG(RADEON_DISP_HW_DEBUG); 654 655 /* other DAC programming */ 656 v = GET32(sc, RADEON_DAC_CNTL); 657 v &= (RADEON_DAC_RANGE_CNTL_MASK | RADEON_DAC_BLANKING); 658 v |= RADEON_DAC_MASK_ALL | RADEON_DAC_8BIT_EN; 659 PUT32(sc, RADEON_DAC_CNTL, v); 660 PRINTREG(RADEON_DAC_CNTL); 661 662 /* XXX: this may need more investigation */ 663 PUT32(sc, RADEON_TV_DAC_CNTL, 0x00280203); 664 PRINTREG(RADEON_TV_DAC_CNTL); 665 666 /* enable TMDS */ 667 SET32(sc, RADEON_FP_GEN_CNTL, 668 RADEON_FP_TMDS_EN | 669 RADEON_FP_CRTC_DONT_SHADOW_VPAR | 670 RADEON_FP_CRTC_DONT_SHADOW_HEND); 671 /* 672 * XXX 673 * no idea why this is necessary - if I do not clear this bit on my 674 * iBook G4 the screen remains black, even though it's already clear. 675 * It needs to be set on my Sun XVR-100 for the DVI port to work 676 */ 677 678 if (sc->sc_fp_gen_cntl & RADEON_FP_SEL_CRTC2) { 679 SET32(sc, RADEON_FP_GEN_CNTL, RADEON_FP_SEL_CRTC2); 680 } else 681 CLR32(sc, RADEON_FP_GEN_CNTL, RADEON_FP_SEL_CRTC2); 682 683 if (HAS_CRTC2(sc)) 684 SET32(sc, RADEON_FP2_GEN_CNTL, RADEON_FP2_SRC_SEL_CRTC2); 685 686 /* 687 * we use bus_space_map instead of pci_mapreg, because we don't 688 * need the full aperature space. no point in wasting virtual 689 * address space we don't intend to use, right? 690 */ 691 if ((sc->sc_memsz < (4096 * 1024)) || 692 (pci_mapreg_info(sc->sc_pc, sc->sc_pt, RADEON_MAPREG_VRAM, 693 PCI_MAPREG_TYPE_MEM, &sc->sc_memaddr, &bsz, NULL) != 0) || 694 (bsz < sc->sc_memsz)) { 695 sc->sc_memsz = 0; 696 aprint_error("%s: Bad frame buffer configuration\n", 697 XNAME(sc)); 698 goto error; 699 } 700 701 /* 64 MB should be enough -- more just wastes map entries */ 702 if (sc->sc_memsz > (64 << 20)) 703 sc->sc_memsz = (64 << 20); 704 705 sc->sc_memt = pa->pa_memt; 706 if (bus_space_map(sc->sc_memt, sc->sc_memaddr, sc->sc_memsz, 707 BUS_SPACE_MAP_LINEAR, &sc->sc_memh) != 0) { 708 sc->sc_memsz = 0; 709 aprint_error("%s: Unable to map frame buffer\n", XNAME(sc)); 710 goto error; 711 } 712 713 aprint_normal("%s: %d MB aperture at 0x%08x, " 714 "%d KB registers at 0x%08x\n", XNAME(sc), 715 (int)sc->sc_memsz >> 20, (unsigned)sc->sc_memaddr, 716 (int)sc->sc_regsz >> 10, (unsigned)sc->sc_regaddr); 717 718 /* setup default video mode from devprop (allows PROM override) */ 719 sc->sc_defaultmode = radeonfb_default_mode; 720 if (prop_dictionary_get_cstring_nocopy(device_properties(sc->sc_dev), 721 "videomode", &mptr)) { 722 723 strncpy(sc->sc_modebuf, mptr, sizeof(sc->sc_modebuf)); 724 sc->sc_defaultmode = sc->sc_modebuf; 725 } 726 727 /* initialize some basic display parameters */ 728 for (i = 0; i < sc->sc_ndisplays; i++) { 729 struct radeonfb_display *dp = &sc->sc_displays[i]; 730 struct rasops_info *ri; 731 long defattr; 732 struct wsemuldisplaydev_attach_args aa; 733 734 /* 735 * Figure out how many "displays" (desktops) we are going to 736 * support. If more than one, then each CRTC gets its own 737 * programming. 738 * 739 * XXX: this code needs to change to support mergedfb. 740 * XXX: would be nice to allow this to be overridden 741 */ 742 if (HAS_CRTC2(sc) && (sc->sc_ndisplays == 1)) { 743 DPRINTF(("dual crtcs!\n")); 744 dp->rd_ncrtcs = 2; 745 dp->rd_crtcs[0].rc_number = 0; 746 dp->rd_crtcs[1].rc_number = 1; 747 } else { 748 dp->rd_ncrtcs = 1; 749 dp->rd_crtcs[0].rc_number = i; 750 } 751 752 /* set up port pointer */ 753 for (j = 0; j < dp->rd_ncrtcs; j++) { 754 dp->rd_crtcs[j].rc_port = 755 &sc->sc_ports[dp->rd_crtcs[j].rc_number]; 756 } 757 758 dp->rd_softc = sc; 759 dp->rd_wsmode = WSDISPLAYIO_MODE_EMUL; 760 dp->rd_bg = WS_DEFAULT_BG; 761 dp->rd_bpp = RADEONFB_DEFAULT_DEPTH; /* XXX */ 762 763 /* for text mode, we pick a resolution that won't 764 * require panning */ 765 radeonfb_pickres(dp, &dp->rd_virtx, &dp->rd_virty, 0); 766 767 aprint_normal("%s: display %d: " 768 "initial virtual resolution %dx%d at %d bpp\n", 769 XNAME(sc), i, dp->rd_virtx, dp->rd_virty, dp->rd_bpp); 770 771 /* now select the *video mode* that we will use */ 772 for (j = 0; j < dp->rd_ncrtcs; j++) { 773 const struct videomode *vmp; 774 vmp = radeonfb_port_mode(sc, dp->rd_crtcs[j].rc_port, 775 dp->rd_virtx, dp->rd_virty); 776 777 /* 778 * virtual resolution should be at least as high as 779 * physical 780 */ 781 if (dp->rd_virtx < vmp->hdisplay || 782 dp->rd_virty < vmp->vdisplay) { 783 dp->rd_virtx = vmp->hdisplay; 784 dp->rd_virty = vmp->vdisplay; 785 } 786 787 dp->rd_crtcs[j].rc_videomode = *vmp; 788 printf("%s: port %d: physical %dx%d %dHz\n", 789 XNAME(sc), j, vmp->hdisplay, vmp->vdisplay, 790 DIVIDE(DIVIDE(vmp->dot_clock * 1000, 791 vmp->htotal), vmp->vtotal)); 792 } 793 794 /* N.B.: radeon wants 64-byte aligned stride */ 795 dp->rd_stride = dp->rd_virtx * dp->rd_bpp / 8; 796 dp->rd_stride = ROUNDUP(dp->rd_stride, RADEON_STRIDEALIGN); 797 798 dp->rd_offset = sc->sc_fboffset * i; 799 dp->rd_fbptr = (vaddr_t)bus_space_vaddr(sc->sc_memt, 800 sc->sc_memh) + dp->rd_offset; 801 dp->rd_curoff = sc->sc_fbsize; 802 dp->rd_curptr = dp->rd_fbptr + dp->rd_curoff; 803 804 DPRINTF(("fpbtr = %p\n", (void *)dp->rd_fbptr)); 805 806 switch (dp->rd_bpp) { 807 case 8: 808 dp->rd_format = 2; 809 break; 810 case 32: 811 dp->rd_format = 6; 812 break; 813 default: 814 aprint_error("%s: bad depth %d\n", XNAME(sc), 815 dp->rd_bpp); 816 goto error; 817 } 818 819 DPRINTF(("init engine\n")); 820 /* XXX: this seems suspicious - per display engine 821 initialization? */ 822 radeonfb_engine_init(dp); 823 824 /* copy the template into place */ 825 dp->rd_wsscreens_storage[0] = radeonfb_stdscreen; 826 dp->rd_wsscreens = dp->rd_wsscreens_storage; 827 828 /* and make up the list */ 829 dp->rd_wsscreenlist.nscreens = 1; 830 dp->rd_wsscreenlist.screens = (void *)&dp->rd_wsscreens; 831 832 vcons_init(&dp->rd_vd, dp, dp->rd_wsscreens, 833 &radeonfb_accessops); 834 835 dp->rd_vd.init_screen = radeonfb_init_screen; 836 837 dp->rd_console = 0; 838 prop_dictionary_get_bool(device_properties(sc->sc_dev), 839 "is_console", &dp->rd_console); 840 841 dp->rd_vscreen.scr_flags |= VCONS_SCREEN_IS_STATIC; 842 843 844 vcons_init_screen(&dp->rd_vd, &dp->rd_vscreen, 845 dp->rd_console, &defattr); 846 847 ri = &dp->rd_vscreen.scr_ri; 848 849 /* clear the screen */ 850 rasops_unpack_attr(defattr, &fg, &bg, &ul); 851 radeonfb_rectfill(dp, 0, 0, ri->ri_width, ri->ri_height, 852 ri->ri_devcmap[bg & 0xf]); 853 854 dp->rd_wsscreens->textops = &ri->ri_ops; 855 dp->rd_wsscreens->capabilities = ri->ri_caps; 856 dp->rd_wsscreens->nrows = ri->ri_rows; 857 dp->rd_wsscreens->ncols = ri->ri_cols; 858 859 #ifdef SPLASHSCREEN 860 dp->rd_splash.si_depth = ri->ri_depth; 861 dp->rd_splash.si_bits = ri->ri_bits; 862 dp->rd_splash.si_hwbits = ri->ri_hwbits; 863 dp->rd_splash.si_width = ri->ri_width; 864 dp->rd_splash.si_height = ri->ri_height; 865 dp->rd_splash.si_stride = ri->ri_stride; 866 dp->rd_splash.si_fillrect = NULL; 867 #endif 868 dp->rd_gc.gc_bitblt = radeonfb_bitblt; 869 dp->rd_gc.gc_rop = RADEON_ROP3_S; 870 dp->rd_gc.gc_blitcookie = dp; 871 glyphcache_init(&dp->rd_gc, dp->rd_virty + 4, 872 (0x800000 / dp->rd_stride) - (dp->rd_virty + 4), 873 dp->rd_virty, 874 ri->ri_font->fontwidth, 875 ri->ri_font->fontheight, 876 defattr); 877 if (dp->rd_console) { 878 879 radeonfb_modeswitch(dp); 880 wsdisplay_cnattach(dp->rd_wsscreens, ri, 0, 0, 881 defattr); 882 #ifdef SPLASHSCREEN 883 if (splash_render(&dp->rd_splash, 884 SPLASH_F_CENTER|SPLASH_F_FILL) == 0) 885 SCREEN_DISABLE_DRAWING(&dp->rd_vscreen); 886 else 887 #endif 888 vcons_replay_msgbuf(&dp->rd_vscreen); 889 } else { 890 891 /* 892 * since we're not the console we can postpone 893 * the rest until someone actually allocates a 894 * screen for us. but we do clear the screen 895 * at least. 896 */ 897 memset(ri->ri_bits, 0, 1024); 898 899 radeonfb_modeswitch(dp); 900 #ifdef SPLASHSCREEN 901 if (splash_render(&dp->rd_splash, 902 SPLASH_F_CENTER|SPLASH_F_FILL) == 0) 903 SCREEN_DISABLE_DRAWING(&dp->rd_vscreen); 904 #endif 905 } 906 907 aa.console = dp->rd_console; 908 aa.scrdata = &dp->rd_wsscreenlist; 909 aa.accessops = &radeonfb_accessops; 910 aa.accesscookie = &dp->rd_vd; 911 912 config_found(sc->sc_dev, &aa, wsemuldisplaydevprint); 913 914 radeonfb_blank(dp, 0); 915 916 /* Initialise delayed lvds operations for backlight. */ 917 callout_init(&dp->rd_bl_lvds_co, 0); 918 callout_setfunc(&dp->rd_bl_lvds_co, 919 radeonfb_lvds_callout, dp); 920 dp->rd_bl_on = 1; 921 dp->rd_bl_level = radeonfb_get_backlight(dp); 922 radeonfb_set_backlight(dp, dp->rd_bl_level); 923 } 924 925 /* 926 * if we have console output via firmware like on sparc64 it may 927 * interfere with DAC programming so program the palette again 928 * here after we took over 929 */ 930 radeonfb_init_palette(sc, 0); 931 if (HAS_CRTC2(sc)) 932 radeonfb_init_palette(sc, 1); 933 934 pmf_event_register(dev, PMFE_DISPLAY_BRIGHTNESS_UP, 935 radeonfb_brightness_up, TRUE); 936 pmf_event_register(dev, PMFE_DISPLAY_BRIGHTNESS_DOWN, 937 radeonfb_brightness_down, TRUE); 938 939 config_found_ia(dev, "drm", aux, radeonfb_drm_print); 940 941 return; 942 943 error: 944 if (sc->sc_biossz) 945 free(sc->sc_bios, M_DEVBUF); 946 947 if (sc->sc_regsz) 948 bus_space_unmap(sc->sc_regt, sc->sc_regh, sc->sc_regsz); 949 950 if (sc->sc_memsz) 951 bus_space_unmap(sc->sc_memt, sc->sc_memh, sc->sc_memsz); 952 } 953 954 static void 955 radeonfb_map(struct radeonfb_softc *sc) 956 { 957 if (bus_space_map(sc->sc_regt, sc->sc_regaddr, sc->sc_regsz, 0, 958 &sc->sc_regh) != 0) { 959 aprint_error("%s: unable to map registers!\n", XNAME(sc)); 960 return; 961 } 962 if (bus_space_map(sc->sc_memt, sc->sc_memaddr, sc->sc_memsz, 963 BUS_SPACE_MAP_LINEAR, &sc->sc_memh) != 0) { 964 sc->sc_memsz = 0; 965 aprint_error("%s: Unable to map frame buffer\n", XNAME(sc)); 966 return; 967 } 968 } 969 970 static void 971 radeonfb_unmap(struct radeonfb_softc *sc) 972 { 973 bus_space_unmap(sc->sc_regt, sc->sc_regh, sc->sc_regsz); 974 bus_space_unmap(sc->sc_memt, sc->sc_memh, sc->sc_memsz); 975 } 976 977 static int 978 radeonfb_drm_print(void *aux, const char *pnp) 979 { 980 if (pnp) 981 aprint_normal("drm at %s", pnp); 982 return (UNCONF); 983 } 984 985 int 986 radeonfb_ioctl(void *v, void *vs, 987 unsigned long cmd, void *d, int flag, struct lwp *l) 988 { 989 struct vcons_data *vd; 990 struct radeonfb_display *dp; 991 struct radeonfb_softc *sc; 992 struct wsdisplay_param *param; 993 994 vd = (struct vcons_data *)v; 995 dp = (struct radeonfb_display *)vd->cookie; 996 sc = dp->rd_softc; 997 998 switch (cmd) { 999 case WSDISPLAYIO_GTYPE: 1000 *(unsigned *)d = WSDISPLAY_TYPE_PCIMISC; 1001 return 0; 1002 1003 case WSDISPLAYIO_GINFO: 1004 if (vd->active != NULL) { 1005 struct wsdisplay_fbinfo *fb; 1006 fb = (struct wsdisplay_fbinfo *)d; 1007 fb->width = dp->rd_virtx; 1008 fb->height = dp->rd_virty; 1009 fb->depth = dp->rd_bpp; 1010 fb->cmsize = 256; 1011 return 0; 1012 } else 1013 return ENODEV; 1014 case WSDISPLAYIO_GVIDEO: 1015 if (radeonfb_isblank(dp)) 1016 *(unsigned *)d = WSDISPLAYIO_VIDEO_OFF; 1017 else 1018 *(unsigned *)d = WSDISPLAYIO_VIDEO_ON; 1019 return 0; 1020 1021 case WSDISPLAYIO_SVIDEO: 1022 radeonfb_blank(dp, 1023 (*(unsigned int *)d == WSDISPLAYIO_VIDEO_OFF)); 1024 return 0; 1025 1026 case WSDISPLAYIO_GETCMAP: 1027 #if 0 1028 if (dp->rd_bpp == 8) 1029 return radeonfb_getcmap(sc, 1030 (struct wsdisplay_cmap *)d); 1031 #endif 1032 return EINVAL; 1033 1034 case WSDISPLAYIO_PUTCMAP: 1035 #if 0 1036 if (dp->rd_bpp == 8) 1037 return radeonfb_putcmap(sc, 1038 (struct wsdisplay_cmap *)d); 1039 #endif 1040 return EINVAL; 1041 1042 case WSDISPLAYIO_LINEBYTES: 1043 *(unsigned *)d = dp->rd_stride; 1044 return 0; 1045 1046 case WSDISPLAYIO_SMODE: 1047 if (*(int *)d != dp->rd_wsmode) { 1048 dp->rd_wsmode = *(int *)d; 1049 if ((dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) && 1050 (dp->rd_vd.active)) { 1051 radeonfb_map(sc); 1052 radeonfb_engine_init(dp); 1053 glyphcache_wipe(&dp->rd_gc); 1054 radeonfb_init_palette(sc, dp == &sc->sc_displays[0] ? 0 : 1); 1055 radeonfb_modeswitch(dp); 1056 vcons_redraw_screen(dp->rd_vd.active); 1057 } else { 1058 radeonfb_unmap(sc); 1059 } 1060 } 1061 return 0; 1062 1063 case WSDISPLAYIO_GCURMAX: 1064 ((struct wsdisplay_curpos *)d)->x = RADEON_CURSORMAXX; 1065 ((struct wsdisplay_curpos *)d)->y = RADEON_CURSORMAXY; 1066 return 0; 1067 1068 case WSDISPLAYIO_SCURSOR: 1069 return radeonfb_set_cursor(dp, (struct wsdisplay_cursor *)d); 1070 1071 case WSDISPLAYIO_GCURSOR: 1072 return EPASSTHROUGH; 1073 1074 case WSDISPLAYIO_GCURPOS: 1075 ((struct wsdisplay_curpos *)d)->x = dp->rd_cursor.rc_pos.x; 1076 ((struct wsdisplay_curpos *)d)->y = dp->rd_cursor.rc_pos.y; 1077 return 0; 1078 1079 case WSDISPLAYIO_SCURPOS: 1080 return radeonfb_set_curpos(dp, (struct wsdisplay_curpos *)d); 1081 1082 case WSDISPLAYIO_SSPLASH: 1083 #if defined(SPLASHSCREEN) 1084 if (*(int *)d == 1) { 1085 SCREEN_DISABLE_DRAWING(&dp->rd_vscreen); 1086 splash_render(&dp->rd_splash, 1087 SPLASH_F_CENTER|SPLASH_F_FILL); 1088 } else 1089 SCREEN_ENABLE_DRAWING(&dp->rd_vscreen); 1090 return 0; 1091 #else 1092 return ENODEV; 1093 #endif 1094 case WSDISPLAYIO_GETPARAM: 1095 param = (struct wsdisplay_param *)d; 1096 switch (param->param) { 1097 case WSDISPLAYIO_PARAM_BRIGHTNESS: 1098 param->min = 0; 1099 param->max = 255; 1100 param->curval = dp->rd_bl_level; 1101 return 0; 1102 case WSDISPLAYIO_PARAM_BACKLIGHT: 1103 param->min = 0; 1104 param->max = RADEONFB_BACKLIGHT_MAX; 1105 param->curval = dp->rd_bl_on; 1106 return 0; 1107 } 1108 return EPASSTHROUGH; 1109 1110 case WSDISPLAYIO_SETPARAM: 1111 param = (struct wsdisplay_param *)d; 1112 switch (param->param) { 1113 case WSDISPLAYIO_PARAM_BRIGHTNESS: 1114 radeonfb_set_backlight(dp, param->curval); 1115 return 0; 1116 case WSDISPLAYIO_PARAM_BACKLIGHT: 1117 radeonfb_switch_backlight(dp, param->curval); 1118 return 0; 1119 } 1120 return EPASSTHROUGH; 1121 1122 /* PCI config read/write passthrough. */ 1123 case PCI_IOC_CFGREAD: 1124 case PCI_IOC_CFGWRITE: 1125 return pci_devioctl(sc->sc_pc, sc->sc_pt, cmd, d, flag, l); 1126 1127 case WSDISPLAYIO_GET_BUSID: 1128 return wsdisplayio_busid_pci(sc->sc_dev, sc->sc_pc, 1129 sc->sc_pt, d); 1130 1131 case WSDISPLAYIO_GET_EDID: { 1132 struct wsdisplayio_edid_info *ei = d; 1133 return wsdisplayio_get_edid(sc->sc_dev, ei); 1134 } 1135 1136 default: 1137 return EPASSTHROUGH; 1138 } 1139 } 1140 1141 paddr_t 1142 radeonfb_mmap(void *v, void *vs, off_t offset, int prot) 1143 { 1144 struct vcons_data *vd; 1145 struct radeonfb_display *dp; 1146 struct radeonfb_softc *sc; 1147 paddr_t pa; 1148 1149 vd = (struct vcons_data *)v; 1150 dp = (struct radeonfb_display *)vd->cookie; 1151 sc = dp->rd_softc; 1152 1153 /* XXX: note that we don't allow mapping of registers right now */ 1154 /* XXX: this means that the XFree86 radeon driver won't work */ 1155 if ((offset >= 0) && (offset < (dp->rd_virty * dp->rd_stride))) { 1156 pa = bus_space_mmap(sc->sc_memt, 1157 sc->sc_memaddr + dp->rd_offset + offset, 0, 1158 prot, BUS_SPACE_MAP_LINEAR); 1159 return pa; 1160 } 1161 1162 #ifdef RADEONFB_MMAP_BARS 1163 /* 1164 * restrict all other mappings to processes with superuser privileges 1165 * or the kernel itself 1166 */ 1167 if (kauth_authorize_machdep(kauth_cred_get(), KAUTH_MACHDEP_UNMANAGEDMEM, 1168 NULL, NULL, NULL, NULL) != 0) { 1169 aprint_error_dev(sc->sc_dev, "mmap() rejected.\n"); 1170 return -1; 1171 } 1172 1173 if ((offset >= sc->sc_regaddr) && 1174 (offset < sc->sc_regaddr + sc->sc_regsz)) { 1175 return bus_space_mmap(sc->sc_regt, offset, 0, prot, 1176 BUS_SPACE_MAP_LINEAR); 1177 } 1178 1179 if ((offset >= sc->sc_memaddr) && 1180 (offset < sc->sc_memaddr + sc->sc_memsz)) { 1181 return bus_space_mmap(sc->sc_memt, offset, 0, prot, 1182 BUS_SPACE_MAP_LINEAR); 1183 } 1184 1185 if ((offset >= sc->sc_romaddr) && 1186 (offset < sc->sc_romaddr + sc->sc_romsz)) { 1187 return bus_space_mmap(sc->sc_memt, offset, 0, prot, 1188 BUS_SPACE_MAP_LINEAR); 1189 } 1190 1191 #ifdef PCI_MAGIC_IO_RANGE 1192 /* allow mapping of IO space */ 1193 if ((offset >= PCI_MAGIC_IO_RANGE) && 1194 (offset < PCI_MAGIC_IO_RANGE + 0x10000)) { 1195 pa = bus_space_mmap(sc->sc_iot, offset - PCI_MAGIC_IO_RANGE, 1196 0, prot, 0); 1197 return pa; 1198 } 1199 #endif /* PCI_MAGIC_IO_RANGE */ 1200 1201 #endif /* RADEONFB_MMAP_BARS */ 1202 1203 return -1; 1204 } 1205 1206 static void 1207 radeonfb_loadbios(struct radeonfb_softc *sc, const struct pci_attach_args *pa) 1208 { 1209 bus_space_tag_t romt; 1210 bus_space_handle_t romh, biosh; 1211 bus_size_t romsz; 1212 bus_addr_t ptr; 1213 1214 if (pci_mapreg_map(pa, PCI_MAPREG_ROM, PCI_MAPREG_TYPE_ROM, 1215 BUS_SPACE_MAP_PREFETCHABLE, &romt, &romh, NULL, &romsz) != 0) { 1216 aprint_verbose("%s: unable to map BIOS!\n", XNAME(sc)); 1217 return; 1218 } 1219 1220 pci_find_rom(pa, romt, romh, PCI_ROM_CODE_TYPE_X86, &biosh, 1221 &sc->sc_biossz); 1222 if (sc->sc_biossz == 0) { 1223 aprint_verbose("%s: Video BIOS not present\n", XNAME(sc)); 1224 return; 1225 } 1226 1227 sc->sc_bios = malloc(sc->sc_biossz, M_DEVBUF, M_WAITOK); 1228 bus_space_read_region_1(romt, biosh, 0, sc->sc_bios, sc->sc_biossz); 1229 1230 /* unmap the PCI expansion rom */ 1231 bus_space_unmap(romt, romh, romsz); 1232 1233 /* turn off rom decoder now */ 1234 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM, 1235 pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM) & 1236 ~PCI_MAPREG_ROM_ENABLE); 1237 1238 ptr = GETBIOS16(sc, 0x48); 1239 if ((GETBIOS32(sc, ptr + 4) == 0x41544f4d /* "ATOM" */) || 1240 (GETBIOS32(sc, ptr + 4) == 0x4d4f5441 /* "MOTA" */)) { 1241 sc->sc_flags |= RFB_ATOM; 1242 } 1243 1244 aprint_verbose("%s: Found %d KB %s BIOS\n", XNAME(sc), 1245 (unsigned)sc->sc_biossz >> 10, IS_ATOM(sc) ? "ATOM" : "Legacy"); 1246 } 1247 1248 1249 uint32_t 1250 radeonfb_get32(struct radeonfb_softc *sc, uint32_t reg) 1251 { 1252 1253 return bus_space_read_4(sc->sc_regt, sc->sc_regh, reg); 1254 } 1255 1256 void 1257 radeonfb_put32(struct radeonfb_softc *sc, uint32_t reg, uint32_t val) 1258 { 1259 1260 bus_space_write_4(sc->sc_regt, sc->sc_regh, reg, val); 1261 } 1262 1263 void 1264 radeonfb_put32s(struct radeonfb_softc *sc, uint32_t reg, uint32_t val) 1265 { 1266 1267 bus_space_write_stream_4(sc->sc_regt, sc->sc_regh, reg, val); 1268 } 1269 1270 void 1271 radeonfb_mask32(struct radeonfb_softc *sc, uint32_t reg, 1272 uint32_t andmask, uint32_t ormask) 1273 { 1274 int s; 1275 uint32_t val; 1276 1277 s = splhigh(); 1278 val = radeonfb_get32(sc, reg); 1279 val = (val & andmask) | ormask; 1280 radeonfb_put32(sc, reg, val); 1281 splx(s); 1282 } 1283 1284 uint32_t 1285 radeonfb_getindex(struct radeonfb_softc *sc, uint32_t idx) 1286 { 1287 int s; 1288 uint32_t val; 1289 1290 s = splhigh(); 1291 radeonfb_put32(sc, RADEON_MM_INDEX, idx); 1292 val = radeonfb_get32(sc, RADEON_MM_DATA); 1293 splx(s); 1294 1295 return (val); 1296 } 1297 1298 void 1299 radeonfb_putindex(struct radeonfb_softc *sc, uint32_t idx, uint32_t val) 1300 { 1301 int s; 1302 1303 s = splhigh(); 1304 radeonfb_put32(sc, RADEON_MM_INDEX, idx); 1305 radeonfb_put32(sc, RADEON_MM_DATA, val); 1306 splx(s); 1307 } 1308 1309 void 1310 radeonfb_maskindex(struct radeonfb_softc *sc, uint32_t idx, 1311 uint32_t andmask, uint32_t ormask) 1312 { 1313 int s; 1314 uint32_t val; 1315 1316 s = splhigh(); 1317 radeonfb_put32(sc, RADEON_MM_INDEX, idx); 1318 val = radeonfb_get32(sc, RADEON_MM_DATA); 1319 val = (val & andmask) | ormask; 1320 radeonfb_put32(sc, RADEON_MM_DATA, val); 1321 splx(s); 1322 } 1323 1324 uint32_t 1325 radeonfb_getpll(struct radeonfb_softc *sc, uint32_t idx) 1326 { 1327 int s; 1328 uint32_t val; 1329 1330 s = splhigh(); 1331 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, idx & 0x3f); 1332 val = radeonfb_get32(sc, RADEON_CLOCK_CNTL_DATA); 1333 if (HAS_R300CG(sc)) 1334 radeonfb_r300cg_workaround(sc); 1335 splx(s); 1336 1337 return (val); 1338 } 1339 1340 void 1341 radeonfb_putpll(struct radeonfb_softc *sc, uint32_t idx, uint32_t val) 1342 { 1343 int s; 1344 1345 s = splhigh(); 1346 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, (idx & 0x3f) | 1347 RADEON_PLL_WR_EN); 1348 radeonfb_put32(sc, RADEON_CLOCK_CNTL_DATA, val); 1349 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, 0); 1350 splx(s); 1351 } 1352 1353 void 1354 radeonfb_maskpll(struct radeonfb_softc *sc, uint32_t idx, 1355 uint32_t andmask, uint32_t ormask) 1356 { 1357 int s; 1358 uint32_t val; 1359 1360 s = splhigh(); 1361 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, (idx & 0x3f) | 1362 RADEON_PLL_WR_EN); 1363 val = radeonfb_get32(sc, RADEON_CLOCK_CNTL_DATA); 1364 val = (val & andmask) | ormask; 1365 radeonfb_put32(sc, RADEON_CLOCK_CNTL_DATA, val); 1366 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, 0); 1367 splx(s); 1368 } 1369 1370 int 1371 radeonfb_scratch_test(struct radeonfb_softc *sc, int reg, uint32_t v) 1372 { 1373 uint32_t saved; 1374 1375 saved = GET32(sc, reg); 1376 PUT32(sc, reg, v); 1377 if (GET32(sc, reg) != v) { 1378 return -1; 1379 } 1380 PUT32(sc, reg, saved); 1381 return 0; 1382 } 1383 1384 uintmax_t 1385 radeonfb_getprop_num(struct radeonfb_softc *sc, const char *name, 1386 uintmax_t defval) 1387 { 1388 prop_number_t pn; 1389 pn = prop_dictionary_get(device_properties(sc->sc_dev), name); 1390 if (pn == NULL) { 1391 return defval; 1392 } 1393 KASSERT(prop_object_type(pn) == PROP_TYPE_NUMBER); 1394 return (prop_number_integer_value(pn)); 1395 } 1396 1397 int 1398 radeonfb_getclocks(struct radeonfb_softc *sc) 1399 { 1400 bus_addr_t ptr; 1401 int refclk = 0; 1402 int refdiv = 0; 1403 int minpll = 0; 1404 int maxpll = 0; 1405 1406 /* load initial property values if port/board provides them */ 1407 refclk = radeonfb_getprop_num(sc, "refclk", 0) & 0xffff; 1408 refdiv = radeonfb_getprop_num(sc, "refdiv", 0) & 0xffff; 1409 minpll = radeonfb_getprop_num(sc, "minpll", 0) & 0xffffffffU; 1410 maxpll = radeonfb_getprop_num(sc, "maxpll", 0) & 0xffffffffU; 1411 1412 if (refclk && refdiv && minpll && maxpll) 1413 goto dontprobe; 1414 1415 if (!sc->sc_biossz) { 1416 /* no BIOS */ 1417 aprint_verbose("%s: No video BIOS, using default clocks\n", 1418 XNAME(sc)); 1419 if (IS_IGP(sc)) 1420 refclk = refclk ? refclk : 1432; 1421 else 1422 refclk = refclk ? refclk : 2700; 1423 refdiv = refdiv ? refdiv : 12; 1424 minpll = minpll ? minpll : 12500; 1425 maxpll = maxpll ? maxpll : 35000; 1426 } else if (IS_ATOM(sc)) { 1427 /* ATOM BIOS */ 1428 ptr = GETBIOS16(sc, 0x48); 1429 ptr = GETBIOS16(sc, ptr + 32); /* aka MasterDataStart */ 1430 ptr = GETBIOS16(sc, ptr + 12); /* pll info block */ 1431 refclk = refclk ? refclk : GETBIOS16(sc, ptr + 82); 1432 minpll = minpll ? minpll : GETBIOS16(sc, ptr + 78); 1433 maxpll = maxpll ? maxpll : GETBIOS16(sc, ptr + 32); 1434 /* 1435 * ATOM BIOS doesn't supply a reference divider, so we 1436 * have to probe for it. 1437 */ 1438 if (refdiv < 2) 1439 refdiv = GETPLL(sc, RADEON_PPLL_REF_DIV) & 1440 RADEON_PPLL_REF_DIV_MASK; 1441 /* 1442 * if probe is zero, just assume one that should work 1443 * for most parts 1444 */ 1445 if (refdiv < 2) 1446 refdiv = 12; 1447 1448 } else { 1449 /* Legacy BIOS */ 1450 ptr = GETBIOS16(sc, 0x48); 1451 ptr = GETBIOS16(sc, ptr + 0x30); 1452 refclk = refclk ? refclk : GETBIOS16(sc, ptr + 0x0E); 1453 refdiv = refdiv ? refdiv : GETBIOS16(sc, ptr + 0x10); 1454 minpll = minpll ? minpll : GETBIOS32(sc, ptr + 0x12); 1455 maxpll = maxpll ? maxpll : GETBIOS32(sc, ptr + 0x16); 1456 } 1457 1458 1459 dontprobe: 1460 sc->sc_refclk = refclk * 10; 1461 sc->sc_refdiv = refdiv; 1462 sc->sc_minpll = minpll * 10; 1463 sc->sc_maxpll = maxpll * 10; 1464 return 0; 1465 } 1466 1467 int 1468 radeonfb_calc_dividers(struct radeonfb_softc *sc, uint32_t dotclock, 1469 uint32_t *postdivbit, uint32_t *feedbackdiv) 1470 { 1471 int i; 1472 uint32_t outfreq; 1473 int div; 1474 1475 DPRINTF(("dot clock: %u\n", dotclock)); 1476 for (i = 0; (div = radeonfb_dividers[i].divider) != 0; i++) { 1477 outfreq = div * dotclock; 1478 if ((outfreq >= sc->sc_minpll) && 1479 (outfreq <= sc->sc_maxpll)) { 1480 DPRINTF(("outfreq: %u\n", outfreq)); 1481 *postdivbit = 1482 ((uint32_t)radeonfb_dividers[i].mask << 16); 1483 DPRINTF(("post divider: %d (mask %x)\n", div, 1484 *postdivbit)); 1485 break; 1486 } 1487 } 1488 1489 if (div == 0) 1490 return 1; 1491 1492 *feedbackdiv = DIVIDE(sc->sc_refdiv * outfreq, sc->sc_refclk); 1493 DPRINTF(("feedback divider: %d\n", *feedbackdiv)); 1494 return 0; 1495 } 1496 1497 #if 0 1498 #ifdef RADEONFB_DEBUG 1499 static void 1500 dump_buffer(const char *pfx, void *buffer, unsigned int size) 1501 { 1502 char asc[17]; 1503 unsigned ptr = (unsigned)buffer; 1504 char *start = (char *)(ptr & ~0xf); 1505 char *end = (char *)(ptr + size); 1506 1507 end = (char *)(((unsigned)end + 0xf) & ~0xf); 1508 1509 if (pfx == NULL) { 1510 pfx = ""; 1511 } 1512 1513 while (start < end) { 1514 unsigned offset = (unsigned)start & 0xf; 1515 if (offset == 0) { 1516 printf("%s%x: ", pfx, (unsigned)start); 1517 } 1518 if (((unsigned)start < ptr) || 1519 ((unsigned)start >= (ptr + size))) { 1520 printf(" "); 1521 asc[offset] = ' '; 1522 } else { 1523 printf("%02x", *(unsigned char *)start); 1524 if ((*start >= ' ') && (*start <= '~')) { 1525 asc[offset] = *start; 1526 } else { 1527 asc[offset] = '.'; 1528 } 1529 } 1530 asc[offset + 1] = 0; 1531 if (offset % 2) { 1532 printf(" "); 1533 } 1534 if (offset == 15) { 1535 printf(" %s\n", asc); 1536 } 1537 start++; 1538 } 1539 } 1540 #endif 1541 #endif 1542 1543 int 1544 radeonfb_getconnectors(struct radeonfb_softc *sc) 1545 { 1546 int i; 1547 int found = 0; 1548 1549 for (i = 0; i < 2; i++) { 1550 sc->sc_ports[i].rp_mon_type = RADEON_MT_UNKNOWN; 1551 sc->sc_ports[i].rp_ddc_type = RADEON_DDC_NONE; 1552 sc->sc_ports[i].rp_dac_type = RADEON_DAC_UNKNOWN; 1553 sc->sc_ports[i].rp_conn_type = RADEON_CONN_NONE; 1554 sc->sc_ports[i].rp_tmds_type = RADEON_TMDS_UNKNOWN; 1555 } 1556 1557 /* 1558 * This logic is borrowed from Xorg's radeon driver. 1559 */ 1560 if (!sc->sc_biossz) 1561 goto nobios; 1562 1563 if (IS_ATOM(sc)) { 1564 /* not done yet */ 1565 } else { 1566 uint16_t ptr; 1567 int port = 0; 1568 1569 ptr = GETBIOS16(sc, 0x48); 1570 ptr = GETBIOS16(sc, ptr + 0x50); 1571 for (i = 1; i < 4; i++) { 1572 uint16_t entry; 1573 uint8_t conn, ddc, dac, tmds; 1574 1575 /* 1576 * Parse the connector table. From reading the code, 1577 * it appears to made up of 16-bit entries for each 1578 * connector. The 16-bits are defined as: 1579 * 1580 * bits 12-15 - connector type (0 == end of table) 1581 * bits 8-11 - DDC type 1582 * bits 5-7 - ??? 1583 * bit 4 - TMDS type (1 = EXT, 0 = INT) 1584 * bits 1-3 - ??? 1585 * bit 0 - DAC, 1 = TVDAC, 0 = primary 1586 */ 1587 if (!GETBIOS8(sc, ptr + i * 2) && i > 1) 1588 break; 1589 entry = GETBIOS16(sc, ptr + i * 2); 1590 1591 conn = (entry >> 12) & 0xf; 1592 ddc = (entry >> 8) & 0xf; 1593 dac = (entry & 0x1) ? RADEON_DAC_TVDAC : 1594 RADEON_DAC_PRIMARY; 1595 tmds = ((entry >> 4) & 0x1) ? RADEON_TMDS_EXT : 1596 RADEON_TMDS_INT; 1597 1598 if (conn == RADEON_CONN_NONE) 1599 continue; /* no connector */ 1600 1601 if ((found > 0) && 1602 (sc->sc_ports[port].rp_ddc_type == ddc)) { 1603 /* duplicate entry for same connector */ 1604 continue; 1605 } 1606 1607 /* internal DDC_DVI port gets priority */ 1608 if ((ddc == RADEON_DDC_DVI) || (port == 1)) 1609 port = 0; 1610 else 1611 port = 1; 1612 1613 sc->sc_ports[port].rp_ddc_type = 1614 ddc > RADEON_DDC_CRT2 ? RADEON_DDC_NONE : ddc; 1615 sc->sc_ports[port].rp_dac_type = dac; 1616 sc->sc_ports[port].rp_conn_type = 1617 min(conn, RADEON_CONN_UNSUPPORTED) ; 1618 1619 sc->sc_ports[port].rp_tmds_type = tmds; 1620 1621 if ((conn != RADEON_CONN_DVI_I) && 1622 (conn != RADEON_CONN_DVI_D) && 1623 (tmds == RADEON_TMDS_INT)) 1624 sc->sc_ports[port].rp_tmds_type = 1625 RADEON_TMDS_UNKNOWN; 1626 1627 found += (port + 1); 1628 } 1629 } 1630 1631 nobios: 1632 if (!found) { 1633 DPRINTF(("No connector info in BIOS!\n")); 1634 /* default, port 0 = internal TMDS, port 1 = CRT */ 1635 sc->sc_ports[0].rp_mon_type = RADEON_MT_UNKNOWN; 1636 sc->sc_ports[0].rp_ddc_type = RADEON_DDC_DVI; 1637 sc->sc_ports[0].rp_dac_type = RADEON_DAC_TVDAC; 1638 sc->sc_ports[0].rp_conn_type = RADEON_CONN_DVI_D; 1639 sc->sc_ports[0].rp_tmds_type = RADEON_TMDS_INT; 1640 1641 sc->sc_ports[1].rp_mon_type = RADEON_MT_UNKNOWN; 1642 sc->sc_ports[1].rp_ddc_type = RADEON_DDC_VGA; 1643 sc->sc_ports[1].rp_dac_type = RADEON_DAC_PRIMARY; 1644 sc->sc_ports[1].rp_conn_type = RADEON_CONN_CRT; 1645 sc->sc_ports[1].rp_tmds_type = RADEON_TMDS_EXT; 1646 } 1647 1648 /* 1649 * Fixup for RS300/RS350/RS400 chips, that lack a primary DAC. 1650 * these chips should use TVDAC for the VGA port. 1651 */ 1652 if (HAS_SDAC(sc)) { 1653 if (sc->sc_ports[0].rp_conn_type == RADEON_CONN_CRT) { 1654 sc->sc_ports[0].rp_dac_type = RADEON_DAC_TVDAC; 1655 sc->sc_ports[1].rp_dac_type = RADEON_DAC_PRIMARY; 1656 } else { 1657 sc->sc_ports[1].rp_dac_type = RADEON_DAC_TVDAC; 1658 sc->sc_ports[0].rp_dac_type = RADEON_DAC_PRIMARY; 1659 } 1660 } else if (!HAS_CRTC2(sc)) { 1661 sc->sc_ports[0].rp_dac_type = RADEON_DAC_PRIMARY; 1662 } 1663 1664 for (i = 0; i < 2; i++) { 1665 char edid[128]; 1666 uint8_t ddc; 1667 struct edid_info *eip = &sc->sc_ports[i].rp_edid; 1668 prop_data_t edid_data; 1669 1670 DPRINTF(("Port #%d:\n", i)); 1671 DPRINTF((" conn = %d\n", sc->sc_ports[i].rp_conn_type)); 1672 DPRINTF((" ddc = %d\n", sc->sc_ports[i].rp_ddc_type)); 1673 DPRINTF((" dac = %d\n", sc->sc_ports[i].rp_dac_type)); 1674 DPRINTF((" tmds = %d\n", sc->sc_ports[i].rp_tmds_type)); 1675 1676 sc->sc_ports[i].rp_edid_valid = 0; 1677 /* first look for static EDID data */ 1678 if ((edid_data = prop_dictionary_get(device_properties( 1679 sc->sc_dev), "EDID")) != NULL) { 1680 1681 aprint_normal_dev(sc->sc_dev, "using static EDID\n"); 1682 memcpy(edid, prop_data_data_nocopy(edid_data), 128); 1683 if (edid_parse(edid, eip) == 0) { 1684 1685 sc->sc_ports[i].rp_edid_valid = 1; 1686 } 1687 } 1688 /* if we didn't find any we'll try to talk to the monitor */ 1689 if (sc->sc_ports[i].rp_edid_valid != 1) { 1690 1691 ddc = sc->sc_ports[i].rp_ddc_type; 1692 if (ddc != RADEON_DDC_NONE) { 1693 if ((radeonfb_i2c_read_edid(sc, ddc, edid) 1694 == 0) && (edid_parse(edid, eip) == 0)) { 1695 1696 sc->sc_ports[i].rp_edid_valid = 1; 1697 edid_print(eip); 1698 } 1699 } 1700 } 1701 } 1702 1703 return found; 1704 } 1705 1706 int 1707 radeonfb_gettmds(struct radeonfb_softc *sc) 1708 { 1709 int i; 1710 1711 if (!sc->sc_biossz) { 1712 goto nobios; 1713 } 1714 1715 if (IS_ATOM(sc)) { 1716 /* XXX: not done yet */ 1717 } else { 1718 uint16_t ptr; 1719 int n; 1720 1721 ptr = GETBIOS16(sc, 0x48); 1722 ptr = GETBIOS16(sc, ptr + 0x34); 1723 DPRINTF(("DFP table revision %d\n", GETBIOS8(sc, ptr))); 1724 if (GETBIOS8(sc, ptr) == 3) { 1725 /* revision three table */ 1726 n = GETBIOS8(sc, ptr + 5) + 1; 1727 n = min(n, 4); 1728 1729 memset(sc->sc_tmds_pll, 0, sizeof (sc->sc_tmds_pll)); 1730 for (i = 0; i < n; i++) { 1731 sc->sc_tmds_pll[i].rtp_pll = GETBIOS32(sc, 1732 ptr + i * 10 + 8); 1733 sc->sc_tmds_pll[i].rtp_freq = GETBIOS16(sc, 1734 ptr + i * 10 + 0x10); 1735 DPRINTF(("TMDS_PLL dot clock %d pll %x\n", 1736 sc->sc_tmds_pll[i].rtp_freq, 1737 sc->sc_tmds_pll[i].rtp_pll)); 1738 } 1739 return 0; 1740 } 1741 } 1742 1743 nobios: 1744 DPRINTF(("no suitable DFP table present\n")); 1745 for (i = 0; 1746 i < sizeof (radeonfb_tmds_pll) / sizeof (radeonfb_tmds_pll[0]); 1747 i++) { 1748 int j; 1749 1750 if (radeonfb_tmds_pll[i].family != sc->sc_family) 1751 continue; 1752 1753 for (j = 0; j < 4; j++) { 1754 sc->sc_tmds_pll[j] = radeonfb_tmds_pll[i].plls[j]; 1755 DPRINTF(("TMDS_PLL dot clock %d pll %x\n", 1756 sc->sc_tmds_pll[j].rtp_freq, 1757 sc->sc_tmds_pll[j].rtp_pll)); 1758 } 1759 return 0; 1760 } 1761 1762 return -1; 1763 } 1764 1765 const struct videomode * 1766 radeonfb_modelookup(const char *name) 1767 { 1768 int i; 1769 1770 for (i = 0; i < videomode_count; i++) 1771 if (!strcmp(name, videomode_list[i].name)) 1772 return &videomode_list[i]; 1773 1774 return NULL; 1775 } 1776 1777 void 1778 radeonfb_pllwriteupdate(struct radeonfb_softc *sc, int crtc) 1779 { 1780 if (crtc) { 1781 while (GETPLL(sc, RADEON_P2PLL_REF_DIV) & 1782 RADEON_P2PLL_ATOMIC_UPDATE_R); 1783 SETPLL(sc, RADEON_P2PLL_REF_DIV, RADEON_P2PLL_ATOMIC_UPDATE_W); 1784 } else { 1785 while (GETPLL(sc, RADEON_PPLL_REF_DIV) & 1786 RADEON_PPLL_ATOMIC_UPDATE_R); 1787 SETPLL(sc, RADEON_PPLL_REF_DIV, RADEON_PPLL_ATOMIC_UPDATE_W); 1788 } 1789 } 1790 1791 void 1792 radeonfb_pllwaitatomicread(struct radeonfb_softc *sc, int crtc) 1793 { 1794 int i; 1795 1796 for (i = 10000; i; i--) { 1797 if (crtc) { 1798 if (GETPLL(sc, RADEON_P2PLL_REF_DIV) & 1799 RADEON_P2PLL_ATOMIC_UPDATE_R) 1800 break; 1801 } else { 1802 if (GETPLL(sc, RADEON_PPLL_REF_DIV) & 1803 RADEON_PPLL_ATOMIC_UPDATE_R) 1804 break; 1805 } 1806 } 1807 } 1808 1809 void 1810 radeonfb_program_vclk(struct radeonfb_softc *sc, int dotclock, int crtc) 1811 { 1812 uint32_t pbit = 0; 1813 uint32_t feed = 0; 1814 uint32_t data; 1815 #if 1 1816 int i; 1817 #endif 1818 1819 radeonfb_calc_dividers(sc, dotclock, &pbit, &feed); 1820 1821 if (crtc == 0) { 1822 1823 /* XXXX: mobility workaround missing */ 1824 /* XXXX: R300 stuff missing */ 1825 1826 PATCHPLL(sc, RADEON_VCLK_ECP_CNTL, 1827 RADEON_VCLK_SRC_SEL_CPUCLK, 1828 ~RADEON_VCLK_SRC_SEL_MASK); 1829 1830 /* put vclk into reset, use atomic updates */ 1831 SETPLL(sc, RADEON_PPLL_CNTL, 1832 RADEON_PPLL_REFCLK_SEL | 1833 RADEON_PPLL_FBCLK_SEL | 1834 RADEON_PPLL_RESET | 1835 RADEON_PPLL_ATOMIC_UPDATE_EN | 1836 RADEON_PPLL_VGA_ATOMIC_UPDATE_EN); 1837 1838 /* select clock 3 */ 1839 #if 0 1840 PATCH32(sc, RADEON_CLOCK_CNTL_INDEX, RADEON_PLL_DIV_SEL, 1841 ~RADEON_PLL_DIV_SEL); 1842 #else 1843 PATCH32(sc, RADEON_CLOCK_CNTL_INDEX, 0, 1844 ~RADEON_PLL_DIV_SEL); 1845 #endif 1846 1847 /* XXX: R300 family -- program divider differently? */ 1848 1849 /* program reference divider */ 1850 PATCHPLL(sc, RADEON_PPLL_REF_DIV, sc->sc_refdiv, 1851 ~RADEON_PPLL_REF_DIV_MASK); 1852 PRINTPLL(RADEON_PPLL_REF_DIV); 1853 1854 #if 0 1855 data = GETPLL(sc, RADEON_PPLL_DIV_3); 1856 data &= ~(RADEON_PPLL_FB3_DIV_MASK | 1857 RADEON_PPLL_POST3_DIV_MASK); 1858 data |= pbit; 1859 data |= (feed & RADEON_PPLL_FB3_DIV_MASK); 1860 PUTPLL(sc, RADEON_PPLL_DIV_3, data); 1861 #else 1862 for (i = 0; i < 4; i++) { 1863 } 1864 #endif 1865 1866 /* use the atomic update */ 1867 radeonfb_pllwriteupdate(sc, crtc); 1868 1869 /* and wait for it to complete */ 1870 radeonfb_pllwaitatomicread(sc, crtc); 1871 1872 /* program HTOTAL (why?) */ 1873 PUTPLL(sc, RADEON_HTOTAL_CNTL, 0); 1874 1875 /* drop reset */ 1876 CLRPLL(sc, RADEON_PPLL_CNTL, 1877 RADEON_PPLL_RESET | RADEON_PPLL_SLEEP | 1878 RADEON_PPLL_ATOMIC_UPDATE_EN | 1879 RADEON_PPLL_VGA_ATOMIC_UPDATE_EN); 1880 1881 PRINTPLL(RADEON_PPLL_CNTL); 1882 1883 /* give clock time to lock */ 1884 delay(50000); 1885 1886 PATCHPLL(sc, RADEON_VCLK_ECP_CNTL, 1887 RADEON_VCLK_SRC_SEL_PPLLCLK, 1888 ~RADEON_VCLK_SRC_SEL_MASK); 1889 1890 } else { 1891 1892 PATCHPLL(sc, RADEON_PIXCLKS_CNTL, 1893 RADEON_PIX2CLK_SRC_SEL_CPUCLK, 1894 ~RADEON_PIX2CLK_SRC_SEL_MASK); 1895 1896 /* put vclk into reset, use atomic updates */ 1897 SETPLL(sc, RADEON_P2PLL_CNTL, 1898 RADEON_P2PLL_RESET | 1899 RADEON_P2PLL_ATOMIC_UPDATE_EN | 1900 RADEON_P2PLL_VGA_ATOMIC_UPDATE_EN); 1901 1902 /* XXX: R300 family -- program divider differently? */ 1903 1904 /* program reference divider */ 1905 PATCHPLL(sc, RADEON_P2PLL_REF_DIV, sc->sc_refdiv, 1906 ~RADEON_P2PLL_REF_DIV_MASK); 1907 1908 /* program feedback and post dividers */ 1909 data = GETPLL(sc, RADEON_P2PLL_DIV_0); 1910 data &= ~(RADEON_P2PLL_FB0_DIV_MASK | 1911 RADEON_P2PLL_POST0_DIV_MASK); 1912 data |= pbit; 1913 data |= (feed & RADEON_P2PLL_FB0_DIV_MASK); 1914 PUTPLL(sc, RADEON_P2PLL_DIV_0, data); 1915 1916 /* use the atomic update */ 1917 radeonfb_pllwriteupdate(sc, crtc); 1918 1919 /* and wait for it to complete */ 1920 radeonfb_pllwaitatomicread(sc, crtc); 1921 1922 /* program HTOTAL (why?) */ 1923 PUTPLL(sc, RADEON_HTOTAL2_CNTL, 0); 1924 1925 /* drop reset */ 1926 CLRPLL(sc, RADEON_P2PLL_CNTL, 1927 RADEON_P2PLL_RESET | RADEON_P2PLL_SLEEP | 1928 RADEON_P2PLL_ATOMIC_UPDATE_EN | 1929 RADEON_P2PLL_VGA_ATOMIC_UPDATE_EN); 1930 1931 /* allow time for clock to lock */ 1932 delay(50000); 1933 1934 PATCHPLL(sc, RADEON_PIXCLKS_CNTL, 1935 RADEON_PIX2CLK_SRC_SEL_P2PLLCLK, 1936 ~RADEON_PIX2CLK_SRC_SEL_MASK); 1937 } 1938 PRINTREG(RADEON_CRTC_MORE_CNTL); 1939 } 1940 1941 void 1942 radeonfb_modeswitch(struct radeonfb_display *dp) 1943 { 1944 struct radeonfb_softc *sc = dp->rd_softc; 1945 int i; 1946 1947 /* blank the display while we switch modes */ 1948 radeonfb_blank(dp, 1); 1949 1950 #if 0 1951 SET32(sc, RADEON_CRTC_EXT_CNTL, 1952 RADEON_CRTC_VSYNC_DIS | RADEON_CRTC_HSYNC_DIS | 1953 RADEON_CRTC_DISPLAY_DIS /* | RADEON_CRTC_DISP_REQ_EN_B */); 1954 #endif 1955 1956 /* these registers might get in the way... */ 1957 PUT32(sc, RADEON_OVR_CLR, 0); 1958 PUT32(sc, RADEON_OVR_WID_LEFT_RIGHT, 0); 1959 PUT32(sc, RADEON_OVR_WID_TOP_BOTTOM, 0); 1960 PUT32(sc, RADEON_OV0_SCALE_CNTL, 0); 1961 PUT32(sc, RADEON_SUBPIC_CNTL, 0); 1962 PUT32(sc, RADEON_VIPH_CONTROL, 0); 1963 PUT32(sc, RADEON_I2C_CNTL_1, 0); 1964 PUT32(sc, RADEON_GEN_INT_CNTL, 0); 1965 PUT32(sc, RADEON_CAP0_TRIG_CNTL, 0); 1966 PUT32(sc, RADEON_CAP1_TRIG_CNTL, 0); 1967 PUT32(sc, RADEON_SURFACE_CNTL, 0); 1968 1969 for (i = 0; i < dp->rd_ncrtcs; i++) 1970 radeonfb_setcrtc(dp, i); 1971 1972 /* activate the display */ 1973 radeonfb_blank(dp, 0); 1974 } 1975 1976 void 1977 radeonfb_setcrtc(struct radeonfb_display *dp, int index) 1978 { 1979 int crtc; 1980 struct videomode *mode; 1981 struct radeonfb_softc *sc; 1982 struct radeonfb_crtc *cp; 1983 uint32_t v; 1984 uint32_t gencntl; 1985 uint32_t htotaldisp; 1986 uint32_t hsyncstrt; 1987 uint32_t vtotaldisp; 1988 uint32_t vsyncstrt; 1989 uint32_t fphsyncstrt; 1990 uint32_t fpvsyncstrt; 1991 uint32_t fphtotaldisp; 1992 uint32_t fpvtotaldisp; 1993 uint32_t pitch; 1994 1995 sc = dp->rd_softc; 1996 cp = &dp->rd_crtcs[index]; 1997 crtc = cp->rc_number; 1998 mode = &cp->rc_videomode; 1999 2000 #if 1 2001 pitch = (((dp->rd_virtx * dp->rd_bpp) + ((dp->rd_bpp * 8) - 1)) / 2002 (dp->rd_bpp * 8)); 2003 #else 2004 pitch = (((sc->sc_maxx * sc->sc_maxbpp) + ((sc->sc_maxbpp * 8) - 1)) / 2005 (sc->sc_maxbpp * 8)); 2006 #endif 2007 2008 switch (crtc) { 2009 case 0: 2010 gencntl = RADEON_CRTC_GEN_CNTL; 2011 htotaldisp = RADEON_CRTC_H_TOTAL_DISP; 2012 hsyncstrt = RADEON_CRTC_H_SYNC_STRT_WID; 2013 vtotaldisp = RADEON_CRTC_V_TOTAL_DISP; 2014 vsyncstrt = RADEON_CRTC_V_SYNC_STRT_WID; 2015 fpvsyncstrt = RADEON_FP_V_SYNC_STRT_WID; 2016 fphsyncstrt = RADEON_FP_H_SYNC_STRT_WID; 2017 fpvtotaldisp = RADEON_FP_CRTC_V_TOTAL_DISP; 2018 fphtotaldisp = RADEON_FP_CRTC_H_TOTAL_DISP; 2019 break; 2020 case 1: 2021 gencntl = RADEON_CRTC2_GEN_CNTL; 2022 htotaldisp = RADEON_CRTC2_H_TOTAL_DISP; 2023 hsyncstrt = RADEON_CRTC2_H_SYNC_STRT_WID; 2024 vtotaldisp = RADEON_CRTC2_V_TOTAL_DISP; 2025 vsyncstrt = RADEON_CRTC2_V_SYNC_STRT_WID; 2026 fpvsyncstrt = RADEON_FP_V2_SYNC_STRT_WID; 2027 fphsyncstrt = RADEON_FP_H2_SYNC_STRT_WID; 2028 fpvtotaldisp = RADEON_FP_CRTC2_V_TOTAL_DISP; 2029 fphtotaldisp = RADEON_FP_CRTC2_H_TOTAL_DISP; 2030 break; 2031 default: 2032 panic("Bad CRTC!"); 2033 break; 2034 } 2035 2036 /* 2037 * CRTC_GEN_CNTL - depth, accelerator mode, etc. 2038 */ 2039 /* only bother with 32bpp and 8bpp */ 2040 v = dp->rd_format << RADEON_CRTC_PIX_WIDTH_SHIFT; 2041 2042 if (crtc == 1) { 2043 v |= RADEON_CRTC2_CRT2_ON | RADEON_CRTC2_EN; 2044 } else { 2045 v |= RADEON_CRTC_EXT_DISP_EN | RADEON_CRTC_EN; 2046 } 2047 2048 if (mode->flags & VID_DBLSCAN) 2049 v |= RADEON_CRTC2_DBL_SCAN_EN; 2050 2051 if (mode->flags & VID_INTERLACE) 2052 v |= RADEON_CRTC2_INTERLACE_EN; 2053 2054 if (mode->flags & VID_CSYNC) { 2055 v |= RADEON_CRTC2_CSYNC_EN; 2056 if (crtc == 1) 2057 v |= RADEON_CRTC2_VSYNC_TRISTAT; 2058 } 2059 2060 PUT32(sc, gencntl, v); 2061 DPRINTF(("CRTC%s_GEN_CNTL = %08x\n", crtc ? "2" : "", v)); 2062 2063 /* 2064 * CRTC_EXT_CNTL - preserve disable flags, set ATI linear and EXT_CNT 2065 */ 2066 v = GET32(sc, RADEON_CRTC_EXT_CNTL); 2067 if (crtc == 0) { 2068 v &= (RADEON_CRTC_VSYNC_DIS | RADEON_CRTC_HSYNC_DIS | 2069 RADEON_CRTC_DISPLAY_DIS); 2070 v |= RADEON_XCRT_CNT_EN | RADEON_VGA_ATI_LINEAR; 2071 if (mode->flags & VID_CSYNC) 2072 v |= RADEON_CRTC_VSYNC_TRISTAT; 2073 } 2074 /* unconditional turn on CRT, in case first CRTC is DFP */ 2075 v |= RADEON_CRTC_CRT_ON; 2076 PUT32(sc, RADEON_CRTC_EXT_CNTL, v); 2077 PRINTREG(RADEON_CRTC_EXT_CNTL); 2078 2079 /* 2080 * H_TOTAL_DISP 2081 */ 2082 v = ((mode->hdisplay / 8) - 1) << 16; 2083 v |= (mode->htotal / 8) - 1; 2084 PUT32(sc, htotaldisp, v); 2085 DPRINTF(("CRTC%s_H_TOTAL_DISP = %08x\n", crtc ? "2" : "", v)); 2086 PUT32(sc, fphtotaldisp, v); 2087 DPRINTF(("FP_H%s_TOTAL_DISP = %08x\n", crtc ? "2" : "", v)); 2088 2089 /* 2090 * H_SYNC_STRT_WID 2091 */ 2092 v = (((mode->hsync_end - mode->hsync_start) / 8) << 16); 2093 v |= mode->hsync_start; 2094 if (mode->flags & VID_NHSYNC) 2095 v |= RADEON_CRTC_H_SYNC_POL; 2096 PUT32(sc, hsyncstrt, v); 2097 DPRINTF(("CRTC%s_H_SYNC_STRT_WID = %08x\n", crtc ? "2" : "", v)); 2098 PUT32(sc, fphsyncstrt, v); 2099 DPRINTF(("FP_H%s_SYNC_STRT_WID = %08x\n", crtc ? "2" : "", v)); 2100 2101 /* 2102 * V_TOTAL_DISP 2103 */ 2104 v = ((mode->vdisplay - 1) << 16); 2105 v |= (mode->vtotal - 1); 2106 PUT32(sc, vtotaldisp, v); 2107 DPRINTF(("CRTC%s_V_TOTAL_DISP = %08x\n", crtc ? "2" : "", v)); 2108 PUT32(sc, fpvtotaldisp, v); 2109 DPRINTF(("FP_V%s_TOTAL_DISP = %08x\n", crtc ? "2" : "", v)); 2110 2111 /* 2112 * V_SYNC_STRT_WID 2113 */ 2114 v = ((mode->vsync_end - mode->vsync_start) << 16); 2115 v |= (mode->vsync_start - 1); 2116 if (mode->flags & VID_NVSYNC) 2117 v |= RADEON_CRTC_V_SYNC_POL; 2118 PUT32(sc, vsyncstrt, v); 2119 DPRINTF(("CRTC%s_V_SYNC_STRT_WID = %08x\n", crtc ? "2" : "", v)); 2120 PUT32(sc, fpvsyncstrt, v); 2121 DPRINTF(("FP_V%s_SYNC_STRT_WID = %08x\n", crtc ? "2" : "", v)); 2122 2123 radeonfb_program_vclk(sc, mode->dot_clock, crtc); 2124 2125 switch (crtc) { 2126 case 0: 2127 PUT32(sc, RADEON_CRTC_OFFSET, 0); 2128 PUT32(sc, RADEON_CRTC_OFFSET_CNTL, 0); 2129 PUT32(sc, RADEON_CRTC_PITCH, pitch); 2130 CLR32(sc, RADEON_DISP_MERGE_CNTL, RADEON_DISP_RGB_OFFSET_EN); 2131 2132 CLR32(sc, RADEON_CRTC_EXT_CNTL, 2133 RADEON_CRTC_VSYNC_DIS | RADEON_CRTC_HSYNC_DIS | 2134 RADEON_CRTC_DISPLAY_DIS /* | RADEON_CRTC_DISP_REQ_EN_B */); 2135 CLR32(sc, RADEON_CRTC_GEN_CNTL, RADEON_CRTC_DISP_REQ_EN_B); 2136 PRINTREG(RADEON_CRTC_EXT_CNTL); 2137 PRINTREG(RADEON_CRTC_GEN_CNTL); 2138 PRINTREG(RADEON_CLOCK_CNTL_INDEX); 2139 break; 2140 2141 case 1: 2142 PUT32(sc, RADEON_CRTC2_OFFSET, 0); 2143 PUT32(sc, RADEON_CRTC2_OFFSET_CNTL, 0); 2144 PUT32(sc, RADEON_CRTC2_PITCH, pitch); 2145 CLR32(sc, RADEON_DISP2_MERGE_CNTL, RADEON_DISP2_RGB_OFFSET_EN); 2146 CLR32(sc, RADEON_CRTC2_GEN_CNTL, 2147 RADEON_CRTC2_VSYNC_DIS | 2148 RADEON_CRTC2_HSYNC_DIS | 2149 RADEON_CRTC2_DISP_DIS | RADEON_CRTC2_DISP_REQ_EN_B); 2150 PRINTREG(RADEON_CRTC2_GEN_CNTL); 2151 break; 2152 } 2153 } 2154 2155 int 2156 radeonfb_isblank(struct radeonfb_display *dp) 2157 { 2158 uint32_t reg, mask; 2159 2160 if (dp->rd_crtcs[0].rc_number) { 2161 reg = RADEON_CRTC2_GEN_CNTL; 2162 mask = RADEON_CRTC2_DISP_DIS; 2163 } else { 2164 reg = RADEON_CRTC_EXT_CNTL; 2165 mask = RADEON_CRTC_DISPLAY_DIS; 2166 } 2167 return ((GET32(dp->rd_softc, reg) & mask) ? 1 : 0); 2168 } 2169 2170 void 2171 radeonfb_blank(struct radeonfb_display *dp, int blank) 2172 { 2173 struct radeonfb_softc *sc = dp->rd_softc; 2174 uint32_t reg, mask; 2175 uint32_t fpreg, fpval; 2176 int i; 2177 2178 for (i = 0; i < dp->rd_ncrtcs; i++) { 2179 2180 if (dp->rd_crtcs[i].rc_number) { 2181 reg = RADEON_CRTC2_GEN_CNTL; 2182 mask = RADEON_CRTC2_DISP_DIS; 2183 fpreg = RADEON_FP2_GEN_CNTL; 2184 fpval = RADEON_FP2_ON; 2185 } else { 2186 reg = RADEON_CRTC_EXT_CNTL; 2187 mask = RADEON_CRTC_DISPLAY_DIS; 2188 fpreg = RADEON_FP_GEN_CNTL; 2189 fpval = RADEON_FP_FPON; 2190 } 2191 2192 if (blank) { 2193 SET32(sc, reg, mask); 2194 CLR32(sc, fpreg, fpval); 2195 } else { 2196 CLR32(sc, reg, mask); 2197 SET32(sc, fpreg, fpval); 2198 } 2199 } 2200 PRINTREG(RADEON_FP_GEN_CNTL); 2201 PRINTREG(RADEON_FP2_GEN_CNTL); 2202 } 2203 2204 void 2205 radeonfb_init_screen(void *cookie, struct vcons_screen *scr, int existing, 2206 long *defattr) 2207 { 2208 struct radeonfb_display *dp = cookie; 2209 struct rasops_info *ri = &scr->scr_ri; 2210 2211 /* initialize font subsystem */ 2212 wsfont_init(); 2213 2214 DPRINTF(("init screen called, existing %d\n", existing)); 2215 2216 ri->ri_depth = dp->rd_bpp; 2217 ri->ri_width = dp->rd_virtx; 2218 ri->ri_height = dp->rd_virty; 2219 ri->ri_stride = dp->rd_stride; 2220 ri->ri_flg = RI_CENTER; 2221 if (ri->ri_depth == 32) { 2222 ri->ri_flg |= RI_ENABLE_ALPHA; 2223 } 2224 if (ri->ri_depth == 8) { 2225 ri->ri_flg |= RI_ENABLE_ALPHA | RI_8BIT_IS_RGB; 2226 } 2227 ri->ri_bits = (void *)dp->rd_fbptr; 2228 2229 #ifdef VCONS_DRAW_INTR 2230 scr->scr_flags |= VCONS_DONT_READ; 2231 #endif 2232 2233 /* this is rgb in "big-endian order..." */ 2234 ri->ri_rnum = 8; 2235 ri->ri_gnum = 8; 2236 ri->ri_bnum = 8; 2237 ri->ri_rpos = 16; 2238 ri->ri_gpos = 8; 2239 ri->ri_bpos = 0; 2240 2241 if (existing) { 2242 ri->ri_flg |= RI_CLEAR; 2243 2244 /* start a modeswitch now */ 2245 radeonfb_modeswitch(dp); 2246 } 2247 2248 /* 2249 * XXX: font selection should be based on properties, with some 2250 * normal/reasonable default. 2251 */ 2252 2253 /* initialize and look for an initial font */ 2254 rasops_init(ri, 0, 0); 2255 ri->ri_caps = WSSCREEN_WSCOLORS; 2256 2257 rasops_reconfig(ri, dp->rd_virty / ri->ri_font->fontheight, 2258 dp->rd_virtx / ri->ri_font->fontwidth); 2259 2260 /* enable acceleration */ 2261 dp->rd_putchar = ri->ri_ops.putchar; 2262 ri->ri_ops.copyrows = radeonfb_copyrows; 2263 ri->ri_ops.copycols = radeonfb_copycols; 2264 ri->ri_ops.eraserows = radeonfb_eraserows; 2265 ri->ri_ops.erasecols = radeonfb_erasecols; 2266 /* pick a putchar method based on font and Radeon model */ 2267 if (ri->ri_font->stride < ri->ri_font->fontwidth) { 2268 /* got a bitmap font */ 2269 if (IS_R300(dp->rd_softc)) { 2270 /* 2271 * radeonfb_putchar() doesn't work right on some R3xx 2272 * so we use software drawing here, the wrapper just 2273 * makes sure the engine is idle before scribbling 2274 * into vram 2275 */ 2276 ri->ri_ops.putchar = radeonfb_putchar_wrapper; 2277 } else { 2278 ri->ri_ops.putchar = radeonfb_putchar; 2279 } 2280 } else { 2281 /* got an alpha font */ 2282 switch(ri->ri_depth) { 2283 case 32: 2284 ri->ri_ops.putchar = radeonfb_putchar_aa32; 2285 break; 2286 case 8: 2287 ri->ri_ops.putchar = radeonfb_putchar_aa8; 2288 break; 2289 default: 2290 /* XXX this should never happen */ 2291 panic("%s: depth is not 8 or 32 but we got an alpha font?!", 2292 __func__); 2293 } 2294 } 2295 ri->ri_ops.cursor = radeonfb_cursor; 2296 } 2297 2298 void 2299 radeonfb_set_fbloc(struct radeonfb_softc *sc) 2300 { 2301 uint32_t gen, ext, gen2 = 0; 2302 uint32_t agploc, aperbase, apersize, mcfbloc; 2303 2304 gen = GET32(sc, RADEON_CRTC_GEN_CNTL); 2305 ext = GET32(sc, RADEON_CRTC_EXT_CNTL); 2306 agploc = GET32(sc, RADEON_MC_AGP_LOCATION); 2307 aperbase = GET32(sc, RADEON_CONFIG_APER_0_BASE); 2308 apersize = GET32(sc, RADEON_CONFIG_APER_SIZE); 2309 2310 PUT32(sc, RADEON_CRTC_GEN_CNTL, gen | RADEON_CRTC_DISP_REQ_EN_B); 2311 PUT32(sc, RADEON_CRTC_EXT_CNTL, ext | RADEON_CRTC_DISPLAY_DIS); 2312 //PUT32(sc, RADEON_CRTC_GEN_CNTL, gen | RADEON_CRTC_DISPLAY_DIS); 2313 //PUT32(sc, RADEON_CRTC_EXT_CNTL, ext | RADEON_CRTC_DISP_REQ_EN_B); 2314 2315 if (HAS_CRTC2(sc)) { 2316 gen2 = GET32(sc, RADEON_CRTC2_GEN_CNTL); 2317 PUT32(sc, RADEON_CRTC2_GEN_CNTL, 2318 gen2 | RADEON_CRTC2_DISP_REQ_EN_B); 2319 } 2320 2321 delay(100000); 2322 2323 mcfbloc = (aperbase >> 16) | 2324 ((aperbase + (apersize - 1)) & 0xffff0000); 2325 2326 sc->sc_aperbase = (mcfbloc & 0xffff) << 16; 2327 sc->sc_memsz = apersize; 2328 2329 if (((agploc & 0xffff) << 16) != 2330 ((mcfbloc & 0xffff0000U) + 0x10000)) { 2331 agploc = mcfbloc & 0xffff0000U; 2332 agploc |= ((agploc + 0x10000) >> 16); 2333 } 2334 2335 PUT32(sc, RADEON_HOST_PATH_CNTL, 0); 2336 2337 PUT32(sc, RADEON_MC_FB_LOCATION, mcfbloc); 2338 PUT32(sc, RADEON_MC_AGP_LOCATION, agploc); 2339 2340 DPRINTF(("aperbase = %u\n", aperbase)); 2341 PRINTREG(RADEON_MC_FB_LOCATION); 2342 PRINTREG(RADEON_MC_AGP_LOCATION); 2343 2344 PUT32(sc, RADEON_DISPLAY_BASE_ADDR, sc->sc_aperbase); 2345 2346 if (HAS_CRTC2(sc)) 2347 PUT32(sc, RADEON_DISPLAY2_BASE_ADDR, sc->sc_aperbase); 2348 2349 PUT32(sc, RADEON_OV0_BASE_ADDR, sc->sc_aperbase); 2350 2351 #if 0 2352 /* XXX: what is this AGP garbage? :-) */ 2353 PUT32(sc, RADEON_AGP_CNTL, 0x00100000); 2354 #endif 2355 2356 delay(100000); 2357 2358 PUT32(sc, RADEON_CRTC_GEN_CNTL, gen); 2359 PUT32(sc, RADEON_CRTC_EXT_CNTL, ext); 2360 2361 if (HAS_CRTC2(sc)) 2362 PUT32(sc, RADEON_CRTC2_GEN_CNTL, gen2); 2363 } 2364 2365 void 2366 radeonfb_init_misc(struct radeonfb_softc *sc) 2367 { 2368 PUT32(sc, RADEON_BUS_CNTL, 2369 RADEON_BUS_MASTER_DIS | 2370 RADEON_BUS_PREFETCH_MODE_ACT | 2371 RADEON_BUS_PCI_READ_RETRY_EN | 2372 RADEON_BUS_PCI_WRT_RETRY_EN | 2373 (3 << RADEON_BUS_RETRY_WS_SHIFT) | 2374 RADEON_BUS_MSTR_RD_MULT | 2375 RADEON_BUS_MSTR_RD_LINE | 2376 RADEON_BUS_RD_DISCARD_EN | 2377 RADEON_BUS_MSTR_DISCONNECT_EN | 2378 RADEON_BUS_READ_BURST); 2379 2380 PUT32(sc, RADEON_BUS_CNTL1, 0xf0); 2381 /* PUT32(sc, RADEON_SEPROM_CNTL1, 0x09ff0000); */ 2382 PUT32(sc, RADEON_FCP_CNTL, RADEON_FCP0_SRC_GND); 2383 PUT32(sc, RADEON_RBBM_CNTL, 2384 (3 << RADEON_RB_SETTLE_SHIFT) | 2385 (4 << RADEON_ABORTCLKS_HI_SHIFT) | 2386 (4 << RADEON_ABORTCLKS_CP_SHIFT) | 2387 (4 << RADEON_ABORTCLKS_CFIFO_SHIFT)); 2388 2389 /* XXX: figure out what these mean! */ 2390 PUT32(sc, RADEON_AGP_CNTL, 0x00100000); 2391 PUT32(sc, RADEON_HOST_PATH_CNTL, 0); 2392 //PUT32(sc, RADEON_DISP_MISC_CNTL, 0x5bb00400); 2393 2394 PUT32(sc, RADEON_GEN_INT_CNTL, 0); 2395 PUT32(sc, RADEON_GEN_INT_STATUS, GET32(sc, RADEON_GEN_INT_STATUS)); 2396 } 2397 2398 /* 2399 * This loads a linear color map for true color. 2400 */ 2401 void 2402 radeonfb_init_palette(struct radeonfb_softc *sc, int crtc) 2403 { 2404 int i; 2405 uint32_t vclk; 2406 2407 #define DAC_WIDTH ((1 << 10) - 1) 2408 #define CLUT_WIDTH ((1 << 8) - 1) 2409 #define CLUT_COLOR(i) ((i * DAC_WIDTH * 2 / CLUT_WIDTH + 1) / 2) 2410 2411 vclk = GETPLL(sc, RADEON_VCLK_ECP_CNTL); 2412 PUTPLL(sc, RADEON_VCLK_ECP_CNTL, vclk & ~RADEON_PIXCLK_DAC_ALWAYS_ONb); 2413 2414 if (crtc) 2415 SET32(sc, RADEON_DAC_CNTL2, RADEON_DAC2_PALETTE_ACC_CTL); 2416 else 2417 CLR32(sc, RADEON_DAC_CNTL2, RADEON_DAC2_PALETTE_ACC_CTL); 2418 2419 PUT32(sc, RADEON_PALETTE_INDEX, 0); 2420 if (sc->sc_displays[crtc].rd_bpp == 0) 2421 sc->sc_displays[crtc].rd_bpp = RADEONFB_DEFAULT_DEPTH; 2422 2423 if (sc->sc_displays[crtc].rd_bpp == 8) { 2424 /* ANSI palette */ 2425 int j = 0; 2426 uint32_t tmp, r, g, b; 2427 2428 for (i = 0; i <= CLUT_WIDTH; ++i) { 2429 tmp = i & 0xe0; 2430 /* 2431 * replicate bits so 0xe0 maps to a red value of 0xff 2432 * in order to make white look actually white 2433 */ 2434 tmp |= (tmp >> 3) | (tmp >> 6); 2435 r = tmp; 2436 2437 tmp = (i & 0x1c) << 3; 2438 tmp |= (tmp >> 3) | (tmp >> 6); 2439 g = tmp; 2440 2441 tmp = (i & 0x03) << 6; 2442 tmp |= tmp >> 2; 2443 tmp |= tmp >> 4; 2444 b = tmp; 2445 PUT32(sc, RADEON_PALETTE_30_DATA, 2446 (r << 22) | 2447 (g << 12) | 2448 (b << 2)); 2449 j += 3; 2450 } 2451 } else { 2452 /* linear ramp */ 2453 for (i = 0; i <= CLUT_WIDTH; ++i) { 2454 PUT32(sc, RADEON_PALETTE_30_DATA, 2455 (CLUT_COLOR(i) << 10) | 2456 (CLUT_COLOR(i) << 20) | 2457 (CLUT_COLOR(i))); 2458 } 2459 } 2460 2461 CLR32(sc, RADEON_DAC_CNTL2, RADEON_DAC2_PALETTE_ACC_CTL); 2462 PRINTREG(RADEON_DAC_CNTL2); 2463 2464 PUTPLL(sc, RADEON_VCLK_ECP_CNTL, vclk); 2465 } 2466 2467 /* 2468 * Bugs in some R300 hardware requires this when accessing CLOCK_CNTL_INDEX. 2469 */ 2470 void 2471 radeonfb_r300cg_workaround(struct radeonfb_softc *sc) 2472 { 2473 uint32_t tmp, save; 2474 2475 save = GET32(sc, RADEON_CLOCK_CNTL_INDEX); 2476 tmp = save & ~(0x3f | RADEON_PLL_WR_EN); 2477 PUT32(sc, RADEON_CLOCK_CNTL_INDEX, tmp); 2478 tmp = GET32(sc, RADEON_CLOCK_CNTL_DATA); 2479 PUT32(sc, RADEON_CLOCK_CNTL_INDEX, save); 2480 } 2481 2482 /* 2483 * Acceleration entry points. 2484 */ 2485 2486 /* this one draws characters using bitmap fonts */ 2487 static void 2488 radeonfb_putchar(void *cookie, int row, int col, u_int c, long attr) 2489 { 2490 struct rasops_info *ri = cookie; 2491 struct vcons_screen *scr = ri->ri_hw; 2492 struct radeonfb_display *dp = scr->scr_cookie; 2493 struct radeonfb_softc *sc = dp->rd_softc; 2494 struct wsdisplay_font *font = PICK_FONT(ri, c); 2495 uint32_t w, h; 2496 int xd, yd, offset, i; 2497 uint32_t bg, fg, gmc; 2498 uint32_t reg; 2499 uint8_t *data8; 2500 uint16_t *data16; 2501 void *data; 2502 2503 if (dp->rd_wsmode != WSDISPLAYIO_MODE_EMUL) 2504 return; 2505 2506 if (!CHAR_IN_FONT(c, font)) 2507 return; 2508 2509 w = font->fontwidth; 2510 h = font->fontheight; 2511 2512 bg = ri->ri_devcmap[(attr >> 16) & 0xf]; 2513 fg = ri->ri_devcmap[(attr >> 24) & 0xf]; 2514 2515 xd = ri->ri_xorigin + col * w; 2516 yd = ri->ri_yorigin + row * h; 2517 2518 if (c == 0x20) { 2519 radeonfb_rectfill(dp, xd, yd, w, h, bg); 2520 return; 2521 } 2522 data = WSFONT_GLYPH(c, font); 2523 2524 gmc = dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT; 2525 2526 radeonfb_wait_fifo(sc, 9); 2527 2528 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 2529 RADEON_GMC_BRUSH_NONE | 2530 RADEON_GMC_SRC_DATATYPE_MONO_FG_BG | 2531 RADEON_GMC_DST_CLIPPING | 2532 RADEON_ROP3_S | 2533 RADEON_DP_SRC_SOURCE_HOST_DATA | 2534 RADEON_GMC_CLR_CMP_CNTL_DIS | 2535 RADEON_GMC_WR_MSK_DIS | 2536 gmc); 2537 2538 PUT32(sc, RADEON_SC_LEFT, xd); 2539 PUT32(sc, RADEON_SC_RIGHT, xd + w); 2540 PUT32(sc, RADEON_DP_SRC_FRGD_CLR, fg); 2541 PUT32(sc, RADEON_DP_SRC_BKGD_CLR, bg); 2542 PUT32(sc, RADEON_DP_CNTL, 2543 RADEON_DST_X_LEFT_TO_RIGHT | 2544 RADEON_DST_Y_TOP_TO_BOTTOM); 2545 2546 PUT32(sc, RADEON_SRC_X_Y, 0); 2547 offset = 32 - (font->stride << 3); 2548 PUT32(sc, RADEON_DST_X_Y, ((xd - offset) << 16) | yd); 2549 PUT32(sc, RADEON_DST_WIDTH_HEIGHT, (32 << 16) | h); 2550 2551 radeonfb_wait_fifo(sc, h); 2552 switch (font->stride) { 2553 case 1: { 2554 data8 = data; 2555 for (i = 0; i < h; i++) { 2556 reg = *data8; 2557 bus_space_write_stream_4(sc->sc_regt, 2558 sc->sc_regh, RADEON_HOST_DATA0, reg); 2559 data8++; 2560 } 2561 break; 2562 } 2563 case 2: { 2564 data16 = data; 2565 for (i = 0; i < h; i++) { 2566 reg = *data16; 2567 bus_space_write_stream_4(sc->sc_regt, 2568 sc->sc_regh, RADEON_HOST_DATA0, reg); 2569 data16++; 2570 } 2571 break; 2572 } 2573 } 2574 } 2575 2576 /* ... while this one is for anti-aliased ones */ 2577 static void 2578 radeonfb_putchar_aa32(void *cookie, int row, int col, u_int c, long attr) 2579 { 2580 struct rasops_info *ri = cookie; 2581 struct vcons_screen *scr = ri->ri_hw; 2582 struct radeonfb_display *dp = scr->scr_cookie; 2583 struct radeonfb_softc *sc = dp->rd_softc; 2584 struct wsdisplay_font *font = PICK_FONT(ri, c); 2585 uint32_t bg, fg, gmc; 2586 uint8_t *data; 2587 int w, h, xd, yd; 2588 int i, r, g, b, aval; 2589 int rf, gf, bf, rb, gb, bb; 2590 uint32_t pixel; 2591 int rv; 2592 2593 if (dp->rd_wsmode != WSDISPLAYIO_MODE_EMUL) 2594 return; 2595 2596 if (!CHAR_IN_FONT(c, font)) 2597 return; 2598 2599 w = font->fontwidth; 2600 h = font->fontheight; 2601 2602 bg = ri->ri_devcmap[(attr >> 16) & 0xf]; 2603 fg = ri->ri_devcmap[(attr >> 24) & 0xf]; 2604 2605 xd = ri->ri_xorigin + col * w; 2606 yd = ri->ri_yorigin + row * h; 2607 2608 if (c == 0x20) { 2609 radeonfb_rectfill(dp, xd, yd, w, h, bg); 2610 return; 2611 } 2612 rv = glyphcache_try(&dp->rd_gc, c, xd, yd, attr); 2613 if (rv == GC_OK) 2614 return; 2615 2616 data = WSFONT_GLYPH(c, font); 2617 2618 gmc = dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT; 2619 2620 radeonfb_wait_fifo(sc, 5); 2621 2622 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 2623 RADEON_GMC_BRUSH_NONE | 2624 RADEON_GMC_SRC_DATATYPE_COLOR | 2625 RADEON_ROP3_S | 2626 RADEON_DP_SRC_SOURCE_HOST_DATA | 2627 RADEON_GMC_CLR_CMP_CNTL_DIS | 2628 RADEON_GMC_WR_MSK_DIS | 2629 gmc); 2630 2631 PUT32(sc, RADEON_DP_CNTL, 2632 RADEON_DST_X_LEFT_TO_RIGHT | 2633 RADEON_DST_Y_TOP_TO_BOTTOM); 2634 2635 PUT32(sc, RADEON_SRC_X_Y, 0); 2636 PUT32(sc, RADEON_DST_X_Y, (xd << 16) | yd); 2637 PUT32(sc, RADEON_DST_WIDTH_HEIGHT, (w << 16) | h); 2638 2639 rf = (fg >> 16) & 0xff; 2640 rb = (bg >> 16) & 0xff; 2641 gf = (fg >> 8) & 0xff; 2642 gb = (bg >> 8) & 0xff; 2643 bf = fg & 0xff; 2644 bb = bg & 0xff; 2645 2646 /* 2647 * I doubt we can upload data faster than even the slowest Radeon 2648 * could process them, especially when doing the alpha blending stuff 2649 * along the way, so just make sure there's some room in the FIFO and 2650 * then hammer away 2651 * As it turns out we can, so make periodic stops to let the FIFO 2652 * drain. 2653 */ 2654 radeonfb_wait_fifo(sc, 20); 2655 for (i = 0; i < ri->ri_fontscale; i++) { 2656 aval = *data; 2657 data++; 2658 if (aval == 0) { 2659 pixel = bg; 2660 } else if (aval == 255) { 2661 pixel = fg; 2662 } else { 2663 r = aval * rf + (255 - aval) * rb; 2664 g = aval * gf + (255 - aval) * gb; 2665 b = aval * bf + (255 - aval) * bb; 2666 pixel = (r & 0xff00) << 8 | 2667 (g & 0xff00) | 2668 (b & 0xff00) >> 8; 2669 } 2670 if (i & 16) 2671 radeonfb_wait_fifo(sc, 20); 2672 PUT32(sc, RADEON_HOST_DATA0, pixel); 2673 } 2674 if (rv == GC_ADD) 2675 glyphcache_add(&dp->rd_gc, c, xd, yd); 2676 } 2677 2678 static void 2679 radeonfb_putchar_aa8(void *cookie, int row, int col, u_int c, long attr) 2680 { 2681 struct rasops_info *ri = cookie; 2682 struct vcons_screen *scr = ri->ri_hw; 2683 struct radeonfb_display *dp = scr->scr_cookie; 2684 struct radeonfb_softc *sc = dp->rd_softc; 2685 struct wsdisplay_font *font = PICK_FONT(ri, c); 2686 uint32_t bg, latch = 0, bg8, fg8, pixel, gmc; 2687 int i, x, y, wi, he, r, g, b, aval; 2688 int r1, g1, b1, r0, g0, b0, fgo, bgo; 2689 uint8_t *data8; 2690 int rv, cnt; 2691 2692 if (dp->rd_wsmode != WSDISPLAYIO_MODE_EMUL) 2693 return; 2694 2695 if (!CHAR_IN_FONT(c, font)) 2696 return; 2697 2698 wi = font->fontwidth; 2699 he = font->fontheight; 2700 2701 bg = ri->ri_devcmap[(attr >> 16) & 0xf]; 2702 2703 x = ri->ri_xorigin + col * wi; 2704 y = ri->ri_yorigin + row * he; 2705 2706 if (c == 0x20) { 2707 radeonfb_rectfill(dp, x, y, wi, he, bg); 2708 return; 2709 } 2710 rv = glyphcache_try(&dp->rd_gc, c, x, y, attr); 2711 if (rv == GC_OK) 2712 return; 2713 2714 data8 = WSFONT_GLYPH(c, font); 2715 2716 gmc = dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT; 2717 2718 radeonfb_wait_fifo(sc, 5); 2719 2720 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 2721 RADEON_GMC_BRUSH_NONE | 2722 RADEON_GMC_SRC_DATATYPE_COLOR | 2723 RADEON_ROP3_S | 2724 RADEON_DP_SRC_SOURCE_HOST_DATA | 2725 RADEON_GMC_CLR_CMP_CNTL_DIS | 2726 RADEON_GMC_WR_MSK_DIS | 2727 gmc); 2728 2729 PUT32(sc, RADEON_DP_CNTL, 2730 RADEON_DST_X_LEFT_TO_RIGHT | 2731 RADEON_DST_Y_TOP_TO_BOTTOM); 2732 2733 PUT32(sc, RADEON_SRC_X_Y, 0); 2734 PUT32(sc, RADEON_DST_X_Y, (x << 16) | y); 2735 PUT32(sc, RADEON_DST_WIDTH_HEIGHT, (wi << 16) | he); 2736 2737 /* 2738 * we need the RGB colours here, so get offsets into rasops_cmap 2739 */ 2740 fgo = ((attr >> 24) & 0xf) * 3; 2741 bgo = ((attr >> 16) & 0xf) * 3; 2742 2743 r0 = rasops_cmap[bgo]; 2744 r1 = rasops_cmap[fgo]; 2745 g0 = rasops_cmap[bgo + 1]; 2746 g1 = rasops_cmap[fgo + 1]; 2747 b0 = rasops_cmap[bgo + 2]; 2748 b1 = rasops_cmap[fgo + 2]; 2749 #define R3G3B2(r, g, b) ((r & 0xe0) | ((g >> 3) & 0x1c) | (b >> 6)) 2750 bg8 = R3G3B2(r0, g0, b0); 2751 fg8 = R3G3B2(r1, g1, b1); 2752 2753 radeonfb_wait_fifo(sc, 20); 2754 cnt = 0; 2755 for (i = 0; i < ri->ri_fontscale; i++) { 2756 aval = *data8; 2757 if (aval == 0) { 2758 pixel = bg8; 2759 } else if (aval == 255) { 2760 pixel = fg8; 2761 } else { 2762 r = aval * r1 + (255 - aval) * r0; 2763 g = aval * g1 + (255 - aval) * g0; 2764 b = aval * b1 + (255 - aval) * b0; 2765 pixel = ((r & 0xe000) >> 8) | 2766 ((g & 0xe000) >> 11) | 2767 ((b & 0xc000) >> 14); 2768 } 2769 latch = (latch << 8) | pixel; 2770 /* write in 32bit chunks */ 2771 if ((i & 3) == 3) { 2772 PUT32S(sc, RADEON_HOST_DATA0, latch); 2773 /* 2774 * not strictly necessary, old data should be shifted 2775 * out 2776 */ 2777 latch = 0; 2778 cnt++; 2779 if (cnt > 16) { 2780 cnt = 0; 2781 radeonfb_wait_fifo(sc, 20); 2782 } 2783 } 2784 data8++; 2785 } 2786 /* if we have pixels left in latch write them out */ 2787 if ((i & 3) != 0) { 2788 /* 2789 * radeon is weird - apparently leftover pixels are written 2790 * from the middle, not from the left as everything else 2791 */ 2792 PUT32(sc, RADEON_HOST_DATA0, latch); 2793 } 2794 2795 if (rv == GC_ADD) 2796 glyphcache_add(&dp->rd_gc, c, x, y); 2797 } 2798 2799 /* 2800 * wrapper for software character drawing 2801 * just sync the engine and call rasops*_putchar() 2802 */ 2803 2804 static void 2805 radeonfb_putchar_wrapper(void *cookie, int row, int col, u_int c, long attr) 2806 { 2807 struct rasops_info *ri = cookie; 2808 struct vcons_screen *scr = ri->ri_hw; 2809 struct radeonfb_display *dp = scr->scr_cookie; 2810 2811 radeonfb_engine_idle(dp->rd_softc); 2812 dp->rd_putchar(ri, row, col, c, attr); 2813 } 2814 2815 static void 2816 radeonfb_eraserows(void *cookie, int row, int nrows, long fillattr) 2817 { 2818 struct rasops_info *ri = cookie; 2819 struct vcons_screen *scr = ri->ri_hw; 2820 struct radeonfb_display *dp = scr->scr_cookie; 2821 uint32_t x, y, w, h, fg, bg, ul; 2822 2823 /* XXX: check for full emulation mode? */ 2824 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 2825 x = ri->ri_xorigin; 2826 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 2827 w = ri->ri_emuwidth; 2828 h = ri->ri_font->fontheight * nrows; 2829 2830 rasops_unpack_attr(fillattr, &fg, &bg, &ul); 2831 radeonfb_rectfill(dp, x, y, w, h, ri->ri_devcmap[bg & 0xf]); 2832 } 2833 } 2834 2835 static void 2836 radeonfb_copyrows(void *cookie, int srcrow, int dstrow, int nrows) 2837 { 2838 struct rasops_info *ri = cookie; 2839 struct vcons_screen *scr = ri->ri_hw; 2840 struct radeonfb_display *dp = scr->scr_cookie; 2841 uint32_t x, ys, yd, w, h; 2842 2843 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 2844 x = ri->ri_xorigin; 2845 ys = ri->ri_yorigin + ri->ri_font->fontheight * srcrow; 2846 yd = ri->ri_yorigin + ri->ri_font->fontheight * dstrow; 2847 w = ri->ri_emuwidth; 2848 h = ri->ri_font->fontheight * nrows; 2849 radeonfb_bitblt(dp, x, ys, x, yd, w, h, 2850 RADEON_ROP3_S); 2851 } 2852 } 2853 2854 static void 2855 radeonfb_copycols(void *cookie, int row, int srccol, int dstcol, int ncols) 2856 { 2857 struct rasops_info *ri = cookie; 2858 struct vcons_screen *scr = ri->ri_hw; 2859 struct radeonfb_display *dp = scr->scr_cookie; 2860 uint32_t xs, xd, y, w, h; 2861 2862 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 2863 xs = ri->ri_xorigin + ri->ri_font->fontwidth * srccol; 2864 xd = ri->ri_xorigin + ri->ri_font->fontwidth * dstcol; 2865 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 2866 w = ri->ri_font->fontwidth * ncols; 2867 h = ri->ri_font->fontheight; 2868 radeonfb_bitblt(dp, xs, y, xd, y, w, h, 2869 RADEON_ROP3_S); 2870 } 2871 } 2872 2873 static void 2874 radeonfb_erasecols(void *cookie, int row, int startcol, int ncols, 2875 long fillattr) 2876 { 2877 struct rasops_info *ri = cookie; 2878 struct vcons_screen *scr = ri->ri_hw; 2879 struct radeonfb_display *dp = scr->scr_cookie; 2880 uint32_t x, y, w, h, fg, bg, ul; 2881 2882 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 2883 x = ri->ri_xorigin + ri->ri_font->fontwidth * startcol; 2884 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 2885 w = ri->ri_font->fontwidth * ncols; 2886 h = ri->ri_font->fontheight; 2887 2888 rasops_unpack_attr(fillattr, &fg, &bg, &ul); 2889 radeonfb_rectfill(dp, x, y, w, h, ri->ri_devcmap[bg & 0xf]); 2890 } 2891 } 2892 2893 static void 2894 radeonfb_cursor(void *cookie, int on, int row, int col) 2895 { 2896 struct rasops_info *ri = cookie; 2897 struct vcons_screen *scr = ri->ri_hw; 2898 struct radeonfb_display *dp = scr->scr_cookie; 2899 int x, y, wi, he; 2900 2901 wi = ri->ri_font->fontwidth; 2902 he = ri->ri_font->fontheight; 2903 2904 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 2905 x = ri->ri_ccol * wi + ri->ri_xorigin; 2906 y = ri->ri_crow * he + ri->ri_yorigin; 2907 /* first turn off the old cursor */ 2908 if (ri->ri_flg & RI_CURSOR) { 2909 radeonfb_bitblt(dp, x, y, x, y, wi, he, 2910 RADEON_ROP3_Dn); 2911 ri->ri_flg &= ~RI_CURSOR; 2912 } 2913 ri->ri_crow = row; 2914 ri->ri_ccol = col; 2915 /* then (possibly) turn on the new one */ 2916 if (on) { 2917 x = ri->ri_ccol * wi + ri->ri_xorigin; 2918 y = ri->ri_crow * he + ri->ri_yorigin; 2919 radeonfb_bitblt(dp, x, y, x, y, wi, he, 2920 RADEON_ROP3_Dn); 2921 ri->ri_flg |= RI_CURSOR; 2922 } 2923 } else { 2924 scr->scr_ri.ri_crow = row; 2925 scr->scr_ri.ri_ccol = col; 2926 scr->scr_ri.ri_flg &= ~RI_CURSOR; 2927 } 2928 } 2929 2930 /* 2931 * Underlying acceleration support. 2932 */ 2933 2934 static void 2935 radeonfb_rectfill(struct radeonfb_display *dp, int dstx, int dsty, 2936 int width, int height, uint32_t color) 2937 { 2938 struct radeonfb_softc *sc = dp->rd_softc; 2939 uint32_t gmc; 2940 2941 gmc = dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT; 2942 2943 radeonfb_wait_fifo(sc, 6); 2944 2945 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 2946 RADEON_GMC_BRUSH_SOLID_COLOR | 2947 RADEON_GMC_SRC_DATATYPE_COLOR | 2948 RADEON_GMC_CLR_CMP_CNTL_DIS | 2949 RADEON_ROP3_P | gmc); 2950 2951 PUT32(sc, RADEON_DP_BRUSH_FRGD_CLR, color); 2952 PUT32(sc, RADEON_DP_WRITE_MASK, 0xffffffff); 2953 PUT32(sc, RADEON_DP_CNTL, 2954 RADEON_DST_X_LEFT_TO_RIGHT | 2955 RADEON_DST_Y_TOP_TO_BOTTOM); 2956 PUT32(sc, RADEON_DST_Y_X, (dsty << 16) | dstx); 2957 PUT32(sc, RADEON_DST_WIDTH_HEIGHT, (width << 16) | (height)); 2958 2959 } 2960 2961 static void 2962 radeonfb_bitblt(void *cookie, int srcx, int srcy, 2963 int dstx, int dsty, int width, int height, int rop) 2964 { 2965 struct radeonfb_display *dp = cookie; 2966 struct radeonfb_softc *sc = dp->rd_softc; 2967 uint32_t gmc; 2968 uint32_t dir; 2969 2970 if (dsty < srcy) { 2971 dir = RADEON_DST_Y_TOP_TO_BOTTOM; 2972 } else { 2973 srcy += height - 1; 2974 dsty += height - 1; 2975 dir = 0; 2976 } 2977 if (dstx < srcx) { 2978 dir |= RADEON_DST_X_LEFT_TO_RIGHT; 2979 } else { 2980 srcx += width - 1; 2981 dstx += width - 1; 2982 } 2983 2984 gmc = dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT; 2985 2986 radeonfb_wait_fifo(sc, 6); 2987 2988 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 2989 RADEON_GMC_BRUSH_SOLID_COLOR | 2990 RADEON_GMC_SRC_DATATYPE_COLOR | 2991 RADEON_GMC_CLR_CMP_CNTL_DIS | 2992 RADEON_DP_SRC_SOURCE_MEMORY | 2993 rop | gmc); 2994 2995 PUT32(sc, RADEON_DP_WRITE_MASK, 0xffffffff); 2996 PUT32(sc, RADEON_DP_CNTL, dir); 2997 PUT32(sc, RADEON_SRC_Y_X, (srcy << 16) | srcx); 2998 PUT32(sc, RADEON_DST_Y_X, (dsty << 16) | dstx); 2999 PUT32(sc, RADEON_DST_WIDTH_HEIGHT, (width << 16) | (height)); 3000 } 3001 3002 static void 3003 radeonfb_engine_idle(struct radeonfb_softc *sc) 3004 { 3005 3006 radeonfb_wait_fifo(sc, 64); 3007 while ((GET32(sc, RADEON_RBBM_STATUS) & 3008 RADEON_RBBM_ACTIVE) != 0); 3009 radeonfb_engine_flush(sc); 3010 } 3011 3012 static inline void 3013 radeonfb_wait_fifo(struct radeonfb_softc *sc, int n) 3014 { 3015 int i; 3016 3017 for (i = RADEON_TIMEOUT; i; i--) { 3018 if ((GET32(sc, RADEON_RBBM_STATUS) & 3019 RADEON_RBBM_FIFOCNT_MASK) >= n) 3020 return; 3021 } 3022 #ifdef DIAGNOSTIC 3023 if (!i) 3024 printf("%s: timed out waiting for fifo (%x)\n", 3025 XNAME(sc), GET32(sc, RADEON_RBBM_STATUS)); 3026 #endif 3027 } 3028 3029 static void 3030 radeonfb_engine_flush(struct radeonfb_softc *sc) 3031 { 3032 int i = 0; 3033 3034 if (IS_R300(sc)) { 3035 SET32(sc, R300_DSTCACHE_CTLSTAT, R300_RB2D_DC_FLUSH_ALL); 3036 while (GET32(sc, R300_DSTCACHE_CTLSTAT) & R300_RB2D_DC_BUSY) { 3037 i++; 3038 } 3039 } else { 3040 SET32(sc, RADEON_RB2D_DSTCACHE_CTLSTAT, 3041 RADEON_RB2D_DC_FLUSH_ALL); 3042 while (GET32(sc, RADEON_RB2D_DSTCACHE_CTLSTAT) & 3043 RADEON_RB2D_DC_BUSY) { 3044 i++; 3045 } 3046 } 3047 #ifdef DIAGNOSTIC 3048 if (i > RADEON_TIMEOUT) 3049 printf("%s: engine flush timed out!\n", XNAME(sc)); 3050 #endif 3051 } 3052 3053 static inline void 3054 radeonfb_unclip(struct radeonfb_softc *sc) 3055 { 3056 3057 radeonfb_wait_fifo(sc, 2); 3058 PUT32(sc, RADEON_SC_TOP_LEFT, 0); 3059 PUT32(sc, RADEON_SC_BOTTOM_RIGHT, 0x1fff1fff); 3060 } 3061 3062 static void 3063 radeonfb_engine_init(struct radeonfb_display *dp) 3064 { 3065 struct radeonfb_softc *sc = dp->rd_softc; 3066 uint32_t pitch; 3067 volatile uint32_t junk; 3068 3069 /* no 3D */ 3070 PUT32(sc, RADEON_RB3D_CNTL, 0); 3071 3072 radeonfb_engine_reset(sc); 3073 pitch = ((dp->rd_virtx * (dp->rd_bpp / 8) + 0x3f)) >> 6; 3074 3075 radeonfb_wait_fifo(sc, 1); 3076 if (!IS_R300(sc)) 3077 PUT32(sc, RADEON_RB2D_DSTCACHE_MODE, 0); 3078 3079 radeonfb_wait_fifo(sc, 3); 3080 PUT32(sc, RADEON_DEFAULT_PITCH_OFFSET, 3081 (pitch << 22) | (sc->sc_aperbase >> 10)); 3082 3083 3084 PUT32(sc, RADEON_DST_PITCH_OFFSET, 3085 (pitch << 22) | (sc->sc_aperbase >> 10)); 3086 PUT32(sc, RADEON_SRC_PITCH_OFFSET, 3087 (pitch << 22) | (sc->sc_aperbase >> 10)); 3088 3089 radeonfb_wait_fifo(sc, 1); 3090 #if _BYTE_ORDER == _BIG_ENDIAN 3091 SET32(sc, RADEON_DP_DATATYPE, RADEON_HOST_BIG_ENDIAN_EN); 3092 #else 3093 CLR32(sc, RADEON_DP_DATATYPE, RADEON_HOST_BIG_ENDIAN_EN); 3094 #endif 3095 junk = GET32(sc, RADEON_DP_DATATYPE); 3096 3097 /* default scissors -- no clipping */ 3098 radeonfb_wait_fifo(sc, 1); 3099 PUT32(sc, RADEON_DEFAULT_SC_BOTTOM_RIGHT, 3100 RADEON_DEFAULT_SC_RIGHT_MAX | RADEON_DEFAULT_SC_BOTTOM_MAX); 3101 3102 radeonfb_wait_fifo(sc, 1); 3103 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 3104 (dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT) | 3105 RADEON_GMC_CLR_CMP_CNTL_DIS | 3106 RADEON_GMC_BRUSH_SOLID_COLOR | 3107 RADEON_GMC_SRC_DATATYPE_COLOR); 3108 3109 radeonfb_wait_fifo(sc, 10); 3110 PUT32(sc, RADEON_DST_LINE_START, 0); 3111 PUT32(sc, RADEON_DST_LINE_END, 0); 3112 PUT32(sc, RADEON_DP_BRUSH_FRGD_CLR, 0xffffffff); 3113 PUT32(sc, RADEON_DP_BRUSH_BKGD_CLR, 0); 3114 PUT32(sc, RADEON_DP_SRC_FRGD_CLR, 0xffffffff); 3115 PUT32(sc, RADEON_DP_SRC_BKGD_CLR, 0); 3116 PUT32(sc, RADEON_DP_WRITE_MASK, 0xffffffff); 3117 PUT32(sc, RADEON_SC_TOP_LEFT, 0); 3118 PUT32(sc, RADEON_SC_BOTTOM_RIGHT, 0x1fff1fff); 3119 PUT32(sc, RADEON_AUX_SC_CNTL, 0); 3120 radeonfb_engine_idle(sc); 3121 } 3122 3123 static void 3124 radeonfb_engine_reset(struct radeonfb_softc *sc) 3125 { 3126 uint32_t hpc, rbbm, mclkcntl, clkindex; 3127 3128 radeonfb_engine_flush(sc); 3129 3130 clkindex = GET32(sc, RADEON_CLOCK_CNTL_INDEX); 3131 if (HAS_R300CG(sc)) 3132 radeonfb_r300cg_workaround(sc); 3133 mclkcntl = GETPLL(sc, RADEON_MCLK_CNTL); 3134 3135 /* 3136 * According to comments in XFree code, resetting the HDP via 3137 * the RBBM_SOFT_RESET can cause bad behavior on some systems. 3138 * So we use HOST_PATH_CNTL instead. 3139 */ 3140 3141 hpc = GET32(sc, RADEON_HOST_PATH_CNTL); 3142 rbbm = GET32(sc, RADEON_RBBM_SOFT_RESET); 3143 if (IS_R300(sc)) { 3144 PUT32(sc, RADEON_RBBM_SOFT_RESET, rbbm | 3145 RADEON_SOFT_RESET_CP | 3146 RADEON_SOFT_RESET_HI | 3147 RADEON_SOFT_RESET_E2); 3148 GET32(sc, RADEON_RBBM_SOFT_RESET); 3149 PUT32(sc, RADEON_RBBM_SOFT_RESET, 0); 3150 /* 3151 * XXX: this bit is not defined in any ATI docs I have, 3152 * nor in the XFree code, but XFree does it. Why? 3153 */ 3154 SET32(sc, RADEON_RB2D_DSTCACHE_MODE, (1<<17)); 3155 } else { 3156 PUT32(sc, RADEON_RBBM_SOFT_RESET, rbbm | 3157 RADEON_SOFT_RESET_CP | 3158 RADEON_SOFT_RESET_SE | 3159 RADEON_SOFT_RESET_RE | 3160 RADEON_SOFT_RESET_PP | 3161 RADEON_SOFT_RESET_E2 | 3162 RADEON_SOFT_RESET_RB); 3163 GET32(sc, RADEON_RBBM_SOFT_RESET); 3164 PUT32(sc, RADEON_RBBM_SOFT_RESET, rbbm & 3165 ~(RADEON_SOFT_RESET_CP | 3166 RADEON_SOFT_RESET_SE | 3167 RADEON_SOFT_RESET_RE | 3168 RADEON_SOFT_RESET_PP | 3169 RADEON_SOFT_RESET_E2 | 3170 RADEON_SOFT_RESET_RB)); 3171 GET32(sc, RADEON_RBBM_SOFT_RESET); 3172 } 3173 3174 PUT32(sc, RADEON_HOST_PATH_CNTL, hpc | RADEON_HDP_SOFT_RESET); 3175 GET32(sc, RADEON_HOST_PATH_CNTL); 3176 PUT32(sc, RADEON_HOST_PATH_CNTL, hpc); 3177 3178 if (IS_R300(sc)) 3179 PUT32(sc, RADEON_RBBM_SOFT_RESET, rbbm); 3180 3181 PUT32(sc, RADEON_CLOCK_CNTL_INDEX, clkindex); 3182 PUTPLL(sc, RADEON_MCLK_CNTL, mclkcntl); 3183 3184 if (HAS_R300CG(sc)) 3185 radeonfb_r300cg_workaround(sc); 3186 } 3187 3188 static int 3189 radeonfb_set_curpos(struct radeonfb_display *dp, struct wsdisplay_curpos *pos) 3190 { 3191 int x, y; 3192 3193 x = pos->x; 3194 y = pos->y; 3195 3196 /* 3197 * This doesn't let a cursor move off the screen. I'm not 3198 * sure if this will have negative effects for e.g. Xinerama. 3199 * I'd guess Xinerama handles it by changing the cursor shape, 3200 * but that needs verification. 3201 */ 3202 if (x >= dp->rd_virtx) 3203 x = dp->rd_virtx - 1; 3204 if (x < 0) 3205 x = 0; 3206 if (y >= dp->rd_virty) 3207 y = dp->rd_virty - 1; 3208 if (y < 0) 3209 y = 0; 3210 3211 dp->rd_cursor.rc_pos.x = x; 3212 dp->rd_cursor.rc_pos.y = y; 3213 3214 radeonfb_cursor_position(dp); 3215 return 0; 3216 } 3217 3218 static int 3219 radeonfb_set_cursor(struct radeonfb_display *dp, struct wsdisplay_cursor *wc) 3220 { 3221 unsigned flags; 3222 3223 uint8_t r[2], g[2], b[2]; 3224 unsigned index, count; 3225 int i, err; 3226 int pitch, size; 3227 struct radeonfb_cursor nc; 3228 3229 flags = wc->which; 3230 3231 /* copy old values */ 3232 nc = dp->rd_cursor; 3233 3234 if (flags & WSDISPLAY_CURSOR_DOCMAP) { 3235 index = wc->cmap.index; 3236 count = wc->cmap.count; 3237 3238 if (index >= 2 || (index + count) > 2) 3239 return EINVAL; 3240 3241 err = copyin(wc->cmap.red, &r[index], count); 3242 if (err) 3243 return err; 3244 err = copyin(wc->cmap.green, &g[index], count); 3245 if (err) 3246 return err; 3247 err = copyin(wc->cmap.blue, &b[index], count); 3248 if (err) 3249 return err; 3250 3251 for (i = index; i < index + count; i++) { 3252 nc.rc_cmap[i] = 3253 (r[i] << 16) + (g[i] << 8) + (b[i] << 0); 3254 } 3255 } 3256 3257 if (flags & WSDISPLAY_CURSOR_DOSHAPE) { 3258 if ((wc->size.x > RADEON_CURSORMAXX) || 3259 (wc->size.y > RADEON_CURSORMAXY)) 3260 return EINVAL; 3261 3262 /* figure bytes per line */ 3263 pitch = (wc->size.x + 7) / 8; 3264 size = pitch * wc->size.y; 3265 3266 /* clear the old cursor and mask */ 3267 memset(nc.rc_image, 0, 512); 3268 memset(nc.rc_mask, 0, 512); 3269 3270 nc.rc_size = wc->size; 3271 3272 if ((err = copyin(wc->image, nc.rc_image, size)) != 0) 3273 return err; 3274 3275 if ((err = copyin(wc->mask, nc.rc_mask, size)) != 0) 3276 return err; 3277 } 3278 3279 if (flags & WSDISPLAY_CURSOR_DOHOT) { 3280 nc.rc_hot = wc->hot; 3281 if (nc.rc_hot.x >= nc.rc_size.x) 3282 nc.rc_hot.x = nc.rc_size.x - 1; 3283 if (nc.rc_hot.y >= nc.rc_size.y) 3284 nc.rc_hot.y = nc.rc_size.y - 1; 3285 } 3286 3287 if (flags & WSDISPLAY_CURSOR_DOPOS) { 3288 nc.rc_pos = wc->pos; 3289 if (nc.rc_pos.x >= dp->rd_virtx) 3290 nc.rc_pos.x = dp->rd_virtx - 1; 3291 #if 0 3292 if (nc.rc_pos.x < 0) 3293 nc.rc_pos.x = 0; 3294 #endif 3295 if (nc.rc_pos.y >= dp->rd_virty) 3296 nc.rc_pos.y = dp->rd_virty - 1; 3297 #if 0 3298 if (nc.rc_pos.y < 0) 3299 nc.rc_pos.y = 0; 3300 #endif 3301 } 3302 if (flags & WSDISPLAY_CURSOR_DOCUR) { 3303 nc.rc_visible = wc->enable; 3304 } 3305 3306 dp->rd_cursor = nc; 3307 radeonfb_cursor_update(dp, wc->which); 3308 3309 return 0; 3310 } 3311 3312 /* 3313 * Change the cursor shape. Call this with the cursor locked to avoid 3314 * flickering/tearing. 3315 */ 3316 static void 3317 radeonfb_cursor_shape(struct radeonfb_display *dp) 3318 { 3319 uint8_t and[512], xor[512]; 3320 int i, j, src, dst, pitch; 3321 const uint8_t *msk = dp->rd_cursor.rc_mask; 3322 const uint8_t *img = dp->rd_cursor.rc_image; 3323 3324 /* 3325 * Radeon cursor data interleaves one line of AND data followed 3326 * by a line of XOR data. (Each line corresponds to a whole hardware 3327 * pitch - i.e. 64 pixels or 8 bytes.) 3328 * 3329 * The cursor is displayed using the following table: 3330 * 3331 * AND XOR Result 3332 * ---------------------- 3333 * 0 0 Cursor color 0 3334 * 0 1 Cursor color 1 3335 * 1 0 Transparent 3336 * 1 1 Complement of background 3337 * 3338 * Our masks are therefore different from what we were passed. 3339 * Passed in, I'm assuming the data represents either color 0 or 1, 3340 * and a mask, so the passed in table looks like: 3341 * 3342 * IMG Mask Result 3343 * ----------------------- 3344 * 0 0 Transparent 3345 * 0 1 Cursor color 0 3346 * 1 0 Transparent 3347 * 1 1 Cursor color 1 3348 * 3349 * IF mask bit == 1, AND = 0, XOR = color. 3350 * IF mask bit == 0, AND = 1, XOR = 0. 3351 * 3352 * hence: AND = ~(mask); XOR = color & ~(mask); 3353 */ 3354 3355 pitch = ((dp->rd_cursor.rc_size.x + 7) / 8); 3356 3357 /* start by assuming all bits are transparent */ 3358 memset(and, 0xff, 512); 3359 memset(xor, 0x00, 512); 3360 3361 src = 0; 3362 dst = 0; 3363 for (i = 0; i < 64; i++) { 3364 for (j = 0; j < 64; j += 8) { 3365 if ((i < dp->rd_cursor.rc_size.y) && 3366 (j < dp->rd_cursor.rc_size.x)) { 3367 3368 /* take care to leave odd bits alone */ 3369 and[dst] &= ~(msk[src]); 3370 xor[dst] = img[src] & msk[src]; 3371 src++; 3372 } 3373 dst++; 3374 } 3375 } 3376 3377 /* copy the image into place */ 3378 for (i = 0; i < 64; i++) { 3379 memcpy((uint8_t *)dp->rd_curptr + (i * 16), 3380 &and[i * 8], 8); 3381 memcpy((uint8_t *)dp->rd_curptr + (i * 16) + 8, 3382 &xor[i * 8], 8); 3383 } 3384 } 3385 3386 static void 3387 radeonfb_cursor_position(struct radeonfb_display *dp) 3388 { 3389 struct radeonfb_softc *sc = dp->rd_softc; 3390 uint32_t offset, hvoff, hvpos; /* registers */ 3391 uint32_t coff; /* cursor offset */ 3392 int i, x, y, xoff, yoff, crtcoff; 3393 3394 /* 3395 * XXX: this also needs to handle pan/scan 3396 */ 3397 for (i = 0; i < dp->rd_ncrtcs; i++) { 3398 3399 struct radeonfb_crtc *rcp = &dp->rd_crtcs[i]; 3400 3401 if (rcp->rc_number) { 3402 offset = RADEON_CUR2_OFFSET; 3403 hvoff = RADEON_CUR2_HORZ_VERT_OFF; 3404 hvpos = RADEON_CUR2_HORZ_VERT_POSN; 3405 crtcoff = RADEON_CRTC2_OFFSET; 3406 } else { 3407 offset = RADEON_CUR_OFFSET; 3408 hvoff = RADEON_CUR_HORZ_VERT_OFF; 3409 hvpos = RADEON_CUR_HORZ_VERT_POSN; 3410 crtcoff = RADEON_CRTC_OFFSET; 3411 } 3412 3413 x = dp->rd_cursor.rc_pos.x; 3414 y = dp->rd_cursor.rc_pos.y; 3415 3416 while (y < rcp->rc_yoffset) { 3417 rcp->rc_yoffset -= RADEON_PANINCREMENT; 3418 } 3419 while (y >= (rcp->rc_yoffset + rcp->rc_videomode.vdisplay)) { 3420 rcp->rc_yoffset += RADEON_PANINCREMENT; 3421 } 3422 while (x < rcp->rc_xoffset) { 3423 rcp->rc_xoffset -= RADEON_PANINCREMENT; 3424 } 3425 while (x >= (rcp->rc_xoffset + rcp->rc_videomode.hdisplay)) { 3426 rcp->rc_xoffset += RADEON_PANINCREMENT; 3427 } 3428 3429 /* adjust for the cursor's hotspot */ 3430 x -= dp->rd_cursor.rc_hot.x; 3431 y -= dp->rd_cursor.rc_hot.y; 3432 xoff = yoff = 0; 3433 3434 if (x >= dp->rd_virtx) 3435 x = dp->rd_virtx - 1; 3436 if (y >= dp->rd_virty) 3437 y = dp->rd_virty - 1; 3438 3439 /* now adjust cursor so it is relative to viewport */ 3440 x -= rcp->rc_xoffset; 3441 y -= rcp->rc_yoffset; 3442 3443 /* 3444 * no need to check for fall off, because we should 3445 * never move off the screen entirely! 3446 */ 3447 coff = 0; 3448 if (x < 0) { 3449 xoff = -x; 3450 x = 0; 3451 } 3452 if (y < 0) { 3453 yoff = -y; 3454 y = 0; 3455 coff = (yoff * 2) * 8; 3456 } 3457 3458 /* pan the display */ 3459 PUT32(sc, crtcoff, (rcp->rc_yoffset * dp->rd_stride) + 3460 rcp->rc_xoffset); 3461 3462 PUT32(sc, offset, (dp->rd_curoff + coff) | RADEON_CUR_LOCK); 3463 PUT32(sc, hvoff, (xoff << 16) | (yoff) | RADEON_CUR_LOCK); 3464 /* NB: this unlocks the cursor */ 3465 PUT32(sc, hvpos, (x << 16) | y); 3466 } 3467 } 3468 3469 static void 3470 radeonfb_cursor_visible(struct radeonfb_display *dp) 3471 { 3472 int i; 3473 uint32_t gencntl, bit; 3474 3475 for (i = 0; i < dp->rd_ncrtcs; i++) { 3476 if (dp->rd_crtcs[i].rc_number) { 3477 gencntl = RADEON_CRTC2_GEN_CNTL; 3478 bit = RADEON_CRTC2_CUR_EN; 3479 } else { 3480 gencntl = RADEON_CRTC_GEN_CNTL; 3481 bit = RADEON_CRTC_CUR_EN; 3482 } 3483 3484 if (dp->rd_cursor.rc_visible) 3485 SET32(dp->rd_softc, gencntl, bit); 3486 else 3487 CLR32(dp->rd_softc, gencntl, bit); 3488 } 3489 } 3490 3491 static void 3492 radeonfb_cursor_cmap(struct radeonfb_display *dp) 3493 { 3494 int i; 3495 uint32_t c0reg, c1reg; 3496 struct radeonfb_softc *sc = dp->rd_softc; 3497 3498 for (i = 0; i < dp->rd_ncrtcs; i++) { 3499 if (dp->rd_crtcs[i].rc_number) { 3500 c0reg = RADEON_CUR2_CLR0; 3501 c1reg = RADEON_CUR2_CLR1; 3502 } else { 3503 c0reg = RADEON_CUR_CLR0; 3504 c1reg = RADEON_CUR_CLR1; 3505 } 3506 3507 PUT32(sc, c0reg, dp->rd_cursor.rc_cmap[0]); 3508 PUT32(sc, c1reg, dp->rd_cursor.rc_cmap[1]); 3509 } 3510 } 3511 3512 static void 3513 radeonfb_cursor_update(struct radeonfb_display *dp, unsigned which) 3514 { 3515 struct radeonfb_softc *sc; 3516 int i; 3517 3518 sc = dp->rd_softc; 3519 for (i = 0; i < dp->rd_ncrtcs; i++) { 3520 if (dp->rd_crtcs[i].rc_number) { 3521 SET32(sc, RADEON_CUR2_OFFSET, RADEON_CUR_LOCK); 3522 } else { 3523 SET32(sc, RADEON_CUR_OFFSET,RADEON_CUR_LOCK); 3524 } 3525 } 3526 3527 if (which & WSDISPLAY_CURSOR_DOCMAP) 3528 radeonfb_cursor_cmap(dp); 3529 3530 if (which & WSDISPLAY_CURSOR_DOSHAPE) 3531 radeonfb_cursor_shape(dp); 3532 3533 if (which & WSDISPLAY_CURSOR_DOCUR) 3534 radeonfb_cursor_visible(dp); 3535 3536 /* this one is unconditional, because it updates other stuff */ 3537 radeonfb_cursor_position(dp); 3538 } 3539 3540 static struct videomode * 3541 radeonfb_best_refresh(struct videomode *m1, struct videomode *m2) 3542 { 3543 int r1, r2; 3544 3545 /* otherwise pick the higher refresh rate */ 3546 r1 = DIVIDE(DIVIDE(m1->dot_clock, m1->htotal), m1->vtotal); 3547 r2 = DIVIDE(DIVIDE(m2->dot_clock, m2->htotal), m2->vtotal); 3548 3549 return (r1 < r2 ? m2 : m1); 3550 } 3551 3552 static const struct videomode * 3553 radeonfb_port_mode(struct radeonfb_softc *sc, struct radeonfb_port *rp, 3554 int x, int y) 3555 { 3556 struct edid_info *ep = &rp->rp_edid; 3557 struct videomode *vmp = NULL; 3558 int i; 3559 3560 if (!rp->rp_edid_valid) { 3561 /* fallback to safe mode */ 3562 return radeonfb_modelookup(sc->sc_defaultmode); 3563 } 3564 3565 /* always choose the preferred mode first! */ 3566 if (ep->edid_preferred_mode) { 3567 3568 /* XXX: add auto-stretching support for native mode */ 3569 3570 /* this may want panning to occur, btw */ 3571 if ((ep->edid_preferred_mode->hdisplay <= x) && 3572 (ep->edid_preferred_mode->vdisplay <= y)) 3573 return ep->edid_preferred_mode; 3574 } 3575 3576 for (i = 0; i < ep->edid_nmodes; i++) { 3577 /* 3578 * We elect to pick a resolution that is too large for 3579 * the monitor than one that is too small. This means 3580 * that we will prefer to pan rather than to try to 3581 * center a smaller display on a larger screen. In 3582 * practice, this shouldn't matter because if a 3583 * monitor can support a larger resolution, it can 3584 * probably also support the smaller. A specific 3585 * exception is fixed format panels, but hopefully 3586 * they are properly dealt with by the "autostretch" 3587 * logic above. 3588 */ 3589 if ((ep->edid_modes[i].hdisplay > x) || 3590 (ep->edid_modes[i].vdisplay > y)) { 3591 continue; 3592 } 3593 3594 /* 3595 * at this point, the display mode is no larger than 3596 * what we've requested. 3597 */ 3598 if (vmp == NULL) 3599 vmp = &ep->edid_modes[i]; 3600 3601 /* eliminate smaller modes */ 3602 if ((vmp->hdisplay >= ep->edid_modes[i].hdisplay) || 3603 (vmp->vdisplay >= ep->edid_modes[i].vdisplay)) 3604 continue; 3605 3606 if ((vmp->hdisplay < ep->edid_modes[i].hdisplay) || 3607 (vmp->vdisplay < ep->edid_modes[i].vdisplay)) { 3608 vmp = &ep->edid_modes[i]; 3609 continue; 3610 } 3611 3612 KASSERT(vmp->hdisplay == ep->edid_modes[i].hdisplay); 3613 KASSERT(vmp->vdisplay == ep->edid_modes[i].vdisplay); 3614 3615 vmp = radeonfb_best_refresh(vmp, &ep->edid_modes[i]); 3616 } 3617 3618 return (vmp ? vmp : radeonfb_modelookup(sc->sc_defaultmode)); 3619 } 3620 3621 static int 3622 radeonfb_hasres(struct videomode *list, int nlist, int x, int y) 3623 { 3624 int i; 3625 3626 for (i = 0; i < nlist; i++) { 3627 if ((x == list[i].hdisplay) && 3628 (y == list[i].vdisplay)) { 3629 return 1; 3630 } 3631 } 3632 return 0; 3633 } 3634 3635 static void 3636 radeonfb_pickres(struct radeonfb_display *dp, uint16_t *x, uint16_t *y, 3637 int pan) 3638 { 3639 struct radeonfb_port *rp; 3640 struct edid_info *ep; 3641 int i, j; 3642 3643 *x = 0; 3644 *y = 0; 3645 3646 if (pan) { 3647 for (i = 0; i < dp->rd_ncrtcs; i++) { 3648 rp = dp->rd_crtcs[i].rc_port; 3649 ep = &rp->rp_edid; 3650 if (!rp->rp_edid_valid) { 3651 /* monitor not present */ 3652 continue; 3653 } 3654 3655 /* 3656 * For now we are ignoring "conflict" that 3657 * could occur when mixing some modes like 3658 * 1280x1024 and 1400x800. It isn't clear 3659 * which is better, so the first one wins. 3660 */ 3661 for (j = 0; j < ep->edid_nmodes; j++) { 3662 /* 3663 * ignore resolutions that are too big for 3664 * the radeon 3665 */ 3666 if (ep->edid_modes[j].hdisplay > 3667 dp->rd_softc->sc_maxx) 3668 continue; 3669 if (ep->edid_modes[j].vdisplay > 3670 dp->rd_softc->sc_maxy) 3671 continue; 3672 3673 /* 3674 * pick largest resolution, the 3675 * smaller monitor will pan 3676 */ 3677 if ((ep->edid_modes[j].hdisplay >= *x) && 3678 (ep->edid_modes[j].vdisplay >= *y)) { 3679 *x = ep->edid_modes[j].hdisplay; 3680 *y = ep->edid_modes[j].vdisplay; 3681 } 3682 } 3683 } 3684 3685 } else { 3686 struct videomode modes[64]; 3687 int nmodes = 0; 3688 int valid = 0; 3689 3690 for (i = 0; i < dp->rd_ncrtcs; i++) { 3691 /* 3692 * pick the largest resolution in common. 3693 */ 3694 rp = dp->rd_crtcs[i].rc_port; 3695 ep = &rp->rp_edid; 3696 3697 if (!rp->rp_edid_valid) 3698 continue; 3699 3700 if (!valid) { 3701 /* 3702 * Pick the preferred mode for this port 3703 * if available. 3704 */ 3705 if (ep->edid_preferred_mode) { 3706 struct videomode *vmp = 3707 ep->edid_preferred_mode; 3708 3709 if ((vmp->hdisplay <= 3710 dp->rd_softc->sc_maxx) && 3711 (vmp->vdisplay <= 3712 dp->rd_softc->sc_maxy)) 3713 modes[nmodes++] = *vmp; 3714 } else { 3715 3716 /* initialize starting list */ 3717 for (j = 0; j < ep->edid_nmodes; j++) { 3718 /* 3719 * ignore resolutions that are 3720 * too big for the radeon 3721 */ 3722 if (ep->edid_modes[j].hdisplay > 3723 dp->rd_softc->sc_maxx) 3724 continue; 3725 if (ep->edid_modes[j].vdisplay > 3726 dp->rd_softc->sc_maxy) 3727 continue; 3728 3729 modes[nmodes] = 3730 ep->edid_modes[j]; 3731 nmodes++; 3732 } 3733 } 3734 valid = 1; 3735 } else { 3736 /* merge into preexisting list */ 3737 for (j = 0; j < nmodes; j++) { 3738 if (!radeonfb_hasres(ep->edid_modes, 3739 ep->edid_nmodes, 3740 modes[j].hdisplay, 3741 modes[j].vdisplay)) { 3742 modes[j] = modes[nmodes]; 3743 j--; 3744 nmodes--; 3745 } 3746 } 3747 } 3748 } 3749 3750 /* now we have to pick from the merged list */ 3751 for (i = 0; i < nmodes; i++) { 3752 if ((modes[i].hdisplay >= *x) && 3753 (modes[i].vdisplay >= *y)) { 3754 *x = modes[i].hdisplay; 3755 *y = modes[i].vdisplay; 3756 } 3757 } 3758 } 3759 3760 if ((*x == 0) || (*y == 0)) { 3761 /* fallback to safe mode */ 3762 *x = 640; 3763 *y = 480; 3764 } 3765 } 3766 3767 /* 3768 * backlight levels are linear on: 3769 * - RV200, RV250, RV280, RV350 3770 * - but NOT on PowerBook4,3 6,3 6,5 3771 * according to Linux' radeonfb 3772 */ 3773 3774 /* Get the current backlight level for the display. */ 3775 3776 static int 3777 radeonfb_get_backlight(struct radeonfb_display *dp) 3778 { 3779 int s; 3780 uint32_t level; 3781 3782 s = spltty(); 3783 3784 level = radeonfb_get32(dp->rd_softc, RADEON_LVDS_GEN_CNTL); 3785 level &= RADEON_LVDS_BL_MOD_LEV_MASK; 3786 level >>= RADEON_LVDS_BL_MOD_LEV_SHIFT; 3787 3788 /* 3789 * On some chips, we should negate the backlight level. 3790 * XXX Find out on which chips. 3791 */ 3792 if (dp->rd_softc->sc_flags & RFB_INV_BLIGHT) 3793 level = RADEONFB_BACKLIGHT_MAX - level; 3794 3795 splx(s); 3796 3797 return level; 3798 } 3799 3800 /* Set the backlight to the given level for the display. */ 3801 static void 3802 radeonfb_switch_backlight(struct radeonfb_display *dp, int on) 3803 { 3804 if (dp->rd_bl_on == on) 3805 return; 3806 dp->rd_bl_on = on; 3807 radeonfb_set_backlight(dp, dp->rd_bl_level); 3808 } 3809 3810 static int 3811 radeonfb_set_backlight(struct radeonfb_display *dp, int level) 3812 { 3813 struct radeonfb_softc *sc; 3814 int rlevel, s; 3815 uint32_t lvds; 3816 3817 s = spltty(); 3818 3819 dp->rd_bl_level = level; 3820 if (dp->rd_bl_on == 0) 3821 level = 0; 3822 3823 if (level < 0) 3824 level = 0; 3825 else if (level >= RADEONFB_BACKLIGHT_MAX) 3826 level = RADEONFB_BACKLIGHT_MAX; 3827 3828 sc = dp->rd_softc; 3829 3830 /* On some chips, we should negate the backlight level. */ 3831 if (dp->rd_softc->sc_flags & RFB_INV_BLIGHT) { 3832 rlevel = RADEONFB_BACKLIGHT_MAX - level; 3833 } else 3834 rlevel = level; 3835 3836 callout_stop(&dp->rd_bl_lvds_co); 3837 radeonfb_engine_idle(sc); 3838 3839 /* 3840 * Turn off the display if the backlight is set to 0, since the 3841 * display is useless without backlight anyway. 3842 */ 3843 if (level == 0) 3844 radeonfb_blank(dp, 1); 3845 else if (radeonfb_get_backlight(dp) == 0) 3846 radeonfb_blank(dp, 0); 3847 3848 lvds = radeonfb_get32(sc, RADEON_LVDS_GEN_CNTL); 3849 lvds &= ~RADEON_LVDS_DISPLAY_DIS; 3850 if (!(lvds & RADEON_LVDS_BLON) || !(lvds & RADEON_LVDS_ON)) { 3851 lvds |= dp->rd_bl_lvds_val & RADEON_LVDS_DIGON; 3852 lvds |= RADEON_LVDS_BLON | RADEON_LVDS_EN; 3853 radeonfb_put32(sc, RADEON_LVDS_GEN_CNTL, lvds); 3854 lvds &= ~RADEON_LVDS_BL_MOD_LEV_MASK; 3855 lvds |= rlevel << RADEON_LVDS_BL_MOD_LEV_SHIFT; 3856 lvds |= RADEON_LVDS_ON; 3857 lvds |= dp->rd_bl_lvds_val & RADEON_LVDS_BL_MOD_EN; 3858 } else { 3859 lvds &= ~RADEON_LVDS_BL_MOD_LEV_MASK; 3860 lvds |= rlevel << RADEON_LVDS_BL_MOD_LEV_SHIFT; 3861 radeonfb_put32(sc, RADEON_LVDS_GEN_CNTL, lvds); 3862 } 3863 3864 dp->rd_bl_lvds_val &= ~RADEON_LVDS_STATE_MASK; 3865 dp->rd_bl_lvds_val |= lvds & RADEON_LVDS_STATE_MASK; 3866 /* XXX What is the correct delay? */ 3867 callout_schedule(&dp->rd_bl_lvds_co, 200 * hz); 3868 3869 splx(s); 3870 3871 return 0; 3872 } 3873 3874 /* 3875 * Callout function for delayed operations on the LVDS_GEN_CNTL register. 3876 * Set the delayed bits in the register, and clear the stored delayed 3877 * value. 3878 */ 3879 3880 static void radeonfb_lvds_callout(void *arg) 3881 { 3882 struct radeonfb_display *dp = arg; 3883 int s; 3884 3885 s = splhigh(); 3886 3887 radeonfb_mask32(dp->rd_softc, RADEON_LVDS_GEN_CNTL, ~0, 3888 dp->rd_bl_lvds_val); 3889 dp->rd_bl_lvds_val = 0; 3890 3891 splx(s); 3892 } 3893 3894 static void 3895 radeonfb_brightness_up(device_t dev) 3896 { 3897 struct radeonfb_softc *sc = device_private(dev); 3898 struct radeonfb_display *dp = &sc->sc_displays[0]; 3899 int level; 3900 3901 /* we assume the main display is the first one - need a better way */ 3902 if (sc->sc_ndisplays < 1) return; 3903 /* make sure pushing the hotkeys always has an effect */ 3904 dp->rd_bl_on = 1; 3905 level = dp->rd_bl_level; 3906 level = min(RADEONFB_BACKLIGHT_MAX, level + 5); 3907 radeonfb_set_backlight(dp, level); 3908 } 3909 3910 static void 3911 radeonfb_brightness_down(device_t dev) 3912 { 3913 struct radeonfb_softc *sc = device_private(dev); 3914 struct radeonfb_display *dp = &sc->sc_displays[0]; 3915 int level; 3916 3917 /* we assume the main display is the first one - need a better way */ 3918 if (sc->sc_ndisplays < 1) return; 3919 /* make sure pushing the hotkeys always has an effect */ 3920 dp->rd_bl_on = 1; 3921 level = dp->rd_bl_level; 3922 level = max(0, level - 5); 3923 radeonfb_set_backlight(dp, level); 3924 } 3925
Indexes created Wed Sep 24 05:09:52 GMT 2025